1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64InstrInfo.h"
15 #include "AArch64Subtarget.h"
16 #include "MCTargetDesc/AArch64AddressingModes.h"
17 #include "AArch64MachineCombinerPattern.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
29 #define GET_INSTRINFO_CTOR_DTOR
30 #include "AArch64GenInstrInfo.inc"
32 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
33 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
34 RI(this, &STI), Subtarget(STI) {}
36 /// GetInstSize - Return the number of bytes of code the specified
37 /// instruction may be. This returns the maximum number of bytes.
38 unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
39 const MachineBasicBlock &MBB = *MI->getParent();
40 const MachineFunction *MF = MBB.getParent();
41 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
43 if (MI->getOpcode() == AArch64::INLINEASM)
44 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
46 const MCInstrDesc &Desc = MI->getDesc();
47 switch (Desc.getOpcode()) {
49 // Anything not explicitly designated otherwise is a nomal 4-byte insn.
51 case TargetOpcode::DBG_VALUE:
52 case TargetOpcode::EH_LABEL:
53 case TargetOpcode::IMPLICIT_DEF:
54 case TargetOpcode::KILL:
58 llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");
61 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
62 SmallVectorImpl<MachineOperand> &Cond) {
63 // Block ends with fall-through condbranch.
64 switch (LastInst->getOpcode()) {
66 llvm_unreachable("Unknown branch instruction?");
68 Target = LastInst->getOperand(1).getMBB();
69 Cond.push_back(LastInst->getOperand(0));
75 Target = LastInst->getOperand(1).getMBB();
76 Cond.push_back(MachineOperand::CreateImm(-1));
77 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
78 Cond.push_back(LastInst->getOperand(0));
84 Target = LastInst->getOperand(2).getMBB();
85 Cond.push_back(MachineOperand::CreateImm(-1));
86 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
87 Cond.push_back(LastInst->getOperand(0));
88 Cond.push_back(LastInst->getOperand(1));
93 bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
94 MachineBasicBlock *&TBB,
95 MachineBasicBlock *&FBB,
96 SmallVectorImpl<MachineOperand> &Cond,
97 bool AllowModify) const {
98 // If the block has no terminators, it just falls into the block after it.
99 MachineBasicBlock::iterator I = MBB.end();
100 if (I == MBB.begin())
103 while (I->isDebugValue()) {
104 if (I == MBB.begin())
108 if (!isUnpredicatedTerminator(I))
111 // Get the last instruction in the block.
112 MachineInstr *LastInst = I;
114 // If there is only one terminator instruction, process it.
115 unsigned LastOpc = LastInst->getOpcode();
116 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
117 if (isUncondBranchOpcode(LastOpc)) {
118 TBB = LastInst->getOperand(0).getMBB();
121 if (isCondBranchOpcode(LastOpc)) {
122 // Block ends with fall-through condbranch.
123 parseCondBranch(LastInst, TBB, Cond);
126 return true; // Can't handle indirect branch.
129 // Get the instruction before it if it is a terminator.
130 MachineInstr *SecondLastInst = I;
131 unsigned SecondLastOpc = SecondLastInst->getOpcode();
133 // If AllowModify is true and the block ends with two or more unconditional
134 // branches, delete all but the first unconditional branch.
135 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
136 while (isUncondBranchOpcode(SecondLastOpc)) {
137 LastInst->eraseFromParent();
138 LastInst = SecondLastInst;
139 LastOpc = LastInst->getOpcode();
140 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
141 // Return now the only terminator is an unconditional branch.
142 TBB = LastInst->getOperand(0).getMBB();
146 SecondLastOpc = SecondLastInst->getOpcode();
151 // If there are three terminators, we don't know what sort of block this is.
152 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
155 // If the block ends with a B and a Bcc, handle it.
156 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
157 parseCondBranch(SecondLastInst, TBB, Cond);
158 FBB = LastInst->getOperand(0).getMBB();
162 // If the block ends with two unconditional branches, handle it. The second
163 // one is not executed, so remove it.
164 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
165 TBB = SecondLastInst->getOperand(0).getMBB();
168 I->eraseFromParent();
172 // ...likewise if it ends with an indirect branch followed by an unconditional
174 if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
177 I->eraseFromParent();
181 // Otherwise, can't handle this.
185 bool AArch64InstrInfo::ReverseBranchCondition(
186 SmallVectorImpl<MachineOperand> &Cond) const {
187 if (Cond[0].getImm() != -1) {
189 AArch64CC::CondCode CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
190 Cond[0].setImm(AArch64CC::getInvertedCondCode(CC));
192 // Folded compare-and-branch
193 switch (Cond[1].getImm()) {
195 llvm_unreachable("Unknown conditional branch!");
197 Cond[1].setImm(AArch64::CBNZW);
200 Cond[1].setImm(AArch64::CBZW);
203 Cond[1].setImm(AArch64::CBNZX);
206 Cond[1].setImm(AArch64::CBZX);
209 Cond[1].setImm(AArch64::TBNZW);
212 Cond[1].setImm(AArch64::TBZW);
215 Cond[1].setImm(AArch64::TBNZX);
218 Cond[1].setImm(AArch64::TBZX);
226 unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
227 MachineBasicBlock::iterator I = MBB.end();
228 if (I == MBB.begin())
231 while (I->isDebugValue()) {
232 if (I == MBB.begin())
236 if (!isUncondBranchOpcode(I->getOpcode()) &&
237 !isCondBranchOpcode(I->getOpcode()))
240 // Remove the branch.
241 I->eraseFromParent();
245 if (I == MBB.begin())
248 if (!isCondBranchOpcode(I->getOpcode()))
251 // Remove the branch.
252 I->eraseFromParent();
256 void AArch64InstrInfo::instantiateCondBranch(
257 MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB,
258 const SmallVectorImpl<MachineOperand> &Cond) const {
259 if (Cond[0].getImm() != -1) {
261 BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
263 // Folded compare-and-branch
264 const MachineInstrBuilder MIB =
265 BuildMI(&MBB, DL, get(Cond[1].getImm())).addReg(Cond[2].getReg());
267 MIB.addImm(Cond[3].getImm());
272 unsigned AArch64InstrInfo::InsertBranch(
273 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
274 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
275 // Shouldn't be a fall through.
276 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
279 if (Cond.empty()) // Unconditional branch?
280 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB);
282 instantiateCondBranch(MBB, DL, TBB, Cond);
286 // Two-way conditional branch.
287 instantiateCondBranch(MBB, DL, TBB, Cond);
288 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB);
292 // Find the original register that VReg is copied from.
293 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
294 while (TargetRegisterInfo::isVirtualRegister(VReg)) {
295 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
296 if (!DefMI->isFullCopy())
298 VReg = DefMI->getOperand(1).getReg();
303 // Determine if VReg is defined by an instruction that can be folded into a
304 // csel instruction. If so, return the folded opcode, and the replacement
306 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
307 unsigned *NewVReg = nullptr) {
308 VReg = removeCopies(MRI, VReg);
309 if (!TargetRegisterInfo::isVirtualRegister(VReg))
312 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
313 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
315 unsigned SrcOpNum = 0;
316 switch (DefMI->getOpcode()) {
317 case AArch64::ADDSXri:
318 case AArch64::ADDSWri:
319 // if NZCV is used, do not fold.
320 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
322 // fall-through to ADDXri and ADDWri.
323 case AArch64::ADDXri:
324 case AArch64::ADDWri:
325 // add x, 1 -> csinc.
326 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
327 DefMI->getOperand(3).getImm() != 0)
330 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr;
333 case AArch64::ORNXrr:
334 case AArch64::ORNWrr: {
335 // not x -> csinv, represented as orn dst, xzr, src.
336 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
337 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
340 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr;
344 case AArch64::SUBSXrr:
345 case AArch64::SUBSWrr:
346 // if NZCV is used, do not fold.
347 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
349 // fall-through to SUBXrr and SUBWrr.
350 case AArch64::SUBXrr:
351 case AArch64::SUBWrr: {
352 // neg x -> csneg, represented as sub dst, xzr, src.
353 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
354 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
357 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr;
363 assert(Opc && SrcOpNum && "Missing parameters");
366 *NewVReg = DefMI->getOperand(SrcOpNum).getReg();
370 bool AArch64InstrInfo::canInsertSelect(
371 const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond,
372 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles,
373 int &FalseCycles) const {
374 // Check register classes.
375 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
376 const TargetRegisterClass *RC =
377 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
381 // Expanding cbz/tbz requires an extra cycle of latency on the condition.
382 unsigned ExtraCondLat = Cond.size() != 1;
384 // GPRs are handled by csel.
385 // FIXME: Fold in x+1, -x, and ~x when applicable.
386 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
387 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
388 // Single-cycle csel, csinc, csinv, and csneg.
389 CondCycles = 1 + ExtraCondLat;
390 TrueCycles = FalseCycles = 1;
391 if (canFoldIntoCSel(MRI, TrueReg))
393 else if (canFoldIntoCSel(MRI, FalseReg))
398 // Scalar floating point is handled by fcsel.
399 // FIXME: Form fabs, fmin, and fmax when applicable.
400 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
401 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
402 CondCycles = 5 + ExtraCondLat;
403 TrueCycles = FalseCycles = 2;
411 void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
412 MachineBasicBlock::iterator I, DebugLoc DL,
414 const SmallVectorImpl<MachineOperand> &Cond,
415 unsigned TrueReg, unsigned FalseReg) const {
416 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
418 // Parse the condition code, see parseCondBranch() above.
419 AArch64CC::CondCode CC;
420 switch (Cond.size()) {
422 llvm_unreachable("Unknown condition opcode in Cond");
424 CC = AArch64CC::CondCode(Cond[0].getImm());
426 case 3: { // cbz/cbnz
427 // We must insert a compare against 0.
429 switch (Cond[1].getImm()) {
431 llvm_unreachable("Unknown branch opcode in Cond");
449 unsigned SrcReg = Cond[2].getReg();
451 // cmp reg, #0 is actually subs xzr, reg, #0.
452 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
453 BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR)
458 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
459 BuildMI(MBB, I, DL, get(AArch64::SUBSWri), AArch64::WZR)
466 case 4: { // tbz/tbnz
467 // We must insert a tst instruction.
468 switch (Cond[1].getImm()) {
470 llvm_unreachable("Unknown branch opcode in Cond");
480 // cmp reg, #foo is actually ands xzr, reg, #1<<foo.
481 if (Cond[1].getImm() == AArch64::TBZW || Cond[1].getImm() == AArch64::TBNZW)
482 BuildMI(MBB, I, DL, get(AArch64::ANDSWri), AArch64::WZR)
483 .addReg(Cond[2].getReg())
485 AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 32));
487 BuildMI(MBB, I, DL, get(AArch64::ANDSXri), AArch64::XZR)
488 .addReg(Cond[2].getReg())
490 AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 64));
496 const TargetRegisterClass *RC = nullptr;
497 bool TryFold = false;
498 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
499 RC = &AArch64::GPR64RegClass;
500 Opc = AArch64::CSELXr;
502 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
503 RC = &AArch64::GPR32RegClass;
504 Opc = AArch64::CSELWr;
506 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) {
507 RC = &AArch64::FPR64RegClass;
508 Opc = AArch64::FCSELDrrr;
509 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) {
510 RC = &AArch64::FPR32RegClass;
511 Opc = AArch64::FCSELSrrr;
513 assert(RC && "Unsupported regclass");
515 // Try folding simple instructions into the csel.
517 unsigned NewVReg = 0;
518 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg);
520 // The folded opcodes csinc, csinc and csneg apply the operation to
521 // FalseReg, so we need to invert the condition.
522 CC = AArch64CC::getInvertedCondCode(CC);
525 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg);
527 // Fold the operation. Leave any dead instructions for DCE to clean up.
531 // The extends the live range of NewVReg.
532 MRI.clearKillFlags(NewVReg);
536 // Pull all virtual register into the appropriate class.
537 MRI.constrainRegClass(TrueReg, RC);
538 MRI.constrainRegClass(FalseReg, RC);
541 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm(
545 // FIXME: this implementation should be micro-architecture dependent, so a
546 // micro-architecture target hook should be introduced here in future.
547 bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const {
548 if (!Subtarget.isCortexA57() && !Subtarget.isCortexA53())
549 return MI->isAsCheapAsAMove();
551 switch (MI->getOpcode()) {
555 // add/sub on register without shift
556 case AArch64::ADDWri:
557 case AArch64::ADDXri:
558 case AArch64::SUBWri:
559 case AArch64::SUBXri:
560 return (MI->getOperand(3).getImm() == 0);
562 // logical ops on immediate
563 case AArch64::ANDWri:
564 case AArch64::ANDXri:
565 case AArch64::EORWri:
566 case AArch64::EORXri:
567 case AArch64::ORRWri:
568 case AArch64::ORRXri:
571 // logical ops on register without shift
572 case AArch64::ANDWrr:
573 case AArch64::ANDXrr:
574 case AArch64::BICWrr:
575 case AArch64::BICXrr:
576 case AArch64::EONWrr:
577 case AArch64::EONXrr:
578 case AArch64::EORWrr:
579 case AArch64::EORXrr:
580 case AArch64::ORNWrr:
581 case AArch64::ORNXrr:
582 case AArch64::ORRWrr:
583 case AArch64::ORRXrr:
587 llvm_unreachable("Unknown opcode to check as cheap as a move!");
590 bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
591 unsigned &SrcReg, unsigned &DstReg,
592 unsigned &SubIdx) const {
593 switch (MI.getOpcode()) {
596 case AArch64::SBFMXri: // aka sxtw
597 case AArch64::UBFMXri: // aka uxtw
598 // Check for the 32 -> 64 bit extension case, these instructions can do
600 if (MI.getOperand(2).getImm() != 0 || MI.getOperand(3).getImm() != 31)
602 // This is a signed or unsigned 32 -> 64 bit extension.
603 SrcReg = MI.getOperand(1).getReg();
604 DstReg = MI.getOperand(0).getReg();
605 SubIdx = AArch64::sub_32;
611 AArch64InstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
613 AliasAnalysis *AA) const {
614 const TargetRegisterInfo *TRI = &getRegisterInfo();
615 unsigned BaseRegA = 0, BaseRegB = 0;
616 int OffsetA = 0, OffsetB = 0;
617 int WidthA = 0, WidthB = 0;
619 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
620 "MIa must be a store or a load");
621 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
622 "MIb must be a store or a load");
624 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
625 MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
628 // Retrieve the base register, offset from the base register and width. Width
629 // is the size of memory that is being loaded/stored (e.g. 1, 2, 4, 8). If
630 // base registers are identical, and the offset of a lower memory access +
631 // the width doesn't overlap the offset of a higher memory access,
632 // then the memory accesses are different.
633 if (getLdStBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) &&
634 getLdStBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) {
635 if (BaseRegA == BaseRegB) {
636 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
637 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
638 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
639 if (LowOffset + LowWidth <= HighOffset)
646 /// analyzeCompare - For a comparison instruction, return the source registers
647 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
648 /// Return true if the comparison instruction can be analyzed.
649 bool AArch64InstrInfo::analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
650 unsigned &SrcReg2, int &CmpMask,
651 int &CmpValue) const {
652 switch (MI->getOpcode()) {
655 case AArch64::SUBSWrr:
656 case AArch64::SUBSWrs:
657 case AArch64::SUBSWrx:
658 case AArch64::SUBSXrr:
659 case AArch64::SUBSXrs:
660 case AArch64::SUBSXrx:
661 case AArch64::ADDSWrr:
662 case AArch64::ADDSWrs:
663 case AArch64::ADDSWrx:
664 case AArch64::ADDSXrr:
665 case AArch64::ADDSXrs:
666 case AArch64::ADDSXrx:
667 // Replace SUBSWrr with SUBWrr if NZCV is not used.
668 SrcReg = MI->getOperand(1).getReg();
669 SrcReg2 = MI->getOperand(2).getReg();
673 case AArch64::SUBSWri:
674 case AArch64::ADDSWri:
675 case AArch64::SUBSXri:
676 case AArch64::ADDSXri:
677 SrcReg = MI->getOperand(1).getReg();
680 // FIXME: In order to convert CmpValue to 0 or 1
681 CmpValue = (MI->getOperand(2).getImm() != 0);
683 case AArch64::ANDSWri:
684 case AArch64::ANDSXri:
685 // ANDS does not use the same encoding scheme as the others xxxS
687 SrcReg = MI->getOperand(1).getReg();
690 // FIXME:The return val type of decodeLogicalImmediate is uint64_t,
691 // while the type of CmpValue is int. When converting uint64_t to int,
692 // the high 32 bits of uint64_t will be lost.
693 // In fact it causes a bug in spec2006-483.xalancbmk
694 // CmpValue is only used to compare with zero in OptimizeCompareInstr
695 CmpValue = (AArch64_AM::decodeLogicalImmediate(
696 MI->getOperand(2).getImm(),
697 MI->getOpcode() == AArch64::ANDSWri ? 32 : 64) != 0);
704 static bool UpdateOperandRegClass(MachineInstr *Instr) {
705 MachineBasicBlock *MBB = Instr->getParent();
706 assert(MBB && "Can't get MachineBasicBlock here");
707 MachineFunction *MF = MBB->getParent();
708 assert(MF && "Can't get MachineFunction here");
709 const TargetMachine *TM = &MF->getTarget();
710 const TargetInstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
711 const TargetRegisterInfo *TRI = TM->getSubtargetImpl()->getRegisterInfo();
712 MachineRegisterInfo *MRI = &MF->getRegInfo();
714 for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx;
716 MachineOperand &MO = Instr->getOperand(OpIdx);
717 const TargetRegisterClass *OpRegCstraints =
718 Instr->getRegClassConstraint(OpIdx, TII, TRI);
720 // If there's no constraint, there's nothing to do.
723 // If the operand is a frame index, there's nothing to do here.
724 // A frame index operand will resolve correctly during PEI.
729 "Operand has register constraints without being a register!");
731 unsigned Reg = MO.getReg();
732 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
733 if (!OpRegCstraints->contains(Reg))
735 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
736 !MRI->constrainRegClass(Reg, OpRegCstraints))
743 /// convertFlagSettingOpcode - return opcode that does not
744 /// set flags when possible. The caller is responsible to do
745 /// the actual substitution and legality checking.
746 static unsigned convertFlagSettingOpcode(MachineInstr *MI) {
748 switch (MI->getOpcode()) {
751 case AArch64::ADDSWrr: NewOpc = AArch64::ADDWrr; break;
752 case AArch64::ADDSWri: NewOpc = AArch64::ADDWri; break;
753 case AArch64::ADDSWrs: NewOpc = AArch64::ADDWrs; break;
754 case AArch64::ADDSWrx: NewOpc = AArch64::ADDWrx; break;
755 case AArch64::ADDSXrr: NewOpc = AArch64::ADDXrr; break;
756 case AArch64::ADDSXri: NewOpc = AArch64::ADDXri; break;
757 case AArch64::ADDSXrs: NewOpc = AArch64::ADDXrs; break;
758 case AArch64::ADDSXrx: NewOpc = AArch64::ADDXrx; break;
759 case AArch64::SUBSWrr: NewOpc = AArch64::SUBWrr; break;
760 case AArch64::SUBSWri: NewOpc = AArch64::SUBWri; break;
761 case AArch64::SUBSWrs: NewOpc = AArch64::SUBWrs; break;
762 case AArch64::SUBSWrx: NewOpc = AArch64::SUBWrx; break;
763 case AArch64::SUBSXrr: NewOpc = AArch64::SUBXrr; break;
764 case AArch64::SUBSXri: NewOpc = AArch64::SUBXri; break;
765 case AArch64::SUBSXrs: NewOpc = AArch64::SUBXrs; break;
766 case AArch64::SUBSXrx: NewOpc = AArch64::SUBXrx; break;
771 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
772 /// comparison into one that sets the zero bit in the flags register.
773 bool AArch64InstrInfo::optimizeCompareInstr(
774 MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
775 int CmpValue, const MachineRegisterInfo *MRI) const {
777 // Replace SUBSWrr with SUBWrr if NZCV is not used.
778 int Cmp_NZCV = CmpInstr->findRegisterDefOperandIdx(AArch64::NZCV, true);
779 if (Cmp_NZCV != -1) {
780 unsigned Opc = CmpInstr->getOpcode();
781 unsigned NewOpc = convertFlagSettingOpcode(CmpInstr);
784 const MCInstrDesc &MCID = get(NewOpc);
785 CmpInstr->setDesc(MCID);
786 CmpInstr->RemoveOperand(Cmp_NZCV);
787 bool succeeded = UpdateOperandRegClass(CmpInstr);
789 assert(succeeded && "Some operands reg class are incompatible!");
793 // Continue only if we have a "ri" where immediate is zero.
794 // FIXME:CmpValue has already been converted to 0 or 1 in analyzeCompare
796 assert((CmpValue == 0 || CmpValue == 1) && "CmpValue must be 0 or 1!");
797 if (CmpValue != 0 || SrcReg2 != 0)
800 // CmpInstr is a Compare instruction if destination register is not used.
801 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
804 // Get the unique definition of SrcReg.
805 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
809 // We iterate backward, starting from the instruction before CmpInstr and
810 // stop when reaching the definition of the source register or done with the
811 // basic block, to check whether NZCV is used or modified in between.
812 MachineBasicBlock::iterator I = CmpInstr, E = MI,
813 B = CmpInstr->getParent()->begin();
815 // Early exit if CmpInstr is at the beginning of the BB.
819 // Check whether the definition of SrcReg is in the same basic block as
820 // Compare. If not, we can't optimize away the Compare.
821 if (MI->getParent() != CmpInstr->getParent())
824 // Check that NZCV isn't set between the comparison instruction and the one we
826 const TargetRegisterInfo *TRI = &getRegisterInfo();
827 for (--I; I != E; --I) {
828 const MachineInstr &Instr = *I;
830 if (Instr.modifiesRegister(AArch64::NZCV, TRI) ||
831 Instr.readsRegister(AArch64::NZCV, TRI))
832 // This instruction modifies or uses NZCV after the one we want to
833 // change. We can't do this transformation.
836 // The 'and' is below the comparison instruction.
840 unsigned NewOpc = MI->getOpcode();
841 switch (MI->getOpcode()) {
844 case AArch64::ADDSWrr:
845 case AArch64::ADDSWri:
846 case AArch64::ADDSXrr:
847 case AArch64::ADDSXri:
848 case AArch64::SUBSWrr:
849 case AArch64::SUBSWri:
850 case AArch64::SUBSXrr:
851 case AArch64::SUBSXri:
853 case AArch64::ADDWrr: NewOpc = AArch64::ADDSWrr; break;
854 case AArch64::ADDWri: NewOpc = AArch64::ADDSWri; break;
855 case AArch64::ADDXrr: NewOpc = AArch64::ADDSXrr; break;
856 case AArch64::ADDXri: NewOpc = AArch64::ADDSXri; break;
857 case AArch64::ADCWr: NewOpc = AArch64::ADCSWr; break;
858 case AArch64::ADCXr: NewOpc = AArch64::ADCSXr; break;
859 case AArch64::SUBWrr: NewOpc = AArch64::SUBSWrr; break;
860 case AArch64::SUBWri: NewOpc = AArch64::SUBSWri; break;
861 case AArch64::SUBXrr: NewOpc = AArch64::SUBSXrr; break;
862 case AArch64::SUBXri: NewOpc = AArch64::SUBSXri; break;
863 case AArch64::SBCWr: NewOpc = AArch64::SBCSWr; break;
864 case AArch64::SBCXr: NewOpc = AArch64::SBCSXr; break;
865 case AArch64::ANDWri: NewOpc = AArch64::ANDSWri; break;
866 case AArch64::ANDXri: NewOpc = AArch64::ANDSXri; break;
869 // Scan forward for the use of NZCV.
870 // When checking against MI: if it's a conditional code requires
871 // checking of V bit, then this is not safe to do.
872 // It is safe to remove CmpInstr if NZCV is redefined or killed.
873 // If we are done with the basic block, we need to check whether NZCV is
876 for (MachineBasicBlock::iterator I = CmpInstr,
877 E = CmpInstr->getParent()->end();
878 !IsSafe && ++I != E;) {
879 const MachineInstr &Instr = *I;
880 for (unsigned IO = 0, EO = Instr.getNumOperands(); !IsSafe && IO != EO;
882 const MachineOperand &MO = Instr.getOperand(IO);
883 if (MO.isRegMask() && MO.clobbersPhysReg(AArch64::NZCV)) {
887 if (!MO.isReg() || MO.getReg() != AArch64::NZCV)
894 // Decode the condition code.
895 unsigned Opc = Instr.getOpcode();
896 AArch64CC::CondCode CC;
901 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 2).getImm();
903 case AArch64::CSINVWr:
904 case AArch64::CSINVXr:
905 case AArch64::CSINCWr:
906 case AArch64::CSINCXr:
907 case AArch64::CSELWr:
908 case AArch64::CSELXr:
909 case AArch64::CSNEGWr:
910 case AArch64::CSNEGXr:
911 case AArch64::FCSELSrrr:
912 case AArch64::FCSELDrrr:
913 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 1).getImm();
917 // It is not safe to remove Compare instruction if Overflow(V) is used.
920 // NZCV can be used multiple times, we should continue.
933 // If NZCV is not killed nor re-defined, we should check whether it is
934 // live-out. If it is live-out, do not optimize.
936 MachineBasicBlock *ParentBlock = CmpInstr->getParent();
937 for (auto *MBB : ParentBlock->successors())
938 if (MBB->isLiveIn(AArch64::NZCV))
942 // Update the instruction to set NZCV.
943 MI->setDesc(get(NewOpc));
944 CmpInstr->eraseFromParent();
945 bool succeeded = UpdateOperandRegClass(MI);
947 assert(succeeded && "Some operands reg class are incompatible!");
948 MI->addRegisterDefined(AArch64::NZCV, TRI);
953 AArch64InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
954 if (MI->getOpcode() != TargetOpcode::LOAD_STACK_GUARD)
957 MachineBasicBlock &MBB = *MI->getParent();
958 DebugLoc DL = MI->getDebugLoc();
959 unsigned Reg = MI->getOperand(0).getReg();
960 const GlobalValue *GV =
961 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
962 const TargetMachine &TM = MBB.getParent()->getTarget();
963 unsigned char OpFlags = Subtarget.ClassifyGlobalReference(GV, TM);
964 const unsigned char MO_NC = AArch64II::MO_NC;
966 if ((OpFlags & AArch64II::MO_GOT) != 0) {
967 BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg)
968 .addGlobalAddress(GV, 0, AArch64II::MO_GOT);
969 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
970 .addReg(Reg, RegState::Kill).addImm(0)
971 .addMemOperand(*MI->memoperands_begin());
972 } else if (TM.getCodeModel() == CodeModel::Large) {
973 BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
974 .addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48);
975 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
976 .addReg(Reg, RegState::Kill)
977 .addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC).addImm(32);
978 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
979 .addReg(Reg, RegState::Kill)
980 .addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC).addImm(16);
981 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
982 .addReg(Reg, RegState::Kill)
983 .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0);
984 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
985 .addReg(Reg, RegState::Kill).addImm(0)
986 .addMemOperand(*MI->memoperands_begin());
988 BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg)
989 .addGlobalAddress(GV, 0, OpFlags | AArch64II::MO_PAGE);
990 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | MO_NC;
991 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
992 .addReg(Reg, RegState::Kill)
993 .addGlobalAddress(GV, 0, LoFlags)
994 .addMemOperand(*MI->memoperands_begin());
1002 /// Return true if this is this instruction has a non-zero immediate
1003 bool AArch64InstrInfo::hasShiftedReg(const MachineInstr *MI) const {
1004 switch (MI->getOpcode()) {
1007 case AArch64::ADDSWrs:
1008 case AArch64::ADDSXrs:
1009 case AArch64::ADDWrs:
1010 case AArch64::ADDXrs:
1011 case AArch64::ANDSWrs:
1012 case AArch64::ANDSXrs:
1013 case AArch64::ANDWrs:
1014 case AArch64::ANDXrs:
1015 case AArch64::BICSWrs:
1016 case AArch64::BICSXrs:
1017 case AArch64::BICWrs:
1018 case AArch64::BICXrs:
1019 case AArch64::CRC32Brr:
1020 case AArch64::CRC32CBrr:
1021 case AArch64::CRC32CHrr:
1022 case AArch64::CRC32CWrr:
1023 case AArch64::CRC32CXrr:
1024 case AArch64::CRC32Hrr:
1025 case AArch64::CRC32Wrr:
1026 case AArch64::CRC32Xrr:
1027 case AArch64::EONWrs:
1028 case AArch64::EONXrs:
1029 case AArch64::EORWrs:
1030 case AArch64::EORXrs:
1031 case AArch64::ORNWrs:
1032 case AArch64::ORNXrs:
1033 case AArch64::ORRWrs:
1034 case AArch64::ORRXrs:
1035 case AArch64::SUBSWrs:
1036 case AArch64::SUBSXrs:
1037 case AArch64::SUBWrs:
1038 case AArch64::SUBXrs:
1039 if (MI->getOperand(3).isImm()) {
1040 unsigned val = MI->getOperand(3).getImm();
1048 /// Return true if this is this instruction has a non-zero immediate
1049 bool AArch64InstrInfo::hasExtendedReg(const MachineInstr *MI) const {
1050 switch (MI->getOpcode()) {
1053 case AArch64::ADDSWrx:
1054 case AArch64::ADDSXrx:
1055 case AArch64::ADDSXrx64:
1056 case AArch64::ADDWrx:
1057 case AArch64::ADDXrx:
1058 case AArch64::ADDXrx64:
1059 case AArch64::SUBSWrx:
1060 case AArch64::SUBSXrx:
1061 case AArch64::SUBSXrx64:
1062 case AArch64::SUBWrx:
1063 case AArch64::SUBXrx:
1064 case AArch64::SUBXrx64:
1065 if (MI->getOperand(3).isImm()) {
1066 unsigned val = MI->getOperand(3).getImm();
1075 // Return true if this instruction simply sets its single destination register
1076 // to zero. This is equivalent to a register rename of the zero-register.
1077 bool AArch64InstrInfo::isGPRZero(const MachineInstr *MI) const {
1078 switch (MI->getOpcode()) {
1081 case AArch64::MOVZWi:
1082 case AArch64::MOVZXi: // movz Rd, #0 (LSL #0)
1083 if (MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) {
1084 assert(MI->getDesc().getNumOperands() == 3 &&
1085 MI->getOperand(2).getImm() == 0 && "invalid MOVZi operands");
1089 case AArch64::ANDWri: // and Rd, Rzr, #imm
1090 return MI->getOperand(1).getReg() == AArch64::WZR;
1091 case AArch64::ANDXri:
1092 return MI->getOperand(1).getReg() == AArch64::XZR;
1093 case TargetOpcode::COPY:
1094 return MI->getOperand(1).getReg() == AArch64::WZR;
1099 // Return true if this instruction simply renames a general register without
1101 bool AArch64InstrInfo::isGPRCopy(const MachineInstr *MI) const {
1102 switch (MI->getOpcode()) {
1105 case TargetOpcode::COPY: {
1106 // GPR32 copies will by lowered to ORRXrs
1107 unsigned DstReg = MI->getOperand(0).getReg();
1108 return (AArch64::GPR32RegClass.contains(DstReg) ||
1109 AArch64::GPR64RegClass.contains(DstReg));
1111 case AArch64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0)
1112 if (MI->getOperand(1).getReg() == AArch64::XZR) {
1113 assert(MI->getDesc().getNumOperands() == 4 &&
1114 MI->getOperand(3).getImm() == 0 && "invalid ORRrs operands");
1118 case AArch64::ADDXri: // add Xd, Xn, #0 (LSL #0)
1119 if (MI->getOperand(2).getImm() == 0) {
1120 assert(MI->getDesc().getNumOperands() == 4 &&
1121 MI->getOperand(3).getImm() == 0 && "invalid ADDXri operands");
1129 // Return true if this instruction simply renames a general register without
1131 bool AArch64InstrInfo::isFPRCopy(const MachineInstr *MI) const {
1132 switch (MI->getOpcode()) {
1135 case TargetOpcode::COPY: {
1136 // FPR64 copies will by lowered to ORR.16b
1137 unsigned DstReg = MI->getOperand(0).getReg();
1138 return (AArch64::FPR64RegClass.contains(DstReg) ||
1139 AArch64::FPR128RegClass.contains(DstReg));
1141 case AArch64::ORRv16i8:
1142 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
1143 assert(MI->getDesc().getNumOperands() == 3 && MI->getOperand(0).isReg() &&
1144 "invalid ORRv16i8 operands");
1152 unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1153 int &FrameIndex) const {
1154 switch (MI->getOpcode()) {
1157 case AArch64::LDRWui:
1158 case AArch64::LDRXui:
1159 case AArch64::LDRBui:
1160 case AArch64::LDRHui:
1161 case AArch64::LDRSui:
1162 case AArch64::LDRDui:
1163 case AArch64::LDRQui:
1164 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
1165 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
1166 FrameIndex = MI->getOperand(1).getIndex();
1167 return MI->getOperand(0).getReg();
1175 unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1176 int &FrameIndex) const {
1177 switch (MI->getOpcode()) {
1180 case AArch64::STRWui:
1181 case AArch64::STRXui:
1182 case AArch64::STRBui:
1183 case AArch64::STRHui:
1184 case AArch64::STRSui:
1185 case AArch64::STRDui:
1186 case AArch64::STRQui:
1187 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
1188 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
1189 FrameIndex = MI->getOperand(1).getIndex();
1190 return MI->getOperand(0).getReg();
1197 /// Return true if this is load/store scales or extends its register offset.
1198 /// This refers to scaling a dynamic index as opposed to scaled immediates.
1199 /// MI should be a memory op that allows scaled addressing.
1200 bool AArch64InstrInfo::isScaledAddr(const MachineInstr *MI) const {
1201 switch (MI->getOpcode()) {
1204 case AArch64::LDRBBroW:
1205 case AArch64::LDRBroW:
1206 case AArch64::LDRDroW:
1207 case AArch64::LDRHHroW:
1208 case AArch64::LDRHroW:
1209 case AArch64::LDRQroW:
1210 case AArch64::LDRSBWroW:
1211 case AArch64::LDRSBXroW:
1212 case AArch64::LDRSHWroW:
1213 case AArch64::LDRSHXroW:
1214 case AArch64::LDRSWroW:
1215 case AArch64::LDRSroW:
1216 case AArch64::LDRWroW:
1217 case AArch64::LDRXroW:
1218 case AArch64::STRBBroW:
1219 case AArch64::STRBroW:
1220 case AArch64::STRDroW:
1221 case AArch64::STRHHroW:
1222 case AArch64::STRHroW:
1223 case AArch64::STRQroW:
1224 case AArch64::STRSroW:
1225 case AArch64::STRWroW:
1226 case AArch64::STRXroW:
1227 case AArch64::LDRBBroX:
1228 case AArch64::LDRBroX:
1229 case AArch64::LDRDroX:
1230 case AArch64::LDRHHroX:
1231 case AArch64::LDRHroX:
1232 case AArch64::LDRQroX:
1233 case AArch64::LDRSBWroX:
1234 case AArch64::LDRSBXroX:
1235 case AArch64::LDRSHWroX:
1236 case AArch64::LDRSHXroX:
1237 case AArch64::LDRSWroX:
1238 case AArch64::LDRSroX:
1239 case AArch64::LDRWroX:
1240 case AArch64::LDRXroX:
1241 case AArch64::STRBBroX:
1242 case AArch64::STRBroX:
1243 case AArch64::STRDroX:
1244 case AArch64::STRHHroX:
1245 case AArch64::STRHroX:
1246 case AArch64::STRQroX:
1247 case AArch64::STRSroX:
1248 case AArch64::STRWroX:
1249 case AArch64::STRXroX:
1251 unsigned Val = MI->getOperand(3).getImm();
1252 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val);
1253 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val);
1258 /// Check all MachineMemOperands for a hint to suppress pairing.
1259 bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr *MI) const {
1260 assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
1261 "Too many target MO flags");
1262 for (auto *MM : MI->memoperands()) {
1263 if (MM->getFlags() &
1264 (MOSuppressPair << MachineMemOperand::MOTargetStartBit)) {
1271 /// Set a flag on the first MachineMemOperand to suppress pairing.
1272 void AArch64InstrInfo::suppressLdStPair(MachineInstr *MI) const {
1273 if (MI->memoperands_empty())
1276 assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
1277 "Too many target MO flags");
1278 (*MI->memoperands_begin())
1279 ->setFlags(MOSuppressPair << MachineMemOperand::MOTargetStartBit);
1283 AArch64InstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
1285 const TargetRegisterInfo *TRI) const {
1286 switch (LdSt->getOpcode()) {
1289 case AArch64::STRSui:
1290 case AArch64::STRDui:
1291 case AArch64::STRQui:
1292 case AArch64::STRXui:
1293 case AArch64::STRWui:
1294 case AArch64::LDRSui:
1295 case AArch64::LDRDui:
1296 case AArch64::LDRQui:
1297 case AArch64::LDRXui:
1298 case AArch64::LDRWui:
1299 if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
1301 BaseReg = LdSt->getOperand(1).getReg();
1302 MachineFunction &MF = *LdSt->getParent()->getParent();
1303 unsigned Width = getRegClass(LdSt->getDesc(), 0, TRI, MF)->getSize();
1304 Offset = LdSt->getOperand(2).getImm() * Width;
1309 bool AArch64InstrInfo::getLdStBaseRegImmOfsWidth(
1310 MachineInstr *LdSt, unsigned &BaseReg, int &Offset, int &Width,
1311 const TargetRegisterInfo *TRI) const {
1312 // Handle only loads/stores with base register followed by immediate offset.
1313 if (LdSt->getNumOperands() != 3)
1315 if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
1318 // Offset is calculated as the immediate operand multiplied by the scaling factor.
1319 // Unscaled instructions have scaling factor set to 1.
1321 switch (LdSt->getOpcode()) {
1324 case AArch64::LDURQi:
1325 case AArch64::STURQi:
1329 case AArch64::LDURXi:
1330 case AArch64::LDURDi:
1331 case AArch64::STURXi:
1332 case AArch64::STURDi:
1336 case AArch64::LDURWi:
1337 case AArch64::LDURSi:
1338 case AArch64::LDURSWi:
1339 case AArch64::STURWi:
1340 case AArch64::STURSi:
1344 case AArch64::LDURHi:
1345 case AArch64::LDURHHi:
1346 case AArch64::LDURSHXi:
1347 case AArch64::LDURSHWi:
1348 case AArch64::STURHi:
1349 case AArch64::STURHHi:
1353 case AArch64::LDURBi:
1354 case AArch64::LDURBBi:
1355 case AArch64::LDURSBXi:
1356 case AArch64::LDURSBWi:
1357 case AArch64::STURBi:
1358 case AArch64::STURBBi:
1362 case AArch64::LDRXui:
1363 case AArch64::STRXui:
1366 case AArch64::LDRWui:
1367 case AArch64::STRWui:
1370 case AArch64::LDRBui:
1371 case AArch64::STRBui:
1374 case AArch64::LDRHui:
1375 case AArch64::STRHui:
1378 case AArch64::LDRSui:
1379 case AArch64::STRSui:
1382 case AArch64::LDRDui:
1383 case AArch64::STRDui:
1386 case AArch64::LDRQui:
1387 case AArch64::STRQui:
1390 case AArch64::LDRBBui:
1391 case AArch64::STRBBui:
1394 case AArch64::LDRHHui:
1395 case AArch64::STRHHui:
1400 BaseReg = LdSt->getOperand(1).getReg();
1401 Offset = LdSt->getOperand(2).getImm() * Scale;
1405 /// Detect opportunities for ldp/stp formation.
1407 /// Only called for LdSt for which getLdStBaseRegImmOfs returns true.
1408 bool AArch64InstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
1409 MachineInstr *SecondLdSt,
1410 unsigned NumLoads) const {
1411 // Only cluster up to a single pair.
1414 if (FirstLdSt->getOpcode() != SecondLdSt->getOpcode())
1416 // getLdStBaseRegImmOfs guarantees that oper 2 isImm.
1417 unsigned Ofs1 = FirstLdSt->getOperand(2).getImm();
1418 // Allow 6 bits of positive range.
1421 // The caller should already have ordered First/SecondLdSt by offset.
1422 unsigned Ofs2 = SecondLdSt->getOperand(2).getImm();
1423 return Ofs1 + 1 == Ofs2;
1426 bool AArch64InstrInfo::shouldScheduleAdjacent(MachineInstr *First,
1427 MachineInstr *Second) const {
1428 // Cyclone can fuse CMN, CMP followed by Bcc.
1430 // FIXME: B0 can also fuse:
1431 // AND, BIC, ORN, ORR, or EOR (optional S) followed by Bcc or CBZ or CBNZ.
1432 if (Second->getOpcode() != AArch64::Bcc)
1434 switch (First->getOpcode()) {
1437 case AArch64::SUBSWri:
1438 case AArch64::ADDSWri:
1439 case AArch64::ANDSWri:
1440 case AArch64::SUBSXri:
1441 case AArch64::ADDSXri:
1442 case AArch64::ANDSXri:
1447 MachineInstr *AArch64InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1450 const MDNode *MDPtr,
1451 DebugLoc DL) const {
1452 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE))
1453 .addFrameIndex(FrameIx)
1456 .addMetadata(MDPtr);
1460 static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
1461 unsigned Reg, unsigned SubIdx,
1463 const TargetRegisterInfo *TRI) {
1465 return MIB.addReg(Reg, State);
1467 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1468 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1469 return MIB.addReg(Reg, State, SubIdx);
1472 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg,
1474 // We really want the positive remainder mod 32 here, that happens to be
1475 // easily obtainable with a mask.
1476 return ((DestReg - SrcReg) & 0x1f) < NumRegs;
1479 void AArch64InstrInfo::copyPhysRegTuple(
1480 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
1481 unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode,
1482 llvm::ArrayRef<unsigned> Indices) const {
1483 assert(Subtarget.hasNEON() &&
1484 "Unexpected register copy without NEON");
1485 const TargetRegisterInfo *TRI = &getRegisterInfo();
1486 uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
1487 uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg);
1488 unsigned NumRegs = Indices.size();
1490 int SubReg = 0, End = NumRegs, Incr = 1;
1491 if (forwardCopyWillClobberTuple(DestEncoding, SrcEncoding, NumRegs)) {
1492 SubReg = NumRegs - 1;
1497 for (; SubReg != End; SubReg += Incr) {
1498 const MachineInstrBuilder &MIB = BuildMI(MBB, I, DL, get(Opcode));
1499 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
1500 AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI);
1501 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
1505 void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1506 MachineBasicBlock::iterator I, DebugLoc DL,
1507 unsigned DestReg, unsigned SrcReg,
1508 bool KillSrc) const {
1509 if (AArch64::GPR32spRegClass.contains(DestReg) &&
1510 (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
1511 const TargetRegisterInfo *TRI = &getRegisterInfo();
1513 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
1514 // If either operand is WSP, expand to ADD #0.
1515 if (Subtarget.hasZeroCycleRegMove()) {
1516 // Cyclone recognizes "ADD Xd, Xn, #0" as a zero-cycle register move.
1517 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
1518 &AArch64::GPR64spRegClass);
1519 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32,
1520 &AArch64::GPR64spRegClass);
1521 // This instruction is reading and writing X registers. This may upset
1522 // the register scavenger and machine verifier, so we need to indicate
1523 // that we are reading an undefined value from SrcRegX, but a proper
1524 // value from SrcReg.
1525 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestRegX)
1526 .addReg(SrcRegX, RegState::Undef)
1528 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
1529 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1531 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
1532 .addReg(SrcReg, getKillRegState(KillSrc))
1534 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1536 } else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroing()) {
1537 BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg).addImm(0).addImm(
1538 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1540 if (Subtarget.hasZeroCycleRegMove()) {
1541 // Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
1542 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
1543 &AArch64::GPR64spRegClass);
1544 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32,
1545 &AArch64::GPR64spRegClass);
1546 // This instruction is reading and writing X registers. This may upset
1547 // the register scavenger and machine verifier, so we need to indicate
1548 // that we are reading an undefined value from SrcRegX, but a proper
1549 // value from SrcReg.
1550 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestRegX)
1551 .addReg(AArch64::XZR)
1552 .addReg(SrcRegX, RegState::Undef)
1553 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1555 // Otherwise, expand to ORR WZR.
1556 BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
1557 .addReg(AArch64::WZR)
1558 .addReg(SrcReg, getKillRegState(KillSrc));
1564 if (AArch64::GPR64spRegClass.contains(DestReg) &&
1565 (AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) {
1566 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) {
1567 // If either operand is SP, expand to ADD #0.
1568 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
1569 .addReg(SrcReg, getKillRegState(KillSrc))
1571 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1572 } else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroing()) {
1573 BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg).addImm(0).addImm(
1574 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1576 // Otherwise, expand to ORR XZR.
1577 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
1578 .addReg(AArch64::XZR)
1579 .addReg(SrcReg, getKillRegState(KillSrc));
1584 // Copy a DDDD register quad by copying the individual sub-registers.
1585 if (AArch64::DDDDRegClass.contains(DestReg) &&
1586 AArch64::DDDDRegClass.contains(SrcReg)) {
1587 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1,
1588 AArch64::dsub2, AArch64::dsub3 };
1589 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1594 // Copy a DDD register triple by copying the individual sub-registers.
1595 if (AArch64::DDDRegClass.contains(DestReg) &&
1596 AArch64::DDDRegClass.contains(SrcReg)) {
1597 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1,
1599 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1604 // Copy a DD register pair by copying the individual sub-registers.
1605 if (AArch64::DDRegClass.contains(DestReg) &&
1606 AArch64::DDRegClass.contains(SrcReg)) {
1607 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1 };
1608 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1613 // Copy a QQQQ register quad by copying the individual sub-registers.
1614 if (AArch64::QQQQRegClass.contains(DestReg) &&
1615 AArch64::QQQQRegClass.contains(SrcReg)) {
1616 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1,
1617 AArch64::qsub2, AArch64::qsub3 };
1618 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1623 // Copy a QQQ register triple by copying the individual sub-registers.
1624 if (AArch64::QQQRegClass.contains(DestReg) &&
1625 AArch64::QQQRegClass.contains(SrcReg)) {
1626 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1,
1628 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1633 // Copy a QQ register pair by copying the individual sub-registers.
1634 if (AArch64::QQRegClass.contains(DestReg) &&
1635 AArch64::QQRegClass.contains(SrcReg)) {
1636 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1 };
1637 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1642 if (AArch64::FPR128RegClass.contains(DestReg) &&
1643 AArch64::FPR128RegClass.contains(SrcReg)) {
1644 if(Subtarget.hasNEON()) {
1645 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1647 .addReg(SrcReg, getKillRegState(KillSrc));
1649 BuildMI(MBB, I, DL, get(AArch64::STRQpre))
1650 .addReg(AArch64::SP, RegState::Define)
1651 .addReg(SrcReg, getKillRegState(KillSrc))
1652 .addReg(AArch64::SP)
1654 BuildMI(MBB, I, DL, get(AArch64::LDRQpre))
1655 .addReg(AArch64::SP, RegState::Define)
1656 .addReg(DestReg, RegState::Define)
1657 .addReg(AArch64::SP)
1663 if (AArch64::FPR64RegClass.contains(DestReg) &&
1664 AArch64::FPR64RegClass.contains(SrcReg)) {
1665 if(Subtarget.hasNEON()) {
1666 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub,
1667 &AArch64::FPR128RegClass);
1668 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub,
1669 &AArch64::FPR128RegClass);
1670 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1672 .addReg(SrcReg, getKillRegState(KillSrc));
1674 BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
1675 .addReg(SrcReg, getKillRegState(KillSrc));
1680 if (AArch64::FPR32RegClass.contains(DestReg) &&
1681 AArch64::FPR32RegClass.contains(SrcReg)) {
1682 if(Subtarget.hasNEON()) {
1683 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
1684 &AArch64::FPR128RegClass);
1685 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
1686 &AArch64::FPR128RegClass);
1687 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1689 .addReg(SrcReg, getKillRegState(KillSrc));
1691 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1692 .addReg(SrcReg, getKillRegState(KillSrc));
1697 if (AArch64::FPR16RegClass.contains(DestReg) &&
1698 AArch64::FPR16RegClass.contains(SrcReg)) {
1699 if(Subtarget.hasNEON()) {
1700 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
1701 &AArch64::FPR128RegClass);
1702 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
1703 &AArch64::FPR128RegClass);
1704 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1706 .addReg(SrcReg, getKillRegState(KillSrc));
1708 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
1709 &AArch64::FPR32RegClass);
1710 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
1711 &AArch64::FPR32RegClass);
1712 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1713 .addReg(SrcReg, getKillRegState(KillSrc));
1718 if (AArch64::FPR8RegClass.contains(DestReg) &&
1719 AArch64::FPR8RegClass.contains(SrcReg)) {
1720 if(Subtarget.hasNEON()) {
1721 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
1722 &AArch64::FPR128RegClass);
1723 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
1724 &AArch64::FPR128RegClass);
1725 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1727 .addReg(SrcReg, getKillRegState(KillSrc));
1729 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
1730 &AArch64::FPR32RegClass);
1731 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
1732 &AArch64::FPR32RegClass);
1733 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1734 .addReg(SrcReg, getKillRegState(KillSrc));
1739 // Copies between GPR64 and FPR64.
1740 if (AArch64::FPR64RegClass.contains(DestReg) &&
1741 AArch64::GPR64RegClass.contains(SrcReg)) {
1742 BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg)
1743 .addReg(SrcReg, getKillRegState(KillSrc));
1746 if (AArch64::GPR64RegClass.contains(DestReg) &&
1747 AArch64::FPR64RegClass.contains(SrcReg)) {
1748 BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
1749 .addReg(SrcReg, getKillRegState(KillSrc));
1752 // Copies between GPR32 and FPR32.
1753 if (AArch64::FPR32RegClass.contains(DestReg) &&
1754 AArch64::GPR32RegClass.contains(SrcReg)) {
1755 BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg)
1756 .addReg(SrcReg, getKillRegState(KillSrc));
1759 if (AArch64::GPR32RegClass.contains(DestReg) &&
1760 AArch64::FPR32RegClass.contains(SrcReg)) {
1761 BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
1762 .addReg(SrcReg, getKillRegState(KillSrc));
1766 if (DestReg == AArch64::NZCV) {
1767 assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy");
1768 BuildMI(MBB, I, DL, get(AArch64::MSR))
1769 .addImm(AArch64SysReg::NZCV)
1770 .addReg(SrcReg, getKillRegState(KillSrc))
1771 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define);
1775 if (SrcReg == AArch64::NZCV) {
1776 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy");
1777 BuildMI(MBB, I, DL, get(AArch64::MRS))
1779 .addImm(AArch64SysReg::NZCV)
1780 .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
1784 llvm_unreachable("unimplemented reg-to-reg copy");
1787 void AArch64InstrInfo::storeRegToStackSlot(
1788 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
1789 bool isKill, int FI, const TargetRegisterClass *RC,
1790 const TargetRegisterInfo *TRI) const {
1792 if (MBBI != MBB.end())
1793 DL = MBBI->getDebugLoc();
1794 MachineFunction &MF = *MBB.getParent();
1795 MachineFrameInfo &MFI = *MF.getFrameInfo();
1796 unsigned Align = MFI.getObjectAlignment(FI);
1798 MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI));
1799 MachineMemOperand *MMO = MF.getMachineMemOperand(
1800 PtrInfo, MachineMemOperand::MOStore, MFI.getObjectSize(FI), Align);
1803 switch (RC->getSize()) {
1805 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
1806 Opc = AArch64::STRBui;
1809 if (AArch64::FPR16RegClass.hasSubClassEq(RC))
1810 Opc = AArch64::STRHui;
1813 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
1814 Opc = AArch64::STRWui;
1815 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
1816 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
1818 assert(SrcReg != AArch64::WSP);
1819 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
1820 Opc = AArch64::STRSui;
1823 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
1824 Opc = AArch64::STRXui;
1825 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
1826 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
1828 assert(SrcReg != AArch64::SP);
1829 } else if (AArch64::FPR64RegClass.hasSubClassEq(RC))
1830 Opc = AArch64::STRDui;
1833 if (AArch64::FPR128RegClass.hasSubClassEq(RC))
1834 Opc = AArch64::STRQui;
1835 else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
1836 assert(Subtarget.hasNEON() &&
1837 "Unexpected register store without NEON");
1838 Opc = AArch64::ST1Twov1d, Offset = false;
1842 if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
1843 assert(Subtarget.hasNEON() &&
1844 "Unexpected register store without NEON");
1845 Opc = AArch64::ST1Threev1d, Offset = false;
1849 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
1850 assert(Subtarget.hasNEON() &&
1851 "Unexpected register store without NEON");
1852 Opc = AArch64::ST1Fourv1d, Offset = false;
1853 } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
1854 assert(Subtarget.hasNEON() &&
1855 "Unexpected register store without NEON");
1856 Opc = AArch64::ST1Twov2d, Offset = false;
1860 if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
1861 assert(Subtarget.hasNEON() &&
1862 "Unexpected register store without NEON");
1863 Opc = AArch64::ST1Threev2d, Offset = false;
1867 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
1868 assert(Subtarget.hasNEON() &&
1869 "Unexpected register store without NEON");
1870 Opc = AArch64::ST1Fourv2d, Offset = false;
1874 assert(Opc && "Unknown register class");
1876 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
1877 .addReg(SrcReg, getKillRegState(isKill))
1882 MI.addMemOperand(MMO);
1885 void AArch64InstrInfo::loadRegFromStackSlot(
1886 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
1887 int FI, const TargetRegisterClass *RC,
1888 const TargetRegisterInfo *TRI) const {
1890 if (MBBI != MBB.end())
1891 DL = MBBI->getDebugLoc();
1892 MachineFunction &MF = *MBB.getParent();
1893 MachineFrameInfo &MFI = *MF.getFrameInfo();
1894 unsigned Align = MFI.getObjectAlignment(FI);
1895 MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI));
1896 MachineMemOperand *MMO = MF.getMachineMemOperand(
1897 PtrInfo, MachineMemOperand::MOLoad, MFI.getObjectSize(FI), Align);
1901 switch (RC->getSize()) {
1903 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
1904 Opc = AArch64::LDRBui;
1907 if (AArch64::FPR16RegClass.hasSubClassEq(RC))
1908 Opc = AArch64::LDRHui;
1911 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
1912 Opc = AArch64::LDRWui;
1913 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1914 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass);
1916 assert(DestReg != AArch64::WSP);
1917 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
1918 Opc = AArch64::LDRSui;
1921 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
1922 Opc = AArch64::LDRXui;
1923 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1924 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass);
1926 assert(DestReg != AArch64::SP);
1927 } else if (AArch64::FPR64RegClass.hasSubClassEq(RC))
1928 Opc = AArch64::LDRDui;
1931 if (AArch64::FPR128RegClass.hasSubClassEq(RC))
1932 Opc = AArch64::LDRQui;
1933 else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
1934 assert(Subtarget.hasNEON() &&
1935 "Unexpected register load without NEON");
1936 Opc = AArch64::LD1Twov1d, Offset = false;
1940 if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
1941 assert(Subtarget.hasNEON() &&
1942 "Unexpected register load without NEON");
1943 Opc = AArch64::LD1Threev1d, Offset = false;
1947 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
1948 assert(Subtarget.hasNEON() &&
1949 "Unexpected register load without NEON");
1950 Opc = AArch64::LD1Fourv1d, Offset = false;
1951 } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
1952 assert(Subtarget.hasNEON() &&
1953 "Unexpected register load without NEON");
1954 Opc = AArch64::LD1Twov2d, Offset = false;
1958 if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
1959 assert(Subtarget.hasNEON() &&
1960 "Unexpected register load without NEON");
1961 Opc = AArch64::LD1Threev2d, Offset = false;
1965 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
1966 assert(Subtarget.hasNEON() &&
1967 "Unexpected register load without NEON");
1968 Opc = AArch64::LD1Fourv2d, Offset = false;
1972 assert(Opc && "Unknown register class");
1974 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
1975 .addReg(DestReg, getDefRegState(true))
1979 MI.addMemOperand(MMO);
1982 void llvm::emitFrameOffset(MachineBasicBlock &MBB,
1983 MachineBasicBlock::iterator MBBI, DebugLoc DL,
1984 unsigned DestReg, unsigned SrcReg, int Offset,
1985 const TargetInstrInfo *TII,
1986 MachineInstr::MIFlag Flag, bool SetNZCV) {
1987 if (DestReg == SrcReg && Offset == 0)
1990 bool isSub = Offset < 0;
1994 // FIXME: If the offset won't fit in 24-bits, compute the offset into a
1995 // scratch register. If DestReg is a virtual register, use it as the
1996 // scratch register; otherwise, create a new virtual register (to be
1997 // replaced by the scavenger at the end of PEI). That case can be optimized
1998 // slightly if DestReg is SP which is always 16-byte aligned, so the scratch
1999 // register can be loaded with offset%8 and the add/sub can use an extending
2000 // instruction with LSL#3.
2001 // Currently the function handles any offsets but generates a poor sequence
2003 // assert(Offset < (1 << 24) && "unimplemented reg plus immediate");
2007 Opc = isSub ? AArch64::SUBSXri : AArch64::ADDSXri;
2009 Opc = isSub ? AArch64::SUBXri : AArch64::ADDXri;
2010 const unsigned MaxEncoding = 0xfff;
2011 const unsigned ShiftSize = 12;
2012 const unsigned MaxEncodableValue = MaxEncoding << ShiftSize;
2013 while (((unsigned)Offset) >= (1 << ShiftSize)) {
2015 if (((unsigned)Offset) > MaxEncodableValue) {
2016 ThisVal = MaxEncodableValue;
2018 ThisVal = Offset & MaxEncodableValue;
2020 assert((ThisVal >> ShiftSize) <= MaxEncoding &&
2021 "Encoding cannot handle value that big");
2022 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
2024 .addImm(ThisVal >> ShiftSize)
2025 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftSize))
2033 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
2036 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
2041 AArch64InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
2042 const SmallVectorImpl<unsigned> &Ops,
2043 int FrameIndex) const {
2044 // This is a bit of a hack. Consider this instruction:
2046 // %vreg0<def> = COPY %SP; GPR64all:%vreg0
2048 // We explicitly chose GPR64all for the virtual register so such a copy might
2049 // be eliminated by RegisterCoalescer. However, that may not be possible, and
2050 // %vreg0 may even spill. We can't spill %SP, and since it is in the GPR64all
2051 // register class, TargetInstrInfo::foldMemoryOperand() is going to try.
2053 // To prevent that, we are going to constrain the %vreg0 register class here.
2055 // <rdar://problem/11522048>
2058 unsigned DstReg = MI->getOperand(0).getReg();
2059 unsigned SrcReg = MI->getOperand(1).getReg();
2060 if (SrcReg == AArch64::SP &&
2061 TargetRegisterInfo::isVirtualRegister(DstReg)) {
2062 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass);
2065 if (DstReg == AArch64::SP &&
2066 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
2067 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
2076 int llvm::isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
2077 bool *OutUseUnscaledOp,
2078 unsigned *OutUnscaledOp,
2079 int *EmittableOffset) {
2081 bool IsSigned = false;
2082 // The ImmIdx should be changed case by case if it is not 2.
2083 unsigned ImmIdx = 2;
2084 unsigned UnscaledOp = 0;
2085 // Set output values in case of early exit.
2086 if (EmittableOffset)
2087 *EmittableOffset = 0;
2088 if (OutUseUnscaledOp)
2089 *OutUseUnscaledOp = false;
2092 switch (MI.getOpcode()) {
2094 llvm_unreachable("unhandled opcode in rewriteAArch64FrameIndex");
2095 // Vector spills/fills can't take an immediate offset.
2096 case AArch64::LD1Twov2d:
2097 case AArch64::LD1Threev2d:
2098 case AArch64::LD1Fourv2d:
2099 case AArch64::LD1Twov1d:
2100 case AArch64::LD1Threev1d:
2101 case AArch64::LD1Fourv1d:
2102 case AArch64::ST1Twov2d:
2103 case AArch64::ST1Threev2d:
2104 case AArch64::ST1Fourv2d:
2105 case AArch64::ST1Twov1d:
2106 case AArch64::ST1Threev1d:
2107 case AArch64::ST1Fourv1d:
2108 return AArch64FrameOffsetCannotUpdate;
2109 case AArch64::PRFMui:
2111 UnscaledOp = AArch64::PRFUMi;
2113 case AArch64::LDRXui:
2115 UnscaledOp = AArch64::LDURXi;
2117 case AArch64::LDRWui:
2119 UnscaledOp = AArch64::LDURWi;
2121 case AArch64::LDRBui:
2123 UnscaledOp = AArch64::LDURBi;
2125 case AArch64::LDRHui:
2127 UnscaledOp = AArch64::LDURHi;
2129 case AArch64::LDRSui:
2131 UnscaledOp = AArch64::LDURSi;
2133 case AArch64::LDRDui:
2135 UnscaledOp = AArch64::LDURDi;
2137 case AArch64::LDRQui:
2139 UnscaledOp = AArch64::LDURQi;
2141 case AArch64::LDRBBui:
2143 UnscaledOp = AArch64::LDURBBi;
2145 case AArch64::LDRHHui:
2147 UnscaledOp = AArch64::LDURHHi;
2149 case AArch64::LDRSBXui:
2151 UnscaledOp = AArch64::LDURSBXi;
2153 case AArch64::LDRSBWui:
2155 UnscaledOp = AArch64::LDURSBWi;
2157 case AArch64::LDRSHXui:
2159 UnscaledOp = AArch64::LDURSHXi;
2161 case AArch64::LDRSHWui:
2163 UnscaledOp = AArch64::LDURSHWi;
2165 case AArch64::LDRSWui:
2167 UnscaledOp = AArch64::LDURSWi;
2170 case AArch64::STRXui:
2172 UnscaledOp = AArch64::STURXi;
2174 case AArch64::STRWui:
2176 UnscaledOp = AArch64::STURWi;
2178 case AArch64::STRBui:
2180 UnscaledOp = AArch64::STURBi;
2182 case AArch64::STRHui:
2184 UnscaledOp = AArch64::STURHi;
2186 case AArch64::STRSui:
2188 UnscaledOp = AArch64::STURSi;
2190 case AArch64::STRDui:
2192 UnscaledOp = AArch64::STURDi;
2194 case AArch64::STRQui:
2196 UnscaledOp = AArch64::STURQi;
2198 case AArch64::STRBBui:
2200 UnscaledOp = AArch64::STURBBi;
2202 case AArch64::STRHHui:
2204 UnscaledOp = AArch64::STURHHi;
2207 case AArch64::LDPXi:
2208 case AArch64::LDPDi:
2209 case AArch64::STPXi:
2210 case AArch64::STPDi:
2214 case AArch64::LDPQi:
2215 case AArch64::STPQi:
2219 case AArch64::LDPWi:
2220 case AArch64::LDPSi:
2221 case AArch64::STPWi:
2222 case AArch64::STPSi:
2227 case AArch64::LDURXi:
2228 case AArch64::LDURWi:
2229 case AArch64::LDURBi:
2230 case AArch64::LDURHi:
2231 case AArch64::LDURSi:
2232 case AArch64::LDURDi:
2233 case AArch64::LDURQi:
2234 case AArch64::LDURHHi:
2235 case AArch64::LDURBBi:
2236 case AArch64::LDURSBXi:
2237 case AArch64::LDURSBWi:
2238 case AArch64::LDURSHXi:
2239 case AArch64::LDURSHWi:
2240 case AArch64::LDURSWi:
2241 case AArch64::STURXi:
2242 case AArch64::STURWi:
2243 case AArch64::STURBi:
2244 case AArch64::STURHi:
2245 case AArch64::STURSi:
2246 case AArch64::STURDi:
2247 case AArch64::STURQi:
2248 case AArch64::STURBBi:
2249 case AArch64::STURHHi:
2254 Offset += MI.getOperand(ImmIdx).getImm() * Scale;
2256 bool useUnscaledOp = false;
2257 // If the offset doesn't match the scale, we rewrite the instruction to
2258 // use the unscaled instruction instead. Likewise, if we have a negative
2259 // offset (and have an unscaled op to use).
2260 if ((Offset & (Scale - 1)) != 0 || (Offset < 0 && UnscaledOp != 0))
2261 useUnscaledOp = true;
2263 // Use an unscaled addressing mode if the instruction has a negative offset
2264 // (or if the instruction is already using an unscaled addressing mode).
2267 // ldp/stp instructions.
2270 } else if (UnscaledOp == 0 || useUnscaledOp) {
2280 // Attempt to fold address computation.
2281 int MaxOff = (1 << (MaskBits - IsSigned)) - 1;
2282 int MinOff = (IsSigned ? (-MaxOff - 1) : 0);
2283 if (Offset >= MinOff && Offset <= MaxOff) {
2284 if (EmittableOffset)
2285 *EmittableOffset = Offset;
2288 int NewOff = Offset < 0 ? MinOff : MaxOff;
2289 if (EmittableOffset)
2290 *EmittableOffset = NewOff;
2291 Offset = (Offset - NewOff) * Scale;
2293 if (OutUseUnscaledOp)
2294 *OutUseUnscaledOp = useUnscaledOp;
2296 *OutUnscaledOp = UnscaledOp;
2297 return AArch64FrameOffsetCanUpdate |
2298 (Offset == 0 ? AArch64FrameOffsetIsLegal : 0);
2301 bool llvm::rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2302 unsigned FrameReg, int &Offset,
2303 const AArch64InstrInfo *TII) {
2304 unsigned Opcode = MI.getOpcode();
2305 unsigned ImmIdx = FrameRegIdx + 1;
2307 if (Opcode == AArch64::ADDSXri || Opcode == AArch64::ADDXri) {
2308 Offset += MI.getOperand(ImmIdx).getImm();
2309 emitFrameOffset(*MI.getParent(), MI, MI.getDebugLoc(),
2310 MI.getOperand(0).getReg(), FrameReg, Offset, TII,
2311 MachineInstr::NoFlags, (Opcode == AArch64::ADDSXri));
2312 MI.eraseFromParent();
2318 unsigned UnscaledOp;
2320 int Status = isAArch64FrameOffsetLegal(MI, Offset, &UseUnscaledOp,
2321 &UnscaledOp, &NewOffset);
2322 if (Status & AArch64FrameOffsetCanUpdate) {
2323 if (Status & AArch64FrameOffsetIsLegal)
2324 // Replace the FrameIndex with FrameReg.
2325 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2327 MI.setDesc(TII->get(UnscaledOp));
2329 MI.getOperand(ImmIdx).ChangeToImmediate(NewOffset);
2336 void AArch64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
2337 NopInst.setOpcode(AArch64::HINT);
2338 NopInst.addOperand(MCOperand::CreateImm(0));
2340 /// useMachineCombiner - return true when a target supports MachineCombiner
2341 bool AArch64InstrInfo::useMachineCombiner() const {
2342 // AArch64 supports the combiner
2346 // True when Opc sets flag
2347 static bool isCombineInstrSettingFlag(unsigned Opc) {
2349 case AArch64::ADDSWrr:
2350 case AArch64::ADDSWri:
2351 case AArch64::ADDSXrr:
2352 case AArch64::ADDSXri:
2353 case AArch64::SUBSWrr:
2354 case AArch64::SUBSXrr:
2355 // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi.
2356 case AArch64::SUBSWri:
2357 case AArch64::SUBSXri:
2365 // 32b Opcodes that can be combined with a MUL
2366 static bool isCombineInstrCandidate32(unsigned Opc) {
2368 case AArch64::ADDWrr:
2369 case AArch64::ADDWri:
2370 case AArch64::SUBWrr:
2371 case AArch64::ADDSWrr:
2372 case AArch64::ADDSWri:
2373 case AArch64::SUBSWrr:
2374 // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi.
2375 case AArch64::SUBWri:
2376 case AArch64::SUBSWri:
2384 // 64b Opcodes that can be combined with a MUL
2385 static bool isCombineInstrCandidate64(unsigned Opc) {
2387 case AArch64::ADDXrr:
2388 case AArch64::ADDXri:
2389 case AArch64::SUBXrr:
2390 case AArch64::ADDSXrr:
2391 case AArch64::ADDSXri:
2392 case AArch64::SUBSXrr:
2393 // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi.
2394 case AArch64::SUBXri:
2395 case AArch64::SUBSXri:
2403 // Opcodes that can be combined with a MUL
2404 static bool isCombineInstrCandidate(unsigned Opc) {
2405 return (isCombineInstrCandidate32(Opc) || isCombineInstrCandidate64(Opc));
2408 static bool canCombineWithMUL(MachineBasicBlock &MBB, MachineOperand &MO,
2409 unsigned MulOpc, unsigned ZeroReg) {
2410 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2411 MachineInstr *MI = nullptr;
2412 // We need a virtual register definition.
2413 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
2414 MI = MRI.getUniqueVRegDef(MO.getReg());
2415 // And it needs to be in the trace (otherwise, it won't have a depth).
2416 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != MulOpc)
2419 assert(MI->getNumOperands() >= 4 && MI->getOperand(0).isReg() &&
2420 MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
2421 MI->getOperand(3).isReg() && "MAdd/MSub must have a least 4 regs");
2423 // The third input reg must be zero.
2424 if (MI->getOperand(3).getReg() != ZeroReg)
2427 // Must only used by the user we combine with.
2428 if (!MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
2434 /// hasPattern - return true when there is potentially a faster code sequence
2435 /// for an instruction chain ending in \p Root. All potential patterns are
2437 /// in the \p Pattern vector. Pattern should be sorted in priority order since
2438 /// the pattern evaluator stops checking as soon as it finds a faster sequence.
2440 bool AArch64InstrInfo::hasPattern(
2442 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const {
2443 unsigned Opc = Root.getOpcode();
2444 MachineBasicBlock &MBB = *Root.getParent();
2447 if (!isCombineInstrCandidate(Opc))
2449 if (isCombineInstrSettingFlag(Opc)) {
2450 int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true);
2451 // When NZCV is live bail out.
2454 unsigned NewOpc = convertFlagSettingOpcode(&Root);
2455 // When opcode can't change bail out.
2456 // CHECKME: do we miss any cases for opcode conversion?
2465 case AArch64::ADDWrr:
2466 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
2467 "ADDWrr does not have register operands");
2468 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2470 Pattern.push_back(MachineCombinerPattern::MC_MULADDW_OP1);
2473 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDWrrr,
2475 Pattern.push_back(MachineCombinerPattern::MC_MULADDW_OP2);
2479 case AArch64::ADDXrr:
2480 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2482 Pattern.push_back(MachineCombinerPattern::MC_MULADDX_OP1);
2485 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDXrrr,
2487 Pattern.push_back(MachineCombinerPattern::MC_MULADDX_OP2);
2491 case AArch64::SUBWrr:
2492 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2494 Pattern.push_back(MachineCombinerPattern::MC_MULSUBW_OP1);
2497 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDWrrr,
2499 Pattern.push_back(MachineCombinerPattern::MC_MULSUBW_OP2);
2503 case AArch64::SUBXrr:
2504 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2506 Pattern.push_back(MachineCombinerPattern::MC_MULSUBX_OP1);
2509 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDXrrr,
2511 Pattern.push_back(MachineCombinerPattern::MC_MULSUBX_OP2);
2515 case AArch64::ADDWri:
2516 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2518 Pattern.push_back(MachineCombinerPattern::MC_MULADDWI_OP1);
2522 case AArch64::ADDXri:
2523 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2525 Pattern.push_back(MachineCombinerPattern::MC_MULADDXI_OP1);
2529 case AArch64::SUBWri:
2530 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2532 Pattern.push_back(MachineCombinerPattern::MC_MULSUBWI_OP1);
2536 case AArch64::SUBXri:
2537 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2539 Pattern.push_back(MachineCombinerPattern::MC_MULSUBXI_OP1);
2547 /// genMadd - Generate madd instruction and combine mul and add.
2551 /// ==> MADD R,A,B,C
2552 /// \param Root is the ADD instruction
2553 /// \param [out] InsInstrs is a vector of machine instructions and will
2554 /// contain the generated madd instruction
2555 /// \param IdxMulOpd is index of operand in Root that is the result of
2556 /// the MUL. In the example above IdxMulOpd is 1.
2557 /// \param MaddOpc the opcode fo the madd instruction
2558 static MachineInstr *genMadd(MachineFunction &MF, MachineRegisterInfo &MRI,
2559 const TargetInstrInfo *TII, MachineInstr &Root,
2560 SmallVectorImpl<MachineInstr *> &InsInstrs,
2561 unsigned IdxMulOpd, unsigned MaddOpc,
2562 const TargetRegisterClass *RC) {
2563 assert(IdxMulOpd == 1 || IdxMulOpd == 2);
2565 unsigned IdxOtherOpd = IdxMulOpd == 1 ? 2 : 1;
2566 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
2567 unsigned ResultReg = Root.getOperand(0).getReg();
2568 unsigned SrcReg0 = MUL->getOperand(1).getReg();
2569 bool Src0IsKill = MUL->getOperand(1).isKill();
2570 unsigned SrcReg1 = MUL->getOperand(2).getReg();
2571 bool Src1IsKill = MUL->getOperand(2).isKill();
2572 unsigned SrcReg2 = Root.getOperand(IdxOtherOpd).getReg();
2573 bool Src2IsKill = Root.getOperand(IdxOtherOpd).isKill();
2575 if (TargetRegisterInfo::isVirtualRegister(ResultReg))
2576 MRI.constrainRegClass(ResultReg, RC);
2577 if (TargetRegisterInfo::isVirtualRegister(SrcReg0))
2578 MRI.constrainRegClass(SrcReg0, RC);
2579 if (TargetRegisterInfo::isVirtualRegister(SrcReg1))
2580 MRI.constrainRegClass(SrcReg1, RC);
2581 if (TargetRegisterInfo::isVirtualRegister(SrcReg2))
2582 MRI.constrainRegClass(SrcReg2, RC);
2584 MachineInstrBuilder MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc),
2586 .addReg(SrcReg0, getKillRegState(Src0IsKill))
2587 .addReg(SrcReg1, getKillRegState(Src1IsKill))
2588 .addReg(SrcReg2, getKillRegState(Src2IsKill));
2590 InsInstrs.push_back(MIB);
2594 /// genMaddR - Generate madd instruction and combine mul and add using
2595 /// an extra virtual register
2596 /// Example - an ADD intermediate needs to be stored in a register:
2599 /// ==> ORR V, ZR, Imm
2600 /// ==> MADD R,A,B,V
2601 /// \param Root is the ADD instruction
2602 /// \param [out] InsInstrs is a vector of machine instructions and will
2603 /// contain the generated madd instruction
2604 /// \param IdxMulOpd is index of operand in Root that is the result of
2605 /// the MUL. In the example above IdxMulOpd is 1.
2606 /// \param MaddOpc the opcode fo the madd instruction
2607 /// \param VR is a virtual register that holds the value of an ADD operand
2608 /// (V in the example above).
2609 static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI,
2610 const TargetInstrInfo *TII, MachineInstr &Root,
2611 SmallVectorImpl<MachineInstr *> &InsInstrs,
2612 unsigned IdxMulOpd, unsigned MaddOpc,
2613 unsigned VR, const TargetRegisterClass *RC) {
2614 assert(IdxMulOpd == 1 || IdxMulOpd == 2);
2616 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
2617 unsigned ResultReg = Root.getOperand(0).getReg();
2618 unsigned SrcReg0 = MUL->getOperand(1).getReg();
2619 bool Src0IsKill = MUL->getOperand(1).isKill();
2620 unsigned SrcReg1 = MUL->getOperand(2).getReg();
2621 bool Src1IsKill = MUL->getOperand(2).isKill();
2623 if (TargetRegisterInfo::isVirtualRegister(ResultReg))
2624 MRI.constrainRegClass(ResultReg, RC);
2625 if (TargetRegisterInfo::isVirtualRegister(SrcReg0))
2626 MRI.constrainRegClass(SrcReg0, RC);
2627 if (TargetRegisterInfo::isVirtualRegister(SrcReg1))
2628 MRI.constrainRegClass(SrcReg1, RC);
2629 if (TargetRegisterInfo::isVirtualRegister(VR))
2630 MRI.constrainRegClass(VR, RC);
2632 MachineInstrBuilder MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc),
2634 .addReg(SrcReg0, getKillRegState(Src0IsKill))
2635 .addReg(SrcReg1, getKillRegState(Src1IsKill))
2638 InsInstrs.push_back(MIB);
2642 /// genAlternativeCodeSequence - when hasPattern() finds a pattern
2643 /// this function generates the instructions that could replace the
2644 /// original code sequence
2645 void AArch64InstrInfo::genAlternativeCodeSequence(
2646 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN Pattern,
2647 SmallVectorImpl<MachineInstr *> &InsInstrs,
2648 SmallVectorImpl<MachineInstr *> &DelInstrs,
2649 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
2650 MachineBasicBlock &MBB = *Root.getParent();
2651 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2652 MachineFunction &MF = *MBB.getParent();
2653 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
2656 const TargetRegisterClass *RC;
2662 case MachineCombinerPattern::MC_MULADDW_OP1:
2663 case MachineCombinerPattern::MC_MULADDX_OP1:
2667 // --- Create(MADD);
2668 if (Pattern == MachineCombinerPattern::MC_MULADDW_OP1) {
2669 Opc = AArch64::MADDWrrr;
2670 RC = &AArch64::GPR32RegClass;
2672 Opc = AArch64::MADDXrrr;
2673 RC = &AArch64::GPR64RegClass;
2675 MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
2677 case MachineCombinerPattern::MC_MULADDW_OP2:
2678 case MachineCombinerPattern::MC_MULADDX_OP2:
2682 // --- Create(MADD);
2683 if (Pattern == MachineCombinerPattern::MC_MULADDW_OP2) {
2684 Opc = AArch64::MADDWrrr;
2685 RC = &AArch64::GPR32RegClass;
2687 Opc = AArch64::MADDXrrr;
2688 RC = &AArch64::GPR64RegClass;
2690 MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
2692 case MachineCombinerPattern::MC_MULADDWI_OP1:
2693 case MachineCombinerPattern::MC_MULADDXI_OP1: {
2696 // ==> ORR V, ZR, Imm
2698 // --- Create(MADD);
2699 const TargetRegisterClass *OrrRC;
2700 unsigned BitSize, OrrOpc, ZeroReg;
2701 if (Pattern == MachineCombinerPattern::MC_MULADDWI_OP1) {
2702 OrrOpc = AArch64::ORRWri;
2703 OrrRC = &AArch64::GPR32spRegClass;
2705 ZeroReg = AArch64::WZR;
2706 Opc = AArch64::MADDWrrr;
2707 RC = &AArch64::GPR32RegClass;
2709 OrrOpc = AArch64::ORRXri;
2710 OrrRC = &AArch64::GPR64spRegClass;
2712 ZeroReg = AArch64::XZR;
2713 Opc = AArch64::MADDXrrr;
2714 RC = &AArch64::GPR64RegClass;
2716 unsigned NewVR = MRI.createVirtualRegister(OrrRC);
2717 uint64_t Imm = Root.getOperand(2).getImm();
2719 if (Root.getOperand(3).isImm()) {
2720 unsigned Val = Root.getOperand(3).getImm();
2723 uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
2725 if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
2726 MachineInstrBuilder MIB1 =
2727 BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
2730 InsInstrs.push_back(MIB1);
2731 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
2732 MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
2736 case MachineCombinerPattern::MC_MULSUBW_OP1:
2737 case MachineCombinerPattern::MC_MULSUBX_OP1: {
2741 // ==> MADD R,A,B,V // = -C + A*B
2742 // --- Create(MADD);
2743 const TargetRegisterClass *SubRC;
2744 unsigned SubOpc, ZeroReg;
2745 if (Pattern == MachineCombinerPattern::MC_MULSUBW_OP1) {
2746 SubOpc = AArch64::SUBWrr;
2747 SubRC = &AArch64::GPR32spRegClass;
2748 ZeroReg = AArch64::WZR;
2749 Opc = AArch64::MADDWrrr;
2750 RC = &AArch64::GPR32RegClass;
2752 SubOpc = AArch64::SUBXrr;
2753 SubRC = &AArch64::GPR64spRegClass;
2754 ZeroReg = AArch64::XZR;
2755 Opc = AArch64::MADDXrrr;
2756 RC = &AArch64::GPR64RegClass;
2758 unsigned NewVR = MRI.createVirtualRegister(SubRC);
2760 MachineInstrBuilder MIB1 =
2761 BuildMI(MF, Root.getDebugLoc(), TII->get(SubOpc), NewVR)
2763 .addOperand(Root.getOperand(2));
2764 InsInstrs.push_back(MIB1);
2765 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
2766 MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
2769 case MachineCombinerPattern::MC_MULSUBW_OP2:
2770 case MachineCombinerPattern::MC_MULSUBX_OP2:
2773 // ==> MSUB R,A,B,C (computes C - A*B)
2774 // --- Create(MSUB);
2775 if (Pattern == MachineCombinerPattern::MC_MULSUBW_OP2) {
2776 Opc = AArch64::MSUBWrrr;
2777 RC = &AArch64::GPR32RegClass;
2779 Opc = AArch64::MSUBXrrr;
2780 RC = &AArch64::GPR64RegClass;
2782 MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
2784 case MachineCombinerPattern::MC_MULSUBWI_OP1:
2785 case MachineCombinerPattern::MC_MULSUBXI_OP1: {
2788 // ==> ORR V, ZR, -Imm
2789 // ==> MADD R,A,B,V // = -Imm + A*B
2790 // --- Create(MADD);
2791 const TargetRegisterClass *OrrRC;
2792 unsigned BitSize, OrrOpc, ZeroReg;
2793 if (Pattern == MachineCombinerPattern::MC_MULSUBWI_OP1) {
2794 OrrOpc = AArch64::ORRWri;
2795 OrrRC = &AArch64::GPR32spRegClass;
2797 ZeroReg = AArch64::WZR;
2798 Opc = AArch64::MADDWrrr;
2799 RC = &AArch64::GPR32RegClass;
2801 OrrOpc = AArch64::ORRXri;
2802 OrrRC = &AArch64::GPR64RegClass;
2804 ZeroReg = AArch64::XZR;
2805 Opc = AArch64::MADDXrrr;
2806 RC = &AArch64::GPR64RegClass;
2808 unsigned NewVR = MRI.createVirtualRegister(OrrRC);
2809 int Imm = Root.getOperand(2).getImm();
2810 if (Root.getOperand(3).isImm()) {
2811 unsigned Val = Root.getOperand(3).getImm();
2814 uint64_t UImm = -Imm << (64 - BitSize) >> (64 - BitSize);
2816 if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
2817 MachineInstrBuilder MIB1 =
2818 BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
2821 InsInstrs.push_back(MIB1);
2822 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
2823 MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
2827 } // end switch (Pattern)
2828 // Record MUL and ADD/SUB for deletion
2829 DelInstrs.push_back(MUL);
2830 DelInstrs.push_back(&Root);