1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64InstrInfo.h"
15 #include "AArch64Subtarget.h"
16 #include "MCTargetDesc/AArch64AddressingModes.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineMemOperand.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/TargetRegistry.h"
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "AArch64GenInstrInfo.inc"
31 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
32 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
33 RI(this, &STI), Subtarget(STI) {}
35 /// GetInstSize - Return the number of bytes of code the specified
36 /// instruction may be. This returns the maximum number of bytes.
37 unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
38 const MachineBasicBlock &MBB = *MI->getParent();
39 const MachineFunction *MF = MBB.getParent();
40 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
42 if (MI->getOpcode() == AArch64::INLINEASM)
43 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
45 const MCInstrDesc &Desc = MI->getDesc();
46 switch (Desc.getOpcode()) {
48 // Anything not explicitly designated otherwise is a nomal 4-byte insn.
50 case TargetOpcode::DBG_VALUE:
51 case TargetOpcode::EH_LABEL:
52 case TargetOpcode::IMPLICIT_DEF:
53 case TargetOpcode::KILL:
57 llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");
60 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
61 SmallVectorImpl<MachineOperand> &Cond) {
62 // Block ends with fall-through condbranch.
63 switch (LastInst->getOpcode()) {
65 llvm_unreachable("Unknown branch instruction?");
67 Target = LastInst->getOperand(1).getMBB();
68 Cond.push_back(LastInst->getOperand(0));
74 Target = LastInst->getOperand(1).getMBB();
75 Cond.push_back(MachineOperand::CreateImm(-1));
76 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
77 Cond.push_back(LastInst->getOperand(0));
83 Target = LastInst->getOperand(2).getMBB();
84 Cond.push_back(MachineOperand::CreateImm(-1));
85 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
86 Cond.push_back(LastInst->getOperand(0));
87 Cond.push_back(LastInst->getOperand(1));
92 bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
93 MachineBasicBlock *&TBB,
94 MachineBasicBlock *&FBB,
95 SmallVectorImpl<MachineOperand> &Cond,
96 bool AllowModify) const {
97 // If the block has no terminators, it just falls into the block after it.
98 MachineBasicBlock::iterator I = MBB.end();
102 while (I->isDebugValue()) {
103 if (I == MBB.begin())
107 if (!isUnpredicatedTerminator(I))
110 // Get the last instruction in the block.
111 MachineInstr *LastInst = I;
113 // If there is only one terminator instruction, process it.
114 unsigned LastOpc = LastInst->getOpcode();
115 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
116 if (isUncondBranchOpcode(LastOpc)) {
117 TBB = LastInst->getOperand(0).getMBB();
120 if (isCondBranchOpcode(LastOpc)) {
121 // Block ends with fall-through condbranch.
122 parseCondBranch(LastInst, TBB, Cond);
125 return true; // Can't handle indirect branch.
128 // Get the instruction before it if it is a terminator.
129 MachineInstr *SecondLastInst = I;
130 unsigned SecondLastOpc = SecondLastInst->getOpcode();
132 // If AllowModify is true and the block ends with two or more unconditional
133 // branches, delete all but the first unconditional branch.
134 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
135 while (isUncondBranchOpcode(SecondLastOpc)) {
136 LastInst->eraseFromParent();
137 LastInst = SecondLastInst;
138 LastOpc = LastInst->getOpcode();
139 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
140 // Return now the only terminator is an unconditional branch.
141 TBB = LastInst->getOperand(0).getMBB();
145 SecondLastOpc = SecondLastInst->getOpcode();
150 // If there are three terminators, we don't know what sort of block this is.
151 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
154 // If the block ends with a B and a Bcc, handle it.
155 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
156 parseCondBranch(SecondLastInst, TBB, Cond);
157 FBB = LastInst->getOperand(0).getMBB();
161 // If the block ends with two unconditional branches, handle it. The second
162 // one is not executed, so remove it.
163 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
164 TBB = SecondLastInst->getOperand(0).getMBB();
167 I->eraseFromParent();
171 // ...likewise if it ends with an indirect branch followed by an unconditional
173 if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
176 I->eraseFromParent();
180 // Otherwise, can't handle this.
184 bool AArch64InstrInfo::ReverseBranchCondition(
185 SmallVectorImpl<MachineOperand> &Cond) const {
186 if (Cond[0].getImm() != -1) {
188 AArch64CC::CondCode CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
189 Cond[0].setImm(AArch64CC::getInvertedCondCode(CC));
191 // Folded compare-and-branch
192 switch (Cond[1].getImm()) {
194 llvm_unreachable("Unknown conditional branch!");
196 Cond[1].setImm(AArch64::CBNZW);
199 Cond[1].setImm(AArch64::CBZW);
202 Cond[1].setImm(AArch64::CBNZX);
205 Cond[1].setImm(AArch64::CBZX);
208 Cond[1].setImm(AArch64::TBNZW);
211 Cond[1].setImm(AArch64::TBZW);
214 Cond[1].setImm(AArch64::TBNZX);
217 Cond[1].setImm(AArch64::TBZX);
225 unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
226 MachineBasicBlock::iterator I = MBB.end();
227 if (I == MBB.begin())
230 while (I->isDebugValue()) {
231 if (I == MBB.begin())
235 if (!isUncondBranchOpcode(I->getOpcode()) &&
236 !isCondBranchOpcode(I->getOpcode()))
239 // Remove the branch.
240 I->eraseFromParent();
244 if (I == MBB.begin())
247 if (!isCondBranchOpcode(I->getOpcode()))
250 // Remove the branch.
251 I->eraseFromParent();
255 void AArch64InstrInfo::instantiateCondBranch(
256 MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB,
257 const SmallVectorImpl<MachineOperand> &Cond) const {
258 if (Cond[0].getImm() != -1) {
260 BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
262 // Folded compare-and-branch
263 const MachineInstrBuilder MIB =
264 BuildMI(&MBB, DL, get(Cond[1].getImm())).addReg(Cond[2].getReg());
266 MIB.addImm(Cond[3].getImm());
271 unsigned AArch64InstrInfo::InsertBranch(
272 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
273 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
274 // Shouldn't be a fall through.
275 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
278 if (Cond.empty()) // Unconditional branch?
279 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB);
281 instantiateCondBranch(MBB, DL, TBB, Cond);
285 // Two-way conditional branch.
286 instantiateCondBranch(MBB, DL, TBB, Cond);
287 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB);
291 // Find the original register that VReg is copied from.
292 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
293 while (TargetRegisterInfo::isVirtualRegister(VReg)) {
294 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
295 if (!DefMI->isFullCopy())
297 VReg = DefMI->getOperand(1).getReg();
302 // Determine if VReg is defined by an instruction that can be folded into a
303 // csel instruction. If so, return the folded opcode, and the replacement
305 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
306 unsigned *NewVReg = nullptr) {
307 VReg = removeCopies(MRI, VReg);
308 if (!TargetRegisterInfo::isVirtualRegister(VReg))
311 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
312 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
314 unsigned SrcOpNum = 0;
315 switch (DefMI->getOpcode()) {
316 case AArch64::ADDSXri:
317 case AArch64::ADDSWri:
318 // if NZCV is used, do not fold.
319 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
321 // fall-through to ADDXri and ADDWri.
322 case AArch64::ADDXri:
323 case AArch64::ADDWri:
324 // add x, 1 -> csinc.
325 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
326 DefMI->getOperand(3).getImm() != 0)
329 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr;
332 case AArch64::ORNXrr:
333 case AArch64::ORNWrr: {
334 // not x -> csinv, represented as orn dst, xzr, src.
335 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
336 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
339 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr;
343 case AArch64::SUBSXrr:
344 case AArch64::SUBSWrr:
345 // if NZCV is used, do not fold.
346 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
348 // fall-through to SUBXrr and SUBWrr.
349 case AArch64::SUBXrr:
350 case AArch64::SUBWrr: {
351 // neg x -> csneg, represented as sub dst, xzr, src.
352 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
353 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
356 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr;
362 assert(Opc && SrcOpNum && "Missing parameters");
365 *NewVReg = DefMI->getOperand(SrcOpNum).getReg();
369 bool AArch64InstrInfo::canInsertSelect(
370 const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond,
371 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles,
372 int &FalseCycles) const {
373 // Check register classes.
374 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
375 const TargetRegisterClass *RC =
376 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
380 // Expanding cbz/tbz requires an extra cycle of latency on the condition.
381 unsigned ExtraCondLat = Cond.size() != 1;
383 // GPRs are handled by csel.
384 // FIXME: Fold in x+1, -x, and ~x when applicable.
385 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
386 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
387 // Single-cycle csel, csinc, csinv, and csneg.
388 CondCycles = 1 + ExtraCondLat;
389 TrueCycles = FalseCycles = 1;
390 if (canFoldIntoCSel(MRI, TrueReg))
392 else if (canFoldIntoCSel(MRI, FalseReg))
397 // Scalar floating point is handled by fcsel.
398 // FIXME: Form fabs, fmin, and fmax when applicable.
399 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
400 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
401 CondCycles = 5 + ExtraCondLat;
402 TrueCycles = FalseCycles = 2;
410 void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
411 MachineBasicBlock::iterator I, DebugLoc DL,
413 const SmallVectorImpl<MachineOperand> &Cond,
414 unsigned TrueReg, unsigned FalseReg) const {
415 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
417 // Parse the condition code, see parseCondBranch() above.
418 AArch64CC::CondCode CC;
419 switch (Cond.size()) {
421 llvm_unreachable("Unknown condition opcode in Cond");
423 CC = AArch64CC::CondCode(Cond[0].getImm());
425 case 3: { // cbz/cbnz
426 // We must insert a compare against 0.
428 switch (Cond[1].getImm()) {
430 llvm_unreachable("Unknown branch opcode in Cond");
448 unsigned SrcReg = Cond[2].getReg();
450 // cmp reg, #0 is actually subs xzr, reg, #0.
451 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
452 BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR)
457 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
458 BuildMI(MBB, I, DL, get(AArch64::SUBSWri), AArch64::WZR)
465 case 4: { // tbz/tbnz
466 // We must insert a tst instruction.
467 switch (Cond[1].getImm()) {
469 llvm_unreachable("Unknown branch opcode in Cond");
479 // cmp reg, #foo is actually ands xzr, reg, #1<<foo.
480 if (Cond[1].getImm() == AArch64::TBZW || Cond[1].getImm() == AArch64::TBNZW)
481 BuildMI(MBB, I, DL, get(AArch64::ANDSWri), AArch64::WZR)
482 .addReg(Cond[2].getReg())
484 AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 32));
486 BuildMI(MBB, I, DL, get(AArch64::ANDSXri), AArch64::XZR)
487 .addReg(Cond[2].getReg())
489 AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 64));
495 const TargetRegisterClass *RC = nullptr;
496 bool TryFold = false;
497 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
498 RC = &AArch64::GPR64RegClass;
499 Opc = AArch64::CSELXr;
501 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
502 RC = &AArch64::GPR32RegClass;
503 Opc = AArch64::CSELWr;
505 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) {
506 RC = &AArch64::FPR64RegClass;
507 Opc = AArch64::FCSELDrrr;
508 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) {
509 RC = &AArch64::FPR32RegClass;
510 Opc = AArch64::FCSELSrrr;
512 assert(RC && "Unsupported regclass");
514 // Try folding simple instructions into the csel.
516 unsigned NewVReg = 0;
517 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg);
519 // The folded opcodes csinc, csinc and csneg apply the operation to
520 // FalseReg, so we need to invert the condition.
521 CC = AArch64CC::getInvertedCondCode(CC);
524 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg);
526 // Fold the operation. Leave any dead instructions for DCE to clean up.
530 // The extends the live range of NewVReg.
531 MRI.clearKillFlags(NewVReg);
535 // Pull all virtual register into the appropriate class.
536 MRI.constrainRegClass(TrueReg, RC);
537 MRI.constrainRegClass(FalseReg, RC);
540 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm(
544 bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
545 unsigned &SrcReg, unsigned &DstReg,
546 unsigned &SubIdx) const {
547 switch (MI.getOpcode()) {
550 case AArch64::SBFMXri: // aka sxtw
551 case AArch64::UBFMXri: // aka uxtw
552 // Check for the 32 -> 64 bit extension case, these instructions can do
554 if (MI.getOperand(2).getImm() != 0 || MI.getOperand(3).getImm() != 31)
556 // This is a signed or unsigned 32 -> 64 bit extension.
557 SrcReg = MI.getOperand(1).getReg();
558 DstReg = MI.getOperand(0).getReg();
559 SubIdx = AArch64::sub_32;
564 /// analyzeCompare - For a comparison instruction, return the source registers
565 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
566 /// Return true if the comparison instruction can be analyzed.
567 bool AArch64InstrInfo::analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
568 unsigned &SrcReg2, int &CmpMask,
569 int &CmpValue) const {
570 switch (MI->getOpcode()) {
573 case AArch64::SUBSWrr:
574 case AArch64::SUBSWrs:
575 case AArch64::SUBSWrx:
576 case AArch64::SUBSXrr:
577 case AArch64::SUBSXrs:
578 case AArch64::SUBSXrx:
579 case AArch64::ADDSWrr:
580 case AArch64::ADDSWrs:
581 case AArch64::ADDSWrx:
582 case AArch64::ADDSXrr:
583 case AArch64::ADDSXrs:
584 case AArch64::ADDSXrx:
585 // Replace SUBSWrr with SUBWrr if NZCV is not used.
586 SrcReg = MI->getOperand(1).getReg();
587 SrcReg2 = MI->getOperand(2).getReg();
591 case AArch64::SUBSWri:
592 case AArch64::ADDSWri:
593 case AArch64::SUBSXri:
594 case AArch64::ADDSXri:
595 SrcReg = MI->getOperand(1).getReg();
598 CmpValue = MI->getOperand(2).getImm();
600 case AArch64::ANDSWri:
601 case AArch64::ANDSXri:
602 // ANDS does not use the same encoding scheme as the others xxxS
604 SrcReg = MI->getOperand(1).getReg();
607 CmpValue = AArch64_AM::decodeLogicalImmediate(
608 MI->getOperand(2).getImm(),
609 MI->getOpcode() == AArch64::ANDSWri ? 32 : 64);
616 static bool UpdateOperandRegClass(MachineInstr *Instr) {
617 MachineBasicBlock *MBB = Instr->getParent();
618 assert(MBB && "Can't get MachineBasicBlock here");
619 MachineFunction *MF = MBB->getParent();
620 assert(MF && "Can't get MachineFunction here");
621 const TargetMachine *TM = &MF->getTarget();
622 const TargetInstrInfo *TII = TM->getInstrInfo();
623 const TargetRegisterInfo *TRI = TM->getRegisterInfo();
624 MachineRegisterInfo *MRI = &MF->getRegInfo();
626 for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx;
628 MachineOperand &MO = Instr->getOperand(OpIdx);
629 const TargetRegisterClass *OpRegCstraints =
630 Instr->getRegClassConstraint(OpIdx, TII, TRI);
632 // If there's no constraint, there's nothing to do.
635 // If the operand is a frame index, there's nothing to do here.
636 // A frame index operand will resolve correctly during PEI.
641 "Operand has register constraints without being a register!");
643 unsigned Reg = MO.getReg();
644 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
645 if (!OpRegCstraints->contains(Reg))
647 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
648 !MRI->constrainRegClass(Reg, OpRegCstraints))
655 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
656 /// comparison into one that sets the zero bit in the flags register.
657 bool AArch64InstrInfo::optimizeCompareInstr(
658 MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
659 int CmpValue, const MachineRegisterInfo *MRI) const {
661 // Replace SUBSWrr with SUBWrr if NZCV is not used.
662 int Cmp_NZCV = CmpInstr->findRegisterDefOperandIdx(AArch64::NZCV, true);
663 if (Cmp_NZCV != -1) {
665 switch (CmpInstr->getOpcode()) {
668 case AArch64::ADDSWrr: NewOpc = AArch64::ADDWrr; break;
669 case AArch64::ADDSWri: NewOpc = AArch64::ADDWri; break;
670 case AArch64::ADDSWrs: NewOpc = AArch64::ADDWrs; break;
671 case AArch64::ADDSWrx: NewOpc = AArch64::ADDWrx; break;
672 case AArch64::ADDSXrr: NewOpc = AArch64::ADDXrr; break;
673 case AArch64::ADDSXri: NewOpc = AArch64::ADDXri; break;
674 case AArch64::ADDSXrs: NewOpc = AArch64::ADDXrs; break;
675 case AArch64::ADDSXrx: NewOpc = AArch64::ADDXrx; break;
676 case AArch64::SUBSWrr: NewOpc = AArch64::SUBWrr; break;
677 case AArch64::SUBSWri: NewOpc = AArch64::SUBWri; break;
678 case AArch64::SUBSWrs: NewOpc = AArch64::SUBWrs; break;
679 case AArch64::SUBSWrx: NewOpc = AArch64::SUBWrx; break;
680 case AArch64::SUBSXrr: NewOpc = AArch64::SUBXrr; break;
681 case AArch64::SUBSXri: NewOpc = AArch64::SUBXri; break;
682 case AArch64::SUBSXrs: NewOpc = AArch64::SUBXrs; break;
683 case AArch64::SUBSXrx: NewOpc = AArch64::SUBXrx; break;
686 const MCInstrDesc &MCID = get(NewOpc);
687 CmpInstr->setDesc(MCID);
688 CmpInstr->RemoveOperand(Cmp_NZCV);
689 bool succeeded = UpdateOperandRegClass(CmpInstr);
691 assert(succeeded && "Some operands reg class are incompatible!");
695 // Continue only if we have a "ri" where immediate is zero.
696 if (CmpValue != 0 || SrcReg2 != 0)
699 // CmpInstr is a Compare instruction if destination register is not used.
700 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
703 // Get the unique definition of SrcReg.
704 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
708 // We iterate backward, starting from the instruction before CmpInstr and
709 // stop when reaching the definition of the source register or done with the
710 // basic block, to check whether NZCV is used or modified in between.
711 MachineBasicBlock::iterator I = CmpInstr, E = MI,
712 B = CmpInstr->getParent()->begin();
714 // Early exit if CmpInstr is at the beginning of the BB.
718 // Check whether the definition of SrcReg is in the same basic block as
719 // Compare. If not, we can't optimize away the Compare.
720 if (MI->getParent() != CmpInstr->getParent())
723 // Check that NZCV isn't set between the comparison instruction and the one we
725 const TargetRegisterInfo *TRI = &getRegisterInfo();
726 for (--I; I != E; --I) {
727 const MachineInstr &Instr = *I;
729 if (Instr.modifiesRegister(AArch64::NZCV, TRI) ||
730 Instr.readsRegister(AArch64::NZCV, TRI))
731 // This instruction modifies or uses NZCV after the one we want to
732 // change. We can't do this transformation.
735 // The 'and' is below the comparison instruction.
739 unsigned NewOpc = MI->getOpcode();
740 switch (MI->getOpcode()) {
743 case AArch64::ADDSWrr:
744 case AArch64::ADDSWri:
745 case AArch64::ADDSXrr:
746 case AArch64::ADDSXri:
747 case AArch64::SUBSWrr:
748 case AArch64::SUBSWri:
749 case AArch64::SUBSXrr:
750 case AArch64::SUBSXri:
752 case AArch64::ADDWrr: NewOpc = AArch64::ADDSWrr; break;
753 case AArch64::ADDWri: NewOpc = AArch64::ADDSWri; break;
754 case AArch64::ADDXrr: NewOpc = AArch64::ADDSXrr; break;
755 case AArch64::ADDXri: NewOpc = AArch64::ADDSXri; break;
756 case AArch64::ADCWr: NewOpc = AArch64::ADCSWr; break;
757 case AArch64::ADCXr: NewOpc = AArch64::ADCSXr; break;
758 case AArch64::SUBWrr: NewOpc = AArch64::SUBSWrr; break;
759 case AArch64::SUBWri: NewOpc = AArch64::SUBSWri; break;
760 case AArch64::SUBXrr: NewOpc = AArch64::SUBSXrr; break;
761 case AArch64::SUBXri: NewOpc = AArch64::SUBSXri; break;
762 case AArch64::SBCWr: NewOpc = AArch64::SBCSWr; break;
763 case AArch64::SBCXr: NewOpc = AArch64::SBCSXr; break;
764 case AArch64::ANDWri: NewOpc = AArch64::ANDSWri; break;
765 case AArch64::ANDXri: NewOpc = AArch64::ANDSXri; break;
768 // Scan forward for the use of NZCV.
769 // When checking against MI: if it's a conditional code requires
770 // checking of V bit, then this is not safe to do.
771 // It is safe to remove CmpInstr if NZCV is redefined or killed.
772 // If we are done with the basic block, we need to check whether NZCV is
775 for (MachineBasicBlock::iterator I = CmpInstr,
776 E = CmpInstr->getParent()->end();
777 !IsSafe && ++I != E;) {
778 const MachineInstr &Instr = *I;
779 for (unsigned IO = 0, EO = Instr.getNumOperands(); !IsSafe && IO != EO;
781 const MachineOperand &MO = Instr.getOperand(IO);
782 if (MO.isRegMask() && MO.clobbersPhysReg(AArch64::NZCV)) {
786 if (!MO.isReg() || MO.getReg() != AArch64::NZCV)
793 // Decode the condition code.
794 unsigned Opc = Instr.getOpcode();
795 AArch64CC::CondCode CC;
800 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 2).getImm();
802 case AArch64::CSINVWr:
803 case AArch64::CSINVXr:
804 case AArch64::CSINCWr:
805 case AArch64::CSINCXr:
806 case AArch64::CSELWr:
807 case AArch64::CSELXr:
808 case AArch64::CSNEGWr:
809 case AArch64::CSNEGXr:
810 case AArch64::FCSELSrrr:
811 case AArch64::FCSELDrrr:
812 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 1).getImm();
816 // It is not safe to remove Compare instruction if Overflow(V) is used.
819 // NZCV can be used multiple times, we should continue.
832 // If NZCV is not killed nor re-defined, we should check whether it is
833 // live-out. If it is live-out, do not optimize.
835 MachineBasicBlock *ParentBlock = CmpInstr->getParent();
836 for (auto *MBB : ParentBlock->successors())
837 if (MBB->isLiveIn(AArch64::NZCV))
841 // Update the instruction to set NZCV.
842 MI->setDesc(get(NewOpc));
843 CmpInstr->eraseFromParent();
844 bool succeeded = UpdateOperandRegClass(MI);
846 assert(succeeded && "Some operands reg class are incompatible!");
847 MI->addRegisterDefined(AArch64::NZCV, TRI);
852 AArch64InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
853 if (MI->getOpcode() != TargetOpcode::LOAD_STACK_GUARD)
856 MachineBasicBlock &MBB = *MI->getParent();
857 DebugLoc DL = MI->getDebugLoc();
858 unsigned Reg = MI->getOperand(0).getReg();
859 const GlobalValue *GV =
860 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
861 const TargetMachine &TM = MBB.getParent()->getTarget();
862 unsigned char OpFlags = Subtarget.ClassifyGlobalReference(GV, TM);
863 const unsigned char MO_NC = AArch64II::MO_NC;
865 if ((OpFlags & AArch64II::MO_GOT) != 0) {
866 BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg)
867 .addGlobalAddress(GV, 0, AArch64II::MO_GOT);
868 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
869 .addReg(Reg, RegState::Kill).addImm(0)
870 .addMemOperand(*MI->memoperands_begin());
871 } else if (TM.getCodeModel() == CodeModel::Large) {
872 BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
873 .addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48);
874 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
875 .addReg(Reg, RegState::Kill)
876 .addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC).addImm(32);
877 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
878 .addReg(Reg, RegState::Kill)
879 .addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC).addImm(16);
880 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
881 .addReg(Reg, RegState::Kill)
882 .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0);
883 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
884 .addReg(Reg, RegState::Kill).addImm(0)
885 .addMemOperand(*MI->memoperands_begin());
887 BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg)
888 .addGlobalAddress(GV, 0, OpFlags | AArch64II::MO_PAGE);
889 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | MO_NC;
890 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
891 .addReg(Reg, RegState::Kill)
892 .addGlobalAddress(GV, 0, LoFlags)
893 .addMemOperand(*MI->memoperands_begin());
901 /// Return true if this is this instruction has a non-zero immediate
902 bool AArch64InstrInfo::hasShiftedReg(const MachineInstr *MI) const {
903 switch (MI->getOpcode()) {
906 case AArch64::ADDSWrs:
907 case AArch64::ADDSXrs:
908 case AArch64::ADDWrs:
909 case AArch64::ADDXrs:
910 case AArch64::ANDSWrs:
911 case AArch64::ANDSXrs:
912 case AArch64::ANDWrs:
913 case AArch64::ANDXrs:
914 case AArch64::BICSWrs:
915 case AArch64::BICSXrs:
916 case AArch64::BICWrs:
917 case AArch64::BICXrs:
918 case AArch64::CRC32Brr:
919 case AArch64::CRC32CBrr:
920 case AArch64::CRC32CHrr:
921 case AArch64::CRC32CWrr:
922 case AArch64::CRC32CXrr:
923 case AArch64::CRC32Hrr:
924 case AArch64::CRC32Wrr:
925 case AArch64::CRC32Xrr:
926 case AArch64::EONWrs:
927 case AArch64::EONXrs:
928 case AArch64::EORWrs:
929 case AArch64::EORXrs:
930 case AArch64::ORNWrs:
931 case AArch64::ORNXrs:
932 case AArch64::ORRWrs:
933 case AArch64::ORRXrs:
934 case AArch64::SUBSWrs:
935 case AArch64::SUBSXrs:
936 case AArch64::SUBWrs:
937 case AArch64::SUBXrs:
938 if (MI->getOperand(3).isImm()) {
939 unsigned val = MI->getOperand(3).getImm();
947 /// Return true if this is this instruction has a non-zero immediate
948 bool AArch64InstrInfo::hasExtendedReg(const MachineInstr *MI) const {
949 switch (MI->getOpcode()) {
952 case AArch64::ADDSWrx:
953 case AArch64::ADDSXrx:
954 case AArch64::ADDSXrx64:
955 case AArch64::ADDWrx:
956 case AArch64::ADDXrx:
957 case AArch64::ADDXrx64:
958 case AArch64::SUBSWrx:
959 case AArch64::SUBSXrx:
960 case AArch64::SUBSXrx64:
961 case AArch64::SUBWrx:
962 case AArch64::SUBXrx:
963 case AArch64::SUBXrx64:
964 if (MI->getOperand(3).isImm()) {
965 unsigned val = MI->getOperand(3).getImm();
974 // Return true if this instruction simply sets its single destination register
975 // to zero. This is equivalent to a register rename of the zero-register.
976 bool AArch64InstrInfo::isGPRZero(const MachineInstr *MI) const {
977 switch (MI->getOpcode()) {
980 case AArch64::MOVZWi:
981 case AArch64::MOVZXi: // movz Rd, #0 (LSL #0)
982 if (MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) {
983 assert(MI->getDesc().getNumOperands() == 3 &&
984 MI->getOperand(2).getImm() == 0 && "invalid MOVZi operands");
988 case AArch64::ANDWri: // and Rd, Rzr, #imm
989 return MI->getOperand(1).getReg() == AArch64::WZR;
990 case AArch64::ANDXri:
991 return MI->getOperand(1).getReg() == AArch64::XZR;
992 case TargetOpcode::COPY:
993 return MI->getOperand(1).getReg() == AArch64::WZR;
998 // Return true if this instruction simply renames a general register without
1000 bool AArch64InstrInfo::isGPRCopy(const MachineInstr *MI) const {
1001 switch (MI->getOpcode()) {
1004 case TargetOpcode::COPY: {
1005 // GPR32 copies will by lowered to ORRXrs
1006 unsigned DstReg = MI->getOperand(0).getReg();
1007 return (AArch64::GPR32RegClass.contains(DstReg) ||
1008 AArch64::GPR64RegClass.contains(DstReg));
1010 case AArch64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0)
1011 if (MI->getOperand(1).getReg() == AArch64::XZR) {
1012 assert(MI->getDesc().getNumOperands() == 4 &&
1013 MI->getOperand(3).getImm() == 0 && "invalid ORRrs operands");
1016 case AArch64::ADDXri: // add Xd, Xn, #0 (LSL #0)
1017 if (MI->getOperand(2).getImm() == 0) {
1018 assert(MI->getDesc().getNumOperands() == 4 &&
1019 MI->getOperand(3).getImm() == 0 && "invalid ADDXri operands");
1026 // Return true if this instruction simply renames a general register without
1028 bool AArch64InstrInfo::isFPRCopy(const MachineInstr *MI) const {
1029 switch (MI->getOpcode()) {
1032 case TargetOpcode::COPY: {
1033 // FPR64 copies will by lowered to ORR.16b
1034 unsigned DstReg = MI->getOperand(0).getReg();
1035 return (AArch64::FPR64RegClass.contains(DstReg) ||
1036 AArch64::FPR128RegClass.contains(DstReg));
1038 case AArch64::ORRv16i8:
1039 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
1040 assert(MI->getDesc().getNumOperands() == 3 && MI->getOperand(0).isReg() &&
1041 "invalid ORRv16i8 operands");
1048 unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1049 int &FrameIndex) const {
1050 switch (MI->getOpcode()) {
1053 case AArch64::LDRWui:
1054 case AArch64::LDRXui:
1055 case AArch64::LDRBui:
1056 case AArch64::LDRHui:
1057 case AArch64::LDRSui:
1058 case AArch64::LDRDui:
1059 case AArch64::LDRQui:
1060 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
1061 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
1062 FrameIndex = MI->getOperand(1).getIndex();
1063 return MI->getOperand(0).getReg();
1071 unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1072 int &FrameIndex) const {
1073 switch (MI->getOpcode()) {
1076 case AArch64::STRWui:
1077 case AArch64::STRXui:
1078 case AArch64::STRBui:
1079 case AArch64::STRHui:
1080 case AArch64::STRSui:
1081 case AArch64::STRDui:
1082 case AArch64::STRQui:
1083 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
1084 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
1085 FrameIndex = MI->getOperand(1).getIndex();
1086 return MI->getOperand(0).getReg();
1093 /// Return true if this is load/store scales or extends its register offset.
1094 /// This refers to scaling a dynamic index as opposed to scaled immediates.
1095 /// MI should be a memory op that allows scaled addressing.
1096 bool AArch64InstrInfo::isScaledAddr(const MachineInstr *MI) const {
1097 switch (MI->getOpcode()) {
1100 case AArch64::LDRBBroW:
1101 case AArch64::LDRBroW:
1102 case AArch64::LDRDroW:
1103 case AArch64::LDRHHroW:
1104 case AArch64::LDRHroW:
1105 case AArch64::LDRQroW:
1106 case AArch64::LDRSBWroW:
1107 case AArch64::LDRSBXroW:
1108 case AArch64::LDRSHWroW:
1109 case AArch64::LDRSHXroW:
1110 case AArch64::LDRSWroW:
1111 case AArch64::LDRSroW:
1112 case AArch64::LDRWroW:
1113 case AArch64::LDRXroW:
1114 case AArch64::STRBBroW:
1115 case AArch64::STRBroW:
1116 case AArch64::STRDroW:
1117 case AArch64::STRHHroW:
1118 case AArch64::STRHroW:
1119 case AArch64::STRQroW:
1120 case AArch64::STRSroW:
1121 case AArch64::STRWroW:
1122 case AArch64::STRXroW:
1123 case AArch64::LDRBBroX:
1124 case AArch64::LDRBroX:
1125 case AArch64::LDRDroX:
1126 case AArch64::LDRHHroX:
1127 case AArch64::LDRHroX:
1128 case AArch64::LDRQroX:
1129 case AArch64::LDRSBWroX:
1130 case AArch64::LDRSBXroX:
1131 case AArch64::LDRSHWroX:
1132 case AArch64::LDRSHXroX:
1133 case AArch64::LDRSWroX:
1134 case AArch64::LDRSroX:
1135 case AArch64::LDRWroX:
1136 case AArch64::LDRXroX:
1137 case AArch64::STRBBroX:
1138 case AArch64::STRBroX:
1139 case AArch64::STRDroX:
1140 case AArch64::STRHHroX:
1141 case AArch64::STRHroX:
1142 case AArch64::STRQroX:
1143 case AArch64::STRSroX:
1144 case AArch64::STRWroX:
1145 case AArch64::STRXroX:
1147 unsigned Val = MI->getOperand(3).getImm();
1148 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val);
1149 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val);
1154 /// Check all MachineMemOperands for a hint to suppress pairing.
1155 bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr *MI) const {
1156 assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
1157 "Too many target MO flags");
1158 for (auto *MM : MI->memoperands()) {
1159 if (MM->getFlags() &
1160 (MOSuppressPair << MachineMemOperand::MOTargetStartBit)) {
1167 /// Set a flag on the first MachineMemOperand to suppress pairing.
1168 void AArch64InstrInfo::suppressLdStPair(MachineInstr *MI) const {
1169 if (MI->memoperands_empty())
1172 assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
1173 "Too many target MO flags");
1174 (*MI->memoperands_begin())
1175 ->setFlags(MOSuppressPair << MachineMemOperand::MOTargetStartBit);
1179 AArch64InstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
1181 const TargetRegisterInfo *TRI) const {
1182 switch (LdSt->getOpcode()) {
1185 case AArch64::STRSui:
1186 case AArch64::STRDui:
1187 case AArch64::STRQui:
1188 case AArch64::STRXui:
1189 case AArch64::STRWui:
1190 case AArch64::LDRSui:
1191 case AArch64::LDRDui:
1192 case AArch64::LDRQui:
1193 case AArch64::LDRXui:
1194 case AArch64::LDRWui:
1195 if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
1197 BaseReg = LdSt->getOperand(1).getReg();
1198 MachineFunction &MF = *LdSt->getParent()->getParent();
1199 unsigned Width = getRegClass(LdSt->getDesc(), 0, TRI, MF)->getSize();
1200 Offset = LdSt->getOperand(2).getImm() * Width;
1205 /// Detect opportunities for ldp/stp formation.
1207 /// Only called for LdSt for which getLdStBaseRegImmOfs returns true.
1208 bool AArch64InstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
1209 MachineInstr *SecondLdSt,
1210 unsigned NumLoads) const {
1211 // Only cluster up to a single pair.
1214 if (FirstLdSt->getOpcode() != SecondLdSt->getOpcode())
1216 // getLdStBaseRegImmOfs guarantees that oper 2 isImm.
1217 unsigned Ofs1 = FirstLdSt->getOperand(2).getImm();
1218 // Allow 6 bits of positive range.
1221 // The caller should already have ordered First/SecondLdSt by offset.
1222 unsigned Ofs2 = SecondLdSt->getOperand(2).getImm();
1223 return Ofs1 + 1 == Ofs2;
1226 bool AArch64InstrInfo::shouldScheduleAdjacent(MachineInstr *First,
1227 MachineInstr *Second) const {
1228 // Cyclone can fuse CMN, CMP followed by Bcc.
1230 // FIXME: B0 can also fuse:
1231 // AND, BIC, ORN, ORR, or EOR (optional S) followed by Bcc or CBZ or CBNZ.
1232 if (Second->getOpcode() != AArch64::Bcc)
1234 switch (First->getOpcode()) {
1237 case AArch64::SUBSWri:
1238 case AArch64::ADDSWri:
1239 case AArch64::ANDSWri:
1240 case AArch64::SUBSXri:
1241 case AArch64::ADDSXri:
1242 case AArch64::ANDSXri:
1247 MachineInstr *AArch64InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1250 const MDNode *MDPtr,
1251 DebugLoc DL) const {
1252 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE))
1253 .addFrameIndex(FrameIx)
1256 .addMetadata(MDPtr);
1260 static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
1261 unsigned Reg, unsigned SubIdx,
1263 const TargetRegisterInfo *TRI) {
1265 return MIB.addReg(Reg, State);
1267 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1268 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1269 return MIB.addReg(Reg, State, SubIdx);
1272 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg,
1274 // We really want the positive remainder mod 32 here, that happens to be
1275 // easily obtainable with a mask.
1276 return ((DestReg - SrcReg) & 0x1f) < NumRegs;
1279 void AArch64InstrInfo::copyPhysRegTuple(
1280 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
1281 unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode,
1282 llvm::ArrayRef<unsigned> Indices) const {
1283 assert(Subtarget.hasNEON() &&
1284 "Unexpected register copy without NEON");
1285 const TargetRegisterInfo *TRI = &getRegisterInfo();
1286 uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
1287 uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg);
1288 unsigned NumRegs = Indices.size();
1290 int SubReg = 0, End = NumRegs, Incr = 1;
1291 if (forwardCopyWillClobberTuple(DestEncoding, SrcEncoding, NumRegs)) {
1292 SubReg = NumRegs - 1;
1297 for (; SubReg != End; SubReg += Incr) {
1298 const MachineInstrBuilder &MIB = BuildMI(MBB, I, DL, get(Opcode));
1299 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
1300 AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI);
1301 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
1305 void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1306 MachineBasicBlock::iterator I, DebugLoc DL,
1307 unsigned DestReg, unsigned SrcReg,
1308 bool KillSrc) const {
1309 if (AArch64::GPR32spRegClass.contains(DestReg) &&
1310 (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
1311 const TargetRegisterInfo *TRI = &getRegisterInfo();
1313 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
1314 // If either operand is WSP, expand to ADD #0.
1315 if (Subtarget.hasZeroCycleRegMove()) {
1316 // Cyclone recognizes "ADD Xd, Xn, #0" as a zero-cycle register move.
1317 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
1318 &AArch64::GPR64spRegClass);
1319 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32,
1320 &AArch64::GPR64spRegClass);
1321 // This instruction is reading and writing X registers. This may upset
1322 // the register scavenger and machine verifier, so we need to indicate
1323 // that we are reading an undefined value from SrcRegX, but a proper
1324 // value from SrcReg.
1325 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestRegX)
1326 .addReg(SrcRegX, RegState::Undef)
1328 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
1329 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1331 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
1332 .addReg(SrcReg, getKillRegState(KillSrc))
1334 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1336 } else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroing()) {
1337 BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg).addImm(0).addImm(
1338 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1340 if (Subtarget.hasZeroCycleRegMove()) {
1341 // Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
1342 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
1343 &AArch64::GPR64spRegClass);
1344 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32,
1345 &AArch64::GPR64spRegClass);
1346 // This instruction is reading and writing X registers. This may upset
1347 // the register scavenger and machine verifier, so we need to indicate
1348 // that we are reading an undefined value from SrcRegX, but a proper
1349 // value from SrcReg.
1350 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestRegX)
1351 .addReg(AArch64::XZR)
1352 .addReg(SrcRegX, RegState::Undef)
1353 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1355 // Otherwise, expand to ORR WZR.
1356 BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
1357 .addReg(AArch64::WZR)
1358 .addReg(SrcReg, getKillRegState(KillSrc));
1364 if (AArch64::GPR64spRegClass.contains(DestReg) &&
1365 (AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) {
1366 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) {
1367 // If either operand is SP, expand to ADD #0.
1368 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
1369 .addReg(SrcReg, getKillRegState(KillSrc))
1371 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1372 } else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroing()) {
1373 BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg).addImm(0).addImm(
1374 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1376 // Otherwise, expand to ORR XZR.
1377 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
1378 .addReg(AArch64::XZR)
1379 .addReg(SrcReg, getKillRegState(KillSrc));
1384 // Copy a DDDD register quad by copying the individual sub-registers.
1385 if (AArch64::DDDDRegClass.contains(DestReg) &&
1386 AArch64::DDDDRegClass.contains(SrcReg)) {
1387 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1,
1388 AArch64::dsub2, AArch64::dsub3 };
1389 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1394 // Copy a DDD register triple by copying the individual sub-registers.
1395 if (AArch64::DDDRegClass.contains(DestReg) &&
1396 AArch64::DDDRegClass.contains(SrcReg)) {
1397 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1,
1399 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1404 // Copy a DD register pair by copying the individual sub-registers.
1405 if (AArch64::DDRegClass.contains(DestReg) &&
1406 AArch64::DDRegClass.contains(SrcReg)) {
1407 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1 };
1408 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1413 // Copy a QQQQ register quad by copying the individual sub-registers.
1414 if (AArch64::QQQQRegClass.contains(DestReg) &&
1415 AArch64::QQQQRegClass.contains(SrcReg)) {
1416 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1,
1417 AArch64::qsub2, AArch64::qsub3 };
1418 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1423 // Copy a QQQ register triple by copying the individual sub-registers.
1424 if (AArch64::QQQRegClass.contains(DestReg) &&
1425 AArch64::QQQRegClass.contains(SrcReg)) {
1426 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1,
1428 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1433 // Copy a QQ register pair by copying the individual sub-registers.
1434 if (AArch64::QQRegClass.contains(DestReg) &&
1435 AArch64::QQRegClass.contains(SrcReg)) {
1436 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1 };
1437 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1442 if (AArch64::FPR128RegClass.contains(DestReg) &&
1443 AArch64::FPR128RegClass.contains(SrcReg)) {
1444 if(Subtarget.hasNEON()) {
1445 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1447 .addReg(SrcReg, getKillRegState(KillSrc));
1449 BuildMI(MBB, I, DL, get(AArch64::STRQpre))
1450 .addReg(AArch64::SP, RegState::Define)
1451 .addReg(SrcReg, getKillRegState(KillSrc))
1452 .addReg(AArch64::SP)
1454 BuildMI(MBB, I, DL, get(AArch64::LDRQpre))
1455 .addReg(AArch64::SP, RegState::Define)
1456 .addReg(DestReg, RegState::Define)
1457 .addReg(AArch64::SP)
1463 if (AArch64::FPR64RegClass.contains(DestReg) &&
1464 AArch64::FPR64RegClass.contains(SrcReg)) {
1465 if(Subtarget.hasNEON()) {
1466 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub,
1467 &AArch64::FPR128RegClass);
1468 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub,
1469 &AArch64::FPR128RegClass);
1470 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1472 .addReg(SrcReg, getKillRegState(KillSrc));
1474 BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
1475 .addReg(SrcReg, getKillRegState(KillSrc));
1480 if (AArch64::FPR32RegClass.contains(DestReg) &&
1481 AArch64::FPR32RegClass.contains(SrcReg)) {
1482 if(Subtarget.hasNEON()) {
1483 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
1484 &AArch64::FPR128RegClass);
1485 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
1486 &AArch64::FPR128RegClass);
1487 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1489 .addReg(SrcReg, getKillRegState(KillSrc));
1491 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1492 .addReg(SrcReg, getKillRegState(KillSrc));
1497 if (AArch64::FPR16RegClass.contains(DestReg) &&
1498 AArch64::FPR16RegClass.contains(SrcReg)) {
1499 if(Subtarget.hasNEON()) {
1500 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
1501 &AArch64::FPR128RegClass);
1502 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
1503 &AArch64::FPR128RegClass);
1504 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1506 .addReg(SrcReg, getKillRegState(KillSrc));
1508 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
1509 &AArch64::FPR32RegClass);
1510 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
1511 &AArch64::FPR32RegClass);
1512 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1513 .addReg(SrcReg, getKillRegState(KillSrc));
1518 if (AArch64::FPR8RegClass.contains(DestReg) &&
1519 AArch64::FPR8RegClass.contains(SrcReg)) {
1520 if(Subtarget.hasNEON()) {
1521 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
1522 &AArch64::FPR128RegClass);
1523 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
1524 &AArch64::FPR128RegClass);
1525 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1527 .addReg(SrcReg, getKillRegState(KillSrc));
1529 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
1530 &AArch64::FPR32RegClass);
1531 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
1532 &AArch64::FPR32RegClass);
1533 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1534 .addReg(SrcReg, getKillRegState(KillSrc));
1539 // Copies between GPR64 and FPR64.
1540 if (AArch64::FPR64RegClass.contains(DestReg) &&
1541 AArch64::GPR64RegClass.contains(SrcReg)) {
1542 BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg)
1543 .addReg(SrcReg, getKillRegState(KillSrc));
1546 if (AArch64::GPR64RegClass.contains(DestReg) &&
1547 AArch64::FPR64RegClass.contains(SrcReg)) {
1548 BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
1549 .addReg(SrcReg, getKillRegState(KillSrc));
1552 // Copies between GPR32 and FPR32.
1553 if (AArch64::FPR32RegClass.contains(DestReg) &&
1554 AArch64::GPR32RegClass.contains(SrcReg)) {
1555 BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg)
1556 .addReg(SrcReg, getKillRegState(KillSrc));
1559 if (AArch64::GPR32RegClass.contains(DestReg) &&
1560 AArch64::FPR32RegClass.contains(SrcReg)) {
1561 BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
1562 .addReg(SrcReg, getKillRegState(KillSrc));
1566 if (DestReg == AArch64::NZCV) {
1567 assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy");
1568 BuildMI(MBB, I, DL, get(AArch64::MSR))
1569 .addImm(AArch64SysReg::NZCV)
1570 .addReg(SrcReg, getKillRegState(KillSrc))
1571 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define);
1575 if (SrcReg == AArch64::NZCV) {
1576 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy");
1577 BuildMI(MBB, I, DL, get(AArch64::MRS))
1579 .addImm(AArch64SysReg::NZCV)
1580 .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
1584 llvm_unreachable("unimplemented reg-to-reg copy");
1587 void AArch64InstrInfo::storeRegToStackSlot(
1588 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
1589 bool isKill, int FI, const TargetRegisterClass *RC,
1590 const TargetRegisterInfo *TRI) const {
1592 if (MBBI != MBB.end())
1593 DL = MBBI->getDebugLoc();
1594 MachineFunction &MF = *MBB.getParent();
1595 MachineFrameInfo &MFI = *MF.getFrameInfo();
1596 unsigned Align = MFI.getObjectAlignment(FI);
1598 MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI));
1599 MachineMemOperand *MMO = MF.getMachineMemOperand(
1600 PtrInfo, MachineMemOperand::MOStore, MFI.getObjectSize(FI), Align);
1603 switch (RC->getSize()) {
1605 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
1606 Opc = AArch64::STRBui;
1609 if (AArch64::FPR16RegClass.hasSubClassEq(RC))
1610 Opc = AArch64::STRHui;
1613 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
1614 Opc = AArch64::STRWui;
1615 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
1616 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
1618 assert(SrcReg != AArch64::WSP);
1619 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
1620 Opc = AArch64::STRSui;
1623 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
1624 Opc = AArch64::STRXui;
1625 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
1626 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
1628 assert(SrcReg != AArch64::SP);
1629 } else if (AArch64::FPR64RegClass.hasSubClassEq(RC))
1630 Opc = AArch64::STRDui;
1633 if (AArch64::FPR128RegClass.hasSubClassEq(RC))
1634 Opc = AArch64::STRQui;
1635 else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
1636 assert(Subtarget.hasNEON() &&
1637 "Unexpected register store without NEON");
1638 Opc = AArch64::ST1Twov1d, Offset = false;
1642 if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
1643 assert(Subtarget.hasNEON() &&
1644 "Unexpected register store without NEON");
1645 Opc = AArch64::ST1Threev1d, Offset = false;
1649 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
1650 assert(Subtarget.hasNEON() &&
1651 "Unexpected register store without NEON");
1652 Opc = AArch64::ST1Fourv1d, Offset = false;
1653 } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
1654 assert(Subtarget.hasNEON() &&
1655 "Unexpected register store without NEON");
1656 Opc = AArch64::ST1Twov2d, Offset = false;
1660 if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
1661 assert(Subtarget.hasNEON() &&
1662 "Unexpected register store without NEON");
1663 Opc = AArch64::ST1Threev2d, Offset = false;
1667 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
1668 assert(Subtarget.hasNEON() &&
1669 "Unexpected register store without NEON");
1670 Opc = AArch64::ST1Fourv2d, Offset = false;
1674 assert(Opc && "Unknown register class");
1676 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
1677 .addReg(SrcReg, getKillRegState(isKill))
1682 MI.addMemOperand(MMO);
1685 void AArch64InstrInfo::loadRegFromStackSlot(
1686 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
1687 int FI, const TargetRegisterClass *RC,
1688 const TargetRegisterInfo *TRI) const {
1690 if (MBBI != MBB.end())
1691 DL = MBBI->getDebugLoc();
1692 MachineFunction &MF = *MBB.getParent();
1693 MachineFrameInfo &MFI = *MF.getFrameInfo();
1694 unsigned Align = MFI.getObjectAlignment(FI);
1695 MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI));
1696 MachineMemOperand *MMO = MF.getMachineMemOperand(
1697 PtrInfo, MachineMemOperand::MOLoad, MFI.getObjectSize(FI), Align);
1701 switch (RC->getSize()) {
1703 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
1704 Opc = AArch64::LDRBui;
1707 if (AArch64::FPR16RegClass.hasSubClassEq(RC))
1708 Opc = AArch64::LDRHui;
1711 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
1712 Opc = AArch64::LDRWui;
1713 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1714 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass);
1716 assert(DestReg != AArch64::WSP);
1717 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
1718 Opc = AArch64::LDRSui;
1721 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
1722 Opc = AArch64::LDRXui;
1723 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1724 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass);
1726 assert(DestReg != AArch64::SP);
1727 } else if (AArch64::FPR64RegClass.hasSubClassEq(RC))
1728 Opc = AArch64::LDRDui;
1731 if (AArch64::FPR128RegClass.hasSubClassEq(RC))
1732 Opc = AArch64::LDRQui;
1733 else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
1734 assert(Subtarget.hasNEON() &&
1735 "Unexpected register load without NEON");
1736 Opc = AArch64::LD1Twov1d, Offset = false;
1740 if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
1741 assert(Subtarget.hasNEON() &&
1742 "Unexpected register load without NEON");
1743 Opc = AArch64::LD1Threev1d, Offset = false;
1747 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
1748 assert(Subtarget.hasNEON() &&
1749 "Unexpected register load without NEON");
1750 Opc = AArch64::LD1Fourv1d, Offset = false;
1751 } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
1752 assert(Subtarget.hasNEON() &&
1753 "Unexpected register load without NEON");
1754 Opc = AArch64::LD1Twov2d, Offset = false;
1758 if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
1759 assert(Subtarget.hasNEON() &&
1760 "Unexpected register load without NEON");
1761 Opc = AArch64::LD1Threev2d, Offset = false;
1765 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
1766 assert(Subtarget.hasNEON() &&
1767 "Unexpected register load without NEON");
1768 Opc = AArch64::LD1Fourv2d, Offset = false;
1772 assert(Opc && "Unknown register class");
1774 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
1775 .addReg(DestReg, getDefRegState(true))
1779 MI.addMemOperand(MMO);
1782 void llvm::emitFrameOffset(MachineBasicBlock &MBB,
1783 MachineBasicBlock::iterator MBBI, DebugLoc DL,
1784 unsigned DestReg, unsigned SrcReg, int Offset,
1785 const TargetInstrInfo *TII,
1786 MachineInstr::MIFlag Flag, bool SetNZCV) {
1787 if (DestReg == SrcReg && Offset == 0)
1790 bool isSub = Offset < 0;
1794 // FIXME: If the offset won't fit in 24-bits, compute the offset into a
1795 // scratch register. If DestReg is a virtual register, use it as the
1796 // scratch register; otherwise, create a new virtual register (to be
1797 // replaced by the scavenger at the end of PEI). That case can be optimized
1798 // slightly if DestReg is SP which is always 16-byte aligned, so the scratch
1799 // register can be loaded with offset%8 and the add/sub can use an extending
1800 // instruction with LSL#3.
1801 // Currently the function handles any offsets but generates a poor sequence
1803 // assert(Offset < (1 << 24) && "unimplemented reg plus immediate");
1807 Opc = isSub ? AArch64::SUBSXri : AArch64::ADDSXri;
1809 Opc = isSub ? AArch64::SUBXri : AArch64::ADDXri;
1810 const unsigned MaxEncoding = 0xfff;
1811 const unsigned ShiftSize = 12;
1812 const unsigned MaxEncodableValue = MaxEncoding << ShiftSize;
1813 while (((unsigned)Offset) >= (1 << ShiftSize)) {
1815 if (((unsigned)Offset) > MaxEncodableValue) {
1816 ThisVal = MaxEncodableValue;
1818 ThisVal = Offset & MaxEncodableValue;
1820 assert((ThisVal >> ShiftSize) <= MaxEncoding &&
1821 "Encoding cannot handle value that big");
1822 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
1824 .addImm(ThisVal >> ShiftSize)
1825 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftSize))
1833 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
1836 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
1841 AArch64InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
1842 const SmallVectorImpl<unsigned> &Ops,
1843 int FrameIndex) const {
1844 // This is a bit of a hack. Consider this instruction:
1846 // %vreg0<def> = COPY %SP; GPR64all:%vreg0
1848 // We explicitly chose GPR64all for the virtual register so such a copy might
1849 // be eliminated by RegisterCoalescer. However, that may not be possible, and
1850 // %vreg0 may even spill. We can't spill %SP, and since it is in the GPR64all
1851 // register class, TargetInstrInfo::foldMemoryOperand() is going to try.
1853 // To prevent that, we are going to constrain the %vreg0 register class here.
1855 // <rdar://problem/11522048>
1858 unsigned DstReg = MI->getOperand(0).getReg();
1859 unsigned SrcReg = MI->getOperand(1).getReg();
1860 if (SrcReg == AArch64::SP &&
1861 TargetRegisterInfo::isVirtualRegister(DstReg)) {
1862 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass);
1865 if (DstReg == AArch64::SP &&
1866 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
1867 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
1876 int llvm::isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
1877 bool *OutUseUnscaledOp,
1878 unsigned *OutUnscaledOp,
1879 int *EmittableOffset) {
1881 bool IsSigned = false;
1882 // The ImmIdx should be changed case by case if it is not 2.
1883 unsigned ImmIdx = 2;
1884 unsigned UnscaledOp = 0;
1885 // Set output values in case of early exit.
1886 if (EmittableOffset)
1887 *EmittableOffset = 0;
1888 if (OutUseUnscaledOp)
1889 *OutUseUnscaledOp = false;
1892 switch (MI.getOpcode()) {
1894 llvm_unreachable("unhandled opcode in rewriteAArch64FrameIndex");
1895 // Vector spills/fills can't take an immediate offset.
1896 case AArch64::LD1Twov2d:
1897 case AArch64::LD1Threev2d:
1898 case AArch64::LD1Fourv2d:
1899 case AArch64::LD1Twov1d:
1900 case AArch64::LD1Threev1d:
1901 case AArch64::LD1Fourv1d:
1902 case AArch64::ST1Twov2d:
1903 case AArch64::ST1Threev2d:
1904 case AArch64::ST1Fourv2d:
1905 case AArch64::ST1Twov1d:
1906 case AArch64::ST1Threev1d:
1907 case AArch64::ST1Fourv1d:
1908 return AArch64FrameOffsetCannotUpdate;
1909 case AArch64::PRFMui:
1911 UnscaledOp = AArch64::PRFUMi;
1913 case AArch64::LDRXui:
1915 UnscaledOp = AArch64::LDURXi;
1917 case AArch64::LDRWui:
1919 UnscaledOp = AArch64::LDURWi;
1921 case AArch64::LDRBui:
1923 UnscaledOp = AArch64::LDURBi;
1925 case AArch64::LDRHui:
1927 UnscaledOp = AArch64::LDURHi;
1929 case AArch64::LDRSui:
1931 UnscaledOp = AArch64::LDURSi;
1933 case AArch64::LDRDui:
1935 UnscaledOp = AArch64::LDURDi;
1937 case AArch64::LDRQui:
1939 UnscaledOp = AArch64::LDURQi;
1941 case AArch64::LDRBBui:
1943 UnscaledOp = AArch64::LDURBBi;
1945 case AArch64::LDRHHui:
1947 UnscaledOp = AArch64::LDURHHi;
1949 case AArch64::LDRSBXui:
1951 UnscaledOp = AArch64::LDURSBXi;
1953 case AArch64::LDRSBWui:
1955 UnscaledOp = AArch64::LDURSBWi;
1957 case AArch64::LDRSHXui:
1959 UnscaledOp = AArch64::LDURSHXi;
1961 case AArch64::LDRSHWui:
1963 UnscaledOp = AArch64::LDURSHWi;
1965 case AArch64::LDRSWui:
1967 UnscaledOp = AArch64::LDURSWi;
1970 case AArch64::STRXui:
1972 UnscaledOp = AArch64::STURXi;
1974 case AArch64::STRWui:
1976 UnscaledOp = AArch64::STURWi;
1978 case AArch64::STRBui:
1980 UnscaledOp = AArch64::STURBi;
1982 case AArch64::STRHui:
1984 UnscaledOp = AArch64::STURHi;
1986 case AArch64::STRSui:
1988 UnscaledOp = AArch64::STURSi;
1990 case AArch64::STRDui:
1992 UnscaledOp = AArch64::STURDi;
1994 case AArch64::STRQui:
1996 UnscaledOp = AArch64::STURQi;
1998 case AArch64::STRBBui:
2000 UnscaledOp = AArch64::STURBBi;
2002 case AArch64::STRHHui:
2004 UnscaledOp = AArch64::STURHHi;
2007 case AArch64::LDPXi:
2008 case AArch64::LDPDi:
2009 case AArch64::STPXi:
2010 case AArch64::STPDi:
2014 case AArch64::LDPQi:
2015 case AArch64::STPQi:
2019 case AArch64::LDPWi:
2020 case AArch64::LDPSi:
2021 case AArch64::STPWi:
2022 case AArch64::STPSi:
2027 case AArch64::LDURXi:
2028 case AArch64::LDURWi:
2029 case AArch64::LDURBi:
2030 case AArch64::LDURHi:
2031 case AArch64::LDURSi:
2032 case AArch64::LDURDi:
2033 case AArch64::LDURQi:
2034 case AArch64::LDURHHi:
2035 case AArch64::LDURBBi:
2036 case AArch64::LDURSBXi:
2037 case AArch64::LDURSBWi:
2038 case AArch64::LDURSHXi:
2039 case AArch64::LDURSHWi:
2040 case AArch64::LDURSWi:
2041 case AArch64::STURXi:
2042 case AArch64::STURWi:
2043 case AArch64::STURBi:
2044 case AArch64::STURHi:
2045 case AArch64::STURSi:
2046 case AArch64::STURDi:
2047 case AArch64::STURQi:
2048 case AArch64::STURBBi:
2049 case AArch64::STURHHi:
2054 Offset += MI.getOperand(ImmIdx).getImm() * Scale;
2056 bool useUnscaledOp = false;
2057 // If the offset doesn't match the scale, we rewrite the instruction to
2058 // use the unscaled instruction instead. Likewise, if we have a negative
2059 // offset (and have an unscaled op to use).
2060 if ((Offset & (Scale - 1)) != 0 || (Offset < 0 && UnscaledOp != 0))
2061 useUnscaledOp = true;
2063 // Use an unscaled addressing mode if the instruction has a negative offset
2064 // (or if the instruction is already using an unscaled addressing mode).
2067 // ldp/stp instructions.
2070 } else if (UnscaledOp == 0 || useUnscaledOp) {
2080 // Attempt to fold address computation.
2081 int MaxOff = (1 << (MaskBits - IsSigned)) - 1;
2082 int MinOff = (IsSigned ? (-MaxOff - 1) : 0);
2083 if (Offset >= MinOff && Offset <= MaxOff) {
2084 if (EmittableOffset)
2085 *EmittableOffset = Offset;
2088 int NewOff = Offset < 0 ? MinOff : MaxOff;
2089 if (EmittableOffset)
2090 *EmittableOffset = NewOff;
2091 Offset = (Offset - NewOff) * Scale;
2093 if (OutUseUnscaledOp)
2094 *OutUseUnscaledOp = useUnscaledOp;
2096 *OutUnscaledOp = UnscaledOp;
2097 return AArch64FrameOffsetCanUpdate |
2098 (Offset == 0 ? AArch64FrameOffsetIsLegal : 0);
2101 bool llvm::rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2102 unsigned FrameReg, int &Offset,
2103 const AArch64InstrInfo *TII) {
2104 unsigned Opcode = MI.getOpcode();
2105 unsigned ImmIdx = FrameRegIdx + 1;
2107 if (Opcode == AArch64::ADDSXri || Opcode == AArch64::ADDXri) {
2108 Offset += MI.getOperand(ImmIdx).getImm();
2109 emitFrameOffset(*MI.getParent(), MI, MI.getDebugLoc(),
2110 MI.getOperand(0).getReg(), FrameReg, Offset, TII,
2111 MachineInstr::NoFlags, (Opcode == AArch64::ADDSXri));
2112 MI.eraseFromParent();
2118 unsigned UnscaledOp;
2120 int Status = isAArch64FrameOffsetLegal(MI, Offset, &UseUnscaledOp,
2121 &UnscaledOp, &NewOffset);
2122 if (Status & AArch64FrameOffsetCanUpdate) {
2123 if (Status & AArch64FrameOffsetIsLegal)
2124 // Replace the FrameIndex with FrameReg.
2125 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2127 MI.setDesc(TII->get(UnscaledOp));
2129 MI.getOperand(ImmIdx).ChangeToImmediate(NewOffset);
2136 void AArch64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
2137 NopInst.setOpcode(AArch64::HINT);
2138 NopInst.addOperand(MCOperand::CreateImm(0));