1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AArch64InstrInfo.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64TargetMachine.h"
18 #include "MCTargetDesc/AArch64MCTargetDesc.h"
19 #include "Utils/AArch64BaseInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
31 #define GET_INSTRINFO_CTOR_DTOR
32 #include "AArch64GenInstrInfo.inc"
36 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
37 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
40 void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
41 MachineBasicBlock::iterator I, DebugLoc DL,
42 unsigned DestReg, unsigned SrcReg,
46 if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) {
47 // E.g. ADD xDst, xsp, #0 (, lsl #0)
48 BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg)
52 } else if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
53 // E.g. ADD wDST, wsp, #0 (, lsl #0)
54 BuildMI(MBB, I, DL, get(AArch64::ADDwwi_lsl0_s), DestReg)
58 } else if (DestReg == AArch64::NZCV) {
59 assert(AArch64::GPR64RegClass.contains(SrcReg));
60 // E.g. MSR NZCV, xDST
61 BuildMI(MBB, I, DL, get(AArch64::MSRix))
62 .addImm(A64SysReg::NZCV)
64 } else if (SrcReg == AArch64::NZCV) {
65 assert(AArch64::GPR64RegClass.contains(DestReg));
66 // E.g. MRS xDST, NZCV
67 BuildMI(MBB, I, DL, get(AArch64::MRSxi), DestReg)
68 .addImm(A64SysReg::NZCV);
69 } else if (AArch64::GPR64RegClass.contains(DestReg)) {
70 if(AArch64::GPR64RegClass.contains(SrcReg)){
71 Opc = AArch64::ORRxxx_lsl;
72 ZeroReg = AArch64::XZR;
74 assert(AArch64::FPR64RegClass.contains(SrcReg));
75 BuildMI(MBB, I, DL, get(AArch64::FMOVxd), DestReg)
79 } else if (AArch64::GPR32RegClass.contains(DestReg)) {
80 if(AArch64::GPR32RegClass.contains(SrcReg)){
81 Opc = AArch64::ORRwww_lsl;
82 ZeroReg = AArch64::WZR;
84 assert(AArch64::FPR32RegClass.contains(SrcReg));
85 BuildMI(MBB, I, DL, get(AArch64::FMOVws), DestReg)
89 } else if (AArch64::FPR32RegClass.contains(DestReg)) {
90 if(AArch64::FPR32RegClass.contains(SrcReg)){
91 BuildMI(MBB, I, DL, get(AArch64::FMOVss), DestReg)
96 assert(AArch64::GPR32RegClass.contains(SrcReg));
97 BuildMI(MBB, I, DL, get(AArch64::FMOVsw), DestReg)
101 } else if (AArch64::FPR64RegClass.contains(DestReg)) {
102 if(AArch64::FPR64RegClass.contains(SrcReg)){
103 BuildMI(MBB, I, DL, get(AArch64::FMOVdd), DestReg)
108 assert(AArch64::GPR64RegClass.contains(SrcReg));
109 BuildMI(MBB, I, DL, get(AArch64::FMOVdx), DestReg)
113 } else if (AArch64::FPR128RegClass.contains(DestReg)) {
114 assert(AArch64::FPR128RegClass.contains(SrcReg));
116 // If NEON is enable, we use ORR to implement this copy.
117 // If NEON isn't available, emit STR and LDR to handle this.
118 if(getSubTarget().hasNEON()) {
119 BuildMI(MBB, I, DL, get(AArch64::ORRvvv_16B), DestReg)
124 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PreInd_STR), AArch64::XSP)
126 .addReg(AArch64::XSP)
127 .addImm(0x1ff & -16);
129 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PostInd_LDR), DestReg)
130 .addReg(AArch64::XSP, RegState::Define)
131 .addReg(AArch64::XSP)
135 } else if (AArch64::FPR16RegClass.contains(DestReg, SrcReg)) {
136 // The copy of two FPR16 registers is implemented by the copy of two FPR32
137 const TargetRegisterInfo *TRI = &getRegisterInfo();
138 unsigned Dst = TRI->getMatchingSuperReg(DestReg, AArch64::sub_16,
139 &AArch64::FPR32RegClass);
140 unsigned Src = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_16,
141 &AArch64::FPR32RegClass);
142 BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)
146 CopyPhysRegTuple(MBB, I, DL, DestReg, SrcReg);
150 // E.g. ORR xDst, xzr, xSrc, lsl #0
151 BuildMI(MBB, I, DL, get(Opc), DestReg)
157 void AArch64InstrInfo::CopyPhysRegTuple(MachineBasicBlock &MBB,
158 MachineBasicBlock::iterator I,
159 DebugLoc DL, unsigned DestReg,
160 unsigned SrcReg) const {
163 if (AArch64::DPairRegClass.contains(DestReg, SrcReg)) {
166 } else if (AArch64::DTripleRegClass.contains(DestReg, SrcReg)) {
169 } else if (AArch64::DQuadRegClass.contains(DestReg, SrcReg)) {
172 } else if (AArch64::QPairRegClass.contains(DestReg, SrcReg)) {
175 } else if (AArch64::QTripleRegClass.contains(DestReg, SrcReg)) {
178 } else if (AArch64::QQuadRegClass.contains(DestReg, SrcReg)) {
182 llvm_unreachable("Unknown register class");
184 unsigned BeginIdx = IsQRegs ? AArch64::qsub_0 : AArch64::dsub_0;
186 const TargetRegisterInfo *TRI = &getRegisterInfo();
187 // Copy register tuples backward when the first Dest reg overlaps
189 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
190 BeginIdx = BeginIdx + (SubRegs - 1);
194 unsigned Opc = IsQRegs ? AArch64::ORRvvv_16B : AArch64::ORRvvv_8B;
195 for (unsigned i = 0; i != SubRegs; ++i) {
196 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
197 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
198 assert(Dst && Src && "Bad sub-register");
199 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
206 /// Does the Opcode represent a conditional branch that we can remove and re-add
207 /// at the end of a basic block?
208 static bool isCondBranch(unsigned Opc) {
209 return Opc == AArch64::Bcc || Opc == AArch64::CBZw || Opc == AArch64::CBZx ||
210 Opc == AArch64::CBNZw || Opc == AArch64::CBNZx ||
211 Opc == AArch64::TBZwii || Opc == AArch64::TBZxii ||
212 Opc == AArch64::TBNZwii || Opc == AArch64::TBNZxii;
215 /// Takes apart a given conditional branch MachineInstr (see isCondBranch),
216 /// setting TBB to the destination basic block and populating the Cond vector
217 /// with data necessary to recreate the conditional branch at a later
218 /// date. First element will be the opcode, and subsequent ones define the
219 /// conditions being branched on in an instruction-specific manner.
220 static void classifyCondBranch(MachineInstr *I, MachineBasicBlock *&TBB,
221 SmallVectorImpl<MachineOperand> &Cond) {
222 switch(I->getOpcode()) {
228 // These instructions just have one predicate operand in position 0 (either
229 // a condition code or a register being compared).
230 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
231 Cond.push_back(I->getOperand(0));
232 TBB = I->getOperand(1).getMBB();
234 case AArch64::TBZwii:
235 case AArch64::TBZxii:
236 case AArch64::TBNZwii:
237 case AArch64::TBNZxii:
238 // These have two predicate operands: a register and a bit position.
239 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
240 Cond.push_back(I->getOperand(0));
241 Cond.push_back(I->getOperand(1));
242 TBB = I->getOperand(2).getMBB();
245 llvm_unreachable("Unknown conditional branch to classify");
251 AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
252 MachineBasicBlock *&FBB,
253 SmallVectorImpl<MachineOperand> &Cond,
254 bool AllowModify) const {
255 // If the block has no terminators, it just falls into the block after it.
256 MachineBasicBlock::iterator I = MBB.end();
257 if (I == MBB.begin())
260 while (I->isDebugValue()) {
261 if (I == MBB.begin())
265 if (!isUnpredicatedTerminator(I))
268 // Get the last instruction in the block.
269 MachineInstr *LastInst = I;
271 // If there is only one terminator instruction, process it.
272 unsigned LastOpc = LastInst->getOpcode();
273 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
274 if (LastOpc == AArch64::Bimm) {
275 TBB = LastInst->getOperand(0).getMBB();
278 if (isCondBranch(LastOpc)) {
279 classifyCondBranch(LastInst, TBB, Cond);
282 return true; // Can't handle indirect branch.
285 // Get the instruction before it if it is a terminator.
286 MachineInstr *SecondLastInst = I;
287 unsigned SecondLastOpc = SecondLastInst->getOpcode();
289 // If AllowModify is true and the block ends with two or more unconditional
290 // branches, delete all but the first unconditional branch.
291 if (AllowModify && LastOpc == AArch64::Bimm) {
292 while (SecondLastOpc == AArch64::Bimm) {
293 LastInst->eraseFromParent();
294 LastInst = SecondLastInst;
295 LastOpc = LastInst->getOpcode();
296 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
297 // Return now the only terminator is an unconditional branch.
298 TBB = LastInst->getOperand(0).getMBB();
302 SecondLastOpc = SecondLastInst->getOpcode();
307 // If there are three terminators, we don't know what sort of block this is.
308 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
311 // If the block ends with a B and a Bcc, handle it.
312 if (LastOpc == AArch64::Bimm) {
313 if (SecondLastOpc == AArch64::Bcc) {
314 TBB = SecondLastInst->getOperand(1).getMBB();
315 Cond.push_back(MachineOperand::CreateImm(AArch64::Bcc));
316 Cond.push_back(SecondLastInst->getOperand(0));
317 FBB = LastInst->getOperand(0).getMBB();
319 } else if (isCondBranch(SecondLastOpc)) {
320 classifyCondBranch(SecondLastInst, TBB, Cond);
321 FBB = LastInst->getOperand(0).getMBB();
326 // If the block ends with two unconditional branches, handle it. The second
327 // one is not executed, so remove it.
328 if (SecondLastOpc == AArch64::Bimm && LastOpc == AArch64::Bimm) {
329 TBB = SecondLastInst->getOperand(0).getMBB();
332 I->eraseFromParent();
336 // Otherwise, can't handle this.
340 bool AArch64InstrInfo::ReverseBranchCondition(
341 SmallVectorImpl<MachineOperand> &Cond) const {
342 switch (Cond[0].getImm()) {
344 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(Cond[1].getImm());
345 CC = A64InvertCondCode(CC);
350 Cond[0].setImm(AArch64::CBNZw);
353 Cond[0].setImm(AArch64::CBNZx);
356 Cond[0].setImm(AArch64::CBZw);
359 Cond[0].setImm(AArch64::CBZx);
361 case AArch64::TBZwii:
362 Cond[0].setImm(AArch64::TBNZwii);
364 case AArch64::TBZxii:
365 Cond[0].setImm(AArch64::TBNZxii);
367 case AArch64::TBNZwii:
368 Cond[0].setImm(AArch64::TBZwii);
370 case AArch64::TBNZxii:
371 Cond[0].setImm(AArch64::TBZxii);
374 llvm_unreachable("Unknown branch type");
380 AArch64InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
381 MachineBasicBlock *FBB,
382 const SmallVectorImpl<MachineOperand> &Cond,
384 if (FBB == 0 && Cond.empty()) {
385 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(TBB);
387 } else if (FBB == 0) {
388 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
389 for (int i = 1, e = Cond.size(); i != e; ++i)
390 MIB.addOperand(Cond[i]);
395 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
396 for (int i = 1, e = Cond.size(); i != e; ++i)
397 MIB.addOperand(Cond[i]);
400 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(FBB);
404 unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
405 MachineBasicBlock::iterator I = MBB.end();
406 if (I == MBB.begin()) return 0;
408 while (I->isDebugValue()) {
409 if (I == MBB.begin())
413 if (I->getOpcode() != AArch64::Bimm && !isCondBranch(I->getOpcode()))
416 // Remove the branch.
417 I->eraseFromParent();
421 if (I == MBB.begin()) return 1;
423 if (!isCondBranch(I->getOpcode()))
426 // Remove the branch.
427 I->eraseFromParent();
432 AArch64InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const {
433 MachineInstr &MI = *MBBI;
434 MachineBasicBlock &MBB = *MI.getParent();
436 unsigned Opcode = MI.getOpcode();
438 case AArch64::TLSDESC_BLRx: {
439 MachineInstr *NewMI =
440 BuildMI(MBB, MBBI, MI.getDebugLoc(), get(AArch64::TLSDESCCALL))
441 .addOperand(MI.getOperand(1));
442 MI.setDesc(get(AArch64::BLRx));
444 llvm::finalizeBundle(MBB, NewMI, *++MBBI);
455 AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
456 MachineBasicBlock::iterator MBBI,
457 unsigned SrcReg, bool isKill,
459 const TargetRegisterClass *RC,
460 const TargetRegisterInfo *TRI) const {
461 DebugLoc DL = MBB.findDebugLoc(MBBI);
462 MachineFunction &MF = *MBB.getParent();
463 MachineFrameInfo &MFI = *MF.getFrameInfo();
464 unsigned Align = MFI.getObjectAlignment(FrameIdx);
466 MachineMemOperand *MMO
467 = MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
468 MachineMemOperand::MOStore,
469 MFI.getObjectSize(FrameIdx),
472 unsigned StoreOp = 0;
473 if (RC->hasType(MVT::i64) || RC->hasType(MVT::i32)) {
474 switch(RC->getSize()) {
475 case 4: StoreOp = AArch64::LS32_STR; break;
476 case 8: StoreOp = AArch64::LS64_STR; break;
478 llvm_unreachable("Unknown size for regclass");
480 } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
481 RC->hasType(MVT::f128)) {
482 switch (RC->getSize()) {
483 case 4: StoreOp = AArch64::LSFP32_STR; break;
484 case 8: StoreOp = AArch64::LSFP64_STR; break;
485 case 16: StoreOp = AArch64::LSFP128_STR; break;
487 llvm_unreachable("Unknown size for regclass");
489 } else { // For a super register class has more than one sub registers
490 if (AArch64::DPairRegClass.hasSubClassEq(RC))
491 StoreOp = AArch64::ST1x2_8B;
492 else if (AArch64::DTripleRegClass.hasSubClassEq(RC))
493 StoreOp = AArch64::ST1x3_8B;
494 else if (AArch64::DQuadRegClass.hasSubClassEq(RC))
495 StoreOp = AArch64::ST1x4_8B;
496 else if (AArch64::QPairRegClass.hasSubClassEq(RC))
497 StoreOp = AArch64::ST1x2_16B;
498 else if (AArch64::QTripleRegClass.hasSubClassEq(RC))
499 StoreOp = AArch64::ST1x3_16B;
500 else if (AArch64::QQuadRegClass.hasSubClassEq(RC))
501 StoreOp = AArch64::ST1x4_16B;
503 llvm_unreachable("Unknown reg class");
505 MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(StoreOp));
506 // Vector store has different operands from other store instructions.
507 NewMI.addFrameIndex(FrameIdx)
508 .addReg(SrcReg, getKillRegState(isKill))
513 MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(StoreOp));
514 NewMI.addReg(SrcReg, getKillRegState(isKill))
515 .addFrameIndex(FrameIdx)
522 AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
523 MachineBasicBlock::iterator MBBI,
524 unsigned DestReg, int FrameIdx,
525 const TargetRegisterClass *RC,
526 const TargetRegisterInfo *TRI) const {
527 DebugLoc DL = MBB.findDebugLoc(MBBI);
528 MachineFunction &MF = *MBB.getParent();
529 MachineFrameInfo &MFI = *MF.getFrameInfo();
530 unsigned Align = MFI.getObjectAlignment(FrameIdx);
532 MachineMemOperand *MMO
533 = MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
534 MachineMemOperand::MOLoad,
535 MFI.getObjectSize(FrameIdx),
539 if (RC->hasType(MVT::i64) || RC->hasType(MVT::i32)) {
540 switch(RC->getSize()) {
541 case 4: LoadOp = AArch64::LS32_LDR; break;
542 case 8: LoadOp = AArch64::LS64_LDR; break;
544 llvm_unreachable("Unknown size for regclass");
546 } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
547 RC->hasType(MVT::f128)) {
548 switch (RC->getSize()) {
549 case 4: LoadOp = AArch64::LSFP32_LDR; break;
550 case 8: LoadOp = AArch64::LSFP64_LDR; break;
551 case 16: LoadOp = AArch64::LSFP128_LDR; break;
553 llvm_unreachable("Unknown size for regclass");
555 } else { // For a super register class has more than one sub registers
556 if (AArch64::DPairRegClass.hasSubClassEq(RC))
557 LoadOp = AArch64::LD1x2_8B;
558 else if (AArch64::DTripleRegClass.hasSubClassEq(RC))
559 LoadOp = AArch64::LD1x3_8B;
560 else if (AArch64::DQuadRegClass.hasSubClassEq(RC))
561 LoadOp = AArch64::LD1x4_8B;
562 else if (AArch64::QPairRegClass.hasSubClassEq(RC))
563 LoadOp = AArch64::LD1x2_16B;
564 else if (AArch64::QTripleRegClass.hasSubClassEq(RC))
565 LoadOp = AArch64::LD1x3_16B;
566 else if (AArch64::QQuadRegClass.hasSubClassEq(RC))
567 LoadOp = AArch64::LD1x4_16B;
569 llvm_unreachable("Unknown reg class");
571 MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(LoadOp), DestReg);
572 // Vector load has different operands from other load instructions.
573 NewMI.addFrameIndex(FrameIdx)
578 MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(LoadOp), DestReg);
579 NewMI.addFrameIndex(FrameIdx)
584 unsigned AArch64InstrInfo::estimateRSStackLimit(MachineFunction &MF) const {
585 unsigned Limit = (1 << 16) - 1;
586 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
587 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
589 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
590 if (!I->getOperand(i).isFI()) continue;
592 // When using ADDxxi_lsl0_s to get the address of a stack object, 0xfff
593 // is the largest offset guaranteed to fit in the immediate offset.
594 if (I->getOpcode() == AArch64::ADDxxi_lsl0_s) {
595 Limit = std::min(Limit, 0xfffu);
599 int AccessScale, MinOffset, MaxOffset;
600 getAddressConstraints(*I, AccessScale, MinOffset, MaxOffset);
601 Limit = std::min(Limit, static_cast<unsigned>(MaxOffset));
603 break; // At most one FI per instruction
610 void AArch64InstrInfo::getAddressConstraints(const MachineInstr &MI,
611 int &AccessScale, int &MinOffset,
612 int &MaxOffset) const {
613 switch (MI.getOpcode()) {
614 default: llvm_unreachable("Unkown load/store kind");
615 case TargetOpcode::DBG_VALUE:
620 case AArch64::LS8_LDR: case AArch64::LS8_STR:
621 case AArch64::LSFP8_LDR: case AArch64::LSFP8_STR:
622 case AArch64::LDRSBw:
623 case AArch64::LDRSBx:
628 case AArch64::LS16_LDR: case AArch64::LS16_STR:
629 case AArch64::LSFP16_LDR: case AArch64::LSFP16_STR:
630 case AArch64::LDRSHw:
631 case AArch64::LDRSHx:
634 MaxOffset = 0xfff * AccessScale;
636 case AArch64::LS32_LDR: case AArch64::LS32_STR:
637 case AArch64::LSFP32_LDR: case AArch64::LSFP32_STR:
638 case AArch64::LDRSWx:
639 case AArch64::LDPSWx:
642 MaxOffset = 0xfff * AccessScale;
644 case AArch64::LS64_LDR: case AArch64::LS64_STR:
645 case AArch64::LSFP64_LDR: case AArch64::LSFP64_STR:
649 MaxOffset = 0xfff * AccessScale;
651 case AArch64::LSFP128_LDR: case AArch64::LSFP128_STR:
654 MaxOffset = 0xfff * AccessScale;
656 case AArch64::LSPair32_LDR: case AArch64::LSPair32_STR:
657 case AArch64::LSFPPair32_LDR: case AArch64::LSFPPair32_STR:
659 MinOffset = -0x40 * AccessScale;
660 MaxOffset = 0x3f * AccessScale;
662 case AArch64::LSPair64_LDR: case AArch64::LSPair64_STR:
663 case AArch64::LSFPPair64_LDR: case AArch64::LSFPPair64_STR:
665 MinOffset = -0x40 * AccessScale;
666 MaxOffset = 0x3f * AccessScale;
668 case AArch64::LSFPPair128_LDR: case AArch64::LSFPPair128_STR:
670 MinOffset = -0x40 * AccessScale;
671 MaxOffset = 0x3f * AccessScale;
673 case AArch64::LD1x2_8B: case AArch64::ST1x2_8B:
676 MaxOffset = 0xfff * AccessScale;
678 case AArch64::LD1x3_8B: case AArch64::ST1x3_8B:
681 MaxOffset = 0xfff * AccessScale;
683 case AArch64::LD1x4_8B: case AArch64::ST1x4_8B:
684 case AArch64::LD1x2_16B: case AArch64::ST1x2_16B:
687 MaxOffset = 0xfff * AccessScale;
689 case AArch64::LD1x3_16B: case AArch64::ST1x3_16B:
692 MaxOffset = 0xfff * AccessScale;
694 case AArch64::LD1x4_16B: case AArch64::ST1x4_16B:
697 MaxOffset = 0xfff * AccessScale;
702 unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
703 const MCInstrDesc &MCID = MI.getDesc();
704 const MachineBasicBlock &MBB = *MI.getParent();
705 const MachineFunction &MF = *MBB.getParent();
706 const MCAsmInfo &MAI = *MF.getTarget().getMCAsmInfo();
709 return MCID.getSize();
711 if (MI.getOpcode() == AArch64::INLINEASM)
712 return getInlineAsmLength(MI.getOperand(0).getSymbolName(), MAI);
717 switch (MI.getOpcode()) {
718 case TargetOpcode::BUNDLE:
719 return getInstBundleLength(MI);
720 case TargetOpcode::IMPLICIT_DEF:
721 case TargetOpcode::KILL:
722 case TargetOpcode::PROLOG_LABEL:
723 case TargetOpcode::EH_LABEL:
724 case TargetOpcode::DBG_VALUE:
726 case AArch64::TLSDESCCALL:
729 llvm_unreachable("Unknown instruction class");
733 unsigned AArch64InstrInfo::getInstBundleLength(const MachineInstr &MI) const {
735 MachineBasicBlock::const_instr_iterator I = MI;
736 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
737 while (++I != E && I->isInsideBundle()) {
738 assert(!I->isBundle() && "No nested bundle!");
739 Size += getInstSizeInBytes(*I);
744 bool llvm::rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
745 unsigned FrameReg, int &Offset,
746 const AArch64InstrInfo &TII) {
747 MachineBasicBlock &MBB = *MI.getParent();
748 MachineFunction &MF = *MBB.getParent();
749 MachineFrameInfo &MFI = *MF.getFrameInfo();
751 MFI.getObjectOffset(FrameRegIdx);
752 llvm_unreachable("Unimplemented rewriteFrameIndex");
755 void llvm::emitRegUpdate(MachineBasicBlock &MBB,
756 MachineBasicBlock::iterator MBBI,
757 DebugLoc dl, const TargetInstrInfo &TII,
758 unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
759 int64_t NumBytes, MachineInstr::MIFlag MIFlags) {
760 if (NumBytes == 0 && DstReg == SrcReg)
762 else if (abs64(NumBytes) & ~0xffffff) {
763 // Generically, we have to materialize the offset into a temporary register
764 // and subtract it. There are a couple of ways this could be done, for now
765 // we'll use a movz/movk or movn/movk sequence.
766 uint64_t Bits = static_cast<uint64_t>(abs64(NumBytes));
767 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVZxii), ScratchReg)
768 .addImm(0xffff & Bits).addImm(0)
769 .setMIFlags(MIFlags);
773 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
775 .addImm(0xffff & Bits).addImm(1)
776 .setMIFlags(MIFlags);
781 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
783 .addImm(0xffff & Bits).addImm(2)
784 .setMIFlags(MIFlags);
789 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
791 .addImm(0xffff & Bits).addImm(3)
792 .setMIFlags(MIFlags);
795 // ADD DST, SRC, xTMP (, lsl #0)
796 unsigned AddOp = NumBytes > 0 ? AArch64::ADDxxx_uxtx : AArch64::SUBxxx_uxtx;
797 BuildMI(MBB, MBBI, dl, TII.get(AddOp), DstReg)
798 .addReg(SrcReg, RegState::Kill)
799 .addReg(ScratchReg, RegState::Kill)
805 // Now we know that the adjustment can be done in at most two add/sub
806 // (immediate) instructions, which is always more efficient than a
807 // literal-pool load, or even a hypothetical movz/movk/add sequence
809 // Decide whether we're doing addition or subtraction
810 unsigned LowOp, HighOp;
812 LowOp = AArch64::ADDxxi_lsl0_s;
813 HighOp = AArch64::ADDxxi_lsl12_s;
815 LowOp = AArch64::SUBxxi_lsl0_s;
816 HighOp = AArch64::SUBxxi_lsl12_s;
817 NumBytes = abs64(NumBytes);
820 // If we're here, at the very least a move needs to be produced, which just
821 // happens to be materializable by an ADD.
822 if ((NumBytes & 0xfff) || NumBytes == 0) {
823 BuildMI(MBB, MBBI, dl, TII.get(LowOp), DstReg)
824 .addReg(SrcReg, RegState::Kill)
825 .addImm(NumBytes & 0xfff)
828 // Next update should use the register we've just defined.
832 if (NumBytes & 0xfff000) {
833 BuildMI(MBB, MBBI, dl, TII.get(HighOp), DstReg)
834 .addReg(SrcReg, RegState::Kill)
835 .addImm(NumBytes >> 12)
840 void llvm::emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
841 DebugLoc dl, const TargetInstrInfo &TII,
842 unsigned ScratchReg, int64_t NumBytes,
843 MachineInstr::MIFlag MIFlags) {
844 emitRegUpdate(MBB, MI, dl, TII, AArch64::XSP, AArch64::XSP, AArch64::X16,
850 struct LDTLSCleanup : public MachineFunctionPass {
852 LDTLSCleanup() : MachineFunctionPass(ID) {}
854 virtual bool runOnMachineFunction(MachineFunction &MF) {
855 AArch64MachineFunctionInfo* MFI
856 = MF.getInfo<AArch64MachineFunctionInfo>();
857 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
858 // No point folding accesses if there isn't at least two.
862 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
863 return VisitNode(DT->getRootNode(), 0);
866 // Visit the dominator subtree rooted at Node in pre-order.
867 // If TLSBaseAddrReg is non-null, then use that to replace any
868 // TLS_base_addr instructions. Otherwise, create the register
869 // when the first such instruction is seen, and then use it
870 // as we encounter more instructions.
871 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
872 MachineBasicBlock *BB = Node->getBlock();
873 bool Changed = false;
875 // Traverse the current block.
876 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
878 switch (I->getOpcode()) {
879 case AArch64::TLSDESC_BLRx:
880 // Make sure it's a local dynamic access.
881 if (!I->getOperand(1).isSymbol() ||
882 strcmp(I->getOperand(1).getSymbolName(), "_TLS_MODULE_BASE_"))
886 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
888 I = SetRegister(I, &TLSBaseAddrReg);
896 // Visit the children of this block in the dominator tree.
897 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
899 Changed |= VisitNode(*I, TLSBaseAddrReg);
905 // Replace the TLS_base_addr instruction I with a copy from
906 // TLSBaseAddrReg, returning the new instruction.
907 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
908 unsigned TLSBaseAddrReg) {
909 MachineFunction *MF = I->getParent()->getParent();
910 const AArch64TargetMachine *TM =
911 static_cast<const AArch64TargetMachine *>(&MF->getTarget());
912 const AArch64InstrInfo *TII = TM->getInstrInfo();
914 // Insert a Copy from TLSBaseAddrReg to x0, which is where the rest of the
915 // code sequence assumes the address will be.
916 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
917 TII->get(TargetOpcode::COPY),
919 .addReg(TLSBaseAddrReg);
921 // Erase the TLS_base_addr instruction.
922 I->eraseFromParent();
927 // Create a virtal register in *TLSBaseAddrReg, and populate it by
928 // inserting a copy instruction after I. Returns the new instruction.
929 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
930 MachineFunction *MF = I->getParent()->getParent();
931 const AArch64TargetMachine *TM =
932 static_cast<const AArch64TargetMachine *>(&MF->getTarget());
933 const AArch64InstrInfo *TII = TM->getInstrInfo();
935 // Create a virtual register for the TLS base address.
936 MachineRegisterInfo &RegInfo = MF->getRegInfo();
937 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
939 // Insert a copy from X0 to TLSBaseAddrReg for later.
940 MachineInstr *Next = I->getNextNode();
941 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
942 TII->get(TargetOpcode::COPY),
944 .addReg(AArch64::X0);
949 virtual const char *getPassName() const {
950 return "Local Dynamic TLS Access Clean-up";
953 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
954 AU.setPreservesCFG();
955 AU.addRequired<MachineDominatorTree>();
956 MachineFunctionPass::getAnalysisUsage(AU);
961 char LDTLSCleanup::ID = 0;
963 llvm::createAArch64CleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }