1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AArch64InstrInfo.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64TargetMachine.h"
18 #include "MCTargetDesc/AArch64MCTargetDesc.h"
19 #include "Utils/AArch64BaseInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
32 #define GET_INSTRINFO_CTOR
33 #include "AArch64GenInstrInfo.inc"
37 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
38 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
39 RI(*this, STI), Subtarget(STI) {}
41 void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator I, DebugLoc DL,
43 unsigned DestReg, unsigned SrcReg,
47 if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) {
48 // E.g. ADD xDst, xsp, #0 (, lsl #0)
49 BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg)
53 } else if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
54 // E.g. ADD wDST, wsp, #0 (, lsl #0)
55 BuildMI(MBB, I, DL, get(AArch64::ADDwwi_lsl0_s), DestReg)
59 } else if (DestReg == AArch64::NZCV) {
60 assert(AArch64::GPR64RegClass.contains(SrcReg));
61 // E.g. MSR NZCV, xDST
62 BuildMI(MBB, I, DL, get(AArch64::MSRix))
63 .addImm(A64SysReg::NZCV)
65 } else if (SrcReg == AArch64::NZCV) {
66 assert(AArch64::GPR64RegClass.contains(DestReg));
67 // E.g. MRS xDST, NZCV
68 BuildMI(MBB, I, DL, get(AArch64::MRSxi), DestReg)
69 .addImm(A64SysReg::NZCV);
70 } else if (AArch64::GPR64RegClass.contains(DestReg)) {
71 assert(AArch64::GPR64RegClass.contains(SrcReg));
72 Opc = AArch64::ORRxxx_lsl;
73 ZeroReg = AArch64::XZR;
74 } else if (AArch64::GPR32RegClass.contains(DestReg)) {
75 assert(AArch64::GPR32RegClass.contains(SrcReg));
76 Opc = AArch64::ORRwww_lsl;
77 ZeroReg = AArch64::WZR;
78 } else if (AArch64::FPR32RegClass.contains(DestReg)) {
79 assert(AArch64::FPR32RegClass.contains(SrcReg));
80 BuildMI(MBB, I, DL, get(AArch64::FMOVss), DestReg)
83 } else if (AArch64::FPR64RegClass.contains(DestReg)) {
84 assert(AArch64::FPR64RegClass.contains(SrcReg));
85 BuildMI(MBB, I, DL, get(AArch64::FMOVdd), DestReg)
88 } else if (AArch64::FPR128RegClass.contains(DestReg)) {
89 assert(AArch64::FPR128RegClass.contains(SrcReg));
91 // FIXME: there's no good way to do this, at least without NEON:
92 // + There's no single move instruction for q-registers
93 // + We can't create a spill slot and use normal STR/LDR because stack
94 // allocation has already happened
95 // + We can't go via X-registers with FMOV because register allocation has
97 // This may not be efficient, but at least it works.
98 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PreInd_STR), AArch64::XSP)
100 .addReg(AArch64::XSP)
101 .addImm(0x1ff & -16);
103 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PostInd_LDR), DestReg)
104 .addReg(AArch64::XSP, RegState::Define)
105 .addReg(AArch64::XSP)
109 llvm_unreachable("Unknown register class in copyPhysReg");
112 // E.g. ORR xDst, xzr, xSrc, lsl #0
113 BuildMI(MBB, I, DL, get(Opc), DestReg)
120 AArch64InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
121 uint64_t Offset, const MDNode *MDPtr,
123 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE))
124 .addFrameIndex(FrameIx).addImm(0)
130 /// Does the Opcode represent a conditional branch that we can remove and re-add
131 /// at the end of a basic block?
132 static bool isCondBranch(unsigned Opc) {
133 return Opc == AArch64::Bcc || Opc == AArch64::CBZw || Opc == AArch64::CBZx ||
134 Opc == AArch64::CBNZw || Opc == AArch64::CBNZx ||
135 Opc == AArch64::TBZwii || Opc == AArch64::TBZxii ||
136 Opc == AArch64::TBNZwii || Opc == AArch64::TBNZxii;
139 /// Takes apart a given conditional branch MachineInstr (see isCondBranch),
140 /// setting TBB to the destination basic block and populating the Cond vector
141 /// with data necessary to recreate the conditional branch at a later
142 /// date. First element will be the opcode, and subsequent ones define the
143 /// conditions being branched on in an instruction-specific manner.
144 static void classifyCondBranch(MachineInstr *I, MachineBasicBlock *&TBB,
145 SmallVectorImpl<MachineOperand> &Cond) {
146 switch(I->getOpcode()) {
152 // These instructions just have one predicate operand in position 0 (either
153 // a condition code or a register being compared).
154 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
155 Cond.push_back(I->getOperand(0));
156 TBB = I->getOperand(1).getMBB();
158 case AArch64::TBZwii:
159 case AArch64::TBZxii:
160 case AArch64::TBNZwii:
161 case AArch64::TBNZxii:
162 // These have two predicate operands: a register and a bit position.
163 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
164 Cond.push_back(I->getOperand(0));
165 Cond.push_back(I->getOperand(1));
166 TBB = I->getOperand(2).getMBB();
169 llvm_unreachable("Unknown conditional branch to classify");
175 AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
176 MachineBasicBlock *&FBB,
177 SmallVectorImpl<MachineOperand> &Cond,
178 bool AllowModify) const {
179 // If the block has no terminators, it just falls into the block after it.
180 MachineBasicBlock::iterator I = MBB.end();
181 if (I == MBB.begin())
184 while (I->isDebugValue()) {
185 if (I == MBB.begin())
189 if (!isUnpredicatedTerminator(I))
192 // Get the last instruction in the block.
193 MachineInstr *LastInst = I;
195 // If there is only one terminator instruction, process it.
196 unsigned LastOpc = LastInst->getOpcode();
197 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
198 if (LastOpc == AArch64::Bimm) {
199 TBB = LastInst->getOperand(0).getMBB();
202 if (isCondBranch(LastOpc)) {
203 classifyCondBranch(LastInst, TBB, Cond);
206 return true; // Can't handle indirect branch.
209 // Get the instruction before it if it is a terminator.
210 MachineInstr *SecondLastInst = I;
211 unsigned SecondLastOpc = SecondLastInst->getOpcode();
213 // If AllowModify is true and the block ends with two or more unconditional
214 // branches, delete all but the first unconditional branch.
215 if (AllowModify && LastOpc == AArch64::Bimm) {
216 while (SecondLastOpc == AArch64::Bimm) {
217 LastInst->eraseFromParent();
218 LastInst = SecondLastInst;
219 LastOpc = LastInst->getOpcode();
220 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
221 // Return now the only terminator is an unconditional branch.
222 TBB = LastInst->getOperand(0).getMBB();
226 SecondLastOpc = SecondLastInst->getOpcode();
231 // If there are three terminators, we don't know what sort of block this is.
232 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
235 // If the block ends with a B and a Bcc, handle it.
236 if (LastOpc == AArch64::Bimm) {
237 if (SecondLastOpc == AArch64::Bcc) {
238 TBB = SecondLastInst->getOperand(1).getMBB();
239 Cond.push_back(MachineOperand::CreateImm(AArch64::Bcc));
240 Cond.push_back(SecondLastInst->getOperand(0));
241 FBB = LastInst->getOperand(0).getMBB();
243 } else if (isCondBranch(SecondLastOpc)) {
244 classifyCondBranch(SecondLastInst, TBB, Cond);
245 FBB = LastInst->getOperand(0).getMBB();
250 // If the block ends with two unconditional branches, handle it. The second
251 // one is not executed, so remove it.
252 if (SecondLastOpc == AArch64::Bimm && LastOpc == AArch64::Bimm) {
253 TBB = SecondLastInst->getOperand(0).getMBB();
256 I->eraseFromParent();
260 // Otherwise, can't handle this.
264 bool AArch64InstrInfo::ReverseBranchCondition(
265 SmallVectorImpl<MachineOperand> &Cond) const {
266 switch (Cond[0].getImm()) {
268 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(Cond[1].getImm());
269 CC = A64InvertCondCode(CC);
274 Cond[0].setImm(AArch64::CBNZw);
277 Cond[0].setImm(AArch64::CBNZx);
280 Cond[0].setImm(AArch64::CBZw);
283 Cond[0].setImm(AArch64::CBZx);
285 case AArch64::TBZwii:
286 Cond[0].setImm(AArch64::TBNZwii);
288 case AArch64::TBZxii:
289 Cond[0].setImm(AArch64::TBNZxii);
291 case AArch64::TBNZwii:
292 Cond[0].setImm(AArch64::TBZwii);
294 case AArch64::TBNZxii:
295 Cond[0].setImm(AArch64::TBZxii);
298 llvm_unreachable("Unknown branch type");
304 AArch64InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
305 MachineBasicBlock *FBB,
306 const SmallVectorImpl<MachineOperand> &Cond,
308 if (FBB == 0 && Cond.empty()) {
309 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(TBB);
311 } else if (FBB == 0) {
312 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
313 for (int i = 1, e = Cond.size(); i != e; ++i)
314 MIB.addOperand(Cond[i]);
319 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
320 for (int i = 1, e = Cond.size(); i != e; ++i)
321 MIB.addOperand(Cond[i]);
324 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(FBB);
328 unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
329 MachineBasicBlock::iterator I = MBB.end();
330 if (I == MBB.begin()) return 0;
332 while (I->isDebugValue()) {
333 if (I == MBB.begin())
337 if (I->getOpcode() != AArch64::Bimm && !isCondBranch(I->getOpcode()))
340 // Remove the branch.
341 I->eraseFromParent();
345 if (I == MBB.begin()) return 1;
347 if (!isCondBranch(I->getOpcode()))
350 // Remove the branch.
351 I->eraseFromParent();
356 AArch64InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const {
357 MachineInstr &MI = *MBBI;
358 MachineBasicBlock &MBB = *MI.getParent();
360 unsigned Opcode = MI.getOpcode();
362 case AArch64::TLSDESC_BLRx: {
363 MachineInstr *NewMI =
364 BuildMI(MBB, MBBI, MI.getDebugLoc(), get(AArch64::TLSDESCCALL))
365 .addOperand(MI.getOperand(1));
366 MI.setDesc(get(AArch64::BLRx));
368 llvm::finalizeBundle(MBB, NewMI, *++MBBI);
379 AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
380 MachineBasicBlock::iterator MBBI,
381 unsigned SrcReg, bool isKill,
383 const TargetRegisterClass *RC,
384 const TargetRegisterInfo *TRI) const {
385 DebugLoc DL = MBB.findDebugLoc(MBBI);
386 MachineFunction &MF = *MBB.getParent();
387 MachineFrameInfo &MFI = *MF.getFrameInfo();
388 unsigned Align = MFI.getObjectAlignment(FrameIdx);
390 MachineMemOperand *MMO
391 = MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
392 MachineMemOperand::MOStore,
393 MFI.getObjectSize(FrameIdx),
396 unsigned StoreOp = 0;
397 if (RC->hasType(MVT::i64) || RC->hasType(MVT::i32)) {
398 switch(RC->getSize()) {
399 case 4: StoreOp = AArch64::LS32_STR; break;
400 case 8: StoreOp = AArch64::LS64_STR; break;
402 llvm_unreachable("Unknown size for regclass");
405 assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
406 RC->hasType(MVT::f128))
407 && "Expected integer or floating type for store");
408 switch (RC->getSize()) {
409 case 4: StoreOp = AArch64::LSFP32_STR; break;
410 case 8: StoreOp = AArch64::LSFP64_STR; break;
411 case 16: StoreOp = AArch64::LSFP128_STR; break;
413 llvm_unreachable("Unknown size for regclass");
417 MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(StoreOp));
418 NewMI.addReg(SrcReg, getKillRegState(isKill))
419 .addFrameIndex(FrameIdx)
426 AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
427 MachineBasicBlock::iterator MBBI,
428 unsigned DestReg, int FrameIdx,
429 const TargetRegisterClass *RC,
430 const TargetRegisterInfo *TRI) const {
431 DebugLoc DL = MBB.findDebugLoc(MBBI);
432 MachineFunction &MF = *MBB.getParent();
433 MachineFrameInfo &MFI = *MF.getFrameInfo();
434 unsigned Align = MFI.getObjectAlignment(FrameIdx);
436 MachineMemOperand *MMO
437 = MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
438 MachineMemOperand::MOLoad,
439 MFI.getObjectSize(FrameIdx),
443 if (RC->hasType(MVT::i64) || RC->hasType(MVT::i32)) {
444 switch(RC->getSize()) {
445 case 4: LoadOp = AArch64::LS32_LDR; break;
446 case 8: LoadOp = AArch64::LS64_LDR; break;
448 llvm_unreachable("Unknown size for regclass");
451 assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64)
452 || RC->hasType(MVT::f128))
453 && "Expected integer or floating type for store");
454 switch (RC->getSize()) {
455 case 4: LoadOp = AArch64::LSFP32_LDR; break;
456 case 8: LoadOp = AArch64::LSFP64_LDR; break;
457 case 16: LoadOp = AArch64::LSFP128_LDR; break;
459 llvm_unreachable("Unknown size for regclass");
463 MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(LoadOp), DestReg);
464 NewMI.addFrameIndex(FrameIdx)
469 unsigned AArch64InstrInfo::estimateRSStackLimit(MachineFunction &MF) const {
470 unsigned Limit = (1 << 16) - 1;
471 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
472 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
474 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
475 if (!I->getOperand(i).isFI()) continue;
477 // When using ADDxxi_lsl0_s to get the address of a stack object, 0xfff
478 // is the largest offset guaranteed to fit in the immediate offset.
479 if (I->getOpcode() == AArch64::ADDxxi_lsl0_s) {
480 Limit = std::min(Limit, 0xfffu);
484 int AccessScale, MinOffset, MaxOffset;
485 getAddressConstraints(*I, AccessScale, MinOffset, MaxOffset);
486 Limit = std::min(Limit, static_cast<unsigned>(MaxOffset));
488 break; // At most one FI per instruction
495 void AArch64InstrInfo::getAddressConstraints(const MachineInstr &MI,
496 int &AccessScale, int &MinOffset,
497 int &MaxOffset) const {
498 switch (MI.getOpcode()) {
499 default: llvm_unreachable("Unkown load/store kind");
500 case TargetOpcode::DBG_VALUE:
505 case AArch64::LS8_LDR: case AArch64::LS8_STR:
506 case AArch64::LSFP8_LDR: case AArch64::LSFP8_STR:
507 case AArch64::LDRSBw:
508 case AArch64::LDRSBx:
513 case AArch64::LS16_LDR: case AArch64::LS16_STR:
514 case AArch64::LSFP16_LDR: case AArch64::LSFP16_STR:
515 case AArch64::LDRSHw:
516 case AArch64::LDRSHx:
519 MaxOffset = 0xfff * AccessScale;
521 case AArch64::LS32_LDR: case AArch64::LS32_STR:
522 case AArch64::LSFP32_LDR: case AArch64::LSFP32_STR:
523 case AArch64::LDRSWx:
524 case AArch64::LDPSWx:
527 MaxOffset = 0xfff * AccessScale;
529 case AArch64::LS64_LDR: case AArch64::LS64_STR:
530 case AArch64::LSFP64_LDR: case AArch64::LSFP64_STR:
534 MaxOffset = 0xfff * AccessScale;
536 case AArch64::LSFP128_LDR: case AArch64::LSFP128_STR:
539 MaxOffset = 0xfff * AccessScale;
541 case AArch64::LSPair32_LDR: case AArch64::LSPair32_STR:
542 case AArch64::LSFPPair32_LDR: case AArch64::LSFPPair32_STR:
544 MinOffset = -0x40 * AccessScale;
545 MaxOffset = 0x3f * AccessScale;
547 case AArch64::LSPair64_LDR: case AArch64::LSPair64_STR:
548 case AArch64::LSFPPair64_LDR: case AArch64::LSFPPair64_STR:
550 MinOffset = -0x40 * AccessScale;
551 MaxOffset = 0x3f * AccessScale;
553 case AArch64::LSFPPair128_LDR: case AArch64::LSFPPair128_STR:
555 MinOffset = -0x40 * AccessScale;
556 MaxOffset = 0x3f * AccessScale;
561 bool llvm::rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
562 unsigned FrameReg, int &Offset,
563 const AArch64InstrInfo &TII) {
564 MachineBasicBlock &MBB = *MI.getParent();
565 MachineFunction &MF = *MBB.getParent();
566 MachineFrameInfo &MFI = *MF.getFrameInfo();
568 MFI.getObjectOffset(FrameRegIdx);
569 llvm_unreachable("Unimplemented rewriteFrameIndex");
572 void llvm::emitRegUpdate(MachineBasicBlock &MBB,
573 MachineBasicBlock::iterator MBBI,
574 DebugLoc dl, const TargetInstrInfo &TII,
575 unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
576 int64_t NumBytes, MachineInstr::MIFlag MIFlags) {
577 if (NumBytes == 0 && DstReg == SrcReg)
579 else if (abs(NumBytes) & ~0xffffff) {
580 // Generically, we have to materialize the offset into a temporary register
581 // and subtract it. There are a couple of ways this could be done, for now
582 // we'll use a movz/movk or movn/movk sequence.
583 uint64_t Bits = static_cast<uint64_t>(abs(NumBytes));
584 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVZxii), ScratchReg)
585 .addImm(0xffff & Bits).addImm(0)
586 .setMIFlags(MIFlags);
590 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
592 .addImm(0xffff & Bits).addImm(1)
593 .setMIFlags(MIFlags);
598 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
600 .addImm(0xffff & Bits).addImm(2)
601 .setMIFlags(MIFlags);
606 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
608 .addImm(0xffff & Bits).addImm(3)
609 .setMIFlags(MIFlags);
612 // ADD DST, SRC, xTMP (, lsl #0)
613 unsigned AddOp = NumBytes > 0 ? AArch64::ADDxxx_uxtx : AArch64::SUBxxx_uxtx;
614 BuildMI(MBB, MBBI, dl, TII.get(AddOp), DstReg)
615 .addReg(SrcReg, RegState::Kill)
616 .addReg(ScratchReg, RegState::Kill)
622 // Now we know that the adjustment can be done in at most two add/sub
623 // (immediate) instructions, which is always more efficient than a
624 // literal-pool load, or even a hypothetical movz/movk/add sequence
626 // Decide whether we're doing addition or subtraction
627 unsigned LowOp, HighOp;
629 LowOp = AArch64::ADDxxi_lsl0_s;
630 HighOp = AArch64::ADDxxi_lsl12_s;
632 LowOp = AArch64::SUBxxi_lsl0_s;
633 HighOp = AArch64::SUBxxi_lsl12_s;
634 NumBytes = abs(NumBytes);
637 // If we're here, at the very least a move needs to be produced, which just
638 // happens to be materializable by an ADD.
639 if ((NumBytes & 0xfff) || NumBytes == 0) {
640 BuildMI(MBB, MBBI, dl, TII.get(LowOp), DstReg)
641 .addReg(SrcReg, RegState::Kill)
642 .addImm(NumBytes & 0xfff)
645 // Next update should use the register we've just defined.
649 if (NumBytes & 0xfff000) {
650 BuildMI(MBB, MBBI, dl, TII.get(HighOp), DstReg)
651 .addReg(SrcReg, RegState::Kill)
652 .addImm(NumBytes >> 12)
657 void llvm::emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
658 DebugLoc dl, const TargetInstrInfo &TII,
659 unsigned ScratchReg, int64_t NumBytes,
660 MachineInstr::MIFlag MIFlags) {
661 emitRegUpdate(MBB, MI, dl, TII, AArch64::XSP, AArch64::XSP, AArch64::X16,
667 struct LDTLSCleanup : public MachineFunctionPass {
669 LDTLSCleanup() : MachineFunctionPass(ID) {}
671 virtual bool runOnMachineFunction(MachineFunction &MF) {
672 AArch64MachineFunctionInfo* MFI
673 = MF.getInfo<AArch64MachineFunctionInfo>();
674 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
675 // No point folding accesses if there isn't at least two.
679 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
680 return VisitNode(DT->getRootNode(), 0);
683 // Visit the dominator subtree rooted at Node in pre-order.
684 // If TLSBaseAddrReg is non-null, then use that to replace any
685 // TLS_base_addr instructions. Otherwise, create the register
686 // when the first such instruction is seen, and then use it
687 // as we encounter more instructions.
688 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
689 MachineBasicBlock *BB = Node->getBlock();
690 bool Changed = false;
692 // Traverse the current block.
693 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
695 switch (I->getOpcode()) {
696 case AArch64::TLSDESC_BLRx:
697 // Make sure it's a local dynamic access.
698 if (!I->getOperand(1).isSymbol() ||
699 strcmp(I->getOperand(1).getSymbolName(), "_TLS_MODULE_BASE_"))
703 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
705 I = SetRegister(I, &TLSBaseAddrReg);
713 // Visit the children of this block in the dominator tree.
714 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
716 Changed |= VisitNode(*I, TLSBaseAddrReg);
722 // Replace the TLS_base_addr instruction I with a copy from
723 // TLSBaseAddrReg, returning the new instruction.
724 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
725 unsigned TLSBaseAddrReg) {
726 MachineFunction *MF = I->getParent()->getParent();
727 const AArch64TargetMachine *TM =
728 static_cast<const AArch64TargetMachine *>(&MF->getTarget());
729 const AArch64InstrInfo *TII = TM->getInstrInfo();
731 // Insert a Copy from TLSBaseAddrReg to x0, which is where the rest of the
732 // code sequence assumes the address will be.
733 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
734 TII->get(TargetOpcode::COPY),
736 .addReg(TLSBaseAddrReg);
738 // Erase the TLS_base_addr instruction.
739 I->eraseFromParent();
744 // Create a virtal register in *TLSBaseAddrReg, and populate it by
745 // inserting a copy instruction after I. Returns the new instruction.
746 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
747 MachineFunction *MF = I->getParent()->getParent();
748 const AArch64TargetMachine *TM =
749 static_cast<const AArch64TargetMachine *>(&MF->getTarget());
750 const AArch64InstrInfo *TII = TM->getInstrInfo();
752 // Create a virtual register for the TLS base address.
753 MachineRegisterInfo &RegInfo = MF->getRegInfo();
754 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
756 // Insert a copy from X0 to TLSBaseAddrReg for later.
757 MachineInstr *Next = I->getNextNode();
758 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
759 TII->get(TargetOpcode::COPY),
761 .addReg(AArch64::X0);
766 virtual const char *getPassName() const {
767 return "Local Dynamic TLS Access Clean-up";
770 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
771 AU.setPreservesCFG();
772 AU.addRequired<MachineDominatorTree>();
773 MachineFunctionPass::getAnalysisUsage(AU);
778 char LDTLSCleanup::ID = 0;
780 llvm::createAArch64CleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }