1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64InstrInfo.h"
15 #include "AArch64MachineCombinerPattern.h"
16 #include "AArch64Subtarget.h"
17 #include "MCTargetDesc/AArch64AddressingModes.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
29 #define GET_INSTRINFO_CTOR_DTOR
30 #include "AArch64GenInstrInfo.inc"
32 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
33 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
36 /// GetInstSize - Return the number of bytes of code the specified
37 /// instruction may be. This returns the maximum number of bytes.
38 unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
39 const MachineBasicBlock &MBB = *MI->getParent();
40 const MachineFunction *MF = MBB.getParent();
41 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
43 if (MI->getOpcode() == AArch64::INLINEASM)
44 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
46 const MCInstrDesc &Desc = MI->getDesc();
47 switch (Desc.getOpcode()) {
49 // Anything not explicitly designated otherwise is a nomal 4-byte insn.
51 case TargetOpcode::DBG_VALUE:
52 case TargetOpcode::EH_LABEL:
53 case TargetOpcode::IMPLICIT_DEF:
54 case TargetOpcode::KILL:
58 llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");
61 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
62 SmallVectorImpl<MachineOperand> &Cond) {
63 // Block ends with fall-through condbranch.
64 switch (LastInst->getOpcode()) {
66 llvm_unreachable("Unknown branch instruction?");
68 Target = LastInst->getOperand(1).getMBB();
69 Cond.push_back(LastInst->getOperand(0));
75 Target = LastInst->getOperand(1).getMBB();
76 Cond.push_back(MachineOperand::CreateImm(-1));
77 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
78 Cond.push_back(LastInst->getOperand(0));
84 Target = LastInst->getOperand(2).getMBB();
85 Cond.push_back(MachineOperand::CreateImm(-1));
86 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
87 Cond.push_back(LastInst->getOperand(0));
88 Cond.push_back(LastInst->getOperand(1));
93 bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
94 MachineBasicBlock *&TBB,
95 MachineBasicBlock *&FBB,
96 SmallVectorImpl<MachineOperand> &Cond,
97 bool AllowModify) const {
98 // If the block has no terminators, it just falls into the block after it.
99 MachineBasicBlock::iterator I = MBB.end();
100 if (I == MBB.begin())
103 while (I->isDebugValue()) {
104 if (I == MBB.begin())
108 if (!isUnpredicatedTerminator(I))
111 // Get the last instruction in the block.
112 MachineInstr *LastInst = I;
114 // If there is only one terminator instruction, process it.
115 unsigned LastOpc = LastInst->getOpcode();
116 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
117 if (isUncondBranchOpcode(LastOpc)) {
118 TBB = LastInst->getOperand(0).getMBB();
121 if (isCondBranchOpcode(LastOpc)) {
122 // Block ends with fall-through condbranch.
123 parseCondBranch(LastInst, TBB, Cond);
126 return true; // Can't handle indirect branch.
129 // Get the instruction before it if it is a terminator.
130 MachineInstr *SecondLastInst = I;
131 unsigned SecondLastOpc = SecondLastInst->getOpcode();
133 // If AllowModify is true and the block ends with two or more unconditional
134 // branches, delete all but the first unconditional branch.
135 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
136 while (isUncondBranchOpcode(SecondLastOpc)) {
137 LastInst->eraseFromParent();
138 LastInst = SecondLastInst;
139 LastOpc = LastInst->getOpcode();
140 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
141 // Return now the only terminator is an unconditional branch.
142 TBB = LastInst->getOperand(0).getMBB();
146 SecondLastOpc = SecondLastInst->getOpcode();
151 // If there are three terminators, we don't know what sort of block this is.
152 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
155 // If the block ends with a B and a Bcc, handle it.
156 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
157 parseCondBranch(SecondLastInst, TBB, Cond);
158 FBB = LastInst->getOperand(0).getMBB();
162 // If the block ends with two unconditional branches, handle it. The second
163 // one is not executed, so remove it.
164 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
165 TBB = SecondLastInst->getOperand(0).getMBB();
168 I->eraseFromParent();
172 // ...likewise if it ends with an indirect branch followed by an unconditional
174 if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
177 I->eraseFromParent();
181 // Otherwise, can't handle this.
185 bool AArch64InstrInfo::ReverseBranchCondition(
186 SmallVectorImpl<MachineOperand> &Cond) const {
187 if (Cond[0].getImm() != -1) {
189 AArch64CC::CondCode CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
190 Cond[0].setImm(AArch64CC::getInvertedCondCode(CC));
192 // Folded compare-and-branch
193 switch (Cond[1].getImm()) {
195 llvm_unreachable("Unknown conditional branch!");
197 Cond[1].setImm(AArch64::CBNZW);
200 Cond[1].setImm(AArch64::CBZW);
203 Cond[1].setImm(AArch64::CBNZX);
206 Cond[1].setImm(AArch64::CBZX);
209 Cond[1].setImm(AArch64::TBNZW);
212 Cond[1].setImm(AArch64::TBZW);
215 Cond[1].setImm(AArch64::TBNZX);
218 Cond[1].setImm(AArch64::TBZX);
226 unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
227 MachineBasicBlock::iterator I = MBB.end();
228 if (I == MBB.begin())
231 while (I->isDebugValue()) {
232 if (I == MBB.begin())
236 if (!isUncondBranchOpcode(I->getOpcode()) &&
237 !isCondBranchOpcode(I->getOpcode()))
240 // Remove the branch.
241 I->eraseFromParent();
245 if (I == MBB.begin())
248 if (!isCondBranchOpcode(I->getOpcode()))
251 // Remove the branch.
252 I->eraseFromParent();
256 void AArch64InstrInfo::instantiateCondBranch(
257 MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB,
258 const SmallVectorImpl<MachineOperand> &Cond) const {
259 if (Cond[0].getImm() != -1) {
261 BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
263 // Folded compare-and-branch
264 // Note that we use addOperand instead of addReg to keep the flags.
265 const MachineInstrBuilder MIB =
266 BuildMI(&MBB, DL, get(Cond[1].getImm())).addOperand(Cond[2]);
268 MIB.addImm(Cond[3].getImm());
273 unsigned AArch64InstrInfo::InsertBranch(
274 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
275 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
276 // Shouldn't be a fall through.
277 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
280 if (Cond.empty()) // Unconditional branch?
281 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB);
283 instantiateCondBranch(MBB, DL, TBB, Cond);
287 // Two-way conditional branch.
288 instantiateCondBranch(MBB, DL, TBB, Cond);
289 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB);
293 // Find the original register that VReg is copied from.
294 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
295 while (TargetRegisterInfo::isVirtualRegister(VReg)) {
296 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
297 if (!DefMI->isFullCopy())
299 VReg = DefMI->getOperand(1).getReg();
304 // Determine if VReg is defined by an instruction that can be folded into a
305 // csel instruction. If so, return the folded opcode, and the replacement
307 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
308 unsigned *NewVReg = nullptr) {
309 VReg = removeCopies(MRI, VReg);
310 if (!TargetRegisterInfo::isVirtualRegister(VReg))
313 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
314 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
316 unsigned SrcOpNum = 0;
317 switch (DefMI->getOpcode()) {
318 case AArch64::ADDSXri:
319 case AArch64::ADDSWri:
320 // if NZCV is used, do not fold.
321 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
323 // fall-through to ADDXri and ADDWri.
324 case AArch64::ADDXri:
325 case AArch64::ADDWri:
326 // add x, 1 -> csinc.
327 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
328 DefMI->getOperand(3).getImm() != 0)
331 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr;
334 case AArch64::ORNXrr:
335 case AArch64::ORNWrr: {
336 // not x -> csinv, represented as orn dst, xzr, src.
337 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
338 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
341 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr;
345 case AArch64::SUBSXrr:
346 case AArch64::SUBSWrr:
347 // if NZCV is used, do not fold.
348 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
350 // fall-through to SUBXrr and SUBWrr.
351 case AArch64::SUBXrr:
352 case AArch64::SUBWrr: {
353 // neg x -> csneg, represented as sub dst, xzr, src.
354 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
355 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
358 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr;
364 assert(Opc && SrcOpNum && "Missing parameters");
367 *NewVReg = DefMI->getOperand(SrcOpNum).getReg();
371 bool AArch64InstrInfo::canInsertSelect(
372 const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond,
373 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles,
374 int &FalseCycles) const {
375 // Check register classes.
376 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
377 const TargetRegisterClass *RC =
378 Subtarget.getRegisterInfo()->getCommonSubClass(MRI.getRegClass(TrueReg),
379 MRI.getRegClass(FalseReg));
383 // Expanding cbz/tbz requires an extra cycle of latency on the condition.
384 unsigned ExtraCondLat = Cond.size() != 1;
386 // GPRs are handled by csel.
387 // FIXME: Fold in x+1, -x, and ~x when applicable.
388 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
389 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
390 // Single-cycle csel, csinc, csinv, and csneg.
391 CondCycles = 1 + ExtraCondLat;
392 TrueCycles = FalseCycles = 1;
393 if (canFoldIntoCSel(MRI, TrueReg))
395 else if (canFoldIntoCSel(MRI, FalseReg))
400 // Scalar floating point is handled by fcsel.
401 // FIXME: Form fabs, fmin, and fmax when applicable.
402 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
403 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
404 CondCycles = 5 + ExtraCondLat;
405 TrueCycles = FalseCycles = 2;
413 void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
414 MachineBasicBlock::iterator I, DebugLoc DL,
416 const SmallVectorImpl<MachineOperand> &Cond,
417 unsigned TrueReg, unsigned FalseReg) const {
418 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
420 // Parse the condition code, see parseCondBranch() above.
421 AArch64CC::CondCode CC;
422 switch (Cond.size()) {
424 llvm_unreachable("Unknown condition opcode in Cond");
426 CC = AArch64CC::CondCode(Cond[0].getImm());
428 case 3: { // cbz/cbnz
429 // We must insert a compare against 0.
431 switch (Cond[1].getImm()) {
433 llvm_unreachable("Unknown branch opcode in Cond");
451 unsigned SrcReg = Cond[2].getReg();
453 // cmp reg, #0 is actually subs xzr, reg, #0.
454 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
455 BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR)
460 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
461 BuildMI(MBB, I, DL, get(AArch64::SUBSWri), AArch64::WZR)
468 case 4: { // tbz/tbnz
469 // We must insert a tst instruction.
470 switch (Cond[1].getImm()) {
472 llvm_unreachable("Unknown branch opcode in Cond");
482 // cmp reg, #foo is actually ands xzr, reg, #1<<foo.
483 if (Cond[1].getImm() == AArch64::TBZW || Cond[1].getImm() == AArch64::TBNZW)
484 BuildMI(MBB, I, DL, get(AArch64::ANDSWri), AArch64::WZR)
485 .addReg(Cond[2].getReg())
487 AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 32));
489 BuildMI(MBB, I, DL, get(AArch64::ANDSXri), AArch64::XZR)
490 .addReg(Cond[2].getReg())
492 AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 64));
498 const TargetRegisterClass *RC = nullptr;
499 bool TryFold = false;
500 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
501 RC = &AArch64::GPR64RegClass;
502 Opc = AArch64::CSELXr;
504 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
505 RC = &AArch64::GPR32RegClass;
506 Opc = AArch64::CSELWr;
508 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) {
509 RC = &AArch64::FPR64RegClass;
510 Opc = AArch64::FCSELDrrr;
511 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) {
512 RC = &AArch64::FPR32RegClass;
513 Opc = AArch64::FCSELSrrr;
515 assert(RC && "Unsupported regclass");
517 // Try folding simple instructions into the csel.
519 unsigned NewVReg = 0;
520 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg);
522 // The folded opcodes csinc, csinc and csneg apply the operation to
523 // FalseReg, so we need to invert the condition.
524 CC = AArch64CC::getInvertedCondCode(CC);
527 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg);
529 // Fold the operation. Leave any dead instructions for DCE to clean up.
533 // The extends the live range of NewVReg.
534 MRI.clearKillFlags(NewVReg);
538 // Pull all virtual register into the appropriate class.
539 MRI.constrainRegClass(TrueReg, RC);
540 MRI.constrainRegClass(FalseReg, RC);
543 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm(
547 // FIXME: this implementation should be micro-architecture dependent, so a
548 // micro-architecture target hook should be introduced here in future.
549 bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const {
550 if (!Subtarget.isCortexA57() && !Subtarget.isCortexA53())
551 return MI->isAsCheapAsAMove();
553 switch (MI->getOpcode()) {
557 // add/sub on register without shift
558 case AArch64::ADDWri:
559 case AArch64::ADDXri:
560 case AArch64::SUBWri:
561 case AArch64::SUBXri:
562 return (MI->getOperand(3).getImm() == 0);
564 // logical ops on immediate
565 case AArch64::ANDWri:
566 case AArch64::ANDXri:
567 case AArch64::EORWri:
568 case AArch64::EORXri:
569 case AArch64::ORRWri:
570 case AArch64::ORRXri:
573 // logical ops on register without shift
574 case AArch64::ANDWrr:
575 case AArch64::ANDXrr:
576 case AArch64::BICWrr:
577 case AArch64::BICXrr:
578 case AArch64::EONWrr:
579 case AArch64::EONXrr:
580 case AArch64::EORWrr:
581 case AArch64::EORXrr:
582 case AArch64::ORNWrr:
583 case AArch64::ORNXrr:
584 case AArch64::ORRWrr:
585 case AArch64::ORRXrr:
589 llvm_unreachable("Unknown opcode to check as cheap as a move!");
592 bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
593 unsigned &SrcReg, unsigned &DstReg,
594 unsigned &SubIdx) const {
595 switch (MI.getOpcode()) {
598 case AArch64::SBFMXri: // aka sxtw
599 case AArch64::UBFMXri: // aka uxtw
600 // Check for the 32 -> 64 bit extension case, these instructions can do
602 if (MI.getOperand(2).getImm() != 0 || MI.getOperand(3).getImm() != 31)
604 // This is a signed or unsigned 32 -> 64 bit extension.
605 SrcReg = MI.getOperand(1).getReg();
606 DstReg = MI.getOperand(0).getReg();
607 SubIdx = AArch64::sub_32;
613 AArch64InstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
615 AliasAnalysis *AA) const {
616 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
617 unsigned BaseRegA = 0, BaseRegB = 0;
618 int OffsetA = 0, OffsetB = 0;
619 int WidthA = 0, WidthB = 0;
621 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
622 "MIa must be a store or a load");
623 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
624 "MIb must be a store or a load");
626 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
627 MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
630 // Retrieve the base register, offset from the base register and width. Width
631 // is the size of memory that is being loaded/stored (e.g. 1, 2, 4, 8). If
632 // base registers are identical, and the offset of a lower memory access +
633 // the width doesn't overlap the offset of a higher memory access,
634 // then the memory accesses are different.
635 if (getLdStBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) &&
636 getLdStBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) {
637 if (BaseRegA == BaseRegB) {
638 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
639 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
640 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
641 if (LowOffset + LowWidth <= HighOffset)
648 /// analyzeCompare - For a comparison instruction, return the source registers
649 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
650 /// Return true if the comparison instruction can be analyzed.
651 bool AArch64InstrInfo::analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
652 unsigned &SrcReg2, int &CmpMask,
653 int &CmpValue) const {
654 switch (MI->getOpcode()) {
657 case AArch64::SUBSWrr:
658 case AArch64::SUBSWrs:
659 case AArch64::SUBSWrx:
660 case AArch64::SUBSXrr:
661 case AArch64::SUBSXrs:
662 case AArch64::SUBSXrx:
663 case AArch64::ADDSWrr:
664 case AArch64::ADDSWrs:
665 case AArch64::ADDSWrx:
666 case AArch64::ADDSXrr:
667 case AArch64::ADDSXrs:
668 case AArch64::ADDSXrx:
669 // Replace SUBSWrr with SUBWrr if NZCV is not used.
670 SrcReg = MI->getOperand(1).getReg();
671 SrcReg2 = MI->getOperand(2).getReg();
675 case AArch64::SUBSWri:
676 case AArch64::ADDSWri:
677 case AArch64::SUBSXri:
678 case AArch64::ADDSXri:
679 SrcReg = MI->getOperand(1).getReg();
682 // FIXME: In order to convert CmpValue to 0 or 1
683 CmpValue = (MI->getOperand(2).getImm() != 0);
685 case AArch64::ANDSWri:
686 case AArch64::ANDSXri:
687 // ANDS does not use the same encoding scheme as the others xxxS
689 SrcReg = MI->getOperand(1).getReg();
692 // FIXME:The return val type of decodeLogicalImmediate is uint64_t,
693 // while the type of CmpValue is int. When converting uint64_t to int,
694 // the high 32 bits of uint64_t will be lost.
695 // In fact it causes a bug in spec2006-483.xalancbmk
696 // CmpValue is only used to compare with zero in OptimizeCompareInstr
697 CmpValue = (AArch64_AM::decodeLogicalImmediate(
698 MI->getOperand(2).getImm(),
699 MI->getOpcode() == AArch64::ANDSWri ? 32 : 64) != 0);
706 static bool UpdateOperandRegClass(MachineInstr *Instr) {
707 MachineBasicBlock *MBB = Instr->getParent();
708 assert(MBB && "Can't get MachineBasicBlock here");
709 MachineFunction *MF = MBB->getParent();
710 assert(MF && "Can't get MachineFunction here");
711 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
712 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
713 MachineRegisterInfo *MRI = &MF->getRegInfo();
715 for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx;
717 MachineOperand &MO = Instr->getOperand(OpIdx);
718 const TargetRegisterClass *OpRegCstraints =
719 Instr->getRegClassConstraint(OpIdx, TII, TRI);
721 // If there's no constraint, there's nothing to do.
724 // If the operand is a frame index, there's nothing to do here.
725 // A frame index operand will resolve correctly during PEI.
730 "Operand has register constraints without being a register!");
732 unsigned Reg = MO.getReg();
733 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
734 if (!OpRegCstraints->contains(Reg))
736 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
737 !MRI->constrainRegClass(Reg, OpRegCstraints))
744 /// \brief Return the opcode that does not set flags when possible - otherwise
745 /// return the original opcode. The caller is responsible to do the actual
746 /// substitution and legality checking.
747 static unsigned convertFlagSettingOpcode(const MachineInstr *MI) {
748 // Don't convert all compare instructions, because for some the zero register
749 // encoding becomes the sp register.
750 bool MIDefinesZeroReg = false;
751 if (MI->definesRegister(AArch64::WZR) || MI->definesRegister(AArch64::XZR))
752 MIDefinesZeroReg = true;
754 switch (MI->getOpcode()) {
756 return MI->getOpcode();
757 case AArch64::ADDSWrr:
758 return AArch64::ADDWrr;
759 case AArch64::ADDSWri:
760 return MIDefinesZeroReg ? AArch64::ADDSWri : AArch64::ADDWri;
761 case AArch64::ADDSWrs:
762 return MIDefinesZeroReg ? AArch64::ADDSWrs : AArch64::ADDWrs;
763 case AArch64::ADDSWrx:
764 return AArch64::ADDWrx;
765 case AArch64::ADDSXrr:
766 return AArch64::ADDXrr;
767 case AArch64::ADDSXri:
768 return MIDefinesZeroReg ? AArch64::ADDSXri : AArch64::ADDXri;
769 case AArch64::ADDSXrs:
770 return MIDefinesZeroReg ? AArch64::ADDSXrs : AArch64::ADDXrs;
771 case AArch64::ADDSXrx:
772 return AArch64::ADDXrx;
773 case AArch64::SUBSWrr:
774 return AArch64::SUBWrr;
775 case AArch64::SUBSWri:
776 return MIDefinesZeroReg ? AArch64::SUBSWri : AArch64::SUBWri;
777 case AArch64::SUBSWrs:
778 return MIDefinesZeroReg ? AArch64::SUBSWrs : AArch64::SUBWrs;
779 case AArch64::SUBSWrx:
780 return AArch64::SUBWrx;
781 case AArch64::SUBSXrr:
782 return AArch64::SUBXrr;
783 case AArch64::SUBSXri:
784 return MIDefinesZeroReg ? AArch64::SUBSXri : AArch64::SUBXri;
785 case AArch64::SUBSXrs:
786 return MIDefinesZeroReg ? AArch64::SUBSXrs : AArch64::SUBXrs;
787 case AArch64::SUBSXrx:
788 return AArch64::SUBXrx;
792 /// True when condition code could be modified on the instruction
793 /// trace starting at from and ending at to.
794 static bool modifiesConditionCode(MachineInstr *From, MachineInstr *To,
795 const bool CheckOnlyCCWrites,
796 const TargetRegisterInfo *TRI) {
797 // We iterate backward starting \p To until we hit \p From
798 MachineBasicBlock::iterator I = To, E = From, B = To->getParent()->begin();
800 // Early exit if To is at the beginning of the BB.
804 // Check whether the definition of SrcReg is in the same basic block as
805 // Compare. If not, assume the condition code gets modified on some path.
806 if (To->getParent() != From->getParent())
809 // Check that NZCV isn't set on the trace.
810 for (--I; I != E; --I) {
811 const MachineInstr &Instr = *I;
813 if (Instr.modifiesRegister(AArch64::NZCV, TRI) ||
814 (!CheckOnlyCCWrites && Instr.readsRegister(AArch64::NZCV, TRI)))
815 // This instruction modifies or uses NZCV after the one we want to
819 // We currently don't allow the instruction trace to cross basic
825 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
826 /// comparison into one that sets the zero bit in the flags register.
827 bool AArch64InstrInfo::optimizeCompareInstr(
828 MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
829 int CmpValue, const MachineRegisterInfo *MRI) const {
831 // Replace SUBSWrr with SUBWrr if NZCV is not used.
832 int Cmp_NZCV = CmpInstr->findRegisterDefOperandIdx(AArch64::NZCV, true);
833 if (Cmp_NZCV != -1) {
834 if (CmpInstr->definesRegister(AArch64::WZR) ||
835 CmpInstr->definesRegister(AArch64::XZR)) {
836 CmpInstr->eraseFromParent();
839 unsigned Opc = CmpInstr->getOpcode();
840 unsigned NewOpc = convertFlagSettingOpcode(CmpInstr);
843 const MCInstrDesc &MCID = get(NewOpc);
844 CmpInstr->setDesc(MCID);
845 CmpInstr->RemoveOperand(Cmp_NZCV);
846 bool succeeded = UpdateOperandRegClass(CmpInstr);
848 assert(succeeded && "Some operands reg class are incompatible!");
852 // Continue only if we have a "ri" where immediate is zero.
853 // FIXME:CmpValue has already been converted to 0 or 1 in analyzeCompare
855 assert((CmpValue == 0 || CmpValue == 1) && "CmpValue must be 0 or 1!");
856 if (CmpValue != 0 || SrcReg2 != 0)
859 // CmpInstr is a Compare instruction if destination register is not used.
860 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
863 // Get the unique definition of SrcReg.
864 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
868 bool CheckOnlyCCWrites = false;
869 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
870 if (modifiesConditionCode(MI, CmpInstr, CheckOnlyCCWrites, TRI))
873 unsigned NewOpc = MI->getOpcode();
874 switch (MI->getOpcode()) {
877 case AArch64::ADDSWrr:
878 case AArch64::ADDSWri:
879 case AArch64::ADDSXrr:
880 case AArch64::ADDSXri:
881 case AArch64::SUBSWrr:
882 case AArch64::SUBSWri:
883 case AArch64::SUBSXrr:
884 case AArch64::SUBSXri:
886 case AArch64::ADDWrr: NewOpc = AArch64::ADDSWrr; break;
887 case AArch64::ADDWri: NewOpc = AArch64::ADDSWri; break;
888 case AArch64::ADDXrr: NewOpc = AArch64::ADDSXrr; break;
889 case AArch64::ADDXri: NewOpc = AArch64::ADDSXri; break;
890 case AArch64::ADCWr: NewOpc = AArch64::ADCSWr; break;
891 case AArch64::ADCXr: NewOpc = AArch64::ADCSXr; break;
892 case AArch64::SUBWrr: NewOpc = AArch64::SUBSWrr; break;
893 case AArch64::SUBWri: NewOpc = AArch64::SUBSWri; break;
894 case AArch64::SUBXrr: NewOpc = AArch64::SUBSXrr; break;
895 case AArch64::SUBXri: NewOpc = AArch64::SUBSXri; break;
896 case AArch64::SBCWr: NewOpc = AArch64::SBCSWr; break;
897 case AArch64::SBCXr: NewOpc = AArch64::SBCSXr; break;
898 case AArch64::ANDWri: NewOpc = AArch64::ANDSWri; break;
899 case AArch64::ANDXri: NewOpc = AArch64::ANDSXri; break;
902 // Scan forward for the use of NZCV.
903 // When checking against MI: if it's a conditional code requires
904 // checking of V bit, then this is not safe to do.
905 // It is safe to remove CmpInstr if NZCV is redefined or killed.
906 // If we are done with the basic block, we need to check whether NZCV is
909 for (MachineBasicBlock::iterator I = CmpInstr,
910 E = CmpInstr->getParent()->end();
911 !IsSafe && ++I != E;) {
912 const MachineInstr &Instr = *I;
913 for (unsigned IO = 0, EO = Instr.getNumOperands(); !IsSafe && IO != EO;
915 const MachineOperand &MO = Instr.getOperand(IO);
916 if (MO.isRegMask() && MO.clobbersPhysReg(AArch64::NZCV)) {
920 if (!MO.isReg() || MO.getReg() != AArch64::NZCV)
927 // Decode the condition code.
928 unsigned Opc = Instr.getOpcode();
929 AArch64CC::CondCode CC;
934 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 2).getImm();
936 case AArch64::CSINVWr:
937 case AArch64::CSINVXr:
938 case AArch64::CSINCWr:
939 case AArch64::CSINCXr:
940 case AArch64::CSELWr:
941 case AArch64::CSELXr:
942 case AArch64::CSNEGWr:
943 case AArch64::CSNEGXr:
944 case AArch64::FCSELSrrr:
945 case AArch64::FCSELDrrr:
946 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 1).getImm();
950 // It is not safe to remove Compare instruction if Overflow(V) is used.
953 // NZCV can be used multiple times, we should continue.
966 // If NZCV is not killed nor re-defined, we should check whether it is
967 // live-out. If it is live-out, do not optimize.
969 MachineBasicBlock *ParentBlock = CmpInstr->getParent();
970 for (auto *MBB : ParentBlock->successors())
971 if (MBB->isLiveIn(AArch64::NZCV))
975 // Update the instruction to set NZCV.
976 MI->setDesc(get(NewOpc));
977 CmpInstr->eraseFromParent();
978 bool succeeded = UpdateOperandRegClass(MI);
980 assert(succeeded && "Some operands reg class are incompatible!");
981 MI->addRegisterDefined(AArch64::NZCV, TRI);
986 AArch64InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
987 if (MI->getOpcode() != TargetOpcode::LOAD_STACK_GUARD)
990 MachineBasicBlock &MBB = *MI->getParent();
991 DebugLoc DL = MI->getDebugLoc();
992 unsigned Reg = MI->getOperand(0).getReg();
993 const GlobalValue *GV =
994 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
995 const TargetMachine &TM = MBB.getParent()->getTarget();
996 unsigned char OpFlags = Subtarget.ClassifyGlobalReference(GV, TM);
997 const unsigned char MO_NC = AArch64II::MO_NC;
999 if ((OpFlags & AArch64II::MO_GOT) != 0) {
1000 BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg)
1001 .addGlobalAddress(GV, 0, AArch64II::MO_GOT);
1002 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1003 .addReg(Reg, RegState::Kill).addImm(0)
1004 .addMemOperand(*MI->memoperands_begin());
1005 } else if (TM.getCodeModel() == CodeModel::Large) {
1006 BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
1007 .addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48);
1008 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1009 .addReg(Reg, RegState::Kill)
1010 .addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC).addImm(32);
1011 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1012 .addReg(Reg, RegState::Kill)
1013 .addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC).addImm(16);
1014 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1015 .addReg(Reg, RegState::Kill)
1016 .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0);
1017 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1018 .addReg(Reg, RegState::Kill).addImm(0)
1019 .addMemOperand(*MI->memoperands_begin());
1021 BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg)
1022 .addGlobalAddress(GV, 0, OpFlags | AArch64II::MO_PAGE);
1023 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | MO_NC;
1024 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1025 .addReg(Reg, RegState::Kill)
1026 .addGlobalAddress(GV, 0, LoFlags)
1027 .addMemOperand(*MI->memoperands_begin());
1035 /// Return true if this is this instruction has a non-zero immediate
1036 bool AArch64InstrInfo::hasShiftedReg(const MachineInstr *MI) const {
1037 switch (MI->getOpcode()) {
1040 case AArch64::ADDSWrs:
1041 case AArch64::ADDSXrs:
1042 case AArch64::ADDWrs:
1043 case AArch64::ADDXrs:
1044 case AArch64::ANDSWrs:
1045 case AArch64::ANDSXrs:
1046 case AArch64::ANDWrs:
1047 case AArch64::ANDXrs:
1048 case AArch64::BICSWrs:
1049 case AArch64::BICSXrs:
1050 case AArch64::BICWrs:
1051 case AArch64::BICXrs:
1052 case AArch64::CRC32Brr:
1053 case AArch64::CRC32CBrr:
1054 case AArch64::CRC32CHrr:
1055 case AArch64::CRC32CWrr:
1056 case AArch64::CRC32CXrr:
1057 case AArch64::CRC32Hrr:
1058 case AArch64::CRC32Wrr:
1059 case AArch64::CRC32Xrr:
1060 case AArch64::EONWrs:
1061 case AArch64::EONXrs:
1062 case AArch64::EORWrs:
1063 case AArch64::EORXrs:
1064 case AArch64::ORNWrs:
1065 case AArch64::ORNXrs:
1066 case AArch64::ORRWrs:
1067 case AArch64::ORRXrs:
1068 case AArch64::SUBSWrs:
1069 case AArch64::SUBSXrs:
1070 case AArch64::SUBWrs:
1071 case AArch64::SUBXrs:
1072 if (MI->getOperand(3).isImm()) {
1073 unsigned val = MI->getOperand(3).getImm();
1081 /// Return true if this is this instruction has a non-zero immediate
1082 bool AArch64InstrInfo::hasExtendedReg(const MachineInstr *MI) const {
1083 switch (MI->getOpcode()) {
1086 case AArch64::ADDSWrx:
1087 case AArch64::ADDSXrx:
1088 case AArch64::ADDSXrx64:
1089 case AArch64::ADDWrx:
1090 case AArch64::ADDXrx:
1091 case AArch64::ADDXrx64:
1092 case AArch64::SUBSWrx:
1093 case AArch64::SUBSXrx:
1094 case AArch64::SUBSXrx64:
1095 case AArch64::SUBWrx:
1096 case AArch64::SUBXrx:
1097 case AArch64::SUBXrx64:
1098 if (MI->getOperand(3).isImm()) {
1099 unsigned val = MI->getOperand(3).getImm();
1108 // Return true if this instruction simply sets its single destination register
1109 // to zero. This is equivalent to a register rename of the zero-register.
1110 bool AArch64InstrInfo::isGPRZero(const MachineInstr *MI) const {
1111 switch (MI->getOpcode()) {
1114 case AArch64::MOVZWi:
1115 case AArch64::MOVZXi: // movz Rd, #0 (LSL #0)
1116 if (MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) {
1117 assert(MI->getDesc().getNumOperands() == 3 &&
1118 MI->getOperand(2).getImm() == 0 && "invalid MOVZi operands");
1122 case AArch64::ANDWri: // and Rd, Rzr, #imm
1123 return MI->getOperand(1).getReg() == AArch64::WZR;
1124 case AArch64::ANDXri:
1125 return MI->getOperand(1).getReg() == AArch64::XZR;
1126 case TargetOpcode::COPY:
1127 return MI->getOperand(1).getReg() == AArch64::WZR;
1132 // Return true if this instruction simply renames a general register without
1134 bool AArch64InstrInfo::isGPRCopy(const MachineInstr *MI) const {
1135 switch (MI->getOpcode()) {
1138 case TargetOpcode::COPY: {
1139 // GPR32 copies will by lowered to ORRXrs
1140 unsigned DstReg = MI->getOperand(0).getReg();
1141 return (AArch64::GPR32RegClass.contains(DstReg) ||
1142 AArch64::GPR64RegClass.contains(DstReg));
1144 case AArch64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0)
1145 if (MI->getOperand(1).getReg() == AArch64::XZR) {
1146 assert(MI->getDesc().getNumOperands() == 4 &&
1147 MI->getOperand(3).getImm() == 0 && "invalid ORRrs operands");
1151 case AArch64::ADDXri: // add Xd, Xn, #0 (LSL #0)
1152 if (MI->getOperand(2).getImm() == 0) {
1153 assert(MI->getDesc().getNumOperands() == 4 &&
1154 MI->getOperand(3).getImm() == 0 && "invalid ADDXri operands");
1162 // Return true if this instruction simply renames a general register without
1164 bool AArch64InstrInfo::isFPRCopy(const MachineInstr *MI) const {
1165 switch (MI->getOpcode()) {
1168 case TargetOpcode::COPY: {
1169 // FPR64 copies will by lowered to ORR.16b
1170 unsigned DstReg = MI->getOperand(0).getReg();
1171 return (AArch64::FPR64RegClass.contains(DstReg) ||
1172 AArch64::FPR128RegClass.contains(DstReg));
1174 case AArch64::ORRv16i8:
1175 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
1176 assert(MI->getDesc().getNumOperands() == 3 && MI->getOperand(0).isReg() &&
1177 "invalid ORRv16i8 operands");
1185 unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1186 int &FrameIndex) const {
1187 switch (MI->getOpcode()) {
1190 case AArch64::LDRWui:
1191 case AArch64::LDRXui:
1192 case AArch64::LDRBui:
1193 case AArch64::LDRHui:
1194 case AArch64::LDRSui:
1195 case AArch64::LDRDui:
1196 case AArch64::LDRQui:
1197 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
1198 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
1199 FrameIndex = MI->getOperand(1).getIndex();
1200 return MI->getOperand(0).getReg();
1208 unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1209 int &FrameIndex) const {
1210 switch (MI->getOpcode()) {
1213 case AArch64::STRWui:
1214 case AArch64::STRXui:
1215 case AArch64::STRBui:
1216 case AArch64::STRHui:
1217 case AArch64::STRSui:
1218 case AArch64::STRDui:
1219 case AArch64::STRQui:
1220 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
1221 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
1222 FrameIndex = MI->getOperand(1).getIndex();
1223 return MI->getOperand(0).getReg();
1230 /// Return true if this is load/store scales or extends its register offset.
1231 /// This refers to scaling a dynamic index as opposed to scaled immediates.
1232 /// MI should be a memory op that allows scaled addressing.
1233 bool AArch64InstrInfo::isScaledAddr(const MachineInstr *MI) const {
1234 switch (MI->getOpcode()) {
1237 case AArch64::LDRBBroW:
1238 case AArch64::LDRBroW:
1239 case AArch64::LDRDroW:
1240 case AArch64::LDRHHroW:
1241 case AArch64::LDRHroW:
1242 case AArch64::LDRQroW:
1243 case AArch64::LDRSBWroW:
1244 case AArch64::LDRSBXroW:
1245 case AArch64::LDRSHWroW:
1246 case AArch64::LDRSHXroW:
1247 case AArch64::LDRSWroW:
1248 case AArch64::LDRSroW:
1249 case AArch64::LDRWroW:
1250 case AArch64::LDRXroW:
1251 case AArch64::STRBBroW:
1252 case AArch64::STRBroW:
1253 case AArch64::STRDroW:
1254 case AArch64::STRHHroW:
1255 case AArch64::STRHroW:
1256 case AArch64::STRQroW:
1257 case AArch64::STRSroW:
1258 case AArch64::STRWroW:
1259 case AArch64::STRXroW:
1260 case AArch64::LDRBBroX:
1261 case AArch64::LDRBroX:
1262 case AArch64::LDRDroX:
1263 case AArch64::LDRHHroX:
1264 case AArch64::LDRHroX:
1265 case AArch64::LDRQroX:
1266 case AArch64::LDRSBWroX:
1267 case AArch64::LDRSBXroX:
1268 case AArch64::LDRSHWroX:
1269 case AArch64::LDRSHXroX:
1270 case AArch64::LDRSWroX:
1271 case AArch64::LDRSroX:
1272 case AArch64::LDRWroX:
1273 case AArch64::LDRXroX:
1274 case AArch64::STRBBroX:
1275 case AArch64::STRBroX:
1276 case AArch64::STRDroX:
1277 case AArch64::STRHHroX:
1278 case AArch64::STRHroX:
1279 case AArch64::STRQroX:
1280 case AArch64::STRSroX:
1281 case AArch64::STRWroX:
1282 case AArch64::STRXroX:
1284 unsigned Val = MI->getOperand(3).getImm();
1285 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val);
1286 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val);
1291 /// Check all MachineMemOperands for a hint to suppress pairing.
1292 bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr *MI) const {
1293 assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
1294 "Too many target MO flags");
1295 for (auto *MM : MI->memoperands()) {
1296 if (MM->getFlags() &
1297 (MOSuppressPair << MachineMemOperand::MOTargetStartBit)) {
1304 /// Set a flag on the first MachineMemOperand to suppress pairing.
1305 void AArch64InstrInfo::suppressLdStPair(MachineInstr *MI) const {
1306 if (MI->memoperands_empty())
1309 assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
1310 "Too many target MO flags");
1311 (*MI->memoperands_begin())
1312 ->setFlags(MOSuppressPair << MachineMemOperand::MOTargetStartBit);
1316 AArch64InstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
1318 const TargetRegisterInfo *TRI) const {
1319 switch (LdSt->getOpcode()) {
1322 case AArch64::STRSui:
1323 case AArch64::STRDui:
1324 case AArch64::STRQui:
1325 case AArch64::STRXui:
1326 case AArch64::STRWui:
1327 case AArch64::LDRSui:
1328 case AArch64::LDRDui:
1329 case AArch64::LDRQui:
1330 case AArch64::LDRXui:
1331 case AArch64::LDRWui:
1332 if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
1334 BaseReg = LdSt->getOperand(1).getReg();
1335 MachineFunction &MF = *LdSt->getParent()->getParent();
1336 unsigned Width = getRegClass(LdSt->getDesc(), 0, TRI, MF)->getSize();
1337 Offset = LdSt->getOperand(2).getImm() * Width;
1342 bool AArch64InstrInfo::getLdStBaseRegImmOfsWidth(
1343 MachineInstr *LdSt, unsigned &BaseReg, int &Offset, int &Width,
1344 const TargetRegisterInfo *TRI) const {
1345 // Handle only loads/stores with base register followed by immediate offset.
1346 if (LdSt->getNumOperands() != 3)
1348 if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
1351 // Offset is calculated as the immediate operand multiplied by the scaling factor.
1352 // Unscaled instructions have scaling factor set to 1.
1354 switch (LdSt->getOpcode()) {
1357 case AArch64::LDURQi:
1358 case AArch64::STURQi:
1362 case AArch64::LDURXi:
1363 case AArch64::LDURDi:
1364 case AArch64::STURXi:
1365 case AArch64::STURDi:
1369 case AArch64::LDURWi:
1370 case AArch64::LDURSi:
1371 case AArch64::LDURSWi:
1372 case AArch64::STURWi:
1373 case AArch64::STURSi:
1377 case AArch64::LDURHi:
1378 case AArch64::LDURHHi:
1379 case AArch64::LDURSHXi:
1380 case AArch64::LDURSHWi:
1381 case AArch64::STURHi:
1382 case AArch64::STURHHi:
1386 case AArch64::LDURBi:
1387 case AArch64::LDURBBi:
1388 case AArch64::LDURSBXi:
1389 case AArch64::LDURSBWi:
1390 case AArch64::STURBi:
1391 case AArch64::STURBBi:
1395 case AArch64::LDRXui:
1396 case AArch64::STRXui:
1399 case AArch64::LDRWui:
1400 case AArch64::STRWui:
1403 case AArch64::LDRBui:
1404 case AArch64::STRBui:
1407 case AArch64::LDRHui:
1408 case AArch64::STRHui:
1411 case AArch64::LDRSui:
1412 case AArch64::STRSui:
1415 case AArch64::LDRDui:
1416 case AArch64::STRDui:
1419 case AArch64::LDRQui:
1420 case AArch64::STRQui:
1423 case AArch64::LDRBBui:
1424 case AArch64::STRBBui:
1427 case AArch64::LDRHHui:
1428 case AArch64::STRHHui:
1433 BaseReg = LdSt->getOperand(1).getReg();
1434 Offset = LdSt->getOperand(2).getImm() * Scale;
1438 /// Detect opportunities for ldp/stp formation.
1440 /// Only called for LdSt for which getLdStBaseRegImmOfs returns true.
1441 bool AArch64InstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
1442 MachineInstr *SecondLdSt,
1443 unsigned NumLoads) const {
1444 // Only cluster up to a single pair.
1447 if (FirstLdSt->getOpcode() != SecondLdSt->getOpcode())
1449 // getLdStBaseRegImmOfs guarantees that oper 2 isImm.
1450 unsigned Ofs1 = FirstLdSt->getOperand(2).getImm();
1451 // Allow 6 bits of positive range.
1454 // The caller should already have ordered First/SecondLdSt by offset.
1455 unsigned Ofs2 = SecondLdSt->getOperand(2).getImm();
1456 return Ofs1 + 1 == Ofs2;
1459 bool AArch64InstrInfo::shouldScheduleAdjacent(MachineInstr *First,
1460 MachineInstr *Second) const {
1461 // Cyclone can fuse CMN, CMP followed by Bcc.
1463 // FIXME: B0 can also fuse:
1464 // AND, BIC, ORN, ORR, or EOR (optional S) followed by Bcc or CBZ or CBNZ.
1465 if (Second->getOpcode() != AArch64::Bcc)
1467 switch (First->getOpcode()) {
1470 case AArch64::SUBSWri:
1471 case AArch64::ADDSWri:
1472 case AArch64::ANDSWri:
1473 case AArch64::SUBSXri:
1474 case AArch64::ADDSXri:
1475 case AArch64::ANDSXri:
1480 MachineInstr *AArch64InstrInfo::emitFrameIndexDebugValue(
1481 MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *Var,
1482 const MDNode *Expr, DebugLoc DL) const {
1483 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE))
1484 .addFrameIndex(FrameIx)
1492 static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
1493 unsigned Reg, unsigned SubIdx,
1495 const TargetRegisterInfo *TRI) {
1497 return MIB.addReg(Reg, State);
1499 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1500 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1501 return MIB.addReg(Reg, State, SubIdx);
1504 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg,
1506 // We really want the positive remainder mod 32 here, that happens to be
1507 // easily obtainable with a mask.
1508 return ((DestReg - SrcReg) & 0x1f) < NumRegs;
1511 void AArch64InstrInfo::copyPhysRegTuple(
1512 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
1513 unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode,
1514 llvm::ArrayRef<unsigned> Indices) const {
1515 assert(Subtarget.hasNEON() &&
1516 "Unexpected register copy without NEON");
1517 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1518 uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
1519 uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg);
1520 unsigned NumRegs = Indices.size();
1522 int SubReg = 0, End = NumRegs, Incr = 1;
1523 if (forwardCopyWillClobberTuple(DestEncoding, SrcEncoding, NumRegs)) {
1524 SubReg = NumRegs - 1;
1529 for (; SubReg != End; SubReg += Incr) {
1530 const MachineInstrBuilder &MIB = BuildMI(MBB, I, DL, get(Opcode));
1531 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
1532 AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI);
1533 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
1537 void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1538 MachineBasicBlock::iterator I, DebugLoc DL,
1539 unsigned DestReg, unsigned SrcReg,
1540 bool KillSrc) const {
1541 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1542 if (AArch64::GPR32spRegClass.contains(DestReg) &&
1543 (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
1544 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
1545 // If either operand is WSP, expand to ADD #0.
1546 if (Subtarget.hasZeroCycleRegMove()) {
1547 // Cyclone recognizes "ADD Xd, Xn, #0" as a zero-cycle register move.
1548 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
1549 &AArch64::GPR64spRegClass);
1550 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32,
1551 &AArch64::GPR64spRegClass);
1552 // This instruction is reading and writing X registers. This may upset
1553 // the register scavenger and machine verifier, so we need to indicate
1554 // that we are reading an undefined value from SrcRegX, but a proper
1555 // value from SrcReg.
1556 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestRegX)
1557 .addReg(SrcRegX, RegState::Undef)
1559 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
1560 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1562 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
1563 .addReg(SrcReg, getKillRegState(KillSrc))
1565 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1567 } else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroing()) {
1568 BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg).addImm(0).addImm(
1569 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1571 if (Subtarget.hasZeroCycleRegMove()) {
1572 // Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
1573 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
1574 &AArch64::GPR64spRegClass);
1575 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32,
1576 &AArch64::GPR64spRegClass);
1577 // This instruction is reading and writing X registers. This may upset
1578 // the register scavenger and machine verifier, so we need to indicate
1579 // that we are reading an undefined value from SrcRegX, but a proper
1580 // value from SrcReg.
1581 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestRegX)
1582 .addReg(AArch64::XZR)
1583 .addReg(SrcRegX, RegState::Undef)
1584 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1586 // Otherwise, expand to ORR WZR.
1587 BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
1588 .addReg(AArch64::WZR)
1589 .addReg(SrcReg, getKillRegState(KillSrc));
1595 if (AArch64::GPR64spRegClass.contains(DestReg) &&
1596 (AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) {
1597 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) {
1598 // If either operand is SP, expand to ADD #0.
1599 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
1600 .addReg(SrcReg, getKillRegState(KillSrc))
1602 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1603 } else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroing()) {
1604 BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg).addImm(0).addImm(
1605 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1607 // Otherwise, expand to ORR XZR.
1608 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
1609 .addReg(AArch64::XZR)
1610 .addReg(SrcReg, getKillRegState(KillSrc));
1615 // Copy a DDDD register quad by copying the individual sub-registers.
1616 if (AArch64::DDDDRegClass.contains(DestReg) &&
1617 AArch64::DDDDRegClass.contains(SrcReg)) {
1618 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1,
1619 AArch64::dsub2, AArch64::dsub3 };
1620 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1625 // Copy a DDD register triple by copying the individual sub-registers.
1626 if (AArch64::DDDRegClass.contains(DestReg) &&
1627 AArch64::DDDRegClass.contains(SrcReg)) {
1628 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1,
1630 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1635 // Copy a DD register pair by copying the individual sub-registers.
1636 if (AArch64::DDRegClass.contains(DestReg) &&
1637 AArch64::DDRegClass.contains(SrcReg)) {
1638 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1 };
1639 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1644 // Copy a QQQQ register quad by copying the individual sub-registers.
1645 if (AArch64::QQQQRegClass.contains(DestReg) &&
1646 AArch64::QQQQRegClass.contains(SrcReg)) {
1647 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1,
1648 AArch64::qsub2, AArch64::qsub3 };
1649 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1654 // Copy a QQQ register triple by copying the individual sub-registers.
1655 if (AArch64::QQQRegClass.contains(DestReg) &&
1656 AArch64::QQQRegClass.contains(SrcReg)) {
1657 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1,
1659 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1664 // Copy a QQ register pair by copying the individual sub-registers.
1665 if (AArch64::QQRegClass.contains(DestReg) &&
1666 AArch64::QQRegClass.contains(SrcReg)) {
1667 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1 };
1668 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1673 if (AArch64::FPR128RegClass.contains(DestReg) &&
1674 AArch64::FPR128RegClass.contains(SrcReg)) {
1675 if(Subtarget.hasNEON()) {
1676 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1678 .addReg(SrcReg, getKillRegState(KillSrc));
1680 BuildMI(MBB, I, DL, get(AArch64::STRQpre))
1681 .addReg(AArch64::SP, RegState::Define)
1682 .addReg(SrcReg, getKillRegState(KillSrc))
1683 .addReg(AArch64::SP)
1685 BuildMI(MBB, I, DL, get(AArch64::LDRQpre))
1686 .addReg(AArch64::SP, RegState::Define)
1687 .addReg(DestReg, RegState::Define)
1688 .addReg(AArch64::SP)
1694 if (AArch64::FPR64RegClass.contains(DestReg) &&
1695 AArch64::FPR64RegClass.contains(SrcReg)) {
1696 if(Subtarget.hasNEON()) {
1697 DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::dsub,
1698 &AArch64::FPR128RegClass);
1699 SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::dsub,
1700 &AArch64::FPR128RegClass);
1701 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1703 .addReg(SrcReg, getKillRegState(KillSrc));
1705 BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
1706 .addReg(SrcReg, getKillRegState(KillSrc));
1711 if (AArch64::FPR32RegClass.contains(DestReg) &&
1712 AArch64::FPR32RegClass.contains(SrcReg)) {
1713 if(Subtarget.hasNEON()) {
1714 DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::ssub,
1715 &AArch64::FPR128RegClass);
1716 SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::ssub,
1717 &AArch64::FPR128RegClass);
1718 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1720 .addReg(SrcReg, getKillRegState(KillSrc));
1722 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1723 .addReg(SrcReg, getKillRegState(KillSrc));
1728 if (AArch64::FPR16RegClass.contains(DestReg) &&
1729 AArch64::FPR16RegClass.contains(SrcReg)) {
1730 if(Subtarget.hasNEON()) {
1731 DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
1732 &AArch64::FPR128RegClass);
1733 SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
1734 &AArch64::FPR128RegClass);
1735 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1737 .addReg(SrcReg, getKillRegState(KillSrc));
1739 DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
1740 &AArch64::FPR32RegClass);
1741 SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
1742 &AArch64::FPR32RegClass);
1743 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1744 .addReg(SrcReg, getKillRegState(KillSrc));
1749 if (AArch64::FPR8RegClass.contains(DestReg) &&
1750 AArch64::FPR8RegClass.contains(SrcReg)) {
1751 if(Subtarget.hasNEON()) {
1752 DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
1753 &AArch64::FPR128RegClass);
1754 SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
1755 &AArch64::FPR128RegClass);
1756 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1758 .addReg(SrcReg, getKillRegState(KillSrc));
1760 DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
1761 &AArch64::FPR32RegClass);
1762 SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
1763 &AArch64::FPR32RegClass);
1764 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1765 .addReg(SrcReg, getKillRegState(KillSrc));
1770 // Copies between GPR64 and FPR64.
1771 if (AArch64::FPR64RegClass.contains(DestReg) &&
1772 AArch64::GPR64RegClass.contains(SrcReg)) {
1773 BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg)
1774 .addReg(SrcReg, getKillRegState(KillSrc));
1777 if (AArch64::GPR64RegClass.contains(DestReg) &&
1778 AArch64::FPR64RegClass.contains(SrcReg)) {
1779 BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
1780 .addReg(SrcReg, getKillRegState(KillSrc));
1783 // Copies between GPR32 and FPR32.
1784 if (AArch64::FPR32RegClass.contains(DestReg) &&
1785 AArch64::GPR32RegClass.contains(SrcReg)) {
1786 BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg)
1787 .addReg(SrcReg, getKillRegState(KillSrc));
1790 if (AArch64::GPR32RegClass.contains(DestReg) &&
1791 AArch64::FPR32RegClass.contains(SrcReg)) {
1792 BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
1793 .addReg(SrcReg, getKillRegState(KillSrc));
1797 if (DestReg == AArch64::NZCV) {
1798 assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy");
1799 BuildMI(MBB, I, DL, get(AArch64::MSR))
1800 .addImm(AArch64SysReg::NZCV)
1801 .addReg(SrcReg, getKillRegState(KillSrc))
1802 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define);
1806 if (SrcReg == AArch64::NZCV) {
1807 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy");
1808 BuildMI(MBB, I, DL, get(AArch64::MRS))
1810 .addImm(AArch64SysReg::NZCV)
1811 .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
1815 llvm_unreachable("unimplemented reg-to-reg copy");
1818 void AArch64InstrInfo::storeRegToStackSlot(
1819 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
1820 bool isKill, int FI, const TargetRegisterClass *RC,
1821 const TargetRegisterInfo *TRI) const {
1823 if (MBBI != MBB.end())
1824 DL = MBBI->getDebugLoc();
1825 MachineFunction &MF = *MBB.getParent();
1826 MachineFrameInfo &MFI = *MF.getFrameInfo();
1827 unsigned Align = MFI.getObjectAlignment(FI);
1829 MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI));
1830 MachineMemOperand *MMO = MF.getMachineMemOperand(
1831 PtrInfo, MachineMemOperand::MOStore, MFI.getObjectSize(FI), Align);
1834 switch (RC->getSize()) {
1836 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
1837 Opc = AArch64::STRBui;
1840 if (AArch64::FPR16RegClass.hasSubClassEq(RC))
1841 Opc = AArch64::STRHui;
1844 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
1845 Opc = AArch64::STRWui;
1846 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
1847 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
1849 assert(SrcReg != AArch64::WSP);
1850 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
1851 Opc = AArch64::STRSui;
1854 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
1855 Opc = AArch64::STRXui;
1856 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
1857 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
1859 assert(SrcReg != AArch64::SP);
1860 } else if (AArch64::FPR64RegClass.hasSubClassEq(RC))
1861 Opc = AArch64::STRDui;
1864 if (AArch64::FPR128RegClass.hasSubClassEq(RC))
1865 Opc = AArch64::STRQui;
1866 else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
1867 assert(Subtarget.hasNEON() &&
1868 "Unexpected register store without NEON");
1869 Opc = AArch64::ST1Twov1d, Offset = false;
1873 if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
1874 assert(Subtarget.hasNEON() &&
1875 "Unexpected register store without NEON");
1876 Opc = AArch64::ST1Threev1d, Offset = false;
1880 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
1881 assert(Subtarget.hasNEON() &&
1882 "Unexpected register store without NEON");
1883 Opc = AArch64::ST1Fourv1d, Offset = false;
1884 } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
1885 assert(Subtarget.hasNEON() &&
1886 "Unexpected register store without NEON");
1887 Opc = AArch64::ST1Twov2d, Offset = false;
1891 if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
1892 assert(Subtarget.hasNEON() &&
1893 "Unexpected register store without NEON");
1894 Opc = AArch64::ST1Threev2d, Offset = false;
1898 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
1899 assert(Subtarget.hasNEON() &&
1900 "Unexpected register store without NEON");
1901 Opc = AArch64::ST1Fourv2d, Offset = false;
1905 assert(Opc && "Unknown register class");
1907 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
1908 .addReg(SrcReg, getKillRegState(isKill))
1913 MI.addMemOperand(MMO);
1916 void AArch64InstrInfo::loadRegFromStackSlot(
1917 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
1918 int FI, const TargetRegisterClass *RC,
1919 const TargetRegisterInfo *TRI) const {
1921 if (MBBI != MBB.end())
1922 DL = MBBI->getDebugLoc();
1923 MachineFunction &MF = *MBB.getParent();
1924 MachineFrameInfo &MFI = *MF.getFrameInfo();
1925 unsigned Align = MFI.getObjectAlignment(FI);
1926 MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI));
1927 MachineMemOperand *MMO = MF.getMachineMemOperand(
1928 PtrInfo, MachineMemOperand::MOLoad, MFI.getObjectSize(FI), Align);
1932 switch (RC->getSize()) {
1934 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
1935 Opc = AArch64::LDRBui;
1938 if (AArch64::FPR16RegClass.hasSubClassEq(RC))
1939 Opc = AArch64::LDRHui;
1942 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
1943 Opc = AArch64::LDRWui;
1944 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1945 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass);
1947 assert(DestReg != AArch64::WSP);
1948 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
1949 Opc = AArch64::LDRSui;
1952 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
1953 Opc = AArch64::LDRXui;
1954 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1955 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass);
1957 assert(DestReg != AArch64::SP);
1958 } else if (AArch64::FPR64RegClass.hasSubClassEq(RC))
1959 Opc = AArch64::LDRDui;
1962 if (AArch64::FPR128RegClass.hasSubClassEq(RC))
1963 Opc = AArch64::LDRQui;
1964 else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
1965 assert(Subtarget.hasNEON() &&
1966 "Unexpected register load without NEON");
1967 Opc = AArch64::LD1Twov1d, Offset = false;
1971 if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
1972 assert(Subtarget.hasNEON() &&
1973 "Unexpected register load without NEON");
1974 Opc = AArch64::LD1Threev1d, Offset = false;
1978 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
1979 assert(Subtarget.hasNEON() &&
1980 "Unexpected register load without NEON");
1981 Opc = AArch64::LD1Fourv1d, Offset = false;
1982 } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
1983 assert(Subtarget.hasNEON() &&
1984 "Unexpected register load without NEON");
1985 Opc = AArch64::LD1Twov2d, Offset = false;
1989 if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
1990 assert(Subtarget.hasNEON() &&
1991 "Unexpected register load without NEON");
1992 Opc = AArch64::LD1Threev2d, Offset = false;
1996 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
1997 assert(Subtarget.hasNEON() &&
1998 "Unexpected register load without NEON");
1999 Opc = AArch64::LD1Fourv2d, Offset = false;
2003 assert(Opc && "Unknown register class");
2005 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
2006 .addReg(DestReg, getDefRegState(true))
2010 MI.addMemOperand(MMO);
2013 void llvm::emitFrameOffset(MachineBasicBlock &MBB,
2014 MachineBasicBlock::iterator MBBI, DebugLoc DL,
2015 unsigned DestReg, unsigned SrcReg, int Offset,
2016 const TargetInstrInfo *TII,
2017 MachineInstr::MIFlag Flag, bool SetNZCV) {
2018 if (DestReg == SrcReg && Offset == 0)
2021 bool isSub = Offset < 0;
2025 // FIXME: If the offset won't fit in 24-bits, compute the offset into a
2026 // scratch register. If DestReg is a virtual register, use it as the
2027 // scratch register; otherwise, create a new virtual register (to be
2028 // replaced by the scavenger at the end of PEI). That case can be optimized
2029 // slightly if DestReg is SP which is always 16-byte aligned, so the scratch
2030 // register can be loaded with offset%8 and the add/sub can use an extending
2031 // instruction with LSL#3.
2032 // Currently the function handles any offsets but generates a poor sequence
2034 // assert(Offset < (1 << 24) && "unimplemented reg plus immediate");
2038 Opc = isSub ? AArch64::SUBSXri : AArch64::ADDSXri;
2040 Opc = isSub ? AArch64::SUBXri : AArch64::ADDXri;
2041 const unsigned MaxEncoding = 0xfff;
2042 const unsigned ShiftSize = 12;
2043 const unsigned MaxEncodableValue = MaxEncoding << ShiftSize;
2044 while (((unsigned)Offset) >= (1 << ShiftSize)) {
2046 if (((unsigned)Offset) > MaxEncodableValue) {
2047 ThisVal = MaxEncodableValue;
2049 ThisVal = Offset & MaxEncodableValue;
2051 assert((ThisVal >> ShiftSize) <= MaxEncoding &&
2052 "Encoding cannot handle value that big");
2053 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
2055 .addImm(ThisVal >> ShiftSize)
2056 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftSize))
2064 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
2067 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
2071 MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2073 ArrayRef<unsigned> Ops,
2074 int FrameIndex) const {
2075 // This is a bit of a hack. Consider this instruction:
2077 // %vreg0<def> = COPY %SP; GPR64all:%vreg0
2079 // We explicitly chose GPR64all for the virtual register so such a copy might
2080 // be eliminated by RegisterCoalescer. However, that may not be possible, and
2081 // %vreg0 may even spill. We can't spill %SP, and since it is in the GPR64all
2082 // register class, TargetInstrInfo::foldMemoryOperand() is going to try.
2084 // To prevent that, we are going to constrain the %vreg0 register class here.
2086 // <rdar://problem/11522048>
2089 unsigned DstReg = MI->getOperand(0).getReg();
2090 unsigned SrcReg = MI->getOperand(1).getReg();
2091 if (SrcReg == AArch64::SP &&
2092 TargetRegisterInfo::isVirtualRegister(DstReg)) {
2093 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass);
2096 if (DstReg == AArch64::SP &&
2097 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
2098 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
2107 int llvm::isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
2108 bool *OutUseUnscaledOp,
2109 unsigned *OutUnscaledOp,
2110 int *EmittableOffset) {
2112 bool IsSigned = false;
2113 // The ImmIdx should be changed case by case if it is not 2.
2114 unsigned ImmIdx = 2;
2115 unsigned UnscaledOp = 0;
2116 // Set output values in case of early exit.
2117 if (EmittableOffset)
2118 *EmittableOffset = 0;
2119 if (OutUseUnscaledOp)
2120 *OutUseUnscaledOp = false;
2123 switch (MI.getOpcode()) {
2125 llvm_unreachable("unhandled opcode in rewriteAArch64FrameIndex");
2126 // Vector spills/fills can't take an immediate offset.
2127 case AArch64::LD1Twov2d:
2128 case AArch64::LD1Threev2d:
2129 case AArch64::LD1Fourv2d:
2130 case AArch64::LD1Twov1d:
2131 case AArch64::LD1Threev1d:
2132 case AArch64::LD1Fourv1d:
2133 case AArch64::ST1Twov2d:
2134 case AArch64::ST1Threev2d:
2135 case AArch64::ST1Fourv2d:
2136 case AArch64::ST1Twov1d:
2137 case AArch64::ST1Threev1d:
2138 case AArch64::ST1Fourv1d:
2139 return AArch64FrameOffsetCannotUpdate;
2140 case AArch64::PRFMui:
2142 UnscaledOp = AArch64::PRFUMi;
2144 case AArch64::LDRXui:
2146 UnscaledOp = AArch64::LDURXi;
2148 case AArch64::LDRWui:
2150 UnscaledOp = AArch64::LDURWi;
2152 case AArch64::LDRBui:
2154 UnscaledOp = AArch64::LDURBi;
2156 case AArch64::LDRHui:
2158 UnscaledOp = AArch64::LDURHi;
2160 case AArch64::LDRSui:
2162 UnscaledOp = AArch64::LDURSi;
2164 case AArch64::LDRDui:
2166 UnscaledOp = AArch64::LDURDi;
2168 case AArch64::LDRQui:
2170 UnscaledOp = AArch64::LDURQi;
2172 case AArch64::LDRBBui:
2174 UnscaledOp = AArch64::LDURBBi;
2176 case AArch64::LDRHHui:
2178 UnscaledOp = AArch64::LDURHHi;
2180 case AArch64::LDRSBXui:
2182 UnscaledOp = AArch64::LDURSBXi;
2184 case AArch64::LDRSBWui:
2186 UnscaledOp = AArch64::LDURSBWi;
2188 case AArch64::LDRSHXui:
2190 UnscaledOp = AArch64::LDURSHXi;
2192 case AArch64::LDRSHWui:
2194 UnscaledOp = AArch64::LDURSHWi;
2196 case AArch64::LDRSWui:
2198 UnscaledOp = AArch64::LDURSWi;
2201 case AArch64::STRXui:
2203 UnscaledOp = AArch64::STURXi;
2205 case AArch64::STRWui:
2207 UnscaledOp = AArch64::STURWi;
2209 case AArch64::STRBui:
2211 UnscaledOp = AArch64::STURBi;
2213 case AArch64::STRHui:
2215 UnscaledOp = AArch64::STURHi;
2217 case AArch64::STRSui:
2219 UnscaledOp = AArch64::STURSi;
2221 case AArch64::STRDui:
2223 UnscaledOp = AArch64::STURDi;
2225 case AArch64::STRQui:
2227 UnscaledOp = AArch64::STURQi;
2229 case AArch64::STRBBui:
2231 UnscaledOp = AArch64::STURBBi;
2233 case AArch64::STRHHui:
2235 UnscaledOp = AArch64::STURHHi;
2238 case AArch64::LDPXi:
2239 case AArch64::LDPDi:
2240 case AArch64::STPXi:
2241 case AArch64::STPDi:
2245 case AArch64::LDPQi:
2246 case AArch64::STPQi:
2250 case AArch64::LDPWi:
2251 case AArch64::LDPSi:
2252 case AArch64::STPWi:
2253 case AArch64::STPSi:
2258 case AArch64::LDURXi:
2259 case AArch64::LDURWi:
2260 case AArch64::LDURBi:
2261 case AArch64::LDURHi:
2262 case AArch64::LDURSi:
2263 case AArch64::LDURDi:
2264 case AArch64::LDURQi:
2265 case AArch64::LDURHHi:
2266 case AArch64::LDURBBi:
2267 case AArch64::LDURSBXi:
2268 case AArch64::LDURSBWi:
2269 case AArch64::LDURSHXi:
2270 case AArch64::LDURSHWi:
2271 case AArch64::LDURSWi:
2272 case AArch64::STURXi:
2273 case AArch64::STURWi:
2274 case AArch64::STURBi:
2275 case AArch64::STURHi:
2276 case AArch64::STURSi:
2277 case AArch64::STURDi:
2278 case AArch64::STURQi:
2279 case AArch64::STURBBi:
2280 case AArch64::STURHHi:
2285 Offset += MI.getOperand(ImmIdx).getImm() * Scale;
2287 bool useUnscaledOp = false;
2288 // If the offset doesn't match the scale, we rewrite the instruction to
2289 // use the unscaled instruction instead. Likewise, if we have a negative
2290 // offset (and have an unscaled op to use).
2291 if ((Offset & (Scale - 1)) != 0 || (Offset < 0 && UnscaledOp != 0))
2292 useUnscaledOp = true;
2294 // Use an unscaled addressing mode if the instruction has a negative offset
2295 // (or if the instruction is already using an unscaled addressing mode).
2298 // ldp/stp instructions.
2301 } else if (UnscaledOp == 0 || useUnscaledOp) {
2311 // Attempt to fold address computation.
2312 int MaxOff = (1 << (MaskBits - IsSigned)) - 1;
2313 int MinOff = (IsSigned ? (-MaxOff - 1) : 0);
2314 if (Offset >= MinOff && Offset <= MaxOff) {
2315 if (EmittableOffset)
2316 *EmittableOffset = Offset;
2319 int NewOff = Offset < 0 ? MinOff : MaxOff;
2320 if (EmittableOffset)
2321 *EmittableOffset = NewOff;
2322 Offset = (Offset - NewOff) * Scale;
2324 if (OutUseUnscaledOp)
2325 *OutUseUnscaledOp = useUnscaledOp;
2327 *OutUnscaledOp = UnscaledOp;
2328 return AArch64FrameOffsetCanUpdate |
2329 (Offset == 0 ? AArch64FrameOffsetIsLegal : 0);
2332 bool llvm::rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2333 unsigned FrameReg, int &Offset,
2334 const AArch64InstrInfo *TII) {
2335 unsigned Opcode = MI.getOpcode();
2336 unsigned ImmIdx = FrameRegIdx + 1;
2338 if (Opcode == AArch64::ADDSXri || Opcode == AArch64::ADDXri) {
2339 Offset += MI.getOperand(ImmIdx).getImm();
2340 emitFrameOffset(*MI.getParent(), MI, MI.getDebugLoc(),
2341 MI.getOperand(0).getReg(), FrameReg, Offset, TII,
2342 MachineInstr::NoFlags, (Opcode == AArch64::ADDSXri));
2343 MI.eraseFromParent();
2349 unsigned UnscaledOp;
2351 int Status = isAArch64FrameOffsetLegal(MI, Offset, &UseUnscaledOp,
2352 &UnscaledOp, &NewOffset);
2353 if (Status & AArch64FrameOffsetCanUpdate) {
2354 if (Status & AArch64FrameOffsetIsLegal)
2355 // Replace the FrameIndex with FrameReg.
2356 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2358 MI.setDesc(TII->get(UnscaledOp));
2360 MI.getOperand(ImmIdx).ChangeToImmediate(NewOffset);
2367 void AArch64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
2368 NopInst.setOpcode(AArch64::HINT);
2369 NopInst.addOperand(MCOperand::CreateImm(0));
2371 /// useMachineCombiner - return true when a target supports MachineCombiner
2372 bool AArch64InstrInfo::useMachineCombiner() const {
2373 // AArch64 supports the combiner
2377 // True when Opc sets flag
2378 static bool isCombineInstrSettingFlag(unsigned Opc) {
2380 case AArch64::ADDSWrr:
2381 case AArch64::ADDSWri:
2382 case AArch64::ADDSXrr:
2383 case AArch64::ADDSXri:
2384 case AArch64::SUBSWrr:
2385 case AArch64::SUBSXrr:
2386 // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi.
2387 case AArch64::SUBSWri:
2388 case AArch64::SUBSXri:
2396 // 32b Opcodes that can be combined with a MUL
2397 static bool isCombineInstrCandidate32(unsigned Opc) {
2399 case AArch64::ADDWrr:
2400 case AArch64::ADDWri:
2401 case AArch64::SUBWrr:
2402 case AArch64::ADDSWrr:
2403 case AArch64::ADDSWri:
2404 case AArch64::SUBSWrr:
2405 // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi.
2406 case AArch64::SUBWri:
2407 case AArch64::SUBSWri:
2415 // 64b Opcodes that can be combined with a MUL
2416 static bool isCombineInstrCandidate64(unsigned Opc) {
2418 case AArch64::ADDXrr:
2419 case AArch64::ADDXri:
2420 case AArch64::SUBXrr:
2421 case AArch64::ADDSXrr:
2422 case AArch64::ADDSXri:
2423 case AArch64::SUBSXrr:
2424 // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi.
2425 case AArch64::SUBXri:
2426 case AArch64::SUBSXri:
2434 // Opcodes that can be combined with a MUL
2435 static bool isCombineInstrCandidate(unsigned Opc) {
2436 return (isCombineInstrCandidate32(Opc) || isCombineInstrCandidate64(Opc));
2439 static bool canCombineWithMUL(MachineBasicBlock &MBB, MachineOperand &MO,
2440 unsigned MulOpc, unsigned ZeroReg) {
2441 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2442 MachineInstr *MI = nullptr;
2443 // We need a virtual register definition.
2444 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
2445 MI = MRI.getUniqueVRegDef(MO.getReg());
2446 // And it needs to be in the trace (otherwise, it won't have a depth).
2447 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != MulOpc)
2450 assert(MI->getNumOperands() >= 4 && MI->getOperand(0).isReg() &&
2451 MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
2452 MI->getOperand(3).isReg() && "MAdd/MSub must have a least 4 regs");
2454 // The third input reg must be zero.
2455 if (MI->getOperand(3).getReg() != ZeroReg)
2458 // Must only used by the user we combine with.
2459 if (!MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
2465 /// hasPattern - return true when there is potentially a faster code sequence
2466 /// for an instruction chain ending in \p Root. All potential patterns are
2468 /// in the \p Pattern vector. Pattern should be sorted in priority order since
2469 /// the pattern evaluator stops checking as soon as it finds a faster sequence.
2471 bool AArch64InstrInfo::hasPattern(
2473 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const {
2474 unsigned Opc = Root.getOpcode();
2475 MachineBasicBlock &MBB = *Root.getParent();
2478 if (!isCombineInstrCandidate(Opc))
2480 if (isCombineInstrSettingFlag(Opc)) {
2481 int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true);
2482 // When NZCV is live bail out.
2485 unsigned NewOpc = convertFlagSettingOpcode(&Root);
2486 // When opcode can't change bail out.
2487 // CHECKME: do we miss any cases for opcode conversion?
2496 case AArch64::ADDWrr:
2497 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
2498 "ADDWrr does not have register operands");
2499 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2501 Pattern.push_back(MachineCombinerPattern::MC_MULADDW_OP1);
2504 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDWrrr,
2506 Pattern.push_back(MachineCombinerPattern::MC_MULADDW_OP2);
2510 case AArch64::ADDXrr:
2511 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2513 Pattern.push_back(MachineCombinerPattern::MC_MULADDX_OP1);
2516 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDXrrr,
2518 Pattern.push_back(MachineCombinerPattern::MC_MULADDX_OP2);
2522 case AArch64::SUBWrr:
2523 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2525 Pattern.push_back(MachineCombinerPattern::MC_MULSUBW_OP1);
2528 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDWrrr,
2530 Pattern.push_back(MachineCombinerPattern::MC_MULSUBW_OP2);
2534 case AArch64::SUBXrr:
2535 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2537 Pattern.push_back(MachineCombinerPattern::MC_MULSUBX_OP1);
2540 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDXrrr,
2542 Pattern.push_back(MachineCombinerPattern::MC_MULSUBX_OP2);
2546 case AArch64::ADDWri:
2547 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2549 Pattern.push_back(MachineCombinerPattern::MC_MULADDWI_OP1);
2553 case AArch64::ADDXri:
2554 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2556 Pattern.push_back(MachineCombinerPattern::MC_MULADDXI_OP1);
2560 case AArch64::SUBWri:
2561 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2563 Pattern.push_back(MachineCombinerPattern::MC_MULSUBWI_OP1);
2567 case AArch64::SUBXri:
2568 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2570 Pattern.push_back(MachineCombinerPattern::MC_MULSUBXI_OP1);
2578 /// genMadd - Generate madd instruction and combine mul and add.
2582 /// ==> MADD R,A,B,C
2583 /// \param Root is the ADD instruction
2584 /// \param [out] InsInstrs is a vector of machine instructions and will
2585 /// contain the generated madd instruction
2586 /// \param IdxMulOpd is index of operand in Root that is the result of
2587 /// the MUL. In the example above IdxMulOpd is 1.
2588 /// \param MaddOpc the opcode fo the madd instruction
2589 static MachineInstr *genMadd(MachineFunction &MF, MachineRegisterInfo &MRI,
2590 const TargetInstrInfo *TII, MachineInstr &Root,
2591 SmallVectorImpl<MachineInstr *> &InsInstrs,
2592 unsigned IdxMulOpd, unsigned MaddOpc,
2593 const TargetRegisterClass *RC) {
2594 assert(IdxMulOpd == 1 || IdxMulOpd == 2);
2596 unsigned IdxOtherOpd = IdxMulOpd == 1 ? 2 : 1;
2597 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
2598 unsigned ResultReg = Root.getOperand(0).getReg();
2599 unsigned SrcReg0 = MUL->getOperand(1).getReg();
2600 bool Src0IsKill = MUL->getOperand(1).isKill();
2601 unsigned SrcReg1 = MUL->getOperand(2).getReg();
2602 bool Src1IsKill = MUL->getOperand(2).isKill();
2603 unsigned SrcReg2 = Root.getOperand(IdxOtherOpd).getReg();
2604 bool Src2IsKill = Root.getOperand(IdxOtherOpd).isKill();
2606 if (TargetRegisterInfo::isVirtualRegister(ResultReg))
2607 MRI.constrainRegClass(ResultReg, RC);
2608 if (TargetRegisterInfo::isVirtualRegister(SrcReg0))
2609 MRI.constrainRegClass(SrcReg0, RC);
2610 if (TargetRegisterInfo::isVirtualRegister(SrcReg1))
2611 MRI.constrainRegClass(SrcReg1, RC);
2612 if (TargetRegisterInfo::isVirtualRegister(SrcReg2))
2613 MRI.constrainRegClass(SrcReg2, RC);
2615 MachineInstrBuilder MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc),
2617 .addReg(SrcReg0, getKillRegState(Src0IsKill))
2618 .addReg(SrcReg1, getKillRegState(Src1IsKill))
2619 .addReg(SrcReg2, getKillRegState(Src2IsKill));
2621 InsInstrs.push_back(MIB);
2625 /// genMaddR - Generate madd instruction and combine mul and add using
2626 /// an extra virtual register
2627 /// Example - an ADD intermediate needs to be stored in a register:
2630 /// ==> ORR V, ZR, Imm
2631 /// ==> MADD R,A,B,V
2632 /// \param Root is the ADD instruction
2633 /// \param [out] InsInstrs is a vector of machine instructions and will
2634 /// contain the generated madd instruction
2635 /// \param IdxMulOpd is index of operand in Root that is the result of
2636 /// the MUL. In the example above IdxMulOpd is 1.
2637 /// \param MaddOpc the opcode fo the madd instruction
2638 /// \param VR is a virtual register that holds the value of an ADD operand
2639 /// (V in the example above).
2640 static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI,
2641 const TargetInstrInfo *TII, MachineInstr &Root,
2642 SmallVectorImpl<MachineInstr *> &InsInstrs,
2643 unsigned IdxMulOpd, unsigned MaddOpc,
2644 unsigned VR, const TargetRegisterClass *RC) {
2645 assert(IdxMulOpd == 1 || IdxMulOpd == 2);
2647 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
2648 unsigned ResultReg = Root.getOperand(0).getReg();
2649 unsigned SrcReg0 = MUL->getOperand(1).getReg();
2650 bool Src0IsKill = MUL->getOperand(1).isKill();
2651 unsigned SrcReg1 = MUL->getOperand(2).getReg();
2652 bool Src1IsKill = MUL->getOperand(2).isKill();
2654 if (TargetRegisterInfo::isVirtualRegister(ResultReg))
2655 MRI.constrainRegClass(ResultReg, RC);
2656 if (TargetRegisterInfo::isVirtualRegister(SrcReg0))
2657 MRI.constrainRegClass(SrcReg0, RC);
2658 if (TargetRegisterInfo::isVirtualRegister(SrcReg1))
2659 MRI.constrainRegClass(SrcReg1, RC);
2660 if (TargetRegisterInfo::isVirtualRegister(VR))
2661 MRI.constrainRegClass(VR, RC);
2663 MachineInstrBuilder MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc),
2665 .addReg(SrcReg0, getKillRegState(Src0IsKill))
2666 .addReg(SrcReg1, getKillRegState(Src1IsKill))
2669 InsInstrs.push_back(MIB);
2673 /// genAlternativeCodeSequence - when hasPattern() finds a pattern
2674 /// this function generates the instructions that could replace the
2675 /// original code sequence
2676 void AArch64InstrInfo::genAlternativeCodeSequence(
2677 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN Pattern,
2678 SmallVectorImpl<MachineInstr *> &InsInstrs,
2679 SmallVectorImpl<MachineInstr *> &DelInstrs,
2680 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
2681 MachineBasicBlock &MBB = *Root.getParent();
2682 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2683 MachineFunction &MF = *MBB.getParent();
2684 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
2687 const TargetRegisterClass *RC;
2693 case MachineCombinerPattern::MC_MULADDW_OP1:
2694 case MachineCombinerPattern::MC_MULADDX_OP1:
2698 // --- Create(MADD);
2699 if (Pattern == MachineCombinerPattern::MC_MULADDW_OP1) {
2700 Opc = AArch64::MADDWrrr;
2701 RC = &AArch64::GPR32RegClass;
2703 Opc = AArch64::MADDXrrr;
2704 RC = &AArch64::GPR64RegClass;
2706 MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
2708 case MachineCombinerPattern::MC_MULADDW_OP2:
2709 case MachineCombinerPattern::MC_MULADDX_OP2:
2713 // --- Create(MADD);
2714 if (Pattern == MachineCombinerPattern::MC_MULADDW_OP2) {
2715 Opc = AArch64::MADDWrrr;
2716 RC = &AArch64::GPR32RegClass;
2718 Opc = AArch64::MADDXrrr;
2719 RC = &AArch64::GPR64RegClass;
2721 MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
2723 case MachineCombinerPattern::MC_MULADDWI_OP1:
2724 case MachineCombinerPattern::MC_MULADDXI_OP1: {
2727 // ==> ORR V, ZR, Imm
2729 // --- Create(MADD);
2730 const TargetRegisterClass *OrrRC;
2731 unsigned BitSize, OrrOpc, ZeroReg;
2732 if (Pattern == MachineCombinerPattern::MC_MULADDWI_OP1) {
2733 OrrOpc = AArch64::ORRWri;
2734 OrrRC = &AArch64::GPR32spRegClass;
2736 ZeroReg = AArch64::WZR;
2737 Opc = AArch64::MADDWrrr;
2738 RC = &AArch64::GPR32RegClass;
2740 OrrOpc = AArch64::ORRXri;
2741 OrrRC = &AArch64::GPR64spRegClass;
2743 ZeroReg = AArch64::XZR;
2744 Opc = AArch64::MADDXrrr;
2745 RC = &AArch64::GPR64RegClass;
2747 unsigned NewVR = MRI.createVirtualRegister(OrrRC);
2748 uint64_t Imm = Root.getOperand(2).getImm();
2750 if (Root.getOperand(3).isImm()) {
2751 unsigned Val = Root.getOperand(3).getImm();
2754 uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
2756 if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
2757 MachineInstrBuilder MIB1 =
2758 BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
2761 InsInstrs.push_back(MIB1);
2762 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
2763 MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
2767 case MachineCombinerPattern::MC_MULSUBW_OP1:
2768 case MachineCombinerPattern::MC_MULSUBX_OP1: {
2772 // ==> MADD R,A,B,V // = -C + A*B
2773 // --- Create(MADD);
2774 const TargetRegisterClass *SubRC;
2775 unsigned SubOpc, ZeroReg;
2776 if (Pattern == MachineCombinerPattern::MC_MULSUBW_OP1) {
2777 SubOpc = AArch64::SUBWrr;
2778 SubRC = &AArch64::GPR32spRegClass;
2779 ZeroReg = AArch64::WZR;
2780 Opc = AArch64::MADDWrrr;
2781 RC = &AArch64::GPR32RegClass;
2783 SubOpc = AArch64::SUBXrr;
2784 SubRC = &AArch64::GPR64spRegClass;
2785 ZeroReg = AArch64::XZR;
2786 Opc = AArch64::MADDXrrr;
2787 RC = &AArch64::GPR64RegClass;
2789 unsigned NewVR = MRI.createVirtualRegister(SubRC);
2791 MachineInstrBuilder MIB1 =
2792 BuildMI(MF, Root.getDebugLoc(), TII->get(SubOpc), NewVR)
2794 .addOperand(Root.getOperand(2));
2795 InsInstrs.push_back(MIB1);
2796 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
2797 MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
2800 case MachineCombinerPattern::MC_MULSUBW_OP2:
2801 case MachineCombinerPattern::MC_MULSUBX_OP2:
2804 // ==> MSUB R,A,B,C (computes C - A*B)
2805 // --- Create(MSUB);
2806 if (Pattern == MachineCombinerPattern::MC_MULSUBW_OP2) {
2807 Opc = AArch64::MSUBWrrr;
2808 RC = &AArch64::GPR32RegClass;
2810 Opc = AArch64::MSUBXrrr;
2811 RC = &AArch64::GPR64RegClass;
2813 MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
2815 case MachineCombinerPattern::MC_MULSUBWI_OP1:
2816 case MachineCombinerPattern::MC_MULSUBXI_OP1: {
2819 // ==> ORR V, ZR, -Imm
2820 // ==> MADD R,A,B,V // = -Imm + A*B
2821 // --- Create(MADD);
2822 const TargetRegisterClass *OrrRC;
2823 unsigned BitSize, OrrOpc, ZeroReg;
2824 if (Pattern == MachineCombinerPattern::MC_MULSUBWI_OP1) {
2825 OrrOpc = AArch64::ORRWri;
2826 OrrRC = &AArch64::GPR32spRegClass;
2828 ZeroReg = AArch64::WZR;
2829 Opc = AArch64::MADDWrrr;
2830 RC = &AArch64::GPR32RegClass;
2832 OrrOpc = AArch64::ORRXri;
2833 OrrRC = &AArch64::GPR64spRegClass;
2835 ZeroReg = AArch64::XZR;
2836 Opc = AArch64::MADDXrrr;
2837 RC = &AArch64::GPR64RegClass;
2839 unsigned NewVR = MRI.createVirtualRegister(OrrRC);
2840 int Imm = Root.getOperand(2).getImm();
2841 if (Root.getOperand(3).isImm()) {
2842 unsigned Val = Root.getOperand(3).getImm();
2845 uint64_t UImm = -Imm << (64 - BitSize) >> (64 - BitSize);
2847 if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
2848 MachineInstrBuilder MIB1 =
2849 BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
2852 InsInstrs.push_back(MIB1);
2853 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
2854 MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
2858 } // end switch (Pattern)
2859 // Record MUL and ADD/SUB for deletion
2860 DelInstrs.push_back(MUL);
2861 DelInstrs.push_back(&Root);
2866 /// \brief Replace csincr-branch sequence by simple conditional branch
2870 /// csinc w9, wzr, wzr, <condition code>
2871 /// tbnz w9, #0, 0x44
2873 /// b.<inverted condition code>
2876 /// csinc w9, wzr, wzr, <condition code>
2877 /// tbz w9, #0, 0x44
2879 /// b.<condition code>
2881 /// \param MI Conditional Branch
2882 /// \return True when the simple conditional branch is generated
2884 bool AArch64InstrInfo::optimizeCondBranch(MachineInstr *MI) const {
2885 bool IsNegativeBranch = false;
2886 bool IsTestAndBranch = false;
2887 unsigned TargetBBInMI = 0;
2888 switch (MI->getOpcode()) {
2890 llvm_unreachable("Unknown branch instruction?");
2897 case AArch64::CBNZW:
2898 case AArch64::CBNZX:
2900 IsNegativeBranch = true;
2905 IsTestAndBranch = true;
2907 case AArch64::TBNZW:
2908 case AArch64::TBNZX:
2910 IsNegativeBranch = true;
2911 IsTestAndBranch = true;
2914 // So we increment a zero register and test for bits other
2915 // than bit 0? Conservatively bail out in case the verifier
2916 // missed this case.
2917 if (IsTestAndBranch && MI->getOperand(1).getImm())
2921 assert(MI->getParent() && "Incomplete machine instruciton\n");
2922 MachineBasicBlock *MBB = MI->getParent();
2923 MachineFunction *MF = MBB->getParent();
2924 MachineRegisterInfo *MRI = &MF->getRegInfo();
2925 unsigned VReg = MI->getOperand(0).getReg();
2926 if (!TargetRegisterInfo::isVirtualRegister(VReg))
2929 MachineInstr *DefMI = MRI->getVRegDef(VReg);
2932 if (!(DefMI->getOpcode() == AArch64::CSINCWr &&
2933 DefMI->getOperand(1).getReg() == AArch64::WZR &&
2934 DefMI->getOperand(2).getReg() == AArch64::WZR) &&
2935 !(DefMI->getOpcode() == AArch64::CSINCXr &&
2936 DefMI->getOperand(1).getReg() == AArch64::XZR &&
2937 DefMI->getOperand(2).getReg() == AArch64::XZR))
2940 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1)
2943 AArch64CC::CondCode CC =
2944 (AArch64CC::CondCode)DefMI->getOperand(3).getImm();
2945 bool CheckOnlyCCWrites = true;
2946 // Convert only when the condition code is not modified between
2947 // the CSINC and the branch. The CC may be used by other
2948 // instructions in between.
2949 if (modifiesConditionCode(DefMI, MI, CheckOnlyCCWrites,
2950 Subtarget.getRegisterInfo()))
2952 MachineBasicBlock &RefToMBB = *MBB;
2953 MachineBasicBlock *TBB = MI->getOperand(TargetBBInMI).getMBB();
2954 DebugLoc DL = MI->getDebugLoc();
2955 if (IsNegativeBranch)
2956 CC = AArch64CC::getInvertedCondCode(CC);
2957 BuildMI(RefToMBB, MI, DL, get(AArch64::Bcc)).addImm(CC).addMBB(TBB);
2958 MI->eraseFromParent();