1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
18 #include "AArch64RegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/CodeGen/MachineCombinerPattern.h"
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
30 class AArch64InstrInfo : public AArch64GenInstrInfo {
31 // Reserve bits in the MachineMemOperand target hint flags, starting at 1.
32 // They will be shifted into MOTargetHintStart when accessed.
33 enum TargetMemOperandFlags {
37 const AArch64RegisterInfo RI;
38 const AArch64Subtarget &Subtarget;
41 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
43 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
44 /// such, whenever a client has an instance of instruction info, it should
45 /// always be able to get register info as well (through this method).
46 const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
48 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
50 bool isAsCheapAsAMove(const MachineInstr *MI) const override;
52 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
53 unsigned &DstReg, unsigned &SubIdx) const override;
55 unsigned isLoadFromStackSlot(const MachineInstr *MI,
56 int &FrameIndex) const override;
57 unsigned isStoreToStackSlot(const MachineInstr *MI,
58 int &FrameIndex) const override;
60 /// Returns true if there is a shiftable register and that the shift value
62 bool hasShiftedReg(const MachineInstr *MI) const;
64 /// Returns true if there is an extendable register and that the extending
65 /// value is non-zero.
66 bool hasExtendedReg(const MachineInstr *MI) const;
68 /// \brief Does this instruction set its full destination register to zero?
69 bool isGPRZero(const MachineInstr *MI) const;
71 /// \brief Does this instruction rename a GPR without modifying bits?
72 bool isGPRCopy(const MachineInstr *MI) const;
74 /// \brief Does this instruction rename an FPR without modifying bits?
75 bool isFPRCopy(const MachineInstr *MI) const;
77 /// Return true if this is load/store scales or extends its register offset.
78 /// This refers to scaling a dynamic index as opposed to scaled immediates.
79 /// MI should be a memory op that allows scaled addressing.
80 bool isScaledAddr(const MachineInstr *MI) const;
82 /// Return true if pairing the given load or store is hinted to be
84 bool isLdStPairSuppressed(const MachineInstr *MI) const;
86 /// Hint that pairing the given load or store is unprofitable.
87 void suppressLdStPair(MachineInstr *MI) const;
89 bool getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
91 const TargetRegisterInfo *TRI) const override;
93 bool enableClusterLoads() const override { return true; }
95 bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt,
96 unsigned NumLoads) const override;
98 bool shouldScheduleAdjacent(MachineInstr *First,
99 MachineInstr *Second) const override;
101 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
102 uint64_t Offset, const MDNode *MDPtr,
104 void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
105 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
106 bool KillSrc, unsigned Opcode,
107 llvm::ArrayRef<unsigned> Indices) const;
108 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
109 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
110 bool KillSrc) const override;
112 void storeRegToStackSlot(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator MBBI, unsigned SrcReg,
114 bool isKill, int FrameIndex,
115 const TargetRegisterClass *RC,
116 const TargetRegisterInfo *TRI) const override;
118 void loadRegFromStackSlot(MachineBasicBlock &MBB,
119 MachineBasicBlock::iterator MBBI, unsigned DestReg,
120 int FrameIndex, const TargetRegisterClass *RC,
121 const TargetRegisterInfo *TRI) const override;
123 using TargetInstrInfo::foldMemoryOperandImpl;
125 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
126 const SmallVectorImpl<unsigned> &Ops,
127 int FrameIndex) const override;
129 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
130 MachineBasicBlock *&FBB,
131 SmallVectorImpl<MachineOperand> &Cond,
132 bool AllowModify = false) const override;
133 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
134 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
135 MachineBasicBlock *FBB,
136 const SmallVectorImpl<MachineOperand> &Cond,
137 DebugLoc DL) const override;
139 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
140 bool canInsertSelect(const MachineBasicBlock &,
141 const SmallVectorImpl<MachineOperand> &Cond, unsigned,
142 unsigned, int &, int &, int &) const override;
143 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
144 DebugLoc DL, unsigned DstReg,
145 const SmallVectorImpl<MachineOperand> &Cond,
146 unsigned TrueReg, unsigned FalseReg) const override;
147 void getNoopForMachoTarget(MCInst &NopInst) const override;
149 /// analyzeCompare - For a comparison instruction, return the source registers
150 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
151 /// Return true if the comparison instruction can be analyzed.
152 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
153 unsigned &SrcReg2, int &CmpMask,
154 int &CmpValue) const override;
155 /// optimizeCompareInstr - Convert the instruction supplying the argument to
156 /// the comparison into one that sets the zero bit in the flags register.
157 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
158 unsigned SrcReg2, int CmpMask, int CmpValue,
159 const MachineRegisterInfo *MRI) const override;
160 /// hasPattern - return true when there is potentially a faster code sequence
161 /// for an instruction chain ending in <Root>. All potential patterns are
163 /// in the <Pattern> array.
164 virtual bool hasPattern(
166 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const;
168 /// genAlternativeCodeSequence - when hasPattern() finds a pattern
169 /// this function generates the instructions that could replace the
170 /// original code sequence
171 virtual void genAlternativeCodeSequence(
172 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
173 SmallVectorImpl<MachineInstr *> &InsInstrs,
174 SmallVectorImpl<MachineInstr *> &DelInstrs,
175 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
176 /// useMachineCombiner - AArch64 supports MachineCombiner
177 virtual bool useMachineCombiner(void) const;
179 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
181 void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL,
182 MachineBasicBlock *TBB,
183 const SmallVectorImpl<MachineOperand> &Cond) const;
186 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
187 /// plus Offset. This is intended to be used from within the prolog/epilog
188 /// insertion (PEI) pass, where a virtual scratch register may be allocated
189 /// if necessary, to be replaced by the scavenger at the end of PEI.
190 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
191 DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
192 const TargetInstrInfo *TII,
193 MachineInstr::MIFlag = MachineInstr::NoFlags,
194 bool SetNZCV = false);
196 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
197 /// FP. Return false if the offset could not be handled directly in MI, and
198 /// return the left-over portion by reference.
199 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
200 unsigned FrameReg, int &Offset,
201 const AArch64InstrInfo *TII);
203 /// \brief Use to report the frame offset status in isAArch64FrameOffsetLegal.
204 enum AArch64FrameOffsetStatus {
205 AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
206 AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
207 AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
210 /// \brief Check if the @p Offset is a valid frame offset for @p MI.
211 /// The returned value reports the validity of the frame offset for @p MI.
212 /// It uses the values defined by AArch64FrameOffsetStatus for that.
213 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
215 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
216 /// rewriten in @p MI.
217 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
218 /// amount that is off the limit of the legal offset.
219 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
220 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
221 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
222 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
223 /// is a legal offset.
224 int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
225 bool *OutUseUnscaledOp = nullptr,
226 unsigned *OutUnscaledOp = nullptr,
227 int *EmittableOffset = nullptr);
229 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
231 static inline bool isCondBranchOpcode(int Opc) {
248 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; }
250 } // end namespace llvm