1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_AARCH64INSTRINFO_H
15 #define LLVM_TARGET_AARCH64INSTRINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "AArch64RegisterInfo.h"
20 #define GET_INSTRINFO_HEADER
21 #include "AArch64GenInstrInfo.inc"
25 class AArch64Subtarget;
27 class AArch64InstrInfo : public AArch64GenInstrInfo {
28 const AArch64RegisterInfo RI;
29 const AArch64Subtarget &Subtarget;
31 explicit AArch64InstrInfo(const AArch64Subtarget &TM);
33 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
34 /// such, whenever a client has an instance of instruction info, it should
35 /// always be able to get register info as well (through this method).
37 const TargetRegisterInfo &getRegisterInfo() const { return RI; }
39 const AArch64Subtarget &getSubTarget() const { return Subtarget; }
41 void copyPhysReg(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator I, DebugLoc DL,
43 unsigned DestReg, unsigned SrcReg,
46 void storeRegToStackSlot(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator MI,
48 unsigned SrcReg, bool isKill, int FrameIndex,
49 const TargetRegisterClass *RC,
50 const TargetRegisterInfo *TRI) const;
51 void loadRegFromStackSlot(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MBBI,
53 unsigned DestReg, int FrameIdx,
54 const TargetRegisterClass *RC,
55 const TargetRegisterInfo *TRI) const;
57 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
58 MachineBasicBlock *&FBB,
59 SmallVectorImpl<MachineOperand> &Cond,
60 bool AllowModify = false) const;
61 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
62 MachineBasicBlock *FBB,
63 const SmallVectorImpl<MachineOperand> &Cond,
65 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
66 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
68 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
70 /// Look through the instructions in this function and work out the largest
71 /// the stack frame can be while maintaining the ability to address local
72 /// slots with no complexities.
73 unsigned estimateRSStackLimit(MachineFunction &MF) const;
75 /// getAddressConstraints - For loads and stores (and PRFMs) taking an
76 /// immediate offset, this function determines the constraints required for
77 /// the immediate. It must satisfy:
78 /// + MinOffset <= imm <= MaxOffset
79 /// + imm % OffsetScale == 0
80 void getAddressConstraints(const MachineInstr &MI, int &AccessScale,
81 int &MinOffset, int &MaxOffset) const;
84 unsigned getInstSizeInBytes(const MachineInstr &MI) const;
86 unsigned getInstBundleLength(const MachineInstr &MI) const;
90 bool rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
91 unsigned FrameReg, int &Offset,
92 const AArch64InstrInfo &TII);
95 void emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
96 DebugLoc dl, const TargetInstrInfo &TII,
97 unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
99 MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags);
101 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
102 DebugLoc dl, const TargetInstrInfo &TII,
103 unsigned ScratchReg, int64_t NumBytes,
104 MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags);