1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
18 #include "AArch64RegisterInfo.h"
19 #include "llvm/CodeGen/MachineCombinerPattern.h"
20 #include "llvm/Target/TargetInstrInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
30 class AArch64InstrInfo : public AArch64GenInstrInfo {
31 // Reserve bits in the MachineMemOperand target hint flags, starting at 1.
32 // They will be shifted into MOTargetHintStart when accessed.
33 enum TargetMemOperandFlags {
37 const AArch64Subtarget &Subtarget;
40 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
42 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
44 bool isAsCheapAsAMove(const MachineInstr *MI) const override;
46 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
47 unsigned &DstReg, unsigned &SubIdx) const override;
50 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
51 AliasAnalysis *AA = nullptr) const override;
53 unsigned isLoadFromStackSlot(const MachineInstr *MI,
54 int &FrameIndex) const override;
55 unsigned isStoreToStackSlot(const MachineInstr *MI,
56 int &FrameIndex) const override;
58 /// Returns true if there is a shiftable register and that the shift value
60 bool hasShiftedReg(const MachineInstr *MI) const;
62 /// Returns true if there is an extendable register and that the extending
63 /// value is non-zero.
64 bool hasExtendedReg(const MachineInstr *MI) const;
66 /// \brief Does this instruction set its full destination register to zero?
67 bool isGPRZero(const MachineInstr *MI) const;
69 /// \brief Does this instruction rename a GPR without modifying bits?
70 bool isGPRCopy(const MachineInstr *MI) const;
72 /// \brief Does this instruction rename an FPR without modifying bits?
73 bool isFPRCopy(const MachineInstr *MI) const;
75 /// Return true if this is load/store scales or extends its register offset.
76 /// This refers to scaling a dynamic index as opposed to scaled immediates.
77 /// MI should be a memory op that allows scaled addressing.
78 bool isScaledAddr(const MachineInstr *MI) const;
80 /// Return true if pairing the given load or store is hinted to be
82 bool isLdStPairSuppressed(const MachineInstr *MI) const;
84 /// Hint that pairing the given load or store is unprofitable.
85 void suppressLdStPair(MachineInstr *MI) const;
87 bool getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
89 const TargetRegisterInfo *TRI) const override;
91 bool getLdStBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
92 int &Offset, int &Width,
93 const TargetRegisterInfo *TRI) const;
95 bool enableClusterLoads() const override { return true; }
97 bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt,
98 unsigned NumLoads) const override;
100 bool shouldScheduleAdjacent(MachineInstr *First,
101 MachineInstr *Second) const override;
103 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
104 uint64_t Offset, const MDNode *Var,
105 const MDNode *Expr, DebugLoc DL) const;
106 void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
107 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
108 bool KillSrc, unsigned Opcode,
109 llvm::ArrayRef<unsigned> Indices) const;
110 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
111 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
112 bool KillSrc) const override;
114 void storeRegToStackSlot(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator MBBI, unsigned SrcReg,
116 bool isKill, int FrameIndex,
117 const TargetRegisterClass *RC,
118 const TargetRegisterInfo *TRI) const override;
120 void loadRegFromStackSlot(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator MBBI, unsigned DestReg,
122 int FrameIndex, const TargetRegisterClass *RC,
123 const TargetRegisterInfo *TRI) const override;
125 using TargetInstrInfo::foldMemoryOperandImpl;
126 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
127 ArrayRef<unsigned> Ops,
128 int FrameIndex) const override;
130 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
131 MachineBasicBlock *&FBB,
132 SmallVectorImpl<MachineOperand> &Cond,
133 bool AllowModify = false) const override;
134 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
135 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
136 MachineBasicBlock *FBB,
137 const SmallVectorImpl<MachineOperand> &Cond,
138 DebugLoc DL) const override;
140 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
141 bool canInsertSelect(const MachineBasicBlock &,
142 const SmallVectorImpl<MachineOperand> &Cond, unsigned,
143 unsigned, int &, int &, int &) const override;
144 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
145 DebugLoc DL, unsigned DstReg,
146 const SmallVectorImpl<MachineOperand> &Cond,
147 unsigned TrueReg, unsigned FalseReg) const override;
148 void getNoopForMachoTarget(MCInst &NopInst) const override;
150 /// analyzeCompare - For a comparison instruction, return the source registers
151 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
152 /// Return true if the comparison instruction can be analyzed.
153 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
154 unsigned &SrcReg2, int &CmpMask,
155 int &CmpValue) const override;
156 /// optimizeCompareInstr - Convert the instruction supplying the argument to
157 /// the comparison into one that sets the zero bit in the flags register.
158 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
159 unsigned SrcReg2, int CmpMask, int CmpValue,
160 const MachineRegisterInfo *MRI) const override;
161 bool optimizeCondBranch(MachineInstr *MI) const override;
162 /// hasPattern - return true when there is potentially a faster code sequence
163 /// for an instruction chain ending in <Root>. All potential patterns are
165 /// in the <Pattern> array.
166 bool hasPattern(MachineInstr &Root,
167 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern)
170 /// genAlternativeCodeSequence - when hasPattern() finds a pattern
171 /// this function generates the instructions that could replace the
172 /// original code sequence
173 void genAlternativeCodeSequence(
174 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
175 SmallVectorImpl<MachineInstr *> &InsInstrs,
176 SmallVectorImpl<MachineInstr *> &DelInstrs,
177 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
178 /// useMachineCombiner - AArch64 supports MachineCombiner
179 bool useMachineCombiner() const override;
181 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
183 void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL,
184 MachineBasicBlock *TBB,
185 const SmallVectorImpl<MachineOperand> &Cond) const;
188 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
189 /// plus Offset. This is intended to be used from within the prolog/epilog
190 /// insertion (PEI) pass, where a virtual scratch register may be allocated
191 /// if necessary, to be replaced by the scavenger at the end of PEI.
192 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
193 DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
194 const TargetInstrInfo *TII,
195 MachineInstr::MIFlag = MachineInstr::NoFlags,
196 bool SetNZCV = false);
198 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
199 /// FP. Return false if the offset could not be handled directly in MI, and
200 /// return the left-over portion by reference.
201 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
202 unsigned FrameReg, int &Offset,
203 const AArch64InstrInfo *TII);
205 /// \brief Use to report the frame offset status in isAArch64FrameOffsetLegal.
206 enum AArch64FrameOffsetStatus {
207 AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
208 AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
209 AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
212 /// \brief Check if the @p Offset is a valid frame offset for @p MI.
213 /// The returned value reports the validity of the frame offset for @p MI.
214 /// It uses the values defined by AArch64FrameOffsetStatus for that.
215 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
217 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
218 /// rewriten in @p MI.
219 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
220 /// amount that is off the limit of the legal offset.
221 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
222 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
223 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
224 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
225 /// is a legal offset.
226 int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
227 bool *OutUseUnscaledOp = nullptr,
228 unsigned *OutUnscaledOp = nullptr,
229 int *EmittableOffset = nullptr);
231 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
233 static inline bool isCondBranchOpcode(int Opc) {
250 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; }
252 } // end namespace llvm