1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
27 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
29 //===----------------------------------------------------------------------===//
30 // AArch64-specific DAG Nodes.
33 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
34 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
39 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
40 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
46 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
47 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
54 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
55 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
57 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
58 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
59 SDTCisVT<2, OtherVT>]>;
62 def SDT_AArch64CSel : SDTypeProfile<1, 4,
67 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
70 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
71 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
72 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
75 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
76 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
77 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
78 SDTCisInt<2>, SDTCisInt<3>]>;
79 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
80 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
82 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
84 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
85 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
86 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
87 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
89 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
92 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
93 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
95 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
97 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
99 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
100 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
101 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
102 SDTCisSameAs<1, 4>]>;
106 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
107 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
108 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
109 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
110 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
111 [SDNPHasChain, SDNPOutGlue]>;
112 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
113 SDCallSeqEnd<[ SDTCisVT<0, i32>,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
116 def AArch64call : SDNode<"AArch64ISD::CALL",
117 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
122 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
124 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
126 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
128 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
132 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
133 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
134 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
135 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
136 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
137 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
138 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
139 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
140 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
142 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
143 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
145 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
146 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
148 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
150 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
152 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
153 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
155 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
156 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
157 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
158 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
159 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
161 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
162 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
163 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
164 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
165 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
166 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
168 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
169 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
170 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
171 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
172 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
173 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
174 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
176 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
177 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
178 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
179 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
181 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
182 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
183 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
184 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
185 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
186 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
187 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
188 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
190 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
191 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
192 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
194 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
195 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
196 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
197 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
198 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
200 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
201 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
202 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
204 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
205 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
206 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
207 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
208 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
209 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
210 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
212 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
213 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
214 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
215 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
216 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
218 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
219 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
221 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
223 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
224 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
226 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
227 [SDNPHasChain, SDNPSideEffect]>;
229 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
230 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
232 def AArch64tlsdesc_call : SDNode<"AArch64ISD::TLSDESC_CALL",
233 SDT_AArch64TLSDescCall,
234 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
237 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
238 SDT_AArch64WrapperLarge>;
240 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
242 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
243 SDTCisSameAs<1, 2>]>;
244 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
245 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
247 //===----------------------------------------------------------------------===//
249 //===----------------------------------------------------------------------===//
251 // AArch64 Instruction Predicate Definitions.
253 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
254 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
255 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
256 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
257 def ForCodeSize : Predicate<"ForCodeSize">;
258 def NotForCodeSize : Predicate<"!ForCodeSize">;
260 include "AArch64InstrFormats.td"
262 //===----------------------------------------------------------------------===//
264 //===----------------------------------------------------------------------===//
265 // Miscellaneous instructions.
266 //===----------------------------------------------------------------------===//
268 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
269 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
270 [(AArch64callseq_start timm:$amt)]>;
271 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
272 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
273 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
275 let isReMaterializable = 1, isCodeGenOnly = 1 in {
276 // FIXME: The following pseudo instructions are only needed because remat
277 // cannot handle multiple instructions. When that changes, they can be
278 // removed, along with the AArch64Wrapper node.
280 let AddedComplexity = 10 in
281 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
282 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
285 // The MOVaddr instruction should match only when the add is not folded
286 // into a load or store address.
288 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
289 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
290 tglobaladdr:$low))]>,
291 Sched<[WriteAdrAdr]>;
293 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
294 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
296 Sched<[WriteAdrAdr]>;
298 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
299 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
301 Sched<[WriteAdrAdr]>;
303 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
304 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
305 tblockaddress:$low))]>,
306 Sched<[WriteAdrAdr]>;
308 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
309 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
310 tglobaltlsaddr:$low))]>,
311 Sched<[WriteAdrAdr]>;
313 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
314 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
315 texternalsym:$low))]>,
316 Sched<[WriteAdrAdr]>;
318 } // isReMaterializable, isCodeGenOnly
320 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
321 (LOADgot tglobaltlsaddr:$addr)>;
323 def : Pat<(AArch64LOADgot texternalsym:$addr),
324 (LOADgot texternalsym:$addr)>;
326 def : Pat<(AArch64LOADgot tconstpool:$addr),
327 (LOADgot tconstpool:$addr)>;
329 //===----------------------------------------------------------------------===//
330 // System instructions.
331 //===----------------------------------------------------------------------===//
333 def HINT : HintI<"hint">;
334 def : InstAlias<"nop", (HINT 0b000)>;
335 def : InstAlias<"yield",(HINT 0b001)>;
336 def : InstAlias<"wfe", (HINT 0b010)>;
337 def : InstAlias<"wfi", (HINT 0b011)>;
338 def : InstAlias<"sev", (HINT 0b100)>;
339 def : InstAlias<"sevl", (HINT 0b101)>;
341 // As far as LLVM is concerned this writes to the system's exclusive monitors.
342 let mayLoad = 1, mayStore = 1 in
343 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
345 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
346 // model patterns with sufficiently fine granularity.
347 let mayLoad = ?, mayStore = ? in {
348 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
349 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
351 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
352 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
354 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
355 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
358 def : InstAlias<"clrex", (CLREX 0xf)>;
359 def : InstAlias<"isb", (ISB 0xf)>;
363 def MSRpstate: MSRpstateI;
365 // The thread pointer (on Linux, at least, where this has been implemented) is
367 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
369 // Generic system instructions
370 def SYSxt : SystemXtI<0, "sys">;
371 def SYSLxt : SystemLXtI<1, "sysl">;
373 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
374 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
375 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
377 //===----------------------------------------------------------------------===//
378 // Move immediate instructions.
379 //===----------------------------------------------------------------------===//
381 defm MOVK : InsertImmediate<0b11, "movk">;
382 defm MOVN : MoveImmediate<0b00, "movn">;
384 let PostEncoderMethod = "fixMOVZ" in
385 defm MOVZ : MoveImmediate<0b10, "movz">;
387 // First group of aliases covers an implicit "lsl #0".
388 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
389 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
390 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
391 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
392 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
393 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
395 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
396 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
397 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
398 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
399 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
401 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
402 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
403 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
404 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
406 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
407 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
408 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
409 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
411 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
412 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
414 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
415 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
417 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
418 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
420 // Final group of aliases covers true "mov $Rd, $imm" cases.
421 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
422 int width, int shift> {
423 def _asmoperand : AsmOperandClass {
424 let Name = basename # width # "_lsl" # shift # "MovAlias";
425 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
427 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
430 def _movimm : Operand<i32> {
431 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
434 def : InstAlias<"mov $Rd, $imm",
435 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
438 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
439 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
441 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
442 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
443 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
444 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
446 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
447 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
449 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
450 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
451 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
452 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
454 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
455 isAsCheapAsAMove = 1 in {
456 // FIXME: The following pseudo instructions are only needed because remat
457 // cannot handle multiple instructions. When that changes, we can select
458 // directly to the real instructions and get rid of these pseudos.
461 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
462 [(set GPR32:$dst, imm:$src)]>,
465 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
466 [(set GPR64:$dst, imm:$src)]>,
468 } // isReMaterializable, isCodeGenOnly
470 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
471 // eventual expansion code fewer bits to worry about getting right. Marshalling
472 // the types is a little tricky though:
473 def i64imm_32bit : ImmLeaf<i64, [{
474 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
477 def trunc_imm : SDNodeXForm<imm, [{
478 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
481 def : Pat<(i64 i64imm_32bit:$src),
482 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
484 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
485 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
486 return CurDAG->getTargetConstant(
487 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
490 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
491 return CurDAG->getTargetConstant(
492 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
496 def : Pat<(f32 fpimm:$in),
497 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
498 def : Pat<(f64 fpimm:$in),
499 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
502 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
504 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
505 tglobaladdr:$g1, tglobaladdr:$g0),
506 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
507 tglobaladdr:$g2, 32),
508 tglobaladdr:$g1, 16),
509 tglobaladdr:$g0, 0)>;
511 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
512 tblockaddress:$g1, tblockaddress:$g0),
513 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
514 tblockaddress:$g2, 32),
515 tblockaddress:$g1, 16),
516 tblockaddress:$g0, 0)>;
518 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
519 tconstpool:$g1, tconstpool:$g0),
520 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
525 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
526 tjumptable:$g1, tjumptable:$g0),
527 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
533 //===----------------------------------------------------------------------===//
534 // Arithmetic instructions.
535 //===----------------------------------------------------------------------===//
537 // Add/subtract with carry.
538 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
539 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
541 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
542 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
543 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
544 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
547 defm ADD : AddSub<0, "add", add>;
548 defm SUB : AddSub<1, "sub">;
550 def : InstAlias<"mov $dst, $src",
551 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
552 def : InstAlias<"mov $dst, $src",
553 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
554 def : InstAlias<"mov $dst, $src",
555 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
556 def : InstAlias<"mov $dst, $src",
557 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
559 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
560 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
562 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
563 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
564 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
565 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
566 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
567 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
568 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
569 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
570 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
571 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
572 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
573 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
574 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
575 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
576 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
577 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
578 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
580 // Because of the immediate format for add/sub-imm instructions, the
581 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
582 // These patterns capture that transformation.
583 let AddedComplexity = 1 in {
584 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
585 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
586 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
587 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
588 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
589 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
590 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
591 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
594 // Because of the immediate format for add/sub-imm instructions, the
595 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
596 // These patterns capture that transformation.
597 let AddedComplexity = 1 in {
598 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
599 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
600 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
601 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
602 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
603 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
604 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
605 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
608 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
609 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
610 def : InstAlias<"neg $dst, $src$shift",
611 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
612 def : InstAlias<"neg $dst, $src$shift",
613 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
615 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
616 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
617 def : InstAlias<"negs $dst, $src$shift",
618 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
619 def : InstAlias<"negs $dst, $src$shift",
620 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
623 // Unsigned/Signed divide
624 defm UDIV : Div<0, "udiv", udiv>;
625 defm SDIV : Div<1, "sdiv", sdiv>;
626 let isCodeGenOnly = 1 in {
627 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
628 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
632 defm ASRV : Shift<0b10, "asr", sra>;
633 defm LSLV : Shift<0b00, "lsl", shl>;
634 defm LSRV : Shift<0b01, "lsr", srl>;
635 defm RORV : Shift<0b11, "ror", rotr>;
637 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
638 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
639 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
640 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
641 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
642 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
643 def : ShiftAlias<"rorv", RORVWr, GPR32>;
644 def : ShiftAlias<"rorv", RORVXr, GPR64>;
647 let AddedComplexity = 7 in {
648 defm MADD : MulAccum<0, "madd", add>;
649 defm MSUB : MulAccum<1, "msub", sub>;
651 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
652 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
653 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
654 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
656 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
657 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
658 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
659 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
660 } // AddedComplexity = 7
662 let AddedComplexity = 5 in {
663 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
664 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
665 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
666 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
668 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
669 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
670 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
671 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
673 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
674 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
675 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
676 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
677 } // AddedComplexity = 5
679 def : MulAccumWAlias<"mul", MADDWrrr>;
680 def : MulAccumXAlias<"mul", MADDXrrr>;
681 def : MulAccumWAlias<"mneg", MSUBWrrr>;
682 def : MulAccumXAlias<"mneg", MSUBXrrr>;
683 def : WideMulAccumAlias<"smull", SMADDLrrr>;
684 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
685 def : WideMulAccumAlias<"umull", UMADDLrrr>;
686 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
689 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
690 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
693 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
694 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
695 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
696 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
698 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
699 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
700 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
701 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
704 //===----------------------------------------------------------------------===//
705 // Logical instructions.
706 //===----------------------------------------------------------------------===//
709 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
710 defm AND : LogicalImm<0b00, "and", and, "bic">;
711 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
712 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
714 // FIXME: these aliases *are* canonical sometimes (when movz can't be
715 // used). Actually, it seems to be working right now, but putting logical_immXX
716 // here is a bit dodgy on the AsmParser side too.
717 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
718 logical_imm32:$imm), 0>;
719 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
720 logical_imm64:$imm), 0>;
724 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
725 defm BICS : LogicalRegS<0b11, 1, "bics",
726 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
727 defm AND : LogicalReg<0b00, 0, "and", and>;
728 defm BIC : LogicalReg<0b00, 1, "bic",
729 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
730 defm EON : LogicalReg<0b10, 1, "eon",
731 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
732 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
733 defm ORN : LogicalReg<0b01, 1, "orn",
734 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
735 defm ORR : LogicalReg<0b01, 0, "orr", or>;
737 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
738 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
740 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
741 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
743 def : InstAlias<"mvn $Wd, $Wm$sh",
744 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
745 def : InstAlias<"mvn $Xd, $Xm$sh",
746 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
748 def : InstAlias<"tst $src1, $src2",
749 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
750 def : InstAlias<"tst $src1, $src2",
751 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
753 def : InstAlias<"tst $src1, $src2",
754 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
755 def : InstAlias<"tst $src1, $src2",
756 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
758 def : InstAlias<"tst $src1, $src2$sh",
759 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
760 def : InstAlias<"tst $src1, $src2$sh",
761 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
764 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
765 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
768 //===----------------------------------------------------------------------===//
769 // One operand data processing instructions.
770 //===----------------------------------------------------------------------===//
772 defm CLS : OneOperandData<0b101, "cls">;
773 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
774 defm RBIT : OneOperandData<0b000, "rbit">;
776 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
777 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
779 def REV16Wr : OneWRegData<0b001, "rev16",
780 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
781 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
783 def : Pat<(cttz GPR32:$Rn),
784 (CLZWr (RBITWr GPR32:$Rn))>;
785 def : Pat<(cttz GPR64:$Rn),
786 (CLZXr (RBITXr GPR64:$Rn))>;
787 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
790 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
794 // Unlike the other one operand instructions, the instructions with the "rev"
795 // mnemonic do *not* just different in the size bit, but actually use different
796 // opcode bits for the different sizes.
797 def REVWr : OneWRegData<0b010, "rev", bswap>;
798 def REVXr : OneXRegData<0b011, "rev", bswap>;
799 def REV32Xr : OneXRegData<0b010, "rev32",
800 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
802 // The bswap commutes with the rotr so we want a pattern for both possible
804 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
805 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
807 //===----------------------------------------------------------------------===//
808 // Bitfield immediate extraction instruction.
809 //===----------------------------------------------------------------------===//
810 let hasSideEffects = 0 in
811 defm EXTR : ExtractImm<"extr">;
812 def : InstAlias<"ror $dst, $src, $shift",
813 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
814 def : InstAlias<"ror $dst, $src, $shift",
815 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
817 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
818 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
819 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
820 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
822 //===----------------------------------------------------------------------===//
823 // Other bitfield immediate instructions.
824 //===----------------------------------------------------------------------===//
825 let hasSideEffects = 0 in {
826 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
827 defm SBFM : BitfieldImm<0b00, "sbfm">;
828 defm UBFM : BitfieldImm<0b10, "ubfm">;
831 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
832 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
833 return CurDAG->getTargetConstant(enc, MVT::i64);
836 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
837 uint64_t enc = 31 - N->getZExtValue();
838 return CurDAG->getTargetConstant(enc, MVT::i64);
841 // min(7, 31 - shift_amt)
842 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
843 uint64_t enc = 31 - N->getZExtValue();
844 enc = enc > 7 ? 7 : enc;
845 return CurDAG->getTargetConstant(enc, MVT::i64);
848 // min(15, 31 - shift_amt)
849 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
850 uint64_t enc = 31 - N->getZExtValue();
851 enc = enc > 15 ? 15 : enc;
852 return CurDAG->getTargetConstant(enc, MVT::i64);
855 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
856 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
857 return CurDAG->getTargetConstant(enc, MVT::i64);
860 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
861 uint64_t enc = 63 - N->getZExtValue();
862 return CurDAG->getTargetConstant(enc, MVT::i64);
865 // min(7, 63 - shift_amt)
866 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
867 uint64_t enc = 63 - N->getZExtValue();
868 enc = enc > 7 ? 7 : enc;
869 return CurDAG->getTargetConstant(enc, MVT::i64);
872 // min(15, 63 - shift_amt)
873 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
874 uint64_t enc = 63 - N->getZExtValue();
875 enc = enc > 15 ? 15 : enc;
876 return CurDAG->getTargetConstant(enc, MVT::i64);
879 // min(31, 63 - shift_amt)
880 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
881 uint64_t enc = 63 - N->getZExtValue();
882 enc = enc > 31 ? 31 : enc;
883 return CurDAG->getTargetConstant(enc, MVT::i64);
886 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
887 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
888 (i64 (i32shift_b imm0_31:$imm)))>;
889 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
890 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
891 (i64 (i64shift_b imm0_63:$imm)))>;
893 let AddedComplexity = 10 in {
894 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
895 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
896 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
897 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
900 def : InstAlias<"asr $dst, $src, $shift",
901 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
902 def : InstAlias<"asr $dst, $src, $shift",
903 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
904 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
905 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
906 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
907 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
908 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
910 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
911 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
912 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
913 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
915 def : InstAlias<"lsr $dst, $src, $shift",
916 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
917 def : InstAlias<"lsr $dst, $src, $shift",
918 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
919 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
920 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
921 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
922 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
923 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
925 //===----------------------------------------------------------------------===//
926 // Conditionally set flags instructions.
927 //===----------------------------------------------------------------------===//
928 defm CCMN : CondSetFlagsImm<0, "ccmn">;
929 defm CCMP : CondSetFlagsImm<1, "ccmp">;
931 defm CCMN : CondSetFlagsReg<0, "ccmn">;
932 defm CCMP : CondSetFlagsReg<1, "ccmp">;
934 //===----------------------------------------------------------------------===//
935 // Conditional select instructions.
936 //===----------------------------------------------------------------------===//
937 defm CSEL : CondSelect<0, 0b00, "csel">;
939 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
940 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
941 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
942 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
944 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
945 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
946 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
947 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
948 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
949 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
950 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
951 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
952 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
953 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
954 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
955 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
957 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
958 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
959 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
960 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
961 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
962 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
963 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
964 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
966 // The inverse of the condition code from the alias instruction is what is used
967 // in the aliased instruction. The parser all ready inverts the condition code
968 // for these aliases.
969 def : InstAlias<"cset $dst, $cc",
970 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
971 def : InstAlias<"cset $dst, $cc",
972 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
974 def : InstAlias<"csetm $dst, $cc",
975 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
976 def : InstAlias<"csetm $dst, $cc",
977 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
979 def : InstAlias<"cinc $dst, $src, $cc",
980 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
981 def : InstAlias<"cinc $dst, $src, $cc",
982 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
984 def : InstAlias<"cinv $dst, $src, $cc",
985 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
986 def : InstAlias<"cinv $dst, $src, $cc",
987 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
989 def : InstAlias<"cneg $dst, $src, $cc",
990 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
991 def : InstAlias<"cneg $dst, $src, $cc",
992 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
994 //===----------------------------------------------------------------------===//
995 // PC-relative instructions.
996 //===----------------------------------------------------------------------===//
997 let isReMaterializable = 1 in {
998 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
999 def ADR : ADRI<0, "adr", adrlabel, []>;
1000 } // hasSideEffects = 0
1002 def ADRP : ADRI<1, "adrp", adrplabel,
1003 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1004 } // isReMaterializable = 1
1006 // page address of a constant pool entry, block address
1007 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1008 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1010 //===----------------------------------------------------------------------===//
1011 // Unconditional branch (register) instructions.
1012 //===----------------------------------------------------------------------===//
1014 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1015 def RET : BranchReg<0b0010, "ret", []>;
1016 def DRPS : SpecialReturn<0b0101, "drps">;
1017 def ERET : SpecialReturn<0b0100, "eret">;
1018 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1020 // Default to the LR register.
1021 def : InstAlias<"ret", (RET LR)>;
1023 let isCall = 1, Defs = [LR], Uses = [SP] in {
1024 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1027 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1028 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1029 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1031 // Create a separate pseudo-instruction for codegen to use so that we don't
1032 // flag lr as used in every function. It'll be restored before the RET by the
1033 // epilogue if it's legitimately used.
1034 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1035 let isTerminator = 1;
1040 // This is a directive-like pseudo-instruction. The purpose is to insert an
1041 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1042 // (which in the usual case is a BLR).
1043 let hasSideEffects = 1 in
1044 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1045 let AsmString = ".tlsdesccall $sym";
1048 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
1049 // gets expanded to two MCInsts during lowering.
1050 let isCall = 1, Defs = [LR] in
1052 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
1053 [(AArch64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
1055 def : Pat<(AArch64tlsdesc_call GPR64:$dest, texternalsym:$sym),
1056 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
1057 //===----------------------------------------------------------------------===//
1058 // Conditional branch (immediate) instruction.
1059 //===----------------------------------------------------------------------===//
1060 def Bcc : BranchCond;
1062 //===----------------------------------------------------------------------===//
1063 // Compare-and-branch instructions.
1064 //===----------------------------------------------------------------------===//
1065 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1066 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1068 //===----------------------------------------------------------------------===//
1069 // Test-bit-and-branch instructions.
1070 //===----------------------------------------------------------------------===//
1071 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1072 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1074 //===----------------------------------------------------------------------===//
1075 // Unconditional branch (immediate) instructions.
1076 //===----------------------------------------------------------------------===//
1077 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1078 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1079 } // isBranch, isTerminator, isBarrier
1081 let isCall = 1, Defs = [LR], Uses = [SP] in {
1082 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1084 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1086 //===----------------------------------------------------------------------===//
1087 // Exception generation instructions.
1088 //===----------------------------------------------------------------------===//
1089 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1090 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1091 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1092 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1093 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1094 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1095 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1096 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1098 // DCPSn defaults to an immediate operand of zero if unspecified.
1099 def : InstAlias<"dcps1", (DCPS1 0)>;
1100 def : InstAlias<"dcps2", (DCPS2 0)>;
1101 def : InstAlias<"dcps3", (DCPS3 0)>;
1103 //===----------------------------------------------------------------------===//
1104 // Load instructions.
1105 //===----------------------------------------------------------------------===//
1107 // Pair (indexed, offset)
1108 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1109 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1110 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1111 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1112 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1114 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1116 // Pair (pre-indexed)
1117 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1118 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1119 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1120 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1121 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1123 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1125 // Pair (post-indexed)
1126 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1127 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1128 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1129 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1130 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1132 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1135 // Pair (no allocate)
1136 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1137 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1138 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1139 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1140 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1143 // (register offset)
1147 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1148 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1149 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1150 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1153 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1154 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1155 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1156 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1157 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1159 // Load sign-extended half-word
1160 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1161 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1163 // Load sign-extended byte
1164 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1165 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1167 // Load sign-extended word
1168 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1171 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1173 // For regular load, we do not have any alignment requirement.
1174 // Thus, it is safe to directly map the vector loads with interesting
1175 // addressing modes.
1176 // FIXME: We could do the same for bitconvert to floating point vectors.
1177 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1178 ValueType ScalTy, ValueType VecTy,
1179 Instruction LOADW, Instruction LOADX,
1181 def : Pat<(VecTy (scalar_to_vector (ScalTy
1182 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1183 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1184 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1187 def : Pat<(VecTy (scalar_to_vector (ScalTy
1188 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1189 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1190 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1194 let AddedComplexity = 10 in {
1195 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1196 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1198 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1199 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1201 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1202 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1204 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1205 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1207 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1208 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1210 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1212 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1215 def : Pat <(v1i64 (scalar_to_vector (i64
1216 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1217 ro_Wextend64:$extend))))),
1218 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1220 def : Pat <(v1i64 (scalar_to_vector (i64
1221 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1222 ro_Xextend64:$extend))))),
1223 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1226 // Match all load 64 bits width whose type is compatible with FPR64
1227 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1228 Instruction LOADW, Instruction LOADX> {
1230 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1231 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1233 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1234 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1237 let AddedComplexity = 10 in {
1238 let Predicates = [IsLE] in {
1239 // We must do vector loads with LD1 in big-endian.
1240 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1241 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1242 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1243 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1244 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1247 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1248 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1250 // Match all load 128 bits width whose type is compatible with FPR128
1251 let Predicates = [IsLE] in {
1252 // We must do vector loads with LD1 in big-endian.
1253 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1254 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1255 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1256 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1257 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1258 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1259 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1261 } // AddedComplexity = 10
1264 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1265 Instruction INSTW, Instruction INSTX> {
1266 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1267 (SUBREG_TO_REG (i64 0),
1268 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1271 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1272 (SUBREG_TO_REG (i64 0),
1273 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1277 let AddedComplexity = 10 in {
1278 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1279 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1280 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1282 // zextloadi1 -> zextloadi8
1283 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1285 // extload -> zextload
1286 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1287 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1288 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1290 // extloadi1 -> zextloadi8
1291 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1296 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1297 Instruction INSTW, Instruction INSTX> {
1298 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1299 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1301 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1302 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1306 let AddedComplexity = 10 in {
1307 // extload -> zextload
1308 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1309 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1310 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1312 // zextloadi1 -> zextloadi8
1313 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1317 // (unsigned immediate)
1319 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1321 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1322 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1324 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1325 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1327 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1328 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1329 [(set (f16 FPR16:$Rt),
1330 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1331 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1332 [(set (f32 FPR32:$Rt),
1333 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1334 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1335 [(set (f64 FPR64:$Rt),
1336 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1337 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1338 [(set (f128 FPR128:$Rt),
1339 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1341 // For regular load, we do not have any alignment requirement.
1342 // Thus, it is safe to directly map the vector loads with interesting
1343 // addressing modes.
1344 // FIXME: We could do the same for bitconvert to floating point vectors.
1345 def : Pat <(v8i8 (scalar_to_vector (i32
1346 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1347 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1348 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1349 def : Pat <(v16i8 (scalar_to_vector (i32
1350 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1351 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1352 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1353 def : Pat <(v4i16 (scalar_to_vector (i32
1354 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1355 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1356 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1357 def : Pat <(v8i16 (scalar_to_vector (i32
1358 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1359 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1360 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1361 def : Pat <(v2i32 (scalar_to_vector (i32
1362 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1363 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1364 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1365 def : Pat <(v4i32 (scalar_to_vector (i32
1366 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1367 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1368 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1369 def : Pat <(v1i64 (scalar_to_vector (i64
1370 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1371 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1372 def : Pat <(v2i64 (scalar_to_vector (i64
1373 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1374 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1375 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1377 // Match all load 64 bits width whose type is compatible with FPR64
1378 let Predicates = [IsLE] in {
1379 // We must use LD1 to perform vector loads in big-endian.
1380 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1381 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1382 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1383 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1384 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1385 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1386 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1387 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1388 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1389 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1391 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1392 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1393 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1394 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1396 // Match all load 128 bits width whose type is compatible with FPR128
1397 let Predicates = [IsLE] in {
1398 // We must use LD1 to perform vector loads in big-endian.
1399 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1400 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1401 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1402 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1403 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1404 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1405 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1406 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1407 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1408 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1409 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1410 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1411 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1412 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1414 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1415 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1417 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1419 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1420 uimm12s2:$offset)))]>;
1421 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1423 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1424 uimm12s1:$offset)))]>;
1426 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1427 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1428 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1429 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1431 // zextloadi1 -> zextloadi8
1432 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1433 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1434 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1435 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1437 // extload -> zextload
1438 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1439 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1440 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1441 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1442 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1443 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1444 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1445 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1446 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1447 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1448 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1449 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1450 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1451 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1453 // load sign-extended half-word
1454 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1456 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1457 uimm12s2:$offset)))]>;
1458 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1460 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1461 uimm12s2:$offset)))]>;
1463 // load sign-extended byte
1464 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1466 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1467 uimm12s1:$offset)))]>;
1468 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1470 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1471 uimm12s1:$offset)))]>;
1473 // load sign-extended word
1474 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1476 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1477 uimm12s4:$offset)))]>;
1479 // load zero-extended word
1480 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1481 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1484 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1485 [(AArch64Prefetch imm:$Rt,
1486 (am_indexed64 GPR64sp:$Rn,
1487 uimm12s8:$offset))]>;
1489 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1493 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1494 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1495 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1496 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1497 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1499 // load sign-extended word
1500 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1503 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1504 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1507 // (unscaled immediate)
1508 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1510 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1511 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1513 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1514 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1516 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1517 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1519 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1520 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1521 [(set (f32 FPR32:$Rt),
1522 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1523 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1524 [(set (f64 FPR64:$Rt),
1525 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1526 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1527 [(set (f128 FPR128:$Rt),
1528 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1531 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1533 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1535 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1537 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1539 // Match all load 64 bits width whose type is compatible with FPR64
1540 let Predicates = [IsLE] in {
1541 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1542 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1543 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1544 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1545 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1546 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1547 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1548 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1549 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1550 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1552 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1553 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1554 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1555 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1557 // Match all load 128 bits width whose type is compatible with FPR128
1558 let Predicates = [IsLE] in {
1559 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1560 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1561 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1562 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1563 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1564 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1565 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1566 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1567 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1568 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1569 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1570 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1571 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1572 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1576 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1577 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1578 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1579 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1580 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1581 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1582 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1583 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1584 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1585 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1586 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1587 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1588 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1589 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1591 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1592 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1593 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1594 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1595 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1596 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1597 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1598 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1599 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1600 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1601 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1602 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1603 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1604 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1608 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1610 // Define new assembler match classes as we want to only match these when
1611 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1612 // associate a DiagnosticType either, as we want the diagnostic for the
1613 // canonical form (the scaled operand) to take precedence.
1614 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1615 let Name = "SImm9OffsetFB" # Width;
1616 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1617 let RenderMethod = "addImmOperands";
1620 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1621 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1622 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1623 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1624 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1626 def simm9_offset_fb8 : Operand<i64> {
1627 let ParserMatchClass = SImm9OffsetFB8Operand;
1629 def simm9_offset_fb16 : Operand<i64> {
1630 let ParserMatchClass = SImm9OffsetFB16Operand;
1632 def simm9_offset_fb32 : Operand<i64> {
1633 let ParserMatchClass = SImm9OffsetFB32Operand;
1635 def simm9_offset_fb64 : Operand<i64> {
1636 let ParserMatchClass = SImm9OffsetFB64Operand;
1638 def simm9_offset_fb128 : Operand<i64> {
1639 let ParserMatchClass = SImm9OffsetFB128Operand;
1642 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1643 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1644 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1645 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1646 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1647 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1648 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1649 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1650 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1651 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1652 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1653 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1654 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1655 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1658 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1659 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1660 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1661 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1663 // load sign-extended half-word
1665 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1667 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1669 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1671 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1673 // load sign-extended byte
1675 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1677 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1679 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1681 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1683 // load sign-extended word
1685 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1687 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1689 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1690 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1691 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1692 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1693 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1694 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1695 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1696 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1697 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1698 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1699 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1700 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1701 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1702 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1703 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1706 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1707 [(AArch64Prefetch imm:$Rt,
1708 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1711 // (unscaled immediate, unprivileged)
1712 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1713 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1715 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1716 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1718 // load sign-extended half-word
1719 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1720 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1722 // load sign-extended byte
1723 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1724 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1726 // load sign-extended word
1727 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1730 // (immediate pre-indexed)
1731 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1732 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1733 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1734 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1735 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1736 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1737 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1739 // load sign-extended half-word
1740 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1741 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1743 // load sign-extended byte
1744 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1745 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1747 // load zero-extended byte
1748 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1749 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1751 // load sign-extended word
1752 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1755 // (immediate post-indexed)
1756 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1757 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1758 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1759 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1760 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1761 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1762 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1764 // load sign-extended half-word
1765 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1766 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1768 // load sign-extended byte
1769 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1770 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1772 // load zero-extended byte
1773 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1774 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1776 // load sign-extended word
1777 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1779 //===----------------------------------------------------------------------===//
1780 // Store instructions.
1781 //===----------------------------------------------------------------------===//
1783 // Pair (indexed, offset)
1784 // FIXME: Use dedicated range-checked addressing mode operand here.
1785 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1786 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1787 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1788 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1789 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1791 // Pair (pre-indexed)
1792 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1793 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1794 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1795 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1796 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1798 // Pair (pre-indexed)
1799 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1800 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1801 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1802 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1803 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1805 // Pair (no allocate)
1806 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1807 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1808 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1809 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1810 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1813 // (Register offset)
1816 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1817 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1818 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1819 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1823 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1824 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1825 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1826 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1827 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1829 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1830 Instruction STRW, Instruction STRX> {
1832 def : Pat<(storeop GPR64:$Rt,
1833 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1834 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1835 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1837 def : Pat<(storeop GPR64:$Rt,
1838 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1839 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1840 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1843 let AddedComplexity = 10 in {
1845 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1846 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1847 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1850 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1851 Instruction STRW, Instruction STRX> {
1852 def : Pat<(store (VecTy FPR:$Rt),
1853 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1854 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1856 def : Pat<(store (VecTy FPR:$Rt),
1857 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1858 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1861 let AddedComplexity = 10 in {
1862 // Match all store 64 bits width whose type is compatible with FPR64
1863 let Predicates = [IsLE] in {
1864 // We must use ST1 to store vectors in big-endian.
1865 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1866 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1867 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1868 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1869 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1872 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1873 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1875 // Match all store 128 bits width whose type is compatible with FPR128
1876 let Predicates = [IsLE] in {
1877 // We must use ST1 to store vectors in big-endian.
1878 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1879 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1880 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1881 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1882 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1883 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1884 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
1886 } // AddedComplexity = 10
1889 // (unsigned immediate)
1890 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1892 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1893 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1895 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1896 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1898 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
1899 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1900 [(store (f16 FPR16:$Rt),
1901 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
1902 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1903 [(store (f32 FPR32:$Rt),
1904 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1905 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1906 [(store (f64 FPR64:$Rt),
1907 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1908 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1910 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1911 [(truncstorei16 GPR32:$Rt,
1912 (am_indexed16 GPR64sp:$Rn,
1913 uimm12s2:$offset))]>;
1914 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
1915 [(truncstorei8 GPR32:$Rt,
1916 (am_indexed8 GPR64sp:$Rn,
1917 uimm12s1:$offset))]>;
1919 // Match all store 64 bits width whose type is compatible with FPR64
1920 let AddedComplexity = 10 in {
1921 let Predicates = [IsLE] in {
1922 // We must use ST1 to store vectors in big-endian.
1923 def : Pat<(store (v2f32 FPR64:$Rt),
1924 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1925 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1926 def : Pat<(store (v8i8 FPR64:$Rt),
1927 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1928 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1929 def : Pat<(store (v4i16 FPR64:$Rt),
1930 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1931 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1932 def : Pat<(store (v2i32 FPR64:$Rt),
1933 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1934 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1935 def : Pat<(store (v4f16 FPR64:$Rt),
1936 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1937 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1939 def : Pat<(store (v1f64 FPR64:$Rt),
1940 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1941 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1942 def : Pat<(store (v1i64 FPR64:$Rt),
1943 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1944 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1946 // Match all store 128 bits width whose type is compatible with FPR128
1947 let Predicates = [IsLE] in {
1948 // We must use ST1 to store vectors in big-endian.
1949 def : Pat<(store (v4f32 FPR128:$Rt),
1950 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1951 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1952 def : Pat<(store (v2f64 FPR128:$Rt),
1953 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1954 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1955 def : Pat<(store (v16i8 FPR128:$Rt),
1956 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1957 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1958 def : Pat<(store (v8i16 FPR128:$Rt),
1959 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1960 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1961 def : Pat<(store (v4i32 FPR128:$Rt),
1962 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1963 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1964 def : Pat<(store (v2i64 FPR128:$Rt),
1965 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1966 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1967 def : Pat<(store (v8f16 FPR128:$Rt),
1968 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1969 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1971 def : Pat<(store (f128 FPR128:$Rt),
1972 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1973 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1976 def : Pat<(truncstorei32 GPR64:$Rt,
1977 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
1978 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
1979 def : Pat<(truncstorei16 GPR64:$Rt,
1980 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
1981 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
1982 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
1983 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
1985 } // AddedComplexity = 10
1988 // (unscaled immediate)
1989 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
1991 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1992 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
1994 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1995 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
1997 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1998 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
1999 [(store (f16 FPR16:$Rt),
2000 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2001 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2002 [(store (f32 FPR32:$Rt),
2003 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2004 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2005 [(store (f64 FPR64:$Rt),
2006 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2007 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2008 [(store (f128 FPR128:$Rt),
2009 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2010 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2011 [(truncstorei16 GPR32:$Rt,
2012 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2013 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2014 [(truncstorei8 GPR32:$Rt,
2015 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2017 // Match all store 64 bits width whose type is compatible with FPR64
2018 let Predicates = [IsLE] in {
2019 // We must use ST1 to store vectors in big-endian.
2020 def : Pat<(store (v2f32 FPR64:$Rt),
2021 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2022 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2023 def : Pat<(store (v8i8 FPR64:$Rt),
2024 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2025 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2026 def : Pat<(store (v4i16 FPR64:$Rt),
2027 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2028 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2029 def : Pat<(store (v2i32 FPR64:$Rt),
2030 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2031 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2032 def : Pat<(store (v4f16 FPR64:$Rt),
2033 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2034 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2036 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2037 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2038 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2039 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2041 // Match all store 128 bits width whose type is compatible with FPR128
2042 let Predicates = [IsLE] in {
2043 // We must use ST1 to store vectors in big-endian.
2044 def : Pat<(store (v4f32 FPR128:$Rt),
2045 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2046 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2047 def : Pat<(store (v2f64 FPR128:$Rt),
2048 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2049 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2050 def : Pat<(store (v16i8 FPR128:$Rt),
2051 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2052 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2053 def : Pat<(store (v8i16 FPR128:$Rt),
2054 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2055 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2056 def : Pat<(store (v4i32 FPR128:$Rt),
2057 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2058 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2059 def : Pat<(store (v2i64 FPR128:$Rt),
2060 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2061 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2062 def : Pat<(store (v2f64 FPR128:$Rt),
2063 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2064 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2065 def : Pat<(store (v8f16 FPR128:$Rt),
2066 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2067 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2070 // unscaled i64 truncating stores
2071 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2072 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2073 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2074 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2075 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2076 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2079 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2080 def : InstAlias<"str $Rt, [$Rn, $offset]",
2081 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2082 def : InstAlias<"str $Rt, [$Rn, $offset]",
2083 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2084 def : InstAlias<"str $Rt, [$Rn, $offset]",
2085 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2086 def : InstAlias<"str $Rt, [$Rn, $offset]",
2087 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2088 def : InstAlias<"str $Rt, [$Rn, $offset]",
2089 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2090 def : InstAlias<"str $Rt, [$Rn, $offset]",
2091 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2092 def : InstAlias<"str $Rt, [$Rn, $offset]",
2093 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2095 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2096 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2097 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2098 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2101 // (unscaled immediate, unprivileged)
2102 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2103 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2105 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2106 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2109 // (immediate pre-indexed)
2110 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2111 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2112 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2113 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2114 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2115 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2116 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2118 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2119 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2122 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2123 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2125 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2126 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2128 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2129 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2132 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2133 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2134 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2135 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2136 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2137 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2138 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2139 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2140 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2141 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2142 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2143 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2144 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2145 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2147 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2148 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2149 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2150 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2151 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2152 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2153 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2154 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2155 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2156 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2157 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2158 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2159 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2160 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2163 // (immediate post-indexed)
2164 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2165 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2166 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2167 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2168 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2169 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2170 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2172 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2173 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2176 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2177 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2179 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2180 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2182 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2183 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2186 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2187 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2188 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2189 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2190 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2191 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2192 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2193 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2194 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2195 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2196 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2197 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2198 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2199 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2201 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2202 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2203 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2204 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2205 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2206 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2207 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2208 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2209 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2210 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2211 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2212 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2213 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2214 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2216 //===----------------------------------------------------------------------===//
2217 // Load/store exclusive instructions.
2218 //===----------------------------------------------------------------------===//
2220 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2221 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2222 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2223 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2225 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2226 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2227 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2228 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2230 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2231 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2232 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2233 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2235 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2236 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2237 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2238 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2240 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2241 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2242 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2243 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2245 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2246 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2247 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2248 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2250 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2251 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2253 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2254 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2256 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2257 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2259 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2260 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2262 //===----------------------------------------------------------------------===//
2263 // Scaled floating point to integer conversion instructions.
2264 //===----------------------------------------------------------------------===//
2266 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2267 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2268 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2269 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2270 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2271 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2272 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2273 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2274 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2275 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2276 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2277 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2278 let isCodeGenOnly = 1 in {
2279 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2280 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2281 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2282 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2285 //===----------------------------------------------------------------------===//
2286 // Scaled integer to floating point conversion instructions.
2287 //===----------------------------------------------------------------------===//
2289 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2290 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2292 //===----------------------------------------------------------------------===//
2293 // Unscaled integer to floating point conversion instruction.
2294 //===----------------------------------------------------------------------===//
2296 defm FMOV : UnscaledConversion<"fmov">;
2298 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
2299 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
2301 //===----------------------------------------------------------------------===//
2302 // Floating point conversion instruction.
2303 //===----------------------------------------------------------------------===//
2305 defm FCVT : FPConversion<"fcvt">;
2307 //===----------------------------------------------------------------------===//
2308 // Floating point single operand instructions.
2309 //===----------------------------------------------------------------------===//
2311 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2312 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2313 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2314 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2315 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2316 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2317 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2318 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2320 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2321 (FRINTNDr FPR64:$Rn)>;
2323 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2324 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2325 // <rdar://problem/13715968>
2326 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2327 let hasSideEffects = 1 in {
2328 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2331 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2333 let SchedRW = [WriteFDiv] in {
2334 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2337 //===----------------------------------------------------------------------===//
2338 // Floating point two operand instructions.
2339 //===----------------------------------------------------------------------===//
2341 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2342 let SchedRW = [WriteFDiv] in {
2343 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2345 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2346 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2347 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2348 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2349 let SchedRW = [WriteFMul] in {
2350 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2351 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2353 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2355 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2356 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2357 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2358 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2359 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2360 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2361 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2362 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2364 //===----------------------------------------------------------------------===//
2365 // Floating point three operand instructions.
2366 //===----------------------------------------------------------------------===//
2368 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2369 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2370 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2371 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2372 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2373 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2374 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2376 // The following def pats catch the case where the LHS of an FMA is negated.
2377 // The TriOpFrag above catches the case where the middle operand is negated.
2379 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2380 // the NEON variant.
2381 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2382 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2384 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2385 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2387 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2389 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2390 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2392 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2393 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2395 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2396 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2398 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2399 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2401 //===----------------------------------------------------------------------===//
2402 // Floating point comparison instructions.
2403 //===----------------------------------------------------------------------===//
2405 defm FCMPE : FPComparison<1, "fcmpe">;
2406 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2408 //===----------------------------------------------------------------------===//
2409 // Floating point conditional comparison instructions.
2410 //===----------------------------------------------------------------------===//
2412 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2413 defm FCCMP : FPCondComparison<0, "fccmp">;
2415 //===----------------------------------------------------------------------===//
2416 // Floating point conditional select instruction.
2417 //===----------------------------------------------------------------------===//
2419 defm FCSEL : FPCondSelect<"fcsel">;
2421 // CSEL instructions providing f128 types need to be handled by a
2422 // pseudo-instruction since the eventual code will need to introduce basic
2423 // blocks and control flow.
2424 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2425 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2426 [(set (f128 FPR128:$Rd),
2427 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2428 (i32 imm:$cond), NZCV))]> {
2430 let usesCustomInserter = 1;
2434 //===----------------------------------------------------------------------===//
2435 // Floating point immediate move.
2436 //===----------------------------------------------------------------------===//
2438 let isReMaterializable = 1 in {
2439 defm FMOV : FPMoveImmediate<"fmov">;
2442 //===----------------------------------------------------------------------===//
2443 // Advanced SIMD two vector instructions.
2444 //===----------------------------------------------------------------------===//
2446 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2447 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2448 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2449 (ABSv8i8 V64:$src)>;
2450 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2451 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2452 (ABSv4i16 V64:$src)>;
2453 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2454 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2455 (ABSv2i32 V64:$src)>;
2456 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2457 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2458 (ABSv16i8 V128:$src)>;
2459 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2460 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2461 (ABSv8i16 V128:$src)>;
2462 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2463 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2464 (ABSv4i32 V128:$src)>;
2465 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2466 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2467 (ABSv2i64 V128:$src)>;
2469 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2470 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2471 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2472 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2473 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2474 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2475 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2476 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2477 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2479 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2480 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2481 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2482 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2483 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2484 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2485 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2486 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2487 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2488 (FCVTLv4i16 V64:$Rn)>;
2489 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2491 (FCVTLv8i16 V128:$Rn)>;
2492 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2493 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2495 (FCVTLv4i32 V128:$Rn)>;
2497 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2498 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2500 (FCVTLv8i16 V128:$Rn)>;
2502 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2503 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2504 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2505 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2506 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2507 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2508 (FCVTNv4i16 V128:$Rn)>;
2509 def : Pat<(concat_vectors V64:$Rd,
2510 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2511 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2512 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2513 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2514 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2515 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2516 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2517 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2518 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2519 int_aarch64_neon_fcvtxn>;
2520 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2521 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2522 let isCodeGenOnly = 1 in {
2523 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2524 int_aarch64_neon_fcvtzs>;
2525 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2526 int_aarch64_neon_fcvtzu>;
2528 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2529 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2530 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2531 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2532 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2533 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2534 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2535 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2536 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2537 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2538 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2539 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2540 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2541 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2542 // Aliases for MVN -> NOT.
2543 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2544 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2545 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2546 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2548 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2549 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2550 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2551 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2552 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2553 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2554 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2556 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2557 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2558 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2559 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2560 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2561 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2562 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2563 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2565 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2566 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2567 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2568 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2569 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2571 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2572 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2573 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2574 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2575 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2576 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2577 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2578 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2579 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2580 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2581 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2582 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2583 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2584 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2585 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2586 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2587 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2588 int_aarch64_neon_uaddlp>;
2589 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2590 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2591 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2592 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2593 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2594 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2596 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2597 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2598 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2599 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2600 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2601 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2603 // Patterns for vector long shift (by element width). These need to match all
2604 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2606 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2607 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2608 (SHLLv8i8 V64:$Rn)>;
2609 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2610 (SHLLv16i8 V128:$Rn)>;
2611 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2612 (SHLLv4i16 V64:$Rn)>;
2613 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2614 (SHLLv8i16 V128:$Rn)>;
2615 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2616 (SHLLv2i32 V64:$Rn)>;
2617 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2618 (SHLLv4i32 V128:$Rn)>;
2621 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2622 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2623 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2625 //===----------------------------------------------------------------------===//
2626 // Advanced SIMD three vector instructions.
2627 //===----------------------------------------------------------------------===//
2629 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2630 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2631 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2632 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2633 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2634 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2635 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2636 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2637 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2638 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2639 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2640 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2641 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2642 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2643 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2644 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2645 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2646 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2647 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2648 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2649 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2650 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2651 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2652 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2653 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2655 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2656 // instruction expects the addend first, while the fma intrinsic puts it last.
2657 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2658 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2659 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2660 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2662 // The following def pats catch the case where the LHS of an FMA is negated.
2663 // The TriOpFrag above catches the case where the middle operand is negated.
2664 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2665 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2667 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2668 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2670 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2671 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2673 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2674 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2675 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2676 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2677 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2678 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2679 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2680 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2681 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2682 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2683 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2684 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2685 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2686 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2687 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2688 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2689 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2690 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2691 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2692 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2693 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2694 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2695 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2696 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2697 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2698 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2699 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2700 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2701 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2702 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2703 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2704 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2705 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2706 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2707 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2708 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2709 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2710 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2711 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2712 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2713 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2714 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2715 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2716 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2717 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2718 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2720 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2721 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2722 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2723 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2724 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2725 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2726 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2727 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2728 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2729 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2730 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2732 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2733 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2734 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2735 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2736 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2737 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2738 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2739 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2741 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2742 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2743 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2744 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2745 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2746 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2747 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2748 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2750 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2751 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2752 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2753 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2754 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2755 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2756 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2757 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2759 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2760 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2761 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2762 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2763 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2764 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2765 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2766 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2768 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2769 "|cmls.8b\t$dst, $src1, $src2}",
2770 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2771 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2772 "|cmls.16b\t$dst, $src1, $src2}",
2773 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2774 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2775 "|cmls.4h\t$dst, $src1, $src2}",
2776 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2777 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2778 "|cmls.8h\t$dst, $src1, $src2}",
2779 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2780 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2781 "|cmls.2s\t$dst, $src1, $src2}",
2782 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2783 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2784 "|cmls.4s\t$dst, $src1, $src2}",
2785 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2786 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2787 "|cmls.2d\t$dst, $src1, $src2}",
2788 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2790 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2791 "|cmlo.8b\t$dst, $src1, $src2}",
2792 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2793 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2794 "|cmlo.16b\t$dst, $src1, $src2}",
2795 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2796 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2797 "|cmlo.4h\t$dst, $src1, $src2}",
2798 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2799 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2800 "|cmlo.8h\t$dst, $src1, $src2}",
2801 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2802 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2803 "|cmlo.2s\t$dst, $src1, $src2}",
2804 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2805 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2806 "|cmlo.4s\t$dst, $src1, $src2}",
2807 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2808 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2809 "|cmlo.2d\t$dst, $src1, $src2}",
2810 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2812 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2813 "|cmle.8b\t$dst, $src1, $src2}",
2814 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2815 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2816 "|cmle.16b\t$dst, $src1, $src2}",
2817 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2818 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2819 "|cmle.4h\t$dst, $src1, $src2}",
2820 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2821 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2822 "|cmle.8h\t$dst, $src1, $src2}",
2823 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2824 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2825 "|cmle.2s\t$dst, $src1, $src2}",
2826 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2827 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2828 "|cmle.4s\t$dst, $src1, $src2}",
2829 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2830 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2831 "|cmle.2d\t$dst, $src1, $src2}",
2832 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2834 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2835 "|cmlt.8b\t$dst, $src1, $src2}",
2836 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2837 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2838 "|cmlt.16b\t$dst, $src1, $src2}",
2839 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2840 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2841 "|cmlt.4h\t$dst, $src1, $src2}",
2842 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2843 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2844 "|cmlt.8h\t$dst, $src1, $src2}",
2845 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2846 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2847 "|cmlt.2s\t$dst, $src1, $src2}",
2848 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2849 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2850 "|cmlt.4s\t$dst, $src1, $src2}",
2851 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2852 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2853 "|cmlt.2d\t$dst, $src1, $src2}",
2854 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2856 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2857 "|fcmle.2s\t$dst, $src1, $src2}",
2858 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2859 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2860 "|fcmle.4s\t$dst, $src1, $src2}",
2861 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2862 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2863 "|fcmle.2d\t$dst, $src1, $src2}",
2864 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2866 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2867 "|fcmlt.2s\t$dst, $src1, $src2}",
2868 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2869 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2870 "|fcmlt.4s\t$dst, $src1, $src2}",
2871 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2872 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2873 "|fcmlt.2d\t$dst, $src1, $src2}",
2874 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2876 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2877 "|facle.2s\t$dst, $src1, $src2}",
2878 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2879 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2880 "|facle.4s\t$dst, $src1, $src2}",
2881 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2882 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2883 "|facle.2d\t$dst, $src1, $src2}",
2884 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2886 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2887 "|faclt.2s\t$dst, $src1, $src2}",
2888 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2889 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2890 "|faclt.4s\t$dst, $src1, $src2}",
2891 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2892 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2893 "|faclt.2d\t$dst, $src1, $src2}",
2894 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2896 //===----------------------------------------------------------------------===//
2897 // Advanced SIMD three scalar instructions.
2898 //===----------------------------------------------------------------------===//
2900 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2901 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
2902 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
2903 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
2904 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
2905 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
2906 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
2907 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
2908 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2909 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2910 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2911 int_aarch64_neon_facge>;
2912 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2913 int_aarch64_neon_facgt>;
2914 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2915 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2916 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2917 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
2918 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
2919 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
2920 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
2921 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
2922 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
2923 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
2924 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
2925 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
2926 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
2927 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
2928 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2929 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
2930 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
2931 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
2932 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
2933 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
2934 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
2936 def : InstAlias<"cmls $dst, $src1, $src2",
2937 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2938 def : InstAlias<"cmle $dst, $src1, $src2",
2939 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2940 def : InstAlias<"cmlo $dst, $src1, $src2",
2941 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2942 def : InstAlias<"cmlt $dst, $src1, $src2",
2943 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2944 def : InstAlias<"fcmle $dst, $src1, $src2",
2945 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2946 def : InstAlias<"fcmle $dst, $src1, $src2",
2947 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2948 def : InstAlias<"fcmlt $dst, $src1, $src2",
2949 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2950 def : InstAlias<"fcmlt $dst, $src1, $src2",
2951 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2952 def : InstAlias<"facle $dst, $src1, $src2",
2953 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2954 def : InstAlias<"facle $dst, $src1, $src2",
2955 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2956 def : InstAlias<"faclt $dst, $src1, $src2",
2957 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2958 def : InstAlias<"faclt $dst, $src1, $src2",
2959 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2961 //===----------------------------------------------------------------------===//
2962 // Advanced SIMD three scalar instructions (mixed operands).
2963 //===----------------------------------------------------------------------===//
2964 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2965 int_aarch64_neon_sqdmulls_scalar>;
2966 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2967 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2969 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
2970 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2971 (i32 FPR32:$Rm))))),
2972 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2973 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
2974 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2975 (i32 FPR32:$Rm))))),
2976 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2978 //===----------------------------------------------------------------------===//
2979 // Advanced SIMD two scalar instructions.
2980 //===----------------------------------------------------------------------===//
2982 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
2983 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
2984 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
2985 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
2986 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
2987 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
2988 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2989 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2990 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2991 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2992 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2993 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2994 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2995 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2996 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2997 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2998 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2999 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
3000 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
3001 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3002 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
3003 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
3004 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
3005 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
3006 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
3007 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3008 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3009 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3010 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3011 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3012 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3013 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3014 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3015 int_aarch64_neon_suqadd>;
3016 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3017 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3018 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3019 int_aarch64_neon_usqadd>;
3021 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3023 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3024 (FCVTASv1i64 FPR64:$Rn)>;
3025 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3026 (FCVTAUv1i64 FPR64:$Rn)>;
3027 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3028 (FCVTMSv1i64 FPR64:$Rn)>;
3029 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3030 (FCVTMUv1i64 FPR64:$Rn)>;
3031 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3032 (FCVTNSv1i64 FPR64:$Rn)>;
3033 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3034 (FCVTNUv1i64 FPR64:$Rn)>;
3035 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3036 (FCVTPSv1i64 FPR64:$Rn)>;
3037 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3038 (FCVTPUv1i64 FPR64:$Rn)>;
3040 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3041 (FRECPEv1i32 FPR32:$Rn)>;
3042 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3043 (FRECPEv1i64 FPR64:$Rn)>;
3044 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3045 (FRECPEv1i64 FPR64:$Rn)>;
3047 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3048 (FRECPXv1i32 FPR32:$Rn)>;
3049 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3050 (FRECPXv1i64 FPR64:$Rn)>;
3052 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3053 (FRSQRTEv1i32 FPR32:$Rn)>;
3054 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3055 (FRSQRTEv1i64 FPR64:$Rn)>;
3056 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3057 (FRSQRTEv1i64 FPR64:$Rn)>;
3059 // If an integer is about to be converted to a floating point value,
3060 // just load it on the floating point unit.
3061 // Here are the patterns for 8 and 16-bits to float.
3063 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3064 SDPatternOperator loadop, Instruction UCVTF,
3065 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3067 def : Pat<(DstTy (uint_to_fp (SrcTy
3068 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3069 ro.Wext:$extend))))),
3070 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3071 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3074 def : Pat<(DstTy (uint_to_fp (SrcTy
3075 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3076 ro.Wext:$extend))))),
3077 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3078 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3082 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3083 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3084 def : Pat <(f32 (uint_to_fp (i32
3085 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3086 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3087 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3088 def : Pat <(f32 (uint_to_fp (i32
3089 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3090 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3091 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3092 // 16-bits -> float.
3093 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3094 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3095 def : Pat <(f32 (uint_to_fp (i32
3096 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3097 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3098 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3099 def : Pat <(f32 (uint_to_fp (i32
3100 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3101 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3102 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3103 // 32-bits are handled in target specific dag combine:
3104 // performIntToFpCombine.
3105 // 64-bits integer to 32-bits floating point, not possible with
3106 // UCVTF on floating point registers (both source and destination
3107 // must have the same size).
3109 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3110 // 8-bits -> double.
3111 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3112 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3113 def : Pat <(f64 (uint_to_fp (i32
3114 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3115 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3116 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3117 def : Pat <(f64 (uint_to_fp (i32
3118 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3119 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3120 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3121 // 16-bits -> double.
3122 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3123 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3124 def : Pat <(f64 (uint_to_fp (i32
3125 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3126 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3127 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3128 def : Pat <(f64 (uint_to_fp (i32
3129 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3130 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3131 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3132 // 32-bits -> double.
3133 defm : UIntToFPROLoadPat<f64, i32, load,
3134 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3135 def : Pat <(f64 (uint_to_fp (i32
3136 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3137 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3138 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3139 def : Pat <(f64 (uint_to_fp (i32
3140 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3141 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3142 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3143 // 64-bits -> double are handled in target specific dag combine:
3144 // performIntToFpCombine.
3146 //===----------------------------------------------------------------------===//
3147 // Advanced SIMD three different-sized vector instructions.
3148 //===----------------------------------------------------------------------===//
3150 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3151 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3152 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3153 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3154 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3155 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3156 int_aarch64_neon_sabd>;
3157 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3158 int_aarch64_neon_sabd>;
3159 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3160 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3161 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3162 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3163 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3164 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3165 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3166 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3167 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3168 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3169 int_aarch64_neon_sqadd>;
3170 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3171 int_aarch64_neon_sqsub>;
3172 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3173 int_aarch64_neon_sqdmull>;
3174 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3175 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3176 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3177 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3178 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3179 int_aarch64_neon_uabd>;
3180 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3181 int_aarch64_neon_uabd>;
3182 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3183 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3184 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3185 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3186 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3187 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3188 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3189 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3190 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3191 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3192 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3193 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3194 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3196 // Additional patterns for SMULL and UMULL
3197 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3198 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3199 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3200 (INST8B V64:$Rn, V64:$Rm)>;
3201 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3202 (INST4H V64:$Rn, V64:$Rm)>;
3203 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3204 (INST2S V64:$Rn, V64:$Rm)>;
3207 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3208 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3209 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3210 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3212 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3213 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3214 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3215 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3216 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3217 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3218 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3219 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3220 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3223 defm : Neon_mulacc_widen_patterns<
3224 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3225 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3226 defm : Neon_mulacc_widen_patterns<
3227 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3228 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3229 defm : Neon_mulacc_widen_patterns<
3230 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3231 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3232 defm : Neon_mulacc_widen_patterns<
3233 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3234 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3236 // Patterns for 64-bit pmull
3237 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3238 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3239 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3240 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3241 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3243 // CodeGen patterns for addhn and subhn instructions, which can actually be
3244 // written in LLVM IR without too much difficulty.
3247 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3248 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3249 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3251 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3252 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3254 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3255 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3256 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3258 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3259 V128:$Rn, V128:$Rm)>;
3260 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3261 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3263 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3264 V128:$Rn, V128:$Rm)>;
3265 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3266 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3268 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3269 V128:$Rn, V128:$Rm)>;
3272 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3273 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3274 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3276 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3277 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3279 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3280 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3281 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3283 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3284 V128:$Rn, V128:$Rm)>;
3285 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3286 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3288 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3289 V128:$Rn, V128:$Rm)>;
3290 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3291 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3293 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3294 V128:$Rn, V128:$Rm)>;
3296 //----------------------------------------------------------------------------
3297 // AdvSIMD bitwise extract from vector instruction.
3298 //----------------------------------------------------------------------------
3300 defm EXT : SIMDBitwiseExtract<"ext">;
3302 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3303 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3304 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3305 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3306 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3307 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3308 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3309 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3310 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3311 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3312 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3313 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3314 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3315 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3316 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3317 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3318 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3319 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3320 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3321 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3323 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3325 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3326 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3327 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3328 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3329 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3330 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3331 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3332 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3333 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3334 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3335 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3336 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3337 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3338 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3341 //----------------------------------------------------------------------------
3342 // AdvSIMD zip vector
3343 //----------------------------------------------------------------------------
3345 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3346 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3347 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3348 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3349 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3350 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3352 //----------------------------------------------------------------------------
3353 // AdvSIMD TBL/TBX instructions
3354 //----------------------------------------------------------------------------
3356 defm TBL : SIMDTableLookup< 0, "tbl">;
3357 defm TBX : SIMDTableLookupTied<1, "tbx">;
3359 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3360 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3361 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3362 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3364 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3365 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3366 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3367 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3368 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3369 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3372 //----------------------------------------------------------------------------
3373 // AdvSIMD scalar CPY instruction
3374 //----------------------------------------------------------------------------
3376 defm CPY : SIMDScalarCPY<"cpy">;
3378 //----------------------------------------------------------------------------
3379 // AdvSIMD scalar pairwise instructions
3380 //----------------------------------------------------------------------------
3382 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3383 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3384 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3385 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3386 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3387 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3388 def : Pat<(i64 (int_aarch64_neon_saddv (v2i64 V128:$Rn))),
3389 (ADDPv2i64p V128:$Rn)>;
3390 def : Pat<(i64 (int_aarch64_neon_uaddv (v2i64 V128:$Rn))),
3391 (ADDPv2i64p V128:$Rn)>;
3392 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3393 (FADDPv2i32p V64:$Rn)>;
3394 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3395 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3396 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3397 (FADDPv2i64p V128:$Rn)>;
3398 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3399 (FMAXNMPv2i32p V64:$Rn)>;
3400 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3401 (FMAXNMPv2i64p V128:$Rn)>;
3402 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3403 (FMAXPv2i32p V64:$Rn)>;
3404 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3405 (FMAXPv2i64p V128:$Rn)>;
3406 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3407 (FMINNMPv2i32p V64:$Rn)>;
3408 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3409 (FMINNMPv2i64p V128:$Rn)>;
3410 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3411 (FMINPv2i32p V64:$Rn)>;
3412 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3413 (FMINPv2i64p V128:$Rn)>;
3415 //----------------------------------------------------------------------------
3416 // AdvSIMD INS/DUP instructions
3417 //----------------------------------------------------------------------------
3419 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3420 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3421 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3422 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3423 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3424 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3425 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3427 def DUPv2i64lane : SIMDDup64FromElement;
3428 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3429 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3430 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3431 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3432 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3433 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3435 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3436 (v2f32 (DUPv2i32lane
3437 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3439 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3440 (v4f32 (DUPv4i32lane
3441 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3443 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3444 (v2f64 (DUPv2i64lane
3445 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3447 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3448 (v4f16 (DUPv4i16lane
3449 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3451 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3452 (v8f16 (DUPv8i16lane
3453 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3456 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3457 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3458 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3459 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3461 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3462 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3463 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3464 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3465 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3466 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3468 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3469 // instruction even if the types don't match: we just have to remap the lane
3470 // carefully. N.b. this trick only applies to truncations.
3471 def VecIndex_x2 : SDNodeXForm<imm, [{
3472 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3474 def VecIndex_x4 : SDNodeXForm<imm, [{
3475 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3477 def VecIndex_x8 : SDNodeXForm<imm, [{
3478 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3481 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3482 ValueType Src128VT, ValueType ScalVT,
3483 Instruction DUP, SDNodeXForm IdxXFORM> {
3484 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3486 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3488 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3490 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3493 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3494 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3495 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3497 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3498 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3499 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3501 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3502 SDNodeXForm IdxXFORM> {
3503 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3505 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3507 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3509 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3512 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3513 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3514 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3516 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3517 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3518 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3520 // SMOV and UMOV definitions, with some extra patterns for convenience
3524 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3525 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3526 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3527 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3528 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3529 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3530 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3531 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3532 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3533 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3534 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3535 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3537 // Extracting i8 or i16 elements will have the zero-extend transformed to
3538 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3539 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3540 // bits of the destination register.
3541 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3543 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3544 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3546 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3550 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3551 (SUBREG_TO_REG (i32 0),
3552 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3553 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3554 (SUBREG_TO_REG (i32 0),
3555 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3557 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3558 (SUBREG_TO_REG (i32 0),
3559 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3560 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3561 (SUBREG_TO_REG (i32 0),
3562 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3564 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3565 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3566 (i32 FPR32:$Rn), ssub))>;
3567 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3568 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3569 (i32 FPR32:$Rn), ssub))>;
3570 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3571 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3572 (i64 FPR64:$Rn), dsub))>;
3574 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3575 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3576 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3577 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3578 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3579 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3581 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3582 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3585 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3587 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3591 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3592 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3594 V128:$Rn, VectorIndexH:$imm,
3595 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3598 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3599 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3602 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3604 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3607 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3608 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3610 V128:$Rn, VectorIndexS:$imm,
3611 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3613 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3614 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3616 V128:$Rn, VectorIndexD:$imm,
3617 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3620 // Copy an element at a constant index in one vector into a constant indexed
3621 // element of another.
3622 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3623 // index type and INS extension
3624 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3625 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3626 VectorIndexB:$idx2)),
3628 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3630 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3631 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3632 VectorIndexH:$idx2)),
3634 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3636 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3637 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3638 VectorIndexS:$idx2)),
3640 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3642 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3643 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3644 VectorIndexD:$idx2)),
3646 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3649 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3650 ValueType VTScal, Instruction INS> {
3651 def : Pat<(VT128 (vector_insert V128:$src,
3652 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3654 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3656 def : Pat<(VT128 (vector_insert V128:$src,
3657 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3659 (INS V128:$src, imm:$Immd,
3660 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3662 def : Pat<(VT64 (vector_insert V64:$src,
3663 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3665 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3666 imm:$Immd, V128:$Rn, imm:$Immn),
3669 def : Pat<(VT64 (vector_insert V64:$src,
3670 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3673 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3674 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3678 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3679 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3680 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3681 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3682 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3683 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3684 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3687 // Floating point vector extractions are codegen'd as either a sequence of
3688 // subregister extractions, possibly fed by an INS if the lane number is
3689 // anything other than zero.
3690 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3691 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3692 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3693 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3694 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3695 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3696 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3697 (f64 (EXTRACT_SUBREG
3698 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3699 V128:$Rn, VectorIndexD:$idx),
3701 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3702 (f32 (EXTRACT_SUBREG
3703 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3704 V128:$Rn, VectorIndexS:$idx),
3706 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3707 (f16 (EXTRACT_SUBREG
3708 (INSvi16lane (v8f16 (IMPLICIT_DEF)), 0,
3709 V128:$Rn, VectorIndexH:$idx),
3712 // All concat_vectors operations are canonicalised to act on i64 vectors for
3713 // AArch64. In the general case we need an instruction, which had just as well be
3715 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3716 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3717 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3718 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3720 def : ConcatPat<v2i64, v1i64>;
3721 def : ConcatPat<v2f64, v1f64>;
3722 def : ConcatPat<v4i32, v2i32>;
3723 def : ConcatPat<v4f32, v2f32>;
3724 def : ConcatPat<v8i16, v4i16>;
3725 def : ConcatPat<v8f16, v4f16>;
3726 def : ConcatPat<v16i8, v8i8>;
3728 // If the high lanes are undef, though, we can just ignore them:
3729 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3730 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3731 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3733 def : ConcatUndefPat<v2i64, v1i64>;
3734 def : ConcatUndefPat<v2f64, v1f64>;
3735 def : ConcatUndefPat<v4i32, v2i32>;
3736 def : ConcatUndefPat<v4f32, v2f32>;
3737 def : ConcatUndefPat<v8i16, v4i16>;
3738 def : ConcatUndefPat<v16i8, v8i8>;
3740 //----------------------------------------------------------------------------
3741 // AdvSIMD across lanes instructions
3742 //----------------------------------------------------------------------------
3744 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3745 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3746 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3747 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3748 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3749 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3750 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3751 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3752 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3753 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3754 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3756 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3757 // If there is a sign extension after this intrinsic, consume it as smov already
3759 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3761 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3762 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3764 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3766 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3767 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3769 // If there is a sign extension after this intrinsic, consume it as smov already
3771 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3773 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3774 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3776 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3778 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3779 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3781 // If there is a sign extension after this intrinsic, consume it as smov already
3783 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3785 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3786 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3788 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3790 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3791 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3793 // If there is a sign extension after this intrinsic, consume it as smov already
3795 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3797 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3798 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3800 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3802 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3803 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3806 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3807 (i32 (EXTRACT_SUBREG
3808 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3809 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3813 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3814 // If there is a masking operation keeping only what has been actually
3815 // generated, consume it.
3816 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3817 (i32 (EXTRACT_SUBREG
3818 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3819 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3821 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3822 (i32 (EXTRACT_SUBREG
3823 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3824 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3826 // If there is a masking operation keeping only what has been actually
3827 // generated, consume it.
3828 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3829 (i32 (EXTRACT_SUBREG
3830 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3831 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3833 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3834 (i32 (EXTRACT_SUBREG
3835 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3836 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3839 // If there is a masking operation keeping only what has been actually
3840 // generated, consume it.
3841 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3842 (i32 (EXTRACT_SUBREG
3843 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3844 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3846 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3847 (i32 (EXTRACT_SUBREG
3848 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3849 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3851 // If there is a masking operation keeping only what has been actually
3852 // generated, consume it.
3853 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3854 (i32 (EXTRACT_SUBREG
3855 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3856 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3858 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3859 (i32 (EXTRACT_SUBREG
3860 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3861 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3864 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3865 (i32 (EXTRACT_SUBREG
3866 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3867 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3872 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3873 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3875 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3876 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3878 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3880 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3881 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3884 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3885 (i32 (EXTRACT_SUBREG
3886 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3887 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3889 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3890 (i32 (EXTRACT_SUBREG
3891 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3892 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3895 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3896 (i64 (EXTRACT_SUBREG
3897 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3898 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3902 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3904 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3905 (i32 (EXTRACT_SUBREG
3906 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3907 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3909 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3910 (i32 (EXTRACT_SUBREG
3911 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3912 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3915 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3916 (i32 (EXTRACT_SUBREG
3917 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3918 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3920 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3921 (i32 (EXTRACT_SUBREG
3922 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3923 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3926 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3927 (i64 (EXTRACT_SUBREG
3928 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3929 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3933 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_aarch64_neon_saddv>;
3934 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3935 def : Pat<(i32 (int_aarch64_neon_saddv (v2i32 V64:$Rn))),
3936 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3938 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_aarch64_neon_uaddv>;
3939 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3940 def : Pat<(i32 (int_aarch64_neon_uaddv (v2i32 V64:$Rn))),
3941 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3943 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_aarch64_neon_smaxv>;
3944 def : Pat<(i32 (int_aarch64_neon_smaxv (v2i32 V64:$Rn))),
3945 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3947 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_aarch64_neon_sminv>;
3948 def : Pat<(i32 (int_aarch64_neon_sminv (v2i32 V64:$Rn))),
3949 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3951 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_aarch64_neon_umaxv>;
3952 def : Pat<(i32 (int_aarch64_neon_umaxv (v2i32 V64:$Rn))),
3953 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3955 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_aarch64_neon_uminv>;
3956 def : Pat<(i32 (int_aarch64_neon_uminv (v2i32 V64:$Rn))),
3957 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3959 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
3960 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
3962 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3963 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
3964 (i64 (EXTRACT_SUBREG
3965 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3966 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3968 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3969 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
3970 (i64 (EXTRACT_SUBREG
3971 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3972 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3975 //------------------------------------------------------------------------------
3976 // AdvSIMD modified immediate instructions
3977 //------------------------------------------------------------------------------
3980 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
3982 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
3984 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3985 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3986 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3987 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3989 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3990 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3991 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3992 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3994 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3995 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3996 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3997 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3999 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4000 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4001 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4002 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4005 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
4007 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4008 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
4010 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4011 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
4013 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4017 // EDIT byte mask: scalar
4018 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4019 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4020 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4021 // The movi_edit node has the immediate value already encoded, so we use
4022 // a plain imm0_255 here.
4023 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4024 (MOVID imm0_255:$shift)>;
4026 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4027 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4028 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4029 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4031 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4032 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4033 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4034 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4036 // EDIT byte mask: 2d
4038 // The movi_edit node has the immediate value already encoded, so we use
4039 // a plain imm0_255 in the pattern
4040 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4041 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
4044 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4047 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4048 // Complexity is added to break a tie with a plain MOVI.
4049 let AddedComplexity = 1 in {
4050 def : Pat<(f32 fpimm0),
4051 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4053 def : Pat<(f64 fpimm0),
4054 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4058 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4059 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4060 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4061 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4063 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4064 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4065 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4066 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4068 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4069 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4071 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4072 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4074 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4075 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4076 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4077 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4079 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4080 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4081 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4082 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4084 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4085 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4086 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4087 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4088 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4089 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4090 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4091 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4093 // EDIT per word: 2s & 4s with MSL shifter
4094 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4095 [(set (v2i32 V64:$Rd),
4096 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4097 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4098 [(set (v4i32 V128:$Rd),
4099 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4101 // Per byte: 8b & 16b
4102 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4104 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4105 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4107 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4111 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4112 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4114 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4115 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4116 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4117 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4119 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4120 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4121 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4122 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4124 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4125 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4126 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4127 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4128 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4129 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4130 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4131 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4133 // EDIT per word: 2s & 4s with MSL shifter
4134 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4135 [(set (v2i32 V64:$Rd),
4136 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4137 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4138 [(set (v4i32 V128:$Rd),
4139 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4141 //----------------------------------------------------------------------------
4142 // AdvSIMD indexed element
4143 //----------------------------------------------------------------------------
4145 let hasSideEffects = 0 in {
4146 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
4147 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
4150 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4151 // instruction expects the addend first, while the intrinsic expects it last.
4153 // On the other hand, there are quite a few valid combinatorial options due to
4154 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4155 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4156 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4157 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4158 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4160 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4161 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4162 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4163 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4164 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4165 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4166 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4167 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4169 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4170 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4172 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4173 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4174 VectorIndexS:$idx))),
4175 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4176 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4177 (v2f32 (AArch64duplane32
4178 (v4f32 (insert_subvector undef,
4179 (v2f32 (fneg V64:$Rm)),
4181 VectorIndexS:$idx)))),
4182 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4183 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4184 VectorIndexS:$idx)>;
4185 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4186 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4187 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4188 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4190 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4192 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4193 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4194 VectorIndexS:$idx))),
4195 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4196 VectorIndexS:$idx)>;
4197 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4198 (v4f32 (AArch64duplane32
4199 (v4f32 (insert_subvector undef,
4200 (v2f32 (fneg V64:$Rm)),
4202 VectorIndexS:$idx)))),
4203 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4204 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4205 VectorIndexS:$idx)>;
4206 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4207 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4208 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4209 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4211 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4212 // (DUPLANE from 64-bit would be trivial).
4213 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4214 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4215 VectorIndexD:$idx))),
4217 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4218 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4219 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4220 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4221 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4223 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4224 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4225 (vector_extract (v4f32 (fneg V128:$Rm)),
4226 VectorIndexS:$idx))),
4227 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4228 V128:$Rm, VectorIndexS:$idx)>;
4229 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4230 (vector_extract (v2f32 (fneg V64:$Rm)),
4231 VectorIndexS:$idx))),
4232 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4233 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4235 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4236 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4237 (vector_extract (v2f64 (fneg V128:$Rm)),
4238 VectorIndexS:$idx))),
4239 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4240 V128:$Rm, VectorIndexS:$idx)>;
4243 defm : FMLSIndexedAfterNegPatterns<
4244 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4245 defm : FMLSIndexedAfterNegPatterns<
4246 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4248 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4249 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4251 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4252 (FMULv2i32_indexed V64:$Rn,
4253 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4255 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4256 (FMULv4i32_indexed V128:$Rn,
4257 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4259 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4260 (FMULv2i64_indexed V128:$Rn,
4261 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4264 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4265 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4266 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4267 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4268 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4269 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4270 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4271 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4272 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4273 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4274 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4275 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4276 int_aarch64_neon_smull>;
4277 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4278 int_aarch64_neon_sqadd>;
4279 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4280 int_aarch64_neon_sqsub>;
4281 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4282 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4283 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4284 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4285 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4286 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4287 int_aarch64_neon_umull>;
4289 // A scalar sqdmull with the second operand being a vector lane can be
4290 // handled directly with the indexed instruction encoding.
4291 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4292 (vector_extract (v4i32 V128:$Vm),
4293 VectorIndexS:$idx)),
4294 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4296 //----------------------------------------------------------------------------
4297 // AdvSIMD scalar shift instructions
4298 //----------------------------------------------------------------------------
4299 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4300 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4301 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4302 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4303 // Codegen patterns for the above. We don't put these directly on the
4304 // instructions because TableGen's type inference can't handle the truth.
4305 // Having the same base pattern for fp <--> int totally freaks it out.
4306 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4307 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4308 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4309 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4310 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4311 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4312 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4313 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4314 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4316 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4317 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4319 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4320 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4321 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4322 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4323 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4324 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4325 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4326 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4327 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4328 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4330 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4331 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4333 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4335 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4336 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4337 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4338 int_aarch64_neon_sqrshrn>;
4339 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4340 int_aarch64_neon_sqrshrun>;
4341 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4342 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4343 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4344 int_aarch64_neon_sqshrn>;
4345 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4346 int_aarch64_neon_sqshrun>;
4347 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4348 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4349 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4350 TriOpFrag<(add node:$LHS,
4351 (AArch64srshri node:$MHS, node:$RHS))>>;
4352 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4353 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4354 TriOpFrag<(add node:$LHS,
4355 (AArch64vashr node:$MHS, node:$RHS))>>;
4356 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4357 int_aarch64_neon_uqrshrn>;
4358 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4359 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4360 int_aarch64_neon_uqshrn>;
4361 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4362 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4363 TriOpFrag<(add node:$LHS,
4364 (AArch64urshri node:$MHS, node:$RHS))>>;
4365 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4366 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4367 TriOpFrag<(add node:$LHS,
4368 (AArch64vlshr node:$MHS, node:$RHS))>>;
4370 //----------------------------------------------------------------------------
4371 // AdvSIMD vector shift instructions
4372 //----------------------------------------------------------------------------
4373 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4374 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4375 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4376 int_aarch64_neon_vcvtfxs2fp>;
4377 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4378 int_aarch64_neon_rshrn>;
4379 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4380 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4381 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4382 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4383 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4384 (i32 vecshiftL64:$imm))),
4385 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4386 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4387 int_aarch64_neon_sqrshrn>;
4388 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4389 int_aarch64_neon_sqrshrun>;
4390 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4391 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4392 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4393 int_aarch64_neon_sqshrn>;
4394 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4395 int_aarch64_neon_sqshrun>;
4396 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4397 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4398 (i32 vecshiftR64:$imm))),
4399 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4400 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4401 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4402 TriOpFrag<(add node:$LHS,
4403 (AArch64srshri node:$MHS, node:$RHS))> >;
4404 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4405 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4407 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4408 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4409 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4410 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4411 int_aarch64_neon_vcvtfxu2fp>;
4412 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4413 int_aarch64_neon_uqrshrn>;
4414 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4415 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4416 int_aarch64_neon_uqshrn>;
4417 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4418 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4419 TriOpFrag<(add node:$LHS,
4420 (AArch64urshri node:$MHS, node:$RHS))> >;
4421 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4422 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4423 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4424 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4425 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4427 // SHRN patterns for when a logical right shift was used instead of arithmetic
4428 // (the immediate guarantees no sign bits actually end up in the result so it
4430 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4431 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4432 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4433 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4434 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4435 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4437 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4438 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4439 vecshiftR16Narrow:$imm)))),
4440 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4441 V128:$Rn, vecshiftR16Narrow:$imm)>;
4442 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4443 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4444 vecshiftR32Narrow:$imm)))),
4445 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4446 V128:$Rn, vecshiftR32Narrow:$imm)>;
4447 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4448 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4449 vecshiftR64Narrow:$imm)))),
4450 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4451 V128:$Rn, vecshiftR32Narrow:$imm)>;
4453 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4454 // Anyexts are implemented as zexts.
4455 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4456 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4457 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4458 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4459 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4460 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4461 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4462 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4463 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4464 // Also match an extend from the upper half of a 128 bit source register.
4465 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4466 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4467 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4468 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4469 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4470 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4471 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4472 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4473 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4474 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4475 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4476 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4477 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4478 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4479 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4480 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4481 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4482 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4484 // Vector shift sxtl aliases
4485 def : InstAlias<"sxtl.8h $dst, $src1",
4486 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4487 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4488 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4489 def : InstAlias<"sxtl.4s $dst, $src1",
4490 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4491 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4492 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4493 def : InstAlias<"sxtl.2d $dst, $src1",
4494 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4495 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4496 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4498 // Vector shift sxtl2 aliases
4499 def : InstAlias<"sxtl2.8h $dst, $src1",
4500 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4501 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4502 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4503 def : InstAlias<"sxtl2.4s $dst, $src1",
4504 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4505 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4506 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4507 def : InstAlias<"sxtl2.2d $dst, $src1",
4508 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4509 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4510 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4512 // Vector shift uxtl aliases
4513 def : InstAlias<"uxtl.8h $dst, $src1",
4514 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4515 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4516 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4517 def : InstAlias<"uxtl.4s $dst, $src1",
4518 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4519 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4520 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4521 def : InstAlias<"uxtl.2d $dst, $src1",
4522 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4523 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4524 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4526 // Vector shift uxtl2 aliases
4527 def : InstAlias<"uxtl2.8h $dst, $src1",
4528 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4529 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4530 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4531 def : InstAlias<"uxtl2.4s $dst, $src1",
4532 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4533 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4534 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4535 def : InstAlias<"uxtl2.2d $dst, $src1",
4536 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4537 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4538 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4540 // If an integer is about to be converted to a floating point value,
4541 // just load it on the floating point unit.
4542 // These patterns are more complex because floating point loads do not
4543 // support sign extension.
4544 // The sign extension has to be explicitly added and is only supported for
4545 // one step: byte-to-half, half-to-word, word-to-doubleword.
4546 // SCVTF GPR -> FPR is 9 cycles.
4547 // SCVTF FPR -> FPR is 4 cyclces.
4548 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4549 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4550 // and still being faster.
4551 // However, this is not good for code size.
4552 // 8-bits -> float. 2 sizes step-up.
4553 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4554 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4555 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4560 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4566 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4568 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4569 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4570 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4571 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4572 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4573 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4574 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4575 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4577 // 16-bits -> float. 1 size step-up.
4578 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4579 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4580 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4582 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4586 ssub)))>, Requires<[NotForCodeSize]>;
4588 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4589 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4590 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4591 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4592 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4593 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4594 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4595 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4597 // 32-bits to 32-bits are handled in target specific dag combine:
4598 // performIntToFpCombine.
4599 // 64-bits integer to 32-bits floating point, not possible with
4600 // SCVTF on floating point registers (both source and destination
4601 // must have the same size).
4603 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4604 // 8-bits -> double. 3 size step-up: give up.
4605 // 16-bits -> double. 2 size step.
4606 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4607 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4608 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4613 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4619 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4621 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4622 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4623 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4624 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4625 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4626 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4627 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4628 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4629 // 32-bits -> double. 1 size step-up.
4630 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4631 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4632 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4634 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4638 dsub)))>, Requires<[NotForCodeSize]>;
4640 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4641 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4642 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4643 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4644 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4645 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4646 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4647 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4649 // 64-bits -> double are handled in target specific dag combine:
4650 // performIntToFpCombine.
4653 //----------------------------------------------------------------------------
4654 // AdvSIMD Load-Store Structure
4655 //----------------------------------------------------------------------------
4656 defm LD1 : SIMDLd1Multiple<"ld1">;
4657 defm LD2 : SIMDLd2Multiple<"ld2">;
4658 defm LD3 : SIMDLd3Multiple<"ld3">;
4659 defm LD4 : SIMDLd4Multiple<"ld4">;
4661 defm ST1 : SIMDSt1Multiple<"st1">;
4662 defm ST2 : SIMDSt2Multiple<"st2">;
4663 defm ST3 : SIMDSt3Multiple<"st3">;
4664 defm ST4 : SIMDSt4Multiple<"st4">;
4666 class Ld1Pat<ValueType ty, Instruction INST>
4667 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4669 def : Ld1Pat<v16i8, LD1Onev16b>;
4670 def : Ld1Pat<v8i16, LD1Onev8h>;
4671 def : Ld1Pat<v4i32, LD1Onev4s>;
4672 def : Ld1Pat<v2i64, LD1Onev2d>;
4673 def : Ld1Pat<v8i8, LD1Onev8b>;
4674 def : Ld1Pat<v4i16, LD1Onev4h>;
4675 def : Ld1Pat<v2i32, LD1Onev2s>;
4676 def : Ld1Pat<v1i64, LD1Onev1d>;
4678 class St1Pat<ValueType ty, Instruction INST>
4679 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4680 (INST ty:$Vt, GPR64sp:$Rn)>;
4682 def : St1Pat<v16i8, ST1Onev16b>;
4683 def : St1Pat<v8i16, ST1Onev8h>;
4684 def : St1Pat<v4i32, ST1Onev4s>;
4685 def : St1Pat<v2i64, ST1Onev2d>;
4686 def : St1Pat<v8i8, ST1Onev8b>;
4687 def : St1Pat<v4i16, ST1Onev4h>;
4688 def : St1Pat<v2i32, ST1Onev2s>;
4689 def : St1Pat<v1i64, ST1Onev1d>;
4695 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4696 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4697 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4698 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4699 let mayLoad = 1, hasSideEffects = 0 in {
4700 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4701 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4702 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4703 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4704 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4705 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4706 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4707 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4708 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4709 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4710 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4711 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4712 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4713 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4714 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4715 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4718 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4719 (LD1Rv8b GPR64sp:$Rn)>;
4720 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4721 (LD1Rv16b GPR64sp:$Rn)>;
4722 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4723 (LD1Rv4h GPR64sp:$Rn)>;
4724 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4725 (LD1Rv8h GPR64sp:$Rn)>;
4726 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4727 (LD1Rv2s GPR64sp:$Rn)>;
4728 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4729 (LD1Rv4s GPR64sp:$Rn)>;
4730 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4731 (LD1Rv2d GPR64sp:$Rn)>;
4732 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4733 (LD1Rv1d GPR64sp:$Rn)>;
4734 // Grab the floating point version too
4735 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4736 (LD1Rv2s GPR64sp:$Rn)>;
4737 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4738 (LD1Rv4s GPR64sp:$Rn)>;
4739 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4740 (LD1Rv2d GPR64sp:$Rn)>;
4741 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4742 (LD1Rv1d GPR64sp:$Rn)>;
4743 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4744 (LD1Rv4h GPR64sp:$Rn)>;
4745 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4746 (LD1Rv8h GPR64sp:$Rn)>;
4748 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4749 ValueType VTy, ValueType STy, Instruction LD1>
4750 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4751 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4752 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4754 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4755 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4756 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4757 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4758 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4759 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4760 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4762 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4763 ValueType VTy, ValueType STy, Instruction LD1>
4764 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4765 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4767 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4768 VecIndex:$idx, GPR64sp:$Rn),
4771 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4772 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4773 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4774 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4775 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4778 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4779 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4780 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4781 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4784 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4785 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4786 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4787 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4789 let AddedComplexity = 15 in
4790 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4791 ValueType VTy, ValueType STy, Instruction ST1>
4793 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4795 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4797 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4798 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4799 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4800 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4801 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4802 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4803 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
4805 let AddedComplexity = 15 in
4806 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4807 ValueType VTy, ValueType STy, Instruction ST1>
4809 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4811 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4812 VecIndex:$idx, GPR64sp:$Rn)>;
4814 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4815 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4816 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4817 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4818 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
4820 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4821 ValueType VTy, ValueType STy, Instruction ST1,
4823 def : Pat<(scalar_store
4824 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4825 GPR64sp:$Rn, offset),
4826 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4827 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4829 def : Pat<(scalar_store
4830 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4831 GPR64sp:$Rn, GPR64:$Rm),
4832 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4833 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4836 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4837 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4839 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4840 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4841 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4842 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4843 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
4845 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4846 ValueType VTy, ValueType STy, Instruction ST1,
4848 def : Pat<(scalar_store
4849 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4850 GPR64sp:$Rn, offset),
4851 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4853 def : Pat<(scalar_store
4854 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4855 GPR64sp:$Rn, GPR64:$Rm),
4856 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4859 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4861 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4863 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4864 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4865 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4866 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4867 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
4869 let mayStore = 1, hasSideEffects = 0 in {
4870 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4871 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4872 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4873 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4874 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4875 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4876 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4877 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4878 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4879 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4880 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4881 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4884 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4885 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4886 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4887 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4889 //----------------------------------------------------------------------------
4890 // Crypto extensions
4891 //----------------------------------------------------------------------------
4893 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
4894 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
4895 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
4896 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
4898 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
4899 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
4900 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
4901 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
4902 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
4903 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
4904 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
4906 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
4907 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
4908 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
4910 //----------------------------------------------------------------------------
4912 //----------------------------------------------------------------------------
4913 // FIXME: Like for X86, these should go in their own separate .td file.
4915 // Any instruction that defines a 32-bit result leaves the high half of the
4916 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4917 // be copying from a truncate. But any other 32-bit operation will zero-extend
4919 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4920 def def32 : PatLeaf<(i32 GPR32:$src), [{
4921 return N->getOpcode() != ISD::TRUNCATE &&
4922 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4923 N->getOpcode() != ISD::CopyFromReg;
4926 // In the case of a 32-bit def that is known to implicitly zero-extend,
4927 // we can use a SUBREG_TO_REG.
4928 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4930 // For an anyext, we don't care what the high bits are, so we can perform an
4931 // INSERT_SUBREF into an IMPLICIT_DEF.
4932 def : Pat<(i64 (anyext GPR32:$src)),
4933 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4935 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4936 // instruction (UBFM) on the enclosing super-reg.
4937 def : Pat<(i64 (zext GPR32:$src)),
4938 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4940 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4941 // containing super-reg.
4942 def : Pat<(i64 (sext GPR32:$src)),
4943 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4944 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4945 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4946 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4947 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4948 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4949 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4950 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4952 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4953 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4954 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4955 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4956 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4957 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4959 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4960 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4961 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4962 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4963 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4964 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4966 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4967 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4968 (i64 (i64shift_a imm0_63:$imm)),
4969 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4971 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4972 // AddedComplexity for the following patterns since we want to match sext + sra
4973 // patterns before we attempt to match a single sra node.
4974 let AddedComplexity = 20 in {
4975 // We support all sext + sra combinations which preserve at least one bit of the
4976 // original value which is to be sign extended. E.g. we support shifts up to
4978 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4979 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4980 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4981 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4983 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4984 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4985 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4986 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4988 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4989 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4990 (i64 imm0_31:$imm), 31)>;
4991 } // AddedComplexity = 20
4993 // To truncate, we can simply extract from a subregister.
4994 def : Pat<(i32 (trunc GPR64sp:$src)),
4995 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4997 // __builtin_trap() uses the BRK instruction on AArch64.
4998 def : Pat<(trap), (BRK 1)>;
5000 // Conversions within AdvSIMD types in the same register size are free.
5001 // But because we need a consistent lane ordering, in big endian many
5002 // conversions require one or more REV instructions.
5004 // Consider a simple memory load followed by a bitconvert then a store.
5006 // v1 = BITCAST v2i32 v0 to v4i16
5009 // In big endian mode every memory access has an implicit byte swap. LDR and
5010 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5011 // is, they treat the vector as a sequence of elements to be byte-swapped.
5012 // The two pairs of instructions are fundamentally incompatible. We've decided
5013 // to use LD1/ST1 only to simplify compiler implementation.
5015 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5016 // the original code sequence:
5018 // v1 = REV v2i32 (implicit)
5019 // v2 = BITCAST v2i32 v1 to v4i16
5020 // v3 = REV v4i16 v2 (implicit)
5023 // But this is now broken - the value stored is different to the value loaded
5024 // due to lane reordering. To fix this, on every BITCAST we must perform two
5027 // v1 = REV v2i32 (implicit)
5029 // v3 = BITCAST v2i32 v2 to v4i16
5031 // v5 = REV v4i16 v4 (implicit)
5034 // This means an extra two instructions, but actually in most cases the two REV
5035 // instructions can be combined into one. For example:
5036 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5038 // There is also no 128-bit REV instruction. This must be synthesized with an
5041 // Most bitconverts require some sort of conversion. The only exceptions are:
5042 // a) Identity conversions - vNfX <-> vNiX
5043 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5046 // Natural vector casts (64 bit)
5047 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5048 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5049 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5050 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5051 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5053 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5054 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5055 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5056 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5058 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5059 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5060 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5061 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5063 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5064 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5065 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5066 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5067 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5068 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5070 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5071 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5072 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5073 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5074 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5076 // Natural vector casts (128 bit)
5077 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5078 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5079 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5080 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5081 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5083 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5084 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5085 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5086 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5088 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5089 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5090 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5091 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5093 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5094 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5095 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5096 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5097 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5098 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5100 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5101 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5102 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5103 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5104 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5106 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5107 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5108 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5109 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5110 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5112 let Predicates = [IsLE] in {
5113 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5114 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5115 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5116 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5117 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5119 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5120 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5121 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5122 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5123 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5124 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5125 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5126 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5127 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5128 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5129 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5130 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5132 let Predicates = [IsBE] in {
5133 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5134 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5135 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5136 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5137 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5138 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5139 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5140 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5141 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5142 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5144 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5145 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5146 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5147 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5148 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5149 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5150 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5151 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5152 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5153 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5155 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5156 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5157 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5158 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5159 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5160 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5161 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5162 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5163 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5165 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5166 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5167 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5168 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5169 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5170 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5171 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5172 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5173 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5174 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5176 let Predicates = [IsLE] in {
5177 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5178 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5179 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5180 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5181 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5183 let Predicates = [IsBE] in {
5184 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5185 (v1i64 (REV64v2i32 FPR64:$src))>;
5186 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5187 (v1i64 (REV64v4i16 FPR64:$src))>;
5188 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5189 (v1i64 (REV64v8i8 FPR64:$src))>;
5190 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5191 (v1i64 (REV64v4i16 FPR64:$src))>;
5192 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5193 (v1i64 (REV64v2i32 FPR64:$src))>;
5195 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5196 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5198 let Predicates = [IsLE] in {
5199 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5200 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5201 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5202 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5203 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5204 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5206 let Predicates = [IsBE] in {
5207 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5208 (v2i32 (REV64v2i32 FPR64:$src))>;
5209 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5210 (v2i32 (REV32v4i16 FPR64:$src))>;
5211 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5212 (v2i32 (REV32v8i8 FPR64:$src))>;
5213 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5214 (v2i32 (REV64v2i32 FPR64:$src))>;
5215 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5216 (v2i32 (REV64v2i32 FPR64:$src))>;
5217 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5218 (v2i32 (REV64v4i16 FPR64:$src))>;
5220 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5222 let Predicates = [IsLE] in {
5223 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5224 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5225 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5226 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5227 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5228 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5229 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5231 let Predicates = [IsBE] in {
5232 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5233 (v4i16 (REV64v4i16 FPR64:$src))>;
5234 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5235 (v4i16 (REV32v4i16 FPR64:$src))>;
5236 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5237 (v4i16 (REV16v8i8 FPR64:$src))>;
5238 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5239 (v4i16 (REV64v4i16 FPR64:$src))>;
5240 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5241 (v4i16 (REV32v4i16 FPR64:$src))>;
5242 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5243 (v4i16 (REV32v4i16 FPR64:$src))>;
5244 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5245 (v4i16 (REV64v4i16 FPR64:$src))>;
5248 let Predicates = [IsLE] in {
5249 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5250 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5251 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5252 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5253 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5254 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5255 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5257 let Predicates = [IsBE] in {
5258 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5259 (v4f16 (REV64v4i16 FPR64:$src))>;
5260 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5261 (v4f16 (REV64v4i16 FPR64:$src))>;
5262 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5263 (v4f16 (REV64v4i16 FPR64:$src))>;
5264 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5265 (v4f16 (REV16v8i8 FPR64:$src))>;
5266 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5267 (v4f16 (REV64v4i16 FPR64:$src))>;
5268 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5269 (v4f16 (REV64v4i16 FPR64:$src))>;
5270 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5271 (v4f16 (REV64v4i16 FPR64:$src))>;
5276 let Predicates = [IsLE] in {
5277 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5278 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5279 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5280 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5281 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5282 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5283 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5285 let Predicates = [IsBE] in {
5286 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5287 (v8i8 (REV64v8i8 FPR64:$src))>;
5288 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5289 (v8i8 (REV32v8i8 FPR64:$src))>;
5290 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5291 (v8i8 (REV16v8i8 FPR64:$src))>;
5292 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5293 (v8i8 (REV64v8i8 FPR64:$src))>;
5294 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5295 (v8i8 (REV32v8i8 FPR64:$src))>;
5296 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5297 (v8i8 (REV64v8i8 FPR64:$src))>;
5298 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5299 (v8i8 (REV16v8i8 FPR64:$src))>;
5302 let Predicates = [IsLE] in {
5303 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5304 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5305 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5306 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5307 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5309 let Predicates = [IsBE] in {
5310 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5311 (f64 (REV64v2i32 FPR64:$src))>;
5312 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5313 (f64 (REV64v4i16 FPR64:$src))>;
5314 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5315 (f64 (REV64v2i32 FPR64:$src))>;
5316 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5317 (f64 (REV64v8i8 FPR64:$src))>;
5318 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5319 (f64 (REV64v4i16 FPR64:$src))>;
5321 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5322 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5324 let Predicates = [IsLE] in {
5325 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5326 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5327 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5328 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5329 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5331 let Predicates = [IsBE] in {
5332 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5333 (v1f64 (REV64v2i32 FPR64:$src))>;
5334 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5335 (v1f64 (REV64v4i16 FPR64:$src))>;
5336 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5337 (v1f64 (REV64v8i8 FPR64:$src))>;
5338 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5339 (v1f64 (REV64v2i32 FPR64:$src))>;
5340 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5341 (v1f64 (REV64v4i16 FPR64:$src))>;
5343 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5344 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5346 let Predicates = [IsLE] in {
5347 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5348 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5349 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5350 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5351 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5352 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5354 let Predicates = [IsBE] in {
5355 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5356 (v2f32 (REV64v2i32 FPR64:$src))>;
5357 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5358 (v2f32 (REV32v4i16 FPR64:$src))>;
5359 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5360 (v2f32 (REV32v8i8 FPR64:$src))>;
5361 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5362 (v2f32 (REV64v2i32 FPR64:$src))>;
5363 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5364 (v2f32 (REV64v2i32 FPR64:$src))>;
5365 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5366 (v2f32 (REV64v4i16 FPR64:$src))>;
5368 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5370 let Predicates = [IsLE] in {
5371 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5372 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5373 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5374 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5375 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5376 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5377 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5379 let Predicates = [IsBE] in {
5380 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5381 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5382 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5383 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5384 (REV64v4i32 FPR128:$src), (i32 8)))>;
5385 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5386 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5387 (REV64v8i16 FPR128:$src), (i32 8)))>;
5388 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5389 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5390 (REV64v8i16 FPR128:$src), (i32 8)))>;
5391 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5392 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5393 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5394 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5395 (REV64v4i32 FPR128:$src), (i32 8)))>;
5396 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5397 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5398 (REV64v16i8 FPR128:$src), (i32 8)))>;
5401 let Predicates = [IsLE] in {
5402 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5403 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5404 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5405 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5406 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5407 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5409 let Predicates = [IsBE] in {
5410 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5411 (v2f64 (EXTv16i8 FPR128:$src,
5412 FPR128:$src, (i32 8)))>;
5413 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5414 (v2f64 (REV64v4i32 FPR128:$src))>;
5415 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5416 (v2f64 (REV64v8i16 FPR128:$src))>;
5417 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5418 (v2f64 (REV64v8i16 FPR128:$src))>;
5419 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5420 (v2f64 (REV64v16i8 FPR128:$src))>;
5421 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5422 (v2f64 (REV64v4i32 FPR128:$src))>;
5424 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5426 let Predicates = [IsLE] in {
5427 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5428 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5429 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5430 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5431 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5432 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5434 let Predicates = [IsBE] in {
5435 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5436 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5437 (REV64v4i32 FPR128:$src), (i32 8)))>;
5438 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5439 (v4f32 (REV32v8i16 FPR128:$src))>;
5440 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5441 (v4f32 (REV32v8i16 FPR128:$src))>;
5442 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5443 (v4f32 (REV32v16i8 FPR128:$src))>;
5444 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5445 (v4f32 (REV64v4i32 FPR128:$src))>;
5446 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5447 (v4f32 (REV64v4i32 FPR128:$src))>;
5449 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5451 let Predicates = [IsLE] in {
5452 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5453 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5454 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5455 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5456 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5457 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5459 let Predicates = [IsBE] in {
5460 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5461 (v2i64 (EXTv16i8 FPR128:$src,
5462 FPR128:$src, (i32 8)))>;
5463 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5464 (v2i64 (REV64v4i32 FPR128:$src))>;
5465 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5466 (v2i64 (REV64v8i16 FPR128:$src))>;
5467 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5468 (v2i64 (REV64v16i8 FPR128:$src))>;
5469 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5470 (v2i64 (REV64v4i32 FPR128:$src))>;
5471 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5472 (v2i64 (REV64v8i16 FPR128:$src))>;
5474 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5476 let Predicates = [IsLE] in {
5477 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5478 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5479 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5480 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5481 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5482 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5484 let Predicates = [IsBE] in {
5485 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5486 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5487 (REV64v4i32 FPR128:$src),
5489 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5490 (v4i32 (REV64v4i32 FPR128:$src))>;
5491 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5492 (v4i32 (REV32v8i16 FPR128:$src))>;
5493 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5494 (v4i32 (REV32v16i8 FPR128:$src))>;
5495 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5496 (v4i32 (REV64v4i32 FPR128:$src))>;
5497 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5498 (v4i32 (REV32v8i16 FPR128:$src))>;
5500 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5502 let Predicates = [IsLE] in {
5503 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5504 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5505 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5506 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5507 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5508 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5509 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5511 let Predicates = [IsBE] in {
5512 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5513 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5514 (REV64v8i16 FPR128:$src),
5516 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5517 (v8i16 (REV64v8i16 FPR128:$src))>;
5518 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5519 (v8i16 (REV32v8i16 FPR128:$src))>;
5520 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5521 (v8i16 (REV16v16i8 FPR128:$src))>;
5522 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5523 (v8i16 (REV64v8i16 FPR128:$src))>;
5524 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5525 (v8i16 (REV32v8i16 FPR128:$src))>;
5526 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5527 (v8i16 (REV32v8i16 FPR128:$src))>;
5530 let Predicates = [IsLE] in {
5531 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5532 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5533 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5534 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5535 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5536 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5537 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5539 let Predicates = [IsBE] in {
5540 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5541 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5542 (REV64v8i16 FPR128:$src),
5544 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5545 (v8f16 (REV64v8i16 FPR128:$src))>;
5546 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5547 (v8f16 (REV32v8i16 FPR128:$src))>;
5548 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5549 (v8f16 (REV64v8i16 FPR128:$src))>;
5550 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5551 (v8f16 (REV16v16i8 FPR128:$src))>;
5552 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5553 (v8f16 (REV64v8i16 FPR128:$src))>;
5554 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5555 (v8f16 (REV32v8i16 FPR128:$src))>;
5558 let Predicates = [IsLE] in {
5559 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5560 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5561 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5562 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5563 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5564 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5565 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5567 let Predicates = [IsBE] in {
5568 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5569 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5570 (REV64v16i8 FPR128:$src),
5572 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5573 (v16i8 (REV64v16i8 FPR128:$src))>;
5574 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5575 (v16i8 (REV32v16i8 FPR128:$src))>;
5576 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5577 (v16i8 (REV16v16i8 FPR128:$src))>;
5578 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5579 (v16i8 (REV64v16i8 FPR128:$src))>;
5580 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5581 (v16i8 (REV32v16i8 FPR128:$src))>;
5582 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5583 (v16i8 (REV16v16i8 FPR128:$src))>;
5586 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5587 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5588 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5589 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5590 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5591 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5592 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5593 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5595 // A 64-bit subvector insert to the first 128-bit vector position
5596 // is a subregister copy that needs no instruction.
5597 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5598 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5599 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5600 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5601 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5602 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5603 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5604 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5605 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5606 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5607 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5608 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5609 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5610 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5612 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5614 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5615 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5616 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5617 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5618 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5619 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5620 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5621 // so we match on v4f32 here, not v2f32. This will also catch adding
5622 // the low two lanes of a true v4f32 vector.
5623 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5624 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5625 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5627 // Scalar 64-bit shifts in FPR64 registers.
5628 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5629 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5630 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5631 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5632 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5633 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5634 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5635 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5637 // Tail call return handling. These are all compiler pseudo-instructions,
5638 // so no encoding information or anything like that.
5639 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5640 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5641 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5644 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5645 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5646 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5647 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5648 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5649 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5651 include "AArch64InstrAtomics.td"