1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
27 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
29 //===----------------------------------------------------------------------===//
30 // AArch64-specific DAG Nodes.
33 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
34 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
39 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
40 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
46 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
47 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
54 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
55 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
57 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
58 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
59 SDTCisVT<2, OtherVT>]>;
62 def SDT_AArch64CSel : SDTypeProfile<1, 4,
67 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
70 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
71 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
72 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
75 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
76 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
77 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
78 SDTCisInt<2>, SDTCisInt<3>]>;
79 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
80 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
82 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
84 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
85 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
86 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
87 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
89 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
92 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
93 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
95 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
97 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
99 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
100 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
101 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
102 SDTCisSameAs<1, 4>]>;
106 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
107 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
108 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
109 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
110 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
111 [SDNPHasChain, SDNPOutGlue]>;
112 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
113 SDCallSeqEnd<[ SDTCisVT<0, i32>,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
116 def AArch64call : SDNode<"AArch64ISD::CALL",
117 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
122 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
124 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
126 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
128 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
132 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
133 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
134 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
135 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
136 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
137 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
138 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
139 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
140 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
142 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
143 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
145 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
146 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
148 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
150 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
152 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
153 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
155 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
156 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
157 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
158 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
159 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
161 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
162 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
163 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
164 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
165 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
166 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
168 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
169 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
170 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
171 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
172 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
173 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
174 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
176 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
177 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
178 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
179 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
181 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
182 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
183 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
184 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
185 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
186 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
187 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
188 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
190 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
191 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
192 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
194 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
195 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
196 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
197 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
198 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
200 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
201 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
202 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
204 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
205 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
206 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
207 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
208 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
209 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
210 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
212 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
213 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
214 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
215 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
216 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
218 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
219 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
221 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
223 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
224 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
226 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
227 [SDNPHasChain, SDNPSideEffect]>;
229 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
230 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
232 def AArch64tlsdesc_call : SDNode<"AArch64ISD::TLSDESC_CALL",
233 SDT_AArch64TLSDescCall,
234 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
237 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
238 SDT_AArch64WrapperLarge>;
241 //===----------------------------------------------------------------------===//
243 //===----------------------------------------------------------------------===//
245 // AArch64 Instruction Predicate Definitions.
247 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
248 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
249 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
250 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
251 def ForCodeSize : Predicate<"ForCodeSize">;
252 def NotForCodeSize : Predicate<"!ForCodeSize">;
254 include "AArch64InstrFormats.td"
256 //===----------------------------------------------------------------------===//
258 //===----------------------------------------------------------------------===//
259 // Miscellaneous instructions.
260 //===----------------------------------------------------------------------===//
262 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
263 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
264 [(AArch64callseq_start timm:$amt)]>;
265 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
266 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
267 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
269 let isReMaterializable = 1, isCodeGenOnly = 1 in {
270 // FIXME: The following pseudo instructions are only needed because remat
271 // cannot handle multiple instructions. When that changes, they can be
272 // removed, along with the AArch64Wrapper node.
274 let AddedComplexity = 10 in
275 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
276 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
279 // The MOVaddr instruction should match only when the add is not folded
280 // into a load or store address.
282 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
283 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
284 tglobaladdr:$low))]>,
285 Sched<[WriteAdrAdr]>;
287 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
288 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
290 Sched<[WriteAdrAdr]>;
292 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
293 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
295 Sched<[WriteAdrAdr]>;
297 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
298 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
299 tblockaddress:$low))]>,
300 Sched<[WriteAdrAdr]>;
302 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
303 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
304 tglobaltlsaddr:$low))]>,
305 Sched<[WriteAdrAdr]>;
307 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
308 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
309 texternalsym:$low))]>,
310 Sched<[WriteAdrAdr]>;
312 } // isReMaterializable, isCodeGenOnly
314 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
315 (LOADgot tglobaltlsaddr:$addr)>;
317 def : Pat<(AArch64LOADgot texternalsym:$addr),
318 (LOADgot texternalsym:$addr)>;
320 def : Pat<(AArch64LOADgot tconstpool:$addr),
321 (LOADgot tconstpool:$addr)>;
323 //===----------------------------------------------------------------------===//
324 // System instructions.
325 //===----------------------------------------------------------------------===//
327 def HINT : HintI<"hint">;
328 def : InstAlias<"nop", (HINT 0b000)>;
329 def : InstAlias<"yield",(HINT 0b001)>;
330 def : InstAlias<"wfe", (HINT 0b010)>;
331 def : InstAlias<"wfi", (HINT 0b011)>;
332 def : InstAlias<"sev", (HINT 0b100)>;
333 def : InstAlias<"sevl", (HINT 0b101)>;
335 // As far as LLVM is concerned this writes to the system's exclusive monitors.
336 let mayLoad = 1, mayStore = 1 in
337 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
339 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
340 // model patterns with sufficiently fine granularity.
341 let mayLoad = ?, mayStore = ? in {
342 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
343 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
345 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
346 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
348 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
349 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
352 def : InstAlias<"clrex", (CLREX 0xf)>;
353 def : InstAlias<"isb", (ISB 0xf)>;
357 def MSRpstate: MSRpstateI;
359 // The thread pointer (on Linux, at least, where this has been implemented) is
361 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
363 // Generic system instructions
364 def SYSxt : SystemXtI<0, "sys">;
365 def SYSLxt : SystemLXtI<1, "sysl">;
367 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
368 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
369 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
371 //===----------------------------------------------------------------------===//
372 // Move immediate instructions.
373 //===----------------------------------------------------------------------===//
375 defm MOVK : InsertImmediate<0b11, "movk">;
376 defm MOVN : MoveImmediate<0b00, "movn">;
378 let PostEncoderMethod = "fixMOVZ" in
379 defm MOVZ : MoveImmediate<0b10, "movz">;
381 // First group of aliases covers an implicit "lsl #0".
382 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
383 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
384 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
385 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
386 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
387 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
389 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
390 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
391 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
392 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
393 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
395 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
396 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
397 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
398 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
400 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
401 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
402 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
403 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
405 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
406 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
408 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
409 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
411 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
412 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
414 // Final group of aliases covers true "mov $Rd, $imm" cases.
415 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
416 int width, int shift> {
417 def _asmoperand : AsmOperandClass {
418 let Name = basename # width # "_lsl" # shift # "MovAlias";
419 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
421 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
424 def _movimm : Operand<i32> {
425 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
428 def : InstAlias<"mov $Rd, $imm",
429 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
432 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
433 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
435 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
436 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
437 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
438 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
440 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
441 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
443 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
444 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
445 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
446 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
448 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
449 isAsCheapAsAMove = 1 in {
450 // FIXME: The following pseudo instructions are only needed because remat
451 // cannot handle multiple instructions. When that changes, we can select
452 // directly to the real instructions and get rid of these pseudos.
455 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
456 [(set GPR32:$dst, imm:$src)]>,
459 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
460 [(set GPR64:$dst, imm:$src)]>,
462 } // isReMaterializable, isCodeGenOnly
464 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
465 // eventual expansion code fewer bits to worry about getting right. Marshalling
466 // the types is a little tricky though:
467 def i64imm_32bit : ImmLeaf<i64, [{
468 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
471 def trunc_imm : SDNodeXForm<imm, [{
472 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
475 def : Pat<(i64 i64imm_32bit:$src),
476 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
478 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
480 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
481 tglobaladdr:$g1, tglobaladdr:$g0),
482 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
483 tglobaladdr:$g2, 32),
484 tglobaladdr:$g1, 16),
485 tglobaladdr:$g0, 0)>;
487 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
488 tblockaddress:$g1, tblockaddress:$g0),
489 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
490 tblockaddress:$g2, 32),
491 tblockaddress:$g1, 16),
492 tblockaddress:$g0, 0)>;
494 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
495 tconstpool:$g1, tconstpool:$g0),
496 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
501 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
502 tjumptable:$g1, tjumptable:$g0),
503 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
509 //===----------------------------------------------------------------------===//
510 // Arithmetic instructions.
511 //===----------------------------------------------------------------------===//
513 // Add/subtract with carry.
514 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
515 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
517 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
518 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
519 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
520 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
523 defm ADD : AddSub<0, "add", add>;
524 defm SUB : AddSub<1, "sub">;
526 def : InstAlias<"mov $dst, $src",
527 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
528 def : InstAlias<"mov $dst, $src",
529 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
530 def : InstAlias<"mov $dst, $src",
531 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
532 def : InstAlias<"mov $dst, $src",
533 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
535 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
536 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
538 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
539 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
540 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
541 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
542 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
543 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
544 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
545 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
546 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
547 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
548 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
549 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
550 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
551 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
552 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
553 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
554 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
556 // Because of the immediate format for add/sub-imm instructions, the
557 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
558 // These patterns capture that transformation.
559 let AddedComplexity = 1 in {
560 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
561 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
562 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
563 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
564 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
565 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
566 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
567 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
570 // Because of the immediate format for add/sub-imm instructions, the
571 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
572 // These patterns capture that transformation.
573 let AddedComplexity = 1 in {
574 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
575 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
576 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
577 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
578 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
579 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
580 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
581 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
584 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
585 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
586 def : InstAlias<"neg $dst, $src$shift",
587 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
588 def : InstAlias<"neg $dst, $src$shift",
589 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
591 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
592 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
593 def : InstAlias<"negs $dst, $src$shift",
594 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
595 def : InstAlias<"negs $dst, $src$shift",
596 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
599 // Unsigned/Signed divide
600 defm UDIV : Div<0, "udiv", udiv>;
601 defm SDIV : Div<1, "sdiv", sdiv>;
602 let isCodeGenOnly = 1 in {
603 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
604 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
608 defm ASRV : Shift<0b10, "asr", sra>;
609 defm LSLV : Shift<0b00, "lsl", shl>;
610 defm LSRV : Shift<0b01, "lsr", srl>;
611 defm RORV : Shift<0b11, "ror", rotr>;
613 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
614 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
615 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
616 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
617 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
618 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
619 def : ShiftAlias<"rorv", RORVWr, GPR32>;
620 def : ShiftAlias<"rorv", RORVXr, GPR64>;
623 let AddedComplexity = 7 in {
624 defm MADD : MulAccum<0, "madd", add>;
625 defm MSUB : MulAccum<1, "msub", sub>;
627 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
628 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
629 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
630 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
632 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
633 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
634 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
635 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
636 } // AddedComplexity = 7
638 let AddedComplexity = 5 in {
639 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
640 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
641 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
642 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
644 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
645 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
646 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
647 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
649 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
650 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
651 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
652 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
653 } // AddedComplexity = 5
655 def : MulAccumWAlias<"mul", MADDWrrr>;
656 def : MulAccumXAlias<"mul", MADDXrrr>;
657 def : MulAccumWAlias<"mneg", MSUBWrrr>;
658 def : MulAccumXAlias<"mneg", MSUBXrrr>;
659 def : WideMulAccumAlias<"smull", SMADDLrrr>;
660 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
661 def : WideMulAccumAlias<"umull", UMADDLrrr>;
662 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
665 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
666 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
669 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
670 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
671 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
672 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
674 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
675 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
676 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
677 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
680 //===----------------------------------------------------------------------===//
681 // Logical instructions.
682 //===----------------------------------------------------------------------===//
685 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
686 defm AND : LogicalImm<0b00, "and", and, "bic">;
687 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
688 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
690 // FIXME: these aliases *are* canonical sometimes (when movz can't be
691 // used). Actually, it seems to be working right now, but putting logical_immXX
692 // here is a bit dodgy on the AsmParser side too.
693 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
694 logical_imm32:$imm), 0>;
695 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
696 logical_imm64:$imm), 0>;
700 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
701 defm BICS : LogicalRegS<0b11, 1, "bics",
702 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
703 defm AND : LogicalReg<0b00, 0, "and", and>;
704 defm BIC : LogicalReg<0b00, 1, "bic",
705 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
706 defm EON : LogicalReg<0b10, 1, "eon",
707 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
708 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
709 defm ORN : LogicalReg<0b01, 1, "orn",
710 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
711 defm ORR : LogicalReg<0b01, 0, "orr", or>;
713 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
714 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
716 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
717 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
719 def : InstAlias<"mvn $Wd, $Wm$sh",
720 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
721 def : InstAlias<"mvn $Xd, $Xm$sh",
722 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
724 def : InstAlias<"tst $src1, $src2",
725 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
726 def : InstAlias<"tst $src1, $src2",
727 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
729 def : InstAlias<"tst $src1, $src2",
730 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
731 def : InstAlias<"tst $src1, $src2",
732 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
734 def : InstAlias<"tst $src1, $src2$sh",
735 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
736 def : InstAlias<"tst $src1, $src2$sh",
737 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
740 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
741 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
744 //===----------------------------------------------------------------------===//
745 // One operand data processing instructions.
746 //===----------------------------------------------------------------------===//
748 defm CLS : OneOperandData<0b101, "cls">;
749 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
750 defm RBIT : OneOperandData<0b000, "rbit">;
752 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
753 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
755 def REV16Wr : OneWRegData<0b001, "rev16",
756 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
757 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
759 def : Pat<(cttz GPR32:$Rn),
760 (CLZWr (RBITWr GPR32:$Rn))>;
761 def : Pat<(cttz GPR64:$Rn),
762 (CLZXr (RBITXr GPR64:$Rn))>;
763 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
766 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
770 // Unlike the other one operand instructions, the instructions with the "rev"
771 // mnemonic do *not* just different in the size bit, but actually use different
772 // opcode bits for the different sizes.
773 def REVWr : OneWRegData<0b010, "rev", bswap>;
774 def REVXr : OneXRegData<0b011, "rev", bswap>;
775 def REV32Xr : OneXRegData<0b010, "rev32",
776 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
778 // The bswap commutes with the rotr so we want a pattern for both possible
780 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
781 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
783 //===----------------------------------------------------------------------===//
784 // Bitfield immediate extraction instruction.
785 //===----------------------------------------------------------------------===//
786 let neverHasSideEffects = 1 in
787 defm EXTR : ExtractImm<"extr">;
788 def : InstAlias<"ror $dst, $src, $shift",
789 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
790 def : InstAlias<"ror $dst, $src, $shift",
791 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
793 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
794 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
795 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
796 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
798 //===----------------------------------------------------------------------===//
799 // Other bitfield immediate instructions.
800 //===----------------------------------------------------------------------===//
801 let neverHasSideEffects = 1 in {
802 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
803 defm SBFM : BitfieldImm<0b00, "sbfm">;
804 defm UBFM : BitfieldImm<0b10, "ubfm">;
807 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
808 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
809 return CurDAG->getTargetConstant(enc, MVT::i64);
812 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
813 uint64_t enc = 31 - N->getZExtValue();
814 return CurDAG->getTargetConstant(enc, MVT::i64);
817 // min(7, 31 - shift_amt)
818 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
819 uint64_t enc = 31 - N->getZExtValue();
820 enc = enc > 7 ? 7 : enc;
821 return CurDAG->getTargetConstant(enc, MVT::i64);
824 // min(15, 31 - shift_amt)
825 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
826 uint64_t enc = 31 - N->getZExtValue();
827 enc = enc > 15 ? 15 : enc;
828 return CurDAG->getTargetConstant(enc, MVT::i64);
831 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
832 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
833 return CurDAG->getTargetConstant(enc, MVT::i64);
836 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
837 uint64_t enc = 63 - N->getZExtValue();
838 return CurDAG->getTargetConstant(enc, MVT::i64);
841 // min(7, 63 - shift_amt)
842 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
843 uint64_t enc = 63 - N->getZExtValue();
844 enc = enc > 7 ? 7 : enc;
845 return CurDAG->getTargetConstant(enc, MVT::i64);
848 // min(15, 63 - shift_amt)
849 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
850 uint64_t enc = 63 - N->getZExtValue();
851 enc = enc > 15 ? 15 : enc;
852 return CurDAG->getTargetConstant(enc, MVT::i64);
855 // min(31, 63 - shift_amt)
856 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
857 uint64_t enc = 63 - N->getZExtValue();
858 enc = enc > 31 ? 31 : enc;
859 return CurDAG->getTargetConstant(enc, MVT::i64);
862 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
863 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
864 (i64 (i32shift_b imm0_31:$imm)))>;
865 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
866 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
867 (i64 (i64shift_b imm0_63:$imm)))>;
869 let AddedComplexity = 10 in {
870 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
871 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
872 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
873 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
876 def : InstAlias<"asr $dst, $src, $shift",
877 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
878 def : InstAlias<"asr $dst, $src, $shift",
879 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
880 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
881 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
882 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
883 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
884 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
886 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
887 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
888 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
889 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
891 def : InstAlias<"lsr $dst, $src, $shift",
892 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
893 def : InstAlias<"lsr $dst, $src, $shift",
894 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
895 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
896 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
897 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
898 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
899 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
901 //===----------------------------------------------------------------------===//
902 // Conditionally set flags instructions.
903 //===----------------------------------------------------------------------===//
904 defm CCMN : CondSetFlagsImm<0, "ccmn">;
905 defm CCMP : CondSetFlagsImm<1, "ccmp">;
907 defm CCMN : CondSetFlagsReg<0, "ccmn">;
908 defm CCMP : CondSetFlagsReg<1, "ccmp">;
910 //===----------------------------------------------------------------------===//
911 // Conditional select instructions.
912 //===----------------------------------------------------------------------===//
913 defm CSEL : CondSelect<0, 0b00, "csel">;
915 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
916 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
917 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
918 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
920 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
921 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
922 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
923 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
924 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
925 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
926 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
927 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
928 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
929 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
930 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
931 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
933 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
934 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
935 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
936 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
937 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
938 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
939 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
940 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
942 // The inverse of the condition code from the alias instruction is what is used
943 // in the aliased instruction. The parser all ready inverts the condition code
944 // for these aliases.
945 def : InstAlias<"cset $dst, $cc",
946 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
947 def : InstAlias<"cset $dst, $cc",
948 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
950 def : InstAlias<"csetm $dst, $cc",
951 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
952 def : InstAlias<"csetm $dst, $cc",
953 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
955 def : InstAlias<"cinc $dst, $src, $cc",
956 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
957 def : InstAlias<"cinc $dst, $src, $cc",
958 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
960 def : InstAlias<"cinv $dst, $src, $cc",
961 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
962 def : InstAlias<"cinv $dst, $src, $cc",
963 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
965 def : InstAlias<"cneg $dst, $src, $cc",
966 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
967 def : InstAlias<"cneg $dst, $src, $cc",
968 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
970 //===----------------------------------------------------------------------===//
971 // PC-relative instructions.
972 //===----------------------------------------------------------------------===//
973 let isReMaterializable = 1 in {
974 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
975 def ADR : ADRI<0, "adr", adrlabel, []>;
976 } // neverHasSideEffects = 1
978 def ADRP : ADRI<1, "adrp", adrplabel,
979 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
980 } // isReMaterializable = 1
982 // page address of a constant pool entry, block address
983 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
984 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
986 //===----------------------------------------------------------------------===//
987 // Unconditional branch (register) instructions.
988 //===----------------------------------------------------------------------===//
990 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
991 def RET : BranchReg<0b0010, "ret", []>;
992 def DRPS : SpecialReturn<0b0101, "drps">;
993 def ERET : SpecialReturn<0b0100, "eret">;
994 } // isReturn = 1, isTerminator = 1, isBarrier = 1
996 // Default to the LR register.
997 def : InstAlias<"ret", (RET LR)>;
999 let isCall = 1, Defs = [LR], Uses = [SP] in {
1000 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1003 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1004 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1005 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1007 // Create a separate pseudo-instruction for codegen to use so that we don't
1008 // flag lr as used in every function. It'll be restored before the RET by the
1009 // epilogue if it's legitimately used.
1010 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1011 let isTerminator = 1;
1016 // This is a directive-like pseudo-instruction. The purpose is to insert an
1017 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1018 // (which in the usual case is a BLR).
1019 let hasSideEffects = 1 in
1020 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1021 let AsmString = ".tlsdesccall $sym";
1024 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
1025 // gets expanded to two MCInsts during lowering.
1026 let isCall = 1, Defs = [LR] in
1028 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
1029 [(AArch64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
1031 def : Pat<(AArch64tlsdesc_call GPR64:$dest, texternalsym:$sym),
1032 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
1033 //===----------------------------------------------------------------------===//
1034 // Conditional branch (immediate) instruction.
1035 //===----------------------------------------------------------------------===//
1036 def Bcc : BranchCond;
1038 //===----------------------------------------------------------------------===//
1039 // Compare-and-branch instructions.
1040 //===----------------------------------------------------------------------===//
1041 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1042 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1044 //===----------------------------------------------------------------------===//
1045 // Test-bit-and-branch instructions.
1046 //===----------------------------------------------------------------------===//
1047 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1048 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1050 //===----------------------------------------------------------------------===//
1051 // Unconditional branch (immediate) instructions.
1052 //===----------------------------------------------------------------------===//
1053 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1054 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1055 } // isBranch, isTerminator, isBarrier
1057 let isCall = 1, Defs = [LR], Uses = [SP] in {
1058 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1060 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1062 //===----------------------------------------------------------------------===//
1063 // Exception generation instructions.
1064 //===----------------------------------------------------------------------===//
1065 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1066 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1067 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1068 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1069 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1070 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1071 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1072 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1074 // DCPSn defaults to an immediate operand of zero if unspecified.
1075 def : InstAlias<"dcps1", (DCPS1 0)>;
1076 def : InstAlias<"dcps2", (DCPS2 0)>;
1077 def : InstAlias<"dcps3", (DCPS3 0)>;
1079 //===----------------------------------------------------------------------===//
1080 // Load instructions.
1081 //===----------------------------------------------------------------------===//
1083 // Pair (indexed, offset)
1084 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1085 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1086 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1087 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1088 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1090 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1092 // Pair (pre-indexed)
1093 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1094 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1095 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1096 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1097 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1099 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1101 // Pair (post-indexed)
1102 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1103 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1104 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1105 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1106 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1108 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1111 // Pair (no allocate)
1112 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1113 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1114 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1115 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1116 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1119 // (register offset)
1123 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1124 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1125 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1126 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1129 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1130 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1131 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1132 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1133 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1135 // Load sign-extended half-word
1136 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1137 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1139 // Load sign-extended byte
1140 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1141 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1143 // Load sign-extended word
1144 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1147 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1149 // For regular load, we do not have any alignment requirement.
1150 // Thus, it is safe to directly map the vector loads with interesting
1151 // addressing modes.
1152 // FIXME: We could do the same for bitconvert to floating point vectors.
1153 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1154 ValueType ScalTy, ValueType VecTy,
1155 Instruction LOADW, Instruction LOADX,
1157 def : Pat<(VecTy (scalar_to_vector (ScalTy
1158 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1159 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1160 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1163 def : Pat<(VecTy (scalar_to_vector (ScalTy
1164 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1165 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1166 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1170 let AddedComplexity = 10 in {
1171 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1172 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1174 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1175 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1177 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1178 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1180 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1181 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1183 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1185 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1188 def : Pat <(v1i64 (scalar_to_vector (i64
1189 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1190 ro_Wextend64:$extend))))),
1191 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1193 def : Pat <(v1i64 (scalar_to_vector (i64
1194 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1195 ro_Xextend64:$extend))))),
1196 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1199 // Match all load 64 bits width whose type is compatible with FPR64
1200 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1201 Instruction LOADW, Instruction LOADX> {
1203 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1204 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1206 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1207 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1210 let AddedComplexity = 10 in {
1211 let Predicates = [IsLE] in {
1212 // We must do vector loads with LD1 in big-endian.
1213 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1214 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1215 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1216 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1219 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1220 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1222 // Match all load 128 bits width whose type is compatible with FPR128
1223 let Predicates = [IsLE] in {
1224 // We must do vector loads with LD1 in big-endian.
1225 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1226 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1227 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1228 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1229 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1230 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1232 } // AddedComplexity = 10
1235 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1236 Instruction INSTW, Instruction INSTX> {
1237 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1238 (SUBREG_TO_REG (i64 0),
1239 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1242 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1243 (SUBREG_TO_REG (i64 0),
1244 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1248 let AddedComplexity = 10 in {
1249 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1250 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1251 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1253 // zextloadi1 -> zextloadi8
1254 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1256 // extload -> zextload
1257 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1258 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1259 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1261 // extloadi1 -> zextloadi8
1262 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1267 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1268 Instruction INSTW, Instruction INSTX> {
1269 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1270 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1272 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1273 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1277 let AddedComplexity = 10 in {
1278 // extload -> zextload
1279 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1280 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1281 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1283 // zextloadi1 -> zextloadi8
1284 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1288 // (unsigned immediate)
1290 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1292 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1293 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1295 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1296 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1298 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1299 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1300 [(set (f16 FPR16:$Rt),
1301 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1302 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1303 [(set (f32 FPR32:$Rt),
1304 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1305 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1306 [(set (f64 FPR64:$Rt),
1307 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1308 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1309 [(set (f128 FPR128:$Rt),
1310 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1312 // For regular load, we do not have any alignment requirement.
1313 // Thus, it is safe to directly map the vector loads with interesting
1314 // addressing modes.
1315 // FIXME: We could do the same for bitconvert to floating point vectors.
1316 def : Pat <(v8i8 (scalar_to_vector (i32
1317 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1318 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1319 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1320 def : Pat <(v16i8 (scalar_to_vector (i32
1321 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1322 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1323 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1324 def : Pat <(v4i16 (scalar_to_vector (i32
1325 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1326 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1327 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1328 def : Pat <(v8i16 (scalar_to_vector (i32
1329 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1330 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1331 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1332 def : Pat <(v2i32 (scalar_to_vector (i32
1333 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1334 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1335 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1336 def : Pat <(v4i32 (scalar_to_vector (i32
1337 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1338 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1339 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1340 def : Pat <(v1i64 (scalar_to_vector (i64
1341 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1342 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1343 def : Pat <(v2i64 (scalar_to_vector (i64
1344 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1345 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1346 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1348 // Match all load 64 bits width whose type is compatible with FPR64
1349 let Predicates = [IsLE] in {
1350 // We must use LD1 to perform vector loads in big-endian.
1351 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1352 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1353 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1354 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1355 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1356 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1357 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1358 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1360 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1361 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1362 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1363 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1365 // Match all load 128 bits width whose type is compatible with FPR128
1366 let Predicates = [IsLE] in {
1367 // We must use LD1 to perform vector loads in big-endian.
1368 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1369 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1370 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1371 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1372 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1373 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1374 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1375 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1376 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1377 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1378 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1379 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1381 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1382 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1384 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1386 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1387 uimm12s2:$offset)))]>;
1388 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1390 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1391 uimm12s1:$offset)))]>;
1393 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1394 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1395 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1396 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1398 // zextloadi1 -> zextloadi8
1399 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1400 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1401 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1402 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1404 // extload -> zextload
1405 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1406 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1407 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1408 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1409 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1410 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1411 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1412 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1413 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1414 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1415 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1416 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1417 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1418 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1420 // load sign-extended half-word
1421 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1423 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1424 uimm12s2:$offset)))]>;
1425 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1427 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1428 uimm12s2:$offset)))]>;
1430 // load sign-extended byte
1431 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1433 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1434 uimm12s1:$offset)))]>;
1435 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1437 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1438 uimm12s1:$offset)))]>;
1440 // load sign-extended word
1441 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1443 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1444 uimm12s4:$offset)))]>;
1446 // load zero-extended word
1447 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1448 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1451 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1452 [(AArch64Prefetch imm:$Rt,
1453 (am_indexed64 GPR64sp:$Rn,
1454 uimm12s8:$offset))]>;
1456 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1460 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1461 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1462 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1463 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1464 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1466 // load sign-extended word
1467 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1470 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1471 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1474 // (unscaled immediate)
1475 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1477 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1478 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1480 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1481 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1483 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1484 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1486 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1487 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1488 [(set (f32 FPR32:$Rt),
1489 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1490 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1491 [(set (f64 FPR64:$Rt),
1492 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1493 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1494 [(set (f128 FPR128:$Rt),
1495 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1498 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1500 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1502 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1504 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1506 // Match all load 64 bits width whose type is compatible with FPR64
1507 let Predicates = [IsLE] in {
1508 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1509 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1510 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1511 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1512 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1513 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1514 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1515 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1517 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1518 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1519 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1520 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1522 // Match all load 128 bits width whose type is compatible with FPR128
1523 let Predicates = [IsLE] in {
1524 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1525 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1526 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1527 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1528 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1529 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1530 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1531 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1532 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1533 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1534 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1535 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1539 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1540 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1541 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1542 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1543 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1544 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1545 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1546 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1547 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1548 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1549 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1550 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1551 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1552 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1554 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1555 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1556 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1557 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1558 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1559 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1560 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1561 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1562 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1563 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1564 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1565 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1566 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1567 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1571 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1573 // Define new assembler match classes as we want to only match these when
1574 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1575 // associate a DiagnosticType either, as we want the diagnostic for the
1576 // canonical form (the scaled operand) to take precedence.
1577 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1578 let Name = "SImm9OffsetFB" # Width;
1579 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1580 let RenderMethod = "addImmOperands";
1583 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1584 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1585 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1586 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1587 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1589 def simm9_offset_fb8 : Operand<i64> {
1590 let ParserMatchClass = SImm9OffsetFB8Operand;
1592 def simm9_offset_fb16 : Operand<i64> {
1593 let ParserMatchClass = SImm9OffsetFB16Operand;
1595 def simm9_offset_fb32 : Operand<i64> {
1596 let ParserMatchClass = SImm9OffsetFB32Operand;
1598 def simm9_offset_fb64 : Operand<i64> {
1599 let ParserMatchClass = SImm9OffsetFB64Operand;
1601 def simm9_offset_fb128 : Operand<i64> {
1602 let ParserMatchClass = SImm9OffsetFB128Operand;
1605 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1606 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1607 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1608 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1609 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1610 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1611 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1612 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1613 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1614 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1615 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1616 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1617 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1618 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1621 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1622 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1623 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1624 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1626 // load sign-extended half-word
1628 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1630 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1632 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1634 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1636 // load sign-extended byte
1638 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1640 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1642 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1644 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1646 // load sign-extended word
1648 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1650 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1652 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1653 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1654 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1655 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1656 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1657 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1658 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1659 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1660 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1661 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1662 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1663 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1664 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1665 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1666 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1669 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1670 [(AArch64Prefetch imm:$Rt,
1671 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1674 // (unscaled immediate, unprivileged)
1675 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1676 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1678 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1679 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1681 // load sign-extended half-word
1682 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1683 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1685 // load sign-extended byte
1686 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1687 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1689 // load sign-extended word
1690 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1693 // (immediate pre-indexed)
1694 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1695 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1696 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1697 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1698 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1699 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1700 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1702 // load sign-extended half-word
1703 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1704 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1706 // load sign-extended byte
1707 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1708 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1710 // load zero-extended byte
1711 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1712 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1714 // load sign-extended word
1715 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1718 // (immediate post-indexed)
1719 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1720 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1721 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1722 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1723 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1724 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1725 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1727 // load sign-extended half-word
1728 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1729 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1731 // load sign-extended byte
1732 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1733 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1735 // load zero-extended byte
1736 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1737 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1739 // load sign-extended word
1740 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1742 //===----------------------------------------------------------------------===//
1743 // Store instructions.
1744 //===----------------------------------------------------------------------===//
1746 // Pair (indexed, offset)
1747 // FIXME: Use dedicated range-checked addressing mode operand here.
1748 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1749 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1750 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1751 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1752 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1754 // Pair (pre-indexed)
1755 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1756 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1757 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1758 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1759 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1761 // Pair (pre-indexed)
1762 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1763 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1764 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1765 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1766 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1768 // Pair (no allocate)
1769 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1770 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1771 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1772 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1773 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1776 // (Register offset)
1779 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1780 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1781 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1782 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1786 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1787 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1788 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1789 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1790 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1792 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1793 Instruction STRW, Instruction STRX> {
1795 def : Pat<(storeop GPR64:$Rt,
1796 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1797 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1798 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1800 def : Pat<(storeop GPR64:$Rt,
1801 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1802 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1803 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1806 let AddedComplexity = 10 in {
1808 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1809 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1810 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1813 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1814 Instruction STRW, Instruction STRX> {
1815 def : Pat<(store (VecTy FPR:$Rt),
1816 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1817 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1819 def : Pat<(store (VecTy FPR:$Rt),
1820 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1821 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1824 let AddedComplexity = 10 in {
1825 // Match all store 64 bits width whose type is compatible with FPR64
1826 let Predicates = [IsLE] in {
1827 // We must use ST1 to store vectors in big-endian.
1828 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1829 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1830 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1831 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1834 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1835 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1837 // Match all store 128 bits width whose type is compatible with FPR128
1838 let Predicates = [IsLE] in {
1839 // We must use ST1 to store vectors in big-endian.
1840 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1841 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1842 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1843 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1844 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1845 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1847 } // AddedComplexity = 10
1850 // (unsigned immediate)
1851 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1853 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1854 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1856 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1857 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1859 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
1860 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1861 [(store (f16 FPR16:$Rt),
1862 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
1863 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1864 [(store (f32 FPR32:$Rt),
1865 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1866 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1867 [(store (f64 FPR64:$Rt),
1868 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1869 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1871 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1872 [(truncstorei16 GPR32:$Rt,
1873 (am_indexed16 GPR64sp:$Rn,
1874 uimm12s2:$offset))]>;
1875 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
1876 [(truncstorei8 GPR32:$Rt,
1877 (am_indexed8 GPR64sp:$Rn,
1878 uimm12s1:$offset))]>;
1880 // Match all store 64 bits width whose type is compatible with FPR64
1881 let AddedComplexity = 10 in {
1882 let Predicates = [IsLE] in {
1883 // We must use ST1 to store vectors in big-endian.
1884 def : Pat<(store (v2f32 FPR64:$Rt),
1885 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1886 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1887 def : Pat<(store (v8i8 FPR64:$Rt),
1888 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1889 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1890 def : Pat<(store (v4i16 FPR64:$Rt),
1891 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1892 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1893 def : Pat<(store (v2i32 FPR64:$Rt),
1894 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1895 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1897 def : Pat<(store (v1f64 FPR64:$Rt),
1898 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1899 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1900 def : Pat<(store (v1i64 FPR64:$Rt),
1901 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1902 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1904 // Match all store 128 bits width whose type is compatible with FPR128
1905 let Predicates = [IsLE] in {
1906 // We must use ST1 to store vectors in big-endian.
1907 def : Pat<(store (v4f32 FPR128:$Rt),
1908 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1909 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1910 def : Pat<(store (v2f64 FPR128:$Rt),
1911 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1912 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1913 def : Pat<(store (v16i8 FPR128:$Rt),
1914 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1915 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1916 def : Pat<(store (v8i16 FPR128:$Rt),
1917 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1918 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1919 def : Pat<(store (v4i32 FPR128:$Rt),
1920 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1921 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1922 def : Pat<(store (v2i64 FPR128:$Rt),
1923 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1924 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1926 def : Pat<(store (f128 FPR128:$Rt),
1927 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1928 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1931 def : Pat<(truncstorei32 GPR64:$Rt,
1932 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
1933 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
1934 def : Pat<(truncstorei16 GPR64:$Rt,
1935 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
1936 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
1937 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
1938 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
1940 } // AddedComplexity = 10
1943 // (unscaled immediate)
1944 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
1946 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1947 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
1949 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1950 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
1952 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1953 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
1954 [(store (f16 FPR16:$Rt),
1955 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1956 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
1957 [(store (f32 FPR32:$Rt),
1958 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1959 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
1960 [(store (f64 FPR64:$Rt),
1961 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1962 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
1963 [(store (f128 FPR128:$Rt),
1964 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
1965 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
1966 [(truncstorei16 GPR32:$Rt,
1967 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1968 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
1969 [(truncstorei8 GPR32:$Rt,
1970 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1972 // Match all store 64 bits width whose type is compatible with FPR64
1973 let Predicates = [IsLE] in {
1974 // We must use ST1 to store vectors in big-endian.
1975 def : Pat<(store (v2f32 FPR64:$Rt),
1976 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1977 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1978 def : Pat<(store (v8i8 FPR64:$Rt),
1979 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1980 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1981 def : Pat<(store (v4i16 FPR64:$Rt),
1982 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1983 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1984 def : Pat<(store (v2i32 FPR64:$Rt),
1985 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1986 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1988 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1989 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1990 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1991 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1993 // Match all store 128 bits width whose type is compatible with FPR128
1994 let Predicates = [IsLE] in {
1995 // We must use ST1 to store vectors in big-endian.
1996 def : Pat<(store (v4f32 FPR128:$Rt),
1997 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1998 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1999 def : Pat<(store (v2f64 FPR128:$Rt),
2000 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2001 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2002 def : Pat<(store (v16i8 FPR128:$Rt),
2003 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2004 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2005 def : Pat<(store (v8i16 FPR128:$Rt),
2006 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2007 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2008 def : Pat<(store (v4i32 FPR128:$Rt),
2009 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2010 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2011 def : Pat<(store (v2i64 FPR128:$Rt),
2012 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2013 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2014 def : Pat<(store (v2f64 FPR128:$Rt),
2015 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2016 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2019 // unscaled i64 truncating stores
2020 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2021 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2022 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2023 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2024 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2025 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2028 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2029 def : InstAlias<"str $Rt, [$Rn, $offset]",
2030 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2031 def : InstAlias<"str $Rt, [$Rn, $offset]",
2032 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2033 def : InstAlias<"str $Rt, [$Rn, $offset]",
2034 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2035 def : InstAlias<"str $Rt, [$Rn, $offset]",
2036 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2037 def : InstAlias<"str $Rt, [$Rn, $offset]",
2038 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2039 def : InstAlias<"str $Rt, [$Rn, $offset]",
2040 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2041 def : InstAlias<"str $Rt, [$Rn, $offset]",
2042 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2044 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2045 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2046 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2047 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2050 // (unscaled immediate, unprivileged)
2051 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2052 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2054 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2055 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2058 // (immediate pre-indexed)
2059 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2060 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2061 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2062 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2063 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2064 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2065 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2067 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2068 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2071 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2072 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2074 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2075 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2077 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2078 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2081 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2082 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2083 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2084 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2085 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2086 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2087 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2088 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2089 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2090 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2091 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2092 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2094 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2095 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2096 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2097 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2098 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2099 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2100 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2101 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2102 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2103 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2104 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2105 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2108 // (immediate post-indexed)
2109 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2110 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2111 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2112 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2113 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2114 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2115 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2117 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2118 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2121 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2122 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2124 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2125 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2127 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2128 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2131 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2132 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2133 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2134 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2135 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2136 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2137 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2138 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2139 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2140 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2141 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2142 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2144 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2145 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2146 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2147 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2148 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2149 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2150 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2151 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2152 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2153 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2154 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2155 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2157 //===----------------------------------------------------------------------===//
2158 // Load/store exclusive instructions.
2159 //===----------------------------------------------------------------------===//
2161 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2162 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2163 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2164 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2166 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2167 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2168 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2169 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2171 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2172 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2173 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2174 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2176 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2177 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2178 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2179 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2181 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2182 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2183 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2184 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2186 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2187 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2188 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2189 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2191 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2192 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2194 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2195 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2197 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2198 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2200 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2201 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2203 //===----------------------------------------------------------------------===//
2204 // Scaled floating point to integer conversion instructions.
2205 //===----------------------------------------------------------------------===//
2207 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2208 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2209 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2210 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2211 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2212 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2213 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2214 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2215 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2216 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2217 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2218 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2219 let isCodeGenOnly = 1 in {
2220 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2221 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2222 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2223 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2226 //===----------------------------------------------------------------------===//
2227 // Scaled integer to floating point conversion instructions.
2228 //===----------------------------------------------------------------------===//
2230 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2231 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2233 //===----------------------------------------------------------------------===//
2234 // Unscaled integer to floating point conversion instruction.
2235 //===----------------------------------------------------------------------===//
2237 defm FMOV : UnscaledConversion<"fmov">;
2239 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
2240 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
2242 //===----------------------------------------------------------------------===//
2243 // Floating point conversion instruction.
2244 //===----------------------------------------------------------------------===//
2246 defm FCVT : FPConversion<"fcvt">;
2248 //===----------------------------------------------------------------------===//
2249 // Floating point single operand instructions.
2250 //===----------------------------------------------------------------------===//
2252 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2253 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2254 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2255 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2256 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2257 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2258 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2259 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2261 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2262 (FRINTNDr FPR64:$Rn)>;
2264 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2265 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2266 // <rdar://problem/13715968>
2267 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2268 let hasSideEffects = 1 in {
2269 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2272 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2274 let SchedRW = [WriteFDiv] in {
2275 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2278 //===----------------------------------------------------------------------===//
2279 // Floating point two operand instructions.
2280 //===----------------------------------------------------------------------===//
2282 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2283 let SchedRW = [WriteFDiv] in {
2284 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2286 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2287 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2288 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2289 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2290 let SchedRW = [WriteFMul] in {
2291 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2292 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2294 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2296 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2297 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2298 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2299 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2300 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2301 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2302 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2303 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2305 //===----------------------------------------------------------------------===//
2306 // Floating point three operand instructions.
2307 //===----------------------------------------------------------------------===//
2309 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2310 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2311 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2312 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2313 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2314 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2315 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2317 // The following def pats catch the case where the LHS of an FMA is negated.
2318 // The TriOpFrag above catches the case where the middle operand is negated.
2320 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2321 // the NEON variant.
2322 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2323 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2325 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2326 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2328 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2330 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2331 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2333 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2334 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2336 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2337 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2339 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2340 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2342 //===----------------------------------------------------------------------===//
2343 // Floating point comparison instructions.
2344 //===----------------------------------------------------------------------===//
2346 defm FCMPE : FPComparison<1, "fcmpe">;
2347 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2349 //===----------------------------------------------------------------------===//
2350 // Floating point conditional comparison instructions.
2351 //===----------------------------------------------------------------------===//
2353 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2354 defm FCCMP : FPCondComparison<0, "fccmp">;
2356 //===----------------------------------------------------------------------===//
2357 // Floating point conditional select instruction.
2358 //===----------------------------------------------------------------------===//
2360 defm FCSEL : FPCondSelect<"fcsel">;
2362 // CSEL instructions providing f128 types need to be handled by a
2363 // pseudo-instruction since the eventual code will need to introduce basic
2364 // blocks and control flow.
2365 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2366 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2367 [(set (f128 FPR128:$Rd),
2368 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2369 (i32 imm:$cond), NZCV))]> {
2371 let usesCustomInserter = 1;
2375 //===----------------------------------------------------------------------===//
2376 // Floating point immediate move.
2377 //===----------------------------------------------------------------------===//
2379 let isReMaterializable = 1 in {
2380 defm FMOV : FPMoveImmediate<"fmov">;
2383 //===----------------------------------------------------------------------===//
2384 // Advanced SIMD two vector instructions.
2385 //===----------------------------------------------------------------------===//
2387 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2388 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2389 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2390 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2391 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2392 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2393 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2394 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2395 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2396 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2398 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2399 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2400 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2401 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2402 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2403 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2404 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2405 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2406 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2407 (FCVTLv4i16 V64:$Rn)>;
2408 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2410 (FCVTLv8i16 V128:$Rn)>;
2411 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2412 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2414 (FCVTLv4i32 V128:$Rn)>;
2416 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2417 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2418 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2419 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2420 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2421 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2422 (FCVTNv4i16 V128:$Rn)>;
2423 def : Pat<(concat_vectors V64:$Rd,
2424 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2425 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2426 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2427 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2428 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2429 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2430 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2431 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2432 int_aarch64_neon_fcvtxn>;
2433 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2434 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2435 let isCodeGenOnly = 1 in {
2436 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2437 int_aarch64_neon_fcvtzs>;
2438 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2439 int_aarch64_neon_fcvtzu>;
2441 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2442 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2443 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2444 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2445 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2446 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2447 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2448 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2449 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2450 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2451 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2452 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2453 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2454 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2455 // Aliases for MVN -> NOT.
2456 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2457 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2458 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2459 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2461 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2462 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2463 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2464 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2465 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2466 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2467 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2469 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2470 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2471 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2472 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2473 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2474 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2475 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2476 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2478 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2479 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2480 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2481 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2482 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2484 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2485 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2486 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2487 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2488 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2489 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2490 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2491 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2492 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2493 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2494 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2495 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2496 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2497 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2498 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2499 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2500 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2501 int_aarch64_neon_uaddlp>;
2502 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2503 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2504 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2505 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2506 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2507 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2509 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2510 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2512 // Patterns for vector long shift (by element width). These need to match all
2513 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2515 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2516 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2517 (SHLLv8i8 V64:$Rn)>;
2518 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2519 (SHLLv16i8 V128:$Rn)>;
2520 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2521 (SHLLv4i16 V64:$Rn)>;
2522 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2523 (SHLLv8i16 V128:$Rn)>;
2524 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2525 (SHLLv2i32 V64:$Rn)>;
2526 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2527 (SHLLv4i32 V128:$Rn)>;
2530 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2531 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2532 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2534 //===----------------------------------------------------------------------===//
2535 // Advanced SIMD three vector instructions.
2536 //===----------------------------------------------------------------------===//
2538 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2539 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2540 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2541 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2542 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2543 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2544 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2545 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2546 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2547 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2548 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2549 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2550 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2551 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2552 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2553 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2554 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2555 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2556 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2557 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2558 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2559 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2560 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2561 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2562 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2564 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2565 // instruction expects the addend first, while the fma intrinsic puts it last.
2566 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2567 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2568 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2569 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2571 // The following def pats catch the case where the LHS of an FMA is negated.
2572 // The TriOpFrag above catches the case where the middle operand is negated.
2573 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2574 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2576 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2577 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2579 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2580 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2582 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2583 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2584 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2585 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2586 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2587 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2588 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2589 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2590 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2591 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2592 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2593 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2594 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2595 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2596 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2597 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2598 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2599 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2600 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2601 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2602 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2603 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2604 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2605 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2606 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2607 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2608 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2609 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2610 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2611 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2612 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2613 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2614 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2615 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2616 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2617 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2618 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2619 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2620 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2621 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2622 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2623 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2624 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2625 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2626 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2627 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2629 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2630 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2631 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2632 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2633 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2634 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2635 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2636 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2637 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2638 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2639 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2641 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2642 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2643 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2644 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2645 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2646 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2647 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2648 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2650 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2651 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2652 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2653 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2654 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2655 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2656 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2657 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2659 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2660 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2661 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2662 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2663 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2664 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2665 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2666 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2668 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2669 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2670 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2671 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2672 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2673 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2674 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2675 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2677 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2678 "|cmls.8b\t$dst, $src1, $src2}",
2679 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2680 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2681 "|cmls.16b\t$dst, $src1, $src2}",
2682 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2683 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2684 "|cmls.4h\t$dst, $src1, $src2}",
2685 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2686 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2687 "|cmls.8h\t$dst, $src1, $src2}",
2688 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2689 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2690 "|cmls.2s\t$dst, $src1, $src2}",
2691 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2692 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2693 "|cmls.4s\t$dst, $src1, $src2}",
2694 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2695 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2696 "|cmls.2d\t$dst, $src1, $src2}",
2697 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2699 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2700 "|cmlo.8b\t$dst, $src1, $src2}",
2701 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2702 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2703 "|cmlo.16b\t$dst, $src1, $src2}",
2704 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2705 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2706 "|cmlo.4h\t$dst, $src1, $src2}",
2707 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2708 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2709 "|cmlo.8h\t$dst, $src1, $src2}",
2710 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2711 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2712 "|cmlo.2s\t$dst, $src1, $src2}",
2713 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2714 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2715 "|cmlo.4s\t$dst, $src1, $src2}",
2716 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2717 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2718 "|cmlo.2d\t$dst, $src1, $src2}",
2719 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2721 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2722 "|cmle.8b\t$dst, $src1, $src2}",
2723 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2724 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2725 "|cmle.16b\t$dst, $src1, $src2}",
2726 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2727 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2728 "|cmle.4h\t$dst, $src1, $src2}",
2729 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2730 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2731 "|cmle.8h\t$dst, $src1, $src2}",
2732 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2733 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2734 "|cmle.2s\t$dst, $src1, $src2}",
2735 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2736 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2737 "|cmle.4s\t$dst, $src1, $src2}",
2738 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2739 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2740 "|cmle.2d\t$dst, $src1, $src2}",
2741 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2743 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2744 "|cmlt.8b\t$dst, $src1, $src2}",
2745 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2746 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2747 "|cmlt.16b\t$dst, $src1, $src2}",
2748 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2749 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2750 "|cmlt.4h\t$dst, $src1, $src2}",
2751 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2752 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2753 "|cmlt.8h\t$dst, $src1, $src2}",
2754 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2755 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2756 "|cmlt.2s\t$dst, $src1, $src2}",
2757 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2758 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2759 "|cmlt.4s\t$dst, $src1, $src2}",
2760 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2761 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2762 "|cmlt.2d\t$dst, $src1, $src2}",
2763 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2765 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2766 "|fcmle.2s\t$dst, $src1, $src2}",
2767 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2768 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2769 "|fcmle.4s\t$dst, $src1, $src2}",
2770 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2771 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2772 "|fcmle.2d\t$dst, $src1, $src2}",
2773 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2775 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2776 "|fcmlt.2s\t$dst, $src1, $src2}",
2777 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2778 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2779 "|fcmlt.4s\t$dst, $src1, $src2}",
2780 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2781 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2782 "|fcmlt.2d\t$dst, $src1, $src2}",
2783 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2785 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2786 "|facle.2s\t$dst, $src1, $src2}",
2787 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2788 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2789 "|facle.4s\t$dst, $src1, $src2}",
2790 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2791 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2792 "|facle.2d\t$dst, $src1, $src2}",
2793 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2795 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2796 "|faclt.2s\t$dst, $src1, $src2}",
2797 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2798 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2799 "|faclt.4s\t$dst, $src1, $src2}",
2800 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2801 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2802 "|faclt.2d\t$dst, $src1, $src2}",
2803 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2805 //===----------------------------------------------------------------------===//
2806 // Advanced SIMD three scalar instructions.
2807 //===----------------------------------------------------------------------===//
2809 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2810 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
2811 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
2812 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
2813 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
2814 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
2815 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
2816 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
2817 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2818 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2819 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2820 int_aarch64_neon_facge>;
2821 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2822 int_aarch64_neon_facgt>;
2823 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2824 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2825 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2826 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
2827 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
2828 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
2829 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
2830 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
2831 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
2832 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
2833 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
2834 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
2835 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
2836 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
2837 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2838 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
2839 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
2840 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
2841 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
2842 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
2843 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
2845 def : InstAlias<"cmls $dst, $src1, $src2",
2846 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2847 def : InstAlias<"cmle $dst, $src1, $src2",
2848 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2849 def : InstAlias<"cmlo $dst, $src1, $src2",
2850 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2851 def : InstAlias<"cmlt $dst, $src1, $src2",
2852 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2853 def : InstAlias<"fcmle $dst, $src1, $src2",
2854 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2855 def : InstAlias<"fcmle $dst, $src1, $src2",
2856 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2857 def : InstAlias<"fcmlt $dst, $src1, $src2",
2858 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2859 def : InstAlias<"fcmlt $dst, $src1, $src2",
2860 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2861 def : InstAlias<"facle $dst, $src1, $src2",
2862 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2863 def : InstAlias<"facle $dst, $src1, $src2",
2864 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2865 def : InstAlias<"faclt $dst, $src1, $src2",
2866 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2867 def : InstAlias<"faclt $dst, $src1, $src2",
2868 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2870 //===----------------------------------------------------------------------===//
2871 // Advanced SIMD three scalar instructions (mixed operands).
2872 //===----------------------------------------------------------------------===//
2873 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2874 int_aarch64_neon_sqdmulls_scalar>;
2875 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2876 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2878 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
2879 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2880 (i32 FPR32:$Rm))))),
2881 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2882 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
2883 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2884 (i32 FPR32:$Rm))))),
2885 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2887 //===----------------------------------------------------------------------===//
2888 // Advanced SIMD two scalar instructions.
2889 //===----------------------------------------------------------------------===//
2891 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
2892 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
2893 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
2894 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
2895 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
2896 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
2897 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2898 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2899 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2900 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2901 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2902 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2903 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2904 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2905 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2906 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2907 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2908 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2909 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2910 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2911 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2912 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2913 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2914 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2915 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2916 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2917 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2918 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
2919 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2920 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2921 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
2922 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
2923 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2924 int_aarch64_neon_suqadd>;
2925 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
2926 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
2927 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2928 int_aarch64_neon_usqadd>;
2930 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
2932 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
2933 (FCVTASv1i64 FPR64:$Rn)>;
2934 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
2935 (FCVTAUv1i64 FPR64:$Rn)>;
2936 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
2937 (FCVTMSv1i64 FPR64:$Rn)>;
2938 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2939 (FCVTMUv1i64 FPR64:$Rn)>;
2940 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
2941 (FCVTNSv1i64 FPR64:$Rn)>;
2942 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2943 (FCVTNUv1i64 FPR64:$Rn)>;
2944 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
2945 (FCVTPSv1i64 FPR64:$Rn)>;
2946 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2947 (FCVTPUv1i64 FPR64:$Rn)>;
2949 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
2950 (FRECPEv1i32 FPR32:$Rn)>;
2951 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
2952 (FRECPEv1i64 FPR64:$Rn)>;
2953 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
2954 (FRECPEv1i64 FPR64:$Rn)>;
2956 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
2957 (FRECPXv1i32 FPR32:$Rn)>;
2958 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
2959 (FRECPXv1i64 FPR64:$Rn)>;
2961 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
2962 (FRSQRTEv1i32 FPR32:$Rn)>;
2963 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
2964 (FRSQRTEv1i64 FPR64:$Rn)>;
2965 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
2966 (FRSQRTEv1i64 FPR64:$Rn)>;
2968 // If an integer is about to be converted to a floating point value,
2969 // just load it on the floating point unit.
2970 // Here are the patterns for 8 and 16-bits to float.
2972 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
2973 SDPatternOperator loadop, Instruction UCVTF,
2974 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
2976 def : Pat<(DstTy (uint_to_fp (SrcTy
2977 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
2978 ro.Wext:$extend))))),
2979 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
2980 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
2983 def : Pat<(DstTy (uint_to_fp (SrcTy
2984 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
2985 ro.Wext:$extend))))),
2986 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
2987 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
2991 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
2992 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
2993 def : Pat <(f32 (uint_to_fp (i32
2994 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
2995 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2996 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
2997 def : Pat <(f32 (uint_to_fp (i32
2998 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
2999 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3000 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3001 // 16-bits -> float.
3002 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3003 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3004 def : Pat <(f32 (uint_to_fp (i32
3005 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3006 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3007 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3008 def : Pat <(f32 (uint_to_fp (i32
3009 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3010 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3011 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3012 // 32-bits are handled in target specific dag combine:
3013 // performIntToFpCombine.
3014 // 64-bits integer to 32-bits floating point, not possible with
3015 // UCVTF on floating point registers (both source and destination
3016 // must have the same size).
3018 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3019 // 8-bits -> double.
3020 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3021 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3022 def : Pat <(f64 (uint_to_fp (i32
3023 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3024 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3025 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3026 def : Pat <(f64 (uint_to_fp (i32
3027 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3028 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3029 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3030 // 16-bits -> double.
3031 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3032 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3033 def : Pat <(f64 (uint_to_fp (i32
3034 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3035 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3036 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3037 def : Pat <(f64 (uint_to_fp (i32
3038 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3039 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3040 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3041 // 32-bits -> double.
3042 defm : UIntToFPROLoadPat<f64, i32, load,
3043 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3044 def : Pat <(f64 (uint_to_fp (i32
3045 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3046 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3047 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3048 def : Pat <(f64 (uint_to_fp (i32
3049 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3050 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3051 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3052 // 64-bits -> double are handled in target specific dag combine:
3053 // performIntToFpCombine.
3055 //===----------------------------------------------------------------------===//
3056 // Advanced SIMD three different-sized vector instructions.
3057 //===----------------------------------------------------------------------===//
3059 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3060 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3061 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3062 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3063 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3064 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3065 int_aarch64_neon_sabd>;
3066 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3067 int_aarch64_neon_sabd>;
3068 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3069 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3070 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3071 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3072 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3073 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3074 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3075 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3076 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3077 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3078 int_aarch64_neon_sqadd>;
3079 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3080 int_aarch64_neon_sqsub>;
3081 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3082 int_aarch64_neon_sqdmull>;
3083 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3084 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3085 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3086 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3087 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3088 int_aarch64_neon_uabd>;
3089 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3090 int_aarch64_neon_uabd>;
3091 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3092 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3093 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3094 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3095 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3096 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3097 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3098 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3099 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3100 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3101 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3102 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3103 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3105 // Patterns for 64-bit pmull
3106 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3107 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3108 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3109 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3110 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3112 // CodeGen patterns for addhn and subhn instructions, which can actually be
3113 // written in LLVM IR without too much difficulty.
3116 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3117 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3118 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3120 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3121 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3123 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3124 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3125 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3127 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3128 V128:$Rn, V128:$Rm)>;
3129 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3130 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3132 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3133 V128:$Rn, V128:$Rm)>;
3134 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3135 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3137 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3138 V128:$Rn, V128:$Rm)>;
3141 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3142 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3143 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3145 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3146 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3148 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3149 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3150 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3152 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3153 V128:$Rn, V128:$Rm)>;
3154 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3155 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3157 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3158 V128:$Rn, V128:$Rm)>;
3159 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3160 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3162 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3163 V128:$Rn, V128:$Rm)>;
3165 //----------------------------------------------------------------------------
3166 // AdvSIMD bitwise extract from vector instruction.
3167 //----------------------------------------------------------------------------
3169 defm EXT : SIMDBitwiseExtract<"ext">;
3171 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3172 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3173 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3174 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3175 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3176 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3177 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3178 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3179 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3180 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3181 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3182 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3183 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3184 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3185 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3186 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3188 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3190 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3191 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3192 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3193 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3194 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3195 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3196 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3197 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3198 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3199 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3200 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3201 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3204 //----------------------------------------------------------------------------
3205 // AdvSIMD zip vector
3206 //----------------------------------------------------------------------------
3208 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3209 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3210 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3211 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3212 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3213 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3215 //----------------------------------------------------------------------------
3216 // AdvSIMD TBL/TBX instructions
3217 //----------------------------------------------------------------------------
3219 defm TBL : SIMDTableLookup< 0, "tbl">;
3220 defm TBX : SIMDTableLookupTied<1, "tbx">;
3222 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3223 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3224 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3225 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3227 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3228 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3229 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3230 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3231 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3232 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3235 //----------------------------------------------------------------------------
3236 // AdvSIMD scalar CPY instruction
3237 //----------------------------------------------------------------------------
3239 defm CPY : SIMDScalarCPY<"cpy">;
3241 //----------------------------------------------------------------------------
3242 // AdvSIMD scalar pairwise instructions
3243 //----------------------------------------------------------------------------
3245 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3246 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3247 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3248 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3249 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3250 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3251 def : Pat<(i64 (int_aarch64_neon_saddv (v2i64 V128:$Rn))),
3252 (ADDPv2i64p V128:$Rn)>;
3253 def : Pat<(i64 (int_aarch64_neon_uaddv (v2i64 V128:$Rn))),
3254 (ADDPv2i64p V128:$Rn)>;
3255 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3256 (FADDPv2i32p V64:$Rn)>;
3257 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3258 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3259 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3260 (FADDPv2i64p V128:$Rn)>;
3261 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3262 (FMAXNMPv2i32p V64:$Rn)>;
3263 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3264 (FMAXNMPv2i64p V128:$Rn)>;
3265 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3266 (FMAXPv2i32p V64:$Rn)>;
3267 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3268 (FMAXPv2i64p V128:$Rn)>;
3269 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3270 (FMINNMPv2i32p V64:$Rn)>;
3271 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3272 (FMINNMPv2i64p V128:$Rn)>;
3273 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3274 (FMINPv2i32p V64:$Rn)>;
3275 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3276 (FMINPv2i64p V128:$Rn)>;
3278 //----------------------------------------------------------------------------
3279 // AdvSIMD INS/DUP instructions
3280 //----------------------------------------------------------------------------
3282 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3283 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3284 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3285 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3286 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3287 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3288 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3290 def DUPv2i64lane : SIMDDup64FromElement;
3291 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3292 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3293 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3294 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3295 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3296 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3298 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3299 (v2f32 (DUPv2i32lane
3300 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3302 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3303 (v4f32 (DUPv4i32lane
3304 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3306 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3307 (v2f64 (DUPv2i64lane
3308 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3311 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3312 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3313 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3314 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3315 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3316 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3318 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3319 // instruction even if the types don't match: we just have to remap the lane
3320 // carefully. N.b. this trick only applies to truncations.
3321 def VecIndex_x2 : SDNodeXForm<imm, [{
3322 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3324 def VecIndex_x4 : SDNodeXForm<imm, [{
3325 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3327 def VecIndex_x8 : SDNodeXForm<imm, [{
3328 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3331 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3332 ValueType Src128VT, ValueType ScalVT,
3333 Instruction DUP, SDNodeXForm IdxXFORM> {
3334 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3336 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3338 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3340 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3343 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3344 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3345 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3347 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3348 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3349 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3351 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3352 SDNodeXForm IdxXFORM> {
3353 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3355 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3357 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3359 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3362 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3363 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3364 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3366 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3367 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3368 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3370 // SMOV and UMOV definitions, with some extra patterns for convenience
3374 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3375 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3376 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3377 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3378 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3379 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3380 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3381 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3382 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3383 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3384 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3385 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3387 // Extracting i8 or i16 elements will have the zero-extend transformed to
3388 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3389 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3390 // bits of the destination register.
3391 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3393 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3394 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3396 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3400 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3401 (SUBREG_TO_REG (i32 0),
3402 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3403 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3404 (SUBREG_TO_REG (i32 0),
3405 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3407 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3408 (SUBREG_TO_REG (i32 0),
3409 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3410 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3411 (SUBREG_TO_REG (i32 0),
3412 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3414 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3415 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3416 (i32 FPR32:$Rn), ssub))>;
3417 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3418 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3419 (i32 FPR32:$Rn), ssub))>;
3420 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3421 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3422 (i64 FPR64:$Rn), dsub))>;
3424 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3425 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3426 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3427 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3428 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3429 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3431 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3432 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3435 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3437 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3440 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3441 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3443 V128:$Rn, VectorIndexS:$imm,
3444 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3446 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3447 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3449 V128:$Rn, VectorIndexD:$imm,
3450 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3453 // Copy an element at a constant index in one vector into a constant indexed
3454 // element of another.
3455 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3456 // index type and INS extension
3457 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3458 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3459 VectorIndexB:$idx2)),
3461 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3463 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3464 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3465 VectorIndexH:$idx2)),
3467 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3469 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3470 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3471 VectorIndexS:$idx2)),
3473 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3475 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3476 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3477 VectorIndexD:$idx2)),
3479 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3482 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3483 ValueType VTScal, Instruction INS> {
3484 def : Pat<(VT128 (vector_insert V128:$src,
3485 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3487 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3489 def : Pat<(VT128 (vector_insert V128:$src,
3490 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3492 (INS V128:$src, imm:$Immd,
3493 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3495 def : Pat<(VT64 (vector_insert V64:$src,
3496 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3498 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3499 imm:$Immd, V128:$Rn, imm:$Immn),
3502 def : Pat<(VT64 (vector_insert V64:$src,
3503 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3506 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3507 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3511 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3512 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3513 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3514 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3515 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3516 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3519 // Floating point vector extractions are codegen'd as either a sequence of
3520 // subregister extractions, possibly fed by an INS if the lane number is
3521 // anything other than zero.
3522 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3523 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3524 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3525 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3526 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3527 (f64 (EXTRACT_SUBREG
3528 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3529 V128:$Rn, VectorIndexD:$idx),
3531 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3532 (f32 (EXTRACT_SUBREG
3533 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3534 V128:$Rn, VectorIndexS:$idx),
3537 // All concat_vectors operations are canonicalised to act on i64 vectors for
3538 // AArch64. In the general case we need an instruction, which had just as well be
3540 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3541 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3542 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3543 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3545 def : ConcatPat<v2i64, v1i64>;
3546 def : ConcatPat<v2f64, v1f64>;
3547 def : ConcatPat<v4i32, v2i32>;
3548 def : ConcatPat<v4f32, v2f32>;
3549 def : ConcatPat<v8i16, v4i16>;
3550 def : ConcatPat<v16i8, v8i8>;
3552 // If the high lanes are undef, though, we can just ignore them:
3553 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3554 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3555 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3557 def : ConcatUndefPat<v2i64, v1i64>;
3558 def : ConcatUndefPat<v2f64, v1f64>;
3559 def : ConcatUndefPat<v4i32, v2i32>;
3560 def : ConcatUndefPat<v4f32, v2f32>;
3561 def : ConcatUndefPat<v8i16, v4i16>;
3562 def : ConcatUndefPat<v16i8, v8i8>;
3564 //----------------------------------------------------------------------------
3565 // AdvSIMD across lanes instructions
3566 //----------------------------------------------------------------------------
3568 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3569 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3570 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3571 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3572 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3573 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3574 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3575 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3576 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3577 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3578 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3580 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3581 // If there is a sign extension after this intrinsic, consume it as smov already
3583 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3585 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3586 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3588 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3590 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3591 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3593 // If there is a sign extension after this intrinsic, consume it as smov already
3595 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3597 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3598 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3600 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3602 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3603 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3605 // If there is a sign extension after this intrinsic, consume it as smov already
3607 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3609 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3610 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3612 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3614 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3615 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3617 // If there is a sign extension after this intrinsic, consume it as smov already
3619 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3621 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3622 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3624 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3626 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3627 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3630 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3631 (i32 (EXTRACT_SUBREG
3632 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3633 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3637 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3638 // If there is a masking operation keeping only what has been actually
3639 // generated, consume it.
3640 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3641 (i32 (EXTRACT_SUBREG
3642 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3643 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3645 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3646 (i32 (EXTRACT_SUBREG
3647 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3648 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3650 // If there is a masking operation keeping only what has been actually
3651 // generated, consume it.
3652 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3653 (i32 (EXTRACT_SUBREG
3654 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3655 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3657 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3658 (i32 (EXTRACT_SUBREG
3659 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3660 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3663 // If there is a masking operation keeping only what has been actually
3664 // generated, consume it.
3665 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3666 (i32 (EXTRACT_SUBREG
3667 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3668 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3670 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3671 (i32 (EXTRACT_SUBREG
3672 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3673 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3675 // If there is a masking operation keeping only what has been actually
3676 // generated, consume it.
3677 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3678 (i32 (EXTRACT_SUBREG
3679 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3680 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3682 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3683 (i32 (EXTRACT_SUBREG
3684 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3685 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3688 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3689 (i32 (EXTRACT_SUBREG
3690 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3691 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3696 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3697 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3699 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3700 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3702 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3704 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3705 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3708 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3709 (i32 (EXTRACT_SUBREG
3710 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3711 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3713 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3714 (i32 (EXTRACT_SUBREG
3715 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3716 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3719 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3720 (i64 (EXTRACT_SUBREG
3721 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3722 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3726 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3728 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3729 (i32 (EXTRACT_SUBREG
3730 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3731 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3733 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3734 (i32 (EXTRACT_SUBREG
3735 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3736 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3739 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3740 (i32 (EXTRACT_SUBREG
3741 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3742 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3744 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3745 (i32 (EXTRACT_SUBREG
3746 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3747 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3750 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3751 (i64 (EXTRACT_SUBREG
3752 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3753 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3757 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_aarch64_neon_saddv>;
3758 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3759 def : Pat<(i32 (int_aarch64_neon_saddv (v2i32 V64:$Rn))),
3760 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3762 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_aarch64_neon_uaddv>;
3763 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3764 def : Pat<(i32 (int_aarch64_neon_uaddv (v2i32 V64:$Rn))),
3765 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3767 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_aarch64_neon_smaxv>;
3768 def : Pat<(i32 (int_aarch64_neon_smaxv (v2i32 V64:$Rn))),
3769 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3771 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_aarch64_neon_sminv>;
3772 def : Pat<(i32 (int_aarch64_neon_sminv (v2i32 V64:$Rn))),
3773 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3775 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_aarch64_neon_umaxv>;
3776 def : Pat<(i32 (int_aarch64_neon_umaxv (v2i32 V64:$Rn))),
3777 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3779 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_aarch64_neon_uminv>;
3780 def : Pat<(i32 (int_aarch64_neon_uminv (v2i32 V64:$Rn))),
3781 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3783 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
3784 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
3786 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3787 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
3788 (i64 (EXTRACT_SUBREG
3789 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3790 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3792 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3793 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
3794 (i64 (EXTRACT_SUBREG
3795 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3796 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3799 //------------------------------------------------------------------------------
3800 // AdvSIMD modified immediate instructions
3801 //------------------------------------------------------------------------------
3804 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
3806 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
3808 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3809 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3810 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3811 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3813 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3814 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3815 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3816 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3818 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3819 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3820 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3821 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3823 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3824 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3825 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3826 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3829 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3831 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3832 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3834 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3835 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3837 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3841 // EDIT byte mask: scalar
3842 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3843 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3844 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3845 // The movi_edit node has the immediate value already encoded, so we use
3846 // a plain imm0_255 here.
3847 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
3848 (MOVID imm0_255:$shift)>;
3850 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3851 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3852 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3853 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3855 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3856 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3857 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3858 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3860 // EDIT byte mask: 2d
3862 // The movi_edit node has the immediate value already encoded, so we use
3863 // a plain imm0_255 in the pattern
3864 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3865 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3868 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
3871 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3872 // Complexity is added to break a tie with a plain MOVI.
3873 let AddedComplexity = 1 in {
3874 def : Pat<(f32 fpimm0),
3875 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3877 def : Pat<(f64 fpimm0),
3878 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3882 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3883 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3884 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3885 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3887 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3888 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3889 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3890 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3892 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
3893 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
3895 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3896 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3898 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3899 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3900 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3901 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3903 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3904 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3905 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3906 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3908 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3909 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3910 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3911 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3912 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3913 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3914 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3915 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
3917 // EDIT per word: 2s & 4s with MSL shifter
3918 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
3919 [(set (v2i32 V64:$Rd),
3920 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3921 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
3922 [(set (v4i32 V128:$Rd),
3923 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3925 // Per byte: 8b & 16b
3926 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
3928 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
3929 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
3931 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
3935 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3936 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
3938 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3939 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3940 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3941 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3943 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3944 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3945 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3946 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3948 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3949 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
3950 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3951 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
3952 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3953 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
3954 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3955 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
3957 // EDIT per word: 2s & 4s with MSL shifter
3958 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
3959 [(set (v2i32 V64:$Rd),
3960 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3961 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
3962 [(set (v4i32 V128:$Rd),
3963 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3965 //----------------------------------------------------------------------------
3966 // AdvSIMD indexed element
3967 //----------------------------------------------------------------------------
3969 let neverHasSideEffects = 1 in {
3970 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
3971 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
3974 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
3975 // instruction expects the addend first, while the intrinsic expects it last.
3977 // On the other hand, there are quite a few valid combinatorial options due to
3978 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
3979 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3980 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
3981 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3982 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
3984 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3985 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3986 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3987 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
3988 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3989 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
3990 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3991 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
3993 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
3994 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3996 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3997 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
3998 VectorIndexS:$idx))),
3999 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4000 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4001 (v2f32 (AArch64duplane32
4002 (v4f32 (insert_subvector undef,
4003 (v2f32 (fneg V64:$Rm)),
4005 VectorIndexS:$idx)))),
4006 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4007 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4008 VectorIndexS:$idx)>;
4009 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4010 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4011 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4012 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4014 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4016 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4017 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4018 VectorIndexS:$idx))),
4019 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4020 VectorIndexS:$idx)>;
4021 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4022 (v4f32 (AArch64duplane32
4023 (v4f32 (insert_subvector undef,
4024 (v2f32 (fneg V64:$Rm)),
4026 VectorIndexS:$idx)))),
4027 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4028 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4029 VectorIndexS:$idx)>;
4030 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4031 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4032 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4033 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4035 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4036 // (DUPLANE from 64-bit would be trivial).
4037 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4038 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4039 VectorIndexD:$idx))),
4041 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4042 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4043 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4044 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4045 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4047 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4048 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4049 (vector_extract (v4f32 (fneg V128:$Rm)),
4050 VectorIndexS:$idx))),
4051 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4052 V128:$Rm, VectorIndexS:$idx)>;
4053 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4054 (vector_extract (v2f32 (fneg V64:$Rm)),
4055 VectorIndexS:$idx))),
4056 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4057 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4059 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4060 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4061 (vector_extract (v2f64 (fneg V128:$Rm)),
4062 VectorIndexS:$idx))),
4063 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4064 V128:$Rm, VectorIndexS:$idx)>;
4067 defm : FMLSIndexedAfterNegPatterns<
4068 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4069 defm : FMLSIndexedAfterNegPatterns<
4070 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4072 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4073 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4075 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4076 (FMULv2i32_indexed V64:$Rn,
4077 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4079 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4080 (FMULv4i32_indexed V128:$Rn,
4081 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4083 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4084 (FMULv2i64_indexed V128:$Rn,
4085 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4088 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4089 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4090 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4091 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4092 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4093 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4094 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4095 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4096 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4097 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4098 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4099 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4100 int_aarch64_neon_smull>;
4101 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4102 int_aarch64_neon_sqadd>;
4103 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4104 int_aarch64_neon_sqsub>;
4105 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4106 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4107 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4108 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4109 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4110 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4111 int_aarch64_neon_umull>;
4113 // A scalar sqdmull with the second operand being a vector lane can be
4114 // handled directly with the indexed instruction encoding.
4115 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4116 (vector_extract (v4i32 V128:$Vm),
4117 VectorIndexS:$idx)),
4118 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4120 //----------------------------------------------------------------------------
4121 // AdvSIMD scalar shift instructions
4122 //----------------------------------------------------------------------------
4123 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4124 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4125 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4126 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4127 // Codegen patterns for the above. We don't put these directly on the
4128 // instructions because TableGen's type inference can't handle the truth.
4129 // Having the same base pattern for fp <--> int totally freaks it out.
4130 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4131 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4132 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4133 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4134 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4135 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4136 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4137 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4138 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4140 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4141 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4143 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4144 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4145 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4146 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4147 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4148 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4149 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4150 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4151 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4152 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4154 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4155 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4157 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4159 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4160 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4161 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4162 int_aarch64_neon_sqrshrn>;
4163 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4164 int_aarch64_neon_sqrshrun>;
4165 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4166 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4167 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4168 int_aarch64_neon_sqshrn>;
4169 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4170 int_aarch64_neon_sqshrun>;
4171 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4172 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4173 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4174 TriOpFrag<(add node:$LHS,
4175 (AArch64srshri node:$MHS, node:$RHS))>>;
4176 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4177 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4178 TriOpFrag<(add node:$LHS,
4179 (AArch64vashr node:$MHS, node:$RHS))>>;
4180 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4181 int_aarch64_neon_uqrshrn>;
4182 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4183 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4184 int_aarch64_neon_uqshrn>;
4185 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4186 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4187 TriOpFrag<(add node:$LHS,
4188 (AArch64urshri node:$MHS, node:$RHS))>>;
4189 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4190 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4191 TriOpFrag<(add node:$LHS,
4192 (AArch64vlshr node:$MHS, node:$RHS))>>;
4194 //----------------------------------------------------------------------------
4195 // AdvSIMD vector shift instructions
4196 //----------------------------------------------------------------------------
4197 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4198 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4199 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4200 int_aarch64_neon_vcvtfxs2fp>;
4201 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4202 int_aarch64_neon_rshrn>;
4203 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4204 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4205 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4206 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4207 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4208 (i32 vecshiftL64:$imm))),
4209 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4210 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4211 int_aarch64_neon_sqrshrn>;
4212 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4213 int_aarch64_neon_sqrshrun>;
4214 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4215 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4216 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4217 int_aarch64_neon_sqshrn>;
4218 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4219 int_aarch64_neon_sqshrun>;
4220 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4221 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4222 (i32 vecshiftR64:$imm))),
4223 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4224 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4225 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4226 TriOpFrag<(add node:$LHS,
4227 (AArch64srshri node:$MHS, node:$RHS))> >;
4228 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4229 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4231 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4232 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4233 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4234 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4235 int_aarch64_neon_vcvtfxu2fp>;
4236 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4237 int_aarch64_neon_uqrshrn>;
4238 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4239 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4240 int_aarch64_neon_uqshrn>;
4241 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4242 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4243 TriOpFrag<(add node:$LHS,
4244 (AArch64urshri node:$MHS, node:$RHS))> >;
4245 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4246 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4247 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4248 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4249 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4251 // SHRN patterns for when a logical right shift was used instead of arithmetic
4252 // (the immediate guarantees no sign bits actually end up in the result so it
4254 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4255 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4256 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4257 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4258 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4259 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4261 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4262 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4263 vecshiftR16Narrow:$imm)))),
4264 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4265 V128:$Rn, vecshiftR16Narrow:$imm)>;
4266 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4267 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4268 vecshiftR32Narrow:$imm)))),
4269 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4270 V128:$Rn, vecshiftR32Narrow:$imm)>;
4271 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4272 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4273 vecshiftR64Narrow:$imm)))),
4274 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4275 V128:$Rn, vecshiftR32Narrow:$imm)>;
4277 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4278 // Anyexts are implemented as zexts.
4279 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4280 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4281 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4282 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4283 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4284 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4285 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4286 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4287 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4288 // Also match an extend from the upper half of a 128 bit source register.
4289 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4290 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4291 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4292 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4293 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4294 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4295 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4296 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4297 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4298 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4299 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4300 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4301 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4302 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4303 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4304 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4305 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4306 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4308 // Vector shift sxtl aliases
4309 def : InstAlias<"sxtl.8h $dst, $src1",
4310 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4311 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4312 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4313 def : InstAlias<"sxtl.4s $dst, $src1",
4314 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4315 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4316 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4317 def : InstAlias<"sxtl.2d $dst, $src1",
4318 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4319 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4320 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4322 // Vector shift sxtl2 aliases
4323 def : InstAlias<"sxtl2.8h $dst, $src1",
4324 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4325 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4326 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4327 def : InstAlias<"sxtl2.4s $dst, $src1",
4328 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4329 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4330 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4331 def : InstAlias<"sxtl2.2d $dst, $src1",
4332 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4333 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4334 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4336 // Vector shift uxtl aliases
4337 def : InstAlias<"uxtl.8h $dst, $src1",
4338 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4339 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4340 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4341 def : InstAlias<"uxtl.4s $dst, $src1",
4342 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4343 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4344 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4345 def : InstAlias<"uxtl.2d $dst, $src1",
4346 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4347 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4348 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4350 // Vector shift uxtl2 aliases
4351 def : InstAlias<"uxtl2.8h $dst, $src1",
4352 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4353 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4354 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4355 def : InstAlias<"uxtl2.4s $dst, $src1",
4356 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4357 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4358 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4359 def : InstAlias<"uxtl2.2d $dst, $src1",
4360 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4361 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4362 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4364 // If an integer is about to be converted to a floating point value,
4365 // just load it on the floating point unit.
4366 // These patterns are more complex because floating point loads do not
4367 // support sign extension.
4368 // The sign extension has to be explicitly added and is only supported for
4369 // one step: byte-to-half, half-to-word, word-to-doubleword.
4370 // SCVTF GPR -> FPR is 9 cycles.
4371 // SCVTF FPR -> FPR is 4 cyclces.
4372 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4373 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4374 // and still being faster.
4375 // However, this is not good for code size.
4376 // 8-bits -> float. 2 sizes step-up.
4377 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4378 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4379 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4384 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4390 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4392 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4393 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4394 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4395 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4396 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4397 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4398 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4399 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4401 // 16-bits -> float. 1 size step-up.
4402 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4403 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4404 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4406 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4410 ssub)))>, Requires<[NotForCodeSize]>;
4412 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4413 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4414 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4415 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4416 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4417 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4418 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4419 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4421 // 32-bits to 32-bits are handled in target specific dag combine:
4422 // performIntToFpCombine.
4423 // 64-bits integer to 32-bits floating point, not possible with
4424 // SCVTF on floating point registers (both source and destination
4425 // must have the same size).
4427 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4428 // 8-bits -> double. 3 size step-up: give up.
4429 // 16-bits -> double. 2 size step.
4430 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4431 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4432 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4437 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4443 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4445 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4446 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4447 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4448 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4449 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4450 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4451 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4452 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4453 // 32-bits -> double. 1 size step-up.
4454 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4455 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4456 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4458 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4462 dsub)))>, Requires<[NotForCodeSize]>;
4464 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4465 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4466 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4467 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4468 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4469 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4470 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4471 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4473 // 64-bits -> double are handled in target specific dag combine:
4474 // performIntToFpCombine.
4477 //----------------------------------------------------------------------------
4478 // AdvSIMD Load-Store Structure
4479 //----------------------------------------------------------------------------
4480 defm LD1 : SIMDLd1Multiple<"ld1">;
4481 defm LD2 : SIMDLd2Multiple<"ld2">;
4482 defm LD3 : SIMDLd3Multiple<"ld3">;
4483 defm LD4 : SIMDLd4Multiple<"ld4">;
4485 defm ST1 : SIMDSt1Multiple<"st1">;
4486 defm ST2 : SIMDSt2Multiple<"st2">;
4487 defm ST3 : SIMDSt3Multiple<"st3">;
4488 defm ST4 : SIMDSt4Multiple<"st4">;
4490 class Ld1Pat<ValueType ty, Instruction INST>
4491 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4493 def : Ld1Pat<v16i8, LD1Onev16b>;
4494 def : Ld1Pat<v8i16, LD1Onev8h>;
4495 def : Ld1Pat<v4i32, LD1Onev4s>;
4496 def : Ld1Pat<v2i64, LD1Onev2d>;
4497 def : Ld1Pat<v8i8, LD1Onev8b>;
4498 def : Ld1Pat<v4i16, LD1Onev4h>;
4499 def : Ld1Pat<v2i32, LD1Onev2s>;
4500 def : Ld1Pat<v1i64, LD1Onev1d>;
4502 class St1Pat<ValueType ty, Instruction INST>
4503 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4504 (INST ty:$Vt, GPR64sp:$Rn)>;
4506 def : St1Pat<v16i8, ST1Onev16b>;
4507 def : St1Pat<v8i16, ST1Onev8h>;
4508 def : St1Pat<v4i32, ST1Onev4s>;
4509 def : St1Pat<v2i64, ST1Onev2d>;
4510 def : St1Pat<v8i8, ST1Onev8b>;
4511 def : St1Pat<v4i16, ST1Onev4h>;
4512 def : St1Pat<v2i32, ST1Onev2s>;
4513 def : St1Pat<v1i64, ST1Onev1d>;
4519 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4520 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4521 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4522 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4523 let mayLoad = 1, neverHasSideEffects = 1 in {
4524 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4525 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4526 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4527 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4528 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4529 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4530 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4531 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4532 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4533 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4534 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4535 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4536 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4537 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4538 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4539 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4542 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4543 (LD1Rv8b GPR64sp:$Rn)>;
4544 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4545 (LD1Rv16b GPR64sp:$Rn)>;
4546 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4547 (LD1Rv4h GPR64sp:$Rn)>;
4548 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4549 (LD1Rv8h GPR64sp:$Rn)>;
4550 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4551 (LD1Rv2s GPR64sp:$Rn)>;
4552 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4553 (LD1Rv4s GPR64sp:$Rn)>;
4554 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4555 (LD1Rv2d GPR64sp:$Rn)>;
4556 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4557 (LD1Rv1d GPR64sp:$Rn)>;
4558 // Grab the floating point version too
4559 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4560 (LD1Rv2s GPR64sp:$Rn)>;
4561 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4562 (LD1Rv4s GPR64sp:$Rn)>;
4563 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4564 (LD1Rv2d GPR64sp:$Rn)>;
4565 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4566 (LD1Rv1d GPR64sp:$Rn)>;
4568 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4569 ValueType VTy, ValueType STy, Instruction LD1>
4570 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4571 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4572 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4574 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4575 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4576 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4577 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4578 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4579 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4581 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4582 ValueType VTy, ValueType STy, Instruction LD1>
4583 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4584 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4586 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4587 VecIndex:$idx, GPR64sp:$Rn),
4590 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4591 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4592 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4593 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4596 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4597 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4598 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4599 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4602 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4603 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4604 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4605 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4607 let AddedComplexity = 15 in
4608 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4609 ValueType VTy, ValueType STy, Instruction ST1>
4611 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4613 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4615 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4616 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4617 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4618 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4619 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4620 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4622 let AddedComplexity = 15 in
4623 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4624 ValueType VTy, ValueType STy, Instruction ST1>
4626 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4628 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4629 VecIndex:$idx, GPR64sp:$Rn)>;
4631 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4632 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4633 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4634 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4636 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4637 ValueType VTy, ValueType STy, Instruction ST1,
4639 def : Pat<(scalar_store
4640 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4641 GPR64sp:$Rn, offset),
4642 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4643 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4645 def : Pat<(scalar_store
4646 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4647 GPR64sp:$Rn, GPR64:$Rm),
4648 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4649 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4652 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4653 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4655 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4656 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4657 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4658 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4660 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4661 ValueType VTy, ValueType STy, Instruction ST1,
4663 def : Pat<(scalar_store
4664 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4665 GPR64sp:$Rn, offset),
4666 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4668 def : Pat<(scalar_store
4669 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4670 GPR64sp:$Rn, GPR64:$Rm),
4671 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4674 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4676 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4678 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4679 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4680 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4681 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4683 let mayStore = 1, neverHasSideEffects = 1 in {
4684 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4685 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4686 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4687 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4688 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4689 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4690 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4691 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4692 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4693 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4694 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4695 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4698 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4699 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4700 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4701 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4703 //----------------------------------------------------------------------------
4704 // Crypto extensions
4705 //----------------------------------------------------------------------------
4707 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
4708 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
4709 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
4710 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
4712 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
4713 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
4714 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
4715 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
4716 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
4717 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
4718 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
4720 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
4721 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
4722 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
4724 //----------------------------------------------------------------------------
4726 //----------------------------------------------------------------------------
4727 // FIXME: Like for X86, these should go in their own separate .td file.
4729 // Any instruction that defines a 32-bit result leaves the high half of the
4730 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4731 // be copying from a truncate. But any other 32-bit operation will zero-extend
4733 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4734 def def32 : PatLeaf<(i32 GPR32:$src), [{
4735 return N->getOpcode() != ISD::TRUNCATE &&
4736 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4737 N->getOpcode() != ISD::CopyFromReg;
4740 // In the case of a 32-bit def that is known to implicitly zero-extend,
4741 // we can use a SUBREG_TO_REG.
4742 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4744 // For an anyext, we don't care what the high bits are, so we can perform an
4745 // INSERT_SUBREF into an IMPLICIT_DEF.
4746 def : Pat<(i64 (anyext GPR32:$src)),
4747 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4749 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4750 // instruction (UBFM) on the enclosing super-reg.
4751 def : Pat<(i64 (zext GPR32:$src)),
4752 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4754 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4755 // containing super-reg.
4756 def : Pat<(i64 (sext GPR32:$src)),
4757 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4758 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4759 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4760 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4761 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4762 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4763 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4764 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4766 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4767 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4768 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4769 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4770 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4771 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4773 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4774 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4775 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4776 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4777 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4778 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4780 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4781 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4782 (i64 (i64shift_a imm0_63:$imm)),
4783 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4785 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4786 // AddedComplexity for the following patterns since we want to match sext + sra
4787 // patterns before we attempt to match a single sra node.
4788 let AddedComplexity = 20 in {
4789 // We support all sext + sra combinations which preserve at least one bit of the
4790 // original value which is to be sign extended. E.g. we support shifts up to
4792 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4793 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4794 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4795 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4797 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4798 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4799 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4800 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4802 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4803 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4804 (i64 imm0_31:$imm), 31)>;
4805 } // AddedComplexity = 20
4807 // To truncate, we can simply extract from a subregister.
4808 def : Pat<(i32 (trunc GPR64sp:$src)),
4809 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4811 // __builtin_trap() uses the BRK instruction on AArch64.
4812 def : Pat<(trap), (BRK 1)>;
4814 // Conversions within AdvSIMD types in the same register size are free.
4815 // But because we need a consistent lane ordering, in big endian many
4816 // conversions require one or more REV instructions.
4818 // Consider a simple memory load followed by a bitconvert then a store.
4820 // v1 = BITCAST v2i32 v0 to v4i16
4823 // In big endian mode every memory access has an implicit byte swap. LDR and
4824 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
4825 // is, they treat the vector as a sequence of elements to be byte-swapped.
4826 // The two pairs of instructions are fundamentally incompatible. We've decided
4827 // to use LD1/ST1 only to simplify compiler implementation.
4829 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
4830 // the original code sequence:
4832 // v1 = REV v2i32 (implicit)
4833 // v2 = BITCAST v2i32 v1 to v4i16
4834 // v3 = REV v4i16 v2 (implicit)
4837 // But this is now broken - the value stored is different to the value loaded
4838 // due to lane reordering. To fix this, on every BITCAST we must perform two
4841 // v1 = REV v2i32 (implicit)
4843 // v3 = BITCAST v2i32 v2 to v4i16
4845 // v5 = REV v4i16 v4 (implicit)
4848 // This means an extra two instructions, but actually in most cases the two REV
4849 // instructions can be combined into one. For example:
4850 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
4852 // There is also no 128-bit REV instruction. This must be synthesized with an
4855 // Most bitconverts require some sort of conversion. The only exceptions are:
4856 // a) Identity conversions - vNfX <-> vNiX
4857 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
4860 let Predicates = [IsLE] in {
4861 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4862 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4863 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4864 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4866 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4867 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4868 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4869 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4870 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4871 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4872 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4873 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4874 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4875 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4877 let Predicates = [IsBE] in {
4878 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
4879 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4880 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
4881 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4882 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
4883 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4884 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
4885 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4887 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4888 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4889 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4890 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4891 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4892 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4893 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4894 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4896 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4897 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4898 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
4899 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4900 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
4901 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4902 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
4903 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4904 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
4906 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
4907 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
4908 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
4909 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
4910 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
4911 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4912 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
4913 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
4914 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4915 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4917 let Predicates = [IsLE] in {
4918 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
4919 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
4920 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
4921 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
4923 let Predicates = [IsBE] in {
4924 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
4925 (v1i64 (REV64v2i32 FPR64:$src))>;
4926 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
4927 (v1i64 (REV64v4i16 FPR64:$src))>;
4928 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
4929 (v1i64 (REV64v8i8 FPR64:$src))>;
4930 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
4931 (v1i64 (REV64v2i32 FPR64:$src))>;
4933 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4934 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4936 let Predicates = [IsLE] in {
4937 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
4938 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4939 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4940 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4941 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4943 let Predicates = [IsBE] in {
4944 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
4945 (v2i32 (REV64v2i32 FPR64:$src))>;
4946 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
4947 (v2i32 (REV32v4i16 FPR64:$src))>;
4948 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
4949 (v2i32 (REV32v8i8 FPR64:$src))>;
4950 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
4951 (v2i32 (REV64v2i32 FPR64:$src))>;
4952 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
4953 (v2i32 (REV64v2i32 FPR64:$src))>;
4955 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4957 let Predicates = [IsLE] in {
4958 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
4959 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4960 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4961 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4962 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4963 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4965 let Predicates = [IsBE] in {
4966 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
4967 (v4i16 (REV64v4i16 FPR64:$src))>;
4968 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
4969 (v4i16 (REV32v4i16 FPR64:$src))>;
4970 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
4971 (v4i16 (REV16v8i8 FPR64:$src))>;
4972 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
4973 (v4i16 (REV64v4i16 FPR64:$src))>;
4974 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
4975 (v4i16 (REV32v4i16 FPR64:$src))>;
4976 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
4977 (v4i16 (REV64v4i16 FPR64:$src))>;
4980 let Predicates = [IsLE] in {
4981 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
4982 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4983 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4984 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4985 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4986 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4988 let Predicates = [IsBE] in {
4989 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
4990 (v8i8 (REV64v8i8 FPR64:$src))>;
4991 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
4992 (v8i8 (REV32v8i8 FPR64:$src))>;
4993 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
4994 (v8i8 (REV16v8i8 FPR64:$src))>;
4995 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
4996 (v8i8 (REV64v8i8 FPR64:$src))>;
4997 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
4998 (v8i8 (REV32v8i8 FPR64:$src))>;
4999 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5000 (v8i8 (REV64v8i8 FPR64:$src))>;
5003 let Predicates = [IsLE] in {
5004 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5005 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5006 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5007 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5009 let Predicates = [IsBE] in {
5010 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5011 (f64 (REV64v2i32 FPR64:$src))>;
5012 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5013 (f64 (REV64v4i16 FPR64:$src))>;
5014 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5015 (f64 (REV64v2i32 FPR64:$src))>;
5016 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5017 (f64 (REV64v8i8 FPR64:$src))>;
5019 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5020 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5022 let Predicates = [IsLE] in {
5023 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5024 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5025 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5026 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5028 let Predicates = [IsBE] in {
5029 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5030 (v1f64 (REV64v2i32 FPR64:$src))>;
5031 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5032 (v1f64 (REV64v4i16 FPR64:$src))>;
5033 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5034 (v1f64 (REV64v8i8 FPR64:$src))>;
5035 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5036 (v1f64 (REV64v2i32 FPR64:$src))>;
5038 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5039 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5041 let Predicates = [IsLE] in {
5042 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5043 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5044 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5045 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5046 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5048 let Predicates = [IsBE] in {
5049 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5050 (v2f32 (REV64v2i32 FPR64:$src))>;
5051 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5052 (v2f32 (REV32v4i16 FPR64:$src))>;
5053 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5054 (v2f32 (REV32v8i8 FPR64:$src))>;
5055 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5056 (v2f32 (REV64v2i32 FPR64:$src))>;
5057 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5058 (v2f32 (REV64v2i32 FPR64:$src))>;
5060 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5062 let Predicates = [IsLE] in {
5063 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5064 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5065 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5066 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5067 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5068 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5070 let Predicates = [IsBE] in {
5071 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5072 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5073 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5074 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5075 (REV64v4i32 FPR128:$src), (i32 8)))>;
5076 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5077 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5078 (REV64v8i16 FPR128:$src), (i32 8)))>;
5079 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5080 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5081 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5082 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5083 (REV64v4i32 FPR128:$src), (i32 8)))>;
5084 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5085 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5086 (REV64v16i8 FPR128:$src), (i32 8)))>;
5089 let Predicates = [IsLE] in {
5090 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5091 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5092 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5093 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5094 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5096 let Predicates = [IsBE] in {
5097 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5098 (v2f64 (EXTv16i8 FPR128:$src,
5099 FPR128:$src, (i32 8)))>;
5100 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5101 (v2f64 (REV64v4i32 FPR128:$src))>;
5102 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5103 (v2f64 (REV64v8i16 FPR128:$src))>;
5104 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5105 (v2f64 (REV64v16i8 FPR128:$src))>;
5106 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5107 (v2f64 (REV64v4i32 FPR128:$src))>;
5109 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5111 let Predicates = [IsLE] in {
5112 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5113 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5114 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5115 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5116 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5118 let Predicates = [IsBE] in {
5119 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5120 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5121 (REV64v4i32 FPR128:$src), (i32 8)))>;
5122 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5123 (v4f32 (REV32v8i16 FPR128:$src))>;
5124 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5125 (v4f32 (REV32v16i8 FPR128:$src))>;
5126 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5127 (v4f32 (REV64v4i32 FPR128:$src))>;
5128 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5129 (v4f32 (REV64v4i32 FPR128:$src))>;
5131 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5133 let Predicates = [IsLE] in {
5134 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5135 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5136 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5137 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5138 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5140 let Predicates = [IsBE] in {
5141 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5142 (v2i64 (EXTv16i8 FPR128:$src,
5143 FPR128:$src, (i32 8)))>;
5144 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5145 (v2i64 (REV64v4i32 FPR128:$src))>;
5146 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5147 (v2i64 (REV64v8i16 FPR128:$src))>;
5148 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5149 (v2i64 (REV64v16i8 FPR128:$src))>;
5150 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5151 (v2i64 (REV64v4i32 FPR128:$src))>;
5153 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5155 let Predicates = [IsLE] in {
5156 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5157 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5158 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5159 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5160 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5162 let Predicates = [IsBE] in {
5163 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5164 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5165 (REV64v4i32 FPR128:$src),
5167 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5168 (v4i32 (REV64v4i32 FPR128:$src))>;
5169 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5170 (v4i32 (REV32v8i16 FPR128:$src))>;
5171 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5172 (v4i32 (REV32v16i8 FPR128:$src))>;
5173 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5174 (v4i32 (REV64v4i32 FPR128:$src))>;
5176 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5178 let Predicates = [IsLE] in {
5179 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5180 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5181 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5182 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5183 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5184 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5186 let Predicates = [IsBE] in {
5187 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5188 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5189 (REV64v8i16 FPR128:$src),
5191 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5192 (v8i16 (REV64v8i16 FPR128:$src))>;
5193 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5194 (v8i16 (REV32v8i16 FPR128:$src))>;
5195 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5196 (v8i16 (REV16v16i8 FPR128:$src))>;
5197 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5198 (v8i16 (REV64v8i16 FPR128:$src))>;
5199 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5200 (v8i16 (REV32v8i16 FPR128:$src))>;
5203 let Predicates = [IsLE] in {
5204 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5205 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5206 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5207 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5208 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5209 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5211 let Predicates = [IsBE] in {
5212 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5213 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5214 (REV64v16i8 FPR128:$src),
5216 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5217 (v16i8 (REV64v16i8 FPR128:$src))>;
5218 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5219 (v16i8 (REV32v16i8 FPR128:$src))>;
5220 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5221 (v16i8 (REV16v16i8 FPR128:$src))>;
5222 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5223 (v16i8 (REV64v16i8 FPR128:$src))>;
5224 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5225 (v16i8 (REV32v16i8 FPR128:$src))>;
5228 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5229 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5230 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5231 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5232 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5233 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5234 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5235 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5237 // A 64-bit subvector insert to the first 128-bit vector position
5238 // is a subregister copy that needs no instruction.
5239 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5240 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5241 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5242 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5243 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5244 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5245 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5246 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5247 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5248 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5249 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5250 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5252 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5254 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5255 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5256 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5257 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5258 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5259 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5260 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5261 // so we match on v4f32 here, not v2f32. This will also catch adding
5262 // the low two lanes of a true v4f32 vector.
5263 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5264 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5265 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5267 // Scalar 64-bit shifts in FPR64 registers.
5268 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5269 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5270 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5271 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5272 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5273 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5274 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5275 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5277 // Tail call return handling. These are all compiler pseudo-instructions,
5278 // so no encoding information or anything like that.
5279 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5280 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5281 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5284 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5285 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5286 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5287 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5288 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5289 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5291 include "AArch64InstrAtomics.td"