1 //===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 scalar instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasNEON : Predicate<"Subtarget->hasNEON()">,
18 AssemblerPredicate<"FeatureNEON", "neon">;
19 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
20 AssemblerPredicate<"FeatureCrypto","crypto">;
22 // Use fused MAC if more precision in FP computation is allowed.
23 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
24 " FPOpFusion::Fast)">;
25 include "AArch64InstrFormats.td"
27 //===----------------------------------------------------------------------===//
28 // Target-specific ISD nodes and profiles
29 //===----------------------------------------------------------------------===//
31 def SDT_A64ret : SDTypeProfile<0, 0, []>;
32 def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain,
36 // (ins NZCV, Condition, Dest)
37 def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>;
38 def A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>;
40 // (outs Result), (ins NZCV, IfTrue, IfFalse, Condition)
41 def SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>,
44 def A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>;
46 // (outs NZCV), (ins LHS, RHS, Condition)
47 def SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
49 def A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>;
52 // (outs GPR64), (ins)
53 def A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
55 // A64 compares don't care about the cond really (they set all flags) so a
56 // simple binary operator is useful.
57 def A64cmp : PatFrag<(ops node:$lhs, node:$rhs),
58 (A64setcc node:$lhs, node:$rhs, cond)>;
61 // When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN
62 // instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C
63 // and V flags can be set differently by this operation. It comes down to
64 // whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are
65 // then everything is fine. If not then the optimization is wrong. Thus general
66 // comparisons are only valid if op2 != 0.
68 // So, finally, the only LLVM-native comparisons that don't mention C and V are
69 // SETEQ and SETNE. They're the only ones we can safely use CMN for in the
70 // absence of information about op2.
71 def equality_cond : PatLeaf<(cond), [{
72 return N->get() == ISD::SETEQ || N->get() == ISD::SETNE;
75 def A64cmn : PatFrag<(ops node:$lhs, node:$rhs),
76 (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>;
78 // There are two layers of indirection here, driven by the following
80 // + TableGen does not know CodeModel or Reloc so that decision should be
81 // made for a variable/address at ISelLowering.
82 // + The output of ISelLowering should be selectable (hence the Wrapper,
83 // rather than a bare target opcode)
84 def SDTAArch64WrapperLarge : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
90 def A64WrapperLarge :SDNode<"AArch64ISD::WrapperLarge", SDTAArch64WrapperLarge>;
92 def SDTAArch64WrapperSmall : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
97 def A64WrapperSmall :SDNode<"AArch64ISD::WrapperSmall", SDTAArch64WrapperSmall>;
100 def SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
101 def A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad,
105 // (A64BFI LHS, RHS, LSB, Width)
106 def SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
111 def A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>;
113 // (A64EXTR HiReg, LoReg, LSB)
114 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
116 def A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
118 // (A64[SU]BFX Field, ImmR, ImmS).
120 // Note that ImmR and ImmS are already encoded for the actual instructions. The
121 // more natural LSB and Width mix together to form ImmR and ImmS, something
122 // which TableGen can't handle.
123 def SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>;
124 def A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>;
126 def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>;
128 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
130 //===----------------------------------------------------------------------===//
131 // Call sequence pseudo-instructions
132 //===----------------------------------------------------------------------===//
135 def SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
136 def AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
139 def AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call,
140 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 // The TLSDESCCALL node is a variant call which goes to an indirectly calculated
143 // destination but needs a relocation against a fixed symbol. As such it has two
144 // certain operands: the callee and the relocated variable.
146 // The TLS ABI only allows it to be selected to a BLR instructin (with
147 // appropriate relocation).
148 def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
150 def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall,
151 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
155 def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>;
156 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart,
157 [SDNPHasChain, SDNPOutGlue]>;
159 def SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>;
160 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd,
161 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
165 // These pseudo-instructions have special semantics by virtue of being passed to
166 // the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by
167 // LowerCall to (in our case) tell the back-end about stack adjustments for
168 // arguments passed on the stack. Here we select those markers to
169 // pseudo-instructions which explicitly set the stack, and finally in the
170 // RegisterInfo we convert them to a true stack adjustment.
171 let Defs = [XSP], Uses = [XSP] in {
172 def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt),
173 [(AArch64callseq_start timm:$amt)]>;
175 def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2),
176 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
179 //===----------------------------------------------------------------------===//
180 // Atomic operation pseudo-instructions
181 //===----------------------------------------------------------------------===//
183 // These get selected from C++ code as a pretty much direct translation from the
184 // generic DAG nodes. The one exception is the AtomicOrdering is added as an
185 // operand so that the eventual lowering can make use of it and choose
186 // acquire/release operations when required.
188 let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in {
189 multiclass AtomicSizes {
190 def _I8 : PseudoInst<(outs GPR32:$dst),
191 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
192 def _I16 : PseudoInst<(outs GPR32:$dst),
193 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
194 def _I32 : PseudoInst<(outs GPR32:$dst),
195 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
196 def _I64 : PseudoInst<(outs GPR64:$dst),
197 (ins GPR64xsp:$ptr, GPR64:$incr, i32imm:$ordering), []>;
201 defm ATOMIC_LOAD_ADD : AtomicSizes;
202 defm ATOMIC_LOAD_SUB : AtomicSizes;
203 defm ATOMIC_LOAD_AND : AtomicSizes;
204 defm ATOMIC_LOAD_OR : AtomicSizes;
205 defm ATOMIC_LOAD_XOR : AtomicSizes;
206 defm ATOMIC_LOAD_NAND : AtomicSizes;
207 defm ATOMIC_SWAP : AtomicSizes;
208 let Defs = [NZCV] in {
209 // These operations need a CMP to calculate the correct value
210 defm ATOMIC_LOAD_MIN : AtomicSizes;
211 defm ATOMIC_LOAD_MAX : AtomicSizes;
212 defm ATOMIC_LOAD_UMIN : AtomicSizes;
213 defm ATOMIC_LOAD_UMAX : AtomicSizes;
216 class AtomicCmpSwap<RegisterClass GPRData>
217 : PseudoInst<(outs GPRData:$dst),
218 (ins GPR64xsp:$ptr, GPRData:$old, GPRData:$new,
219 i32imm:$ordering), []> {
220 let usesCustomInserter = 1;
227 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>;
228 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>;
229 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>;
230 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>;
232 //===----------------------------------------------------------------------===//
233 // Add-subtract (extended register) instructions
234 //===----------------------------------------------------------------------===//
235 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP
237 // The RHS of these operations is conceptually a sign/zero-extended
238 // register, optionally shifted left by 1-4. The extension can be a
239 // NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but
240 // must be specified with one exception:
242 // If one of the registers is sp/wsp then LSL is an alias for UXTW in
243 // 32-bit instructions and UXTX in 64-bit versions, the shift amount
244 // is not optional in that case (but can explicitly be 0), and the
245 // entire suffix can be skipped (e.g. "add sp, x3, x2").
247 multiclass extend_operands<string PREFIX, string Diag> {
248 def _asmoperand : AsmOperandClass {
250 let RenderMethod = "addRegExtendOperands";
251 let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">";
252 let DiagnosticType = "AddSubRegExtend" # Diag;
255 def _operand : Operand<i64>,
256 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> {
257 let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">";
258 let DecoderMethod = "DecodeRegExtendOperand";
259 let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand");
263 defm UXTB : extend_operands<"UXTB", "Small">;
264 defm UXTH : extend_operands<"UXTH", "Small">;
265 defm UXTW : extend_operands<"UXTW", "Small">;
266 defm UXTX : extend_operands<"UXTX", "Large">;
267 defm SXTB : extend_operands<"SXTB", "Small">;
268 defm SXTH : extend_operands<"SXTH", "Small">;
269 defm SXTW : extend_operands<"SXTW", "Small">;
270 defm SXTX : extend_operands<"SXTX", "Large">;
272 def LSL_extasmoperand : AsmOperandClass {
273 let Name = "RegExtendLSL";
274 let RenderMethod = "addRegExtendOperands";
275 let DiagnosticType = "AddSubRegExtendLarge";
278 def LSL_extoperand : Operand<i64> {
279 let ParserMatchClass = LSL_extasmoperand;
283 // The patterns for various sign-extensions are a little ugly and
284 // non-uniform because everything has already been promoted to the
285 // legal i64 and i32 types. We'll wrap the various variants up in a
286 // class for use later.
288 dag uxtb; dag uxth; dag uxtw; dag uxtx;
289 dag sxtb; dag sxth; dag sxtw; dag sxtx;
294 def extends_to_i64 : extend_types {
295 let uxtb = (and (anyext i32:$Rm), 255);
296 let uxth = (and (anyext i32:$Rm), 65535);
297 let uxtw = (zext i32:$Rm);
298 let uxtx = (i64 $Rm);
300 let sxtb = (sext_inreg (anyext i32:$Rm), i8);
301 let sxth = (sext_inreg (anyext i32:$Rm), i16);
302 let sxtw = (sext i32:$Rm);
303 let sxtx = (i64 $Rm);
310 def extends_to_i32 : extend_types {
311 let uxtb = (and i32:$Rm, 255);
312 let uxth = (and i32:$Rm, 65535);
313 let uxtw = (i32 i32:$Rm);
314 let uxtx = (i32 i32:$Rm);
316 let sxtb = (sext_inreg i32:$Rm, i8);
317 let sxth = (sext_inreg i32:$Rm, i16);
318 let sxtw = (i32 i32:$Rm);
319 let sxtx = (i32 i32:$Rm);
325 // Now, six of the extensions supported are easy and uniform: if the source size
326 // is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate
327 // those instructions in one block.
329 // The uxtx/sxtx could potentially be merged in, but three facts dissuaded me:
330 // + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would
332 // + Patterns are very different as well.
333 // + Passing different registers would be ugly (more fields in extend_types
334 // would probably be the best option).
335 multiclass addsub_exts<bit sf, bit op, bit S, string asmop,
336 SDPatternOperator opfrag,
337 dag outs, extend_types exts> {
338 def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000,
339 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
340 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
341 [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
343 def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001,
344 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
345 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
346 [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
348 def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010,
349 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
350 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
351 [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
354 def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100,
355 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
356 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
357 [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
359 def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101,
360 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
361 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
362 [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
364 def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110,
365 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
366 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
367 [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
371 // These two could be merge in with the above, but their patterns aren't really
372 // necessary and the naming-scheme would necessarily break:
373 multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag,
375 def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011,
377 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
378 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
379 [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))],
382 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
384 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),
385 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
386 [/* No Pattern: same as uxtx */],
390 multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {
391 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
393 (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
394 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
395 [/* No pattern: probably same as uxtw */],
398 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,
400 (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
401 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
402 [/* No Pattern: probably same as uxtw */],
406 class SetRD<RegisterClass RC, SDPatternOperator op>
407 : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>;
408 class SetNZCV<SDPatternOperator op>
409 : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>;
411 defm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
412 (outs GPR64xsp:$Rd), extends_to_i64>,
413 addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
414 (outs GPR64xsp:$Rd)>;
415 defm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>,
416 (outs GPR32wsp:$Rd), extends_to_i32>,
417 addsub_wxtx< 0b0, 0b0, "add\t$Rd, ",
418 (outs GPR32wsp:$Rd)>;
419 defm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
420 (outs GPR64xsp:$Rd), extends_to_i64>,
421 addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
422 (outs GPR64xsp:$Rd)>;
423 defm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>,
424 (outs GPR32wsp:$Rd), extends_to_i32>,
425 addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ",
426 (outs GPR32wsp:$Rd)>;
428 let Defs = [NZCV] in {
429 defm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
430 (outs GPR64:$Rd), extends_to_i64>,
431 addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
433 defm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>,
434 (outs GPR32:$Rd), extends_to_i32>,
435 addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ",
437 defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
438 (outs GPR64:$Rd), extends_to_i64>,
439 addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
441 defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>,
442 (outs GPR32:$Rd), extends_to_i32>,
443 addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ",
447 let Rd = 0b11111, isCompare = 1 in {
448 defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
449 (outs), extends_to_i64>,
450 addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
451 defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
452 (outs), extends_to_i32>,
453 addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>;
454 defm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
455 (outs), extends_to_i64>,
456 addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>;
457 defm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
458 (outs), extends_to_i32>,
459 addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>;
463 // Now patterns for the operation without a shift being needed. No patterns are
464 // created for uxtx/sxtx since they're non-uniform and it's expected that
465 // add/sub (shifted register) will handle those cases anyway.
466 multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop,
468 def : Pat<(nodeop exts.ty:$Rn, exts.uxtb),
469 (!cast<Instruction>(prefix # "w_uxtb") $Rn, $Rm, 0)>;
470 def : Pat<(nodeop exts.ty:$Rn, exts.uxth),
471 (!cast<Instruction>(prefix # "w_uxth") $Rn, $Rm, 0)>;
472 def : Pat<(nodeop exts.ty:$Rn, exts.uxtw),
473 (!cast<Instruction>(prefix # "w_uxtw") $Rn, $Rm, 0)>;
475 def : Pat<(nodeop exts.ty:$Rn, exts.sxtb),
476 (!cast<Instruction>(prefix # "w_sxtb") $Rn, $Rm, 0)>;
477 def : Pat<(nodeop exts.ty:$Rn, exts.sxth),
478 (!cast<Instruction>(prefix # "w_sxth") $Rn, $Rm, 0)>;
479 def : Pat<(nodeop exts.ty:$Rn, exts.sxtw),
480 (!cast<Instruction>(prefix # "w_sxtw") $Rn, $Rm, 0)>;
483 defm : addsubext_noshift_patterns<"ADDxx", add, extends_to_i64>;
484 defm : addsubext_noshift_patterns<"ADDww", add, extends_to_i32>;
485 defm : addsubext_noshift_patterns<"SUBxx", sub, extends_to_i64>;
486 defm : addsubext_noshift_patterns<"SUBww", sub, extends_to_i32>;
488 defm : addsubext_noshift_patterns<"CMNx", A64cmn, extends_to_i64>;
489 defm : addsubext_noshift_patterns<"CMNw", A64cmn, extends_to_i32>;
490 defm : addsubext_noshift_patterns<"CMPx", A64cmp, extends_to_i64>;
491 defm : addsubext_noshift_patterns<"CMPw", A64cmp, extends_to_i32>;
493 // An extend of "lsl #imm" is valid if and only if one of Rn and Rd is
494 // sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the
495 // operation. Also permitted in this case is complete omission of the argument,
496 // which implies "lsl #0".
497 multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd,
498 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
499 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
500 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
502 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"),
503 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
507 defm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
508 defm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
509 defm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>;
510 defm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>;
511 defm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
512 defm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
513 defm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>;
514 defm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>;
516 // Rd cannot be sp for flag-setting variants so only half of the aliases are
518 defm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>;
519 defm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>;
520 defm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>;
521 defm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>;
523 // CMP unfortunately has to be different because the instruction doesn't have a
525 multiclass cmp_lsl_aliases<string asmop, Instruction inst,
526 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
527 def : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
528 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
530 def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"),
531 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
534 defm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>;
535 defm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>;
536 defm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>;
537 defm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>;
539 //===----------------------------------------------------------------------===//
540 // Add-subtract (immediate) instructions
541 //===----------------------------------------------------------------------===//
542 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV
544 // These instructions accept a 12-bit unsigned immediate, optionally shifted
545 // left by 12 bits. Official assembly format specifies a 12 bit immediate with
546 // one of "", "LSL #0", "LSL #12" supplementary operands.
548 // There are surprisingly few ways to make this work with TableGen, so this
549 // implementation has separate instructions for the "LSL #0" and "LSL #12"
552 // If the MCInst retained a single combined immediate (which could be 0x123000,
553 // for example) then both components (imm & shift) would have to be delegated to
554 // a single assembly operand. This would entail a separate operand parser
555 // (because the LSL would have to live in the same AArch64Operand as the
556 // immediate to be accessible); assembly parsing is rather complex and
557 // error-prone C++ code.
559 // By splitting the immediate, we can delegate handling this optional operand to
560 // an InstAlias. Supporting functions to generate the correct MCInst are still
561 // required, but these are essentially trivial and parsing can remain generic.
563 // Rejected plans with rationale:
564 // ------------------------------
566 // In an ideal world you'de have two first class immediate operands (in
567 // InOperandList, specifying imm12 and shift). Unfortunately this is not
568 // selectable by any means I could discover.
570 // An Instruction with two MCOperands hidden behind a single entry in
571 // InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional,
572 // but required more C++ code to handle encoding/decoding. Parsing (the intended
573 // main beneficiary) ended up equally complex because of the optional nature of
576 // Attempting to circumvent the need for a custom OperandParser above by giving
577 // InstAliases without the "lsl #0" failed. add/sub could be accommodated but
578 // the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands
579 // should be parsed: there was no way to accommodate an "lsl #12".
581 let ParserMethod = "ParseImmWithLSLOperand",
582 RenderMethod = "addImmWithLSLOperands" in {
583 // Derived PredicateMethod fields are different for each
584 def addsubimm_lsl0_asmoperand : AsmOperandClass {
585 let Name = "AddSubImmLSL0";
586 // If an error is reported against this operand, instruction could also be a
588 let DiagnosticType = "AddSubSecondSource";
591 def addsubimm_lsl12_asmoperand : AsmOperandClass {
592 let Name = "AddSubImmLSL12";
593 let DiagnosticType = "AddSubSecondSource";
597 def shr_12_XFORM : SDNodeXForm<imm, [{
598 return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32);
601 def shr_12_neg_XFORM : SDNodeXForm<imm, [{
602 return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32);
605 def neg_XFORM : SDNodeXForm<imm, [{
606 return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32);
610 multiclass addsub_imm_operands<ValueType ty> {
611 let PrintMethod = "printAddSubImmLSL0Operand",
612 EncoderMethod = "getAddSubImmOpValue",
613 ParserMatchClass = addsubimm_lsl0_asmoperand in {
614 def _posimm_lsl0 : Operand<ty>,
615 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>;
616 def _negimm_lsl0 : Operand<ty>,
617 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }],
621 let PrintMethod = "printAddSubImmLSL12Operand",
622 EncoderMethod = "getAddSubImmOpValue",
623 ParserMatchClass = addsubimm_lsl12_asmoperand in {
624 def _posimm_lsl12 : Operand<ty>,
625 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }],
628 def _negimm_lsl12 : Operand<ty>,
629 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }],
634 // The add operands don't need any transformation
635 defm addsubimm_operand_i32 : addsub_imm_operands<i32>;
636 defm addsubimm_operand_i64 : addsub_imm_operands<i64>;
638 multiclass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift,
639 string asmop, string cmpasmop,
640 Operand imm_operand, Operand cmp_imm_operand,
641 RegisterClass GPR, RegisterClass GPRsp,
642 AArch64Reg ZR, ValueType Ty> {
643 // All registers for non-S variants allow SP
644 def _s : A64I_addsubimm<sf, op, 0b0, shift,
646 (ins GPRsp:$Rn, imm_operand:$Imm12),
647 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
648 [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],
652 // S variants can read SP but would write to ZR
653 def _S : A64I_addsubimm<sf, op, 0b1, shift,
655 (ins GPRsp:$Rn, imm_operand:$Imm12),
656 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
657 [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],
662 // Note that the pattern here for ADDS is subtle. Canonically CMP
663 // a, b becomes SUBS a, b. If b < 0 then this is equivalent to
664 // ADDS a, (-b). This is not true in general.
665 def _cmp : A64I_addsubimm<sf, op, 0b1, shift,
666 (outs), (ins GPRsp:$Rn, imm_operand:$Imm12),
667 !strconcat(cmpasmop, " $Rn, $Imm12"),
669 (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
678 multiclass addsubimm_shifts<string prefix, bit sf, bit op,
679 string asmop, string cmpasmop, string operand, string cmpoperand,
680 RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR,
682 defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00,
684 !cast<Operand>(operand # "_lsl0"),
685 !cast<Operand>(cmpoperand # "_lsl0"),
688 defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01,
690 !cast<Operand>(operand # "_lsl12"),
691 !cast<Operand>(cmpoperand # "_lsl12"),
695 defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn",
696 "addsubimm_operand_i32_posimm",
697 "addsubimm_operand_i32_negimm",
698 GPR32, GPR32wsp, WZR, i32>;
699 defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn",
700 "addsubimm_operand_i64_posimm",
701 "addsubimm_operand_i64_negimm",
702 GPR64, GPR64xsp, XZR, i64>;
703 defm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp",
704 "addsubimm_operand_i32_negimm",
705 "addsubimm_operand_i32_posimm",
706 GPR32, GPR32wsp, WZR, i32>;
707 defm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp",
708 "addsubimm_operand_i64_negimm",
709 "addsubimm_operand_i64_posimm",
710 GPR64, GPR64xsp, XZR, i64>;
712 multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> {
713 def _fromsp : InstAlias<"mov $Rd, $Rn",
714 (addop GPRsp:$Rd, SP:$Rn, 0),
717 def _tosp : InstAlias<"mov $Rd, $Rn",
718 (addop SP:$Rd, GPRsp:$Rn, 0),
722 // Recall Rxsp is a RegisterClass containing *just* xsp.
723 defm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>;
724 defm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>;
726 //===----------------------------------------------------------------------===//
727 // Add-subtract (shifted register) instructions
728 //===----------------------------------------------------------------------===//
729 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS
731 //===-------------------------------
732 // 1. The "shifed register" operands. Shared with logical insts.
733 //===-------------------------------
735 multiclass shift_operands<string prefix, string form> {
736 def _asmoperand_i32 : AsmOperandClass {
737 let Name = "Shift" # form # "i32";
738 let RenderMethod = "addShiftOperands";
739 let PredicateMethod = "isShift<A64SE::" # form # ", false>";
740 let DiagnosticType = "AddSubRegShift32";
743 // Note that the operand type is intentionally i64 because the DAGCombiner
744 // puts these into a canonical form.
745 def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
747 = !cast<AsmOperandClass>(prefix # "_asmoperand_i32");
748 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
749 let DecoderMethod = "Decode32BitShiftOperand";
752 def _asmoperand_i64 : AsmOperandClass {
753 let Name = "Shift" # form # "i64";
754 let RenderMethod = "addShiftOperands";
755 let PredicateMethod = "isShift<A64SE::" # form # ", true>";
756 let DiagnosticType = "AddSubRegShift64";
759 def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
761 = !cast<AsmOperandClass>(prefix # "_asmoperand_i64");
762 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
766 defm lsl_operand : shift_operands<"lsl_operand", "LSL">;
767 defm lsr_operand : shift_operands<"lsr_operand", "LSR">;
768 defm asr_operand : shift_operands<"asr_operand", "ASR">;
770 // Not used for add/sub, but defined here for completeness. The "logical
771 // (shifted register)" instructions *do* have an ROR variant.
772 defm ror_operand : shift_operands<"ror_operand", "ROR">;
774 //===-------------------------------
775 // 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions.
776 //===-------------------------------
778 // N.b. the commutable parameter is just !N. It will be first against the wall
779 // when the revolution comes.
780 multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable,
781 string asmop, SDPatternOperator opfrag, ValueType ty,
782 RegisterClass GPR, list<Register> defs> {
783 let isCommutable = commutable, Defs = defs in {
784 def _lsl : A64I_addsubshift<sf, op, s, 0b00,
786 (ins GPR:$Rn, GPR:$Rm,
787 !cast<Operand>("lsl_operand_" # ty):$Imm6),
788 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
789 [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
790 !cast<Operand>("lsl_operand_" # ty):$Imm6))
794 def _lsr : A64I_addsubshift<sf, op, s, 0b01,
796 (ins GPR:$Rn, GPR:$Rm,
797 !cast<Operand>("lsr_operand_" # ty):$Imm6),
798 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
799 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
800 !cast<Operand>("lsr_operand_" # ty):$Imm6))
804 def _asr : A64I_addsubshift<sf, op, s, 0b10,
806 (ins GPR:$Rn, GPR:$Rm,
807 !cast<Operand>("asr_operand_" # ty):$Imm6),
808 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
809 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
810 !cast<Operand>("asr_operand_" # ty):$Imm6))
816 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
817 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
820 def : Pat<(opfrag ty:$Rn, ty:$Rm),
821 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
824 multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable,
825 string asmop, SDPatternOperator opfrag,
826 list<Register> defs> {
827 defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s,
828 commutable, asmop, opfrag, i64, GPR64, defs>;
829 defm www : addsub_shifts<prefix # "www", 0b0, op, s,
830 commutable, asmop, opfrag, i32, GPR32, defs>;
834 defm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>;
835 defm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>;
837 defm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>;
838 defm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>;
840 //===-------------------------------
841 // 1. The NEG/NEGS aliases
842 //===-------------------------------
844 multiclass neg_alias<Instruction INST, RegisterClass GPR, Register ZR,
845 ValueType ty, Operand shift_operand, SDNode shiftop> {
846 def : InstAlias<"neg $Rd, $Rm, $Imm6",
847 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
849 def : Pat<(sub 0, (shiftop ty:$Rm, shift_operand:$Imm6)),
850 (INST ZR, $Rm, shift_operand:$Imm6)>;
853 defm : neg_alias<SUBwww_lsl, GPR32, WZR, i32, lsl_operand_i32, shl>;
854 defm : neg_alias<SUBwww_lsr, GPR32, WZR, i32, lsr_operand_i32, srl>;
855 defm : neg_alias<SUBwww_asr, GPR32, WZR, i32, asr_operand_i32, sra>;
856 def : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
857 def : Pat<(sub 0, i32:$Rm), (SUBwww_lsl WZR, $Rm, 0)>;
859 defm : neg_alias<SUBxxx_lsl, GPR64, XZR, i64, lsl_operand_i64, shl>;
860 defm : neg_alias<SUBxxx_lsr, GPR64, XZR, i64, lsr_operand_i64, srl>;
861 defm : neg_alias<SUBxxx_asr, GPR64, XZR, i64, asr_operand_i64, sra>;
862 def : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
863 def : Pat<(sub 0, i64:$Rm), (SUBxxx_lsl XZR, $Rm, 0)>;
865 // NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to
867 class negs_alias<Instruction INST, RegisterClass GPR,
868 Register ZR, Operand shift_operand, SDNode shiftop>
869 : InstAlias<"negs $Rd, $Rm, $Imm6",
870 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
872 def : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>;
873 def : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>;
874 def : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>;
875 def : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
877 def : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>;
878 def : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>;
879 def : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>;
880 def : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
882 //===-------------------------------
883 // 1. The CMP/CMN aliases
884 //===-------------------------------
886 multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable,
887 string asmop, SDPatternOperator opfrag, ValueType ty,
889 let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in {
890 def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00,
892 (ins GPR:$Rn, GPR:$Rm,
893 !cast<Operand>("lsl_operand_" # ty):$Imm6),
894 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
895 [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm,
896 !cast<Operand>("lsl_operand_" # ty):$Imm6))
900 def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01,
902 (ins GPR:$Rn, GPR:$Rm,
903 !cast<Operand>("lsr_operand_" # ty):$Imm6),
904 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
905 [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm,
906 !cast<Operand>("lsr_operand_" # ty):$Imm6))
910 def _asr : A64I_addsubshift<sf, op, 0b1, 0b10,
912 (ins GPR:$Rn, GPR:$Rm,
913 !cast<Operand>("asr_operand_" # ty):$Imm6),
914 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
915 [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm,
916 !cast<Operand>("asr_operand_" # ty):$Imm6))
922 : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
923 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
925 def : Pat<(opfrag ty:$Rn, ty:$Rm),
926 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
929 defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, i32, GPR32>;
930 defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, i64, GPR64>;
932 defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, i32, GPR32>;
933 defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, i64, GPR64>;
935 //===----------------------------------------------------------------------===//
936 // Add-subtract (with carry) instructions
937 //===----------------------------------------------------------------------===//
938 // Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS
940 multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> {
941 let Uses = [NZCV] in {
942 def www : A64I_addsubcarry<0b0, op, s, 0b000000,
943 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
944 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
947 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,
948 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
949 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
954 let isCommutable = 1 in {
955 defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">;
958 defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">;
960 let Defs = [NZCV] in {
961 let isCommutable = 1 in {
962 defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">;
965 defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">;
968 def : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>;
969 def : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
970 def : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>;
971 def : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
973 // Note that adde and sube can form a chain longer than two (e.g. for 256-bit
974 // addition). So the flag-setting instructions are appropriate.
975 def : Pat<(adde i32:$Rn, i32:$Rm), (ADCSwww $Rn, $Rm)>;
976 def : Pat<(adde i64:$Rn, i64:$Rm), (ADCSxxx $Rn, $Rm)>;
977 def : Pat<(sube i32:$Rn, i32:$Rm), (SBCSwww $Rn, $Rm)>;
978 def : Pat<(sube i64:$Rn, i64:$Rm), (SBCSxxx $Rn, $Rm)>;
980 //===----------------------------------------------------------------------===//
982 //===----------------------------------------------------------------------===//
983 // Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL,
986 // Because of the rather complicated nearly-overlapping aliases, the decoding of
987 // this range of instructions is handled manually. The architectural
988 // instructions are BFM, SBFM and UBFM but a disassembler should never produce
991 // In the end, the best option was to use BFM instructions for decoding under
992 // almost all circumstances, but to create aliasing *Instructions* for each of
993 // the canonical forms and specify a completely custom decoder which would
994 // substitute the correct MCInst as needed.
996 // This also simplifies instruction selection, parsing etc because the MCInsts
997 // have a shape that's closer to their use in code.
999 //===-------------------------------
1000 // 1. The architectural BFM instructions
1001 //===-------------------------------
1003 def uimm5_asmoperand : AsmOperandClass {
1005 let PredicateMethod = "isUImm<5>";
1006 let RenderMethod = "addImmOperands";
1007 let DiagnosticType = "UImm5";
1010 def uimm6_asmoperand : AsmOperandClass {
1012 let PredicateMethod = "isUImm<6>";
1013 let RenderMethod = "addImmOperands";
1014 let DiagnosticType = "UImm6";
1017 def bitfield32_imm : Operand<i64>,
1018 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> {
1019 let ParserMatchClass = uimm5_asmoperand;
1021 let DecoderMethod = "DecodeBitfield32ImmOperand";
1025 def bitfield64_imm : Operand<i64>,
1026 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
1027 let ParserMatchClass = uimm6_asmoperand;
1029 // Default decoder works in 64-bit case: the 6-bit field can take any value.
1032 multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> {
1033 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1034 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1035 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1037 let DecoderMethod = "DecodeBitfieldInstruction";
1040 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1041 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1042 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1044 let DecoderMethod = "DecodeBitfieldInstruction";
1048 defm SBFM : A64I_bitfieldSizes<0b00, "sbfm">;
1049 defm UBFM : A64I_bitfieldSizes<0b10, "ubfm">;
1051 // BFM instructions modify the destination register rather than defining it
1054 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1055 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1056 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1057 let DecoderMethod = "DecodeBitfieldInstruction";
1058 let Constraints = "$src = $Rd";
1062 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1063 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1064 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1065 let DecoderMethod = "DecodeBitfieldInstruction";
1066 let Constraints = "$src = $Rd";
1070 //===-------------------------------
1071 // 2. Extend aliases to 64-bit dest
1072 //===-------------------------------
1074 // Unfortunately the extensions that end up as 64-bits cannot be handled by an
1075 // instruction alias: their syntax is (for example) "SXTB x0, w0", which needs
1076 // to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is
1077 // not capable of such a map as far as I'm aware
1079 // Note that these instructions are strictly more specific than the
1080 // BFM ones (in ImmR) so they can handle their own decoding.
1081 class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, ValueType dty,
1082 string asmop, bits<6> imms, dag pattern>
1083 : A64I_bitfield<sf, opc, sf,
1084 (outs GPRDest:$Rd), (ins GPR32:$Rn),
1085 !strconcat(asmop, "\t$Rd, $Rn"),
1086 [(set dty:$Rd, pattern)], NoItinerary> {
1087 let ImmR = 0b000000;
1091 // Signed extensions
1092 def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtb", 7,
1093 (sext_inreg (anyext i32:$Rn), i8)>;
1094 def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxtb", 7,
1095 (sext_inreg i32:$Rn, i8)>;
1096 def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxth", 15,
1097 (sext_inreg (anyext i32:$Rn), i16)>;
1098 def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxth", 15,
1099 (sext_inreg i32:$Rn, i16)>;
1100 def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtw", 31, (sext i32:$Rn)>;
1102 // Unsigned extensions
1103 def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxtb", 7,
1104 (and i32:$Rn, 255)>;
1105 def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxth", 15,
1106 (and i32:$Rn, 65535)>;
1108 // The 64-bit unsigned variants are not strictly architectural but recommended
1110 let isAsmParserOnly = 1 in {
1111 def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxtb", 7,
1112 (and (anyext i32:$Rn), 255)>;
1113 def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxth", 15,
1114 (and (anyext i32:$Rn), 65535)>;
1117 // Extra patterns for when the source register is actually 64-bits
1118 // too. There's no architectural difference here, it's just LLVM
1119 // shinanigans. There's no need for equivalent zero-extension patterns
1120 // because they'll already be caught by logical (immediate) matching.
1121 def : Pat<(sext_inreg i64:$Rn, i8),
1122 (SXTBxw (EXTRACT_SUBREG $Rn, sub_32))>;
1123 def : Pat<(sext_inreg i64:$Rn, i16),
1124 (SXTHxw (EXTRACT_SUBREG $Rn, sub_32))>;
1125 def : Pat<(sext_inreg i64:$Rn, i32),
1126 (SXTWxw (EXTRACT_SUBREG $Rn, sub_32))>;
1129 //===-------------------------------
1130 // 3. Aliases for ASR and LSR (the simple shifts)
1131 //===-------------------------------
1133 // These also handle their own decoding because ImmS being set makes
1134 // them take precedence over BFM.
1135 multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> {
1136 def wwi : A64I_bitfield<0b0, opc, 0b0,
1137 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
1138 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1139 [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))],
1144 def xxi : A64I_bitfield<0b1, opc, 0b1,
1145 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
1146 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1147 [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))],
1154 defm ASR : A64I_shift<0b00, "asr", sra>;
1155 defm LSR : A64I_shift<0b10, "lsr", srl>;
1157 //===-------------------------------
1158 // 4. Aliases for LSL
1159 //===-------------------------------
1161 // Unfortunately LSL and subsequent aliases are much more complicated. We need
1162 // to be able to say certain output instruction fields depend in a complex
1163 // manner on combinations of input assembly fields).
1165 // MIOperandInfo *might* have been able to do it, but at the cost of
1166 // significantly more C++ code.
1168 // N.b. contrary to usual practice these operands store the shift rather than
1169 // the machine bits in an MCInst. The complexity overhead of consistency
1170 // outweighed the benefits in this case (custom asmparser, printer and selection
1171 // vs custom encoder).
1172 def bitfield32_lsl_imm : Operand<i64>,
1173 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1174 let ParserMatchClass = uimm5_asmoperand;
1175 let EncoderMethod = "getBitfield32LSLOpValue";
1178 def bitfield64_lsl_imm : Operand<i64>,
1179 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1180 let ParserMatchClass = uimm6_asmoperand;
1181 let EncoderMethod = "getBitfield64LSLOpValue";
1184 class A64I_bitfield_lsl<bit sf, RegisterClass GPR, ValueType ty,
1186 : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),
1187 "lsl\t$Rd, $Rn, $FullImm",
1188 [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))],
1191 let ImmR = FullImm{5-0};
1192 let ImmS = FullImm{11-6};
1194 // No disassembler allowed because it would overlap with BFM which does the
1196 let isAsmParserOnly = 1;
1199 def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, i32, bitfield32_lsl_imm>;
1200 def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, i64, bitfield64_lsl_imm>;
1202 //===-------------------------------
1203 // 5. Aliases for bitfield extract instructions
1204 //===-------------------------------
1206 def bfx32_width_asmoperand : AsmOperandClass {
1207 let Name = "BFX32Width";
1208 let PredicateMethod = "isBitfieldWidth<32>";
1209 let RenderMethod = "addBFXWidthOperands";
1210 let DiagnosticType = "Width32";
1213 def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> {
1214 let PrintMethod = "printBFXWidthOperand";
1215 let ParserMatchClass = bfx32_width_asmoperand;
1218 def bfx64_width_asmoperand : AsmOperandClass {
1219 let Name = "BFX64Width";
1220 let PredicateMethod = "isBitfieldWidth<64>";
1221 let RenderMethod = "addBFXWidthOperands";
1222 let DiagnosticType = "Width64";
1225 def bfx64_width : Operand<i64> {
1226 let PrintMethod = "printBFXWidthOperand";
1227 let ParserMatchClass = bfx64_width_asmoperand;
1231 multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> {
1232 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1233 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1234 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1235 [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))],
1237 // As above, no disassembler allowed.
1238 let isAsmParserOnly = 1;
1241 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1242 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1243 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1244 [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))],
1246 // As above, no disassembler allowed.
1247 let isAsmParserOnly = 1;
1251 defm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>;
1252 defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>;
1254 // Again, variants based on BFM modify Rd so need it as an input too.
1255 def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1256 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1257 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1258 // As above, no disassembler allowed.
1259 let isAsmParserOnly = 1;
1260 let Constraints = "$src = $Rd";
1263 def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1264 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1265 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1266 // As above, no disassembler allowed.
1267 let isAsmParserOnly = 1;
1268 let Constraints = "$src = $Rd";
1271 // SBFX instructions can do a 1-instruction sign-extension of boolean values.
1272 def : Pat<(sext_inreg i64:$Rn, i1), (SBFXxxii $Rn, 0, 0)>;
1273 def : Pat<(sext_inreg i32:$Rn, i1), (SBFXwwii $Rn, 0, 0)>;
1274 def : Pat<(i64 (sext_inreg (anyext i32:$Rn), i1)),
1275 (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>;
1277 // UBFX makes sense as an implementation of a 64-bit zero-extension too. Could
1278 // use either 64-bit or 32-bit variant, but 32-bit might be more efficient.
1279 def : Pat<(zext i32:$Rn), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31),
1282 //===-------------------------------
1283 // 6. Aliases for bitfield insert instructions
1284 //===-------------------------------
1286 def bfi32_lsb_asmoperand : AsmOperandClass {
1287 let Name = "BFI32LSB";
1288 let PredicateMethod = "isUImm<5>";
1289 let RenderMethod = "addBFILSBOperands<32>";
1290 let DiagnosticType = "UImm5";
1293 def bfi32_lsb : Operand<i64>,
1294 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1295 let PrintMethod = "printBFILSBOperand<32>";
1296 let ParserMatchClass = bfi32_lsb_asmoperand;
1299 def bfi64_lsb_asmoperand : AsmOperandClass {
1300 let Name = "BFI64LSB";
1301 let PredicateMethod = "isUImm<6>";
1302 let RenderMethod = "addBFILSBOperands<64>";
1303 let DiagnosticType = "UImm6";
1306 def bfi64_lsb : Operand<i64>,
1307 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1308 let PrintMethod = "printBFILSBOperand<64>";
1309 let ParserMatchClass = bfi64_lsb_asmoperand;
1312 // Width verification is performed during conversion so width operand can be
1313 // shared between 32/64-bit cases. Still needed for the print method though
1314 // because ImmR encodes "width - 1".
1315 def bfi32_width_asmoperand : AsmOperandClass {
1316 let Name = "BFI32Width";
1317 let PredicateMethod = "isBitfieldWidth<32>";
1318 let RenderMethod = "addBFIWidthOperands";
1319 let DiagnosticType = "Width32";
1322 def bfi32_width : Operand<i64>,
1323 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> {
1324 let PrintMethod = "printBFIWidthOperand";
1325 let ParserMatchClass = bfi32_width_asmoperand;
1328 def bfi64_width_asmoperand : AsmOperandClass {
1329 let Name = "BFI64Width";
1330 let PredicateMethod = "isBitfieldWidth<64>";
1331 let RenderMethod = "addBFIWidthOperands";
1332 let DiagnosticType = "Width64";
1335 def bfi64_width : Operand<i64>,
1336 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> {
1337 let PrintMethod = "printBFIWidthOperand";
1338 let ParserMatchClass = bfi64_width_asmoperand;
1341 multiclass A64I_bitfield_insert<bits<2> opc, string asmop> {
1342 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1343 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1344 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1346 // As above, no disassembler allowed.
1347 let isAsmParserOnly = 1;
1350 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1351 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1352 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1354 // As above, no disassembler allowed.
1355 let isAsmParserOnly = 1;
1359 defm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">;
1360 defm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">;
1363 def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1364 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1365 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1366 // As above, no disassembler allowed.
1367 let isAsmParserOnly = 1;
1368 let Constraints = "$src = $Rd";
1371 def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1372 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1373 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1374 // As above, no disassembler allowed.
1375 let isAsmParserOnly = 1;
1376 let Constraints = "$src = $Rd";
1379 //===----------------------------------------------------------------------===//
1380 // Compare and branch (immediate)
1381 //===----------------------------------------------------------------------===//
1382 // Contains: CBZ, CBNZ
1384 class label_asmoperand<int width, int scale> : AsmOperandClass {
1385 let Name = "Label" # width # "_" # scale;
1386 let PredicateMethod = "isLabel<" # width # "," # scale # ">";
1387 let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">";
1388 let DiagnosticType = "Label";
1391 def label_wid19_scal4_asmoperand : label_asmoperand<19, 4>;
1393 // All conditional immediate branches are the same really: 19 signed bits scaled
1394 // by the instruction-size (4).
1395 def bcc_target : Operand<OtherVT> {
1396 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
1397 let ParserMatchClass = label_wid19_scal4_asmoperand;
1398 let PrintMethod = "printLabelOperand<19, 4>";
1399 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>";
1400 let OperandType = "OPERAND_PCREL";
1403 multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> {
1404 let isBranch = 1, isTerminator = 1 in {
1405 def x : A64I_cmpbr<0b1, op,
1407 (ins GPR64:$Rt, bcc_target:$Label),
1408 !strconcat(asmop,"\t$Rt, $Label"),
1409 [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],
1412 def w : A64I_cmpbr<0b0, op,
1414 (ins GPR32:$Rt, bcc_target:$Label),
1415 !strconcat(asmop,"\t$Rt, $Label"),
1416 [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],
1421 defm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{
1422 return Imm == A64CC::EQ;
1424 defm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{
1425 return Imm == A64CC::NE;
1428 //===----------------------------------------------------------------------===//
1429 // Conditional branch (immediate) instructions
1430 //===----------------------------------------------------------------------===//
1433 def cond_code_asmoperand : AsmOperandClass {
1434 let Name = "CondCode";
1435 let DiagnosticType = "CondCode";
1438 def cond_code : Operand<i32>, ImmLeaf<i32, [{
1439 return Imm >= 0 && Imm <= 15;
1441 let PrintMethod = "printCondCodeOperand";
1442 let ParserMatchClass = cond_code_asmoperand;
1445 def Bcc : A64I_condbr<0b0, 0b0, (outs),
1446 (ins cond_code:$Cond, bcc_target:$Label),
1447 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
1451 let isTerminator = 1;
1454 //===----------------------------------------------------------------------===//
1455 // Conditional compare (immediate) instructions
1456 //===----------------------------------------------------------------------===//
1457 // Contains: CCMN, CCMP
1459 def uimm4_asmoperand : AsmOperandClass {
1461 let PredicateMethod = "isUImm<4>";
1462 let RenderMethod = "addImmOperands";
1463 let DiagnosticType = "UImm4";
1466 def uimm4 : Operand<i32> {
1467 let ParserMatchClass = uimm4_asmoperand;
1470 def uimm5 : Operand<i32> {
1471 let ParserMatchClass = uimm5_asmoperand;
1474 // The only difference between this operand and the one for instructions like
1475 // B.cc is that it's parsed manually. The other get parsed implicitly as part of
1476 // the mnemonic handling.
1477 def cond_code_op_asmoperand : AsmOperandClass {
1478 let Name = "CondCodeOp";
1479 let RenderMethod = "addCondCodeOperands";
1480 let PredicateMethod = "isCondCode";
1481 let ParserMethod = "ParseCondCodeOperand";
1482 let DiagnosticType = "CondCode";
1485 def cond_code_op : Operand<i32> {
1486 let PrintMethod = "printCondCodeOperand";
1487 let ParserMatchClass = cond_code_op_asmoperand;
1490 class A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1491 : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),
1492 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
1493 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
1498 def CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">;
1499 def CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">;
1500 def CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">;
1501 def CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">;
1503 //===----------------------------------------------------------------------===//
1504 // Conditional compare (register) instructions
1505 //===----------------------------------------------------------------------===//
1506 // Contains: CCMN, CCMP
1508 class A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1509 : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1,
1511 (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
1512 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
1517 def CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">;
1518 def CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">;
1519 def CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">;
1520 def CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">;
1522 //===----------------------------------------------------------------------===//
1523 // Conditional select instructions
1524 //===----------------------------------------------------------------------===//
1525 // Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG
1527 // Condition code which is encoded as the inversion (semantically rather than
1528 // bitwise) in the instruction.
1529 def inv_cond_code_op_asmoperand : AsmOperandClass {
1530 let Name = "InvCondCodeOp";
1531 let RenderMethod = "addInvCondCodeOperands";
1532 let PredicateMethod = "isCondCode";
1533 let ParserMethod = "ParseCondCodeOperand";
1534 let DiagnosticType = "CondCode";
1537 def inv_cond_code_op : Operand<i32> {
1538 let ParserMatchClass = inv_cond_code_op_asmoperand;
1541 // Having a separate operand for the selectable use-case is debatable, but gives
1542 // consistency with cond_code.
1543 def inv_cond_XFORM : SDNodeXForm<imm, [{
1544 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue());
1545 return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32);
1549 : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>;
1552 multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
1553 SDPatternOperator select> {
1554 let Uses = [NZCV] in {
1555 def wwwc : A64I_condsel<0b0, op, 0b0, op2,
1557 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
1558 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1559 [(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
1563 def xxxc : A64I_condsel<0b1, op, 0b0, op2,
1565 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
1566 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1567 [(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
1573 : PatFrag<(ops node:$lhs, node:$rhs),
1574 (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>;
1576 class complex_select<SDPatternOperator opnode>
1577 : PatFrag<(ops node:$lhs, node:$rhs),
1578 (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>;
1581 defm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>;
1582 defm CSINC : A64I_condselSizes<0b0, 0b01, "csinc",
1583 complex_select<PatFrag<(ops node:$val),
1584 (add node:$val, 1)>>>;
1585 defm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>;
1586 defm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>;
1588 // Now the instruction aliases, which fit nicely into LLVM's model:
1590 def : InstAlias<"cset $Rd, $Cond",
1591 (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1592 def : InstAlias<"cset $Rd, $Cond",
1593 (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1594 def : InstAlias<"csetm $Rd, $Cond",
1595 (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1596 def : InstAlias<"csetm $Rd, $Cond",
1597 (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1598 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1599 (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1600 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1601 (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1602 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1603 (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1604 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1605 (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1606 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1607 (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1608 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1609 (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1611 // Finally some helper patterns.
1613 // For CSET (a.k.a. zero-extension of icmp)
1614 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1615 (CSINCwwwc WZR, WZR, cond_code:$Cond)>;
1616 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1617 (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>;
1619 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1620 (CSINCxxxc XZR, XZR, cond_code:$Cond)>;
1621 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1622 (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>;
1624 // For CSETM (a.k.a. sign-extension of icmp)
1625 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1626 (CSINVwwwc WZR, WZR, cond_code:$Cond)>;
1627 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1628 (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>;
1630 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1631 (CSINVxxxc XZR, XZR, cond_code:$Cond)>;
1632 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1633 (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>;
1635 // CINC, CINV and CNEG get dealt with automatically, which leaves the issue of
1636 // commutativity. The instructions are to complex for isCommutable to be used,
1637 // so we have to create the patterns manually:
1639 // No commutable pattern for CSEL since the commuted version is isomorphic.
1642 def :Pat<(A64select_cc NZCV, (add i32:$Rm, 1), i32:$Rn, inv_cond_code:$Cond),
1643 (CSINCwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1644 def :Pat<(A64select_cc NZCV, (add i64:$Rm, 1), i64:$Rn, inv_cond_code:$Cond),
1645 (CSINCxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1648 def :Pat<(A64select_cc NZCV, (not i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1649 (CSINVwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1650 def :Pat<(A64select_cc NZCV, (not i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1651 (CSINVxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1654 def :Pat<(A64select_cc NZCV, (ineg i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1655 (CSNEGwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1656 def :Pat<(A64select_cc NZCV, (ineg i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1657 (CSNEGxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1659 //===----------------------------------------------------------------------===//
1660 // Data Processing (1 source) instructions
1661 //===----------------------------------------------------------------------===//
1662 // Contains: RBIT, REV16, REV, REV32, CLZ, CLS.
1664 // We define an unary operator which always fails. We will use this to
1665 // define unary operators that cannot be matched.
1667 class A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop,
1668 list<dag> patterns, RegisterClass GPRrc,
1669 InstrItinClass itin>:
1674 !strconcat(asmop, "\t$Rd, $Rn"),
1680 multiclass A64I_dp_1src <bits<6> opcode, string asmop> {
1681 let hasSideEffects = 0 in {
1682 def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>;
1683 def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>;
1687 defm RBIT : A64I_dp_1src<0b000000, "rbit">;
1688 defm CLS : A64I_dp_1src<0b000101, "cls">;
1689 defm CLZ : A64I_dp_1src<0b000100, "clz">;
1691 def : Pat<(ctlz i32:$Rn), (CLZww $Rn)>;
1692 def : Pat<(ctlz i64:$Rn), (CLZxx $Rn)>;
1693 def : Pat<(ctlz_zero_undef i32:$Rn), (CLZww $Rn)>;
1694 def : Pat<(ctlz_zero_undef i64:$Rn), (CLZxx $Rn)>;
1696 def : Pat<(cttz i32:$Rn), (CLZww (RBITww $Rn))>;
1697 def : Pat<(cttz i64:$Rn), (CLZxx (RBITxx $Rn))>;
1698 def : Pat<(cttz_zero_undef i32:$Rn), (CLZww (RBITww $Rn))>;
1699 def : Pat<(cttz_zero_undef i64:$Rn), (CLZxx (RBITxx $Rn))>;
1702 def REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev",
1703 [(set i32:$Rd, (bswap i32:$Rn))],
1704 GPR32, NoItinerary>;
1705 def REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev",
1706 [(set i64:$Rd, (bswap i64:$Rn))],
1707 GPR64, NoItinerary>;
1708 def REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32",
1709 [(set i64:$Rd, (bswap (rotr i64:$Rn, (i64 32))))],
1710 GPR64, NoItinerary>;
1711 def REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16",
1712 [(set i32:$Rd, (bswap (rotr i32:$Rn, (i64 16))))],
1715 def REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>;
1717 //===----------------------------------------------------------------------===//
1718 // Data Processing (2 sources) instructions
1719 //===----------------------------------------------------------------------===//
1720 // Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL,
1724 class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns,
1725 RegisterClass GPRsp,
1726 InstrItinClass itin>:
1730 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
1732 (ins GPRsp:$Rn, GPRsp:$Rm),
1736 multiclass dp_2src_crc<bit c, string asmop> {
1737 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
1738 !strconcat(asmop, "b"), [], GPR32, NoItinerary>;
1739 def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1},
1740 !strconcat(asmop, "h"), [], GPR32, NoItinerary>;
1741 def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0},
1742 !strconcat(asmop, "w"), [], GPR32, NoItinerary>;
1743 def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
1744 !strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
1745 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
1749 multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
1750 def www : dp_2src_impl<0b0,
1754 (op i32:$Rn, (i64 (zext i32:$Rm))))],
1757 def xxx : dp_2src_impl<0b1,
1760 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1766 multiclass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> {
1767 def www : dp_2src_impl<0b0,
1770 [(set i32:$Rd, (op i32:$Rn, i32:$Rm))],
1773 def xxx : dp_2src_impl<0b1,
1776 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1781 // Here we define the data processing 2 source instructions.
1782 defm CRC32 : dp_2src_crc<0b0, "crc32">;
1783 defm CRC32C : dp_2src_crc<0b1, "crc32c">;
1785 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1786 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1788 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1789 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1790 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1791 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1793 // Extra patterns for an incoming 64-bit value for a 32-bit
1794 // operation. Since the LLVM operations are undefined (as in C) if the
1795 // RHS is out of range, it's perfectly permissible to discard the high
1796 // bits of the GPR64.
1797 def : Pat<(shl i32:$Rn, i64:$Rm),
1798 (LSLVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1799 def : Pat<(srl i32:$Rn, i64:$Rm),
1800 (LSRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1801 def : Pat<(sra i32:$Rn, i64:$Rm),
1802 (ASRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1803 def : Pat<(rotr i32:$Rn, i64:$Rm),
1804 (RORVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1806 // Here we define the aliases for the data processing 2 source instructions.
1807 def LSL_mnemonic : MnemonicAlias<"lslv", "lsl">;
1808 def LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">;
1809 def ASR_menmonic : MnemonicAlias<"asrv", "asr">;
1810 def ROR_menmonic : MnemonicAlias<"rorv", "ror">;
1812 //===----------------------------------------------------------------------===//
1813 // Data Processing (3 sources) instructions
1814 //===----------------------------------------------------------------------===//
1815 // Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH
1816 // + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL
1818 class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg,
1819 ValueType AccTy, RegisterClass SrcReg,
1820 string asmop, dag pattern>
1821 : A64I_dp3<sf, opcode,
1822 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
1823 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
1824 [(set AccTy:$Rd, pattern)], NoItinerary> {
1825 RegisterClass AccGPR = AccReg;
1826 RegisterClass SrcGPR = SrcReg;
1829 def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, i32, GPR32, "madd",
1830 (add i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1831 def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, i64, GPR64, "madd",
1832 (add i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1834 def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, i32, GPR32, "msub",
1835 (sub i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1836 def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, i64, GPR64, "msub",
1837 (sub i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1839 def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, i64, GPR32, "smaddl",
1840 (add i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1841 def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, i64, GPR32, "smsubl",
1842 (sub i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1844 def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, i64, GPR32, "umaddl",
1845 (add i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1846 def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, i64, GPR32, "umsubl",
1847 (sub i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1849 let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in {
1850 def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd),
1851 (ins GPR64:$Rn, GPR64:$Rm),
1852 "umulh\t$Rd, $Rn, $Rm",
1853 [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))],
1856 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
1857 (ins GPR64:$Rn, GPR64:$Rm),
1858 "smulh\t$Rd, $Rn, $Rm",
1859 [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))],
1863 multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,
1864 Register ZR, dag pattern> {
1865 def : InstAlias<asmop # " $Rd, $Rn, $Rm",
1866 (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
1868 def : Pat<pattern, (INST $Rn, $Rm, ZR)>;
1871 defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul i32:$Rn, i32:$Rm)>;
1872 defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul i64:$Rn, i64:$Rm)>;
1874 defm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR,
1875 (sub 0, (mul i32:$Rn, i32:$Rm))>;
1876 defm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR,
1877 (sub 0, (mul i64:$Rn, i64:$Rm))>;
1879 defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR,
1880 (mul (i64 (sext i32:$Rn)), (sext i32:$Rm))>;
1881 defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR,
1882 (sub 0, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1884 defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR,
1885 (mul (i64 (zext i32:$Rn)), (zext i32:$Rm))>;
1886 defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR,
1887 (sub 0, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1890 //===----------------------------------------------------------------------===//
1891 // Exception generation
1892 //===----------------------------------------------------------------------===//
1893 // Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3
1895 def uimm16_asmoperand : AsmOperandClass {
1896 let Name = "UImm16";
1897 let PredicateMethod = "isUImm<16>";
1898 let RenderMethod = "addImmOperands";
1899 let DiagnosticType = "UImm16";
1902 def uimm16 : Operand<i32> {
1903 let ParserMatchClass = uimm16_asmoperand;
1906 class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop>
1907 : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),
1908 !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {
1910 let isTerminator = 1;
1913 def SVCi : A64I_exceptImpl<0b000, 0b01, "svc">;
1914 def HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">;
1915 def SMCi : A64I_exceptImpl<0b000, 0b11, "smc">;
1916 def BRKi : A64I_exceptImpl<0b001, 0b00, "brk">;
1917 def HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">;
1919 def DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">;
1920 def DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">;
1921 def DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">;
1923 // The immediate is optional for the DCPS instructions, defaulting to 0.
1924 def : InstAlias<"dcps1", (DCPS1i 0)>;
1925 def : InstAlias<"dcps2", (DCPS2i 0)>;
1926 def : InstAlias<"dcps3", (DCPS3i 0)>;
1928 //===----------------------------------------------------------------------===//
1929 // Extract (immediate)
1930 //===----------------------------------------------------------------------===//
1931 // Contains: EXTR + alias ROR
1933 def EXTRwwwi : A64I_extract<0b0, 0b000, 0b0,
1935 (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB),
1936 "extr\t$Rd, $Rn, $Rm, $LSB",
1938 (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))],
1940 def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
1942 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
1943 "extr\t$Rd, $Rn, $Rm, $LSB",
1945 (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))],
1948 def : InstAlias<"ror $Rd, $Rs, $LSB",
1949 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;
1950 def : InstAlias<"ror $Rd, $Rs, $LSB",
1951 (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>;
1953 def : Pat<(rotr i32:$Rn, bitfield32_imm:$LSB),
1954 (EXTRwwwi $Rn, $Rn, bitfield32_imm:$LSB)>;
1955 def : Pat<(rotr i64:$Rn, bitfield64_imm:$LSB),
1956 (EXTRxxxi $Rn, $Rn, bitfield64_imm:$LSB)>;
1958 //===----------------------------------------------------------------------===//
1959 // Floating-point compare instructions
1960 //===----------------------------------------------------------------------===//
1961 // Contains: FCMP, FCMPE
1963 def fpzero_asmoperand : AsmOperandClass {
1964 let Name = "FPZero";
1965 let ParserMethod = "ParseFPImmOperand";
1966 let DiagnosticType = "FPZero";
1969 def fpz32 : Operand<f32>,
1970 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
1971 let ParserMatchClass = fpzero_asmoperand;
1972 let PrintMethod = "printFPZeroOperand";
1973 let DecoderMethod = "DecodeFPZeroOperand";
1976 def fpz64 : Operand<f64>,
1977 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
1978 let ParserMatchClass = fpzero_asmoperand;
1979 let PrintMethod = "printFPZeroOperand";
1980 let DecoderMethod = "DecodeFPZeroOperand";
1983 multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {
1984 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
1985 (outs), ins, "fcmp\t$Rn, $Rm", [pattern],
1990 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
1991 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> {
1996 defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm),
1997 (set NZCV, (A64cmp f32:$Rn, f32:$Rm))>;
1998 defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm),
1999 (set NZCV, (A64cmp f64:$Rn, f64:$Rm))>;
2001 // What would be Rm should be written as 0; note that even though it's called
2002 // "$Rm" here to fit in with the InstrFormats, it's actually an immediate.
2003 defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm),
2004 (set NZCV, (A64cmp f32:$Rn, fpz32:$Rm))>;
2006 defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm),
2007 (set NZCV, (A64cmp f64:$Rn, fpz64:$Rm))>;
2010 //===----------------------------------------------------------------------===//
2011 // Floating-point conditional compare instructions
2012 //===----------------------------------------------------------------------===//
2013 // Contains: FCCMP, FCCMPE
2015 class A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop>
2016 : A64I_fpccmp<0b0, 0b0, type, op,
2018 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
2019 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
2024 def FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">;
2025 def FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">;
2026 def FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">;
2027 def FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">;
2029 //===----------------------------------------------------------------------===//
2030 // Floating-point conditional select instructions
2031 //===----------------------------------------------------------------------===//
2034 let Uses = [NZCV] in {
2035 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
2036 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
2037 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2039 (simple_select f32:$Rn, f32:$Rm))],
2043 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
2044 (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond),
2045 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2047 (simple_select f64:$Rn, f64:$Rm))],
2051 //===----------------------------------------------------------------------===//
2052 // Floating-point data-processing (1 source)
2053 //===----------------------------------------------------------------------===//
2054 // Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI].
2056 def FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val),
2057 [{ (void)N; return false; }]>;
2059 // First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d"
2060 // syntax. Default to no pattern because most are odd enough not to have one.
2061 multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr,
2062 SDPatternOperator opnode = FPNoUnop> {
2063 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
2064 !strconcat(asmstr, "\t$Rd, $Rn"),
2065 [(set f32:$Rd, (opnode f32:$Rn))],
2068 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
2069 !strconcat(asmstr, "\t$Rd, $Rn"),
2070 [(set f64:$Rd, (opnode f64:$Rn))],
2074 defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;
2075 defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;
2076 defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;
2077 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
2079 defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;
2080 defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;
2081 defm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>;
2082 defm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>;
2083 defm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">;
2084 defm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>;
2085 defm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>;
2087 // The FCVT instrucitons have different source and destination register-types,
2088 // but the fields are uniform everywhere a D-register (say) crops up. Package
2089 // this information in a Record.
2090 class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> {
2091 RegisterClass Class = rc;
2097 def FCVT16 : FCVTRegType<FPR16, 0b11, f16>;
2098 def FCVT32 : FCVTRegType<FPR32, 0b00, f32>;
2099 def FCVT64 : FCVTRegType<FPR64, 0b01, f64>;
2101 class A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode>
2102 : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0},
2103 {0,0,0,1, DestReg.t1, DestReg.t0},
2104 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
2106 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>;
2108 def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>;
2109 def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>;
2110 def FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>;
2111 def FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>;
2112 def FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>;
2113 def FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>;
2116 //===----------------------------------------------------------------------===//
2117 // Floating-point data-processing (2 sources) instructions
2118 //===----------------------------------------------------------------------===//
2119 // Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
2121 def FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs),
2122 [{ (void)N; return false; }]>;
2124 multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr,
2125 SDPatternOperator opnode> {
2126 def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode,
2128 (ins FPR32:$Rn, FPR32:$Rm),
2129 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2130 [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))],
2133 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
2135 (ins FPR64:$Rn, FPR64:$Rm),
2136 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2137 [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))],
2141 let isCommutable = 1 in {
2142 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
2143 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;
2145 // No patterns for these.
2146 defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>;
2147 defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>;
2148 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;
2149 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;
2151 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2152 PatFrag<(ops node:$lhs, node:$rhs),
2153 (fneg (fmul node:$lhs, node:$rhs))> >;
2156 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
2157 defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;
2159 //===----------------------------------------------------------------------===//
2160 // Floating-point data-processing (3 sources) instructions
2161 //===----------------------------------------------------------------------===//
2162 // Contains: FMADD, FMSUB, FNMADD, FNMSUB
2164 def fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2165 (fma (fneg node:$Rn), node:$Rm, node:$Ra)>;
2166 def fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2167 (fma node:$Rn, node:$Rm, (fneg node:$Ra))>;
2168 def fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2169 (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>;
2171 class A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT,
2172 bits<2> type, bit o1, bit o0, SDPatternOperator fmakind>
2173 : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd),
2174 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
2175 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
2176 [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))],
2179 def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
2180 def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;
2181 def FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>;
2182 def FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>;
2184 def FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>;
2185 def FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>;
2186 def FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>;
2187 def FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>;
2189 // Extra patterns for when we're allowed to optimise separate multiplication and
2191 let Predicates = [UseFusedMAC] in {
2192 def : Pat<(f32 (fadd FPR32:$Ra, (f32 (fmul FPR32:$Rn, FPR32:$Rm)))),
2193 (FMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2194 def : Pat<(f32 (fsub FPR32:$Ra, (f32 (fmul FPR32:$Rn, FPR32:$Rm)))),
2195 (FMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2196 def : Pat<(f32 (fsub (f32 (fmul FPR32:$Rn, FPR32:$Rm)), FPR32:$Ra)),
2197 (FNMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2198 def : Pat<(f32 (fsub (f32 (fneg FPR32:$Ra)), (f32 (fmul FPR32:$Rn, FPR32:$Rm)))),
2199 (FNMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2201 def : Pat<(f64 (fadd FPR64:$Ra, (f64 (fmul FPR64:$Rn, FPR64:$Rm)))),
2202 (FMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2203 def : Pat<(f64 (fsub FPR64:$Ra, (f64 (fmul FPR64:$Rn, FPR64:$Rm)))),
2204 (FMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2205 def : Pat<(f64 (fsub (f64 (fmul FPR64:$Rn, FPR64:$Rm)), FPR64:$Ra)),
2206 (FNMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2207 def : Pat<(f64 (fsub (f64 (fneg FPR64:$Ra)), (f64 (fmul FPR64:$Rn, FPR64:$Rm)))),
2208 (FNMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2212 //===----------------------------------------------------------------------===//
2213 // Floating-point <-> fixed-point conversion instructions
2214 //===----------------------------------------------------------------------===//
2215 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2217 // #1-#32 allowed, encoded as "64 - <specified imm>
2218 def fixedpos_asmoperand_i32 : AsmOperandClass {
2219 let Name = "CVTFixedPos32";
2220 let RenderMethod = "addCVTFixedPosOperands";
2221 let PredicateMethod = "isCVTFixedPos<32>";
2222 let DiagnosticType = "CVTFixedPos32";
2225 // Also encoded as "64 - <specified imm>" but #1-#64 allowed.
2226 def fixedpos_asmoperand_i64 : AsmOperandClass {
2227 let Name = "CVTFixedPos64";
2228 let RenderMethod = "addCVTFixedPosOperands";
2229 let PredicateMethod = "isCVTFixedPos<64>";
2230 let DiagnosticType = "CVTFixedPos64";
2233 // We need the cartesian product of f32/f64 i32/i64 operands for
2235 // + Selection needs to use operands of correct floating type
2236 // + Assembly parsing and decoding depend on integer width
2237 class cvtfix_i32_op<ValueType FloatVT>
2239 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> {
2240 let ParserMatchClass = fixedpos_asmoperand_i32;
2241 let DecoderMethod = "DecodeCVT32FixedPosOperand";
2242 let PrintMethod = "printCVTFixedPosOperand";
2245 class cvtfix_i64_op<ValueType FloatVT>
2247 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> {
2248 let ParserMatchClass = fixedpos_asmoperand_i64;
2249 let PrintMethod = "printCVTFixedPosOperand";
2252 // Because of the proliferation of weird operands, it's not really
2253 // worth going for a multiclass here. Oh well.
2255 class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode,
2256 RegisterClass GPR, RegisterClass FPR,
2257 ValueType DstTy, ValueType SrcTy,
2258 Operand scale_op, string asmop, SDNode cvtop>
2259 : A64I_fpfixed<sf, 0b0, type, 0b11, opcode,
2260 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
2261 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2262 [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))],
2265 def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32,
2266 cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>;
2267 def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32, i64, f32,
2268 cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>;
2269 def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32, i32, f32,
2270 cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>;
2271 def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32, i64, f32,
2272 cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>;
2274 def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64, i32, f64,
2275 cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>;
2276 def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64, i64, f64,
2277 cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>;
2278 def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64, i32, f64,
2279 cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>;
2280 def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64, i64, f64,
2281 cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>;
2284 class A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode,
2285 RegisterClass FPR, RegisterClass GPR,
2286 ValueType DstTy, ValueType SrcTy,
2287 Operand scale_op, string asmop, SDNode cvtop>
2288 : A64I_fpfixed<sf, 0b0, type, 0b00, opcode,
2289 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
2290 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2291 [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))],
2294 def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32,
2295 cvtfix_i32_op<f32>, "scvtf", sint_to_fp>;
2296 def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64, f32, i64,
2297 cvtfix_i64_op<f32>, "scvtf", sint_to_fp>;
2298 def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32, f32, i32,
2299 cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>;
2300 def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64, f32, i64,
2301 cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>;
2302 def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32, f64, i32,
2303 cvtfix_i32_op<f64>, "scvtf", sint_to_fp>;
2304 def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64, f64, i64,
2305 cvtfix_i64_op<f64>, "scvtf", sint_to_fp>;
2306 def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32, f64, i32,
2307 cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>;
2308 def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64, f64, i64,
2309 cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>;
2311 //===----------------------------------------------------------------------===//
2312 // Floating-point <-> integer conversion instructions
2313 //===----------------------------------------------------------------------===//
2314 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2316 class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode,
2317 RegisterClass DestPR, RegisterClass SrcPR, string asmop>
2318 : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),
2319 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;
2321 multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {
2322 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
2323 GPR32, FPR32, asmop # "s">;
2324 def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0},
2325 GPR64, FPR32, asmop # "s">;
2326 def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1},
2327 GPR32, FPR32, asmop # "u">;
2328 def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1},
2329 GPR64, FPR32, asmop # "u">;
2331 def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0},
2332 GPR32, FPR64, asmop # "s">;
2333 def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0},
2334 GPR64, FPR64, asmop # "s">;
2335 def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1},
2336 GPR32, FPR64, asmop # "u">;
2337 def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1},
2338 GPR64, FPR64, asmop # "u">;
2341 defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">;
2342 defm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">;
2343 defm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">;
2344 defm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">;
2345 defm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">;
2347 def : Pat<(i32 (fp_to_sint f32:$Rn)), (FCVTZSws $Rn)>;
2348 def : Pat<(i64 (fp_to_sint f32:$Rn)), (FCVTZSxs $Rn)>;
2349 def : Pat<(i32 (fp_to_uint f32:$Rn)), (FCVTZUws $Rn)>;
2350 def : Pat<(i64 (fp_to_uint f32:$Rn)), (FCVTZUxs $Rn)>;
2351 def : Pat<(i32 (fp_to_sint f64:$Rn)), (FCVTZSwd $Rn)>;
2352 def : Pat<(i64 (fp_to_sint f64:$Rn)), (FCVTZSxd $Rn)>;
2353 def : Pat<(i32 (fp_to_uint f64:$Rn)), (FCVTZUwd $Rn)>;
2354 def : Pat<(i64 (fp_to_uint f64:$Rn)), (FCVTZUxd $Rn)>;
2356 multiclass A64I_inttofp<bit o0, string asmop> {
2357 def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>;
2358 def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>;
2359 def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>;
2360 def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>;
2363 defm S : A64I_inttofp<0b0, "scvtf">;
2364 defm U : A64I_inttofp<0b1, "ucvtf">;
2366 def : Pat<(f32 (sint_to_fp i32:$Rn)), (SCVTFsw $Rn)>;
2367 def : Pat<(f32 (sint_to_fp i64:$Rn)), (SCVTFsx $Rn)>;
2368 def : Pat<(f64 (sint_to_fp i32:$Rn)), (SCVTFdw $Rn)>;
2369 def : Pat<(f64 (sint_to_fp i64:$Rn)), (SCVTFdx $Rn)>;
2370 def : Pat<(f32 (uint_to_fp i32:$Rn)), (UCVTFsw $Rn)>;
2371 def : Pat<(f32 (uint_to_fp i64:$Rn)), (UCVTFsx $Rn)>;
2372 def : Pat<(f64 (uint_to_fp i32:$Rn)), (UCVTFdw $Rn)>;
2373 def : Pat<(f64 (uint_to_fp i64:$Rn)), (UCVTFdx $Rn)>;
2375 def FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">;
2376 def FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">;
2377 def FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">;
2378 def FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">;
2380 def : Pat<(i32 (bitconvert f32:$Rn)), (FMOVws $Rn)>;
2381 def : Pat<(f32 (bitconvert i32:$Rn)), (FMOVsw $Rn)>;
2382 def : Pat<(i64 (bitconvert f64:$Rn)), (FMOVxd $Rn)>;
2383 def : Pat<(f64 (bitconvert i64:$Rn)), (FMOVdx $Rn)>;
2385 def lane1_asmoperand : AsmOperandClass {
2387 let RenderMethod = "addImmOperands";
2388 let DiagnosticType = "Lane1";
2391 def lane1 : Operand<i32> {
2392 let ParserMatchClass = lane1_asmoperand;
2393 let PrintMethod = "printBareImmOperand";
2396 let DecoderMethod = "DecodeFMOVLaneInstruction" in {
2397 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
2398 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
2399 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;
2401 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,
2402 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),
2403 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>;
2406 def : InstAlias<"fmov $Rd, $Rn.2d[$Lane]",
2407 (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>;
2409 def : InstAlias<"fmov $Rd.2d[$Lane], $Rn",
2410 (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>;
2412 //===----------------------------------------------------------------------===//
2413 // Floating-point immediate instructions
2414 //===----------------------------------------------------------------------===//
2417 def fpimm_asmoperand : AsmOperandClass {
2418 let Name = "FMOVImm";
2419 let ParserMethod = "ParseFPImmOperand";
2420 let DiagnosticType = "FPImm";
2423 // The MCOperand for these instructions are the encoded 8-bit values.
2424 def SDXF_fpimm : SDNodeXForm<fpimm, [{
2426 A64Imms::isFPImm(N->getValueAPF(), Imm8);
2427 return CurDAG->getTargetConstant(Imm8, MVT::i32);
2430 class fmov_operand<ValueType FT>
2432 PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }],
2434 let PrintMethod = "printFPImmOperand";
2435 let ParserMatchClass = fpimm_asmoperand;
2438 def fmov32_operand : fmov_operand<f32>;
2439 def fmov64_operand : fmov_operand<f64>;
2441 class A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT,
2442 Operand fmov_operand>
2443 : A64I_fpimm<0b0, 0b0, type, 0b00000,
2445 (ins fmov_operand:$Imm8),
2447 [(set VT:$Rd, fmov_operand:$Imm8)],
2450 def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
2451 def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;
2453 //===----------------------------------------------------------------------===//
2454 // Load-register (literal) instructions
2455 //===----------------------------------------------------------------------===//
2456 // Contains: LDR, LDRSW, PRFM
2458 def ldrlit_label_asmoperand : AsmOperandClass {
2459 let Name = "LoadLitLabel";
2460 let RenderMethod = "addLabelOperands<19, 4>";
2461 let DiagnosticType = "Label";
2464 def ldrlit_label : Operand<i64> {
2465 let EncoderMethod = "getLoadLitLabelOpValue";
2467 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
2468 let PrintMethod = "printLabelOperand<19, 4>";
2469 let ParserMatchClass = ldrlit_label_asmoperand;
2470 let OperandType = "OPERAND_PCREL";
2473 // Various instructions take an immediate value (which can always be used),
2474 // where some numbers have a symbolic name to make things easier. These operands
2475 // and the associated functions abstract away the differences.
2476 multiclass namedimm<string prefix, string mapper> {
2477 def _asmoperand : AsmOperandClass {
2478 let Name = "NamedImm" # prefix;
2479 let PredicateMethod = "isUImm";
2480 let RenderMethod = "addImmOperands";
2481 let ParserMethod = "ParseNamedImmOperand<" # mapper # ">";
2482 let DiagnosticType = "NamedImm_" # prefix;
2485 def _op : Operand<i32> {
2486 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
2487 let PrintMethod = "printNamedImmOperand<" # mapper # ">";
2488 let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">";
2492 defm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">;
2494 class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg,
2495 list<dag> patterns = []>
2496 : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
2497 "ldr\t$Rt, $Imm19", patterns, NoItinerary>;
2499 let mayLoad = 1 in {
2500 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
2501 def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>;
2504 def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>;
2505 def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>;
2507 let mayLoad = 1 in {
2508 def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>;
2511 def LDRSWx_lit : A64I_LDRlit<0b10, 0b0,
2513 (ins ldrlit_label:$Imm19),
2514 "ldrsw\t$Rt, $Imm19",
2517 def PRFM_lit : A64I_LDRlit<0b11, 0b0,
2518 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
2519 "prfm\t$Rt, $Imm19",
2523 //===----------------------------------------------------------------------===//
2524 // Load-store exclusive instructions
2525 //===----------------------------------------------------------------------===//
2526 // Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB,
2527 // STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB,
2528 // STLRH, STLR, LDARB, LDARH, LDAR
2530 // Since these instructions have the undefined register bits set to 1 in
2531 // their canonical form, we need a post encoder method to set those bits
2532 // to 1 when encoding these instructions. We do this using the
2533 // fixLoadStoreExclusive function. This function has template parameters:
2535 // fixLoadStoreExclusive<int hasRs, int hasRt2>
2537 // hasRs indicates that the instruction uses the Rs field, so we won't set
2538 // it to 1 (and the same for Rt2). We don't need template parameters for
2539 // the other register fiels since Rt and Rn are always used.
2541 // This operand parses a GPR64xsp register, followed by an optional immediate
2543 def GPR64xsp0_asmoperand : AsmOperandClass {
2544 let Name = "GPR64xsp0";
2545 let PredicateMethod = "isWrappedReg";
2546 let RenderMethod = "addRegOperands";
2547 let ParserMethod = "ParseLSXAddressOperand";
2548 // Diagnostics are provided by ParserMethod
2551 def GPR64xsp0 : RegisterOperand<GPR64xsp> {
2552 let ParserMatchClass = GPR64xsp0_asmoperand;
2555 //===----------------------------------
2556 // Store-exclusive (releasing & normal)
2557 //===----------------------------------
2559 class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2560 dag ins, list<dag> pat,
2561 InstrItinClass itin> :
2562 A64I_LDSTex_stn <size,
2563 opcode{2}, 0, opcode{1}, opcode{0},
2565 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
2568 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
2571 multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
2572 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2573 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2576 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2577 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2580 def _word: A64I_SRexs_impl<0b10, opcode, asmstr,
2581 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2584 def _dword: A64I_SRexs_impl<0b11, opcode, asmstr,
2585 (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2589 defm STXR : A64I_SRex<"stxr", 0b000, "STXR">;
2590 defm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">;
2592 //===----------------------------------
2594 //===----------------------------------
2596 class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2597 dag ins, list<dag> pat,
2598 InstrItinClass itin> :
2599 A64I_LDSTex_tn <size,
2600 opcode{2}, 1, opcode{1}, opcode{0},
2602 !strconcat(asm, "\t$Rt, [$Rn]"),
2605 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2608 multiclass A64I_LRex<string asmstr, bits<3> opcode> {
2609 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2610 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2613 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2614 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2617 def _word: A64I_LRexs_impl<0b10, opcode, asmstr,
2618 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2621 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,
2622 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn),
2626 defm LDXR : A64I_LRex<"ldxr", 0b000>;
2627 defm LDAXR : A64I_LRex<"ldaxr", 0b001>;
2628 defm LDAR : A64I_LRex<"ldar", 0b101>;
2630 class acquiring_load<PatFrag base>
2631 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
2632 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2633 return Ordering == Acquire || Ordering == SequentiallyConsistent;
2636 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
2637 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
2638 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
2639 def atomic_load_acquire_64 : acquiring_load<atomic_load_64>;
2641 def : Pat<(atomic_load_acquire_8 i64:$Rn), (LDAR_byte $Rn)>;
2642 def : Pat<(atomic_load_acquire_16 i64:$Rn), (LDAR_hword $Rn)>;
2643 def : Pat<(atomic_load_acquire_32 i64:$Rn), (LDAR_word $Rn)>;
2644 def : Pat<(atomic_load_acquire_64 i64:$Rn), (LDAR_dword $Rn)>;
2646 //===----------------------------------
2647 // Store-release (no exclusivity)
2648 //===----------------------------------
2650 class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2651 dag ins, list<dag> pat,
2652 InstrItinClass itin> :
2653 A64I_LDSTex_tn <size,
2654 opcode{2}, 0, opcode{1}, opcode{0},
2656 !strconcat(asm, "\t$Rt, [$Rn]"),
2659 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2662 class releasing_store<PatFrag base>
2663 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
2664 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2665 return Ordering == Release || Ordering == SequentiallyConsistent;
2668 def atomic_store_release_8 : releasing_store<atomic_store_8>;
2669 def atomic_store_release_16 : releasing_store<atomic_store_16>;
2670 def atomic_store_release_32 : releasing_store<atomic_store_32>;
2671 def atomic_store_release_64 : releasing_store<atomic_store_64>;
2673 multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> {
2674 def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2675 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2676 [(atomic_store_release_8 i64:$Rn, i32:$Rt)],
2679 def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2680 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2681 [(atomic_store_release_16 i64:$Rn, i32:$Rt)],
2684 def _word: A64I_SLexs_impl<0b10, opcode, asmstr,
2685 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2686 [(atomic_store_release_32 i64:$Rn, i32:$Rt)],
2689 def _dword: A64I_SLexs_impl<0b11, opcode, asmstr,
2690 (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2691 [(atomic_store_release_64 i64:$Rn, i64:$Rt)],
2695 defm STLR : A64I_SLex<"stlr", 0b101, "STLR">;
2697 //===----------------------------------
2698 // Store-exclusive pair (releasing & normal)
2699 //===----------------------------------
2701 class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2702 dag ins, list<dag> pat,
2703 InstrItinClass itin> :
2704 A64I_LDSTex_stt2n <size,
2705 opcode{2}, 0, opcode{1}, opcode{0},
2707 !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"),
2713 multiclass A64I_SPex<string asmstr, bits<3> opcode> {
2714 def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs),
2715 (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2,
2719 def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs),
2720 (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2,
2725 defm STXP : A64I_SPex<"stxp", 0b010>;
2726 defm STLXP : A64I_SPex<"stlxp", 0b011>;
2728 //===----------------------------------
2729 // Load-exclusive pair (acquiring & normal)
2730 //===----------------------------------
2732 class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2733 dag ins, list<dag> pat,
2734 InstrItinClass itin> :
2735 A64I_LDSTex_tt2n <size,
2736 opcode{2}, 1, opcode{1}, opcode{0},
2738 !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"),
2741 let DecoderMethod = "DecodeLoadPairExclusiveInstruction";
2742 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
2745 multiclass A64I_LPex<string asmstr, bits<3> opcode> {
2746 def _word: A64I_LPexs_impl<0b10, opcode, asmstr,
2747 (outs GPR32:$Rt, GPR32:$Rt2),
2748 (ins GPR64xsp0:$Rn),
2751 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
2752 (outs GPR64:$Rt, GPR64:$Rt2),
2753 (ins GPR64xsp0:$Rn),
2757 defm LDXP : A64I_LPex<"ldxp", 0b010>;
2758 defm LDAXP : A64I_LPex<"ldaxp", 0b011>;
2760 //===----------------------------------------------------------------------===//
2761 // Load-store register (unscaled immediate) instructions
2762 //===----------------------------------------------------------------------===//
2763 // Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM
2767 //===----------------------------------------------------------------------===//
2768 // Load-store register (register offset) instructions
2769 //===----------------------------------------------------------------------===//
2770 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2774 //===----------------------------------------------------------------------===//
2775 // Load-store register (unsigned immediate) instructions
2776 //===----------------------------------------------------------------------===//
2777 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2781 //===----------------------------------------------------------------------===//
2782 // Load-store register (immediate post-indexed) instructions
2783 //===----------------------------------------------------------------------===//
2784 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2788 //===----------------------------------------------------------------------===//
2789 // Load-store register (immediate pre-indexed) instructions
2790 //===----------------------------------------------------------------------===//
2791 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2793 // Note that patterns are much later on in a completely separate section (they
2794 // need ADRPxi to be defined).
2796 //===-------------------------------
2797 // 1. Various operands needed
2798 //===-------------------------------
2800 //===-------------------------------
2801 // 1.1 Unsigned 12-bit immediate operands
2802 //===-------------------------------
2803 // The addressing mode for these instructions consists of an unsigned 12-bit
2804 // immediate which is scaled by the size of the memory access.
2806 // We represent this in the MC layer by two operands:
2807 // 1. A base register.
2808 // 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]"
2809 // would have '1' in this field.
2810 // This means that separate functions are needed for converting representations
2811 // which *are* aware of the intended access size.
2813 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
2814 // know the access size via some means. An isolated operand does not have this
2815 // information unless told from here, which means we need separate tablegen
2816 // Operands for each access size. This multiclass takes care of instantiating
2817 // the correct template functions in the rest of the backend.
2819 //===-------------------------------
2820 // 1.1 Unsigned 12-bit immediate operands
2821 //===-------------------------------
2823 multiclass offsets_uimm12<int MemSize, string prefix> {
2824 def uimm12_asmoperand : AsmOperandClass {
2825 let Name = "OffsetUImm12_" # MemSize;
2826 let PredicateMethod = "isOffsetUImm12<" # MemSize # ">";
2827 let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">";
2828 let DiagnosticType = "LoadStoreUImm12_" # MemSize;
2831 // Pattern is really no more than an ImmLeaf, but predicated on MemSize which
2832 // complicates things beyond TableGen's ken.
2833 def uimm12 : Operand<i64>,
2834 ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> {
2835 let ParserMatchClass
2836 = !cast<AsmOperandClass>(prefix # uimm12_asmoperand);
2838 let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">";
2839 let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">";
2843 defm byte_ : offsets_uimm12<1, "byte_">;
2844 defm hword_ : offsets_uimm12<2, "hword_">;
2845 defm word_ : offsets_uimm12<4, "word_">;
2846 defm dword_ : offsets_uimm12<8, "dword_">;
2847 defm qword_ : offsets_uimm12<16, "qword_">;
2849 //===-------------------------------
2850 // 1.1 Signed 9-bit immediate operands
2851 //===-------------------------------
2853 // The MCInst is expected to store the bit-wise encoding of the value,
2854 // which amounts to lopping off the extended sign bits.
2855 def SDXF_simm9 : SDNodeXForm<imm, [{
2856 return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32);
2859 def simm9_asmoperand : AsmOperandClass {
2861 let PredicateMethod = "isSImm<9>";
2862 let RenderMethod = "addSImmOperands<9>";
2863 let DiagnosticType = "LoadStoreSImm9";
2866 def simm9 : Operand<i64>,
2867 ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }],
2869 let PrintMethod = "printOffsetSImm9Operand";
2870 let ParserMatchClass = simm9_asmoperand;
2874 //===-------------------------------
2875 // 1.3 Register offset extensions
2876 //===-------------------------------
2878 // The assembly-syntax for these addressing-modes is:
2879 // [<Xn|SP>, <R><m> {, <extend> {<amount>}}]
2881 // The essential semantics are:
2882 // + <amount> is a shift: #<log(transfer size)> or #0
2883 // + <R> can be W or X.
2884 // + If <R> is W, <extend> can be UXTW or SXTW
2885 // + If <R> is X, <extend> can be LSL or SXTX
2887 // The trickiest of those constraints is that Rm can be either GPR32 or GPR64,
2888 // which will need separate instructions for LLVM type-consistency. We'll also
2889 // need separate operands, of course.
2890 multiclass regexts<int MemSize, int RmSize, RegisterClass GPR,
2891 string Rm, string prefix> {
2892 def regext_asmoperand : AsmOperandClass {
2893 let Name = "AddrRegExtend_" # MemSize # "_" # Rm;
2894 let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">";
2895 let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">";
2896 let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize;
2899 def regext : Operand<i64> {
2901 = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">";
2903 let DecoderMethod = "DecodeAddrRegExtendOperand";
2904 let ParserMatchClass
2905 = !cast<AsmOperandClass>(prefix # regext_asmoperand);
2909 multiclass regexts_wx<int MemSize, string prefix> {
2910 // Rm is an X-register if LSL or SXTX are specified as the shift.
2911 defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">;
2913 // Rm is a W-register if UXTW or SXTW are specified as the shift.
2914 defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">;
2917 defm byte_ : regexts_wx<1, "byte_">;
2918 defm hword_ : regexts_wx<2, "hword_">;
2919 defm word_ : regexts_wx<4, "word_">;
2920 defm dword_ : regexts_wx<8, "dword_">;
2921 defm qword_ : regexts_wx<16, "qword_">;
2924 //===------------------------------
2925 // 2. The instructions themselves.
2926 //===------------------------------
2928 // We have the following instructions to implement:
2929 // | | B | H | W | X |
2930 // |-----------------+-------+-------+-------+--------|
2931 // | unsigned str | STRB | STRH | STR | STR |
2932 // | unsigned ldr | LDRB | LDRH | LDR | LDR |
2933 // | signed ldr to W | LDRSB | LDRSH | - | - |
2934 // | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) |
2936 // This will instantiate the LDR/STR instructions you'd expect to use for an
2937 // unsigned datatype (first two rows above) or floating-point register, which is
2938 // reasonably uniform across all access sizes.
2941 //===------------------------------
2942 // 2.1 Regular instructions
2943 //===------------------------------
2945 // This class covers the basic unsigned or irrelevantly-signed loads and stores,
2946 // to general-purpose and floating-point registers.
2948 class AddrParams<string prefix> {
2949 Operand uimm12 = !cast<Operand>(prefix # "_uimm12");
2951 Operand regextWm = !cast<Operand>(prefix # "_Wm_regext");
2952 Operand regextXm = !cast<Operand>(prefix # "_Xm_regext");
2955 def byte_addrparams : AddrParams<"byte">;
2956 def hword_addrparams : AddrParams<"hword">;
2957 def word_addrparams : AddrParams<"word">;
2958 def dword_addrparams : AddrParams<"dword">;
2959 def qword_addrparams : AddrParams<"qword">;
2961 multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
2962 bit high_opc, string asmsuffix,
2963 RegisterClass GPR, AddrParams params> {
2964 // Unsigned immediate
2965 def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
2966 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
2967 "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
2971 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
2972 (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2974 def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},
2975 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
2976 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
2980 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
2981 (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2983 // Register offset (four of these: load/store and Wm/Xm).
2984 let mayLoad = 1 in {
2985 def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0,
2987 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
2988 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2991 def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1,
2993 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
2994 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2997 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",
2998 (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
3001 let mayStore = 1 in {
3002 def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0,
3003 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
3004 params.regextWm:$Ext),
3005 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3008 def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1,
3009 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm,
3010 params.regextXm:$Ext),
3011 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3014 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]",
3015 (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn,
3018 // Unaligned immediate
3019 def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
3020 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3021 "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3025 def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
3026 (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3028 def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},
3029 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3030 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3034 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
3035 (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3038 def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0},
3039 (outs GPR64xsp:$Rn_wb),
3040 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3041 "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3043 let Constraints = "$Rn = $Rn_wb";
3046 // Decoder only needed for unpredictability checking (FIXME).
3047 let DecoderMethod = "DecodeSingleIndexedInstruction";
3050 def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1},
3051 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3052 (ins GPR64xsp:$Rn, simm9:$SImm9),
3053 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3056 let Constraints = "$Rn = $Rn_wb";
3057 let DecoderMethod = "DecodeSingleIndexedInstruction";
3061 def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0},
3062 (outs GPR64xsp:$Rn_wb),
3063 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3064 "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3066 let Constraints = "$Rn = $Rn_wb";
3069 // Decoder only needed for unpredictability checking (FIXME).
3070 let DecoderMethod = "DecodeSingleIndexedInstruction";
3073 def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1},
3074 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3075 (ins GPR64xsp:$Rn, simm9:$SImm9),
3076 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3079 let Constraints = "$Rn = $Rn_wb";
3080 let DecoderMethod = "DecodeSingleIndexedInstruction";
3085 // STRB/LDRB: First define the instructions
3087 : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>;
3091 : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>;
3094 // STR/LDR to/from a W register
3096 : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>;
3098 // STR/LDR to/from an X register
3100 : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>;
3102 // STR/LDR to/from a B register
3104 : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>;
3106 // STR/LDR to/from an H register
3108 : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>;
3110 // STR/LDR to/from an S register
3112 : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>;
3113 // STR/LDR to/from a D register
3115 : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>;
3116 // STR/LDR to/from a Q register
3118 : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128,
3121 //===------------------------------
3123 //===------------------------------
3125 // Byte and half-word signed loads can both go into either an X or a W register,
3126 // so it's worth factoring out. Signed word loads don't fit because there is no
3128 multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
3131 def w : A64I_LSunsigimm<size, 0b0, 0b11,
3133 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3134 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3138 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3139 (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3141 def x : A64I_LSunsigimm<size, 0b0, 0b10,
3143 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3144 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3148 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3149 (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3152 let mayLoad = 1 in {
3153 def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0,
3155 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3156 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3159 def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1,
3161 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3162 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3165 def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0,
3167 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3168 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3171 def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1,
3173 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3174 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3177 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3178 (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,
3181 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3182 (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn,
3186 let mayLoad = 1 in {
3188 def w_U : A64I_LSunalimm<size, 0b0, 0b11,
3190 (ins GPR64xsp:$Rn, simm9:$SImm9),
3191 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3194 def x_U : A64I_LSunalimm<size, 0b0, 0b10,
3196 (ins GPR64xsp:$Rn, simm9:$SImm9),
3197 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3202 def w_PostInd : A64I_LSpostind<size, 0b0, 0b11,
3203 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3204 (ins GPR64xsp:$Rn, simm9:$SImm9),
3205 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3207 let Constraints = "$Rn = $Rn_wb";
3208 let DecoderMethod = "DecodeSingleIndexedInstruction";
3211 def x_PostInd : A64I_LSpostind<size, 0b0, 0b10,
3212 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3213 (ins GPR64xsp:$Rn, simm9:$SImm9),
3214 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3216 let Constraints = "$Rn = $Rn_wb";
3217 let DecoderMethod = "DecodeSingleIndexedInstruction";
3221 def w_PreInd : A64I_LSpreind<size, 0b0, 0b11,
3222 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3223 (ins GPR64xsp:$Rn, simm9:$SImm9),
3224 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3226 let Constraints = "$Rn = $Rn_wb";
3227 let DecoderMethod = "DecodeSingleIndexedInstruction";
3230 def x_PreInd : A64I_LSpreind<size, 0b0, 0b10,
3231 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3232 (ins GPR64xsp:$Rn, simm9:$SImm9),
3233 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3235 let Constraints = "$Rn = $Rn_wb";
3236 let DecoderMethod = "DecodeSingleIndexedInstruction";
3238 } // let mayLoad = 1
3242 defm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">;
3244 defm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">;
3246 // LDRSW: load a 32-bit register, sign-extending to 64-bits.
3248 : A64I_LSunsigimm<0b10, 0b0, 0b10,
3250 (ins GPR64xsp:$Rn, word_uimm12:$UImm12),
3251 "ldrsw\t$Rt, [$Rn, $UImm12]",
3255 def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3257 let mayLoad = 1 in {
3258 def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0,
3260 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
3261 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3264 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,
3266 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),
3267 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3270 def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",
3271 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;
3275 : A64I_LSunalimm<0b10, 0b0, 0b10,
3277 (ins GPR64xsp:$Rn, simm9:$SImm9),
3278 "ldursw\t$Rt, [$Rn, $SImm9]",
3282 def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3285 : A64I_LSpostind<0b10, 0b0, 0b10,
3286 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3287 (ins GPR64xsp:$Rn, simm9:$SImm9),
3288 "ldrsw\t$Rt, [$Rn], $SImm9",
3291 let Constraints = "$Rn = $Rn_wb";
3292 let DecoderMethod = "DecodeSingleIndexedInstruction";
3295 def LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10,
3296 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3297 (ins GPR64xsp:$Rn, simm9:$SImm9),
3298 "ldrsw\t$Rt, [$Rn, $SImm9]!",
3301 let Constraints = "$Rn = $Rn_wb";
3302 let DecoderMethod = "DecodeSingleIndexedInstruction";
3305 //===------------------------------
3306 // 2.4 Prefetch operations
3307 //===------------------------------
3309 def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
3310 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
3311 "prfm\t$Rt, [$Rn, $UImm12]",
3315 def : InstAlias<"prfm $Rt, [$Rn]",
3316 (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3318 let mayLoad = 1 in {
3319 def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs),
3320 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3321 GPR32:$Rm, dword_Wm_regext:$Ext),
3322 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3324 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),
3325 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3326 GPR64:$Rm, dword_Xm_regext:$Ext),
3327 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3331 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
3332 (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn,
3336 def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
3337 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3338 "prfum\t$Rt, [$Rn, $SImm9]",
3342 def : InstAlias<"prfum $Rt, [$Rn]",
3343 (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3345 //===----------------------------------------------------------------------===//
3346 // Load-store register (unprivileged) instructions
3347 //===----------------------------------------------------------------------===//
3348 // Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH
3350 // These instructions very much mirror the "unscaled immediate" loads, but since
3351 // there are no floating-point variants we need to split them out into their own
3352 // section to avoid instantiation of "ldtr d0, [sp]" etc.
3354 multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR,
3356 def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,
3357 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3358 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3363 def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]",
3364 (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3366 def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,
3367 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3368 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3373 def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]",
3374 (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3378 // STTRB/LDTRB: First define the instructions
3379 defm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">;
3382 defm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">;
3384 // STTR/LDTR to/from a W register
3385 defm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">;
3387 // STTR/LDTR to/from an X register
3388 defm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">;
3390 // Now a class for the signed instructions that can go to either 32 or 64
3392 multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> {
3393 let mayLoad = 1 in {
3394 def w : A64I_LSunpriv<size, 0b0, 0b11,
3396 (ins GPR64xsp:$Rn, simm9:$SImm9),
3397 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3400 def x : A64I_LSunpriv<size, 0b0, 0b10,
3402 (ins GPR64xsp:$Rn, simm9:$SImm9),
3403 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3407 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3408 (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3410 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3411 (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3416 defm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">;
3418 defm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">;
3420 // And finally LDTRSW which only goes to 64 bits.
3421 def LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10,
3423 (ins GPR64xsp:$Rn, simm9:$SImm9),
3424 "ldtrsw\t$Rt, [$Rn, $SImm9]",
3428 def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3430 //===----------------------------------------------------------------------===//
3431 // Load-store register pair (offset) instructions
3432 //===----------------------------------------------------------------------===//
3436 //===----------------------------------------------------------------------===//
3437 // Load-store register pair (post-indexed) instructions
3438 //===----------------------------------------------------------------------===//
3439 // Contains: STP, LDP, LDPSW
3443 //===----------------------------------------------------------------------===//
3444 // Load-store register pair (pre-indexed) instructions
3445 //===----------------------------------------------------------------------===//
3446 // Contains: STP, LDP, LDPSW
3450 //===----------------------------------------------------------------------===//
3451 // Load-store non-temporal register pair (offset) instructions
3452 //===----------------------------------------------------------------------===//
3453 // Contains: STNP, LDNP
3456 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
3457 // know the access size via some means. An isolated operand does not have this
3458 // information unless told from here, which means we need separate tablegen
3459 // Operands for each access size. This multiclass takes care of instantiating
3460 // the correct template functions in the rest of the backend.
3462 multiclass offsets_simm7<string MemSize, string prefix> {
3463 // The bare signed 7-bit immediate is used in post-indexed instructions, but
3464 // because of the scaling performed a generic "simm7" operand isn't
3465 // appropriate here either.
3466 def simm7_asmoperand : AsmOperandClass {
3467 let Name = "SImm7_Scaled" # MemSize;
3468 let PredicateMethod = "isSImm7Scaled<" # MemSize # ">";
3469 let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">";
3470 let DiagnosticType = "LoadStoreSImm7_" # MemSize;
3473 def simm7 : Operand<i64> {
3474 let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">";
3475 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand");
3479 defm word_ : offsets_simm7<"4", "word_">;
3480 defm dword_ : offsets_simm7<"8", "dword_">;
3481 defm qword_ : offsets_simm7<"16", "qword_">;
3483 multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
3484 Operand simm7, string prefix> {
3485 def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),
3486 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3487 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3489 let DecoderMethod = "DecodeLDSTPairInstruction";
3491 def : InstAlias<"stp $Rt, $Rt2, [$Rn]",
3492 (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt,
3493 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3495 def _LDR : A64I_LSPoffset<opc, v, 0b1,
3496 (outs SomeReg:$Rt, SomeReg:$Rt2),
3497 (ins GPR64xsp:$Rn, simm7:$SImm7),
3498 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3500 let DecoderMethod = "DecodeLDSTPairInstruction";
3502 def : InstAlias<"ldp $Rt, $Rt2, [$Rn]",
3503 (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt,
3504 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3506 def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0,
3507 (outs GPR64xsp:$Rn_wb),
3508 (ins SomeReg:$Rt, SomeReg:$Rt2,
3511 "stp\t$Rt, $Rt2, [$Rn], $SImm7",
3514 let Constraints = "$Rn = $Rn_wb";
3516 // Decoder only needed for unpredictability checking (FIXME).
3517 let DecoderMethod = "DecodeLDSTPairInstruction";
3520 def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1,
3521 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3522 (ins GPR64xsp:$Rn, simm7:$SImm7),
3523 "ldp\t$Rt, $Rt2, [$Rn], $SImm7",
3526 let Constraints = "$Rn = $Rn_wb";
3527 let DecoderMethod = "DecodeLDSTPairInstruction";
3530 def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
3531 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3532 "stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3535 let Constraints = "$Rn = $Rn_wb";
3536 let DecoderMethod = "DecodeLDSTPairInstruction";
3539 def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1,
3540 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3541 (ins GPR64xsp:$Rn, simm7:$SImm7),
3542 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3545 let Constraints = "$Rn = $Rn_wb";
3546 let DecoderMethod = "DecodeLDSTPairInstruction";
3549 def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
3550 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3551 "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3553 let DecoderMethod = "DecodeLDSTPairInstruction";
3555 def : InstAlias<"stnp $Rt, $Rt2, [$Rn]",
3556 (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt,
3557 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3559 def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,
3560 (outs SomeReg:$Rt, SomeReg:$Rt2),
3561 (ins GPR64xsp:$Rn, simm7:$SImm7),
3562 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3564 let DecoderMethod = "DecodeLDSTPairInstruction";
3566 def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]",
3567 (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt,
3568 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3573 defm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">;
3574 defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">;
3575 defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">;
3576 defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">;
3577 defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7,
3581 def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
3582 (outs GPR64:$Rt, GPR64:$Rt2),
3583 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3584 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3586 let DecoderMethod = "DecodeLDSTPairInstruction";
3588 def : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]",
3589 (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>;
3591 def LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1,
3592 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3593 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3594 "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
3597 let Constraints = "$Rn = $Rn_wb";
3598 let DecoderMethod = "DecodeLDSTPairInstruction";
3601 def LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1,
3602 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3603 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3604 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
3607 let Constraints = "$Rn = $Rn_wb";
3608 let DecoderMethod = "DecodeLDSTPairInstruction";
3611 //===----------------------------------------------------------------------===//
3612 // Logical (immediate) instructions
3613 //===----------------------------------------------------------------------===//
3614 // Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV
3616 multiclass logical_imm_operands<string prefix, string note,
3617 int size, ValueType VT> {
3618 def _asmoperand : AsmOperandClass {
3619 let Name = "LogicalImm" # note # size;
3620 let PredicateMethod = "isLogicalImm" # note # "<" # size # ">";
3621 let RenderMethod = "addLogicalImmOperands<" # size # ">";
3622 let DiagnosticType = "LogicalSecondSource";
3626 : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> {
3627 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3628 let PrintMethod = "printLogicalImmOperand<" # size # ">";
3629 let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">";
3633 defm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>;
3634 defm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>;
3636 // The mov versions only differ in assembly parsing, where they
3637 // exclude values representable with either MOVZ or MOVN.
3638 defm logical_imm32_mov
3639 : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>;
3640 defm logical_imm64_mov
3641 : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>;
3644 multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> {
3645 def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd),
3646 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3647 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3649 (opnode i32:$Rn, logical_imm32_operand:$Imm))],
3652 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
3653 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3654 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3656 (opnode i64:$Rn, logical_imm64_operand:$Imm))],
3660 defm AND : A64I_logimmSizes<0b00, "and", and>;
3661 defm ORR : A64I_logimmSizes<0b01, "orr", or>;
3662 defm EOR : A64I_logimmSizes<0b10, "eor", xor>;
3664 let Defs = [NZCV] in {
3665 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
3666 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3667 "ands\t$Rd, $Rn, $Imm",
3670 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),
3671 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3672 "ands\t$Rd, $Rn, $Imm",
3677 def : InstAlias<"tst $Rn, $Imm",
3678 (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>;
3679 def : InstAlias<"tst $Rn, $Imm",
3680 (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>;
3681 def : InstAlias<"mov $Rd, $Imm",
3682 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>;
3683 def : InstAlias<"mov $Rd, $Imm",
3684 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>;
3686 //===----------------------------------------------------------------------===//
3687 // Logical (shifted register) instructions
3688 //===----------------------------------------------------------------------===//
3689 // Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV
3691 // Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS"
3692 // behaves differently for unsigned comparisons, so we defensively only allow
3693 // signed or n/a as the operand. In practice "unsigned greater than 0" is "not
3694 // equal to 0" and LLVM gives us this.
3695 def signed_cond : PatLeaf<(cond), [{
3696 return !isUnsignedIntSetCC(N->get());
3700 // These instructions share their "shift" operands with add/sub (shifted
3701 // register instructions). They are defined there.
3703 // N.b. the commutable parameter is just !N. It will be first against the wall
3704 // when the revolution comes.
3705 multiclass logical_shifts<string prefix, bit sf, bits<2> opc,
3706 bit N, bit commutable,
3707 string asmop, SDPatternOperator opfrag, ValueType ty,
3708 RegisterClass GPR, list<Register> defs> {
3709 let isCommutable = commutable, Defs = defs in {
3710 def _lsl : A64I_logicalshift<sf, opc, 0b00, N,
3712 (ins GPR:$Rn, GPR:$Rm,
3713 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3714 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3715 [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
3716 !cast<Operand>("lsl_operand_" # ty):$Imm6))
3720 def _lsr : A64I_logicalshift<sf, opc, 0b01, N,
3722 (ins GPR:$Rn, GPR:$Rm,
3723 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3724 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3725 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
3726 !cast<Operand>("lsr_operand_" # ty):$Imm6))
3730 def _asr : A64I_logicalshift<sf, opc, 0b10, N,
3732 (ins GPR:$Rn, GPR:$Rm,
3733 !cast<Operand>("asr_operand_" # ty):$Imm6),
3734 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3735 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
3736 !cast<Operand>("asr_operand_" # ty):$Imm6))
3740 def _ror : A64I_logicalshift<sf, opc, 0b11, N,
3742 (ins GPR:$Rn, GPR:$Rm,
3743 !cast<Operand>("ror_operand_" # ty):$Imm6),
3744 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3745 [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm,
3746 !cast<Operand>("ror_operand_" # ty):$Imm6))
3752 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
3753 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
3756 def : Pat<(opfrag ty:$Rn, ty:$Rm),
3757 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
3760 multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable,
3761 string asmop, SDPatternOperator opfrag,
3762 list<Register> defs> {
3763 defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N,
3764 commutable, asmop, opfrag, i64, GPR64, defs>;
3765 defm www : logical_shifts<prefix # "www", 0b0, opc, N,
3766 commutable, asmop, opfrag, i32, GPR32, defs>;
3770 defm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>;
3771 defm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>;
3772 defm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>;
3773 defm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands",
3774 PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs),
3775 [{ (void)N; return false; }]>,
3778 defm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic",
3779 PatFrag<(ops node:$lhs, node:$rhs),
3780 (and node:$lhs, (not node:$rhs))>, []>;
3781 defm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn",
3782 PatFrag<(ops node:$lhs, node:$rhs),
3783 (or node:$lhs, (not node:$rhs))>, []>;
3784 defm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon",
3785 PatFrag<(ops node:$lhs, node:$rhs),
3786 (xor node:$lhs, (not node:$rhs))>, []>;
3787 defm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics",
3788 PatFrag<(ops node:$lhs, node:$rhs),
3789 (and node:$lhs, (not node:$rhs)),
3790 [{ (void)N; return false; }]>,
3793 multiclass tst_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
3794 let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in {
3795 def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0,
3797 (ins GPR:$Rn, GPR:$Rm,
3798 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3799 "tst\t$Rn, $Rm, $Imm6",
3800 [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm,
3801 !cast<Operand>("lsl_operand_" # ty):$Imm6)),
3806 def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0,
3808 (ins GPR:$Rn, GPR:$Rm,
3809 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3810 "tst\t$Rn, $Rm, $Imm6",
3811 [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm,
3812 !cast<Operand>("lsr_operand_" # ty):$Imm6)),
3816 def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0,
3818 (ins GPR:$Rn, GPR:$Rm,
3819 !cast<Operand>("asr_operand_" # ty):$Imm6),
3820 "tst\t$Rn, $Rm, $Imm6",
3821 [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm,
3822 !cast<Operand>("asr_operand_" # ty):$Imm6)),
3826 def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0,
3828 (ins GPR:$Rn, GPR:$Rm,
3829 !cast<Operand>("ror_operand_" # ty):$Imm6),
3830 "tst\t$Rn, $Rm, $Imm6",
3831 [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm,
3832 !cast<Operand>("ror_operand_" # ty):$Imm6)),
3837 def _noshift : InstAlias<"tst $Rn, $Rm",
3838 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3840 def : Pat<(A64setcc (and ty:$Rn, ty:$Rm), 0, signed_cond),
3841 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
3844 defm TSTxx : tst_shifts<"TSTxx", 0b1, i64, GPR64>;
3845 defm TSTww : tst_shifts<"TSTww", 0b0, i32, GPR32>;
3848 multiclass mvn_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
3849 let isCommutable = 0, Rn = 0b11111 in {
3850 def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1,
3853 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3854 "mvn\t$Rd, $Rm, $Imm6",
3855 [(set ty:$Rd, (not (shl ty:$Rm,
3856 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
3860 def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1,
3863 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3864 "mvn\t$Rd, $Rm, $Imm6",
3865 [(set ty:$Rd, (not (srl ty:$Rm,
3866 !cast<Operand>("lsr_operand_" # ty):$Imm6)))],
3869 def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1,
3872 !cast<Operand>("asr_operand_" # ty):$Imm6),
3873 "mvn\t$Rd, $Rm, $Imm6",
3874 [(set ty:$Rd, (not (sra ty:$Rm,
3875 !cast<Operand>("asr_operand_" # ty):$Imm6)))],
3878 def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1,
3881 !cast<Operand>("ror_operand_" # ty):$Imm6),
3882 "mvn\t$Rd, $Rm, $Imm6",
3883 [(set ty:$Rd, (not (rotr ty:$Rm,
3884 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
3888 def _noshift : InstAlias<"mvn $Rn, $Rm",
3889 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3891 def : Pat<(not ty:$Rm),
3892 (!cast<Instruction>(prefix # "_lsl") $Rm, 0)>;
3895 defm MVNxx : mvn_shifts<"MVNxx", 0b1, i64, GPR64>;
3896 defm MVNww : mvn_shifts<"MVNww", 0b0, i32, GPR32>;
3898 def MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
3899 def MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
3901 //===----------------------------------------------------------------------===//
3902 // Move wide (immediate) instructions
3903 //===----------------------------------------------------------------------===//
3904 // Contains: MOVN, MOVZ, MOVK + MOV aliases
3906 // A wide variety of different relocations are needed for variants of these
3907 // instructions, so it turns out that we need a different operand for all of
3909 multiclass movw_operands<string prefix, string instname, int width> {
3910 def _imm_asmoperand : AsmOperandClass {
3911 let Name = instname # width # "Shifted" # shift;
3912 let PredicateMethod = "is" # instname # width # "Imm";
3913 let RenderMethod = "addMoveWideImmOperands";
3914 let ParserMethod = "ParseImmWithLSLOperand";
3915 let DiagnosticType = "MOVWUImm16";
3918 def _imm : Operand<i64> {
3919 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand");
3920 let PrintMethod = "printMoveWideImmOperand";
3921 let EncoderMethod = "getMoveWideImmOpValue";
3922 let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">";
3924 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
3928 defm movn32 : movw_operands<"movn32", "MOVN", 32>;
3929 defm movn64 : movw_operands<"movn64", "MOVN", 64>;
3930 defm movz32 : movw_operands<"movz32", "MOVZ", 32>;
3931 defm movz64 : movw_operands<"movz64", "MOVZ", 64>;
3932 defm movk32 : movw_operands<"movk32", "MOVK", 32>;
3933 defm movk64 : movw_operands<"movk64", "MOVK", 64>;
3935 multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit,
3938 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
3939 !strconcat(asmop, "\t$Rd, $FullImm"),
3942 let UImm16 = FullImm{15-0};
3943 let Shift = FullImm{17-16};
3946 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
3947 !strconcat(asmop, "\t$Rd, $FullImm"),
3950 let UImm16 = FullImm{15-0};
3951 let Shift = FullImm{17-16};
3955 let isMoveImm = 1, isReMaterializable = 1,
3956 isAsCheapAsAMove = 1, hasSideEffects = 0 in {
3957 defm MOVN : A64I_movwSizes<0b00, "movn",
3958 (ins movn32_imm:$FullImm),
3959 (ins movn64_imm:$FullImm)>;
3961 // Some relocations are able to convert between a MOVZ and a MOVN. If these
3962 // are applied the instruction must be emitted with the corresponding bits as
3963 // 0, which means a MOVZ needs to override that bit from the default.
3964 let PostEncoderMethod = "fixMOVZ" in
3965 defm MOVZ : A64I_movwSizes<0b10, "movz",
3966 (ins movz32_imm:$FullImm),
3967 (ins movz64_imm:$FullImm)>;
3970 let Constraints = "$src = $Rd" in
3971 defm MOVK : A64I_movwSizes<0b11, "movk",
3972 (ins GPR32:$src, movk32_imm:$FullImm),
3973 (ins GPR64:$src, movk64_imm:$FullImm)>;
3976 // And now the "MOV" aliases. These also need their own operands because what
3977 // they accept is completely different to what the base instructions accept.
3978 multiclass movalias_operand<string prefix, string basename,
3979 string immpredicate, int width> {
3980 def _asmoperand : AsmOperandClass {
3981 let Name = basename # width # "MovAlias";
3983 = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">";
3985 = "addMoveWideMovAliasOperands<" # width # ", "
3986 # "A64Imms::" # immpredicate # ">";
3989 def _movimm : Operand<i64> {
3990 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3992 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
3996 defm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>;
3997 defm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>;
3998 defm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>;
3999 defm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>;
4001 // FIXME: these are officially canonical aliases, but TableGen is too limited to
4002 // print them at the moment. I believe in this case an "AliasPredicate" method
4003 // will need to be implemented. to allow it, as well as the more generally
4004 // useful handling of non-register, non-constant operands.
4005 class movalias<Instruction INST, RegisterClass GPR, Operand operand>
4006 : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>;
4008 def : movalias<MOVZwii, GPR32, movz32_movimm>;
4009 def : movalias<MOVZxii, GPR64, movz64_movimm>;
4010 def : movalias<MOVNwii, GPR32, movn32_movimm>;
4011 def : movalias<MOVNxii, GPR64, movn64_movimm>;
4013 def movw_addressref_g0 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<0>">;
4014 def movw_addressref_g1 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<1>">;
4015 def movw_addressref_g2 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<2>">;
4016 def movw_addressref_g3 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<3>">;
4018 def : Pat<(A64WrapperLarge movw_addressref_g3:$G3, movw_addressref_g2:$G2,
4019 movw_addressref_g1:$G1, movw_addressref_g0:$G0),
4020 (MOVKxii (MOVKxii (MOVKxii (MOVZxii movw_addressref_g3:$G3),
4021 movw_addressref_g2:$G2),
4022 movw_addressref_g1:$G1),
4023 movw_addressref_g0:$G0)>;
4025 //===----------------------------------------------------------------------===//
4026 // PC-relative addressing instructions
4027 //===----------------------------------------------------------------------===//
4028 // Contains: ADR, ADRP
4030 def adr_label : Operand<i64> {
4031 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>";
4033 // This label is a 21-bit offset from PC, unscaled
4034 let PrintMethod = "printLabelOperand<21, 1>";
4035 let ParserMatchClass = label_asmoperand<21, 1>;
4036 let OperandType = "OPERAND_PCREL";
4039 def adrp_label_asmoperand : AsmOperandClass {
4040 let Name = "AdrpLabel";
4041 let RenderMethod = "addLabelOperands<21, 4096>";
4042 let DiagnosticType = "Label";
4045 def adrp_label : Operand<i64> {
4046 let EncoderMethod = "getAdrpLabelOpValue";
4048 // This label is a 21-bit offset from PC, scaled by the page-size: 4096.
4049 let PrintMethod = "printLabelOperand<21, 4096>";
4050 let ParserMatchClass = adrp_label_asmoperand;
4051 let OperandType = "OPERAND_PCREL";
4054 let hasSideEffects = 0 in {
4055 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
4056 "adr\t$Rd, $Label", [], NoItinerary>;
4058 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),
4059 "adrp\t$Rd, $Label", [], NoItinerary>;
4062 //===----------------------------------------------------------------------===//
4063 // System instructions
4064 //===----------------------------------------------------------------------===//
4065 // Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS
4066 // + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL
4068 // Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values.
4069 def uimm3_asmoperand : AsmOperandClass {
4071 let PredicateMethod = "isUImm<3>";
4072 let RenderMethod = "addImmOperands";
4073 let DiagnosticType = "UImm3";
4076 def uimm3 : Operand<i32> {
4077 let ParserMatchClass = uimm3_asmoperand;
4080 // The HINT alias can accept a simple unsigned 7-bit immediate.
4081 def uimm7_asmoperand : AsmOperandClass {
4083 let PredicateMethod = "isUImm<7>";
4084 let RenderMethod = "addImmOperands";
4085 let DiagnosticType = "UImm7";
4088 def uimm7 : Operand<i32> {
4089 let ParserMatchClass = uimm7_asmoperand;
4092 // Multiclass namedimm is defined with the prefetch operands. Most of these fit
4093 // into the NamedImmMapper scheme well: they either accept a named operand or
4094 // any immediate under a particular value (which may be 0, implying no immediate
4096 defm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">;
4097 defm isb : namedimm<"isb", "A64ISB::ISBMapper">;
4098 defm ic : namedimm<"ic", "A64IC::ICMapper">;
4099 defm dc : namedimm<"dc", "A64DC::DCMapper">;
4100 defm at : namedimm<"at", "A64AT::ATMapper">;
4101 defm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">;
4103 // However, MRS and MSR are more complicated for a few reasons:
4104 // * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an
4105 // implementation-defined effect
4106 // * Most registers are shared, but some are read-only or write-only.
4107 // * There is a variant of MSR which accepts the same register name (SPSel),
4108 // but which would have a different encoding.
4110 // In principle these could be resolved in with more complicated subclasses of
4111 // NamedImmMapper, however that imposes an overhead on other "named
4112 // immediates". Both in concrete terms with virtual tables and in unnecessary
4115 // The solution adopted here is to take the MRS/MSR Mappers out of the usual
4116 // hierarchy (they're not derived from NamedImmMapper) and to add logic for
4117 // their special situation.
4118 def mrs_asmoperand : AsmOperandClass {
4120 let ParserMethod = "ParseSysRegOperand";
4121 let DiagnosticType = "MRS";
4124 def mrs_op : Operand<i32> {
4125 let ParserMatchClass = mrs_asmoperand;
4126 let PrintMethod = "printMRSOperand";
4127 let DecoderMethod = "DecodeMRSOperand";
4130 def msr_asmoperand : AsmOperandClass {
4131 let Name = "MSRWithReg";
4133 // Note that SPSel is valid for both this and the pstate operands, but with
4134 // different immediate encodings. This is why these operands provide a string
4135 // AArch64Operand rather than an immediate. The overlap is small enough that
4136 // it could be resolved with hackery now, but who can say in future?
4137 let ParserMethod = "ParseSysRegOperand";
4138 let DiagnosticType = "MSR";
4141 def msr_op : Operand<i32> {
4142 let ParserMatchClass = msr_asmoperand;
4143 let PrintMethod = "printMSROperand";
4144 let DecoderMethod = "DecodeMSROperand";
4147 def pstate_asmoperand : AsmOperandClass {
4148 let Name = "MSRPState";
4149 // See comment above about parser.
4150 let ParserMethod = "ParseSysRegOperand";
4151 let DiagnosticType = "MSR";
4154 def pstate_op : Operand<i32> {
4155 let ParserMatchClass = pstate_asmoperand;
4156 let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>";
4157 let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>";
4160 // When <CRn> is specified, an assembler should accept something like "C4", not
4161 // the usual "#4" immediate.
4162 def CRx_asmoperand : AsmOperandClass {
4164 let PredicateMethod = "isUImm<4>";
4165 let RenderMethod = "addImmOperands";
4166 let ParserMethod = "ParseCRxOperand";
4167 // Diagnostics are handled in all cases by ParseCRxOperand.
4170 def CRx : Operand<i32> {
4171 let ParserMatchClass = CRx_asmoperand;
4172 let PrintMethod = "printCRxOperand";
4176 // Finally, we can start defining the instructions.
4178 // HINT is straightforward, with a few aliases.
4179 def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7",
4182 let CRm = UImm7{6-3};
4183 let Op2 = UImm7{2-0};
4191 def : InstAlias<"nop", (HINTi 0)>;
4192 def : InstAlias<"yield", (HINTi 1)>;
4193 def : InstAlias<"wfe", (HINTi 2)>;
4194 def : InstAlias<"wfi", (HINTi 3)>;
4195 def : InstAlias<"sev", (HINTi 4)>;
4196 def : InstAlias<"sevl", (HINTi 5)>;
4198 // Quite a few instructions then follow a similar pattern of fixing common
4199 // fields in the bitpattern, we'll define a helper-class for them.
4200 class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2,
4201 Operand operand, string asmop>
4202 : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"),
4212 def CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">;
4213 def DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">;
4214 def DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">;
4215 def ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">;
4217 def : InstAlias<"clrex", (CLREXi 0b1111)>;
4218 def : InstAlias<"isb", (ISBi 0b1111)>;
4220 // (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP
4221 // configurations at least.
4222 def : Pat<(atomic_fence imm, imm), (DMBi 0xb)>;
4224 // Any SYS bitpattern can be represented with a complex and opaque "SYS"
4226 def SYSiccix : A64I_system<0b0, (outs),
4227 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm,
4228 uimm3:$Op2, GPR64:$Rt),
4229 "sys\t$Op1, $CRn, $CRm, $Op2, $Rt",
4234 // You can skip the Xt argument whether it makes sense or not for the generic
4236 def : InstAlias<"sys $Op1, $CRn, $CRm, $Op2",
4237 (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>;
4240 // But many have aliases, which obviously don't fit into
4241 class SYSalias<dag ins, string asmstring>
4242 : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> {
4243 let isAsmParserOnly = 1;
4247 let Op1 = SysOp{13-11};
4248 let CRn = SysOp{10-7};
4249 let CRm = SysOp{6-3};
4250 let Op2 = SysOp{2-0};
4253 def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">;
4255 def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> {
4259 def DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">;
4260 def ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">;
4262 def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">;
4264 def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> {
4269 def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt),
4270 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2),
4271 "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2",
4276 // The instructions themselves are rather simple for MSR and MRS.
4277 def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt),
4278 "msr\t$SysReg, $Rt", [], NoItinerary> {
4280 let Op0 = SysReg{15-14};
4281 let Op1 = SysReg{13-11};
4282 let CRn = SysReg{10-7};
4283 let CRm = SysReg{6-3};
4284 let Op2 = SysReg{2-0};
4287 def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg),
4288 "mrs\t$Rt, $SysReg", [], NoItinerary> {
4290 let Op0 = SysReg{15-14};
4291 let Op1 = SysReg{13-11};
4292 let CRn = SysReg{10-7};
4293 let CRm = SysReg{6-3};
4294 let Op2 = SysReg{2-0};
4297 def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm),
4298 "msr\t$PState, $CRm", [], NoItinerary> {
4302 let Op1 = PState{5-3};
4304 let Op2 = PState{2-0};
4308 //===----------------------------------------------------------------------===//
4309 // Test & branch (immediate) instructions
4310 //===----------------------------------------------------------------------===//
4311 // Contains: TBZ, TBNZ
4313 // The bit to test is a simple unsigned 6-bit immediate in the X-register
4315 def uimm6 : Operand<i64> {
4316 let ParserMatchClass = uimm6_asmoperand;
4319 def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>;
4321 def tbimm_target : Operand<OtherVT> {
4322 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>";
4324 // This label is a 14-bit offset from PC, scaled by the instruction-width: 4.
4325 let PrintMethod = "printLabelOperand<14, 4>";
4326 let ParserMatchClass = label_wid14_scal4_asmoperand;
4328 let OperandType = "OPERAND_PCREL";
4331 def A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>;
4332 def A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>;
4334 // These instructions correspond to patterns involving "and" with a power of
4335 // two, which we need to be able to select.
4336 def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">;
4337 def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">;
4339 let isBranch = 1, isTerminator = 1 in {
4340 def TBZxii : A64I_TBimm<0b0, (outs),
4341 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4342 "tbz\t$Rt, $Imm, $Label",
4343 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4347 def TBNZxii : A64I_TBimm<0b1, (outs),
4348 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4349 "tbnz\t$Rt, $Imm, $Label",
4350 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4355 // Note, these instructions overlap with the above 64-bit patterns. This is
4356 // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both
4357 // do the same thing and are both permitted assembly. They also both have
4358 // sensible DAG patterns.
4359 def TBZwii : A64I_TBimm<0b0, (outs),
4360 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4361 "tbz\t$Rt, $Imm, $Label",
4362 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4368 def TBNZwii : A64I_TBimm<0b1, (outs),
4369 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4370 "tbnz\t$Rt, $Imm, $Label",
4371 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4378 //===----------------------------------------------------------------------===//
4379 // Unconditional branch (immediate) instructions
4380 //===----------------------------------------------------------------------===//
4383 def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>;
4385 def bimm_target : Operand<OtherVT> {
4386 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>";
4388 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4389 let PrintMethod = "printLabelOperand<26, 4>";
4390 let ParserMatchClass = label_wid26_scal4_asmoperand;
4392 let OperandType = "OPERAND_PCREL";
4395 def blimm_target : Operand<i64> {
4396 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>";
4398 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4399 let PrintMethod = "printLabelOperand<26, 4>";
4400 let ParserMatchClass = label_wid26_scal4_asmoperand;
4402 let OperandType = "OPERAND_PCREL";
4405 class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type>
4406 : A64I_Bimm<op, (outs), (ins lbl_type:$Label),
4407 !strconcat(asmop, "\t$Label"), patterns,
4410 let isBranch = 1 in {
4411 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
4412 let isTerminator = 1;
4416 def BLimm : A64I_BimmImpl<0b1, "bl",
4417 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4423 def : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>;
4425 //===----------------------------------------------------------------------===//
4426 // Unconditional branch (register) instructions
4427 //===----------------------------------------------------------------------===//
4428 // Contains: BR, BLR, RET, ERET, DRP.
4430 // Most of the notional opcode fields in the A64I_Breg format are fixed in A64
4432 class A64I_BregImpl<bits<4> opc,
4433 dag outs, dag ins, string asmstr, list<dag> patterns,
4434 InstrItinClass itin = NoItinerary>
4435 : A64I_Breg<opc, 0b11111, 0b000000, 0b00000,
4436 outs, ins, asmstr, patterns, itin> {
4438 let isIndirectBranch = 1;
4441 // Note that these are not marked isCall or isReturn because as far as LLVM is
4442 // concerned they're not. "ret" is just another jump unless it has been selected
4443 // by LLVM as the function's return.
4445 let isBranch = 1 in {
4446 def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn),
4447 "br\t$Rn", [(brind i64:$Rn)]> {
4449 let isTerminator = 1;
4452 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4453 "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
4459 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
4462 let isTerminator = 1;
4466 // Create a separate pseudo-instruction for codegen to use so that we don't
4467 // flag x30 as used in every function. It'll be restored before the RET by the
4468 // epilogue if it's legitimately used.
4469 def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> {
4470 let isTerminator = 1;
4475 def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> {
4478 let isTerminator = 1;
4482 def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> {
4488 def RETAlias : InstAlias<"ret", (RETx X30)>;
4491 //===----------------------------------------------------------------------===//
4492 // Address generation patterns
4493 //===----------------------------------------------------------------------===//
4495 // Primary method of address generation for the small/absolute memory model is
4496 // an ADRP/ADR pair:
4497 // ADRP x0, some_variable
4498 // ADD x0, x0, #:lo12:some_variable
4500 // The load/store elision of the ADD is accomplished when selecting
4501 // addressing-modes. This just mops up the cases where that doesn't work and we
4502 // really need an address in some register.
4504 // This wrapper applies a LO12 modifier to the address. Otherwise we could just
4505 // use the same address.
4507 class ADRP_ADD<SDNode Wrapper, SDNode addrop>
4508 : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)),
4509 (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>;
4511 def : ADRP_ADD<A64WrapperSmall, tblockaddress>;
4512 def : ADRP_ADD<A64WrapperSmall, texternalsym>;
4513 def : ADRP_ADD<A64WrapperSmall, tglobaladdr>;
4514 def : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>;
4515 def : ADRP_ADD<A64WrapperSmall, tjumptable>;
4517 //===----------------------------------------------------------------------===//
4518 // GOT access patterns
4519 //===----------------------------------------------------------------------===//
4521 class GOTLoadSmall<SDNode addrfrag>
4522 : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)),
4523 (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>;
4525 def : GOTLoadSmall<texternalsym>;
4526 def : GOTLoadSmall<tglobaladdr>;
4527 def : GOTLoadSmall<tglobaltlsaddr>;
4529 //===----------------------------------------------------------------------===//
4530 // Tail call handling
4531 //===----------------------------------------------------------------------===//
4533 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in {
4535 : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff),
4536 [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>;
4539 : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff),
4540 [(AArch64tcret i64:$dst, (i32 timm:$FPDiff))]>;
4543 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
4545 def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [],
4546 (Bimm bimm_target:$Label)>;
4548 def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [],
4553 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
4554 (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>;
4556 //===----------------------------------------------------------------------===//
4557 // Thread local storage
4558 //===----------------------------------------------------------------------===//
4560 // This is a pseudo-instruction representing the ".tlsdesccall" directive in
4561 // assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the
4562 // current location. It should always be immediately followed by a BLR
4563 // instruction, and is intended solely for relaxation by the linker.
4565 def : Pat<(A64threadpointer), (MRSxi 0xde82)>;
4567 def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> {
4568 let hasSideEffects = 1;
4571 def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var),
4572 [(A64tlsdesc_blr i64:$Rn, tglobaltlsaddr:$Var)]> {
4577 def : Pat<(A64tlsdesc_blr i64:$Rn, texternalsym:$Var),
4578 (TLSDESC_BLRx $Rn, texternalsym:$Var)>;
4580 //===----------------------------------------------------------------------===//
4581 // Bitfield patterns
4582 //===----------------------------------------------------------------------===//
4584 def bfi32_lsb_to_immr : SDNodeXForm<imm, [{
4585 return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64);
4588 def bfi64_lsb_to_immr : SDNodeXForm<imm, [{
4589 return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64);
4592 def bfi_width_to_imms : SDNodeXForm<imm, [{
4593 return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64);
4597 // The simpler patterns deal with cases where no AND mask is actually needed
4598 // (either all bits are used or the low 32 bits are used).
4599 let AddedComplexity = 10 in {
4601 def : Pat<(A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4603 (bfi64_lsb_to_immr (i64 imm:$ImmR)),
4604 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4606 def : Pat<(A64Bfi i32:$src, i32:$Rn, imm:$ImmR, imm:$ImmS),
4608 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4609 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4612 def : Pat<(and (A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4614 (SUBREG_TO_REG (i64 0),
4615 (BFIwwii (EXTRACT_SUBREG $src, sub_32),
4616 (EXTRACT_SUBREG $Rn, sub_32),
4617 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4618 (bfi_width_to_imms (i64 imm:$ImmS))),
4623 //===----------------------------------------------------------------------===//
4624 // Miscellaneous patterns
4625 //===----------------------------------------------------------------------===//
4627 // Truncation from 64 to 32-bits just involves renaming your register.
4628 def : Pat<(i32 (trunc i64:$val)), (EXTRACT_SUBREG $val, sub_32)>;
4630 // Similarly, extension where we don't care about the high bits is
4632 def : Pat<(i64 (anyext i32:$val)),
4633 (INSERT_SUBREG (IMPLICIT_DEF), $val, sub_32)>;
4635 // SELECT instructions providing f128 types need to be handled by a
4636 // pseudo-instruction since the eventual code will need to introduce basic
4637 // blocks and control flow.
4638 def F128CSEL : PseudoInst<(outs FPR128:$Rd),
4639 (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond),
4640 [(set f128:$Rd, (simple_select f128:$Rn, f128:$Rm))]> {
4642 let usesCustomInserter = 1;
4645 //===----------------------------------------------------------------------===//
4646 // Load/store patterns
4647 //===----------------------------------------------------------------------===//
4649 // There are lots of patterns here, because we need to allow at least three
4650 // parameters to vary independently.
4651 // 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ...
4652 // 2. LLVM source: zextloadi8, anyextloadi8, ...
4653 // 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ...
4655 // The biggest problem turns out to be the address-generation variable. At the
4656 // point of instantiation we need to produce two DAGs, one for the pattern and
4657 // one for the instruction. Doing this at the lowest level of classes doesn't
4660 // Consider the simple uimm12 addressing mode, and the desire to match both (add
4661 // GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the
4662 // instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or
4663 // "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this
4664 // operation, and PatFrags are for selection not output.
4666 // As a result, the address-generation patterns are the final
4667 // instantiations. However, we do still need to vary the operand for the address
4668 // further down (At the point we're deciding A64WrapperSmall, we don't know
4669 // the memory width of the operation).
4671 //===------------------------------
4672 // 1. Basic infrastructural defs
4673 //===------------------------------
4675 // First, some simple classes for !foreach and !subst to use:
4686 // You can't use !subst on an actual immediate, but you *can* use it on an
4687 // operand record that happens to match a single immediate. So we do.
4688 def imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>;
4689 def imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>;
4690 def imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>;
4691 def imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>;
4692 def imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>;
4694 // If the low bits of a pointer are known to be 0 then an "or" is just as good
4695 // as addition for computing an offset. This fragment forwards that check for
4697 def add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),
4699 return CurDAG->isBaseWithConstantOffset(SDValue(N, 0));
4702 // Load/store (unsigned immediate) operations with relocations against global
4703 // symbols (for lo12) are only valid if those symbols have correct alignment
4704 // (since the immediate offset is divided by the access scale, it can't have a
4707 // The guaranteed alignment is provided as part of the WrapperSmall
4708 // operation, and checked against one of these.
4709 def any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>;
4710 def min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>;
4711 def min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>;
4712 def min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>;
4713 def min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>;
4715 // "Normal" load/store instructions can be used on atomic operations, provided
4716 // the ordering parameter is at most "monotonic". Anything above that needs
4717 // special handling with acquire/release instructions.
4718 class simple_load<PatFrag base>
4719 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4720 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4723 def atomic_load_simple_i8 : simple_load<atomic_load_8>;
4724 def atomic_load_simple_i16 : simple_load<atomic_load_16>;
4725 def atomic_load_simple_i32 : simple_load<atomic_load_32>;
4726 def atomic_load_simple_i64 : simple_load<atomic_load_64>;
4728 class simple_store<PatFrag base>
4729 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4730 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4733 def atomic_store_simple_i8 : simple_store<atomic_store_8>;
4734 def atomic_store_simple_i16 : simple_store<atomic_store_16>;
4735 def atomic_store_simple_i32 : simple_store<atomic_store_32>;
4736 def atomic_store_simple_i64 : simple_store<atomic_store_64>;
4738 //===------------------------------
4739 // 2. UImm12 and SImm9
4740 //===------------------------------
4742 // These instructions have two operands providing the address so they can be
4743 // treated similarly for most purposes.
4745 //===------------------------------
4746 // 2.1 Base patterns covering extend/truncate semantics
4747 //===------------------------------
4749 // Atomic patterns can be shared between integer operations of all sizes, a
4750 // quick multiclass here allows reuse.
4751 multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4752 dag Offset, dag address, ValueType transty,
4754 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4755 (LOAD Base, Offset)>;
4757 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
4758 (STORE $Rt, Base, Offset)>;
4761 // Instructions accessing a memory chunk smaller than a register (or, in a
4762 // pinch, the same size) have a characteristic set of patterns they want to
4763 // match: extending loads and truncating stores. This class deals with the
4764 // sign-neutral version of those patterns.
4766 // It will be instantiated across multiple addressing-modes.
4767 multiclass ls_small_pats<Instruction LOAD, Instruction STORE,
4768 dag Base, dag Offset,
4769 dag address, ValueType sty>
4770 : ls_atomic_pats<LOAD, STORE, Base, Offset, address, i32, sty> {
4771 def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>;
4773 def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>;
4775 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4776 // register was actually set.
4777 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4778 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4780 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
4781 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4783 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
4784 (STORE $Rt, Base, Offset)>;
4786 // For truncating store from 64-bits, we have to manually tell LLVM to
4787 // ignore the high bits of the x register.
4788 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
4789 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
4792 // Next come patterns for sign-extending loads.
4793 multiclass load_signed_pats<string T, string U, dag Base, dag Offset,
4794 dag address, ValueType sty> {
4795 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
4796 (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>;
4798 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
4799 (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>;
4803 // and finally "natural-width" loads and stores come next.
4804 multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4805 dag Offset, dag address, ValueType sty> {
4806 def : Pat<(sty (load address)), (LOAD Base, Offset)>;
4807 def : Pat<(store sty:$Rt, address), (STORE $Rt, Base, Offset)>;
4810 // Integer operations also get atomic instructions to select for.
4811 multiclass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4812 dag Offset, dag address, ValueType sty>
4813 : ls_neutral_pats<LOAD, STORE, Base, Offset, address, sty>,
4814 ls_atomic_pats<LOAD, STORE, Base, Offset, address, sty, sty>;
4816 //===------------------------------
4817 // 2.2. Addressing-mode instantiations
4818 //===------------------------------
4820 multiclass uimm12_pats<dag address, dag Base, dag Offset> {
4821 defm : ls_small_pats<LS8_LDR, LS8_STR, Base,
4822 !foreach(decls.pattern, Offset,
4823 !subst(OFFSET, byte_uimm12, decls.pattern)),
4824 !foreach(decls.pattern, address,
4825 !subst(OFFSET, byte_uimm12,
4826 !subst(ALIGN, any_align, decls.pattern))),
4828 defm : ls_small_pats<LS16_LDR, LS16_STR, Base,
4829 !foreach(decls.pattern, Offset,
4830 !subst(OFFSET, hword_uimm12, decls.pattern)),
4831 !foreach(decls.pattern, address,
4832 !subst(OFFSET, hword_uimm12,
4833 !subst(ALIGN, min_align2, decls.pattern))),
4835 defm : ls_small_pats<LS32_LDR, LS32_STR, Base,
4836 !foreach(decls.pattern, Offset,
4837 !subst(OFFSET, word_uimm12, decls.pattern)),
4838 !foreach(decls.pattern, address,
4839 !subst(OFFSET, word_uimm12,
4840 !subst(ALIGN, min_align4, decls.pattern))),
4843 defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base,
4844 !foreach(decls.pattern, Offset,
4845 !subst(OFFSET, word_uimm12, decls.pattern)),
4846 !foreach(decls.pattern, address,
4847 !subst(OFFSET, word_uimm12,
4848 !subst(ALIGN, min_align4, decls.pattern))),
4851 defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base,
4852 !foreach(decls.pattern, Offset,
4853 !subst(OFFSET, dword_uimm12, decls.pattern)),
4854 !foreach(decls.pattern, address,
4855 !subst(OFFSET, dword_uimm12,
4856 !subst(ALIGN, min_align8, decls.pattern))),
4859 defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base,
4860 !foreach(decls.pattern, Offset,
4861 !subst(OFFSET, hword_uimm12, decls.pattern)),
4862 !foreach(decls.pattern, address,
4863 !subst(OFFSET, hword_uimm12,
4864 !subst(ALIGN, min_align2, decls.pattern))),
4867 defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base,
4868 !foreach(decls.pattern, Offset,
4869 !subst(OFFSET, word_uimm12, decls.pattern)),
4870 !foreach(decls.pattern, address,
4871 !subst(OFFSET, word_uimm12,
4872 !subst(ALIGN, min_align4, decls.pattern))),
4875 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
4876 !foreach(decls.pattern, Offset,
4877 !subst(OFFSET, dword_uimm12, decls.pattern)),
4878 !foreach(decls.pattern, address,
4879 !subst(OFFSET, dword_uimm12,
4880 !subst(ALIGN, min_align8, decls.pattern))),
4883 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
4884 !foreach(decls.pattern, Offset,
4885 !subst(OFFSET, qword_uimm12, decls.pattern)),
4886 !foreach(decls.pattern, address,
4887 !subst(OFFSET, qword_uimm12,
4888 !subst(ALIGN, min_align16, decls.pattern))),
4891 defm : load_signed_pats<"B", "", Base,
4892 !foreach(decls.pattern, Offset,
4893 !subst(OFFSET, byte_uimm12, decls.pattern)),
4894 !foreach(decls.pattern, address,
4895 !subst(OFFSET, byte_uimm12,
4896 !subst(ALIGN, any_align, decls.pattern))),
4899 defm : load_signed_pats<"H", "", Base,
4900 !foreach(decls.pattern, Offset,
4901 !subst(OFFSET, hword_uimm12, decls.pattern)),
4902 !foreach(decls.pattern, address,
4903 !subst(OFFSET, hword_uimm12,
4904 !subst(ALIGN, min_align2, decls.pattern))),
4907 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
4908 !subst(OFFSET, word_uimm12,
4909 !subst(ALIGN, min_align4, decls.pattern)))),
4910 (LDRSWx Base, !foreach(decls.pattern, Offset,
4911 !subst(OFFSET, word_uimm12, decls.pattern)))>;
4914 // Straightforward patterns of last resort: a pointer with or without an
4915 // appropriate offset.
4916 defm : uimm12_pats<(i64 i64:$Rn), (i64 i64:$Rn), (i64 0)>;
4917 defm : uimm12_pats<(add i64:$Rn, OFFSET:$UImm12),
4918 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
4920 // The offset could be hidden behind an "or", of course:
4921 defm : uimm12_pats<(add_like_or i64:$Rn, OFFSET:$UImm12),
4922 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
4924 // Global addresses under the small-absolute model should use these
4925 // instructions. There are ELF relocations specifically for it.
4926 defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN),
4927 (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>;
4929 defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12,
4931 (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>;
4933 // External symbols that make it this far should also get standard relocations.
4934 defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12,
4936 (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>;
4938 defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
4939 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
4941 // We also want to use uimm12 instructions for local variables at the moment.
4942 def tframeindex_XFORM : SDNodeXForm<frameindex, [{
4943 int FI = cast<FrameIndexSDNode>(N)->getIndex();
4944 return CurDAG->getTargetFrameIndex(FI, MVT::i64);
4947 defm : uimm12_pats<(i64 frameindex:$Rn),
4948 (tframeindex_XFORM tframeindex:$Rn), (i64 0)>;
4950 // These can be much simpler than uimm12 because we don't to change the operand
4951 // type (e.g. LDURB and LDURH take the same operands).
4952 multiclass simm9_pats<dag address, dag Base, dag Offset> {
4953 defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>;
4954 defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>;
4956 defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address, i32>;
4957 defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address, i64>;
4959 defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address, f16>;
4960 defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address, f32>;
4961 defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address, f64>;
4962 defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address,
4965 def : Pat<(i64 (zextloadi32 address)),
4966 (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>;
4968 def : Pat<(truncstorei32 i64:$Rt, address),
4969 (LS32_STUR (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
4971 defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>;
4972 defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>;
4973 def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>;
4976 defm : simm9_pats<(add i64:$Rn, simm9:$SImm9),
4977 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
4979 defm : simm9_pats<(add_like_or i64:$Rn, simm9:$SImm9),
4980 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
4983 //===------------------------------
4984 // 3. Register offset patterns
4985 //===------------------------------
4987 // Atomic patterns can be shared between integer operations of all sizes, a
4988 // quick multiclass here allows reuse.
4989 multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4990 dag Offset, dag Extend, dag address,
4991 ValueType transty, ValueType sty> {
4992 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4993 (LOAD Base, Offset, Extend)>;
4995 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
4996 (STORE $Rt, Base, Offset, Extend)>;
4999 // The register offset instructions take three operands giving the instruction,
5000 // and have an annoying split between instructions where Rm is 32-bit and
5001 // 64-bit. So we need a special hierarchy to describe them. Other than that the
5002 // same operations should be supported as for simm9 and uimm12 addressing.
5004 multiclass ro_small_pats<Instruction LOAD, Instruction STORE,
5005 dag Base, dag Offset, dag Extend,
5006 dag address, ValueType sty>
5007 : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, i32, sty> {
5008 def : Pat<(!cast<SDNode>(zextload # sty) address),
5009 (LOAD Base, Offset, Extend)>;
5011 def : Pat<(!cast<SDNode>(extload # sty) address),
5012 (LOAD Base, Offset, Extend)>;
5014 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
5015 // register was actually set.
5016 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
5017 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
5019 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
5020 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
5022 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
5023 (STORE $Rt, Base, Offset, Extend)>;
5025 // For truncating store from 64-bits, we have to manually tell LLVM to
5026 // ignore the high bits of the x register.
5027 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
5028 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset, Extend)>;
5032 // Next come patterns for sign-extending loads.
5033 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
5034 dag address, ValueType sty> {
5035 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
5036 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
5037 Base, Offset, Extend)>;
5039 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
5040 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
5041 Base, Offset, Extend)>;
5044 // and finally "natural-width" loads and stores come next.
5045 multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE,
5046 dag Base, dag Offset, dag Extend, dag address,
5048 def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>;
5049 def : Pat<(store sty:$Rt, address),
5050 (STORE $Rt, Base, Offset, Extend)>;
5053 multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE,
5054 dag Base, dag Offset, dag Extend, dag address,
5056 : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, sty>,
5057 ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, sty, sty>;
5059 multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset,
5061 defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"),
5062 !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"),
5063 Base, Offset, Extend,
5064 !foreach(decls.pattern, address,
5065 !subst(SHIFT, imm_eq0, decls.pattern)),
5067 defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"),
5068 !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"),
5069 Base, Offset, Extend,
5070 !foreach(decls.pattern, address,
5071 !subst(SHIFT, imm_eq1, decls.pattern)),
5073 defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5074 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5075 Base, Offset, Extend,
5076 !foreach(decls.pattern, address,
5077 !subst(SHIFT, imm_eq2, decls.pattern)),
5080 defm : ro_int_neutral_pats<
5081 !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5082 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5083 Base, Offset, Extend,
5084 !foreach(decls.pattern, address,
5085 !subst(SHIFT, imm_eq2, decls.pattern)),
5088 defm : ro_int_neutral_pats<
5089 !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
5090 !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
5091 Base, Offset, Extend,
5092 !foreach(decls.pattern, address,
5093 !subst(SHIFT, imm_eq3, decls.pattern)),
5096 defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"),
5097 !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"),
5098 Base, Offset, Extend,
5099 !foreach(decls.pattern, address,
5100 !subst(SHIFT, imm_eq1, decls.pattern)),
5103 defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"),
5104 !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"),
5105 Base, Offset, Extend,
5106 !foreach(decls.pattern, address,
5107 !subst(SHIFT, imm_eq2, decls.pattern)),
5110 defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"),
5111 !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"),
5112 Base, Offset, Extend,
5113 !foreach(decls.pattern, address,
5114 !subst(SHIFT, imm_eq3, decls.pattern)),
5117 defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"),
5118 !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"),
5119 Base, Offset, Extend,
5120 !foreach(decls.pattern, address,
5121 !subst(SHIFT, imm_eq4, decls.pattern)),
5124 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,
5125 !foreach(decls.pattern, address,
5126 !subst(SHIFT, imm_eq0, decls.pattern)),
5129 defm : ro_signed_pats<"H", Rm, Base, Offset, Extend,
5130 !foreach(decls.pattern, address,
5131 !subst(SHIFT, imm_eq1, decls.pattern)),
5134 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
5135 !subst(SHIFT, imm_eq2, decls.pattern))),
5136 (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset")
5137 Base, Offset, Extend)>;
5141 // Finally we're in a position to tell LLVM exactly what addresses are reachable
5142 // using register-offset instructions. Essentially a base plus a possibly
5143 // extended, possibly shifted (by access size) offset.
5145 defm : regoff_pats<"Wm", (add i64:$Rn, (sext i32:$Rm)),
5146 (i64 i64:$Rn), (i32 i32:$Rm), (i64 6)>;
5148 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (sext i32:$Rm), SHIFT)),
5149 (i64 i64:$Rn), (i32 i32:$Rm), (i64 7)>;
5151 defm : regoff_pats<"Wm", (add i64:$Rn, (zext i32:$Rm)),
5152 (i64 i64:$Rn), (i32 i32:$Rm), (i64 2)>;
5154 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (zext i32:$Rm), SHIFT)),
5155 (i64 i64:$Rn), (i32 i32:$Rm), (i64 3)>;
5157 defm : regoff_pats<"Xm", (add i64:$Rn, i64:$Rm),
5158 (i64 i64:$Rn), (i64 i64:$Rm), (i64 2)>;
5160 defm : regoff_pats<"Xm", (add i64:$Rn, (shl i64:$Rm, SHIFT)),
5161 (i64 i64:$Rn), (i64 i64:$Rm), (i64 3)>;
5163 //===----------------------------------------------------------------------===//
5164 // Advanced SIMD (NEON) Support
5167 include "AArch64InstrNEON.td"