1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
28 //===----------------------------------------------------------------------===//
29 // AArch64-specific DAG Nodes.
32 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
33 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
39 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
45 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
46 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
53 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
54 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
56 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
57 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
58 SDTCisVT<2, OtherVT>]>;
61 def SDT_AArch64CSel : SDTypeProfile<1, 4,
66 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
69 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
70 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
71 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
74 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
75 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
76 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
77 SDTCisInt<2>, SDTCisInt<3>]>;
78 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
79 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
80 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
81 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
83 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
84 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
85 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
86 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
91 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
92 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
94 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
96 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
98 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
99 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
100 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
101 SDTCisSameAs<1, 4>]>;
105 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
106 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
107 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
108 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
109 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
110 [SDNPHasChain, SDNPOutGlue]>;
111 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
112 SDCallSeqEnd<[ SDTCisVT<0, i32>,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
115 def AArch64call : SDNode<"AArch64ISD::CALL",
116 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
121 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
123 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
125 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
127 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
131 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
132 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
133 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
134 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
135 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
136 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
137 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
138 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
139 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
141 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
142 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
144 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
145 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
147 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
149 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
151 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
152 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
154 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
155 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
156 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
157 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
158 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
160 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
161 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
162 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
163 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
164 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
165 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
167 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
168 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
169 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
170 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
171 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
172 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
173 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
175 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
176 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
177 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
178 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
180 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
181 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
182 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
183 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
184 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
185 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
186 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
187 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
189 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
190 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
191 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
193 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
194 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
195 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
196 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
197 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
199 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
200 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
201 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
203 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
204 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
205 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
206 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
207 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
208 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
209 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
211 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
212 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
213 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
214 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
215 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
217 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
218 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
220 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
222 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
223 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
225 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
226 [SDNPHasChain, SDNPSideEffect]>;
228 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
229 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
231 def AArch64tlsdesc_call : SDNode<"AArch64ISD::TLSDESC_CALL",
232 SDT_AArch64TLSDescCall,
233 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
236 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
237 SDT_AArch64WrapperLarge>;
240 //===----------------------------------------------------------------------===//
242 //===----------------------------------------------------------------------===//
244 // AArch64 Instruction Predicate Definitions.
246 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
247 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
248 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
249 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
250 def ForCodeSize : Predicate<"ForCodeSize">;
251 def NotForCodeSize : Predicate<"!ForCodeSize">;
253 include "AArch64InstrFormats.td"
255 //===----------------------------------------------------------------------===//
257 //===----------------------------------------------------------------------===//
258 // Miscellaneous instructions.
259 //===----------------------------------------------------------------------===//
261 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
262 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
263 [(AArch64callseq_start timm:$amt)]>;
264 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
265 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
266 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
268 let isReMaterializable = 1, isCodeGenOnly = 1 in {
269 // FIXME: The following pseudo instructions are only needed because remat
270 // cannot handle multiple instructions. When that changes, they can be
271 // removed, along with the AArch64Wrapper node.
273 let AddedComplexity = 10 in
274 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
275 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
278 // The MOVaddr instruction should match only when the add is not folded
279 // into a load or store address.
281 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
282 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
283 tglobaladdr:$low))]>,
284 Sched<[WriteAdrAdr]>;
286 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
287 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
289 Sched<[WriteAdrAdr]>;
291 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
292 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
294 Sched<[WriteAdrAdr]>;
296 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
297 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
298 tblockaddress:$low))]>,
299 Sched<[WriteAdrAdr]>;
301 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
302 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
303 tglobaltlsaddr:$low))]>,
304 Sched<[WriteAdrAdr]>;
306 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
307 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
308 texternalsym:$low))]>,
309 Sched<[WriteAdrAdr]>;
311 } // isReMaterializable, isCodeGenOnly
313 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
314 (LOADgot tglobaltlsaddr:$addr)>;
316 def : Pat<(AArch64LOADgot texternalsym:$addr),
317 (LOADgot texternalsym:$addr)>;
319 def : Pat<(AArch64LOADgot tconstpool:$addr),
320 (LOADgot tconstpool:$addr)>;
322 //===----------------------------------------------------------------------===//
323 // System instructions.
324 //===----------------------------------------------------------------------===//
326 def HINT : HintI<"hint">;
327 def : InstAlias<"nop", (HINT 0b000)>;
328 def : InstAlias<"yield",(HINT 0b001)>;
329 def : InstAlias<"wfe", (HINT 0b010)>;
330 def : InstAlias<"wfi", (HINT 0b011)>;
331 def : InstAlias<"sev", (HINT 0b100)>;
332 def : InstAlias<"sevl", (HINT 0b101)>;
334 // As far as LLVM is concerned this writes to the system's exclusive monitors.
335 let mayLoad = 1, mayStore = 1 in
336 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
338 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
339 // model patterns with sufficiently fine granularity.
340 let mayLoad = ?, mayStore = ? in {
341 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
342 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
344 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
345 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
347 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
348 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
351 def : InstAlias<"clrex", (CLREX 0xf)>;
352 def : InstAlias<"isb", (ISB 0xf)>;
356 def MSRpstate: MSRpstateI;
358 // The thread pointer (on Linux, at least, where this has been implemented) is
360 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
362 // Generic system instructions
363 def SYSxt : SystemXtI<0, "sys">;
364 def SYSLxt : SystemLXtI<1, "sysl">;
366 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
367 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
368 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
370 //===----------------------------------------------------------------------===//
371 // Move immediate instructions.
372 //===----------------------------------------------------------------------===//
374 defm MOVK : InsertImmediate<0b11, "movk">;
375 defm MOVN : MoveImmediate<0b00, "movn">;
377 let PostEncoderMethod = "fixMOVZ" in
378 defm MOVZ : MoveImmediate<0b10, "movz">;
380 // First group of aliases covers an implicit "lsl #0".
381 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
382 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
383 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
384 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
385 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
386 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
388 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
389 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
390 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
391 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
392 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
394 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
395 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
396 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
397 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
399 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
400 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
401 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
402 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
404 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
405 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
407 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
408 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
410 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
411 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
413 // Final group of aliases covers true "mov $Rd, $imm" cases.
414 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
415 int width, int shift> {
416 def _asmoperand : AsmOperandClass {
417 let Name = basename # width # "_lsl" # shift # "MovAlias";
418 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
420 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
423 def _movimm : Operand<i32> {
424 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
427 def : InstAlias<"mov $Rd, $imm",
428 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
431 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
432 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
434 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
435 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
436 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
437 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
439 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
440 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
442 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
443 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
444 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
445 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
447 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
448 isAsCheapAsAMove = 1 in {
449 // FIXME: The following pseudo instructions are only needed because remat
450 // cannot handle multiple instructions. When that changes, we can select
451 // directly to the real instructions and get rid of these pseudos.
454 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
455 [(set GPR32:$dst, imm:$src)]>,
458 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
459 [(set GPR64:$dst, imm:$src)]>,
461 } // isReMaterializable, isCodeGenOnly
463 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
464 // eventual expansion code fewer bits to worry about getting right. Marshalling
465 // the types is a little tricky though:
466 def i64imm_32bit : ImmLeaf<i64, [{
467 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
470 def trunc_imm : SDNodeXForm<imm, [{
471 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
474 def : Pat<(i64 i64imm_32bit:$src),
475 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
477 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
479 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
480 tglobaladdr:$g1, tglobaladdr:$g0),
481 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
482 tglobaladdr:$g2, 32),
483 tglobaladdr:$g1, 16),
484 tglobaladdr:$g0, 0)>;
486 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
487 tblockaddress:$g1, tblockaddress:$g0),
488 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
489 tblockaddress:$g2, 32),
490 tblockaddress:$g1, 16),
491 tblockaddress:$g0, 0)>;
493 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
494 tconstpool:$g1, tconstpool:$g0),
495 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
500 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
501 tjumptable:$g1, tjumptable:$g0),
502 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
508 //===----------------------------------------------------------------------===//
509 // Arithmetic instructions.
510 //===----------------------------------------------------------------------===//
512 // Add/subtract with carry.
513 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
514 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
516 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
517 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
518 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
519 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
522 defm ADD : AddSub<0, "add", add>;
523 defm SUB : AddSub<1, "sub">;
525 def : InstAlias<"mov $dst, $src",
526 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
527 def : InstAlias<"mov $dst, $src",
528 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
529 def : InstAlias<"mov $dst, $src",
530 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
531 def : InstAlias<"mov $dst, $src",
532 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
534 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
535 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
537 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
538 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
539 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
540 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
541 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
542 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
543 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
544 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
545 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
546 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
547 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
548 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
549 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
550 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
551 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
552 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
553 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
555 // Because of the immediate format for add/sub-imm instructions, the
556 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
557 // These patterns capture that transformation.
558 let AddedComplexity = 1 in {
559 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
560 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
561 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
562 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
563 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
564 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
565 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
566 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
569 // Because of the immediate format for add/sub-imm instructions, the
570 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
571 // These patterns capture that transformation.
572 let AddedComplexity = 1 in {
573 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
574 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
575 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
576 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
577 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
578 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
579 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
580 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
583 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
584 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
585 def : InstAlias<"neg $dst, $src$shift",
586 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
587 def : InstAlias<"neg $dst, $src$shift",
588 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
590 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
591 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
592 def : InstAlias<"negs $dst, $src$shift",
593 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
594 def : InstAlias<"negs $dst, $src$shift",
595 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
598 // Unsigned/Signed divide
599 defm UDIV : Div<0, "udiv", udiv>;
600 defm SDIV : Div<1, "sdiv", sdiv>;
601 let isCodeGenOnly = 1 in {
602 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
603 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
607 defm ASRV : Shift<0b10, "asr", sra>;
608 defm LSLV : Shift<0b00, "lsl", shl>;
609 defm LSRV : Shift<0b01, "lsr", srl>;
610 defm RORV : Shift<0b11, "ror", rotr>;
612 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
613 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
614 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
615 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
616 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
617 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
618 def : ShiftAlias<"rorv", RORVWr, GPR32>;
619 def : ShiftAlias<"rorv", RORVXr, GPR64>;
622 let AddedComplexity = 7 in {
623 defm MADD : MulAccum<0, "madd", add>;
624 defm MSUB : MulAccum<1, "msub", sub>;
626 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
627 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
628 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
629 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
631 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
632 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
633 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
634 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
635 } // AddedComplexity = 7
637 let AddedComplexity = 5 in {
638 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
639 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
640 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
641 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
643 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
644 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
645 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
646 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
648 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
649 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
650 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
651 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
652 } // AddedComplexity = 5
654 def : MulAccumWAlias<"mul", MADDWrrr>;
655 def : MulAccumXAlias<"mul", MADDXrrr>;
656 def : MulAccumWAlias<"mneg", MSUBWrrr>;
657 def : MulAccumXAlias<"mneg", MSUBXrrr>;
658 def : WideMulAccumAlias<"smull", SMADDLrrr>;
659 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
660 def : WideMulAccumAlias<"umull", UMADDLrrr>;
661 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
664 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
665 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
668 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
669 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
670 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
671 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
673 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
674 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
675 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
676 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
679 //===----------------------------------------------------------------------===//
680 // Logical instructions.
681 //===----------------------------------------------------------------------===//
684 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
685 defm AND : LogicalImm<0b00, "and", and, "bic">;
686 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
687 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
689 // FIXME: these aliases *are* canonical sometimes (when movz can't be
690 // used). Actually, it seems to be working right now, but putting logical_immXX
691 // here is a bit dodgy on the AsmParser side too.
692 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
693 logical_imm32:$imm), 0>;
694 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
695 logical_imm64:$imm), 0>;
699 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
700 defm BICS : LogicalRegS<0b11, 1, "bics",
701 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
702 defm AND : LogicalReg<0b00, 0, "and", and>;
703 defm BIC : LogicalReg<0b00, 1, "bic",
704 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
705 defm EON : LogicalReg<0b10, 1, "eon",
706 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
707 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
708 defm ORN : LogicalReg<0b01, 1, "orn",
709 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
710 defm ORR : LogicalReg<0b01, 0, "orr", or>;
712 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
713 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
715 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
716 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
718 def : InstAlias<"mvn $Wd, $Wm$sh",
719 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
720 def : InstAlias<"mvn $Xd, $Xm$sh",
721 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
723 def : InstAlias<"tst $src1, $src2",
724 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
725 def : InstAlias<"tst $src1, $src2",
726 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
728 def : InstAlias<"tst $src1, $src2",
729 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
730 def : InstAlias<"tst $src1, $src2",
731 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
733 def : InstAlias<"tst $src1, $src2$sh",
734 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
735 def : InstAlias<"tst $src1, $src2$sh",
736 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
739 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
740 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
743 //===----------------------------------------------------------------------===//
744 // One operand data processing instructions.
745 //===----------------------------------------------------------------------===//
747 defm CLS : OneOperandData<0b101, "cls">;
748 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
749 defm RBIT : OneOperandData<0b000, "rbit">;
751 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
752 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
754 def REV16Wr : OneWRegData<0b001, "rev16",
755 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
756 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
758 def : Pat<(cttz GPR32:$Rn),
759 (CLZWr (RBITWr GPR32:$Rn))>;
760 def : Pat<(cttz GPR64:$Rn),
761 (CLZXr (RBITXr GPR64:$Rn))>;
762 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
765 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
769 // Unlike the other one operand instructions, the instructions with the "rev"
770 // mnemonic do *not* just different in the size bit, but actually use different
771 // opcode bits for the different sizes.
772 def REVWr : OneWRegData<0b010, "rev", bswap>;
773 def REVXr : OneXRegData<0b011, "rev", bswap>;
774 def REV32Xr : OneXRegData<0b010, "rev32",
775 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
777 // The bswap commutes with the rotr so we want a pattern for both possible
779 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
780 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
782 //===----------------------------------------------------------------------===//
783 // Bitfield immediate extraction instruction.
784 //===----------------------------------------------------------------------===//
785 let neverHasSideEffects = 1 in
786 defm EXTR : ExtractImm<"extr">;
787 def : InstAlias<"ror $dst, $src, $shift",
788 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
789 def : InstAlias<"ror $dst, $src, $shift",
790 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
792 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
793 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
794 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
795 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
797 //===----------------------------------------------------------------------===//
798 // Other bitfield immediate instructions.
799 //===----------------------------------------------------------------------===//
800 let neverHasSideEffects = 1 in {
801 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
802 defm SBFM : BitfieldImm<0b00, "sbfm">;
803 defm UBFM : BitfieldImm<0b10, "ubfm">;
806 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
807 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
808 return CurDAG->getTargetConstant(enc, MVT::i64);
811 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
812 uint64_t enc = 31 - N->getZExtValue();
813 return CurDAG->getTargetConstant(enc, MVT::i64);
816 // min(7, 31 - shift_amt)
817 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
818 uint64_t enc = 31 - N->getZExtValue();
819 enc = enc > 7 ? 7 : enc;
820 return CurDAG->getTargetConstant(enc, MVT::i64);
823 // min(15, 31 - shift_amt)
824 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
825 uint64_t enc = 31 - N->getZExtValue();
826 enc = enc > 15 ? 15 : enc;
827 return CurDAG->getTargetConstant(enc, MVT::i64);
830 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
831 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
832 return CurDAG->getTargetConstant(enc, MVT::i64);
835 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
836 uint64_t enc = 63 - N->getZExtValue();
837 return CurDAG->getTargetConstant(enc, MVT::i64);
840 // min(7, 63 - shift_amt)
841 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
842 uint64_t enc = 63 - N->getZExtValue();
843 enc = enc > 7 ? 7 : enc;
844 return CurDAG->getTargetConstant(enc, MVT::i64);
847 // min(15, 63 - shift_amt)
848 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
849 uint64_t enc = 63 - N->getZExtValue();
850 enc = enc > 15 ? 15 : enc;
851 return CurDAG->getTargetConstant(enc, MVT::i64);
854 // min(31, 63 - shift_amt)
855 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
856 uint64_t enc = 63 - N->getZExtValue();
857 enc = enc > 31 ? 31 : enc;
858 return CurDAG->getTargetConstant(enc, MVT::i64);
861 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
862 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
863 (i64 (i32shift_b imm0_31:$imm)))>;
864 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
865 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
866 (i64 (i64shift_b imm0_63:$imm)))>;
868 let AddedComplexity = 10 in {
869 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
870 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
871 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
872 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
875 def : InstAlias<"asr $dst, $src, $shift",
876 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
877 def : InstAlias<"asr $dst, $src, $shift",
878 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
879 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
880 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
881 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
882 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
883 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
885 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
886 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
887 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
888 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
890 def : InstAlias<"lsr $dst, $src, $shift",
891 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
892 def : InstAlias<"lsr $dst, $src, $shift",
893 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
894 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
895 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
896 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
897 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
898 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
900 //===----------------------------------------------------------------------===//
901 // Conditionally set flags instructions.
902 //===----------------------------------------------------------------------===//
903 defm CCMN : CondSetFlagsImm<0, "ccmn">;
904 defm CCMP : CondSetFlagsImm<1, "ccmp">;
906 defm CCMN : CondSetFlagsReg<0, "ccmn">;
907 defm CCMP : CondSetFlagsReg<1, "ccmp">;
909 //===----------------------------------------------------------------------===//
910 // Conditional select instructions.
911 //===----------------------------------------------------------------------===//
912 defm CSEL : CondSelect<0, 0b00, "csel">;
914 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
915 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
916 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
917 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
919 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
920 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
921 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
922 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
923 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
924 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
925 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
926 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
927 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
928 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
929 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
930 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
932 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
933 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
934 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
935 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
936 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
937 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
938 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
939 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
941 // The inverse of the condition code from the alias instruction is what is used
942 // in the aliased instruction. The parser all ready inverts the condition code
943 // for these aliases.
944 def : InstAlias<"cset $dst, $cc",
945 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
946 def : InstAlias<"cset $dst, $cc",
947 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
949 def : InstAlias<"csetm $dst, $cc",
950 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
951 def : InstAlias<"csetm $dst, $cc",
952 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
954 def : InstAlias<"cinc $dst, $src, $cc",
955 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
956 def : InstAlias<"cinc $dst, $src, $cc",
957 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
959 def : InstAlias<"cinv $dst, $src, $cc",
960 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
961 def : InstAlias<"cinv $dst, $src, $cc",
962 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
964 def : InstAlias<"cneg $dst, $src, $cc",
965 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
966 def : InstAlias<"cneg $dst, $src, $cc",
967 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
969 //===----------------------------------------------------------------------===//
970 // PC-relative instructions.
971 //===----------------------------------------------------------------------===//
972 let isReMaterializable = 1 in {
973 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
974 def ADR : ADRI<0, "adr", adrlabel, []>;
975 } // neverHasSideEffects = 1
977 def ADRP : ADRI<1, "adrp", adrplabel,
978 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
979 } // isReMaterializable = 1
981 // page address of a constant pool entry, block address
982 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
983 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
985 //===----------------------------------------------------------------------===//
986 // Unconditional branch (register) instructions.
987 //===----------------------------------------------------------------------===//
989 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
990 def RET : BranchReg<0b0010, "ret", []>;
991 def DRPS : SpecialReturn<0b0101, "drps">;
992 def ERET : SpecialReturn<0b0100, "eret">;
993 } // isReturn = 1, isTerminator = 1, isBarrier = 1
995 // Default to the LR register.
996 def : InstAlias<"ret", (RET LR)>;
998 let isCall = 1, Defs = [LR], Uses = [SP] in {
999 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1002 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1003 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1004 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1006 // Create a separate pseudo-instruction for codegen to use so that we don't
1007 // flag lr as used in every function. It'll be restored before the RET by the
1008 // epilogue if it's legitimately used.
1009 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1010 let isTerminator = 1;
1015 // This is a directive-like pseudo-instruction. The purpose is to insert an
1016 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1017 // (which in the usual case is a BLR).
1018 let hasSideEffects = 1 in
1019 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1020 let AsmString = ".tlsdesccall $sym";
1023 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
1024 // gets expanded to two MCInsts during lowering.
1025 let isCall = 1, Defs = [LR] in
1027 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
1028 [(AArch64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
1030 def : Pat<(AArch64tlsdesc_call GPR64:$dest, texternalsym:$sym),
1031 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
1032 //===----------------------------------------------------------------------===//
1033 // Conditional branch (immediate) instruction.
1034 //===----------------------------------------------------------------------===//
1035 def Bcc : BranchCond;
1037 //===----------------------------------------------------------------------===//
1038 // Compare-and-branch instructions.
1039 //===----------------------------------------------------------------------===//
1040 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1041 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1043 //===----------------------------------------------------------------------===//
1044 // Test-bit-and-branch instructions.
1045 //===----------------------------------------------------------------------===//
1046 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1047 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1049 //===----------------------------------------------------------------------===//
1050 // Unconditional branch (immediate) instructions.
1051 //===----------------------------------------------------------------------===//
1052 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1053 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1054 } // isBranch, isTerminator, isBarrier
1056 let isCall = 1, Defs = [LR], Uses = [SP] in {
1057 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1059 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1061 //===----------------------------------------------------------------------===//
1062 // Exception generation instructions.
1063 //===----------------------------------------------------------------------===//
1064 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1065 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1066 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1067 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1068 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1069 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1070 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1071 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1073 // DCPSn defaults to an immediate operand of zero if unspecified.
1074 def : InstAlias<"dcps1", (DCPS1 0)>;
1075 def : InstAlias<"dcps2", (DCPS2 0)>;
1076 def : InstAlias<"dcps3", (DCPS3 0)>;
1078 //===----------------------------------------------------------------------===//
1079 // Load instructions.
1080 //===----------------------------------------------------------------------===//
1082 // Pair (indexed, offset)
1083 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1084 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1085 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1086 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1087 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1089 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1091 // Pair (pre-indexed)
1092 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1093 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1094 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1095 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1096 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1098 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1100 // Pair (post-indexed)
1101 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1102 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1103 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1104 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1105 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1107 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1110 // Pair (no allocate)
1111 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1112 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1113 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1114 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1115 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1118 // (register offset)
1122 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1123 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1124 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1125 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1128 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1129 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1130 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1131 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1132 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1134 // Load sign-extended half-word
1135 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1136 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1138 // Load sign-extended byte
1139 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1140 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1142 // Load sign-extended word
1143 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1146 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1148 // For regular load, we do not have any alignment requirement.
1149 // Thus, it is safe to directly map the vector loads with interesting
1150 // addressing modes.
1151 // FIXME: We could do the same for bitconvert to floating point vectors.
1152 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1153 ValueType ScalTy, ValueType VecTy,
1154 Instruction LOADW, Instruction LOADX,
1156 def : Pat<(VecTy (scalar_to_vector (ScalTy
1157 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1158 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1159 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1162 def : Pat<(VecTy (scalar_to_vector (ScalTy
1163 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1164 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1165 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1169 let AddedComplexity = 10 in {
1170 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1171 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1173 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1174 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1176 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1177 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1179 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1180 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1182 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1184 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1187 def : Pat <(v1i64 (scalar_to_vector (i64
1188 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1189 ro_Wextend64:$extend))))),
1190 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1192 def : Pat <(v1i64 (scalar_to_vector (i64
1193 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1194 ro_Xextend64:$extend))))),
1195 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1198 // Match all load 64 bits width whose type is compatible with FPR64
1199 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1200 Instruction LOADW, Instruction LOADX> {
1202 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1203 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1205 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1206 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1209 let AddedComplexity = 10 in {
1210 let Predicates = [IsLE] in {
1211 // We must do vector loads with LD1 in big-endian.
1212 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1213 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1214 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1215 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1218 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1219 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1221 // Match all load 128 bits width whose type is compatible with FPR128
1222 let Predicates = [IsLE] in {
1223 // We must do vector loads with LD1 in big-endian.
1224 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1225 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1226 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1227 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1228 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1229 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1231 } // AddedComplexity = 10
1234 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1235 Instruction INSTW, Instruction INSTX> {
1236 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1237 (SUBREG_TO_REG (i64 0),
1238 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1241 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1242 (SUBREG_TO_REG (i64 0),
1243 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1247 let AddedComplexity = 10 in {
1248 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1249 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1250 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1252 // zextloadi1 -> zextloadi8
1253 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1255 // extload -> zextload
1256 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1257 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1258 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1260 // extloadi1 -> zextloadi8
1261 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1266 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1267 Instruction INSTW, Instruction INSTX> {
1268 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1269 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1271 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1272 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1276 let AddedComplexity = 10 in {
1277 // extload -> zextload
1278 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1279 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1280 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1282 // zextloadi1 -> zextloadi8
1283 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1287 // (unsigned immediate)
1289 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1291 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1292 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1294 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1295 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1297 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1298 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1299 [(set (f16 FPR16:$Rt),
1300 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1301 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1302 [(set (f32 FPR32:$Rt),
1303 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1304 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1305 [(set (f64 FPR64:$Rt),
1306 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1307 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1308 [(set (f128 FPR128:$Rt),
1309 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1311 // For regular load, we do not have any alignment requirement.
1312 // Thus, it is safe to directly map the vector loads with interesting
1313 // addressing modes.
1314 // FIXME: We could do the same for bitconvert to floating point vectors.
1315 def : Pat <(v8i8 (scalar_to_vector (i32
1316 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1317 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1318 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1319 def : Pat <(v16i8 (scalar_to_vector (i32
1320 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1321 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1322 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1323 def : Pat <(v4i16 (scalar_to_vector (i32
1324 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1325 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1326 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1327 def : Pat <(v8i16 (scalar_to_vector (i32
1328 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1329 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1330 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1331 def : Pat <(v2i32 (scalar_to_vector (i32
1332 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1333 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1334 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1335 def : Pat <(v4i32 (scalar_to_vector (i32
1336 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1337 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1338 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1339 def : Pat <(v1i64 (scalar_to_vector (i64
1340 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1341 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1342 def : Pat <(v2i64 (scalar_to_vector (i64
1343 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1344 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1345 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1347 // Match all load 64 bits width whose type is compatible with FPR64
1348 let Predicates = [IsLE] in {
1349 // We must use LD1 to perform vector loads in big-endian.
1350 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1351 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1352 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1353 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1354 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1355 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1356 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1357 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1359 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1360 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1361 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1362 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1364 // Match all load 128 bits width whose type is compatible with FPR128
1365 let Predicates = [IsLE] in {
1366 // We must use LD1 to perform vector loads in big-endian.
1367 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1368 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1369 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1370 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1371 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1372 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1373 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1374 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1375 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1376 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1377 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1378 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1380 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1381 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1383 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1385 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1386 uimm12s2:$offset)))]>;
1387 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1389 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1390 uimm12s1:$offset)))]>;
1392 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1393 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1394 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1395 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1397 // zextloadi1 -> zextloadi8
1398 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1399 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1400 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1401 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1403 // extload -> zextload
1404 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1405 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1406 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1407 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1408 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1409 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1410 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1411 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1412 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1413 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1414 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1415 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1416 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1417 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1419 // load sign-extended half-word
1420 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1422 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1423 uimm12s2:$offset)))]>;
1424 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1426 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1427 uimm12s2:$offset)))]>;
1429 // load sign-extended byte
1430 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1432 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1433 uimm12s1:$offset)))]>;
1434 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1436 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1437 uimm12s1:$offset)))]>;
1439 // load sign-extended word
1440 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1442 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1443 uimm12s4:$offset)))]>;
1445 // load zero-extended word
1446 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1447 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1450 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1451 [(AArch64Prefetch imm:$Rt,
1452 (am_indexed64 GPR64sp:$Rn,
1453 uimm12s8:$offset))]>;
1455 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1459 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1460 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1461 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1462 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1463 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1465 // load sign-extended word
1466 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1469 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1470 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1473 // (unscaled immediate)
1474 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1476 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1477 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1479 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1480 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1482 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1483 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1485 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1486 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1487 [(set (f32 FPR32:$Rt),
1488 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1489 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1490 [(set (f64 FPR64:$Rt),
1491 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1492 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1493 [(set (f128 FPR128:$Rt),
1494 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1497 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1499 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1501 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1503 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1505 // Match all load 64 bits width whose type is compatible with FPR64
1506 let Predicates = [IsLE] in {
1507 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1508 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1509 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1510 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1511 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1512 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1513 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1514 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1516 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1517 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1518 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1519 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1521 // Match all load 128 bits width whose type is compatible with FPR128
1522 let Predicates = [IsLE] in {
1523 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1524 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1525 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1526 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1527 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1528 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1529 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1530 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1531 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1532 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1533 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1534 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1538 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1539 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1540 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1541 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1542 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1543 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1544 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1545 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1546 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1547 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1548 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1549 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1550 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1551 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1553 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1554 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1555 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1556 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1557 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1558 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1559 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1560 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1561 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1562 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1563 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1564 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1565 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1566 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1570 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1572 // Define new assembler match classes as we want to only match these when
1573 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1574 // associate a DiagnosticType either, as we want the diagnostic for the
1575 // canonical form (the scaled operand) to take precedence.
1576 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1577 let Name = "SImm9OffsetFB" # Width;
1578 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1579 let RenderMethod = "addImmOperands";
1582 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1583 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1584 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1585 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1586 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1588 def simm9_offset_fb8 : Operand<i64> {
1589 let ParserMatchClass = SImm9OffsetFB8Operand;
1591 def simm9_offset_fb16 : Operand<i64> {
1592 let ParserMatchClass = SImm9OffsetFB16Operand;
1594 def simm9_offset_fb32 : Operand<i64> {
1595 let ParserMatchClass = SImm9OffsetFB32Operand;
1597 def simm9_offset_fb64 : Operand<i64> {
1598 let ParserMatchClass = SImm9OffsetFB64Operand;
1600 def simm9_offset_fb128 : Operand<i64> {
1601 let ParserMatchClass = SImm9OffsetFB128Operand;
1604 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1605 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1606 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1607 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1608 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1609 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1610 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1611 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1612 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1613 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1614 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1615 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1616 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1617 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1620 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1621 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1622 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1623 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1625 // load sign-extended half-word
1627 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1629 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1631 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1633 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1635 // load sign-extended byte
1637 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1639 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1641 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1643 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1645 // load sign-extended word
1647 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1649 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1651 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1652 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1653 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1654 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1655 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1656 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1657 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1658 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1659 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1660 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1661 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1662 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1663 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1664 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1665 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1668 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1669 [(AArch64Prefetch imm:$Rt,
1670 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1673 // (unscaled immediate, unprivileged)
1674 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1675 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1677 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1678 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1680 // load sign-extended half-word
1681 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1682 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1684 // load sign-extended byte
1685 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1686 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1688 // load sign-extended word
1689 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1692 // (immediate pre-indexed)
1693 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1694 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1695 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1696 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1697 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1698 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1699 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1701 // load sign-extended half-word
1702 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1703 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1705 // load sign-extended byte
1706 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1707 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1709 // load zero-extended byte
1710 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1711 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1713 // load sign-extended word
1714 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1717 // (immediate post-indexed)
1718 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1719 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1720 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1721 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1722 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1723 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1724 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1726 // load sign-extended half-word
1727 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1728 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1730 // load sign-extended byte
1731 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1732 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1734 // load zero-extended byte
1735 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1736 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1738 // load sign-extended word
1739 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1741 //===----------------------------------------------------------------------===//
1742 // Store instructions.
1743 //===----------------------------------------------------------------------===//
1745 // Pair (indexed, offset)
1746 // FIXME: Use dedicated range-checked addressing mode operand here.
1747 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1748 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1749 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1750 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1751 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1753 // Pair (pre-indexed)
1754 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1755 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1756 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1757 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1758 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1760 // Pair (pre-indexed)
1761 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1762 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1763 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1764 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1765 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1767 // Pair (no allocate)
1768 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1769 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1770 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1771 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1772 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1775 // (Register offset)
1778 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1779 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1780 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1781 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1785 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1786 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1787 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1788 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1789 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1791 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1792 Instruction STRW, Instruction STRX> {
1794 def : Pat<(storeop GPR64:$Rt,
1795 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1796 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1797 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1799 def : Pat<(storeop GPR64:$Rt,
1800 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1801 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1802 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1805 let AddedComplexity = 10 in {
1807 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1808 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1809 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1812 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1813 Instruction STRW, Instruction STRX> {
1814 def : Pat<(store (VecTy FPR:$Rt),
1815 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1816 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1818 def : Pat<(store (VecTy FPR:$Rt),
1819 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1820 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1823 let AddedComplexity = 10 in {
1824 // Match all store 64 bits width whose type is compatible with FPR64
1825 let Predicates = [IsLE] in {
1826 // We must use ST1 to store vectors in big-endian.
1827 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1828 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1829 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1830 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1833 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1834 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1836 // Match all store 128 bits width whose type is compatible with FPR128
1837 let Predicates = [IsLE] in {
1838 // We must use ST1 to store vectors in big-endian.
1839 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1840 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1841 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1842 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1843 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1844 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1846 } // AddedComplexity = 10
1849 // (unsigned immediate)
1850 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1852 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1853 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1855 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1856 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1858 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
1859 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1860 [(store (f16 FPR16:$Rt),
1861 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
1862 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1863 [(store (f32 FPR32:$Rt),
1864 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1865 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1866 [(store (f64 FPR64:$Rt),
1867 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1868 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1870 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1871 [(truncstorei16 GPR32:$Rt,
1872 (am_indexed16 GPR64sp:$Rn,
1873 uimm12s2:$offset))]>;
1874 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
1875 [(truncstorei8 GPR32:$Rt,
1876 (am_indexed8 GPR64sp:$Rn,
1877 uimm12s1:$offset))]>;
1879 // Match all store 64 bits width whose type is compatible with FPR64
1880 let AddedComplexity = 10 in {
1881 let Predicates = [IsLE] in {
1882 // We must use ST1 to store vectors in big-endian.
1883 def : Pat<(store (v2f32 FPR64:$Rt),
1884 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1885 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1886 def : Pat<(store (v8i8 FPR64:$Rt),
1887 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1888 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1889 def : Pat<(store (v4i16 FPR64:$Rt),
1890 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1891 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1892 def : Pat<(store (v2i32 FPR64:$Rt),
1893 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1894 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1896 def : Pat<(store (v1f64 FPR64:$Rt),
1897 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1898 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1899 def : Pat<(store (v1i64 FPR64:$Rt),
1900 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1901 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1903 // Match all store 128 bits width whose type is compatible with FPR128
1904 let Predicates = [IsLE] in {
1905 // We must use ST1 to store vectors in big-endian.
1906 def : Pat<(store (v4f32 FPR128:$Rt),
1907 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1908 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1909 def : Pat<(store (v2f64 FPR128:$Rt),
1910 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1911 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1912 def : Pat<(store (v16i8 FPR128:$Rt),
1913 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1914 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1915 def : Pat<(store (v8i16 FPR128:$Rt),
1916 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1917 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1918 def : Pat<(store (v4i32 FPR128:$Rt),
1919 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1920 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1921 def : Pat<(store (v2i64 FPR128:$Rt),
1922 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1923 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1925 def : Pat<(store (f128 FPR128:$Rt),
1926 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1927 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1930 def : Pat<(truncstorei32 GPR64:$Rt,
1931 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
1932 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
1933 def : Pat<(truncstorei16 GPR64:$Rt,
1934 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
1935 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
1936 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
1937 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
1939 } // AddedComplexity = 10
1942 // (unscaled immediate)
1943 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
1945 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1946 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
1948 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1949 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
1951 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1952 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
1953 [(store (f16 FPR16:$Rt),
1954 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1955 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
1956 [(store (f32 FPR32:$Rt),
1957 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1958 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
1959 [(store (f64 FPR64:$Rt),
1960 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1961 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
1962 [(store (f128 FPR128:$Rt),
1963 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
1964 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
1965 [(truncstorei16 GPR32:$Rt,
1966 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1967 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
1968 [(truncstorei8 GPR32:$Rt,
1969 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1971 // Match all store 64 bits width whose type is compatible with FPR64
1972 let Predicates = [IsLE] in {
1973 // We must use ST1 to store vectors in big-endian.
1974 def : Pat<(store (v2f32 FPR64:$Rt),
1975 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1976 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1977 def : Pat<(store (v8i8 FPR64:$Rt),
1978 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1979 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1980 def : Pat<(store (v4i16 FPR64:$Rt),
1981 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1982 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1983 def : Pat<(store (v2i32 FPR64:$Rt),
1984 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1985 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1987 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1988 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1989 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1990 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1992 // Match all store 128 bits width whose type is compatible with FPR128
1993 let Predicates = [IsLE] in {
1994 // We must use ST1 to store vectors in big-endian.
1995 def : Pat<(store (v4f32 FPR128:$Rt),
1996 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1997 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1998 def : Pat<(store (v2f64 FPR128:$Rt),
1999 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2000 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2001 def : Pat<(store (v16i8 FPR128:$Rt),
2002 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2003 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2004 def : Pat<(store (v8i16 FPR128:$Rt),
2005 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2006 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2007 def : Pat<(store (v4i32 FPR128:$Rt),
2008 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2009 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2010 def : Pat<(store (v2i64 FPR128:$Rt),
2011 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2012 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2013 def : Pat<(store (v2f64 FPR128:$Rt),
2014 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2015 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2018 // unscaled i64 truncating stores
2019 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2020 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2021 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2022 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2023 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2024 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2027 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2028 def : InstAlias<"str $Rt, [$Rn, $offset]",
2029 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2030 def : InstAlias<"str $Rt, [$Rn, $offset]",
2031 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2032 def : InstAlias<"str $Rt, [$Rn, $offset]",
2033 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2034 def : InstAlias<"str $Rt, [$Rn, $offset]",
2035 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2036 def : InstAlias<"str $Rt, [$Rn, $offset]",
2037 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2038 def : InstAlias<"str $Rt, [$Rn, $offset]",
2039 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2040 def : InstAlias<"str $Rt, [$Rn, $offset]",
2041 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2043 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2044 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2045 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2046 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2049 // (unscaled immediate, unprivileged)
2050 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2051 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2053 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2054 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2057 // (immediate pre-indexed)
2058 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2059 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2060 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2061 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2062 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2063 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2064 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2066 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2067 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2070 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2071 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2073 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2074 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2076 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2077 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2080 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2081 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2082 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2083 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2084 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2085 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2086 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2087 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2088 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2089 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2090 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2091 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2093 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2094 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2095 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2096 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2097 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2098 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2099 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2100 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2101 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2102 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2103 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2104 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2107 // (immediate post-indexed)
2108 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2109 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2110 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2111 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2112 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2113 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2114 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2116 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2117 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2120 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2121 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2123 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2124 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2126 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2127 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2130 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2131 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2132 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2133 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2134 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2135 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2136 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2137 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2138 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2139 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2140 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2141 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2143 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2144 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2145 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2146 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2147 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2148 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2149 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2150 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2151 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2152 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2153 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2154 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2156 //===----------------------------------------------------------------------===//
2157 // Load/store exclusive instructions.
2158 //===----------------------------------------------------------------------===//
2160 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2161 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2162 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2163 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2165 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2166 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2167 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2168 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2170 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2171 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2172 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2173 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2175 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2176 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2177 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2178 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2180 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2181 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2182 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2183 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2185 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2186 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2187 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2188 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2190 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2191 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2193 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2194 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2196 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2197 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2199 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2200 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2202 //===----------------------------------------------------------------------===//
2203 // Scaled floating point to integer conversion instructions.
2204 //===----------------------------------------------------------------------===//
2206 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2207 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2208 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2209 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2210 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2211 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2212 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2213 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2214 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2215 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2216 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2217 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2218 let isCodeGenOnly = 1 in {
2219 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2220 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2221 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2222 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2225 //===----------------------------------------------------------------------===//
2226 // Scaled integer to floating point conversion instructions.
2227 //===----------------------------------------------------------------------===//
2229 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2230 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2232 //===----------------------------------------------------------------------===//
2233 // Unscaled integer to floating point conversion instruction.
2234 //===----------------------------------------------------------------------===//
2236 defm FMOV : UnscaledConversion<"fmov">;
2238 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
2239 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
2241 //===----------------------------------------------------------------------===//
2242 // Floating point conversion instruction.
2243 //===----------------------------------------------------------------------===//
2245 defm FCVT : FPConversion<"fcvt">;
2247 def : Pat<(fp_to_f16 FPR32:$Rn),
2248 (i32 (COPY_TO_REGCLASS
2249 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
2252 def : Pat<(f32 (f16_to_fp i32:$Rn)),
2253 (FCVTSHr (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS i32:$Rn, FPR32)),
2256 // When converting from f16 coming directly from a load, make sure we
2257 // load into the FPR16 registers rather than going through the GPRs.
2259 def : Pat<(f32 (f16_to_fp (i32
2260 (zextloadi16 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2261 ro_Wextend16:$extend))))),
2262 (FCVTSHr (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend))>;
2263 def : Pat<(f32 (f16_to_fp (i32
2264 (zextloadi16 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2265 ro_Xextend16:$extend))))),
2266 (FCVTSHr (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend))>;
2267 def : Pat <(f32 (f16_to_fp (i32
2268 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
2269 (FCVTSHr (LDRHui GPR64sp:$Rn, uimm12s2:$offset))>;
2270 def : Pat <(f32 (f16_to_fp (i32
2271 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
2272 (FCVTSHr (LDURHi GPR64sp:$Rn, simm9:$offset))>;
2275 def : Pat<(f64 (fextend (f32 (f16_to_fp (i32
2276 (zextloadi16 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2277 ro_Wextend16:$extend))))))),
2278 (FCVTDHr (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend))>;
2279 def : Pat<(f64 (fextend (f32 (f16_to_fp (i32
2280 (zextloadi16 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2281 ro_Xextend16:$extend))))))),
2282 (FCVTDHr (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend))>;
2283 def : Pat <(f64 (fextend (f32 (f16_to_fp (i32
2284 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))))),
2285 (FCVTDHr (LDRHui GPR64sp:$Rn, uimm12s2:$offset))>;
2286 def : Pat <(f64 (fextend (f32 (f16_to_fp (i32
2287 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))))),
2288 (FCVTDHr (LDURHi GPR64sp:$Rn, simm9:$offset))>;
2290 // When converting to f16 going directly to a store, make sure we use the
2291 // appropriate direct conversion instructions and store via the FPR16
2292 // registers rather than going through the GPRs.
2293 let AddedComplexity = 10 in {
2295 def : Pat< (truncstorei16 (assertzext (i32 (fp_to_f16 FPR32:$Rt))),
2296 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2297 ro_Wextend16:$extend)),
2298 (STRHroW (FCVTHSr FPR32:$Rt), GPR64sp:$Rn, GPR32:$Rm,
2299 ro_Wextend16:$extend)>;
2300 def : Pat< (truncstorei16 (assertzext (i32 (fp_to_f16 FPR32:$Rt))),
2301 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2302 ro_Xextend16:$extend)),
2303 (STRHroX (FCVTHSr FPR32:$Rt), GPR64sp:$Rn, GPR64:$Rm,
2304 ro_Xextend16:$extend)>;
2305 def : Pat <(truncstorei16 (assertzext (i32 (fp_to_f16 FPR32:$Rt))),
2306 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2307 (STRHui (FCVTHSr FPR32:$Rt), GPR64sp:$Rn, uimm12s2:$offset)>;
2308 def : Pat <(truncstorei16 (assertzext (i32 (fp_to_f16 FPR32:$Rt))),
2309 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2310 (STURHi (FCVTHSr FPR32:$Rt), GPR64sp:$Rn, simm9:$offset)>;
2312 def : Pat< (truncstorei16 (assertzext (i32 (fp_to_f16 (f32 (fround FPR64:$Rt))))),
2313 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2314 ro_Wextend16:$extend)),
2315 (STRHroW (FCVTHDr FPR64:$Rt), GPR64sp:$Rn, GPR32:$Rm,
2316 ro_Wextend16:$extend)>;
2317 def : Pat< (truncstorei16 (assertzext (i32 (fp_to_f16 (f32 (fround FPR64:$Rt))))),
2318 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2319 ro_Xextend16:$extend)),
2320 (STRHroX (FCVTHDr FPR64:$Rt), GPR64sp:$Rn, GPR64:$Rm,
2321 ro_Xextend16:$extend)>;
2322 def : Pat <(truncstorei16 (assertzext (i32 (fp_to_f16 (f32 (fround FPR64:$Rt))))),
2323 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2324 (STRHui (FCVTHDr FPR64:$Rt), GPR64sp:$Rn, uimm12s2:$offset)>;
2325 def : Pat <(truncstorei16 (assertzext (i32 (fp_to_f16 (f32 (fround FPR64:$Rt))))),
2326 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2327 (STURHi (FCVTHDr FPR64:$Rt), GPR64sp:$Rn, simm9:$offset)>;
2331 //===----------------------------------------------------------------------===//
2332 // Floating point single operand instructions.
2333 //===----------------------------------------------------------------------===//
2335 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2336 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2337 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2338 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2339 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2340 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2341 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2342 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2344 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2345 (FRINTNDr FPR64:$Rn)>;
2347 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2348 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2349 // <rdar://problem/13715968>
2350 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2351 let hasSideEffects = 1 in {
2352 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2355 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2357 let SchedRW = [WriteFDiv] in {
2358 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2361 //===----------------------------------------------------------------------===//
2362 // Floating point two operand instructions.
2363 //===----------------------------------------------------------------------===//
2365 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2366 let SchedRW = [WriteFDiv] in {
2367 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2369 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2370 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2371 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2372 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2373 let SchedRW = [WriteFMul] in {
2374 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2375 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2377 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2379 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2380 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2381 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2382 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2383 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2384 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2385 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2386 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2388 //===----------------------------------------------------------------------===//
2389 // Floating point three operand instructions.
2390 //===----------------------------------------------------------------------===//
2392 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2393 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2394 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2395 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2396 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2397 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2398 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2400 // The following def pats catch the case where the LHS of an FMA is negated.
2401 // The TriOpFrag above catches the case where the middle operand is negated.
2403 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2404 // the NEON variant.
2405 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2406 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2408 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2409 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2411 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2413 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2414 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2416 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2417 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2419 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2420 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2422 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2423 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2425 //===----------------------------------------------------------------------===//
2426 // Floating point comparison instructions.
2427 //===----------------------------------------------------------------------===//
2429 defm FCMPE : FPComparison<1, "fcmpe">;
2430 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2432 //===----------------------------------------------------------------------===//
2433 // Floating point conditional comparison instructions.
2434 //===----------------------------------------------------------------------===//
2436 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2437 defm FCCMP : FPCondComparison<0, "fccmp">;
2439 //===----------------------------------------------------------------------===//
2440 // Floating point conditional select instruction.
2441 //===----------------------------------------------------------------------===//
2443 defm FCSEL : FPCondSelect<"fcsel">;
2445 // CSEL instructions providing f128 types need to be handled by a
2446 // pseudo-instruction since the eventual code will need to introduce basic
2447 // blocks and control flow.
2448 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2449 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2450 [(set (f128 FPR128:$Rd),
2451 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2452 (i32 imm:$cond), NZCV))]> {
2454 let usesCustomInserter = 1;
2458 //===----------------------------------------------------------------------===//
2459 // Floating point immediate move.
2460 //===----------------------------------------------------------------------===//
2462 let isReMaterializable = 1 in {
2463 defm FMOV : FPMoveImmediate<"fmov">;
2466 //===----------------------------------------------------------------------===//
2467 // Advanced SIMD two vector instructions.
2468 //===----------------------------------------------------------------------===//
2470 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2471 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2472 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2473 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2474 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2475 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2476 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2477 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2478 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2479 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2481 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2482 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2483 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2484 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2485 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2486 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2487 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2488 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2489 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2490 (FCVTLv4i16 V64:$Rn)>;
2491 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2493 (FCVTLv8i16 V128:$Rn)>;
2494 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2495 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2497 (FCVTLv4i32 V128:$Rn)>;
2499 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2500 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2501 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2502 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2503 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2504 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2505 (FCVTNv4i16 V128:$Rn)>;
2506 def : Pat<(concat_vectors V64:$Rd,
2507 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2508 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2509 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2510 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2511 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2512 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2513 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2514 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2515 int_aarch64_neon_fcvtxn>;
2516 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2517 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2518 let isCodeGenOnly = 1 in {
2519 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2520 int_aarch64_neon_fcvtzs>;
2521 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2522 int_aarch64_neon_fcvtzu>;
2524 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2525 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2526 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2527 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2528 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2529 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2530 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2531 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2532 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2533 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2534 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2535 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2536 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2537 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2538 // Aliases for MVN -> NOT.
2539 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2540 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2541 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2542 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2544 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2545 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2546 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2547 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2548 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2549 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2550 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2552 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2553 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2554 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2555 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2556 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2557 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2558 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2559 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2561 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2562 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2563 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2564 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2565 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2567 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2568 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2569 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2570 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2571 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2572 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2573 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2574 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2575 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2576 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2577 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2578 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2579 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2580 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2581 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2582 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2583 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2584 int_aarch64_neon_uaddlp>;
2585 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2586 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2587 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2588 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2589 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2590 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2592 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2593 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2595 // Patterns for vector long shift (by element width). These need to match all
2596 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2598 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2599 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2600 (SHLLv8i8 V64:$Rn)>;
2601 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2602 (SHLLv16i8 V128:$Rn)>;
2603 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2604 (SHLLv4i16 V64:$Rn)>;
2605 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2606 (SHLLv8i16 V128:$Rn)>;
2607 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2608 (SHLLv2i32 V64:$Rn)>;
2609 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2610 (SHLLv4i32 V128:$Rn)>;
2613 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2614 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2615 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2617 //===----------------------------------------------------------------------===//
2618 // Advanced SIMD three vector instructions.
2619 //===----------------------------------------------------------------------===//
2621 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2622 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2623 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2624 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2625 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2626 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2627 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2628 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2629 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2630 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2631 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2632 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2633 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2634 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2635 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2636 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2637 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2638 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2639 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2640 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2641 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2642 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2643 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2644 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2645 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2647 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2648 // instruction expects the addend first, while the fma intrinsic puts it last.
2649 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2650 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2651 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2652 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2654 // The following def pats catch the case where the LHS of an FMA is negated.
2655 // The TriOpFrag above catches the case where the middle operand is negated.
2656 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2657 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2659 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2660 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2662 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2663 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2665 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2666 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2667 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2668 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2669 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2670 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2671 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2672 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2673 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2674 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2675 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2676 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2677 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2678 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2679 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2680 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2681 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2682 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2683 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2684 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2685 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2686 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2687 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2688 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2689 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2690 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2691 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2692 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2693 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2694 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2695 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2696 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2697 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2698 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2699 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2700 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2701 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2702 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2703 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2704 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2705 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2706 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2707 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2708 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2709 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2710 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2712 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2713 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2714 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2715 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2716 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2717 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2718 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2719 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2720 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2721 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2722 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2724 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2725 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2726 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2727 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2728 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2729 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2730 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2731 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2733 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2734 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2735 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2736 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2737 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2738 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2739 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2740 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2742 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2743 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2744 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2745 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2746 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2747 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2748 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2749 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2751 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2752 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2753 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2754 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2755 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2756 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2757 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2758 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2760 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2761 "|cmls.8b\t$dst, $src1, $src2}",
2762 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2763 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2764 "|cmls.16b\t$dst, $src1, $src2}",
2765 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2766 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2767 "|cmls.4h\t$dst, $src1, $src2}",
2768 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2769 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2770 "|cmls.8h\t$dst, $src1, $src2}",
2771 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2772 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2773 "|cmls.2s\t$dst, $src1, $src2}",
2774 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2775 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2776 "|cmls.4s\t$dst, $src1, $src2}",
2777 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2778 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2779 "|cmls.2d\t$dst, $src1, $src2}",
2780 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2782 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2783 "|cmlo.8b\t$dst, $src1, $src2}",
2784 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2785 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2786 "|cmlo.16b\t$dst, $src1, $src2}",
2787 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2788 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2789 "|cmlo.4h\t$dst, $src1, $src2}",
2790 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2791 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2792 "|cmlo.8h\t$dst, $src1, $src2}",
2793 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2794 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2795 "|cmlo.2s\t$dst, $src1, $src2}",
2796 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2797 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2798 "|cmlo.4s\t$dst, $src1, $src2}",
2799 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2800 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2801 "|cmlo.2d\t$dst, $src1, $src2}",
2802 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2804 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2805 "|cmle.8b\t$dst, $src1, $src2}",
2806 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2807 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2808 "|cmle.16b\t$dst, $src1, $src2}",
2809 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2810 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2811 "|cmle.4h\t$dst, $src1, $src2}",
2812 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2813 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2814 "|cmle.8h\t$dst, $src1, $src2}",
2815 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2816 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2817 "|cmle.2s\t$dst, $src1, $src2}",
2818 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2819 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2820 "|cmle.4s\t$dst, $src1, $src2}",
2821 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2822 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2823 "|cmle.2d\t$dst, $src1, $src2}",
2824 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2826 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2827 "|cmlt.8b\t$dst, $src1, $src2}",
2828 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2829 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2830 "|cmlt.16b\t$dst, $src1, $src2}",
2831 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2832 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2833 "|cmlt.4h\t$dst, $src1, $src2}",
2834 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2835 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2836 "|cmlt.8h\t$dst, $src1, $src2}",
2837 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2838 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2839 "|cmlt.2s\t$dst, $src1, $src2}",
2840 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2841 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2842 "|cmlt.4s\t$dst, $src1, $src2}",
2843 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2844 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2845 "|cmlt.2d\t$dst, $src1, $src2}",
2846 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2848 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2849 "|fcmle.2s\t$dst, $src1, $src2}",
2850 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2851 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2852 "|fcmle.4s\t$dst, $src1, $src2}",
2853 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2854 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2855 "|fcmle.2d\t$dst, $src1, $src2}",
2856 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2858 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2859 "|fcmlt.2s\t$dst, $src1, $src2}",
2860 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2861 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2862 "|fcmlt.4s\t$dst, $src1, $src2}",
2863 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2864 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2865 "|fcmlt.2d\t$dst, $src1, $src2}",
2866 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2868 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2869 "|facle.2s\t$dst, $src1, $src2}",
2870 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2871 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2872 "|facle.4s\t$dst, $src1, $src2}",
2873 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2874 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2875 "|facle.2d\t$dst, $src1, $src2}",
2876 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2878 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2879 "|faclt.2s\t$dst, $src1, $src2}",
2880 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2881 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2882 "|faclt.4s\t$dst, $src1, $src2}",
2883 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2884 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2885 "|faclt.2d\t$dst, $src1, $src2}",
2886 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2888 //===----------------------------------------------------------------------===//
2889 // Advanced SIMD three scalar instructions.
2890 //===----------------------------------------------------------------------===//
2892 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2893 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
2894 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
2895 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
2896 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
2897 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
2898 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
2899 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
2900 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2901 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2902 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2903 int_aarch64_neon_facge>;
2904 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2905 int_aarch64_neon_facgt>;
2906 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2907 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2908 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2909 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
2910 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
2911 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
2912 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
2913 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
2914 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
2915 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
2916 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
2917 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
2918 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
2919 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
2920 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2921 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
2922 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
2923 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
2924 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
2925 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
2926 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
2928 def : InstAlias<"cmls $dst, $src1, $src2",
2929 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2930 def : InstAlias<"cmle $dst, $src1, $src2",
2931 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2932 def : InstAlias<"cmlo $dst, $src1, $src2",
2933 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2934 def : InstAlias<"cmlt $dst, $src1, $src2",
2935 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2936 def : InstAlias<"fcmle $dst, $src1, $src2",
2937 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2938 def : InstAlias<"fcmle $dst, $src1, $src2",
2939 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2940 def : InstAlias<"fcmlt $dst, $src1, $src2",
2941 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2942 def : InstAlias<"fcmlt $dst, $src1, $src2",
2943 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2944 def : InstAlias<"facle $dst, $src1, $src2",
2945 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2946 def : InstAlias<"facle $dst, $src1, $src2",
2947 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2948 def : InstAlias<"faclt $dst, $src1, $src2",
2949 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2950 def : InstAlias<"faclt $dst, $src1, $src2",
2951 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2953 //===----------------------------------------------------------------------===//
2954 // Advanced SIMD three scalar instructions (mixed operands).
2955 //===----------------------------------------------------------------------===//
2956 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2957 int_aarch64_neon_sqdmulls_scalar>;
2958 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2959 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2961 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
2962 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2963 (i32 FPR32:$Rm))))),
2964 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2965 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
2966 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2967 (i32 FPR32:$Rm))))),
2968 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2970 //===----------------------------------------------------------------------===//
2971 // Advanced SIMD two scalar instructions.
2972 //===----------------------------------------------------------------------===//
2974 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
2975 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
2976 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
2977 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
2978 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
2979 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
2980 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2981 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2982 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2983 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2984 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2985 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2986 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2987 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2988 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2989 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2990 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2991 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2992 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2993 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2994 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2995 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2996 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2997 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2998 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2999 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3000 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3001 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3002 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3003 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3004 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3005 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3006 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3007 int_aarch64_neon_suqadd>;
3008 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3009 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3010 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3011 int_aarch64_neon_usqadd>;
3013 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3015 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3016 (FCVTASv1i64 FPR64:$Rn)>;
3017 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3018 (FCVTAUv1i64 FPR64:$Rn)>;
3019 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3020 (FCVTMSv1i64 FPR64:$Rn)>;
3021 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3022 (FCVTMUv1i64 FPR64:$Rn)>;
3023 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3024 (FCVTNSv1i64 FPR64:$Rn)>;
3025 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3026 (FCVTNUv1i64 FPR64:$Rn)>;
3027 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3028 (FCVTPSv1i64 FPR64:$Rn)>;
3029 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3030 (FCVTPUv1i64 FPR64:$Rn)>;
3032 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3033 (FRECPEv1i32 FPR32:$Rn)>;
3034 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3035 (FRECPEv1i64 FPR64:$Rn)>;
3036 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3037 (FRECPEv1i64 FPR64:$Rn)>;
3039 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3040 (FRECPXv1i32 FPR32:$Rn)>;
3041 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3042 (FRECPXv1i64 FPR64:$Rn)>;
3044 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3045 (FRSQRTEv1i32 FPR32:$Rn)>;
3046 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3047 (FRSQRTEv1i64 FPR64:$Rn)>;
3048 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3049 (FRSQRTEv1i64 FPR64:$Rn)>;
3051 // If an integer is about to be converted to a floating point value,
3052 // just load it on the floating point unit.
3053 // Here are the patterns for 8 and 16-bits to float.
3055 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3056 SDPatternOperator loadop, Instruction UCVTF,
3057 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3059 def : Pat<(DstTy (uint_to_fp (SrcTy
3060 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3061 ro.Wext:$extend))))),
3062 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3063 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3066 def : Pat<(DstTy (uint_to_fp (SrcTy
3067 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3068 ro.Wext:$extend))))),
3069 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3070 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3074 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3075 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3076 def : Pat <(f32 (uint_to_fp (i32
3077 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3078 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3079 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3080 def : Pat <(f32 (uint_to_fp (i32
3081 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3082 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3083 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3084 // 16-bits -> float.
3085 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3086 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3087 def : Pat <(f32 (uint_to_fp (i32
3088 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3089 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3090 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3091 def : Pat <(f32 (uint_to_fp (i32
3092 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3093 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3094 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3095 // 32-bits are handled in target specific dag combine:
3096 // performIntToFpCombine.
3097 // 64-bits integer to 32-bits floating point, not possible with
3098 // UCVTF on floating point registers (both source and destination
3099 // must have the same size).
3101 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3102 // 8-bits -> double.
3103 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3104 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3105 def : Pat <(f64 (uint_to_fp (i32
3106 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3107 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3108 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3109 def : Pat <(f64 (uint_to_fp (i32
3110 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3111 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3112 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3113 // 16-bits -> double.
3114 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3115 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3116 def : Pat <(f64 (uint_to_fp (i32
3117 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3118 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3119 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3120 def : Pat <(f64 (uint_to_fp (i32
3121 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3122 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3123 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3124 // 32-bits -> double.
3125 defm : UIntToFPROLoadPat<f64, i32, load,
3126 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3127 def : Pat <(f64 (uint_to_fp (i32
3128 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3129 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3130 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3131 def : Pat <(f64 (uint_to_fp (i32
3132 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3133 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3134 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3135 // 64-bits -> double are handled in target specific dag combine:
3136 // performIntToFpCombine.
3138 //===----------------------------------------------------------------------===//
3139 // Advanced SIMD three different-sized vector instructions.
3140 //===----------------------------------------------------------------------===//
3142 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3143 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3144 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3145 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3146 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3147 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3148 int_aarch64_neon_sabd>;
3149 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3150 int_aarch64_neon_sabd>;
3151 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3152 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3153 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3154 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3155 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3156 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3157 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3158 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3159 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3160 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3161 int_aarch64_neon_sqadd>;
3162 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3163 int_aarch64_neon_sqsub>;
3164 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3165 int_aarch64_neon_sqdmull>;
3166 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3167 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3168 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3169 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3170 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3171 int_aarch64_neon_uabd>;
3172 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3173 int_aarch64_neon_uabd>;
3174 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3175 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3176 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3177 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3178 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3179 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3180 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3181 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3182 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3183 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3184 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3185 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3186 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3188 // Patterns for 64-bit pmull
3189 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3190 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3191 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3192 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3193 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3195 // CodeGen patterns for addhn and subhn instructions, which can actually be
3196 // written in LLVM IR without too much difficulty.
3199 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3200 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3201 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3203 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3204 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3206 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3207 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3208 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3210 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3211 V128:$Rn, V128:$Rm)>;
3212 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3213 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3215 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3216 V128:$Rn, V128:$Rm)>;
3217 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3218 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3220 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3221 V128:$Rn, V128:$Rm)>;
3224 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3225 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3226 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3228 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3229 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3231 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3232 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3233 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3235 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3236 V128:$Rn, V128:$Rm)>;
3237 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3238 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3240 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3241 V128:$Rn, V128:$Rm)>;
3242 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3243 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3245 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3246 V128:$Rn, V128:$Rm)>;
3248 //----------------------------------------------------------------------------
3249 // AdvSIMD bitwise extract from vector instruction.
3250 //----------------------------------------------------------------------------
3252 defm EXT : SIMDBitwiseExtract<"ext">;
3254 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3255 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3256 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3257 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3258 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3259 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3260 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3261 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3262 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3263 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3264 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3265 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3266 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3267 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3268 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3269 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3271 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3273 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3274 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3275 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3276 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3277 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3278 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3279 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3280 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3281 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3282 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3283 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3284 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3287 //----------------------------------------------------------------------------
3288 // AdvSIMD zip vector
3289 //----------------------------------------------------------------------------
3291 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3292 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3293 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3294 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3295 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3296 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3298 //----------------------------------------------------------------------------
3299 // AdvSIMD TBL/TBX instructions
3300 //----------------------------------------------------------------------------
3302 defm TBL : SIMDTableLookup< 0, "tbl">;
3303 defm TBX : SIMDTableLookupTied<1, "tbx">;
3305 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3306 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3307 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3308 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3310 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3311 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3312 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3313 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3314 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3315 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3318 //----------------------------------------------------------------------------
3319 // AdvSIMD scalar CPY instruction
3320 //----------------------------------------------------------------------------
3322 defm CPY : SIMDScalarCPY<"cpy">;
3324 //----------------------------------------------------------------------------
3325 // AdvSIMD scalar pairwise instructions
3326 //----------------------------------------------------------------------------
3328 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3329 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3330 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3331 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3332 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3333 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3334 def : Pat<(i64 (int_aarch64_neon_saddv (v2i64 V128:$Rn))),
3335 (ADDPv2i64p V128:$Rn)>;
3336 def : Pat<(i64 (int_aarch64_neon_uaddv (v2i64 V128:$Rn))),
3337 (ADDPv2i64p V128:$Rn)>;
3338 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3339 (FADDPv2i32p V64:$Rn)>;
3340 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3341 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3342 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3343 (FADDPv2i64p V128:$Rn)>;
3344 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3345 (FMAXNMPv2i32p V64:$Rn)>;
3346 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3347 (FMAXNMPv2i64p V128:$Rn)>;
3348 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3349 (FMAXPv2i32p V64:$Rn)>;
3350 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3351 (FMAXPv2i64p V128:$Rn)>;
3352 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3353 (FMINNMPv2i32p V64:$Rn)>;
3354 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3355 (FMINNMPv2i64p V128:$Rn)>;
3356 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3357 (FMINPv2i32p V64:$Rn)>;
3358 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3359 (FMINPv2i64p V128:$Rn)>;
3361 //----------------------------------------------------------------------------
3362 // AdvSIMD INS/DUP instructions
3363 //----------------------------------------------------------------------------
3365 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3366 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3367 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3368 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3369 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3370 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3371 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3373 def DUPv2i64lane : SIMDDup64FromElement;
3374 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3375 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3376 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3377 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3378 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3379 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3381 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3382 (v2f32 (DUPv2i32lane
3383 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3385 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3386 (v4f32 (DUPv4i32lane
3387 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3389 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3390 (v2f64 (DUPv2i64lane
3391 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3394 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3395 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3396 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3397 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3398 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3399 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3401 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3402 // instruction even if the types don't match: we just have to remap the lane
3403 // carefully. N.b. this trick only applies to truncations.
3404 def VecIndex_x2 : SDNodeXForm<imm, [{
3405 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3407 def VecIndex_x4 : SDNodeXForm<imm, [{
3408 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3410 def VecIndex_x8 : SDNodeXForm<imm, [{
3411 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3414 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3415 ValueType Src128VT, ValueType ScalVT,
3416 Instruction DUP, SDNodeXForm IdxXFORM> {
3417 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3419 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3421 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3423 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3426 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3427 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3428 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3430 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3431 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3432 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3434 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3435 SDNodeXForm IdxXFORM> {
3436 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3438 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3440 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3442 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3445 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3446 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3447 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3449 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3450 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3451 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3453 // SMOV and UMOV definitions, with some extra patterns for convenience
3457 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3458 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3459 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3460 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3461 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3462 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3463 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3464 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3465 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3466 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3467 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3468 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3470 // Extracting i8 or i16 elements will have the zero-extend transformed to
3471 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3472 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3473 // bits of the destination register.
3474 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3476 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3477 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3479 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3483 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3484 (SUBREG_TO_REG (i32 0),
3485 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3486 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3487 (SUBREG_TO_REG (i32 0),
3488 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3490 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3491 (SUBREG_TO_REG (i32 0),
3492 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3493 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3494 (SUBREG_TO_REG (i32 0),
3495 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3497 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3498 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3499 (i32 FPR32:$Rn), ssub))>;
3500 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3501 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3502 (i32 FPR32:$Rn), ssub))>;
3503 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3504 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3505 (i64 FPR64:$Rn), dsub))>;
3507 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3508 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3509 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3510 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3511 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3512 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3514 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3515 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3518 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3520 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3523 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3524 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3526 V128:$Rn, VectorIndexS:$imm,
3527 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3529 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3530 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3532 V128:$Rn, VectorIndexD:$imm,
3533 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3536 // Copy an element at a constant index in one vector into a constant indexed
3537 // element of another.
3538 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3539 // index type and INS extension
3540 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3541 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3542 VectorIndexB:$idx2)),
3544 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3546 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3547 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3548 VectorIndexH:$idx2)),
3550 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3552 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3553 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3554 VectorIndexS:$idx2)),
3556 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3558 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3559 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3560 VectorIndexD:$idx2)),
3562 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3565 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3566 ValueType VTScal, Instruction INS> {
3567 def : Pat<(VT128 (vector_insert V128:$src,
3568 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3570 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3572 def : Pat<(VT128 (vector_insert V128:$src,
3573 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3575 (INS V128:$src, imm:$Immd,
3576 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3578 def : Pat<(VT64 (vector_insert V64:$src,
3579 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3581 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3582 imm:$Immd, V128:$Rn, imm:$Immn),
3585 def : Pat<(VT64 (vector_insert V64:$src,
3586 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3589 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3590 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3594 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3595 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3596 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3597 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3598 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3599 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3602 // Floating point vector extractions are codegen'd as either a sequence of
3603 // subregister extractions, possibly fed by an INS if the lane number is
3604 // anything other than zero.
3605 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3606 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3607 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3608 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3609 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3610 (f64 (EXTRACT_SUBREG
3611 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3612 V128:$Rn, VectorIndexD:$idx),
3614 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3615 (f32 (EXTRACT_SUBREG
3616 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3617 V128:$Rn, VectorIndexS:$idx),
3620 // All concat_vectors operations are canonicalised to act on i64 vectors for
3621 // AArch64. In the general case we need an instruction, which had just as well be
3623 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3624 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3625 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3626 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3628 def : ConcatPat<v2i64, v1i64>;
3629 def : ConcatPat<v2f64, v1f64>;
3630 def : ConcatPat<v4i32, v2i32>;
3631 def : ConcatPat<v4f32, v2f32>;
3632 def : ConcatPat<v8i16, v4i16>;
3633 def : ConcatPat<v16i8, v8i8>;
3635 // If the high lanes are undef, though, we can just ignore them:
3636 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3637 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3638 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3640 def : ConcatUndefPat<v2i64, v1i64>;
3641 def : ConcatUndefPat<v2f64, v1f64>;
3642 def : ConcatUndefPat<v4i32, v2i32>;
3643 def : ConcatUndefPat<v4f32, v2f32>;
3644 def : ConcatUndefPat<v8i16, v4i16>;
3645 def : ConcatUndefPat<v16i8, v8i8>;
3647 //----------------------------------------------------------------------------
3648 // AdvSIMD across lanes instructions
3649 //----------------------------------------------------------------------------
3651 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3652 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3653 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3654 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3655 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3656 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3657 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3658 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3659 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3660 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3661 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3663 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3664 // If there is a sign extension after this intrinsic, consume it as smov already
3666 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3668 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3669 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3671 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3673 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3674 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3676 // If there is a sign extension after this intrinsic, consume it as smov already
3678 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3680 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3681 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3683 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3685 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3686 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3688 // If there is a sign extension after this intrinsic, consume it as smov already
3690 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3692 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3693 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3695 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3697 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3698 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3700 // If there is a sign extension after this intrinsic, consume it as smov already
3702 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3704 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3705 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3707 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3709 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3710 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3713 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3714 (i32 (EXTRACT_SUBREG
3715 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3716 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3720 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3721 // If there is a masking operation keeping only what has been actually
3722 // generated, consume it.
3723 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3724 (i32 (EXTRACT_SUBREG
3725 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3726 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3728 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3729 (i32 (EXTRACT_SUBREG
3730 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3731 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3733 // If there is a masking operation keeping only what has been actually
3734 // generated, consume it.
3735 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3736 (i32 (EXTRACT_SUBREG
3737 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3738 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3740 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3741 (i32 (EXTRACT_SUBREG
3742 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3743 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3746 // If there is a masking operation keeping only what has been actually
3747 // generated, consume it.
3748 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3749 (i32 (EXTRACT_SUBREG
3750 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3751 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3753 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3754 (i32 (EXTRACT_SUBREG
3755 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3756 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3758 // If there is a masking operation keeping only what has been actually
3759 // generated, consume it.
3760 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3761 (i32 (EXTRACT_SUBREG
3762 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3763 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3765 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3766 (i32 (EXTRACT_SUBREG
3767 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3768 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3771 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3772 (i32 (EXTRACT_SUBREG
3773 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3774 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3779 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3780 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3782 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3783 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3785 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3787 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3788 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3791 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3792 (i32 (EXTRACT_SUBREG
3793 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3794 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3796 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3797 (i32 (EXTRACT_SUBREG
3798 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3799 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3802 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3803 (i64 (EXTRACT_SUBREG
3804 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3805 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3809 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3811 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3812 (i32 (EXTRACT_SUBREG
3813 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3814 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3816 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3817 (i32 (EXTRACT_SUBREG
3818 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3819 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3822 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3823 (i32 (EXTRACT_SUBREG
3824 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3825 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3827 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3828 (i32 (EXTRACT_SUBREG
3829 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3830 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3833 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3834 (i64 (EXTRACT_SUBREG
3835 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3836 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3840 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_aarch64_neon_saddv>;
3841 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3842 def : Pat<(i32 (int_aarch64_neon_saddv (v2i32 V64:$Rn))),
3843 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3845 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_aarch64_neon_uaddv>;
3846 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3847 def : Pat<(i32 (int_aarch64_neon_uaddv (v2i32 V64:$Rn))),
3848 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3850 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_aarch64_neon_smaxv>;
3851 def : Pat<(i32 (int_aarch64_neon_smaxv (v2i32 V64:$Rn))),
3852 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3854 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_aarch64_neon_sminv>;
3855 def : Pat<(i32 (int_aarch64_neon_sminv (v2i32 V64:$Rn))),
3856 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3858 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_aarch64_neon_umaxv>;
3859 def : Pat<(i32 (int_aarch64_neon_umaxv (v2i32 V64:$Rn))),
3860 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3862 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_aarch64_neon_uminv>;
3863 def : Pat<(i32 (int_aarch64_neon_uminv (v2i32 V64:$Rn))),
3864 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3866 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
3867 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
3869 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3870 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
3871 (i64 (EXTRACT_SUBREG
3872 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3873 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3875 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3876 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
3877 (i64 (EXTRACT_SUBREG
3878 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3879 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3882 //------------------------------------------------------------------------------
3883 // AdvSIMD modified immediate instructions
3884 //------------------------------------------------------------------------------
3887 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
3889 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
3891 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3892 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3893 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3894 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3896 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3897 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3898 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3899 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3901 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3902 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3903 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3904 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3906 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3907 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3908 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3909 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3912 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3914 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3915 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3917 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3918 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3920 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3924 // EDIT byte mask: scalar
3925 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3926 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3927 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3928 // The movi_edit node has the immediate value already encoded, so we use
3929 // a plain imm0_255 here.
3930 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
3931 (MOVID imm0_255:$shift)>;
3933 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3934 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3935 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3936 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3938 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3939 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3940 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3941 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3943 // EDIT byte mask: 2d
3945 // The movi_edit node has the immediate value already encoded, so we use
3946 // a plain imm0_255 in the pattern
3947 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3948 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3951 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
3954 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3955 // Complexity is added to break a tie with a plain MOVI.
3956 let AddedComplexity = 1 in {
3957 def : Pat<(f32 fpimm0),
3958 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3960 def : Pat<(f64 fpimm0),
3961 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3965 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3966 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3967 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3968 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3970 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3971 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3972 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3973 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3975 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
3976 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
3978 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3979 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3981 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3982 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3983 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3984 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3986 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3987 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3988 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3989 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3991 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3992 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3993 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3994 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3995 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3996 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3997 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3998 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4000 // EDIT per word: 2s & 4s with MSL shifter
4001 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4002 [(set (v2i32 V64:$Rd),
4003 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4004 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4005 [(set (v4i32 V128:$Rd),
4006 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4008 // Per byte: 8b & 16b
4009 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4011 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4012 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4014 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4018 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4019 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4021 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4022 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4023 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4024 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4026 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4027 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4028 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4029 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4031 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4032 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4033 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4034 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4035 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4036 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4037 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4038 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4040 // EDIT per word: 2s & 4s with MSL shifter
4041 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4042 [(set (v2i32 V64:$Rd),
4043 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4044 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4045 [(set (v4i32 V128:$Rd),
4046 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4048 //----------------------------------------------------------------------------
4049 // AdvSIMD indexed element
4050 //----------------------------------------------------------------------------
4052 let neverHasSideEffects = 1 in {
4053 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
4054 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
4057 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4058 // instruction expects the addend first, while the intrinsic expects it last.
4060 // On the other hand, there are quite a few valid combinatorial options due to
4061 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4062 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4063 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4064 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4065 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4067 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4068 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4069 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4070 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4071 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4072 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4073 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4074 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4076 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4077 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4079 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4080 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4081 VectorIndexS:$idx))),
4082 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4083 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4084 (v2f32 (AArch64duplane32
4085 (v4f32 (insert_subvector undef,
4086 (v2f32 (fneg V64:$Rm)),
4088 VectorIndexS:$idx)))),
4089 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4090 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4091 VectorIndexS:$idx)>;
4092 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4093 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4094 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4095 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4097 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4099 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4100 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4101 VectorIndexS:$idx))),
4102 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4103 VectorIndexS:$idx)>;
4104 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4105 (v4f32 (AArch64duplane32
4106 (v4f32 (insert_subvector undef,
4107 (v2f32 (fneg V64:$Rm)),
4109 VectorIndexS:$idx)))),
4110 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4111 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4112 VectorIndexS:$idx)>;
4113 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4114 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4115 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4116 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4118 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4119 // (DUPLANE from 64-bit would be trivial).
4120 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4121 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4122 VectorIndexD:$idx))),
4124 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4125 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4126 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4127 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4128 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4130 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4131 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4132 (vector_extract (v4f32 (fneg V128:$Rm)),
4133 VectorIndexS:$idx))),
4134 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4135 V128:$Rm, VectorIndexS:$idx)>;
4136 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4137 (vector_extract (v2f32 (fneg V64:$Rm)),
4138 VectorIndexS:$idx))),
4139 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4140 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4142 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4143 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4144 (vector_extract (v2f64 (fneg V128:$Rm)),
4145 VectorIndexS:$idx))),
4146 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4147 V128:$Rm, VectorIndexS:$idx)>;
4150 defm : FMLSIndexedAfterNegPatterns<
4151 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4152 defm : FMLSIndexedAfterNegPatterns<
4153 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4155 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4156 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4158 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4159 (FMULv2i32_indexed V64:$Rn,
4160 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4162 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4163 (FMULv4i32_indexed V128:$Rn,
4164 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4166 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4167 (FMULv2i64_indexed V128:$Rn,
4168 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4171 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4172 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4173 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4174 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4175 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4176 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4177 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4178 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4179 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4180 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4181 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4182 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4183 int_aarch64_neon_smull>;
4184 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4185 int_aarch64_neon_sqadd>;
4186 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4187 int_aarch64_neon_sqsub>;
4188 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4189 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4190 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4191 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4192 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4193 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4194 int_aarch64_neon_umull>;
4196 // A scalar sqdmull with the second operand being a vector lane can be
4197 // handled directly with the indexed instruction encoding.
4198 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4199 (vector_extract (v4i32 V128:$Vm),
4200 VectorIndexS:$idx)),
4201 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4203 //----------------------------------------------------------------------------
4204 // AdvSIMD scalar shift instructions
4205 //----------------------------------------------------------------------------
4206 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4207 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4208 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4209 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4210 // Codegen patterns for the above. We don't put these directly on the
4211 // instructions because TableGen's type inference can't handle the truth.
4212 // Having the same base pattern for fp <--> int totally freaks it out.
4213 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4214 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4215 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4216 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4217 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4218 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4219 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4220 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4221 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4223 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4224 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4226 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4227 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4228 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4229 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4230 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4231 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4232 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4233 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4234 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4235 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4237 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4238 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4240 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4242 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4243 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4244 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4245 int_aarch64_neon_sqrshrn>;
4246 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4247 int_aarch64_neon_sqrshrun>;
4248 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4249 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4250 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4251 int_aarch64_neon_sqshrn>;
4252 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4253 int_aarch64_neon_sqshrun>;
4254 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4255 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4256 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4257 TriOpFrag<(add node:$LHS,
4258 (AArch64srshri node:$MHS, node:$RHS))>>;
4259 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4260 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4261 TriOpFrag<(add node:$LHS,
4262 (AArch64vashr node:$MHS, node:$RHS))>>;
4263 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4264 int_aarch64_neon_uqrshrn>;
4265 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4266 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4267 int_aarch64_neon_uqshrn>;
4268 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4269 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4270 TriOpFrag<(add node:$LHS,
4271 (AArch64urshri node:$MHS, node:$RHS))>>;
4272 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4273 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4274 TriOpFrag<(add node:$LHS,
4275 (AArch64vlshr node:$MHS, node:$RHS))>>;
4277 //----------------------------------------------------------------------------
4278 // AdvSIMD vector shift instructions
4279 //----------------------------------------------------------------------------
4280 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4281 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4282 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4283 int_aarch64_neon_vcvtfxs2fp>;
4284 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4285 int_aarch64_neon_rshrn>;
4286 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4287 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4288 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4289 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4290 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4291 (i32 vecshiftL64:$imm))),
4292 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4293 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4294 int_aarch64_neon_sqrshrn>;
4295 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4296 int_aarch64_neon_sqrshrun>;
4297 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4298 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4299 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4300 int_aarch64_neon_sqshrn>;
4301 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4302 int_aarch64_neon_sqshrun>;
4303 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4304 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4305 (i32 vecshiftR64:$imm))),
4306 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4307 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4308 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4309 TriOpFrag<(add node:$LHS,
4310 (AArch64srshri node:$MHS, node:$RHS))> >;
4311 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4312 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4314 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4315 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4316 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4317 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4318 int_aarch64_neon_vcvtfxu2fp>;
4319 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4320 int_aarch64_neon_uqrshrn>;
4321 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4322 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4323 int_aarch64_neon_uqshrn>;
4324 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4325 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4326 TriOpFrag<(add node:$LHS,
4327 (AArch64urshri node:$MHS, node:$RHS))> >;
4328 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4329 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4330 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4331 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4332 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4334 // SHRN patterns for when a logical right shift was used instead of arithmetic
4335 // (the immediate guarantees no sign bits actually end up in the result so it
4337 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4338 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4339 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4340 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4341 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4342 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4344 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4345 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4346 vecshiftR16Narrow:$imm)))),
4347 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4348 V128:$Rn, vecshiftR16Narrow:$imm)>;
4349 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4350 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4351 vecshiftR32Narrow:$imm)))),
4352 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4353 V128:$Rn, vecshiftR32Narrow:$imm)>;
4354 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4355 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4356 vecshiftR64Narrow:$imm)))),
4357 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4358 V128:$Rn, vecshiftR32Narrow:$imm)>;
4360 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4361 // Anyexts are implemented as zexts.
4362 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4363 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4364 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4365 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4366 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4367 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4368 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4369 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4370 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4371 // Also match an extend from the upper half of a 128 bit source register.
4372 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4373 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4374 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4375 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4376 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4377 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4378 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4379 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4380 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4381 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4382 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4383 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4384 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4385 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4386 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4387 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4388 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4389 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4391 // Vector shift sxtl aliases
4392 def : InstAlias<"sxtl.8h $dst, $src1",
4393 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4394 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4395 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4396 def : InstAlias<"sxtl.4s $dst, $src1",
4397 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4398 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4399 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4400 def : InstAlias<"sxtl.2d $dst, $src1",
4401 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4402 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4403 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4405 // Vector shift sxtl2 aliases
4406 def : InstAlias<"sxtl2.8h $dst, $src1",
4407 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4408 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4409 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4410 def : InstAlias<"sxtl2.4s $dst, $src1",
4411 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4412 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4413 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4414 def : InstAlias<"sxtl2.2d $dst, $src1",
4415 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4416 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4417 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4419 // Vector shift uxtl aliases
4420 def : InstAlias<"uxtl.8h $dst, $src1",
4421 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4422 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4423 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4424 def : InstAlias<"uxtl.4s $dst, $src1",
4425 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4426 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4427 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4428 def : InstAlias<"uxtl.2d $dst, $src1",
4429 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4430 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4431 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4433 // Vector shift uxtl2 aliases
4434 def : InstAlias<"uxtl2.8h $dst, $src1",
4435 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4436 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4437 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4438 def : InstAlias<"uxtl2.4s $dst, $src1",
4439 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4440 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4441 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4442 def : InstAlias<"uxtl2.2d $dst, $src1",
4443 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4444 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4445 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4447 // If an integer is about to be converted to a floating point value,
4448 // just load it on the floating point unit.
4449 // These patterns are more complex because floating point loads do not
4450 // support sign extension.
4451 // The sign extension has to be explicitly added and is only supported for
4452 // one step: byte-to-half, half-to-word, word-to-doubleword.
4453 // SCVTF GPR -> FPR is 9 cycles.
4454 // SCVTF FPR -> FPR is 4 cyclces.
4455 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4456 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4457 // and still being faster.
4458 // However, this is not good for code size.
4459 // 8-bits -> float. 2 sizes step-up.
4460 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4461 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4462 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4467 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4473 ssub)))>, Requires<[NotForCodeSize]>;
4475 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4476 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4477 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4478 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4479 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4480 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4481 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4482 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4484 // 16-bits -> float. 1 size step-up.
4485 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4486 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4487 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4489 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4493 ssub)))>, Requires<[NotForCodeSize]>;
4495 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4496 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4497 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4498 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4499 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4500 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4501 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4502 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4504 // 32-bits to 32-bits are handled in target specific dag combine:
4505 // performIntToFpCombine.
4506 // 64-bits integer to 32-bits floating point, not possible with
4507 // SCVTF on floating point registers (both source and destination
4508 // must have the same size).
4510 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4511 // 8-bits -> double. 3 size step-up: give up.
4512 // 16-bits -> double. 2 size step.
4513 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4514 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4515 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4520 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4526 dsub)))>, Requires<[NotForCodeSize]>;
4528 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4529 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4530 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4531 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4532 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4533 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4534 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4535 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4536 // 32-bits -> double. 1 size step-up.
4537 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4538 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4539 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4541 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4545 dsub)))>, Requires<[NotForCodeSize]>;
4547 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4548 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4549 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4550 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4551 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4552 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4553 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4554 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4556 // 64-bits -> double are handled in target specific dag combine:
4557 // performIntToFpCombine.
4560 //----------------------------------------------------------------------------
4561 // AdvSIMD Load-Store Structure
4562 //----------------------------------------------------------------------------
4563 defm LD1 : SIMDLd1Multiple<"ld1">;
4564 defm LD2 : SIMDLd2Multiple<"ld2">;
4565 defm LD3 : SIMDLd3Multiple<"ld3">;
4566 defm LD4 : SIMDLd4Multiple<"ld4">;
4568 defm ST1 : SIMDSt1Multiple<"st1">;
4569 defm ST2 : SIMDSt2Multiple<"st2">;
4570 defm ST3 : SIMDSt3Multiple<"st3">;
4571 defm ST4 : SIMDSt4Multiple<"st4">;
4573 class Ld1Pat<ValueType ty, Instruction INST>
4574 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4576 def : Ld1Pat<v16i8, LD1Onev16b>;
4577 def : Ld1Pat<v8i16, LD1Onev8h>;
4578 def : Ld1Pat<v4i32, LD1Onev4s>;
4579 def : Ld1Pat<v2i64, LD1Onev2d>;
4580 def : Ld1Pat<v8i8, LD1Onev8b>;
4581 def : Ld1Pat<v4i16, LD1Onev4h>;
4582 def : Ld1Pat<v2i32, LD1Onev2s>;
4583 def : Ld1Pat<v1i64, LD1Onev1d>;
4585 class St1Pat<ValueType ty, Instruction INST>
4586 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4587 (INST ty:$Vt, GPR64sp:$Rn)>;
4589 def : St1Pat<v16i8, ST1Onev16b>;
4590 def : St1Pat<v8i16, ST1Onev8h>;
4591 def : St1Pat<v4i32, ST1Onev4s>;
4592 def : St1Pat<v2i64, ST1Onev2d>;
4593 def : St1Pat<v8i8, ST1Onev8b>;
4594 def : St1Pat<v4i16, ST1Onev4h>;
4595 def : St1Pat<v2i32, ST1Onev2s>;
4596 def : St1Pat<v1i64, ST1Onev1d>;
4602 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4603 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4604 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4605 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4606 let mayLoad = 1, neverHasSideEffects = 1 in {
4607 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4608 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4609 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4610 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4611 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4612 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4613 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4614 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4615 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4616 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4617 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4618 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4619 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4620 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4621 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4622 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4625 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4626 (LD1Rv8b GPR64sp:$Rn)>;
4627 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4628 (LD1Rv16b GPR64sp:$Rn)>;
4629 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4630 (LD1Rv4h GPR64sp:$Rn)>;
4631 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4632 (LD1Rv8h GPR64sp:$Rn)>;
4633 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4634 (LD1Rv2s GPR64sp:$Rn)>;
4635 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4636 (LD1Rv4s GPR64sp:$Rn)>;
4637 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4638 (LD1Rv2d GPR64sp:$Rn)>;
4639 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4640 (LD1Rv1d GPR64sp:$Rn)>;
4641 // Grab the floating point version too
4642 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4643 (LD1Rv2s GPR64sp:$Rn)>;
4644 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4645 (LD1Rv4s GPR64sp:$Rn)>;
4646 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4647 (LD1Rv2d GPR64sp:$Rn)>;
4648 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4649 (LD1Rv1d GPR64sp:$Rn)>;
4651 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4652 ValueType VTy, ValueType STy, Instruction LD1>
4653 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4654 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4655 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4657 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4658 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4659 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4660 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4661 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4662 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4664 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4665 ValueType VTy, ValueType STy, Instruction LD1>
4666 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4667 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4669 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4670 VecIndex:$idx, GPR64sp:$Rn),
4673 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4674 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4675 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4676 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4679 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4680 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4681 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4682 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4685 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4686 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4687 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4688 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4690 let AddedComplexity = 15 in
4691 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4692 ValueType VTy, ValueType STy, Instruction ST1>
4694 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4696 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4698 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4699 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4700 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4701 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4702 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4703 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4705 let AddedComplexity = 15 in
4706 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4707 ValueType VTy, ValueType STy, Instruction ST1>
4709 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4711 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4712 VecIndex:$idx, GPR64sp:$Rn)>;
4714 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4715 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4716 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4717 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4719 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4720 ValueType VTy, ValueType STy, Instruction ST1,
4722 def : Pat<(scalar_store
4723 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4724 GPR64sp:$Rn, offset),
4725 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4726 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4728 def : Pat<(scalar_store
4729 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4730 GPR64sp:$Rn, GPR64:$Rm),
4731 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4732 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4735 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4736 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4738 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4739 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4740 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4741 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4743 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4744 ValueType VTy, ValueType STy, Instruction ST1,
4746 def : Pat<(scalar_store
4747 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4748 GPR64sp:$Rn, offset),
4749 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4751 def : Pat<(scalar_store
4752 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4753 GPR64sp:$Rn, GPR64:$Rm),
4754 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4757 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4759 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4761 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4762 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4763 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4764 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4766 let mayStore = 1, neverHasSideEffects = 1 in {
4767 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4768 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4769 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4770 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4771 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4772 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4773 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4774 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4775 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4776 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4777 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4778 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4781 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4782 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4783 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4784 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4786 //----------------------------------------------------------------------------
4787 // Crypto extensions
4788 //----------------------------------------------------------------------------
4790 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
4791 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
4792 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
4793 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
4795 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
4796 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
4797 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
4798 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
4799 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
4800 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
4801 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
4803 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
4804 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
4805 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
4807 //----------------------------------------------------------------------------
4809 //----------------------------------------------------------------------------
4810 // FIXME: Like for X86, these should go in their own separate .td file.
4812 // Any instruction that defines a 32-bit result leaves the high half of the
4813 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4814 // be copying from a truncate. But any other 32-bit operation will zero-extend
4816 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4817 def def32 : PatLeaf<(i32 GPR32:$src), [{
4818 return N->getOpcode() != ISD::TRUNCATE &&
4819 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4820 N->getOpcode() != ISD::CopyFromReg;
4823 // In the case of a 32-bit def that is known to implicitly zero-extend,
4824 // we can use a SUBREG_TO_REG.
4825 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4827 // For an anyext, we don't care what the high bits are, so we can perform an
4828 // INSERT_SUBREF into an IMPLICIT_DEF.
4829 def : Pat<(i64 (anyext GPR32:$src)),
4830 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4832 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4833 // instruction (UBFM) on the enclosing super-reg.
4834 def : Pat<(i64 (zext GPR32:$src)),
4835 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4837 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4838 // containing super-reg.
4839 def : Pat<(i64 (sext GPR32:$src)),
4840 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4841 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4842 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4843 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4844 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4845 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4846 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4847 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4849 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4850 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4851 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4852 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4853 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4854 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4856 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4857 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4858 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4859 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4860 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4861 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4863 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4864 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4865 (i64 (i64shift_a imm0_63:$imm)),
4866 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4868 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4869 // AddedComplexity for the following patterns since we want to match sext + sra
4870 // patterns before we attempt to match a single sra node.
4871 let AddedComplexity = 20 in {
4872 // We support all sext + sra combinations which preserve at least one bit of the
4873 // original value which is to be sign extended. E.g. we support shifts up to
4875 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4876 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4877 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4878 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4880 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4881 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4882 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4883 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4885 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4886 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4887 (i64 imm0_31:$imm), 31)>;
4888 } // AddedComplexity = 20
4890 // To truncate, we can simply extract from a subregister.
4891 def : Pat<(i32 (trunc GPR64sp:$src)),
4892 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4894 // __builtin_trap() uses the BRK instruction on AArch64.
4895 def : Pat<(trap), (BRK 1)>;
4897 // Conversions within AdvSIMD types in the same register size are free.
4898 // But because we need a consistent lane ordering, in big endian many
4899 // conversions require one or more REV instructions.
4901 // Consider a simple memory load followed by a bitconvert then a store.
4903 // v1 = BITCAST v2i32 v0 to v4i16
4906 // In big endian mode every memory access has an implicit byte swap. LDR and
4907 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
4908 // is, they treat the vector as a sequence of elements to be byte-swapped.
4909 // The two pairs of instructions are fundamentally incompatible. We've decided
4910 // to use LD1/ST1 only to simplify compiler implementation.
4912 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
4913 // the original code sequence:
4915 // v1 = REV v2i32 (implicit)
4916 // v2 = BITCAST v2i32 v1 to v4i16
4917 // v3 = REV v4i16 v2 (implicit)
4920 // But this is now broken - the value stored is different to the value loaded
4921 // due to lane reordering. To fix this, on every BITCAST we must perform two
4924 // v1 = REV v2i32 (implicit)
4926 // v3 = BITCAST v2i32 v2 to v4i16
4928 // v5 = REV v4i16 v4 (implicit)
4931 // This means an extra two instructions, but actually in most cases the two REV
4932 // instructions can be combined into one. For example:
4933 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
4935 // There is also no 128-bit REV instruction. This must be synthesized with an
4938 // Most bitconverts require some sort of conversion. The only exceptions are:
4939 // a) Identity conversions - vNfX <-> vNiX
4940 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
4943 let Predicates = [IsLE] in {
4944 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4945 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4946 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4947 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4949 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4950 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4951 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4952 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4953 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4954 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4955 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4956 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4957 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4958 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4960 let Predicates = [IsBE] in {
4961 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
4962 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4963 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
4964 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4965 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
4966 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4967 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
4968 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4970 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4971 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4972 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4973 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4974 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4975 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4976 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4977 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4979 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4980 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4981 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
4982 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4983 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
4984 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4985 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
4986 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4987 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
4989 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
4990 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
4991 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
4992 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
4993 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
4994 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4995 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
4996 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
4997 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4998 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5000 let Predicates = [IsLE] in {
5001 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5002 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5003 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5004 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5006 let Predicates = [IsBE] in {
5007 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5008 (v1i64 (REV64v2i32 FPR64:$src))>;
5009 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5010 (v1i64 (REV64v4i16 FPR64:$src))>;
5011 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5012 (v1i64 (REV64v8i8 FPR64:$src))>;
5013 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5014 (v1i64 (REV64v2i32 FPR64:$src))>;
5016 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5017 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5019 let Predicates = [IsLE] in {
5020 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5021 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5022 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5023 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5024 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5026 let Predicates = [IsBE] in {
5027 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5028 (v2i32 (REV64v2i32 FPR64:$src))>;
5029 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5030 (v2i32 (REV32v4i16 FPR64:$src))>;
5031 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5032 (v2i32 (REV32v8i8 FPR64:$src))>;
5033 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5034 (v2i32 (REV64v2i32 FPR64:$src))>;
5035 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5036 (v2i32 (REV64v2i32 FPR64:$src))>;
5038 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5040 let Predicates = [IsLE] in {
5041 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5042 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5043 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5044 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5045 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5046 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5048 let Predicates = [IsBE] in {
5049 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5050 (v4i16 (REV64v4i16 FPR64:$src))>;
5051 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5052 (v4i16 (REV32v4i16 FPR64:$src))>;
5053 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5054 (v4i16 (REV16v8i8 FPR64:$src))>;
5055 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5056 (v4i16 (REV64v4i16 FPR64:$src))>;
5057 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5058 (v4i16 (REV32v4i16 FPR64:$src))>;
5059 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5060 (v4i16 (REV64v4i16 FPR64:$src))>;
5063 let Predicates = [IsLE] in {
5064 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5065 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5066 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5067 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5068 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5069 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5071 let Predicates = [IsBE] in {
5072 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5073 (v8i8 (REV64v8i8 FPR64:$src))>;
5074 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5075 (v8i8 (REV32v8i8 FPR64:$src))>;
5076 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5077 (v8i8 (REV16v8i8 FPR64:$src))>;
5078 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5079 (v8i8 (REV64v8i8 FPR64:$src))>;
5080 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5081 (v8i8 (REV32v8i8 FPR64:$src))>;
5082 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5083 (v8i8 (REV64v8i8 FPR64:$src))>;
5086 let Predicates = [IsLE] in {
5087 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5088 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5089 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5090 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5092 let Predicates = [IsBE] in {
5093 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5094 (f64 (REV64v2i32 FPR64:$src))>;
5095 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5096 (f64 (REV64v4i16 FPR64:$src))>;
5097 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5098 (f64 (REV64v2i32 FPR64:$src))>;
5099 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5100 (f64 (REV64v8i8 FPR64:$src))>;
5102 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5103 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5105 let Predicates = [IsLE] in {
5106 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5107 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5108 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5109 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5111 let Predicates = [IsBE] in {
5112 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5113 (v1f64 (REV64v2i32 FPR64:$src))>;
5114 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5115 (v1f64 (REV64v4i16 FPR64:$src))>;
5116 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5117 (v1f64 (REV64v8i8 FPR64:$src))>;
5118 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5119 (v1f64 (REV64v2i32 FPR64:$src))>;
5121 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5122 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5124 let Predicates = [IsLE] in {
5125 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5126 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5127 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5128 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5129 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5131 let Predicates = [IsBE] in {
5132 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5133 (v2f32 (REV64v2i32 FPR64:$src))>;
5134 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5135 (v2f32 (REV32v4i16 FPR64:$src))>;
5136 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5137 (v2f32 (REV32v8i8 FPR64:$src))>;
5138 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5139 (v2f32 (REV64v2i32 FPR64:$src))>;
5140 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5141 (v2f32 (REV64v2i32 FPR64:$src))>;
5143 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5145 let Predicates = [IsLE] in {
5146 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5147 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5148 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5149 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5150 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5151 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5153 let Predicates = [IsBE] in {
5154 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5155 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5156 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5157 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5158 (REV64v4i32 FPR128:$src), (i32 8)))>;
5159 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5160 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5161 (REV64v8i16 FPR128:$src), (i32 8)))>;
5162 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5163 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5164 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5165 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5166 (REV64v4i32 FPR128:$src), (i32 8)))>;
5167 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5168 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5169 (REV64v16i8 FPR128:$src), (i32 8)))>;
5172 let Predicates = [IsLE] in {
5173 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5174 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5175 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5176 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5177 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5179 let Predicates = [IsBE] in {
5180 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5181 (v2f64 (EXTv16i8 FPR128:$src,
5182 FPR128:$src, (i32 8)))>;
5183 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5184 (v2f64 (REV64v4i32 FPR128:$src))>;
5185 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5186 (v2f64 (REV64v8i16 FPR128:$src))>;
5187 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5188 (v2f64 (REV64v16i8 FPR128:$src))>;
5189 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5190 (v2f64 (REV64v4i32 FPR128:$src))>;
5192 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5194 let Predicates = [IsLE] in {
5195 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5196 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5197 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5198 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5199 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5201 let Predicates = [IsBE] in {
5202 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5203 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5204 (REV64v4i32 FPR128:$src), (i32 8)))>;
5205 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5206 (v4f32 (REV32v8i16 FPR128:$src))>;
5207 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5208 (v4f32 (REV32v16i8 FPR128:$src))>;
5209 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5210 (v4f32 (REV64v4i32 FPR128:$src))>;
5211 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5212 (v4f32 (REV64v4i32 FPR128:$src))>;
5214 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5216 let Predicates = [IsLE] in {
5217 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5218 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5219 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5220 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5221 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5223 let Predicates = [IsBE] in {
5224 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5225 (v2i64 (EXTv16i8 FPR128:$src,
5226 FPR128:$src, (i32 8)))>;
5227 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5228 (v2i64 (REV64v4i32 FPR128:$src))>;
5229 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5230 (v2i64 (REV64v8i16 FPR128:$src))>;
5231 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5232 (v2i64 (REV64v16i8 FPR128:$src))>;
5233 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5234 (v2i64 (REV64v4i32 FPR128:$src))>;
5236 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5238 let Predicates = [IsLE] in {
5239 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5240 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5241 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5242 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5243 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5245 let Predicates = [IsBE] in {
5246 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5247 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5248 (REV64v4i32 FPR128:$src),
5250 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5251 (v4i32 (REV64v4i32 FPR128:$src))>;
5252 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5253 (v4i32 (REV32v8i16 FPR128:$src))>;
5254 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5255 (v4i32 (REV32v16i8 FPR128:$src))>;
5256 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5257 (v4i32 (REV64v4i32 FPR128:$src))>;
5259 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5261 let Predicates = [IsLE] in {
5262 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5263 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5264 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5265 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5266 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5267 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5269 let Predicates = [IsBE] in {
5270 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5271 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5272 (REV64v8i16 FPR128:$src),
5274 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5275 (v8i16 (REV64v8i16 FPR128:$src))>;
5276 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5277 (v8i16 (REV32v8i16 FPR128:$src))>;
5278 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5279 (v8i16 (REV16v16i8 FPR128:$src))>;
5280 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5281 (v8i16 (REV64v8i16 FPR128:$src))>;
5282 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5283 (v8i16 (REV32v8i16 FPR128:$src))>;
5286 let Predicates = [IsLE] in {
5287 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5288 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5289 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5290 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5291 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5292 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5294 let Predicates = [IsBE] in {
5295 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5296 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5297 (REV64v16i8 FPR128:$src),
5299 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5300 (v16i8 (REV64v16i8 FPR128:$src))>;
5301 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5302 (v16i8 (REV32v16i8 FPR128:$src))>;
5303 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5304 (v16i8 (REV16v16i8 FPR128:$src))>;
5305 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5306 (v16i8 (REV64v16i8 FPR128:$src))>;
5307 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5308 (v16i8 (REV32v16i8 FPR128:$src))>;
5311 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5312 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5313 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5314 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5315 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5316 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5317 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5318 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5320 // A 64-bit subvector insert to the first 128-bit vector position
5321 // is a subregister copy that needs no instruction.
5322 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5323 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5324 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5325 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5326 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5327 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5328 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5329 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5330 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5331 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5332 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5333 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5335 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5337 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5338 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5339 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5340 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5341 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5342 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5343 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5344 // so we match on v4f32 here, not v2f32. This will also catch adding
5345 // the low two lanes of a true v4f32 vector.
5346 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5347 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5348 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5350 // Scalar 64-bit shifts in FPR64 registers.
5351 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5352 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5353 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5354 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5355 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5356 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5357 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5358 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5360 // Tail call return handling. These are all compiler pseudo-instructions,
5361 // so no encoding information or anything like that.
5362 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5363 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5364 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5367 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5368 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5369 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5370 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5371 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5372 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5374 include "AArch64InstrAtomics.td"