1 //===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 scalar instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "AArch64InstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Target-specific ISD nodes and profiles
18 //===----------------------------------------------------------------------===//
20 def SDT_A64ret : SDTypeProfile<0, 0, []>;
21 def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain,
25 // (ins NZCV, Condition, Dest)
26 def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>;
27 def A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>;
29 // (outs Result), (ins NZCV, IfTrue, IfFalse, Condition)
30 def SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>,
33 def A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>;
35 // (outs NZCV), (ins LHS, RHS, Condition)
36 def SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
38 def A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>;
41 // (outs GPR64), (ins)
42 def A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
44 // A64 compares don't care about the cond really (they set all flags) so a
45 // simple binary operator is useful.
46 def A64cmp : PatFrag<(ops node:$lhs, node:$rhs),
47 (A64setcc node:$lhs, node:$rhs, cond)>;
50 // When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN
51 // instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C
52 // and V flags can be set differently by this operation. It comes down to
53 // whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are
54 // then everything is fine. If not then the optimization is wrong. Thus general
55 // comparisons are only valid if op2 != 0.
57 // So, finally, the only LLVM-native comparisons that don't mention C and V are
58 // SETEQ and SETNE. They're the only ones we can safely use CMN for in the
59 // absence of information about op2.
60 def equality_cond : PatLeaf<(cond), [{
61 return N->get() == ISD::SETEQ || N->get() == ISD::SETNE;
64 def A64cmn : PatFrag<(ops node:$lhs, node:$rhs),
65 (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>;
67 // There are two layers of indirection here, driven by the following
69 // + TableGen does not know CodeModel or Reloc so that decision should be
70 // made for a variable/address at ISelLowering.
71 // + The output of ISelLowering should be selectable (hence the Wrapper,
72 // rather than a bare target opcode)
73 def SDTAArch64Wrapper : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
78 def A64WrapperSmall : SDNode<"AArch64ISD::WrapperSmall", SDTAArch64Wrapper>;
81 def SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
82 def A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad,
86 // (A64BFI LHS, RHS, LSB, Width)
87 def SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
92 def A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>;
94 // (A64EXTR HiReg, LoReg, LSB)
95 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
97 def A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
99 // (A64[SU]BFX Field, ImmR, ImmS).
101 // Note that ImmR and ImmS are already encoded for the actual instructions. The
102 // more natural LSB and Width mix together to form ImmR and ImmS, something
103 // which TableGen can't handle.
104 def SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>;
105 def A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>;
107 def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>;
109 //===----------------------------------------------------------------------===//
110 // Call sequence pseudo-instructions
111 //===----------------------------------------------------------------------===//
114 def SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
115 def AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
118 def AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call,
119 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
121 // The TLSDESCCALL node is a variant call which goes to an indirectly calculated
122 // destination but needs a relocation against a fixed symbol. As such it has two
123 // certain operands: the callee and the relocated variable.
125 // The TLS ABI only allows it to be selected to a BLR instructin (with
126 // appropriate relocation).
127 def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
129 def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall,
130 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
134 def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>;
135 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart,
136 [SDNPHasChain, SDNPOutGlue]>;
138 def SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>;
139 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
144 // These pseudo-instructions have special semantics by virtue of being passed to
145 // the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by
146 // LowerCall to (in our case) tell the back-end about stack adjustments for
147 // arguments passed on the stack. Here we select those markers to
148 // pseudo-instructions which explicitly set the stack, and finally in the
149 // RegisterInfo we convert them to a true stack adjustment.
150 let Defs = [XSP], Uses = [XSP] in {
151 def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt),
152 [(AArch64callseq_start timm:$amt)]>;
154 def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2),
155 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
158 //===----------------------------------------------------------------------===//
159 // Atomic operation pseudo-instructions
160 //===----------------------------------------------------------------------===//
162 let usesCustomInserter = 1 in {
163 multiclass AtomicSizes<string opname> {
164 def _I8 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
165 [(set GPR32:$dst, (!cast<SDNode>(opname # "_8") GPR64:$ptr, GPR32:$incr))]>;
166 def _I16 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
167 [(set GPR32:$dst, (!cast<SDNode>(opname # "_16") GPR64:$ptr, GPR32:$incr))]>;
168 def _I32 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
169 [(set GPR32:$dst, (!cast<SDNode>(opname # "_32") GPR64:$ptr, GPR32:$incr))]>;
170 def _I64 : PseudoInst<(outs GPR64:$dst), (ins GPR64:$ptr, GPR64:$incr),
171 [(set GPR64:$dst, (!cast<SDNode>(opname # "_64") GPR64:$ptr, GPR64:$incr))]>;
175 defm ATOMIC_LOAD_ADD : AtomicSizes<"atomic_load_add">;
176 defm ATOMIC_LOAD_SUB : AtomicSizes<"atomic_load_sub">;
177 defm ATOMIC_LOAD_AND : AtomicSizes<"atomic_load_and">;
178 defm ATOMIC_LOAD_OR : AtomicSizes<"atomic_load_or">;
179 defm ATOMIC_LOAD_XOR : AtomicSizes<"atomic_load_xor">;
180 defm ATOMIC_LOAD_NAND : AtomicSizes<"atomic_load_nand">;
181 defm ATOMIC_SWAP : AtomicSizes<"atomic_swap">;
182 let Defs = [NZCV] in {
183 // These operations need a CMP to calculate the correct value
184 defm ATOMIC_LOAD_MIN : AtomicSizes<"atomic_load_min">;
185 defm ATOMIC_LOAD_MAX : AtomicSizes<"atomic_load_max">;
186 defm ATOMIC_LOAD_UMIN : AtomicSizes<"atomic_load_umin">;
187 defm ATOMIC_LOAD_UMAX : AtomicSizes<"atomic_load_umax">;
190 let usesCustomInserter = 1, Defs = [NZCV] in {
191 def ATOMIC_CMP_SWAP_I8
192 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
194 (atomic_cmp_swap_8 GPR64:$ptr, GPR32:$old, GPR32:$new))]>;
195 def ATOMIC_CMP_SWAP_I16
196 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
198 (atomic_cmp_swap_16 GPR64:$ptr, GPR32:$old, GPR32:$new))]>;
199 def ATOMIC_CMP_SWAP_I32
200 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
202 (atomic_cmp_swap_32 GPR64:$ptr, GPR32:$old, GPR32:$new))]>;
203 def ATOMIC_CMP_SWAP_I64
204 : PseudoInst<(outs GPR64:$dst), (ins GPR64:$ptr, GPR64:$old, GPR64:$new),
206 (atomic_cmp_swap_64 GPR64:$ptr, GPR64:$old, GPR64:$new))]>;
209 //===----------------------------------------------------------------------===//
210 // Add-subtract (extended register) instructions
211 //===----------------------------------------------------------------------===//
212 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP
214 // The RHS of these operations is conceptually a sign/zero-extended
215 // register, optionally shifted left by 1-4. The extension can be a
216 // NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but
217 // must be specified with one exception:
219 // If one of the registers is sp/wsp then LSL is an alias for UXTW in
220 // 32-bit instructions and UXTX in 64-bit versions, the shift amount
221 // is not optional in that case (but can explicitly be 0), and the
222 // entire suffix can be skipped (e.g. "add sp, x3, x2").
224 multiclass extend_operands<string PREFIX, string Diag> {
225 def _asmoperand : AsmOperandClass {
227 let RenderMethod = "addRegExtendOperands";
228 let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">";
229 let DiagnosticType = "AddSubRegExtend" # Diag;
232 def _operand : Operand<i64>,
233 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> {
234 let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">";
235 let DecoderMethod = "DecodeRegExtendOperand";
236 let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand");
240 defm UXTB : extend_operands<"UXTB", "Small">;
241 defm UXTH : extend_operands<"UXTH", "Small">;
242 defm UXTW : extend_operands<"UXTW", "Small">;
243 defm UXTX : extend_operands<"UXTX", "Large">;
244 defm SXTB : extend_operands<"SXTB", "Small">;
245 defm SXTH : extend_operands<"SXTH", "Small">;
246 defm SXTW : extend_operands<"SXTW", "Small">;
247 defm SXTX : extend_operands<"SXTX", "Large">;
249 def LSL_extasmoperand : AsmOperandClass {
250 let Name = "RegExtendLSL";
251 let RenderMethod = "addRegExtendOperands";
252 let DiagnosticType = "AddSubRegExtendLarge";
255 def LSL_extoperand : Operand<i64> {
256 let ParserMatchClass = LSL_extasmoperand;
260 // The patterns for various sign-extensions are a little ugly and
261 // non-uniform because everything has already been promoted to the
262 // legal i64 and i32 types. We'll wrap the various variants up in a
263 // class for use later.
265 dag uxtb; dag uxth; dag uxtw; dag uxtx;
266 dag sxtb; dag sxth; dag sxtw; dag sxtx;
269 def extends_to_i64 : extend_types {
270 let uxtb = (and (anyext GPR32:$Rm), 255);
271 let uxth = (and (anyext GPR32:$Rm), 65535);
272 let uxtw = (zext GPR32:$Rm);
273 let uxtx = (i64 GPR64:$Rm);
275 let sxtb = (sext_inreg (anyext GPR32:$Rm), i8);
276 let sxth = (sext_inreg (anyext GPR32:$Rm), i16);
277 let sxtw = (sext GPR32:$Rm);
278 let sxtx = (i64 GPR64:$Rm);
282 def extends_to_i32 : extend_types {
283 let uxtb = (and GPR32:$Rm, 255);
284 let uxth = (and GPR32:$Rm, 65535);
285 let uxtw = (i32 GPR32:$Rm);
286 let uxtx = (i32 GPR32:$Rm);
288 let sxtb = (sext_inreg GPR32:$Rm, i8);
289 let sxth = (sext_inreg GPR32:$Rm, i16);
290 let sxtw = (i32 GPR32:$Rm);
291 let sxtx = (i32 GPR32:$Rm);
294 // Now, six of the extensions supported are easy and uniform: if the source size
295 // is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate
296 // those instructions in one block.
298 // The uxtx/sxtx could potentially be merged in, but three facts dissuaded me:
299 // + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would
301 // + Patterns are very different as well.
302 // + Passing different registers would be ugly (more fields in extend_types
303 // would probably be the best option).
304 multiclass addsub_exts<bit sf, bit op, bit S, string asmop,
305 SDPatternOperator opfrag,
306 dag outs, extend_types exts, RegisterClass GPRsp> {
307 def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000,
309 (ins GPRsp:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
310 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
311 [(opfrag GPRsp:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
313 def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001,
315 (ins GPRsp:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
316 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
317 [(opfrag GPRsp:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
319 def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010,
321 (ins GPRsp:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
322 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
323 [(opfrag GPRsp:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
326 def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100,
328 (ins GPRsp:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
329 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
330 [(opfrag GPRsp:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
332 def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101,
334 (ins GPRsp:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
335 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
336 [(opfrag GPRsp:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
338 def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110,
340 (ins GPRsp:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
341 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
342 [(opfrag GPRsp:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
346 // These two could be merge in with the above, but their patterns aren't really
347 // necessary and the naming-scheme would necessarily break:
348 multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag,
350 def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011,
352 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
353 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
354 [(opfrag GPR64xsp:$Rn, (shl GPR64:$Rm, UXTX_operand:$Imm3))],
357 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
359 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),
360 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
361 [/* No Pattern: same as uxtx */],
365 multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {
366 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
368 (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
369 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
370 [/* No pattern: probably same as uxtw */],
373 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,
375 (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
376 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
377 [/* No Pattern: probably same as uxtw */],
381 class SetRD<RegisterClass RC, SDPatternOperator op>
382 : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>;
383 class SetNZCV<SDPatternOperator op>
384 : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>;
386 defm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
387 (outs GPR64xsp:$Rd), extends_to_i64, GPR64xsp>,
388 addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
389 (outs GPR64xsp:$Rd)>;
390 defm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>,
391 (outs GPR32wsp:$Rd), extends_to_i32, GPR32wsp>,
392 addsub_wxtx< 0b0, 0b0, "add\t$Rd, ",
393 (outs GPR32wsp:$Rd)>;
394 defm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
395 (outs GPR64xsp:$Rd), extends_to_i64, GPR64xsp>,
396 addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
397 (outs GPR64xsp:$Rd)>;
398 defm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>,
399 (outs GPR32wsp:$Rd), extends_to_i32, GPR32wsp>,
400 addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ",
401 (outs GPR32wsp:$Rd)>;
403 let Defs = [NZCV] in {
404 defm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
405 (outs GPR64:$Rd), extends_to_i64, GPR64xsp>,
406 addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
408 defm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>,
409 (outs GPR32:$Rd), extends_to_i32, GPR32wsp>,
410 addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ",
412 defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
413 (outs GPR64:$Rd), extends_to_i64, GPR64xsp>,
414 addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
416 defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>,
417 (outs GPR32:$Rd), extends_to_i32, GPR32wsp>,
418 addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ",
422 let Rd = 0b11111, isCompare = 1 in {
423 defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
424 (outs), extends_to_i64, GPR64xsp>,
425 addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
426 defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
427 (outs), extends_to_i32, GPR32wsp>,
428 addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>;
429 defm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
430 (outs), extends_to_i64, GPR64xsp>,
431 addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>;
432 defm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
433 (outs), extends_to_i32, GPR32wsp>,
434 addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>;
438 // Now patterns for the operation without a shift being needed. No patterns are
439 // created for uxtx/sxtx since they're non-uniform and it's expected that
440 // add/sub (shifted register) will handle those cases anyway.
441 multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop,
442 RegisterClass GPRsp, extend_types exts> {
443 def : Pat<(nodeop GPRsp:$Rn, exts.uxtb),
444 (!cast<Instruction>(prefix # "w_uxtb") GPRsp:$Rn, GPR32:$Rm, 0)>;
445 def : Pat<(nodeop GPRsp:$Rn, exts.uxth),
446 (!cast<Instruction>(prefix # "w_uxth") GPRsp:$Rn, GPR32:$Rm, 0)>;
447 def : Pat<(nodeop GPRsp:$Rn, exts.uxtw),
448 (!cast<Instruction>(prefix # "w_uxtw") GPRsp:$Rn, GPR32:$Rm, 0)>;
450 def : Pat<(nodeop GPRsp:$Rn, exts.sxtb),
451 (!cast<Instruction>(prefix # "w_sxtb") GPRsp:$Rn, GPR32:$Rm, 0)>;
452 def : Pat<(nodeop GPRsp:$Rn, exts.sxth),
453 (!cast<Instruction>(prefix # "w_sxth") GPRsp:$Rn, GPR32:$Rm, 0)>;
454 def : Pat<(nodeop GPRsp:$Rn, exts.sxtw),
455 (!cast<Instruction>(prefix # "w_sxtw") GPRsp:$Rn, GPR32:$Rm, 0)>;
458 defm : addsubext_noshift_patterns<"ADDxx", add, GPR64xsp, extends_to_i64>;
459 defm : addsubext_noshift_patterns<"ADDww", add, GPR32wsp, extends_to_i32>;
460 defm : addsubext_noshift_patterns<"SUBxx", sub, GPR64xsp, extends_to_i64>;
461 defm : addsubext_noshift_patterns<"SUBww", sub, GPR32wsp, extends_to_i32>;
463 defm : addsubext_noshift_patterns<"CMNx", A64cmn, GPR64xsp, extends_to_i64>;
464 defm : addsubext_noshift_patterns<"CMNw", A64cmn, GPR32wsp, extends_to_i32>;
465 defm : addsubext_noshift_patterns<"CMPx", A64cmp, GPR64xsp, extends_to_i64>;
466 defm : addsubext_noshift_patterns<"CMPw", A64cmp, GPR32wsp, extends_to_i32>;
468 // An extend of "lsl #imm" is valid if and only if one of Rn and Rd is
469 // sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the
470 // operation. Also permitted in this case is complete omission of the argument,
471 // which implies "lsl #0".
472 multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd,
473 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
474 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
475 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
477 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"),
478 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
482 defm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
483 defm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
484 defm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>;
485 defm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>;
486 defm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
487 defm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
488 defm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>;
489 defm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>;
491 // Rd cannot be sp for flag-setting variants so only half of the aliases are
493 defm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>;
494 defm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>;
495 defm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>;
496 defm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>;
498 // CMP unfortunately has to be different because the instruction doesn't have a
500 multiclass cmp_lsl_aliases<string asmop, Instruction inst,
501 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
502 def : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
503 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
505 def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"),
506 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
509 defm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>;
510 defm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>;
511 defm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>;
512 defm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>;
514 //===----------------------------------------------------------------------===//
515 // Add-subtract (immediate) instructions
516 //===----------------------------------------------------------------------===//
517 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV
519 // These instructions accept a 12-bit unsigned immediate, optionally shifted
520 // left by 12 bits. Official assembly format specifies a 12 bit immediate with
521 // one of "", "LSL #0", "LSL #12" supplementary operands.
523 // There are surprisingly few ways to make this work with TableGen, so this
524 // implementation has separate instructions for the "LSL #0" and "LSL #12"
527 // If the MCInst retained a single combined immediate (which could be 0x123000,
528 // for example) then both components (imm & shift) would have to be delegated to
529 // a single assembly operand. This would entail a separate operand parser
530 // (because the LSL would have to live in the same AArch64Operand as the
531 // immediate to be accessible); assembly parsing is rather complex and
532 // error-prone C++ code.
534 // By splitting the immediate, we can delegate handling this optional operand to
535 // an InstAlias. Supporting functions to generate the correct MCInst are still
536 // required, but these are essentially trivial and parsing can remain generic.
538 // Rejected plans with rationale:
539 // ------------------------------
541 // In an ideal world you'de have two first class immediate operands (in
542 // InOperandList, specifying imm12 and shift). Unfortunately this is not
543 // selectable by any means I could discover.
545 // An Instruction with two MCOperands hidden behind a single entry in
546 // InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional,
547 // but required more C++ code to handle encoding/decoding. Parsing (the intended
548 // main beneficiary) ended up equally complex because of the optional nature of
551 // Attempting to circumvent the need for a custom OperandParser above by giving
552 // InstAliases without the "lsl #0" failed. add/sub could be accommodated but
553 // the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands
554 // should be parsed: there was no way to accommodate an "lsl #12".
556 let ParserMethod = "ParseImmWithLSLOperand",
557 RenderMethod = "addImmWithLSLOperands" in {
558 // Derived PredicateMethod fields are different for each
559 def addsubimm_lsl0_asmoperand : AsmOperandClass {
560 let Name = "AddSubImmLSL0";
561 // If an error is reported against this operand, instruction could also be a
563 let DiagnosticType = "AddSubSecondSource";
566 def addsubimm_lsl12_asmoperand : AsmOperandClass {
567 let Name = "AddSubImmLSL12";
568 let DiagnosticType = "AddSubSecondSource";
572 def shr_12_XFORM : SDNodeXForm<imm, [{
573 return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32);
576 def shr_12_neg_XFORM : SDNodeXForm<imm, [{
577 return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32);
580 def neg_XFORM : SDNodeXForm<imm, [{
581 return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32);
585 multiclass addsub_imm_operands<ValueType ty> {
586 let PrintMethod = "printAddSubImmLSL0Operand",
587 EncoderMethod = "getAddSubImmOpValue",
588 ParserMatchClass = addsubimm_lsl0_asmoperand in {
589 def _posimm_lsl0 : Operand<ty>,
590 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>;
591 def _negimm_lsl0 : Operand<ty>,
592 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }],
596 let PrintMethod = "printAddSubImmLSL12Operand",
597 EncoderMethod = "getAddSubImmOpValue",
598 ParserMatchClass = addsubimm_lsl12_asmoperand in {
599 def _posimm_lsl12 : Operand<ty>,
600 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }],
603 def _negimm_lsl12 : Operand<ty>,
604 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }],
609 // The add operands don't need any transformation
610 defm addsubimm_operand_i32 : addsub_imm_operands<i32>;
611 defm addsubimm_operand_i64 : addsub_imm_operands<i64>;
613 multiclass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift,
614 string asmop, string cmpasmop,
615 Operand imm_operand, Operand cmp_imm_operand,
616 RegisterClass GPR, RegisterClass GPRsp,
618 // All registers for non-S variants allow SP
619 def _s : A64I_addsubimm<sf, op, 0b0, shift,
621 (ins GPRsp:$Rn, imm_operand:$Imm12),
622 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
624 (add GPRsp:$Rn, imm_operand:$Imm12))],
628 // S variants can read SP but would write to ZR
629 def _S : A64I_addsubimm<sf, op, 0b1, shift,
631 (ins GPRsp:$Rn, imm_operand:$Imm12),
632 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
633 [(set GPR:$Rd, (addc GPRsp:$Rn, imm_operand:$Imm12))],
638 // Note that the pattern here for ADDS is subtle. Canonically CMP
639 // a, b becomes SUBS a, b. If b < 0 then this is equivalent to
640 // ADDS a, (-b). This is not true in general.
641 def _cmp : A64I_addsubimm<sf, op, 0b1, shift,
642 (outs), (ins GPRsp:$Rn, imm_operand:$Imm12),
643 !strconcat(cmpasmop, " $Rn, $Imm12"),
645 (A64cmp GPRsp:$Rn, cmp_imm_operand:$Imm12))],
654 multiclass addsubimm_shifts<string prefix, bit sf, bit op,
655 string asmop, string cmpasmop, string operand, string cmpoperand,
656 RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR> {
657 defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00,
659 !cast<Operand>(operand # "_lsl0"),
660 !cast<Operand>(cmpoperand # "_lsl0"),
663 defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01,
665 !cast<Operand>(operand # "_lsl12"),
666 !cast<Operand>(cmpoperand # "_lsl12"),
670 defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn",
671 "addsubimm_operand_i32_posimm",
672 "addsubimm_operand_i32_negimm",
673 GPR32, GPR32wsp, WZR>;
674 defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn",
675 "addsubimm_operand_i64_posimm",
676 "addsubimm_operand_i64_negimm",
677 GPR64, GPR64xsp, XZR>;
678 defm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp",
679 "addsubimm_operand_i32_negimm",
680 "addsubimm_operand_i32_posimm",
681 GPR32, GPR32wsp, WZR>;
682 defm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp",
683 "addsubimm_operand_i64_negimm",
684 "addsubimm_operand_i64_posimm",
685 GPR64, GPR64xsp, XZR>;
687 multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> {
688 def _fromsp : InstAlias<"mov $Rd, $Rn",
689 (addop GPRsp:$Rd, SP:$Rn, 0),
692 def _tosp : InstAlias<"mov $Rd, $Rn",
693 (addop SP:$Rd, GPRsp:$Rn, 0),
697 // Recall Rxsp is a RegisterClass containing *just* xsp.
698 defm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>;
699 defm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>;
701 //===----------------------------------------------------------------------===//
702 // Add-subtract (shifted register) instructions
703 //===----------------------------------------------------------------------===//
704 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS
706 //===-------------------------------
707 // 1. The "shifed register" operands. Shared with logical insts.
708 //===-------------------------------
710 multiclass shift_operands<string prefix, string form> {
711 def _asmoperand_i32 : AsmOperandClass {
712 let Name = "Shift" # form # "i32";
713 let RenderMethod = "addShiftOperands";
714 let PredicateMethod = "isShift<A64SE::" # form # ", false>";
715 let DiagnosticType = "AddSubRegShift32";
718 // Note that the operand type is intentionally i64 because the DAGCombiner
719 // puts these into a canonical form.
720 def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
722 = !cast<AsmOperandClass>(prefix # "_asmoperand_i32");
723 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
724 let DecoderMethod = "Decode32BitShiftOperand";
727 def _asmoperand_i64 : AsmOperandClass {
728 let Name = "Shift" # form # "i64";
729 let RenderMethod = "addShiftOperands";
730 let PredicateMethod = "isShift<A64SE::" # form # ", true>";
731 let DiagnosticType = "AddSubRegShift64";
734 def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
736 = !cast<AsmOperandClass>(prefix # "_asmoperand_i64");
737 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
741 defm lsl_operand : shift_operands<"lsl_operand", "LSL">;
742 defm lsr_operand : shift_operands<"lsr_operand", "LSR">;
743 defm asr_operand : shift_operands<"asr_operand", "ASR">;
745 // Not used for add/sub, but defined here for completeness. The "logical
746 // (shifted register)" instructions *do* have an ROR variant.
747 defm ror_operand : shift_operands<"ror_operand", "ROR">;
749 //===-------------------------------
750 // 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions.
751 //===-------------------------------
753 // N.b. the commutable parameter is just !N. It will be first against the wall
754 // when the revolution comes.
755 multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable,
756 string asmop, SDPatternOperator opfrag, string sty,
757 RegisterClass GPR, list<Register> defs> {
758 let isCommutable = commutable, Defs = defs in {
759 def _lsl : A64I_addsubshift<sf, op, s, 0b00,
761 (ins GPR:$Rn, GPR:$Rm,
762 !cast<Operand>("lsl_operand_" # sty):$Imm6),
763 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
764 [(set GPR:$Rd, (opfrag GPR:$Rn, (shl GPR:$Rm,
765 !cast<Operand>("lsl_operand_" # sty):$Imm6))
769 def _lsr : A64I_addsubshift<sf, op, s, 0b01,
771 (ins GPR:$Rn, GPR:$Rm,
772 !cast<Operand>("lsr_operand_" # sty):$Imm6),
773 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
774 [(set GPR:$Rd, (opfrag GPR:$Rn, (srl GPR:$Rm,
775 !cast<Operand>("lsr_operand_" # sty):$Imm6))
779 def _asr : A64I_addsubshift<sf, op, s, 0b10,
781 (ins GPR:$Rn, GPR:$Rm,
782 !cast<Operand>("asr_operand_" # sty):$Imm6),
783 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
784 [(set GPR:$Rd, (opfrag GPR:$Rn, (sra GPR:$Rm,
785 !cast<Operand>("asr_operand_" # sty):$Imm6))
791 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
792 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
795 def : Pat<(opfrag GPR:$Rn, GPR:$Rm),
796 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
799 multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable,
800 string asmop, SDPatternOperator opfrag,
801 list<Register> defs> {
802 defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s,
803 commutable, asmop, opfrag, "i64", GPR64, defs>;
804 defm www : addsub_shifts<prefix # "www", 0b0, op, s,
805 commutable, asmop, opfrag, "i32", GPR32, defs>;
809 defm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>;
810 defm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>;
812 defm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>;
813 defm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>;
815 //===-------------------------------
816 // 1. The NEG/NEGS aliases
817 //===-------------------------------
819 multiclass neg_alias<Instruction INST, RegisterClass GPR,
820 Register ZR, Operand shift_operand, SDNode shiftop> {
821 def : InstAlias<"neg $Rd, $Rm, $Imm6",
822 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
824 def : Pat<(sub 0, (shiftop GPR:$Rm, shift_operand:$Imm6)),
825 (INST ZR, GPR:$Rm, shift_operand:$Imm6)>;
828 defm : neg_alias<SUBwww_lsl, GPR32, WZR, lsl_operand_i32, shl>;
829 defm : neg_alias<SUBwww_lsr, GPR32, WZR, lsr_operand_i32, srl>;
830 defm : neg_alias<SUBwww_asr, GPR32, WZR, asr_operand_i32, sra>;
831 def : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
832 def : Pat<(sub 0, GPR32:$Rm), (SUBwww_lsl WZR, GPR32:$Rm, 0)>;
834 defm : neg_alias<SUBxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>;
835 defm : neg_alias<SUBxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>;
836 defm : neg_alias<SUBxxx_asr, GPR64, XZR, asr_operand_i64, sra>;
837 def : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
838 def : Pat<(sub 0, GPR64:$Rm), (SUBxxx_lsl XZR, GPR64:$Rm, 0)>;
840 // NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to
842 class negs_alias<Instruction INST, RegisterClass GPR,
843 Register ZR, Operand shift_operand, SDNode shiftop>
844 : InstAlias<"negs $Rd, $Rm, $Imm6",
845 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
847 def : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>;
848 def : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>;
849 def : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>;
850 def : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
852 def : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>;
853 def : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>;
854 def : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>;
855 def : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
857 //===-------------------------------
858 // 1. The CMP/CMN aliases
859 //===-------------------------------
861 multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable,
862 string asmop, SDPatternOperator opfrag, string sty,
864 let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in {
865 def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00,
867 (ins GPR:$Rn, GPR:$Rm,
868 !cast<Operand>("lsl_operand_" # sty):$Imm6),
869 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
870 [(set NZCV, (opfrag GPR:$Rn, (shl GPR:$Rm,
871 !cast<Operand>("lsl_operand_" # sty):$Imm6))
875 def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01,
877 (ins GPR:$Rn, GPR:$Rm,
878 !cast<Operand>("lsr_operand_" # sty):$Imm6),
879 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
880 [(set NZCV, (opfrag GPR:$Rn, (srl GPR:$Rm,
881 !cast<Operand>("lsr_operand_" # sty):$Imm6))
885 def _asr : A64I_addsubshift<sf, op, 0b1, 0b10,
887 (ins GPR:$Rn, GPR:$Rm,
888 !cast<Operand>("asr_operand_" # sty):$Imm6),
889 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
890 [(set NZCV, (opfrag GPR:$Rn, (sra GPR:$Rm,
891 !cast<Operand>("asr_operand_" # sty):$Imm6))
897 : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
898 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
900 def : Pat<(opfrag GPR:$Rn, GPR:$Rm),
901 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
904 defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, "i32", GPR32>;
905 defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, "i64", GPR64>;
907 defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, "i32", GPR32>;
908 defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, "i64", GPR64>;
910 //===----------------------------------------------------------------------===//
911 // Add-subtract (with carry) instructions
912 //===----------------------------------------------------------------------===//
913 // Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS
915 multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> {
916 let Uses = [NZCV] in {
917 def www : A64I_addsubcarry<0b0, op, s, 0b000000,
918 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
919 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
922 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,
923 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
924 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
929 let isCommutable = 1 in {
930 defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">;
933 defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">;
935 let Defs = [NZCV] in {
936 let isCommutable = 1 in {
937 defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">;
940 defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">;
943 def : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>;
944 def : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
945 def : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>;
946 def : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
948 // Note that adde and sube can form a chain longer than two (e.g. for 256-bit
949 // addition). So the flag-setting instructions are appropriate.
950 def : Pat<(adde GPR32:$Rn, GPR32:$Rm), (ADCSwww GPR32:$Rn, GPR32:$Rm)>;
951 def : Pat<(adde GPR64:$Rn, GPR64:$Rm), (ADCSxxx GPR64:$Rn, GPR64:$Rm)>;
952 def : Pat<(sube GPR32:$Rn, GPR32:$Rm), (SBCSwww GPR32:$Rn, GPR32:$Rm)>;
953 def : Pat<(sube GPR64:$Rn, GPR64:$Rm), (SBCSxxx GPR64:$Rn, GPR64:$Rm)>;
955 //===----------------------------------------------------------------------===//
957 //===----------------------------------------------------------------------===//
958 // Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL,
961 // Because of the rather complicated nearly-overlapping aliases, the decoding of
962 // this range of instructions is handled manually. The architectural
963 // instructions are BFM, SBFM and UBFM but a disassembler should never produce
966 // In the end, the best option was to use BFM instructions for decoding under
967 // almost all circumstances, but to create aliasing *Instructions* for each of
968 // the canonical forms and specify a completely custom decoder which would
969 // substitute the correct MCInst as needed.
971 // This also simplifies instruction selection, parsing etc because the MCInsts
972 // have a shape that's closer to their use in code.
974 //===-------------------------------
975 // 1. The architectural BFM instructions
976 //===-------------------------------
978 def uimm5_asmoperand : AsmOperandClass {
980 let PredicateMethod = "isUImm<5>";
981 let RenderMethod = "addImmOperands";
982 let DiagnosticType = "UImm5";
985 def uimm6_asmoperand : AsmOperandClass {
987 let PredicateMethod = "isUImm<6>";
988 let RenderMethod = "addImmOperands";
989 let DiagnosticType = "UImm6";
992 def bitfield32_imm : Operand<i64>,
993 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> {
994 let ParserMatchClass = uimm5_asmoperand;
996 let DecoderMethod = "DecodeBitfield32ImmOperand";
1000 def bitfield64_imm : Operand<i64>,
1001 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
1002 let ParserMatchClass = uimm6_asmoperand;
1004 // Default decoder works in 64-bit case: the 6-bit field can take any value.
1007 multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> {
1008 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1009 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1010 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1012 let DecoderMethod = "DecodeBitfieldInstruction";
1015 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1016 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1017 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1019 let DecoderMethod = "DecodeBitfieldInstruction";
1023 defm SBFM : A64I_bitfieldSizes<0b00, "sbfm">;
1024 defm UBFM : A64I_bitfieldSizes<0b10, "ubfm">;
1026 // BFM instructions modify the destination register rather than defining it
1029 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1030 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1031 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1032 let DecoderMethod = "DecodeBitfieldInstruction";
1033 let Constraints = "$src = $Rd";
1037 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1038 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1039 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1040 let DecoderMethod = "DecodeBitfieldInstruction";
1041 let Constraints = "$src = $Rd";
1045 //===-------------------------------
1046 // 2. Extend aliases to 64-bit dest
1047 //===-------------------------------
1049 // Unfortunately the extensions that end up as 64-bits cannot be handled by an
1050 // instruction alias: their syntax is (for example) "SXTB x0, w0", which needs
1051 // to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is
1052 // not capable of such a map as far as I'm aware
1054 // Note that these instructions are strictly more specific than the
1055 // BFM ones (in ImmR) so they can handle their own decoding.
1056 class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, string asmop,
1057 bits<6> imms, dag pattern>
1058 : A64I_bitfield<sf, opc, sf,
1059 (outs GPRDest:$Rd), (ins GPR32:$Rn),
1060 !strconcat(asmop, "\t$Rd, $Rn"),
1061 [(set GPRDest:$Rd, pattern)], NoItinerary> {
1062 let ImmR = 0b000000;
1066 // Signed extensions
1067 def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, "sxtb", 7,
1068 (sext_inreg (anyext GPR32:$Rn), i8)>;
1069 def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, "sxtb", 7,
1070 (sext_inreg GPR32:$Rn, i8)>;
1071 def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, "sxth", 15,
1072 (sext_inreg (anyext GPR32:$Rn), i16)>;
1073 def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, "sxth", 15,
1074 (sext_inreg GPR32:$Rn, i16)>;
1075 def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, "sxtw", 31, (sext GPR32:$Rn)>;
1077 // Unsigned extensions
1078 def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, "uxtb", 7,
1079 (and GPR32:$Rn, 255)>;
1080 def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, "uxth", 15,
1081 (and GPR32:$Rn, 65535)>;
1083 // The 64-bit unsigned variants are not strictly architectural but recommended
1085 let isAsmParserOnly = 1 in {
1086 def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, "uxtb", 7,
1087 (and (anyext GPR32:$Rn), 255)>;
1088 def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, "uxth", 15,
1089 (and (anyext GPR32:$Rn), 65535)>;
1092 // Extra patterns for when the source register is actually 64-bits
1093 // too. There's no architectural difference here, it's just LLVM
1094 // shinanigans. There's no need for equivalent zero-extension patterns
1095 // because they'll already be caught by logical (immediate) matching.
1096 def : Pat<(sext_inreg GPR64:$Rn, i8),
1097 (SXTBxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
1098 def : Pat<(sext_inreg GPR64:$Rn, i16),
1099 (SXTHxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
1100 def : Pat<(sext_inreg GPR64:$Rn, i32),
1101 (SXTWxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
1104 //===-------------------------------
1105 // 3. Aliases for ASR and LSR (the simple shifts)
1106 //===-------------------------------
1108 // These also handle their own decoding because ImmS being set makes
1109 // them take precedence over BFM.
1110 multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> {
1111 def wwi : A64I_bitfield<0b0, opc, 0b0,
1112 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
1113 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1114 [(set GPR32:$Rd, (opnode GPR32:$Rn, bitfield32_imm:$ImmR))],
1119 def xxi : A64I_bitfield<0b1, opc, 0b1,
1120 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
1121 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1122 [(set GPR64:$Rd, (opnode GPR64:$Rn, bitfield64_imm:$ImmR))],
1129 defm ASR : A64I_shift<0b00, "asr", sra>;
1130 defm LSR : A64I_shift<0b10, "lsr", srl>;
1132 //===-------------------------------
1133 // 4. Aliases for LSL
1134 //===-------------------------------
1136 // Unfortunately LSL and subsequent aliases are much more complicated. We need
1137 // to be able to say certain output instruction fields depend in a complex
1138 // manner on combinations of input assembly fields).
1140 // MIOperandInfo *might* have been able to do it, but at the cost of
1141 // significantly more C++ code.
1143 // N.b. contrary to usual practice these operands store the shift rather than
1144 // the machine bits in an MCInst. The complexity overhead of consistency
1145 // outweighed the benefits in this case (custom asmparser, printer and selection
1146 // vs custom encoder).
1147 def bitfield32_lsl_imm : Operand<i64>,
1148 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1149 let ParserMatchClass = uimm5_asmoperand;
1150 let EncoderMethod = "getBitfield32LSLOpValue";
1153 def bitfield64_lsl_imm : Operand<i64>,
1154 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1155 let ParserMatchClass = uimm6_asmoperand;
1156 let EncoderMethod = "getBitfield64LSLOpValue";
1159 class A64I_bitfield_lsl<bit sf, RegisterClass GPR, Operand operand>
1160 : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),
1161 "lsl\t$Rd, $Rn, $FullImm",
1162 [(set GPR:$Rd, (shl GPR:$Rn, operand:$FullImm))],
1165 let ImmR = FullImm{5-0};
1166 let ImmS = FullImm{11-6};
1168 // No disassembler allowed because it would overlap with BFM which does the
1170 let isAsmParserOnly = 1;
1173 def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, bitfield32_lsl_imm>;
1174 def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, bitfield64_lsl_imm>;
1176 //===-------------------------------
1177 // 5. Aliases for bitfield extract instructions
1178 //===-------------------------------
1180 def bfx32_width_asmoperand : AsmOperandClass {
1181 let Name = "BFX32Width";
1182 let PredicateMethod = "isBitfieldWidth<32>";
1183 let RenderMethod = "addBFXWidthOperands";
1184 let DiagnosticType = "Width32";
1187 def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> {
1188 let PrintMethod = "printBFXWidthOperand";
1189 let ParserMatchClass = bfx32_width_asmoperand;
1192 def bfx64_width_asmoperand : AsmOperandClass {
1193 let Name = "BFX64Width";
1194 let PredicateMethod = "isBitfieldWidth<64>";
1195 let RenderMethod = "addBFXWidthOperands";
1196 let DiagnosticType = "Width64";
1199 def bfx64_width : Operand<i64> {
1200 let PrintMethod = "printBFXWidthOperand";
1201 let ParserMatchClass = bfx64_width_asmoperand;
1205 multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> {
1206 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1207 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1208 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1209 [(set GPR32:$Rd, (op GPR32:$Rn, imm:$ImmR, imm:$ImmS))],
1211 // As above, no disassembler allowed.
1212 let isAsmParserOnly = 1;
1215 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1216 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1217 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1218 [(set GPR64:$Rd, (op GPR64:$Rn, imm:$ImmR, imm:$ImmS))],
1220 // As above, no disassembler allowed.
1221 let isAsmParserOnly = 1;
1225 defm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>;
1226 defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>;
1228 // Again, variants based on BFM modify Rd so need it as an input too.
1229 def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1230 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1231 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1232 // As above, no disassembler allowed.
1233 let isAsmParserOnly = 1;
1234 let Constraints = "$src = $Rd";
1237 def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1238 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1239 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1240 // As above, no disassembler allowed.
1241 let isAsmParserOnly = 1;
1242 let Constraints = "$src = $Rd";
1245 // SBFX instructions can do a 1-instruction sign-extension of boolean values.
1246 def : Pat<(sext_inreg GPR64:$Rn, i1), (SBFXxxii GPR64:$Rn, 0, 0)>;
1247 def : Pat<(sext_inreg GPR32:$Rn, i1), (SBFXwwii GPR32:$Rn, 0, 0)>;
1248 def : Pat<(i64 (sext_inreg (anyext GPR32:$Rn), i1)),
1249 (SBFXxxii (SUBREG_TO_REG (i64 0), GPR32:$Rn, sub_32), 0, 0)>;
1251 // UBFX makes sense as an implementation of a 64-bit zero-extension too. Could
1252 // use either 64-bit or 32-bit variant, but 32-bit might be more efficient.
1253 def : Pat<(zext GPR32:$Rn), (SUBREG_TO_REG (i64 0), (UBFXwwii GPR32:$Rn, 0, 31),
1256 //===-------------------------------
1257 // 6. Aliases for bitfield insert instructions
1258 //===-------------------------------
1260 def bfi32_lsb_asmoperand : AsmOperandClass {
1261 let Name = "BFI32LSB";
1262 let PredicateMethod = "isUImm<5>";
1263 let RenderMethod = "addBFILSBOperands<32>";
1264 let DiagnosticType = "UImm5";
1267 def bfi32_lsb : Operand<i64>,
1268 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1269 let PrintMethod = "printBFILSBOperand<32>";
1270 let ParserMatchClass = bfi32_lsb_asmoperand;
1273 def bfi64_lsb_asmoperand : AsmOperandClass {
1274 let Name = "BFI64LSB";
1275 let PredicateMethod = "isUImm<6>";
1276 let RenderMethod = "addBFILSBOperands<64>";
1277 let DiagnosticType = "UImm6";
1280 def bfi64_lsb : Operand<i64>,
1281 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1282 let PrintMethod = "printBFILSBOperand<64>";
1283 let ParserMatchClass = bfi64_lsb_asmoperand;
1286 // Width verification is performed during conversion so width operand can be
1287 // shared between 32/64-bit cases. Still needed for the print method though
1288 // because ImmR encodes "width - 1".
1289 def bfi32_width_asmoperand : AsmOperandClass {
1290 let Name = "BFI32Width";
1291 let PredicateMethod = "isBitfieldWidth<32>";
1292 let RenderMethod = "addBFIWidthOperands";
1293 let DiagnosticType = "Width32";
1296 def bfi32_width : Operand<i64>,
1297 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> {
1298 let PrintMethod = "printBFIWidthOperand";
1299 let ParserMatchClass = bfi32_width_asmoperand;
1302 def bfi64_width_asmoperand : AsmOperandClass {
1303 let Name = "BFI64Width";
1304 let PredicateMethod = "isBitfieldWidth<64>";
1305 let RenderMethod = "addBFIWidthOperands";
1306 let DiagnosticType = "Width64";
1309 def bfi64_width : Operand<i64>,
1310 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> {
1311 let PrintMethod = "printBFIWidthOperand";
1312 let ParserMatchClass = bfi64_width_asmoperand;
1315 multiclass A64I_bitfield_insert<bits<2> opc, string asmop> {
1316 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1317 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1318 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1320 // As above, no disassembler allowed.
1321 let isAsmParserOnly = 1;
1324 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1325 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1326 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1328 // As above, no disassembler allowed.
1329 let isAsmParserOnly = 1;
1333 defm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">;
1334 defm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">;
1337 def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1338 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1339 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1340 // As above, no disassembler allowed.
1341 let isAsmParserOnly = 1;
1342 let Constraints = "$src = $Rd";
1345 def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1346 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1347 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1348 // As above, no disassembler allowed.
1349 let isAsmParserOnly = 1;
1350 let Constraints = "$src = $Rd";
1353 //===----------------------------------------------------------------------===//
1354 // Compare and branch (immediate)
1355 //===----------------------------------------------------------------------===//
1356 // Contains: CBZ, CBNZ
1358 class label_asmoperand<int width, int scale> : AsmOperandClass {
1359 let Name = "Label" # width # "_" # scale;
1360 let PredicateMethod = "isLabel<" # width # "," # scale # ">";
1361 let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">";
1362 let DiagnosticType = "Label";
1365 def label_wid19_scal4_asmoperand : label_asmoperand<19, 4>;
1367 // All conditional immediate branches are the same really: 19 signed bits scaled
1368 // by the instruction-size (4).
1369 def bcc_target : Operand<OtherVT> {
1370 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
1371 let ParserMatchClass = label_wid19_scal4_asmoperand;
1372 let PrintMethod = "printLabelOperand<19, 4>";
1373 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>";
1374 let OperandType = "OPERAND_PCREL";
1377 multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> {
1378 let isBranch = 1, isTerminator = 1 in {
1379 def x : A64I_cmpbr<0b1, op,
1381 (ins GPR64:$Rt, bcc_target:$Label),
1382 !strconcat(asmop,"\t$Rt, $Label"),
1383 [(A64br_cc (A64cmp GPR64:$Rt, 0), SETOP, bb:$Label)],
1386 def w : A64I_cmpbr<0b0, op,
1388 (ins GPR32:$Rt, bcc_target:$Label),
1389 !strconcat(asmop,"\t$Rt, $Label"),
1390 [(A64br_cc (A64cmp GPR32:$Rt, 0), SETOP, bb:$Label)],
1395 defm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{
1396 return Imm == A64CC::EQ;
1398 defm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{
1399 return Imm == A64CC::NE;
1402 //===----------------------------------------------------------------------===//
1403 // Conditional branch (immediate) instructions
1404 //===----------------------------------------------------------------------===//
1407 def cond_code_asmoperand : AsmOperandClass {
1408 let Name = "CondCode";
1409 let DiagnosticType = "CondCode";
1412 def cond_code : Operand<i32>, ImmLeaf<i32, [{
1413 return Imm >= 0 && Imm <= 15;
1415 let PrintMethod = "printCondCodeOperand";
1416 let ParserMatchClass = cond_code_asmoperand;
1419 def Bcc : A64I_condbr<0b0, 0b0, (outs),
1420 (ins cond_code:$Cond, bcc_target:$Label),
1421 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
1425 let isTerminator = 1;
1428 //===----------------------------------------------------------------------===//
1429 // Conditional compare (immediate) instructions
1430 //===----------------------------------------------------------------------===//
1431 // Contains: CCMN, CCMP
1433 def uimm4_asmoperand : AsmOperandClass {
1435 let PredicateMethod = "isUImm<4>";
1436 let RenderMethod = "addImmOperands";
1437 let DiagnosticType = "UImm4";
1440 def uimm4 : Operand<i32> {
1441 let ParserMatchClass = uimm4_asmoperand;
1444 def uimm5 : Operand<i32> {
1445 let ParserMatchClass = uimm5_asmoperand;
1448 // The only difference between this operand and the one for instructions like
1449 // B.cc is that it's parsed manually. The other get parsed implicitly as part of
1450 // the mnemonic handling.
1451 def cond_code_op_asmoperand : AsmOperandClass {
1452 let Name = "CondCodeOp";
1453 let RenderMethod = "addCondCodeOperands";
1454 let PredicateMethod = "isCondCode";
1455 let ParserMethod = "ParseCondCodeOperand";
1456 let DiagnosticType = "CondCode";
1459 def cond_code_op : Operand<i32> {
1460 let PrintMethod = "printCondCodeOperand";
1461 let ParserMatchClass = cond_code_op_asmoperand;
1464 class A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1465 : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),
1466 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
1467 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
1472 def CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">;
1473 def CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">;
1474 def CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">;
1475 def CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">;
1477 //===----------------------------------------------------------------------===//
1478 // Conditional compare (register) instructions
1479 //===----------------------------------------------------------------------===//
1480 // Contains: CCMN, CCMP
1482 class A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1483 : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1,
1485 (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
1486 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
1491 def CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">;
1492 def CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">;
1493 def CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">;
1494 def CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">;
1496 //===----------------------------------------------------------------------===//
1497 // Conditional select instructions
1498 //===----------------------------------------------------------------------===//
1499 // Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG
1501 // Condition code which is encoded as the inversion (semantically rather than
1502 // bitwise) in the instruction.
1503 def inv_cond_code_op_asmoperand : AsmOperandClass {
1504 let Name = "InvCondCodeOp";
1505 let RenderMethod = "addInvCondCodeOperands";
1506 let PredicateMethod = "isCondCode";
1507 let ParserMethod = "ParseCondCodeOperand";
1508 let DiagnosticType = "CondCode";
1511 def inv_cond_code_op : Operand<i32> {
1512 let ParserMatchClass = inv_cond_code_op_asmoperand;
1515 // Having a separate operand for the selectable use-case is debatable, but gives
1516 // consistency with cond_code.
1517 def inv_cond_XFORM : SDNodeXForm<imm, [{
1518 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue());
1519 return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32);
1523 : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>;
1526 multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
1527 SDPatternOperator select> {
1528 let Uses = [NZCV] in {
1529 def wwwc : A64I_condsel<0b0, op, 0b0, op2,
1531 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
1532 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1533 [(set GPR32:$Rd, (select GPR32:$Rn, GPR32:$Rm))],
1537 def xxxc : A64I_condsel<0b1, op, 0b0, op2,
1539 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
1540 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1541 [(set GPR64:$Rd, (select GPR64:$Rn, GPR64:$Rm))],
1547 : PatFrag<(ops node:$lhs, node:$rhs),
1548 (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>;
1550 class complex_select<SDPatternOperator opnode>
1551 : PatFrag<(ops node:$lhs, node:$rhs),
1552 (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>;
1555 defm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>;
1556 defm CSINC : A64I_condselSizes<0b0, 0b01, "csinc",
1557 complex_select<PatFrag<(ops node:$val),
1558 (add node:$val, 1)>>>;
1559 defm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>;
1560 defm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>;
1562 // Now the instruction aliases, which fit nicely into LLVM's model:
1564 def : InstAlias<"cset $Rd, $Cond",
1565 (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1566 def : InstAlias<"cset $Rd, $Cond",
1567 (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1568 def : InstAlias<"csetm $Rd, $Cond",
1569 (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1570 def : InstAlias<"csetm $Rd, $Cond",
1571 (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1572 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1573 (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1574 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1575 (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1576 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1577 (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1578 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1579 (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1580 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1581 (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1582 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1583 (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1585 // Finally some helper patterns.
1587 // For CSET (a.k.a. zero-extension of icmp)
1588 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1589 (CSINCwwwc WZR, WZR, cond_code:$Cond)>;
1590 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1591 (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>;
1593 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1594 (CSINCxxxc XZR, XZR, cond_code:$Cond)>;
1595 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1596 (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>;
1598 // For CSETM (a.k.a. sign-extension of icmp)
1599 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1600 (CSINVwwwc WZR, WZR, cond_code:$Cond)>;
1601 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1602 (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>;
1604 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1605 (CSINVxxxc XZR, XZR, cond_code:$Cond)>;
1606 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1607 (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>;
1609 // CINC, CINV and CNEG get dealt with automatically, which leaves the issue of
1610 // commutativity. The instructions are to complex for isCommutable to be used,
1611 // so we have to create the patterns manually:
1613 // No commutable pattern for CSEL since the commuted version is isomorphic.
1616 def :Pat<(A64select_cc NZCV, (add GPR32:$Rm, 1), GPR32:$Rn,
1617 inv_cond_code:$Cond),
1618 (CSINCwwwc GPR32:$Rn, GPR32:$Rm, inv_cond_code:$Cond)>;
1619 def :Pat<(A64select_cc NZCV, (add GPR64:$Rm, 1), GPR64:$Rn,
1620 inv_cond_code:$Cond),
1621 (CSINCxxxc GPR64:$Rn, GPR64:$Rm, inv_cond_code:$Cond)>;
1624 def :Pat<(A64select_cc NZCV, (not GPR32:$Rm), GPR32:$Rn, inv_cond_code:$Cond),
1625 (CSINVwwwc GPR32:$Rn, GPR32:$Rm, inv_cond_code:$Cond)>;
1626 def :Pat<(A64select_cc NZCV, (not GPR64:$Rm), GPR64:$Rn, inv_cond_code:$Cond),
1627 (CSINVxxxc GPR64:$Rn, GPR64:$Rm, inv_cond_code:$Cond)>;
1630 def :Pat<(A64select_cc NZCV, (ineg GPR32:$Rm), GPR32:$Rn, inv_cond_code:$Cond),
1631 (CSNEGwwwc GPR32:$Rn, GPR32:$Rm, inv_cond_code:$Cond)>;
1632 def :Pat<(A64select_cc NZCV, (ineg GPR64:$Rm), GPR64:$Rn, inv_cond_code:$Cond),
1633 (CSNEGxxxc GPR64:$Rn, GPR64:$Rm, inv_cond_code:$Cond)>;
1635 //===----------------------------------------------------------------------===//
1636 // Data Processing (1 source) instructions
1637 //===----------------------------------------------------------------------===//
1638 // Contains: RBIT, REV16, REV, REV32, CLZ, CLS.
1640 // We define an unary operator which always fails. We will use this to
1641 // define unary operators that cannot be matched.
1643 class A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop,
1644 list<dag> patterns, RegisterClass GPRrc,
1645 InstrItinClass itin>:
1650 !strconcat(asmop, "\t$Rd, $Rn"),
1656 multiclass A64I_dp_1src <bits<6> opcode, string asmop> {
1657 let hasSideEffects = 0 in {
1658 def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>;
1659 def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>;
1663 defm RBIT : A64I_dp_1src<0b000000, "rbit">;
1664 defm CLS : A64I_dp_1src<0b000101, "cls">;
1665 defm CLZ : A64I_dp_1src<0b000100, "clz">;
1667 def : Pat<(ctlz GPR32:$Rn), (CLZww GPR32:$Rn)>;
1668 def : Pat<(ctlz GPR64:$Rn), (CLZxx GPR64:$Rn)>;
1669 def : Pat<(ctlz_zero_undef GPR32:$Rn), (CLZww GPR32:$Rn)>;
1670 def : Pat<(ctlz_zero_undef GPR64:$Rn), (CLZxx GPR64:$Rn)>;
1672 def : Pat<(cttz GPR32:$Rn), (CLZww (RBITww GPR32:$Rn))>;
1673 def : Pat<(cttz GPR64:$Rn), (CLZxx (RBITxx GPR64:$Rn))>;
1674 def : Pat<(cttz_zero_undef GPR32:$Rn), (CLZww (RBITww GPR32:$Rn))>;
1675 def : Pat<(cttz_zero_undef GPR64:$Rn), (CLZxx (RBITxx GPR64:$Rn))>;
1678 def REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev",
1679 [(set GPR32:$Rd, (bswap GPR32:$Rn))],
1680 GPR32, NoItinerary>;
1681 def REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev",
1682 [(set GPR64:$Rd, (bswap GPR64:$Rn))],
1683 GPR64, NoItinerary>;
1684 def REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32",
1685 [(set GPR64:$Rd, (bswap (rotr GPR64:$Rn, (i64 32))))],
1686 GPR64, NoItinerary>;
1687 def REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16",
1688 [(set GPR32:$Rd, (bswap (rotr GPR32:$Rn, (i64 16))))],
1691 def REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>;
1693 //===----------------------------------------------------------------------===//
1694 // Data Processing (2 sources) instructions
1695 //===----------------------------------------------------------------------===//
1696 // Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL,
1700 class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns,
1701 RegisterClass GPRsp,
1702 InstrItinClass itin>:
1706 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
1708 (ins GPRsp:$Rn, GPRsp:$Rm),
1712 multiclass dp_2src_crc<bit c, string asmop> {
1713 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
1714 !strconcat(asmop, "b"), [], GPR32, NoItinerary>;
1715 def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1},
1716 !strconcat(asmop, "h"), [], GPR32, NoItinerary>;
1717 def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0},
1718 !strconcat(asmop, "w"), [], GPR32, NoItinerary>;
1719 def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
1720 !strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
1721 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
1725 multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
1726 def www : dp_2src_impl<0b0,
1730 (op GPR32:$Rn, (i64 (zext GPR32:$Rm))))],
1733 def xxx : dp_2src_impl<0b1,
1736 [(set GPR64:$Rd, (op GPR64:$Rn, GPR64:$Rm))],
1742 multiclass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> {
1743 def www : dp_2src_impl<0b0,
1746 [(set GPR32:$Rd, (op GPR32:$Rn, GPR32:$Rm))],
1749 def xxx : dp_2src_impl<0b1,
1752 [(set GPR64:$Rd, (op GPR64:$Rn, GPR64:$Rm))],
1757 // Here we define the data processing 2 source instructions.
1758 defm CRC32 : dp_2src_crc<0b0, "crc32">;
1759 defm CRC32C : dp_2src_crc<0b1, "crc32c">;
1761 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1762 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1764 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1765 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1766 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1767 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1769 // Extra patterns for an incoming 64-bit value for a 32-bit
1770 // operation. Since the LLVM operations are undefined (as in C) if the
1771 // RHS is out of range, it's perfectly permissible to discard the high
1772 // bits of the GPR64.
1773 def : Pat<(shl GPR32:$Rn, GPR64:$Rm),
1774 (LSLVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
1775 def : Pat<(srl GPR32:$Rn, GPR64:$Rm),
1776 (LSRVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
1777 def : Pat<(sra GPR32:$Rn, GPR64:$Rm),
1778 (ASRVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
1779 def : Pat<(rotr GPR32:$Rn, GPR64:$Rm),
1780 (RORVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
1782 // Here we define the aliases for the data processing 2 source instructions.
1783 def LSL_mnemonic : MnemonicAlias<"lslv", "lsl">;
1784 def LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">;
1785 def ASR_menmonic : MnemonicAlias<"asrv", "asr">;
1786 def ROR_menmonic : MnemonicAlias<"rorv", "ror">;
1788 //===----------------------------------------------------------------------===//
1789 // Data Processing (3 sources) instructions
1790 //===----------------------------------------------------------------------===//
1791 // Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH
1792 // + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL
1794 class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg,
1795 RegisterClass SrcReg, string asmop, dag pattern>
1796 : A64I_dp3<sf, opcode,
1797 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
1798 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
1799 [(set AccReg:$Rd, pattern)], NoItinerary> {
1800 RegisterClass AccGPR = AccReg;
1801 RegisterClass SrcGPR = SrcReg;
1804 def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, GPR32, "madd",
1805 (add GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm))>;
1806 def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, GPR64, "madd",
1807 (add GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm))>;
1809 def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, GPR32, "msub",
1810 (sub GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm))>;
1811 def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, GPR64, "msub",
1812 (sub GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm))>;
1814 def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, GPR32, "smaddl",
1815 (add GPR64:$Ra, (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm)))>;
1816 def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, GPR32, "smsubl",
1817 (sub GPR64:$Ra, (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm)))>;
1819 def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, GPR32, "umaddl",
1820 (add GPR64:$Ra, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
1821 def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, GPR32, "umsubl",
1822 (sub GPR64:$Ra, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
1824 let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in {
1825 def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd),
1826 (ins GPR64:$Rn, GPR64:$Rm),
1827 "umulh\t$Rd, $Rn, $Rm",
1828 [(set GPR64:$Rd, (mulhu GPR64:$Rn, GPR64:$Rm))],
1831 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
1832 (ins GPR64:$Rn, GPR64:$Rm),
1833 "smulh\t$Rd, $Rn, $Rm",
1834 [(set GPR64:$Rd, (mulhs GPR64:$Rn, GPR64:$Rm))],
1838 multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,
1839 Register ZR, dag pattern> {
1840 def : InstAlias<asmop # " $Rd, $Rn, $Rm",
1841 (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
1843 def : Pat<pattern, (INST INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
1846 defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul GPR32:$Rn, GPR32:$Rm)>;
1847 defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul GPR64:$Rn, GPR64:$Rm)>;
1849 defm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR,
1850 (sub 0, (mul GPR32:$Rn, GPR32:$Rm))>;
1851 defm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR,
1852 (sub 0, (mul GPR64:$Rn, GPR64:$Rm))>;
1854 defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR,
1855 (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm))>;
1856 defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR,
1857 (sub 0, (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm)))>;
1859 defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR,
1860 (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm))>;
1861 defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR,
1862 (sub 0, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
1865 //===----------------------------------------------------------------------===//
1866 // Exception generation
1867 //===----------------------------------------------------------------------===//
1868 // Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3
1870 def uimm16_asmoperand : AsmOperandClass {
1871 let Name = "UImm16";
1872 let PredicateMethod = "isUImm<16>";
1873 let RenderMethod = "addImmOperands";
1874 let DiagnosticType = "UImm16";
1877 def uimm16 : Operand<i32> {
1878 let ParserMatchClass = uimm16_asmoperand;
1881 class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop>
1882 : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),
1883 !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {
1885 let isTerminator = 1;
1888 def SVCi : A64I_exceptImpl<0b000, 0b01, "svc">;
1889 def HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">;
1890 def SMCi : A64I_exceptImpl<0b000, 0b11, "smc">;
1891 def BRKi : A64I_exceptImpl<0b001, 0b00, "brk">;
1892 def HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">;
1894 def DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">;
1895 def DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">;
1896 def DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">;
1898 // The immediate is optional for the DCPS instructions, defaulting to 0.
1899 def : InstAlias<"dcps1", (DCPS1i 0)>;
1900 def : InstAlias<"dcps2", (DCPS2i 0)>;
1901 def : InstAlias<"dcps3", (DCPS3i 0)>;
1903 //===----------------------------------------------------------------------===//
1904 // Extract (immediate)
1905 //===----------------------------------------------------------------------===//
1906 // Contains: EXTR + alias ROR
1908 def EXTRwwwi : A64I_extract<0b0, 0b000, 0b0,
1910 (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB),
1911 "extr\t$Rd, $Rn, $Rm, $LSB",
1913 (A64Extr GPR32:$Rn, GPR32:$Rm, imm:$LSB))],
1915 def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
1917 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
1918 "extr\t$Rd, $Rn, $Rm, $LSB",
1920 (A64Extr GPR64:$Rn, GPR64:$Rm, imm:$LSB))],
1923 def : InstAlias<"ror $Rd, $Rs, $LSB",
1924 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;
1925 def : InstAlias<"ror $Rd, $Rs, $LSB",
1926 (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>;
1928 def : Pat<(rotr GPR32:$Rn, bitfield32_imm:$LSB),
1929 (EXTRwwwi GPR32:$Rn, GPR32:$Rn, bitfield32_imm:$LSB)>;
1930 def : Pat<(rotr GPR64:$Rn, bitfield64_imm:$LSB),
1931 (EXTRxxxi GPR64:$Rn, GPR64:$Rn, bitfield64_imm:$LSB)>;
1933 //===----------------------------------------------------------------------===//
1934 // Floating-point compare instructions
1935 //===----------------------------------------------------------------------===//
1936 // Contains: FCMP, FCMPE
1938 def fpzero_asmoperand : AsmOperandClass {
1939 let Name = "FPZero";
1940 let ParserMethod = "ParseFPImmOperand";
1941 let DiagnosticType = "FPZero";
1944 def fpz32 : Operand<f32>,
1945 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
1946 let ParserMatchClass = fpzero_asmoperand;
1947 let PrintMethod = "printFPZeroOperand";
1948 let DecoderMethod = "DecodeFPZeroOperand";
1951 def fpz64 : Operand<f64>,
1952 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
1953 let ParserMatchClass = fpzero_asmoperand;
1954 let PrintMethod = "printFPZeroOperand";
1955 let DecoderMethod = "DecodeFPZeroOperand";
1958 multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {
1959 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
1960 (outs), ins, "fcmp\t$Rn, $Rm", [pattern],
1965 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
1966 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> {
1971 defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm),
1972 (set NZCV, (A64cmp (f32 FPR32:$Rn), FPR32:$Rm))>;
1973 defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm),
1974 (set NZCV, (A64cmp (f64 FPR64:$Rn), FPR64:$Rm))>;
1976 // What would be Rm should be written as 0; note that even though it's called
1977 // "$Rm" here to fit in with the InstrFormats, it's actually an immediate.
1978 defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm),
1979 (set NZCV, (A64cmp (f32 FPR32:$Rn), fpz32:$Rm))>;
1981 defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm),
1982 (set NZCV, (A64cmp (f64 FPR64:$Rn), fpz64:$Rm))>;
1985 //===----------------------------------------------------------------------===//
1986 // Floating-point conditional compare instructions
1987 //===----------------------------------------------------------------------===//
1988 // Contains: FCCMP, FCCMPE
1990 class A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop>
1991 : A64I_fpccmp<0b0, 0b0, type, op,
1993 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
1994 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
1999 def FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">;
2000 def FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">;
2001 def FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">;
2002 def FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">;
2004 //===----------------------------------------------------------------------===//
2005 // Floating-point conditional select instructions
2006 //===----------------------------------------------------------------------===//
2009 let Uses = [NZCV] in {
2010 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
2011 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
2012 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2014 (simple_select (f32 FPR32:$Rn),
2019 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
2020 (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond),
2021 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2023 (simple_select (f64 FPR64:$Rn),
2028 //===----------------------------------------------------------------------===//
2029 // Floating-point data-processing (1 source)
2030 //===----------------------------------------------------------------------===//
2031 // Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI].
2033 def FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val),
2034 [{ (void)N; return false; }]>;
2036 // First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d"
2037 // syntax. Default to no pattern because most are odd enough not to have one.
2038 multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr,
2039 SDPatternOperator opnode = FPNoUnop> {
2040 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
2041 !strconcat(asmstr, "\t$Rd, $Rn"),
2042 [(set (f32 FPR32:$Rd), (opnode FPR32:$Rn))],
2045 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
2046 !strconcat(asmstr, "\t$Rd, $Rn"),
2047 [(set (f64 FPR64:$Rd), (opnode FPR64:$Rn))],
2051 defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;
2052 defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;
2053 defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;
2054 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
2056 defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;
2057 defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;
2058 defm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>;
2059 defm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>;
2060 defm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">;
2061 defm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>;
2062 defm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>;
2064 // The FCVT instrucitons have different source and destination register-types,
2065 // but the fields are uniform everywhere a D-register (say) crops up. Package
2066 // this information in a Record.
2067 class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> {
2068 RegisterClass Class = rc;
2074 def FCVT16 : FCVTRegType<FPR16, 0b11, f16>;
2075 def FCVT32 : FCVTRegType<FPR32, 0b00, f32>;
2076 def FCVT64 : FCVTRegType<FPR64, 0b01, f64>;
2078 class A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode>
2079 : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0},
2080 {0,0,0,1, DestReg.t1, DestReg.t0},
2081 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
2083 [(set (DestReg.VT DestReg.Class:$Rd),
2084 (opnode (SrcReg.VT SrcReg.Class:$Rn)))], NoItinerary>;
2086 def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>;
2087 def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>;
2088 def FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>;
2089 def FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>;
2090 def FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>;
2091 def FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>;
2094 //===----------------------------------------------------------------------===//
2095 // Floating-point data-processing (2 sources) instructions
2096 //===----------------------------------------------------------------------===//
2097 // Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
2099 def FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs),
2100 [{ (void)N; return false; }]>;
2102 multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr,
2103 SDPatternOperator opnode> {
2104 def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode,
2106 (ins FPR32:$Rn, FPR32:$Rm),
2107 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2108 [(set (f32 FPR32:$Rd), (opnode FPR32:$Rn, FPR32:$Rm))],
2111 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
2113 (ins FPR64:$Rn, FPR64:$Rm),
2114 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2115 [(set (f64 FPR64:$Rd), (opnode FPR64:$Rn, FPR64:$Rm))],
2119 let isCommutable = 1 in {
2120 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
2121 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;
2123 // No patterns for these.
2124 defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>;
2125 defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>;
2126 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;
2127 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;
2129 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2130 PatFrag<(ops node:$lhs, node:$rhs),
2131 (fneg (fmul node:$lhs, node:$rhs))> >;
2134 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
2135 defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;
2137 //===----------------------------------------------------------------------===//
2138 // Floating-point data-processing (3 sources) instructions
2139 //===----------------------------------------------------------------------===//
2140 // Contains: FMADD, FMSUB, FNMADD, FNMSUB
2142 def fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2143 (fma (fneg node:$Rn), node:$Rm, node:$Ra)>;
2144 def fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2145 (fma node:$Rn, node:$Rm, (fneg node:$Ra))>;
2146 def fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2147 (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>;
2149 class A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT,
2150 bits<2> type, bit o1, bit o0, SDPatternOperator fmakind>
2151 : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd),
2152 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
2153 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
2154 [(set FPR:$Rd, (fmakind (VT FPR:$Rn), FPR:$Rm, FPR:$Ra))],
2157 def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
2158 def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;
2159 def FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>;
2160 def FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>;
2162 def FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>;
2163 def FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>;
2164 def FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>;
2165 def FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>;
2167 //===----------------------------------------------------------------------===//
2168 // Floating-point <-> fixed-point conversion instructions
2169 //===----------------------------------------------------------------------===//
2170 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2172 // #1-#32 allowed, encoded as "64 - <specified imm>
2173 def fixedpos_asmoperand_i32 : AsmOperandClass {
2174 let Name = "CVTFixedPos32";
2175 let RenderMethod = "addCVTFixedPosOperands";
2176 let PredicateMethod = "isCVTFixedPos<32>";
2177 let DiagnosticType = "CVTFixedPos32";
2180 // Also encoded as "64 - <specified imm>" but #1-#64 allowed.
2181 def fixedpos_asmoperand_i64 : AsmOperandClass {
2182 let Name = "CVTFixedPos64";
2183 let RenderMethod = "addCVTFixedPosOperands";
2184 let PredicateMethod = "isCVTFixedPos<64>";
2185 let DiagnosticType = "CVTFixedPos64";
2188 // We need the cartesian product of f32/f64 i32/i64 operands for
2190 // + Selection needs to use operands of correct floating type
2191 // + Assembly parsing and decoding depend on integer width
2192 class cvtfix_i32_op<ValueType FloatVT>
2194 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> {
2195 let ParserMatchClass = fixedpos_asmoperand_i32;
2196 let DecoderMethod = "DecodeCVT32FixedPosOperand";
2197 let PrintMethod = "printCVTFixedPosOperand";
2200 class cvtfix_i64_op<ValueType FloatVT>
2202 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> {
2203 let ParserMatchClass = fixedpos_asmoperand_i64;
2204 let PrintMethod = "printCVTFixedPosOperand";
2207 // Because of the proliferation of weird operands, it's not really
2208 // worth going for a multiclass here. Oh well.
2210 class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode,
2211 RegisterClass GPR, RegisterClass FPR, Operand scale_op,
2212 string asmop, SDNode cvtop>
2213 : A64I_fpfixed<sf, 0b0, type, 0b11, opcode,
2214 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
2215 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2216 [(set GPR:$Rd, (cvtop (fmul FPR:$Rn, scale_op:$Scale)))],
2219 def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32,
2220 cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>;
2221 def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32,
2222 cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>;
2223 def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32,
2224 cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>;
2225 def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32,
2226 cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>;
2228 def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64,
2229 cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>;
2230 def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64,
2231 cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>;
2232 def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64,
2233 cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>;
2234 def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64,
2235 cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>;
2238 class A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode,
2239 RegisterClass FPR, RegisterClass GPR, Operand scale_op,
2240 string asmop, SDNode cvtop>
2241 : A64I_fpfixed<sf, 0b0, type, 0b00, opcode,
2242 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
2243 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2244 [(set FPR:$Rd, (fdiv (cvtop GPR:$Rn), scale_op:$Scale))],
2247 def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32,
2248 cvtfix_i32_op<f32>, "scvtf", sint_to_fp>;
2249 def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64,
2250 cvtfix_i64_op<f32>, "scvtf", sint_to_fp>;
2251 def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32,
2252 cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>;
2253 def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64,
2254 cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>;
2255 def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32,
2256 cvtfix_i32_op<f64>, "scvtf", sint_to_fp>;
2257 def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64,
2258 cvtfix_i64_op<f64>, "scvtf", sint_to_fp>;
2259 def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32,
2260 cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>;
2261 def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64,
2262 cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>;
2264 //===----------------------------------------------------------------------===//
2265 // Floating-point <-> integer conversion instructions
2266 //===----------------------------------------------------------------------===//
2267 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2269 class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode,
2270 RegisterClass DestPR, RegisterClass SrcPR, string asmop>
2271 : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),
2272 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;
2274 multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {
2275 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
2276 GPR32, FPR32, asmop # "s">;
2277 def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0},
2278 GPR64, FPR32, asmop # "s">;
2279 def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1},
2280 GPR32, FPR32, asmop # "u">;
2281 def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1},
2282 GPR64, FPR32, asmop # "u">;
2284 def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0},
2285 GPR32, FPR64, asmop # "s">;
2286 def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0},
2287 GPR64, FPR64, asmop # "s">;
2288 def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1},
2289 GPR32, FPR64, asmop # "u">;
2290 def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1},
2291 GPR64, FPR64, asmop # "u">;
2294 defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">;
2295 defm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">;
2296 defm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">;
2297 defm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">;
2298 defm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">;
2300 def : Pat<(i32 (fp_to_sint FPR32:$Rn)), (FCVTZSws FPR32:$Rn)>;
2301 def : Pat<(i64 (fp_to_sint FPR32:$Rn)), (FCVTZSxs FPR32:$Rn)>;
2302 def : Pat<(i32 (fp_to_uint FPR32:$Rn)), (FCVTZUws FPR32:$Rn)>;
2303 def : Pat<(i64 (fp_to_uint FPR32:$Rn)), (FCVTZUxs FPR32:$Rn)>;
2304 def : Pat<(i32 (fp_to_sint (f64 FPR64:$Rn))), (FCVTZSwd FPR64:$Rn)>;
2305 def : Pat<(i64 (fp_to_sint (f64 FPR64:$Rn))), (FCVTZSxd FPR64:$Rn)>;
2306 def : Pat<(i32 (fp_to_uint (f64 FPR64:$Rn))), (FCVTZUwd FPR64:$Rn)>;
2307 def : Pat<(i64 (fp_to_uint (f64 FPR64:$Rn))), (FCVTZUxd FPR64:$Rn)>;
2309 multiclass A64I_inttofp<bit o0, string asmop> {
2310 def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>;
2311 def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>;
2312 def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>;
2313 def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>;
2316 defm S : A64I_inttofp<0b0, "scvtf">;
2317 defm U : A64I_inttofp<0b1, "ucvtf">;
2319 def : Pat<(f32 (sint_to_fp GPR32:$Rn)), (SCVTFsw GPR32:$Rn)>;
2320 def : Pat<(f32 (sint_to_fp GPR64:$Rn)), (SCVTFsx GPR64:$Rn)>;
2321 def : Pat<(f64 (sint_to_fp GPR32:$Rn)), (SCVTFdw GPR32:$Rn)>;
2322 def : Pat<(f64 (sint_to_fp GPR64:$Rn)), (SCVTFdx GPR64:$Rn)>;
2323 def : Pat<(f32 (uint_to_fp GPR32:$Rn)), (UCVTFsw GPR32:$Rn)>;
2324 def : Pat<(f32 (uint_to_fp GPR64:$Rn)), (UCVTFsx GPR64:$Rn)>;
2325 def : Pat<(f64 (uint_to_fp GPR32:$Rn)), (UCVTFdw GPR32:$Rn)>;
2326 def : Pat<(f64 (uint_to_fp GPR64:$Rn)), (UCVTFdx GPR64:$Rn)>;
2328 def FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">;
2329 def FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">;
2330 def FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">;
2331 def FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">;
2333 def : Pat<(i32 (bitconvert (f32 FPR32:$Rn))), (FMOVws FPR32:$Rn)>;
2334 def : Pat<(f32 (bitconvert (i32 GPR32:$Rn))), (FMOVsw GPR32:$Rn)>;
2335 def : Pat<(i64 (bitconvert (f64 FPR64:$Rn))), (FMOVxd FPR64:$Rn)>;
2336 def : Pat<(f64 (bitconvert (i64 GPR64:$Rn))), (FMOVdx GPR64:$Rn)>;
2338 def lane1_asmoperand : AsmOperandClass {
2340 let RenderMethod = "addImmOperands";
2341 let DiagnosticType = "Lane1";
2344 def lane1 : Operand<i32> {
2345 let ParserMatchClass = lane1_asmoperand;
2346 let PrintMethod = "printBareImmOperand";
2349 let DecoderMethod = "DecodeFMOVLaneInstruction" in {
2350 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
2351 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
2352 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;
2354 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,
2355 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),
2356 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>;
2359 def : InstAlias<"fmov $Rd, $Rn.2d[$Lane]",
2360 (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>;
2362 def : InstAlias<"fmov $Rd.2d[$Lane], $Rn",
2363 (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>;
2365 //===----------------------------------------------------------------------===//
2366 // Floating-point immediate instructions
2367 //===----------------------------------------------------------------------===//
2370 def fpimm_asmoperand : AsmOperandClass {
2371 let Name = "FMOVImm";
2372 let ParserMethod = "ParseFPImmOperand";
2373 let DiagnosticType = "FPImm";
2376 // The MCOperand for these instructions are the encoded 8-bit values.
2377 def SDXF_fpimm : SDNodeXForm<fpimm, [{
2379 A64Imms::isFPImm(N->getValueAPF(), Imm8);
2380 return CurDAG->getTargetConstant(Imm8, MVT::i32);
2383 class fmov_operand<ValueType FT>
2385 PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }],
2387 let PrintMethod = "printFPImmOperand";
2388 let ParserMatchClass = fpimm_asmoperand;
2391 def fmov32_operand : fmov_operand<f32>;
2392 def fmov64_operand : fmov_operand<f64>;
2394 class A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT,
2395 Operand fmov_operand>
2396 : A64I_fpimm<0b0, 0b0, type, 0b00000,
2398 (ins fmov_operand:$Imm8),
2400 [(set (VT Reg:$Rd), fmov_operand:$Imm8)],
2403 def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
2404 def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;
2406 //===----------------------------------------------------------------------===//
2407 // Load-register (literal) instructions
2408 //===----------------------------------------------------------------------===//
2409 // Contains: LDR, LDRSW, PRFM
2411 def ldrlit_label_asmoperand : AsmOperandClass {
2412 let Name = "LoadLitLabel";
2413 let RenderMethod = "addLabelOperands<19, 4>";
2414 let DiagnosticType = "Label";
2417 def ldrlit_label : Operand<i64> {
2418 let EncoderMethod = "getLoadLitLabelOpValue";
2420 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
2421 let PrintMethod = "printLabelOperand<19, 4>";
2422 let ParserMatchClass = ldrlit_label_asmoperand;
2423 let OperandType = "OPERAND_PCREL";
2426 // Various instructions take an immediate value (which can always be used),
2427 // where some numbers have a symbolic name to make things easier. These operands
2428 // and the associated functions abstract away the differences.
2429 multiclass namedimm<string prefix, string mapper> {
2430 def _asmoperand : AsmOperandClass {
2431 let Name = "NamedImm" # prefix;
2432 let PredicateMethod = "isUImm";
2433 let RenderMethod = "addImmOperands";
2434 let ParserMethod = "ParseNamedImmOperand<" # mapper # ">";
2435 let DiagnosticType = "NamedImm_" # prefix;
2438 def _op : Operand<i32> {
2439 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
2440 let PrintMethod = "printNamedImmOperand<" # mapper # ">";
2441 let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">";
2445 defm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">;
2447 class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg,
2448 list<dag> patterns = []>
2449 : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
2450 "ldr\t$Rt, $Imm19", patterns, NoItinerary>;
2452 let mayLoad = 1 in {
2453 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
2454 def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>;
2457 def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>;
2458 def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>;
2460 let mayLoad = 1 in {
2461 def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>;
2464 def LDRSWx_lit : A64I_LDRlit<0b10, 0b0,
2466 (ins ldrlit_label:$Imm19),
2467 "ldrsw\t$Rt, $Imm19",
2470 def PRFM_lit : A64I_LDRlit<0b11, 0b0,
2471 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
2472 "prfm\t$Rt, $Imm19",
2476 //===----------------------------------------------------------------------===//
2477 // Load-store exclusive instructions
2478 //===----------------------------------------------------------------------===//
2479 // Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB,
2480 // STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB,
2481 // STLRH, STLR, LDARB, LDARH, LDAR
2483 // Since these instructions have the undefined register bits set to 1 in
2484 // their canonical form, we need a post encoder method to set those bits
2485 // to 1 when encoding these instructions. We do this using the
2486 // fixLoadStoreExclusive function. This function has template parameters:
2488 // fixLoadStoreExclusive<int hasRs, int hasRt2>
2490 // hasRs indicates that the instruction uses the Rs field, so we won't set
2491 // it to 1 (and the same for Rt2). We don't need template parameters for
2492 // the other register fiels since Rt and Rn are always used.
2494 // This operand parses a GPR64xsp register, followed by an optional immediate
2496 def GPR64xsp0_asmoperand : AsmOperandClass {
2497 let Name = "GPR64xsp0";
2498 let PredicateMethod = "isWrappedReg";
2499 let RenderMethod = "addRegOperands";
2500 let ParserMethod = "ParseLSXAddressOperand";
2501 // Diagnostics are provided by ParserMethod
2504 def GPR64xsp0 : RegisterOperand<GPR64xsp> {
2505 let ParserMatchClass = GPR64xsp0_asmoperand;
2508 //===----------------------------------
2509 // Store-exclusive (releasing & normal)
2510 //===----------------------------------
2512 class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2513 dag ins, list<dag> pat,
2514 InstrItinClass itin> :
2515 A64I_LDSTex_stn <size,
2516 opcode{2}, 0, opcode{1}, opcode{0},
2518 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
2521 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
2524 multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
2525 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2526 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2529 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2530 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2533 def _word: A64I_SRexs_impl<0b10, opcode, asmstr,
2534 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2537 def _dword: A64I_SRexs_impl<0b11, opcode, asmstr,
2538 (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2542 defm STXR : A64I_SRex<"stxr", 0b000, "STXR">;
2543 defm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">;
2545 //===----------------------------------
2547 //===----------------------------------
2549 class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2550 dag ins, list<dag> pat,
2551 InstrItinClass itin> :
2552 A64I_LDSTex_tn <size,
2553 opcode{2}, 1, opcode{1}, opcode{0},
2555 !strconcat(asm, "\t$Rt, [$Rn]"),
2558 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2561 multiclass A64I_LRex<string asmstr, bits<3> opcode> {
2562 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2563 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2566 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2567 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2570 def _word: A64I_LRexs_impl<0b10, opcode, asmstr,
2571 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2574 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,
2575 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn),
2579 defm LDXR : A64I_LRex<"ldxr", 0b000>;
2580 defm LDAXR : A64I_LRex<"ldaxr", 0b001>;
2581 defm LDAR : A64I_LRex<"ldar", 0b101>;
2583 class acquiring_load<PatFrag base>
2584 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
2585 return cast<AtomicSDNode>(N)->getOrdering() == Acquire;
2588 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
2589 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
2590 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
2591 def atomic_load_acquire_64 : acquiring_load<atomic_load_64>;
2593 def : Pat<(atomic_load_acquire_8 GPR64xsp:$Rn), (LDAR_byte GPR64xsp0:$Rn)>;
2594 def : Pat<(atomic_load_acquire_16 GPR64xsp:$Rn), (LDAR_hword GPR64xsp0:$Rn)>;
2595 def : Pat<(atomic_load_acquire_32 GPR64xsp:$Rn), (LDAR_word GPR64xsp0:$Rn)>;
2596 def : Pat<(atomic_load_acquire_64 GPR64xsp:$Rn), (LDAR_dword GPR64xsp0:$Rn)>;
2598 //===----------------------------------
2599 // Store-release (no exclusivity)
2600 //===----------------------------------
2602 class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2603 dag ins, list<dag> pat,
2604 InstrItinClass itin> :
2605 A64I_LDSTex_tn <size,
2606 opcode{2}, 0, opcode{1}, opcode{0},
2608 !strconcat(asm, "\t$Rt, [$Rn]"),
2611 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2614 class releasing_store<PatFrag base>
2615 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
2616 return cast<AtomicSDNode>(N)->getOrdering() == Release;
2619 def atomic_store_release_8 : releasing_store<atomic_store_8>;
2620 def atomic_store_release_16 : releasing_store<atomic_store_16>;
2621 def atomic_store_release_32 : releasing_store<atomic_store_32>;
2622 def atomic_store_release_64 : releasing_store<atomic_store_64>;
2624 multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> {
2625 def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2626 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2627 [(atomic_store_release_8 GPR64xsp0:$Rn, GPR32:$Rt)],
2630 def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2631 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2632 [(atomic_store_release_16 GPR64xsp0:$Rn, GPR32:$Rt)],
2635 def _word: A64I_SLexs_impl<0b10, opcode, asmstr,
2636 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2637 [(atomic_store_release_32 GPR64xsp0:$Rn, GPR32:$Rt)],
2640 def _dword: A64I_SLexs_impl<0b11, opcode, asmstr,
2641 (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2642 [(atomic_store_release_64 GPR64xsp0:$Rn, GPR64:$Rt)],
2646 defm STLR : A64I_SLex<"stlr", 0b101, "STLR">;
2648 //===----------------------------------
2649 // Store-exclusive pair (releasing & normal)
2650 //===----------------------------------
2652 class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2653 dag ins, list<dag> pat,
2654 InstrItinClass itin> :
2655 A64I_LDSTex_stt2n <size,
2656 opcode{2}, 0, opcode{1}, opcode{0},
2658 !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"),
2664 multiclass A64I_SPex<string asmstr, bits<3> opcode> {
2665 def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs),
2666 (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2,
2670 def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs),
2671 (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2,
2676 defm STXP : A64I_SPex<"stxp", 0b010>;
2677 defm STLXP : A64I_SPex<"stlxp", 0b011>;
2679 //===----------------------------------
2680 // Load-exclusive pair (acquiring & normal)
2681 //===----------------------------------
2683 class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2684 dag ins, list<dag> pat,
2685 InstrItinClass itin> :
2686 A64I_LDSTex_tt2n <size,
2687 opcode{2}, 1, opcode{1}, opcode{0},
2689 !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"),
2692 let DecoderMethod = "DecodeLoadPairExclusiveInstruction";
2693 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
2696 multiclass A64I_LPex<string asmstr, bits<3> opcode> {
2697 def _word: A64I_LPexs_impl<0b10, opcode, asmstr,
2698 (outs GPR32:$Rt, GPR32:$Rt2),
2699 (ins GPR64xsp0:$Rn),
2702 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
2703 (outs GPR64:$Rt, GPR64:$Rt2),
2704 (ins GPR64xsp0:$Rn),
2708 defm LDXP : A64I_LPex<"ldxp", 0b010>;
2709 defm LDAXP : A64I_LPex<"ldaxp", 0b011>;
2711 //===----------------------------------------------------------------------===//
2712 // Load-store register (unscaled immediate) instructions
2713 //===----------------------------------------------------------------------===//
2714 // Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM
2718 //===----------------------------------------------------------------------===//
2719 // Load-store register (register offset) instructions
2720 //===----------------------------------------------------------------------===//
2721 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2725 //===----------------------------------------------------------------------===//
2726 // Load-store register (unsigned immediate) instructions
2727 //===----------------------------------------------------------------------===//
2728 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2732 //===----------------------------------------------------------------------===//
2733 // Load-store register (immediate post-indexed) instructions
2734 //===----------------------------------------------------------------------===//
2735 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2739 //===----------------------------------------------------------------------===//
2740 // Load-store register (immediate pre-indexed) instructions
2741 //===----------------------------------------------------------------------===//
2742 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2744 // Note that patterns are much later on in a completely separate section (they
2745 // need ADRPxi to be defined).
2747 //===-------------------------------
2748 // 1. Various operands needed
2749 //===-------------------------------
2751 //===-------------------------------
2752 // 1.1 Unsigned 12-bit immediate operands
2753 //===-------------------------------
2754 // The addressing mode for these instructions consists of an unsigned 12-bit
2755 // immediate which is scaled by the size of the memory access.
2757 // We represent this in the MC layer by two operands:
2758 // 1. A base register.
2759 // 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]"
2760 // would have '1' in this field.
2761 // This means that separate functions are needed for converting representations
2762 // which *are* aware of the intended access size.
2764 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
2765 // know the access size via some means. An isolated operand does not have this
2766 // information unless told from here, which means we need separate tablegen
2767 // Operands for each access size. This multiclass takes care of instantiating
2768 // the correct template functions in the rest of the backend.
2770 //===-------------------------------
2771 // 1.1 Unsigned 12-bit immediate operands
2772 //===-------------------------------
2774 multiclass offsets_uimm12<int MemSize, string prefix> {
2775 def uimm12_asmoperand : AsmOperandClass {
2776 let Name = "OffsetUImm12_" # MemSize;
2777 let PredicateMethod = "isOffsetUImm12<" # MemSize # ">";
2778 let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">";
2779 let DiagnosticType = "LoadStoreUImm12_" # MemSize;
2782 // Pattern is really no more than an ImmLeaf, but predicated on MemSize which
2783 // complicates things beyond TableGen's ken.
2784 def uimm12 : Operand<i64>,
2785 ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> {
2786 let ParserMatchClass
2787 = !cast<AsmOperandClass>(prefix # uimm12_asmoperand);
2789 let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">";
2790 let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">";
2794 defm byte_ : offsets_uimm12<1, "byte_">;
2795 defm hword_ : offsets_uimm12<2, "hword_">;
2796 defm word_ : offsets_uimm12<4, "word_">;
2797 defm dword_ : offsets_uimm12<8, "dword_">;
2798 defm qword_ : offsets_uimm12<16, "qword_">;
2800 //===-------------------------------
2801 // 1.1 Signed 9-bit immediate operands
2802 //===-------------------------------
2804 // The MCInst is expected to store the bit-wise encoding of the value,
2805 // which amounts to lopping off the extended sign bits.
2806 def SDXF_simm9 : SDNodeXForm<imm, [{
2807 return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32);
2810 def simm9_asmoperand : AsmOperandClass {
2812 let PredicateMethod = "isSImm<9>";
2813 let RenderMethod = "addSImmOperands<9>";
2814 let DiagnosticType = "LoadStoreSImm9";
2817 def simm9 : Operand<i64>,
2818 ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }],
2820 let PrintMethod = "printOffsetSImm9Operand";
2821 let ParserMatchClass = simm9_asmoperand;
2825 //===-------------------------------
2826 // 1.3 Register offset extensions
2827 //===-------------------------------
2829 // The assembly-syntax for these addressing-modes is:
2830 // [<Xn|SP>, <R><m> {, <extend> {<amount>}}]
2832 // The essential semantics are:
2833 // + <amount> is a shift: #<log(transfer size)> or #0
2834 // + <R> can be W or X.
2835 // + If <R> is W, <extend> can be UXTW or SXTW
2836 // + If <R> is X, <extend> can be LSL or SXTX
2838 // The trickiest of those constraints is that Rm can be either GPR32 or GPR64,
2839 // which will need separate instructions for LLVM type-consistency. We'll also
2840 // need separate operands, of course.
2841 multiclass regexts<int MemSize, int RmSize, RegisterClass GPR,
2842 string Rm, string prefix> {
2843 def regext_asmoperand : AsmOperandClass {
2844 let Name = "AddrRegExtend_" # MemSize # "_" # Rm;
2845 let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">";
2846 let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">";
2847 let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize;
2850 def regext : Operand<i64> {
2852 = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">";
2854 let DecoderMethod = "DecodeAddrRegExtendOperand";
2855 let ParserMatchClass
2856 = !cast<AsmOperandClass>(prefix # regext_asmoperand);
2860 multiclass regexts_wx<int MemSize, string prefix> {
2861 // Rm is an X-register if LSL or SXTX are specified as the shift.
2862 defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">;
2864 // Rm is a W-register if UXTW or SXTW are specified as the shift.
2865 defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">;
2868 defm byte_ : regexts_wx<1, "byte_">;
2869 defm hword_ : regexts_wx<2, "hword_">;
2870 defm word_ : regexts_wx<4, "word_">;
2871 defm dword_ : regexts_wx<8, "dword_">;
2872 defm qword_ : regexts_wx<16, "qword_">;
2875 //===------------------------------
2876 // 2. The instructions themselves.
2877 //===------------------------------
2879 // We have the following instructions to implement:
2880 // | | B | H | W | X |
2881 // |-----------------+-------+-------+-------+--------|
2882 // | unsigned str | STRB | STRH | STR | STR |
2883 // | unsigned ldr | LDRB | LDRH | LDR | LDR |
2884 // | signed ldr to W | LDRSB | LDRSH | - | - |
2885 // | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) |
2887 // This will instantiate the LDR/STR instructions you'd expect to use for an
2888 // unsigned datatype (first two rows above) or floating-point register, which is
2889 // reasonably uniform across all access sizes.
2892 //===------------------------------
2893 // 2.1 Regular instructions
2894 //===------------------------------
2896 // This class covers the basic unsigned or irrelevantly-signed loads and stores,
2897 // to general-purpose and floating-point registers.
2899 class AddrParams<string prefix> {
2900 Operand uimm12 = !cast<Operand>(prefix # "_uimm12");
2902 Operand regextWm = !cast<Operand>(prefix # "_Wm_regext");
2903 Operand regextXm = !cast<Operand>(prefix # "_Xm_regext");
2906 def byte_addrparams : AddrParams<"byte">;
2907 def hword_addrparams : AddrParams<"hword">;
2908 def word_addrparams : AddrParams<"word">;
2909 def dword_addrparams : AddrParams<"dword">;
2910 def qword_addrparams : AddrParams<"qword">;
2912 multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
2913 bit high_opc, string asmsuffix,
2914 RegisterClass GPR, AddrParams params> {
2915 // Unsigned immediate
2916 def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
2917 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
2918 "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
2922 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
2923 (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2925 def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},
2926 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
2927 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
2931 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
2932 (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2934 // Register offset (four of these: load/store and Wm/Xm).
2935 let mayLoad = 1 in {
2936 def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0,
2938 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
2939 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2942 def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1,
2944 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
2945 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2948 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",
2949 (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
2952 let mayStore = 1 in {
2953 def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0,
2954 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
2955 params.regextWm:$Ext),
2956 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2959 def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1,
2960 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm,
2961 params.regextXm:$Ext),
2962 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2965 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]",
2966 (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn,
2969 // Unaligned immediate
2970 def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
2971 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
2972 "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
2976 def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
2977 (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2979 def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},
2980 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
2981 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
2985 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
2986 (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2989 def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0},
2990 (outs GPR64xsp:$Rn_wb),
2991 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
2992 "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
2994 let Constraints = "$Rn = $Rn_wb";
2997 // Decoder only needed for unpredictability checking (FIXME).
2998 let DecoderMethod = "DecodeSingleIndexedInstruction";
3001 def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1},
3002 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3003 (ins GPR64xsp:$Rn, simm9:$SImm9),
3004 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3007 let Constraints = "$Rn = $Rn_wb";
3008 let DecoderMethod = "DecodeSingleIndexedInstruction";
3012 def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0},
3013 (outs GPR64xsp:$Rn_wb),
3014 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3015 "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3017 let Constraints = "$Rn = $Rn_wb";
3020 // Decoder only needed for unpredictability checking (FIXME).
3021 let DecoderMethod = "DecodeSingleIndexedInstruction";
3024 def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1},
3025 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3026 (ins GPR64xsp:$Rn, simm9:$SImm9),
3027 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3030 let Constraints = "$Rn = $Rn_wb";
3031 let DecoderMethod = "DecodeSingleIndexedInstruction";
3036 // STRB/LDRB: First define the instructions
3038 : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>;
3042 : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>;
3045 // STR/LDR to/from a W register
3047 : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>;
3049 // STR/LDR to/from an X register
3051 : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>;
3053 // STR/LDR to/from a B register
3055 : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>;
3057 // STR/LDR to/from an H register
3059 : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>;
3061 // STR/LDR to/from an S register
3063 : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>;
3064 // STR/LDR to/from a D register
3066 : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>;
3067 // STR/LDR to/from a Q register
3069 : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128,
3072 //===------------------------------
3074 //===------------------------------
3076 // Byte and half-word signed loads can both go into either an X or a W register,
3077 // so it's worth factoring out. Signed word loads don't fit because there is no
3079 multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
3082 def w : A64I_LSunsigimm<size, 0b0, 0b11,
3084 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3085 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3089 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3090 (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3092 def x : A64I_LSunsigimm<size, 0b0, 0b10,
3094 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3095 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3099 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3100 (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3103 let mayLoad = 1 in {
3104 def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0,
3106 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3107 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3110 def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1,
3112 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3113 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3116 def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0,
3118 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3119 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3122 def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1,
3124 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3125 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3128 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3129 (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,
3132 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3133 (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn,
3137 let mayLoad = 1 in {
3139 def w_U : A64I_LSunalimm<size, 0b0, 0b11,
3141 (ins GPR64xsp:$Rn, simm9:$SImm9),
3142 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3145 def x_U : A64I_LSunalimm<size, 0b0, 0b10,
3147 (ins GPR64xsp:$Rn, simm9:$SImm9),
3148 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3153 def w_PostInd : A64I_LSpostind<size, 0b0, 0b11,
3154 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3155 (ins GPR64xsp:$Rn, simm9:$SImm9),
3156 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3158 let Constraints = "$Rn = $Rn_wb";
3159 let DecoderMethod = "DecodeSingleIndexedInstruction";
3162 def x_PostInd : A64I_LSpostind<size, 0b0, 0b10,
3163 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3164 (ins GPR64xsp:$Rn, simm9:$SImm9),
3165 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3167 let Constraints = "$Rn = $Rn_wb";
3168 let DecoderMethod = "DecodeSingleIndexedInstruction";
3172 def w_PreInd : A64I_LSpreind<size, 0b0, 0b11,
3173 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3174 (ins GPR64xsp:$Rn, simm9:$SImm9),
3175 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3177 let Constraints = "$Rn = $Rn_wb";
3178 let DecoderMethod = "DecodeSingleIndexedInstruction";
3181 def x_PreInd : A64I_LSpreind<size, 0b0, 0b10,
3182 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3183 (ins GPR64xsp:$Rn, simm9:$SImm9),
3184 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3186 let Constraints = "$Rn = $Rn_wb";
3187 let DecoderMethod = "DecodeSingleIndexedInstruction";
3189 } // let mayLoad = 1
3193 defm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">;
3195 defm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">;
3197 // LDRSW: load a 32-bit register, sign-extending to 64-bits.
3199 : A64I_LSunsigimm<0b10, 0b0, 0b10,
3201 (ins GPR64xsp:$Rn, word_uimm12:$UImm12),
3202 "ldrsw\t$Rt, [$Rn, $UImm12]",
3206 def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3208 let mayLoad = 1 in {
3209 def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0,
3211 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
3212 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3215 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,
3217 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),
3218 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3221 def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",
3222 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;
3226 : A64I_LSunalimm<0b10, 0b0, 0b10,
3228 (ins GPR64xsp:$Rn, simm9:$SImm9),
3229 "ldursw\t$Rt, [$Rn, $SImm9]",
3233 def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3236 : A64I_LSpostind<0b10, 0b0, 0b10,
3237 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3238 (ins GPR64xsp:$Rn, simm9:$SImm9),
3239 "ldrsw\t$Rt, [$Rn], $SImm9",
3242 let Constraints = "$Rn = $Rn_wb";
3243 let DecoderMethod = "DecodeSingleIndexedInstruction";
3246 def LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10,
3247 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3248 (ins GPR64xsp:$Rn, simm9:$SImm9),
3249 "ldrsw\t$Rt, [$Rn, $SImm9]!",
3252 let Constraints = "$Rn = $Rn_wb";
3253 let DecoderMethod = "DecodeSingleIndexedInstruction";
3256 //===------------------------------
3257 // 2.4 Prefetch operations
3258 //===------------------------------
3260 def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
3261 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
3262 "prfm\t$Rt, [$Rn, $UImm12]",
3266 def : InstAlias<"prfm $Rt, [$Rn]",
3267 (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3269 let mayLoad = 1 in {
3270 def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs),
3271 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3272 GPR32:$Rm, dword_Wm_regext:$Ext),
3273 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3275 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),
3276 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3277 GPR64:$Rm, dword_Xm_regext:$Ext),
3278 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3282 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
3283 (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn,
3287 def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
3288 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3289 "prfum\t$Rt, [$Rn, $SImm9]",
3293 def : InstAlias<"prfum $Rt, [$Rn]",
3294 (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3296 //===----------------------------------------------------------------------===//
3297 // Load-store register (unprivileged) instructions
3298 //===----------------------------------------------------------------------===//
3299 // Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH
3301 // These instructions very much mirror the "unscaled immediate" loads, but since
3302 // there are no floating-point variants we need to split them out into their own
3303 // section to avoid instantiation of "ldtr d0, [sp]" etc.
3305 multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR,
3307 def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,
3308 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3309 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3314 def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]",
3315 (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3317 def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,
3318 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3319 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3324 def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]",
3325 (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3329 // STTRB/LDTRB: First define the instructions
3330 defm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">;
3333 defm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">;
3335 // STTR/LDTR to/from a W register
3336 defm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">;
3338 // STTR/LDTR to/from an X register
3339 defm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">;
3341 // Now a class for the signed instructions that can go to either 32 or 64
3343 multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> {
3344 let mayLoad = 1 in {
3345 def w : A64I_LSunpriv<size, 0b0, 0b11,
3347 (ins GPR64xsp:$Rn, simm9:$SImm9),
3348 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3351 def x : A64I_LSunpriv<size, 0b0, 0b10,
3353 (ins GPR64xsp:$Rn, simm9:$SImm9),
3354 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3358 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3359 (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3361 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3362 (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3367 defm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">;
3369 defm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">;
3371 // And finally LDTRSW which only goes to 64 bits.
3372 def LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10,
3374 (ins GPR64xsp:$Rn, simm9:$SImm9),
3375 "ldtrsw\t$Rt, [$Rn, $SImm9]",
3379 def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3381 //===----------------------------------------------------------------------===//
3382 // Load-store register pair (offset) instructions
3383 //===----------------------------------------------------------------------===//
3387 //===----------------------------------------------------------------------===//
3388 // Load-store register pair (post-indexed) instructions
3389 //===----------------------------------------------------------------------===//
3390 // Contains: STP, LDP, LDPSW
3394 //===----------------------------------------------------------------------===//
3395 // Load-store register pair (pre-indexed) instructions
3396 //===----------------------------------------------------------------------===//
3397 // Contains: STP, LDP, LDPSW
3401 //===----------------------------------------------------------------------===//
3402 // Load-store non-temporal register pair (offset) instructions
3403 //===----------------------------------------------------------------------===//
3404 // Contains: STNP, LDNP
3407 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
3408 // know the access size via some means. An isolated operand does not have this
3409 // information unless told from here, which means we need separate tablegen
3410 // Operands for each access size. This multiclass takes care of instantiating
3411 // the correct template functions in the rest of the backend.
3413 multiclass offsets_simm7<string MemSize, string prefix> {
3414 // The bare signed 7-bit immediate is used in post-indexed instructions, but
3415 // because of the scaling performed a generic "simm7" operand isn't
3416 // appropriate here either.
3417 def simm7_asmoperand : AsmOperandClass {
3418 let Name = "SImm7_Scaled" # MemSize;
3419 let PredicateMethod = "isSImm7Scaled<" # MemSize # ">";
3420 let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">";
3421 let DiagnosticType = "LoadStoreSImm7_" # MemSize;
3424 def simm7 : Operand<i64> {
3425 let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">";
3426 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand");
3430 defm word_ : offsets_simm7<"4", "word_">;
3431 defm dword_ : offsets_simm7<"8", "dword_">;
3432 defm qword_ : offsets_simm7<"16", "qword_">;
3434 multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
3435 Operand simm7, string prefix> {
3436 def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),
3437 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3438 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3440 let DecoderMethod = "DecodeLDSTPairInstruction";
3442 def : InstAlias<"stp $Rt, $Rt2, [$Rn]",
3443 (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt,
3444 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3446 def _LDR : A64I_LSPoffset<opc, v, 0b1,
3447 (outs SomeReg:$Rt, SomeReg:$Rt2),
3448 (ins GPR64xsp:$Rn, simm7:$SImm7),
3449 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3451 let DecoderMethod = "DecodeLDSTPairInstruction";
3453 def : InstAlias<"ldp $Rt, $Rt2, [$Rn]",
3454 (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt,
3455 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3457 def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0,
3458 (outs GPR64xsp:$Rn_wb),
3459 (ins SomeReg:$Rt, SomeReg:$Rt2,
3462 "stp\t$Rt, $Rt2, [$Rn], $SImm7",
3465 let Constraints = "$Rn = $Rn_wb";
3467 // Decoder only needed for unpredictability checking (FIXME).
3468 let DecoderMethod = "DecodeLDSTPairInstruction";
3471 def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1,
3472 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3473 (ins GPR64xsp:$Rn, simm7:$SImm7),
3474 "ldp\t$Rt, $Rt2, [$Rn], $SImm7",
3477 let Constraints = "$Rn = $Rn_wb";
3478 let DecoderMethod = "DecodeLDSTPairInstruction";
3481 def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
3482 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3483 "stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3486 let Constraints = "$Rn = $Rn_wb";
3487 let DecoderMethod = "DecodeLDSTPairInstruction";
3490 def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1,
3491 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3492 (ins GPR64xsp:$Rn, simm7:$SImm7),
3493 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3496 let Constraints = "$Rn = $Rn_wb";
3497 let DecoderMethod = "DecodeLDSTPairInstruction";
3500 def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
3501 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3502 "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3504 let DecoderMethod = "DecodeLDSTPairInstruction";
3506 def : InstAlias<"stnp $Rt, $Rt2, [$Rn]",
3507 (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt,
3508 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3510 def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,
3511 (outs SomeReg:$Rt, SomeReg:$Rt2),
3512 (ins GPR64xsp:$Rn, simm7:$SImm7),
3513 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3515 let DecoderMethod = "DecodeLDSTPairInstruction";
3517 def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]",
3518 (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt,
3519 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3524 defm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">;
3525 defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">;
3526 defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">;
3527 defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">;
3528 defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7,
3532 def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
3533 (outs GPR64:$Rt, GPR64:$Rt2),
3534 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3535 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3537 let DecoderMethod = "DecodeLDSTPairInstruction";
3539 def : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]",
3540 (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>;
3542 def LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1,
3543 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3544 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3545 "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
3548 let Constraints = "$Rn = $Rn_wb";
3549 let DecoderMethod = "DecodeLDSTPairInstruction";
3552 def LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1,
3553 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3554 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3555 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
3558 let Constraints = "$Rn = $Rn_wb";
3559 let DecoderMethod = "DecodeLDSTPairInstruction";
3562 //===----------------------------------------------------------------------===//
3563 // Logical (immediate) instructions
3564 //===----------------------------------------------------------------------===//
3565 // Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV
3567 multiclass logical_imm_operands<string prefix, string note,
3568 int size, ValueType VT> {
3569 def _asmoperand : AsmOperandClass {
3570 let Name = "LogicalImm" # note # size;
3571 let PredicateMethod = "isLogicalImm" # note # "<" # size # ">";
3572 let RenderMethod = "addLogicalImmOperands<" # size # ">";
3573 let DiagnosticType = "LogicalSecondSource";
3577 : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> {
3578 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3579 let PrintMethod = "printLogicalImmOperand<" # size # ">";
3580 let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">";
3584 defm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>;
3585 defm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>;
3587 // The mov versions only differ in assembly parsing, where they
3588 // exclude values representable with either MOVZ or MOVN.
3589 defm logical_imm32_mov
3590 : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>;
3591 defm logical_imm64_mov
3592 : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>;
3595 multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> {
3596 def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd),
3597 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3598 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3600 (opnode GPR32:$Rn, logical_imm32_operand:$Imm))],
3603 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
3604 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3605 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3607 (opnode GPR64:$Rn, logical_imm64_operand:$Imm))],
3611 defm AND : A64I_logimmSizes<0b00, "and", and>;
3612 defm ORR : A64I_logimmSizes<0b01, "orr", or>;
3613 defm EOR : A64I_logimmSizes<0b10, "eor", xor>;
3615 let Defs = [NZCV] in {
3616 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
3617 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3618 "ands\t$Rd, $Rn, $Imm",
3621 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),
3622 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3623 "ands\t$Rd, $Rn, $Imm",
3628 def : InstAlias<"tst $Rn, $Imm",
3629 (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>;
3630 def : InstAlias<"tst $Rn, $Imm",
3631 (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>;
3632 def : InstAlias<"mov $Rd, $Imm",
3633 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>;
3634 def : InstAlias<"mov $Rd, $Imm",
3635 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>;
3637 //===----------------------------------------------------------------------===//
3638 // Logical (shifted register) instructions
3639 //===----------------------------------------------------------------------===//
3640 // Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV
3642 // Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS"
3643 // behaves differently for unsigned comparisons, so we defensively only allow
3644 // signed or n/a as the operand. In practice "unsigned greater than 0" is "not
3645 // equal to 0" and LLVM gives us this.
3646 def signed_cond : PatLeaf<(cond), [{
3647 return !isUnsignedIntSetCC(N->get());
3651 // These instructions share their "shift" operands with add/sub (shifted
3652 // register instructions). They are defined there.
3654 // N.b. the commutable parameter is just !N. It will be first against the wall
3655 // when the revolution comes.
3656 multiclass logical_shifts<string prefix, bit sf, bits<2> opc,
3657 bit N, bit commutable,
3658 string asmop, SDPatternOperator opfrag, string sty,
3659 RegisterClass GPR, list<Register> defs> {
3660 let isCommutable = commutable, Defs = defs in {
3661 def _lsl : A64I_logicalshift<sf, opc, 0b00, N,
3663 (ins GPR:$Rn, GPR:$Rm,
3664 !cast<Operand>("lsl_operand_" # sty):$Imm6),
3665 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3666 [(set GPR:$Rd, (opfrag GPR:$Rn, (shl GPR:$Rm,
3667 !cast<Operand>("lsl_operand_" # sty):$Imm6))
3671 def _lsr : A64I_logicalshift<sf, opc, 0b01, N,
3673 (ins GPR:$Rn, GPR:$Rm,
3674 !cast<Operand>("lsr_operand_" # sty):$Imm6),
3675 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3676 [(set GPR:$Rd, (opfrag GPR:$Rn, (srl GPR:$Rm,
3677 !cast<Operand>("lsr_operand_" # sty):$Imm6))
3681 def _asr : A64I_logicalshift<sf, opc, 0b10, N,
3683 (ins GPR:$Rn, GPR:$Rm,
3684 !cast<Operand>("asr_operand_" # sty):$Imm6),
3685 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3686 [(set GPR:$Rd, (opfrag GPR:$Rn, (sra GPR:$Rm,
3687 !cast<Operand>("asr_operand_" # sty):$Imm6))
3691 def _ror : A64I_logicalshift<sf, opc, 0b11, N,
3693 (ins GPR:$Rn, GPR:$Rm,
3694 !cast<Operand>("ror_operand_" # sty):$Imm6),
3695 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3696 [(set GPR:$Rd, (opfrag GPR:$Rn, (rotr GPR:$Rm,
3697 !cast<Operand>("ror_operand_" # sty):$Imm6))
3703 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
3704 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
3707 def : Pat<(opfrag GPR:$Rn, GPR:$Rm),
3708 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3711 multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable,
3712 string asmop, SDPatternOperator opfrag,
3713 list<Register> defs> {
3714 defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N,
3715 commutable, asmop, opfrag, "i64", GPR64, defs>;
3716 defm www : logical_shifts<prefix # "www", 0b0, opc, N,
3717 commutable, asmop, opfrag, "i32", GPR32, defs>;
3721 defm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>;
3722 defm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>;
3723 defm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>;
3724 defm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands",
3725 PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs),
3726 [{ (void)N; return false; }]>,
3729 defm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic",
3730 PatFrag<(ops node:$lhs, node:$rhs),
3731 (and node:$lhs, (not node:$rhs))>, []>;
3732 defm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn",
3733 PatFrag<(ops node:$lhs, node:$rhs),
3734 (or node:$lhs, (not node:$rhs))>, []>;
3735 defm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon",
3736 PatFrag<(ops node:$lhs, node:$rhs),
3737 (xor node:$lhs, (not node:$rhs))>, []>;
3738 defm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics",
3739 PatFrag<(ops node:$lhs, node:$rhs),
3740 (and node:$lhs, (not node:$rhs)),
3741 [{ (void)N; return false; }]>,
3744 multiclass tst_shifts<string prefix, bit sf, string sty, RegisterClass GPR> {
3745 let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in {
3746 def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0,
3748 (ins GPR:$Rn, GPR:$Rm,
3749 !cast<Operand>("lsl_operand_" # sty):$Imm6),
3750 "tst\t$Rn, $Rm, $Imm6",
3751 [(set NZCV, (A64setcc (and GPR:$Rn, (shl GPR:$Rm,
3752 !cast<Operand>("lsl_operand_" # sty):$Imm6)),
3757 def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0,
3759 (ins GPR:$Rn, GPR:$Rm,
3760 !cast<Operand>("lsr_operand_" # sty):$Imm6),
3761 "tst\t$Rn, $Rm, $Imm6",
3762 [(set NZCV, (A64setcc (and GPR:$Rn, (srl GPR:$Rm,
3763 !cast<Operand>("lsr_operand_" # sty):$Imm6)),
3767 def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0,
3769 (ins GPR:$Rn, GPR:$Rm,
3770 !cast<Operand>("asr_operand_" # sty):$Imm6),
3771 "tst\t$Rn, $Rm, $Imm6",
3772 [(set NZCV, (A64setcc (and GPR:$Rn, (sra GPR:$Rm,
3773 !cast<Operand>("asr_operand_" # sty):$Imm6)),
3777 def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0,
3779 (ins GPR:$Rn, GPR:$Rm,
3780 !cast<Operand>("ror_operand_" # sty):$Imm6),
3781 "tst\t$Rn, $Rm, $Imm6",
3782 [(set NZCV, (A64setcc (and GPR:$Rn, (rotr GPR:$Rm,
3783 !cast<Operand>("ror_operand_" # sty):$Imm6)),
3788 def _noshift : InstAlias<"tst $Rn, $Rm",
3789 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3791 def : Pat<(A64setcc (and GPR:$Rn, GPR:$Rm), 0, signed_cond),
3792 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3795 defm TSTxx : tst_shifts<"TSTxx", 0b1, "i64", GPR64>;
3796 defm TSTww : tst_shifts<"TSTww", 0b0, "i32", GPR32>;
3799 multiclass mvn_shifts<string prefix, bit sf, string sty, RegisterClass GPR> {
3800 let isCommutable = 0, Rn = 0b11111 in {
3801 def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1,
3804 !cast<Operand>("lsl_operand_" # sty):$Imm6),
3805 "mvn\t$Rd, $Rm, $Imm6",
3806 [(set GPR:$Rd, (not (shl GPR:$Rm,
3807 !cast<Operand>("lsl_operand_" # sty):$Imm6)))],
3811 def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1,
3814 !cast<Operand>("lsr_operand_" # sty):$Imm6),
3815 "mvn\t$Rd, $Rm, $Imm6",
3816 [(set GPR:$Rd, (not (srl GPR:$Rm,
3817 !cast<Operand>("lsr_operand_" # sty):$Imm6)))],
3820 def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1,
3823 !cast<Operand>("asr_operand_" # sty):$Imm6),
3824 "mvn\t$Rd, $Rm, $Imm6",
3825 [(set GPR:$Rd, (not (sra GPR:$Rm,
3826 !cast<Operand>("asr_operand_" # sty):$Imm6)))],
3829 def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1,
3832 !cast<Operand>("ror_operand_" # sty):$Imm6),
3833 "mvn\t$Rd, $Rm, $Imm6",
3834 [(set GPR:$Rd, (not (rotr GPR:$Rm,
3835 !cast<Operand>("lsl_operand_" # sty):$Imm6)))],
3839 def _noshift : InstAlias<"mvn $Rn, $Rm",
3840 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3842 def : Pat<(not GPR:$Rm),
3843 (!cast<Instruction>(prefix # "_lsl") GPR:$Rm, 0)>;
3846 defm MVNxx : mvn_shifts<"MVNxx", 0b1, "i64", GPR64>;
3847 defm MVNww : mvn_shifts<"MVNww", 0b0, "i32", GPR32>;
3849 def MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
3850 def MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
3852 //===----------------------------------------------------------------------===//
3853 // Move wide (immediate) instructions
3854 //===----------------------------------------------------------------------===//
3855 // Contains: MOVN, MOVZ, MOVK + MOV aliases
3857 // A wide variety of different relocations are needed for variants of these
3858 // instructions, so it turns out that we need a different operand for all of
3860 multiclass movw_operands<string prefix, string instname, int width> {
3861 def _imm_asmoperand : AsmOperandClass {
3862 let Name = instname # width # "Shifted" # shift;
3863 let PredicateMethod = "is" # instname # width # "Imm";
3864 let RenderMethod = "addMoveWideImmOperands";
3865 let ParserMethod = "ParseImmWithLSLOperand";
3866 let DiagnosticType = "MOVWUImm16";
3869 def _imm : Operand<i32> {
3870 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand");
3871 let PrintMethod = "printMoveWideImmOperand";
3872 let EncoderMethod = "getMoveWideImmOpValue";
3873 let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">";
3875 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
3879 defm movn32 : movw_operands<"movn32", "MOVN", 32>;
3880 defm movn64 : movw_operands<"movn64", "MOVN", 64>;
3881 defm movz32 : movw_operands<"movz32", "MOVZ", 32>;
3882 defm movz64 : movw_operands<"movz64", "MOVZ", 64>;
3883 defm movk32 : movw_operands<"movk32", "MOVK", 32>;
3884 defm movk64 : movw_operands<"movk64", "MOVK", 64>;
3886 multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit,
3889 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
3890 !strconcat(asmop, "\t$Rd, $FullImm"),
3893 let UImm16 = FullImm{15-0};
3894 let Shift = FullImm{17-16};
3897 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
3898 !strconcat(asmop, "\t$Rd, $FullImm"),
3901 let UImm16 = FullImm{15-0};
3902 let Shift = FullImm{17-16};
3906 let isMoveImm = 1, isReMaterializable = 1,
3907 isAsCheapAsAMove = 1, hasSideEffects = 0 in {
3908 defm MOVN : A64I_movwSizes<0b00, "movn",
3909 (ins movn32_imm:$FullImm),
3910 (ins movn64_imm:$FullImm)>;
3912 // Some relocations are able to convert between a MOVZ and a MOVN. If these
3913 // are applied the instruction must be emitted with the corresponding bits as
3914 // 0, which means a MOVZ needs to override that bit from the default.
3915 let PostEncoderMethod = "fixMOVZ" in
3916 defm MOVZ : A64I_movwSizes<0b10, "movz",
3917 (ins movz32_imm:$FullImm),
3918 (ins movz64_imm:$FullImm)>;
3921 let Constraints = "$src = $Rd" in
3922 defm MOVK : A64I_movwSizes<0b11, "movk",
3923 (ins GPR32:$src, movk32_imm:$FullImm),
3924 (ins GPR64:$src, movk64_imm:$FullImm)>;
3927 // And now the "MOV" aliases. These also need their own operands because what
3928 // they accept is completely different to what the base instructions accept.
3929 multiclass movalias_operand<string prefix, string basename,
3930 string immpredicate, int width> {
3931 def _asmoperand : AsmOperandClass {
3932 let Name = basename # width # "MovAlias";
3934 = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">";
3936 = "addMoveWideMovAliasOperands<" # width # ", "
3937 # "A64Imms::" # immpredicate # ">";
3940 def _movimm : Operand<i32> {
3941 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3943 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
3947 defm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>;
3948 defm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>;
3949 defm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>;
3950 defm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>;
3952 // FIXME: these are officially canonical aliases, but TableGen is too limited to
3953 // print them at the moment. I believe in this case an "AliasPredicate" method
3954 // will need to be implemented. to allow it, as well as the more generally
3955 // useful handling of non-register, non-constant operands.
3956 class movalias<Instruction INST, RegisterClass GPR, Operand operand>
3957 : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>;
3959 def : movalias<MOVZwii, GPR32, movz32_movimm>;
3960 def : movalias<MOVZxii, GPR64, movz64_movimm>;
3961 def : movalias<MOVNwii, GPR32, movn32_movimm>;
3962 def : movalias<MOVNxii, GPR64, movn64_movimm>;
3964 //===----------------------------------------------------------------------===//
3965 // PC-relative addressing instructions
3966 //===----------------------------------------------------------------------===//
3967 // Contains: ADR, ADRP
3969 def adr_label : Operand<i64> {
3970 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>";
3972 // This label is a 21-bit offset from PC, unscaled
3973 let PrintMethod = "printLabelOperand<21, 1>";
3974 let ParserMatchClass = label_asmoperand<21, 1>;
3975 let OperandType = "OPERAND_PCREL";
3978 def adrp_label_asmoperand : AsmOperandClass {
3979 let Name = "AdrpLabel";
3980 let RenderMethod = "addLabelOperands<21, 4096>";
3981 let DiagnosticType = "Label";
3984 def adrp_label : Operand<i64> {
3985 let EncoderMethod = "getAdrpLabelOpValue";
3987 // This label is a 21-bit offset from PC, scaled by the page-size: 4096.
3988 let PrintMethod = "printLabelOperand<21, 4096>";
3989 let ParserMatchClass = adrp_label_asmoperand;
3990 let OperandType = "OPERAND_PCREL";
3993 let hasSideEffects = 0 in {
3994 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
3995 "adr\t$Rd, $Label", [], NoItinerary>;
3997 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),
3998 "adrp\t$Rd, $Label", [], NoItinerary>;
4001 //===----------------------------------------------------------------------===//
4002 // System instructions
4003 //===----------------------------------------------------------------------===//
4004 // Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS
4005 // + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL
4007 // Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values.
4008 def uimm3_asmoperand : AsmOperandClass {
4010 let PredicateMethod = "isUImm<3>";
4011 let RenderMethod = "addImmOperands";
4012 let DiagnosticType = "UImm3";
4015 def uimm3 : Operand<i32> {
4016 let ParserMatchClass = uimm3_asmoperand;
4019 // The HINT alias can accept a simple unsigned 7-bit immediate.
4020 def uimm7_asmoperand : AsmOperandClass {
4022 let PredicateMethod = "isUImm<7>";
4023 let RenderMethod = "addImmOperands";
4024 let DiagnosticType = "UImm7";
4027 def uimm7 : Operand<i32> {
4028 let ParserMatchClass = uimm7_asmoperand;
4031 // Multiclass namedimm is defined with the prefetch operands. Most of these fit
4032 // into the NamedImmMapper scheme well: they either accept a named operand or
4033 // any immediate under a particular value (which may be 0, implying no immediate
4035 defm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">;
4036 defm isb : namedimm<"isb", "A64ISB::ISBMapper">;
4037 defm ic : namedimm<"ic", "A64IC::ICMapper">;
4038 defm dc : namedimm<"dc", "A64DC::DCMapper">;
4039 defm at : namedimm<"at", "A64AT::ATMapper">;
4040 defm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">;
4042 // However, MRS and MSR are more complicated for a few reasons:
4043 // * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an
4044 // implementation-defined effect
4045 // * Most registers are shared, but some are read-only or write-only.
4046 // * There is a variant of MSR which accepts the same register name (SPSel),
4047 // but which would have a different encoding.
4049 // In principle these could be resolved in with more complicated subclasses of
4050 // NamedImmMapper, however that imposes an overhead on other "named
4051 // immediates". Both in concrete terms with virtual tables and in unnecessary
4054 // The solution adopted here is to take the MRS/MSR Mappers out of the usual
4055 // hierarchy (they're not derived from NamedImmMapper) and to add logic for
4056 // their special situation.
4057 def mrs_asmoperand : AsmOperandClass {
4059 let ParserMethod = "ParseSysRegOperand";
4060 let DiagnosticType = "MRS";
4063 def mrs_op : Operand<i32> {
4064 let ParserMatchClass = mrs_asmoperand;
4065 let PrintMethod = "printMRSOperand";
4066 let DecoderMethod = "DecodeMRSOperand";
4069 def msr_asmoperand : AsmOperandClass {
4070 let Name = "MSRWithReg";
4072 // Note that SPSel is valid for both this and the pstate operands, but with
4073 // different immediate encodings. This is why these operands provide a string
4074 // AArch64Operand rather than an immediate. The overlap is small enough that
4075 // it could be resolved with hackery now, but who can say in future?
4076 let ParserMethod = "ParseSysRegOperand";
4077 let DiagnosticType = "MSR";
4080 def msr_op : Operand<i32> {
4081 let ParserMatchClass = msr_asmoperand;
4082 let PrintMethod = "printMSROperand";
4083 let DecoderMethod = "DecodeMSROperand";
4086 def pstate_asmoperand : AsmOperandClass {
4087 let Name = "MSRPState";
4088 // See comment above about parser.
4089 let ParserMethod = "ParseSysRegOperand";
4090 let DiagnosticType = "MSR";
4093 def pstate_op : Operand<i32> {
4094 let ParserMatchClass = pstate_asmoperand;
4095 let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>";
4096 let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>";
4099 // When <CRn> is specified, an assembler should accept something like "C4", not
4100 // the usual "#4" immediate.
4101 def CRx_asmoperand : AsmOperandClass {
4103 let PredicateMethod = "isUImm<4>";
4104 let RenderMethod = "addImmOperands";
4105 let ParserMethod = "ParseCRxOperand";
4106 // Diagnostics are handled in all cases by ParseCRxOperand.
4109 def CRx : Operand<i32> {
4110 let ParserMatchClass = CRx_asmoperand;
4111 let PrintMethod = "printCRxOperand";
4115 // Finally, we can start defining the instructions.
4117 // HINT is straightforward, with a few aliases.
4118 def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7",
4121 let CRm = UImm7{6-3};
4122 let Op2 = UImm7{2-0};
4130 def : InstAlias<"nop", (HINTi 0)>;
4131 def : InstAlias<"yield", (HINTi 1)>;
4132 def : InstAlias<"wfe", (HINTi 2)>;
4133 def : InstAlias<"wfi", (HINTi 3)>;
4134 def : InstAlias<"sev", (HINTi 4)>;
4135 def : InstAlias<"sevl", (HINTi 5)>;
4137 // Quite a few instructions then follow a similar pattern of fixing common
4138 // fields in the bitpattern, we'll define a helper-class for them.
4139 class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2,
4140 Operand operand, string asmop>
4141 : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"),
4151 def CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">;
4152 def DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">;
4153 def DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">;
4154 def ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">;
4156 def : InstAlias<"clrex", (CLREXi 0b1111)>;
4157 def : InstAlias<"isb", (ISBi 0b1111)>;
4159 // (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP
4160 // configurations at least.
4161 def : Pat<(atomic_fence imm, imm), (DMBi 0xb)>;
4163 // Any SYS bitpattern can be represented with a complex and opaque "SYS"
4165 def SYSiccix : A64I_system<0b0, (outs),
4166 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm,
4167 uimm3:$Op2, GPR64:$Rt),
4168 "sys\t$Op1, $CRn, $CRm, $Op2, $Rt",
4173 // You can skip the Xt argument whether it makes sense or not for the generic
4175 def : InstAlias<"sys $Op1, $CRn, $CRm, $Op2",
4176 (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>;
4179 // But many have aliases, which obviously don't fit into
4180 class SYSalias<dag ins, string asmstring>
4181 : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> {
4182 let isAsmParserOnly = 1;
4186 let Op1 = SysOp{13-11};
4187 let CRn = SysOp{10-7};
4188 let CRm = SysOp{6-3};
4189 let Op2 = SysOp{2-0};
4192 def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">;
4194 def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> {
4198 def DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">;
4199 def ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">;
4201 def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">;
4203 def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> {
4208 def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt),
4209 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2),
4210 "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2",
4215 // The instructions themselves are rather simple for MSR and MRS.
4216 def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt),
4217 "msr\t$SysReg, $Rt", [], NoItinerary> {
4219 let Op0 = SysReg{15-14};
4220 let Op1 = SysReg{13-11};
4221 let CRn = SysReg{10-7};
4222 let CRm = SysReg{6-3};
4223 let Op2 = SysReg{2-0};
4226 def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg),
4227 "mrs\t$Rt, $SysReg", [], NoItinerary> {
4229 let Op0 = SysReg{15-14};
4230 let Op1 = SysReg{13-11};
4231 let CRn = SysReg{10-7};
4232 let CRm = SysReg{6-3};
4233 let Op2 = SysReg{2-0};
4236 def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm),
4237 "msr\t$PState, $CRm", [], NoItinerary> {
4241 let Op1 = PState{5-3};
4243 let Op2 = PState{2-0};
4247 //===----------------------------------------------------------------------===//
4248 // Test & branch (immediate) instructions
4249 //===----------------------------------------------------------------------===//
4250 // Contains: TBZ, TBNZ
4252 // The bit to test is a simple unsigned 6-bit immediate in the X-register
4254 def uimm6 : Operand<i64> {
4255 let ParserMatchClass = uimm6_asmoperand;
4258 def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>;
4260 def tbimm_target : Operand<OtherVT> {
4261 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>";
4263 // This label is a 14-bit offset from PC, scaled by the instruction-width: 4.
4264 let PrintMethod = "printLabelOperand<14, 4>";
4265 let ParserMatchClass = label_wid14_scal4_asmoperand;
4267 let OperandType = "OPERAND_PCREL";
4270 def A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>;
4271 def A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>;
4273 // These instructions correspond to patterns involving "and" with a power of
4274 // two, which we need to be able to select.
4275 def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">;
4276 def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">;
4278 let isBranch = 1, isTerminator = 1 in {
4279 def TBZxii : A64I_TBimm<0b0, (outs),
4280 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4281 "tbz\t$Rt, $Imm, $Label",
4282 [(A64br_cc (A64cmp (and GPR64:$Rt, tstb64_pat:$Imm), 0),
4286 def TBNZxii : A64I_TBimm<0b1, (outs),
4287 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4288 "tbnz\t$Rt, $Imm, $Label",
4289 [(A64br_cc (A64cmp (and GPR64:$Rt, tstb64_pat:$Imm), 0),
4294 // Note, these instructions overlap with the above 64-bit patterns. This is
4295 // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both
4296 // do the same thing and are both permitted assembly. They also both have
4297 // sensible DAG patterns.
4298 def TBZwii : A64I_TBimm<0b0, (outs),
4299 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4300 "tbz\t$Rt, $Imm, $Label",
4301 [(A64br_cc (A64cmp (and GPR32:$Rt, tstb32_pat:$Imm), 0),
4307 def TBNZwii : A64I_TBimm<0b1, (outs),
4308 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4309 "tbnz\t$Rt, $Imm, $Label",
4310 [(A64br_cc (A64cmp (and GPR32:$Rt, tstb32_pat:$Imm), 0),
4317 //===----------------------------------------------------------------------===//
4318 // Unconditional branch (immediate) instructions
4319 //===----------------------------------------------------------------------===//
4322 def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>;
4324 def bimm_target : Operand<OtherVT> {
4325 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>";
4327 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4328 let PrintMethod = "printLabelOperand<26, 4>";
4329 let ParserMatchClass = label_wid26_scal4_asmoperand;
4331 let OperandType = "OPERAND_PCREL";
4334 def blimm_target : Operand<i64> {
4335 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>";
4337 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4338 let PrintMethod = "printLabelOperand<26, 4>";
4339 let ParserMatchClass = label_wid26_scal4_asmoperand;
4341 let OperandType = "OPERAND_PCREL";
4344 class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type>
4345 : A64I_Bimm<op, (outs), (ins lbl_type:$Label),
4346 !strconcat(asmop, "\t$Label"), patterns,
4349 let isBranch = 1 in {
4350 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
4351 let isTerminator = 1;
4355 def BLimm : A64I_BimmImpl<0b1, "bl",
4356 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4362 def : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>;
4364 //===----------------------------------------------------------------------===//
4365 // Unconditional branch (register) instructions
4366 //===----------------------------------------------------------------------===//
4367 // Contains: BR, BLR, RET, ERET, DRP.
4369 // Most of the notional opcode fields in the A64I_Breg format are fixed in A64
4371 class A64I_BregImpl<bits<4> opc,
4372 dag outs, dag ins, string asmstr, list<dag> patterns,
4373 InstrItinClass itin = NoItinerary>
4374 : A64I_Breg<opc, 0b11111, 0b000000, 0b00000,
4375 outs, ins, asmstr, patterns, itin> {
4377 let isIndirectBranch = 1;
4380 // Note that these are not marked isCall or isReturn because as far as LLVM is
4381 // concerned they're not. "ret" is just another jump unless it has been selected
4382 // by LLVM as the function's return.
4384 let isBranch = 1 in {
4385 def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn),
4386 "br\t$Rn", [(brind GPR64:$Rn)]> {
4388 let isTerminator = 1;
4391 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4392 "blr\t$Rn", [(AArch64Call GPR64:$Rn)]> {
4398 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
4401 let isTerminator = 1;
4405 // Create a separate pseudo-instruction for codegen to use so that we don't
4406 // flag x30 as used in every function. It'll be restored before the RET by the
4407 // epilogue if it's legitimately used.
4408 def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> {
4409 let isTerminator = 1;
4414 def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> {
4417 let isTerminator = 1;
4421 def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> {
4427 def RETAlias : InstAlias<"ret", (RETx X30)>;
4430 //===----------------------------------------------------------------------===//
4431 // Address generation patterns
4432 //===----------------------------------------------------------------------===//
4434 // Primary method of address generation for the small/absolute memory model is
4435 // an ADRP/ADR pair:
4436 // ADRP x0, some_variable
4437 // ADD x0, x0, #:lo12:some_variable
4439 // The load/store elision of the ADD is accomplished when selecting
4440 // addressing-modes. This just mops up the cases where that doesn't work and we
4441 // really need an address in some register.
4443 // This wrapper applies a LO12 modifier to the address. Otherwise we could just
4444 // use the same address.
4446 class ADRP_ADD<SDNode Wrapper, SDNode addrop>
4447 : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)),
4448 (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>;
4450 def : ADRP_ADD<A64WrapperSmall, tblockaddress>;
4451 def : ADRP_ADD<A64WrapperSmall, texternalsym>;
4452 def : ADRP_ADD<A64WrapperSmall, tglobaladdr>;
4453 def : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>;
4454 def : ADRP_ADD<A64WrapperSmall, tjumptable>;
4456 //===----------------------------------------------------------------------===//
4457 // GOT access patterns
4458 //===----------------------------------------------------------------------===//
4462 class GOTLoadSmall<SDNode addrfrag>
4463 : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)),
4464 (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>;
4466 def : GOTLoadSmall<texternalsym>;
4467 def : GOTLoadSmall<tglobaladdr>;
4468 def : GOTLoadSmall<tglobaltlsaddr>;
4470 //===----------------------------------------------------------------------===//
4471 // Tail call handling
4472 //===----------------------------------------------------------------------===//
4474 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in {
4476 : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff),
4477 [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>;
4480 : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff),
4481 [(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff))]>;
4484 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
4486 def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [],
4487 (Bimm bimm_target:$Label)>;
4489 def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [],
4494 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
4495 (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>;
4497 //===----------------------------------------------------------------------===//
4498 // Thread local storage
4499 //===----------------------------------------------------------------------===//
4501 // This is a pseudo-instruction representing the ".tlsdesccall" directive in
4502 // assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the
4503 // current location. It should always be immediately followed by a BLR
4504 // instruction, and is intended solely for relaxation by the linker.
4506 def : Pat<(A64threadpointer), (MRSxi 0xde82)>;
4508 def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> {
4509 let hasSideEffects = 1;
4512 def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var),
4513 [(A64tlsdesc_blr GPR64:$Rn, tglobaltlsaddr:$Var)]> {
4518 def : Pat<(A64tlsdesc_blr GPR64:$Rn, texternalsym:$Var),
4519 (TLSDESC_BLRx GPR64:$Rn, texternalsym:$Var)>;
4521 //===----------------------------------------------------------------------===//
4522 // Bitfield patterns
4523 //===----------------------------------------------------------------------===//
4525 def bfi32_lsb_to_immr : SDNodeXForm<imm, [{
4526 return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64);
4529 def bfi64_lsb_to_immr : SDNodeXForm<imm, [{
4530 return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64);
4533 def bfi_width_to_imms : SDNodeXForm<imm, [{
4534 return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64);
4538 // The simpler patterns deal with cases where no AND mask is actually needed
4539 // (either all bits are used or the low 32 bits are used).
4540 let AddedComplexity = 10 in {
4542 def : Pat<(A64Bfi GPR64:$src, GPR64:$Rn, imm:$ImmR, imm:$ImmS),
4543 (BFIxxii GPR64:$src, GPR64:$Rn,
4544 (bfi64_lsb_to_immr (i64 imm:$ImmR)),
4545 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4547 def : Pat<(A64Bfi GPR32:$src, GPR32:$Rn, imm:$ImmR, imm:$ImmS),
4548 (BFIwwii GPR32:$src, GPR32:$Rn,
4549 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4550 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4553 def : Pat<(and (A64Bfi GPR64:$src, GPR64:$Rn, imm:$ImmR, imm:$ImmS),
4555 (SUBREG_TO_REG (i64 0),
4556 (BFIwwii (EXTRACT_SUBREG GPR64:$src, sub_32),
4557 (EXTRACT_SUBREG GPR64:$Rn, sub_32),
4558 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4559 (bfi_width_to_imms (i64 imm:$ImmS))),
4564 //===----------------------------------------------------------------------===//
4565 // Miscellaneous patterns
4566 //===----------------------------------------------------------------------===//
4568 // Truncation from 64 to 32-bits just involves renaming your register.
4569 def : Pat<(i32 (trunc (i64 GPR64:$val))), (EXTRACT_SUBREG GPR64:$val, sub_32)>;
4571 // Similarly, extension where we don't care about the high bits is
4573 def : Pat<(i64 (anyext (i32 GPR32:$val))),
4574 (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$val, sub_32)>;
4576 // SELECT instructions providing f128 types need to be handled by a
4577 // pseudo-instruction since the eventual code will need to introduce basic
4578 // blocks and control flow.
4579 def F128CSEL : PseudoInst<(outs FPR128:$Rd),
4580 (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond),
4581 [(set FPR128:$Rd, (simple_select (f128 FPR128:$Rn),
4584 let usesCustomInserter = 1;
4587 //===----------------------------------------------------------------------===//
4588 // Load/store patterns
4589 //===----------------------------------------------------------------------===//
4591 // There are lots of patterns here, because we need to allow at least three
4592 // parameters to vary independently.
4593 // 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ...
4594 // 2. LLVM source: zextloadi8, anyextloadi8, ...
4595 // 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ...
4597 // The biggest problem turns out to be the address-generation variable. At the
4598 // point of instantiation we need to produce two DAGs, one for the pattern and
4599 // one for the instruction. Doing this at the lowest level of classes doesn't
4602 // Consider the simple uimm12 addressing mode, and the desire to match both (add
4603 // GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the
4604 // instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or
4605 // "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this
4606 // operation, and PatFrags are for selection not output.
4608 // As a result, the address-generation patterns are the final
4609 // instantiations. However, we do still need to vary the operand for the address
4610 // further down (At the point we're deciding A64WrapperSmall, we don't know
4611 // the memory width of the operation).
4613 //===------------------------------
4614 // 1. Basic infrastructural defs
4615 //===------------------------------
4617 // First, some simple classes for !foreach and !subst to use:
4628 // You can't use !subst on an actual immediate, but you *can* use it on an
4629 // operand record that happens to match a single immediate. So we do.
4630 def imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>;
4631 def imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>;
4632 def imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>;
4633 def imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>;
4634 def imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>;
4636 // If the low bits of a pointer are known to be 0 then an "or" is just as good
4637 // as addition for computing an offset. This fragment forwards that check for
4639 def add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),
4641 return CurDAG->isBaseWithConstantOffset(SDValue(N, 0));
4644 // Load/store (unsigned immediate) operations with relocations against global
4645 // symbols (for lo12) are only valid if those symbols have correct alignment
4646 // (since the immediate offset is divided by the access scale, it can't have a
4649 // The guaranteed alignment is provided as part of the WrapperSmall
4650 // operation, and checked against one of these.
4651 def any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>;
4652 def min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>;
4653 def min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>;
4654 def min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>;
4655 def min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>;
4657 // "Normal" load/store instructions can be used on atomic operations, provided
4658 // the ordering parameter is at most "monotonic". Anything above that needs
4659 // special handling with acquire/release instructions.
4660 class simple_load<PatFrag base>
4661 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4662 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4665 def atomic_load_simple_i8 : simple_load<atomic_load_8>;
4666 def atomic_load_simple_i16 : simple_load<atomic_load_16>;
4667 def atomic_load_simple_i32 : simple_load<atomic_load_32>;
4668 def atomic_load_simple_i64 : simple_load<atomic_load_64>;
4670 class simple_store<PatFrag base>
4671 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4672 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4675 def atomic_store_simple_i8 : simple_store<atomic_store_8>;
4676 def atomic_store_simple_i16 : simple_store<atomic_store_16>;
4677 def atomic_store_simple_i32 : simple_store<atomic_store_32>;
4678 def atomic_store_simple_i64 : simple_store<atomic_store_64>;
4680 //===------------------------------
4681 // 2. UImm12 and SImm9
4682 //===------------------------------
4684 // These instructions have two operands providing the address so they can be
4685 // treated similarly for most purposes.
4687 //===------------------------------
4688 // 2.1 Base patterns covering extend/truncate semantics
4689 //===------------------------------
4691 // Atomic patterns can be shared between integer operations of all sizes, a
4692 // quick multiclass here allows reuse.
4693 multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4694 dag Offset, dag address, RegisterClass TPR,
4696 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4697 (LOAD Base, Offset)>;
4699 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, TPR:$Rt),
4700 (STORE TPR:$Rt, Base, Offset)>;
4703 // Instructions accessing a memory chunk smaller than a register (or, in a
4704 // pinch, the same size) have a characteristic set of patterns they want to
4705 // match: extending loads and truncating stores. This class deals with the
4706 // sign-neutral version of those patterns.
4708 // It will be instantiated across multiple addressing-modes.
4709 multiclass ls_small_pats<Instruction LOAD, Instruction STORE,
4710 dag Base, dag Offset,
4711 dag address, ValueType sty>
4712 : ls_atomic_pats<LOAD, STORE, Base, Offset, address, GPR32, sty> {
4713 def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>;
4715 def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>;
4717 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4718 // register was actually set.
4719 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4720 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4722 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
4723 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4725 def : Pat<(!cast<SDNode>(truncstore # sty) GPR32:$Rt, address),
4726 (STORE GPR32:$Rt, Base, Offset)>;
4728 // For truncating store from 64-bits, we have to manually tell LLVM to
4729 // ignore the high bits of the x register.
4730 def : Pat<(!cast<SDNode>(truncstore # sty) GPR64:$Rt, address),
4731 (STORE (EXTRACT_SUBREG GPR64:$Rt, sub_32), Base, Offset)>;
4734 // Next come patterns for sign-extending loads.
4735 multiclass load_signed_pats<string T, string U, dag Base, dag Offset,
4736 dag address, ValueType sty> {
4737 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
4738 (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>;
4740 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
4741 (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>;
4745 // and finally "natural-width" loads and stores come next.
4746 multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4747 dag Offset, dag address, RegisterClass TPR,
4749 def : Pat<(sty (load address)), (LOAD Base, Offset)>;
4750 def : Pat<(store (sty TPR:$Rt), address), (STORE TPR:$Rt, Base, Offset)>;
4753 // Integer operations also get atomic instructions to select for.
4754 multiclass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4755 dag Offset, dag address, RegisterClass TPR,
4757 : ls_neutral_pats<LOAD, STORE, Base, Offset, address, TPR, sty>,
4758 ls_atomic_pats<LOAD, STORE, Base, Offset, address, TPR, sty>;
4760 //===------------------------------
4761 // 2.2. Addressing-mode instantiations
4762 //===------------------------------
4764 multiclass uimm12_pats<dag address, dag Base, dag Offset> {
4765 defm : ls_small_pats<LS8_LDR, LS8_STR, Base,
4766 !foreach(decls.pattern, Offset,
4767 !subst(OFFSET, byte_uimm12, decls.pattern)),
4768 !foreach(decls.pattern, address,
4769 !subst(OFFSET, byte_uimm12,
4770 !subst(ALIGN, any_align, decls.pattern))),
4772 defm : ls_small_pats<LS16_LDR, LS16_STR, Base,
4773 !foreach(decls.pattern, Offset,
4774 !subst(OFFSET, hword_uimm12, decls.pattern)),
4775 !foreach(decls.pattern, address,
4776 !subst(OFFSET, hword_uimm12,
4777 !subst(ALIGN, min_align2, decls.pattern))),
4779 defm : ls_small_pats<LS32_LDR, LS32_STR, Base,
4780 !foreach(decls.pattern, Offset,
4781 !subst(OFFSET, word_uimm12, decls.pattern)),
4782 !foreach(decls.pattern, address,
4783 !subst(OFFSET, word_uimm12,
4784 !subst(ALIGN, min_align4, decls.pattern))),
4787 defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base,
4788 !foreach(decls.pattern, Offset,
4789 !subst(OFFSET, word_uimm12, decls.pattern)),
4790 !foreach(decls.pattern, address,
4791 !subst(OFFSET, word_uimm12,
4792 !subst(ALIGN, min_align4, decls.pattern))),
4795 defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base,
4796 !foreach(decls.pattern, Offset,
4797 !subst(OFFSET, dword_uimm12, decls.pattern)),
4798 !foreach(decls.pattern, address,
4799 !subst(OFFSET, dword_uimm12,
4800 !subst(ALIGN, min_align8, decls.pattern))),
4803 defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base,
4804 !foreach(decls.pattern, Offset,
4805 !subst(OFFSET, hword_uimm12, decls.pattern)),
4806 !foreach(decls.pattern, address,
4807 !subst(OFFSET, hword_uimm12,
4808 !subst(ALIGN, min_align2, decls.pattern))),
4811 defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base,
4812 !foreach(decls.pattern, Offset,
4813 !subst(OFFSET, word_uimm12, decls.pattern)),
4814 !foreach(decls.pattern, address,
4815 !subst(OFFSET, word_uimm12,
4816 !subst(ALIGN, min_align4, decls.pattern))),
4819 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
4820 !foreach(decls.pattern, Offset,
4821 !subst(OFFSET, dword_uimm12, decls.pattern)),
4822 !foreach(decls.pattern, address,
4823 !subst(OFFSET, dword_uimm12,
4824 !subst(ALIGN, min_align8, decls.pattern))),
4827 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
4828 !foreach(decls.pattern, Offset,
4829 !subst(OFFSET, qword_uimm12, decls.pattern)),
4830 !foreach(decls.pattern, address,
4831 !subst(OFFSET, qword_uimm12,
4832 !subst(ALIGN, min_align16, decls.pattern))),
4835 defm : load_signed_pats<"B", "", Base,
4836 !foreach(decls.pattern, Offset,
4837 !subst(OFFSET, byte_uimm12, decls.pattern)),
4838 !foreach(decls.pattern, address,
4839 !subst(OFFSET, byte_uimm12,
4840 !subst(ALIGN, any_align, decls.pattern))),
4843 defm : load_signed_pats<"H", "", Base,
4844 !foreach(decls.pattern, Offset,
4845 !subst(OFFSET, hword_uimm12, decls.pattern)),
4846 !foreach(decls.pattern, address,
4847 !subst(OFFSET, hword_uimm12,
4848 !subst(ALIGN, min_align2, decls.pattern))),
4851 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
4852 !subst(OFFSET, word_uimm12,
4853 !subst(ALIGN, min_align4, decls.pattern)))),
4854 (LDRSWx Base, !foreach(decls.pattern, Offset,
4855 !subst(OFFSET, word_uimm12, decls.pattern)))>;
4858 // Straightforward patterns of last resort: a pointer with or without an
4859 // appropriate offset.
4860 defm : uimm12_pats<(i64 GPR64xsp:$Rn), (i64 GPR64xsp:$Rn), (i64 0)>;
4861 defm : uimm12_pats<(add GPR64xsp:$Rn, OFFSET:$UImm12),
4862 (i64 GPR64xsp:$Rn), (i64 OFFSET:$UImm12)>;
4864 // The offset could be hidden behind an "or", of course:
4865 defm : uimm12_pats<(add_like_or GPR64xsp:$Rn, OFFSET:$UImm12),
4866 (i64 GPR64xsp:$Rn), (i64 OFFSET:$UImm12)>;
4868 // Global addresses under the small-absolute model should use these
4869 // instructions. There are ELF relocations specifically for it.
4870 defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN),
4871 (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>;
4873 defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12,
4875 (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>;
4877 // External symbols that make it this far should also get standard relocations.
4878 defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12,
4880 (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>;
4882 defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
4883 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
4885 // We also want to use uimm12 instructions for local variables at the moment.
4886 def tframeindex_XFORM : SDNodeXForm<frameindex, [{
4887 int FI = cast<FrameIndexSDNode>(N)->getIndex();
4888 return CurDAG->getTargetFrameIndex(FI, MVT::i64);
4891 defm : uimm12_pats<(i64 frameindex:$Rn),
4892 (tframeindex_XFORM tframeindex:$Rn), (i64 0)>;
4894 // These can be much simpler than uimm12 because we don't to change the operand
4895 // type (e.g. LDURB and LDURH take the same operands).
4896 multiclass simm9_pats<dag address, dag Base, dag Offset> {
4897 defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>;
4898 defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>;
4900 defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address,
4902 defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address,
4905 defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address,
4907 defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address,
4909 defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address,
4911 defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address,
4914 def : Pat<(i64 (zextloadi32 address)),
4915 (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>;
4917 def : Pat<(truncstorei32 GPR64:$Rt, address),
4918 (LS32_STUR (EXTRACT_SUBREG GPR64:$Rt, sub_32), Base, Offset)>;
4920 defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>;
4921 defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>;
4922 def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>;
4925 defm : simm9_pats<(add GPR64xsp:$Rn, simm9:$SImm9),
4926 (i64 GPR64xsp:$Rn), (SDXF_simm9 simm9:$SImm9)>;
4928 defm : simm9_pats<(add_like_or GPR64xsp:$Rn, simm9:$SImm9),
4929 (i64 GPR64xsp:$Rn), (SDXF_simm9 simm9:$SImm9)>;
4932 //===------------------------------
4933 // 3. Register offset patterns
4934 //===------------------------------
4936 // Atomic patterns can be shared between integer operations of all sizes, a
4937 // quick multiclass here allows reuse.
4938 multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4939 dag Offset, dag Extend, dag address,
4940 RegisterClass TPR, ValueType sty> {
4941 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4942 (LOAD Base, Offset, Extend)>;
4944 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, TPR:$Rt),
4945 (STORE TPR:$Rt, Base, Offset, Extend)>;
4948 // The register offset instructions take three operands giving the instruction,
4949 // and have an annoying split between instructions where Rm is 32-bit and
4950 // 64-bit. So we need a special hierarchy to describe them. Other than that the
4951 // same operations should be supported as for simm9 and uimm12 addressing.
4953 multiclass ro_small_pats<Instruction LOAD, Instruction STORE,
4954 dag Base, dag Offset, dag Extend,
4955 dag address, ValueType sty>
4956 : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, GPR32, sty> {
4957 def : Pat<(!cast<SDNode>(zextload # sty) address),
4958 (LOAD Base, Offset, Extend)>;
4960 def : Pat<(!cast<SDNode>(extload # sty) address),
4961 (LOAD Base, Offset, Extend)>;
4963 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4964 // register was actually set.
4965 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4966 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
4968 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
4969 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
4971 def : Pat<(!cast<SDNode>(truncstore # sty) GPR32:$Rt, address),
4972 (STORE GPR32:$Rt, Base, Offset, Extend)>;
4974 // For truncating store from 64-bits, we have to manually tell LLVM to
4975 // ignore the high bits of the x register.
4976 def : Pat<(!cast<SDNode>(truncstore # sty) GPR64:$Rt, address),
4977 (STORE (EXTRACT_SUBREG GPR64:$Rt, sub_32), Base, Offset, Extend)>;
4981 // Next come patterns for sign-extending loads.
4982 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
4983 dag address, ValueType sty> {
4984 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
4985 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
4986 Base, Offset, Extend)>;
4988 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
4989 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
4990 Base, Offset, Extend)>;
4993 // and finally "natural-width" loads and stores come next.
4994 multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE,
4995 dag Base, dag Offset, dag Extend, dag address,
4996 RegisterClass TPR, ValueType sty> {
4997 def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>;
4998 def : Pat<(store (sty TPR:$Rt), address),
4999 (STORE TPR:$Rt, Base, Offset, Extend)>;
5002 multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE,
5003 dag Base, dag Offset, dag Extend, dag address,
5004 RegisterClass TPR, ValueType sty>
5005 : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, TPR, sty>,
5006 ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, TPR, sty>;
5008 multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset,
5010 defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"),
5011 !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"),
5012 Base, Offset, Extend,
5013 !foreach(decls.pattern, address,
5014 !subst(SHIFT, imm_eq0, decls.pattern)),
5016 defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"),
5017 !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"),
5018 Base, Offset, Extend,
5019 !foreach(decls.pattern, address,
5020 !subst(SHIFT, imm_eq1, decls.pattern)),
5022 defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5023 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5024 Base, Offset, Extend,
5025 !foreach(decls.pattern, address,
5026 !subst(SHIFT, imm_eq2, decls.pattern)),
5029 defm : ro_int_neutral_pats<
5030 !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5031 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5032 Base, Offset, Extend,
5033 !foreach(decls.pattern, address,
5034 !subst(SHIFT, imm_eq2, decls.pattern)),
5037 defm : ro_int_neutral_pats<
5038 !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
5039 !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
5040 Base, Offset, Extend,
5041 !foreach(decls.pattern, address,
5042 !subst(SHIFT, imm_eq3, decls.pattern)),
5045 defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"),
5046 !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"),
5047 Base, Offset, Extend,
5048 !foreach(decls.pattern, address,
5049 !subst(SHIFT, imm_eq1, decls.pattern)),
5052 defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"),
5053 !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"),
5054 Base, Offset, Extend,
5055 !foreach(decls.pattern, address,
5056 !subst(SHIFT, imm_eq2, decls.pattern)),
5059 defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"),
5060 !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"),
5061 Base, Offset, Extend,
5062 !foreach(decls.pattern, address,
5063 !subst(SHIFT, imm_eq3, decls.pattern)),
5066 defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"),
5067 !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"),
5068 Base, Offset, Extend,
5069 !foreach(decls.pattern, address,
5070 !subst(SHIFT, imm_eq4, decls.pattern)),
5073 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,
5074 !foreach(decls.pattern, address,
5075 !subst(SHIFT, imm_eq0, decls.pattern)),
5078 defm : ro_signed_pats<"H", Rm, Base, Offset, Extend,
5079 !foreach(decls.pattern, address,
5080 !subst(SHIFT, imm_eq1, decls.pattern)),
5083 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
5084 !subst(SHIFT, imm_eq2, decls.pattern))),
5085 (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset")
5086 Base, Offset, Extend)>;
5090 // Finally we're in a position to tell LLVM exactly what addresses are reachable
5091 // using register-offset instructions. Essentially a base plus a possibly
5092 // extended, possibly shifted (by access size) offset.
5094 defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (sext GPR32:$Rm)),
5095 (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 6)>;
5097 defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (shl (sext GPR32:$Rm), SHIFT)),
5098 (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 7)>;
5100 defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (zext GPR32:$Rm)),
5101 (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 2)>;
5103 defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (shl (zext GPR32:$Rm), SHIFT)),
5104 (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 3)>;
5106 defm : regoff_pats<"Xm", (add GPR64xsp:$Rn, GPR64:$Rm),
5107 (i64 GPR64xsp:$Rn), (i64 GPR64:$Rm), (i64 2)>;
5109 defm : regoff_pats<"Xm", (add GPR64xsp:$Rn, (shl GPR64:$Rm, SHIFT)),
5110 (i64 GPR64xsp:$Rn), (i64 GPR64:$Rm), (i64 3)>;