1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
27 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
29 //===----------------------------------------------------------------------===//
30 // AArch64-specific DAG Nodes.
33 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
34 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
39 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
40 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
46 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
47 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
54 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
55 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
57 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
58 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
59 SDTCisVT<2, OtherVT>]>;
62 def SDT_AArch64CSel : SDTypeProfile<1, 4,
67 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
70 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
71 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
72 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
75 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
76 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
77 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
78 SDTCisInt<2>, SDTCisInt<3>]>;
79 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
80 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
82 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
84 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
85 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
86 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
87 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
89 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
92 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
93 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
95 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
97 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
99 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
100 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
101 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
102 SDTCisSameAs<1, 4>]>;
106 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
107 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
108 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
109 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
110 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
111 [SDNPHasChain, SDNPOutGlue]>;
112 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
113 SDCallSeqEnd<[ SDTCisVT<0, i32>,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
116 def AArch64call : SDNode<"AArch64ISD::CALL",
117 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
122 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
124 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
126 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
128 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
132 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
133 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
134 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
135 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
136 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
137 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
138 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
139 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
140 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
142 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
143 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
145 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
146 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
148 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
150 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
152 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
153 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
155 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
156 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
157 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
158 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
159 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
161 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
162 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
163 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
164 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
165 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
166 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
168 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
169 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
170 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
171 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
172 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
173 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
174 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
176 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
177 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
178 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
179 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
181 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
182 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
183 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
184 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
185 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
186 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
187 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
188 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
190 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
191 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
192 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
194 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
195 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
196 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
197 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
198 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
200 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
201 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
202 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
204 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
205 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
206 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
207 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
208 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
209 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
210 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
212 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
213 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
214 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
215 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
216 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
218 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
219 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
221 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
223 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
224 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
226 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
227 [SDNPHasChain, SDNPSideEffect]>;
229 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
230 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
232 def AArch64tlsdesc_call : SDNode<"AArch64ISD::TLSDESC_CALL",
233 SDT_AArch64TLSDescCall,
234 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
237 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
238 SDT_AArch64WrapperLarge>;
241 //===----------------------------------------------------------------------===//
243 //===----------------------------------------------------------------------===//
245 // AArch64 Instruction Predicate Definitions.
247 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
248 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
249 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
250 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
251 def ForCodeSize : Predicate<"ForCodeSize">;
252 def NotForCodeSize : Predicate<"!ForCodeSize">;
254 include "AArch64InstrFormats.td"
256 //===----------------------------------------------------------------------===//
258 //===----------------------------------------------------------------------===//
259 // Miscellaneous instructions.
260 //===----------------------------------------------------------------------===//
262 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
263 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
264 [(AArch64callseq_start timm:$amt)]>;
265 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
266 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
267 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
269 let isReMaterializable = 1, isCodeGenOnly = 1 in {
270 // FIXME: The following pseudo instructions are only needed because remat
271 // cannot handle multiple instructions. When that changes, they can be
272 // removed, along with the AArch64Wrapper node.
274 let AddedComplexity = 10 in
275 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
276 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
279 // The MOVaddr instruction should match only when the add is not folded
280 // into a load or store address.
282 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
283 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
284 tglobaladdr:$low))]>,
285 Sched<[WriteAdrAdr]>;
287 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
288 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
290 Sched<[WriteAdrAdr]>;
292 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
293 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
295 Sched<[WriteAdrAdr]>;
297 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
298 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
299 tblockaddress:$low))]>,
300 Sched<[WriteAdrAdr]>;
302 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
303 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
304 tglobaltlsaddr:$low))]>,
305 Sched<[WriteAdrAdr]>;
307 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
308 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
309 texternalsym:$low))]>,
310 Sched<[WriteAdrAdr]>;
312 } // isReMaterializable, isCodeGenOnly
314 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
315 (LOADgot tglobaltlsaddr:$addr)>;
317 def : Pat<(AArch64LOADgot texternalsym:$addr),
318 (LOADgot texternalsym:$addr)>;
320 def : Pat<(AArch64LOADgot tconstpool:$addr),
321 (LOADgot tconstpool:$addr)>;
323 //===----------------------------------------------------------------------===//
324 // System instructions.
325 //===----------------------------------------------------------------------===//
327 def HINT : HintI<"hint">;
328 def : InstAlias<"nop", (HINT 0b000)>;
329 def : InstAlias<"yield",(HINT 0b001)>;
330 def : InstAlias<"wfe", (HINT 0b010)>;
331 def : InstAlias<"wfi", (HINT 0b011)>;
332 def : InstAlias<"sev", (HINT 0b100)>;
333 def : InstAlias<"sevl", (HINT 0b101)>;
335 // As far as LLVM is concerned this writes to the system's exclusive monitors.
336 let mayLoad = 1, mayStore = 1 in
337 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
339 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
340 // model patterns with sufficiently fine granularity.
341 let mayLoad = ?, mayStore = ? in {
342 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
343 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
345 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
346 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
348 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
349 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
352 def : InstAlias<"clrex", (CLREX 0xf)>;
353 def : InstAlias<"isb", (ISB 0xf)>;
357 def MSRpstate: MSRpstateI;
359 // The thread pointer (on Linux, at least, where this has been implemented) is
361 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
363 // Generic system instructions
364 def SYSxt : SystemXtI<0, "sys">;
365 def SYSLxt : SystemLXtI<1, "sysl">;
367 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
368 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
369 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
371 //===----------------------------------------------------------------------===//
372 // Move immediate instructions.
373 //===----------------------------------------------------------------------===//
375 defm MOVK : InsertImmediate<0b11, "movk">;
376 defm MOVN : MoveImmediate<0b00, "movn">;
378 let PostEncoderMethod = "fixMOVZ" in
379 defm MOVZ : MoveImmediate<0b10, "movz">;
381 // First group of aliases covers an implicit "lsl #0".
382 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
383 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
384 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
385 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
386 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
387 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
389 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
390 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
391 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
392 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
393 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
395 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
396 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
397 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
398 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
400 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
401 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
402 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
403 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
405 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
406 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
408 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
409 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
411 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
412 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
414 // Final group of aliases covers true "mov $Rd, $imm" cases.
415 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
416 int width, int shift> {
417 def _asmoperand : AsmOperandClass {
418 let Name = basename # width # "_lsl" # shift # "MovAlias";
419 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
421 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
424 def _movimm : Operand<i32> {
425 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
428 def : InstAlias<"mov $Rd, $imm",
429 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
432 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
433 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
435 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
436 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
437 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
438 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
440 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
441 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
443 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
444 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
445 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
446 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
448 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
449 isAsCheapAsAMove = 1 in {
450 // FIXME: The following pseudo instructions are only needed because remat
451 // cannot handle multiple instructions. When that changes, we can select
452 // directly to the real instructions and get rid of these pseudos.
455 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
456 [(set GPR32:$dst, imm:$src)]>,
459 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
460 [(set GPR64:$dst, imm:$src)]>,
462 } // isReMaterializable, isCodeGenOnly
464 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
465 // eventual expansion code fewer bits to worry about getting right. Marshalling
466 // the types is a little tricky though:
467 def i64imm_32bit : ImmLeaf<i64, [{
468 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
471 def trunc_imm : SDNodeXForm<imm, [{
472 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
475 def : Pat<(i64 i64imm_32bit:$src),
476 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
478 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
480 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
481 tglobaladdr:$g1, tglobaladdr:$g0),
482 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
483 tglobaladdr:$g2, 32),
484 tglobaladdr:$g1, 16),
485 tglobaladdr:$g0, 0)>;
487 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
488 tblockaddress:$g1, tblockaddress:$g0),
489 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
490 tblockaddress:$g2, 32),
491 tblockaddress:$g1, 16),
492 tblockaddress:$g0, 0)>;
494 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
495 tconstpool:$g1, tconstpool:$g0),
496 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
501 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
502 tjumptable:$g1, tjumptable:$g0),
503 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
509 //===----------------------------------------------------------------------===//
510 // Arithmetic instructions.
511 //===----------------------------------------------------------------------===//
513 // Add/subtract with carry.
514 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
515 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
517 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
518 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
519 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
520 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
523 defm ADD : AddSub<0, "add", add>;
524 defm SUB : AddSub<1, "sub">;
526 def : InstAlias<"mov $dst, $src",
527 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
528 def : InstAlias<"mov $dst, $src",
529 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
530 def : InstAlias<"mov $dst, $src",
531 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
532 def : InstAlias<"mov $dst, $src",
533 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
535 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
536 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
538 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
539 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
540 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
541 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
542 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
543 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
544 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
545 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
546 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
547 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
548 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
549 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
550 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
551 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
552 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
553 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
554 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
556 // Because of the immediate format for add/sub-imm instructions, the
557 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
558 // These patterns capture that transformation.
559 let AddedComplexity = 1 in {
560 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
561 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
562 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
563 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
564 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
565 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
566 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
567 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
570 // Because of the immediate format for add/sub-imm instructions, the
571 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
572 // These patterns capture that transformation.
573 let AddedComplexity = 1 in {
574 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
575 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
576 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
577 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
578 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
579 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
580 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
581 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
584 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
585 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
586 def : InstAlias<"neg $dst, $src$shift",
587 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
588 def : InstAlias<"neg $dst, $src$shift",
589 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
591 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
592 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
593 def : InstAlias<"negs $dst, $src$shift",
594 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
595 def : InstAlias<"negs $dst, $src$shift",
596 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
599 // Unsigned/Signed divide
600 defm UDIV : Div<0, "udiv", udiv>;
601 defm SDIV : Div<1, "sdiv", sdiv>;
602 let isCodeGenOnly = 1 in {
603 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
604 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
608 defm ASRV : Shift<0b10, "asr", sra>;
609 defm LSLV : Shift<0b00, "lsl", shl>;
610 defm LSRV : Shift<0b01, "lsr", srl>;
611 defm RORV : Shift<0b11, "ror", rotr>;
613 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
614 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
615 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
616 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
617 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
618 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
619 def : ShiftAlias<"rorv", RORVWr, GPR32>;
620 def : ShiftAlias<"rorv", RORVXr, GPR64>;
623 let AddedComplexity = 7 in {
624 defm MADD : MulAccum<0, "madd", add>;
625 defm MSUB : MulAccum<1, "msub", sub>;
627 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
628 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
629 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
630 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
632 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
633 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
634 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
635 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
636 } // AddedComplexity = 7
638 let AddedComplexity = 5 in {
639 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
640 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
641 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
642 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
644 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
645 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
646 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
647 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
649 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
650 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
651 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
652 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
653 } // AddedComplexity = 5
655 def : MulAccumWAlias<"mul", MADDWrrr>;
656 def : MulAccumXAlias<"mul", MADDXrrr>;
657 def : MulAccumWAlias<"mneg", MSUBWrrr>;
658 def : MulAccumXAlias<"mneg", MSUBXrrr>;
659 def : WideMulAccumAlias<"smull", SMADDLrrr>;
660 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
661 def : WideMulAccumAlias<"umull", UMADDLrrr>;
662 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
665 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
666 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
669 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
670 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
671 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
672 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
674 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
675 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
676 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
677 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
680 //===----------------------------------------------------------------------===//
681 // Logical instructions.
682 //===----------------------------------------------------------------------===//
685 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
686 defm AND : LogicalImm<0b00, "and", and, "bic">;
687 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
688 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
690 // FIXME: these aliases *are* canonical sometimes (when movz can't be
691 // used). Actually, it seems to be working right now, but putting logical_immXX
692 // here is a bit dodgy on the AsmParser side too.
693 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
694 logical_imm32:$imm), 0>;
695 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
696 logical_imm64:$imm), 0>;
700 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
701 defm BICS : LogicalRegS<0b11, 1, "bics",
702 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
703 defm AND : LogicalReg<0b00, 0, "and", and>;
704 defm BIC : LogicalReg<0b00, 1, "bic",
705 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
706 defm EON : LogicalReg<0b10, 1, "eon",
707 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
708 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
709 defm ORN : LogicalReg<0b01, 1, "orn",
710 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
711 defm ORR : LogicalReg<0b01, 0, "orr", or>;
713 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
714 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
716 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
717 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
719 def : InstAlias<"mvn $Wd, $Wm$sh",
720 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
721 def : InstAlias<"mvn $Xd, $Xm$sh",
722 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
724 def : InstAlias<"tst $src1, $src2",
725 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
726 def : InstAlias<"tst $src1, $src2",
727 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
729 def : InstAlias<"tst $src1, $src2",
730 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
731 def : InstAlias<"tst $src1, $src2",
732 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
734 def : InstAlias<"tst $src1, $src2$sh",
735 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
736 def : InstAlias<"tst $src1, $src2$sh",
737 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
740 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
741 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
744 //===----------------------------------------------------------------------===//
745 // One operand data processing instructions.
746 //===----------------------------------------------------------------------===//
748 defm CLS : OneOperandData<0b101, "cls">;
749 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
750 defm RBIT : OneOperandData<0b000, "rbit">;
752 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
753 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
755 def REV16Wr : OneWRegData<0b001, "rev16",
756 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
757 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
759 def : Pat<(cttz GPR32:$Rn),
760 (CLZWr (RBITWr GPR32:$Rn))>;
761 def : Pat<(cttz GPR64:$Rn),
762 (CLZXr (RBITXr GPR64:$Rn))>;
763 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
766 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
770 // Unlike the other one operand instructions, the instructions with the "rev"
771 // mnemonic do *not* just different in the size bit, but actually use different
772 // opcode bits for the different sizes.
773 def REVWr : OneWRegData<0b010, "rev", bswap>;
774 def REVXr : OneXRegData<0b011, "rev", bswap>;
775 def REV32Xr : OneXRegData<0b010, "rev32",
776 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
778 // The bswap commutes with the rotr so we want a pattern for both possible
780 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
781 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
783 //===----------------------------------------------------------------------===//
784 // Bitfield immediate extraction instruction.
785 //===----------------------------------------------------------------------===//
786 let neverHasSideEffects = 1 in
787 defm EXTR : ExtractImm<"extr">;
788 def : InstAlias<"ror $dst, $src, $shift",
789 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
790 def : InstAlias<"ror $dst, $src, $shift",
791 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
793 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
794 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
795 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
796 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
798 //===----------------------------------------------------------------------===//
799 // Other bitfield immediate instructions.
800 //===----------------------------------------------------------------------===//
801 let neverHasSideEffects = 1 in {
802 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
803 defm SBFM : BitfieldImm<0b00, "sbfm">;
804 defm UBFM : BitfieldImm<0b10, "ubfm">;
807 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
808 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
809 return CurDAG->getTargetConstant(enc, MVT::i64);
812 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
813 uint64_t enc = 31 - N->getZExtValue();
814 return CurDAG->getTargetConstant(enc, MVT::i64);
817 // min(7, 31 - shift_amt)
818 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
819 uint64_t enc = 31 - N->getZExtValue();
820 enc = enc > 7 ? 7 : enc;
821 return CurDAG->getTargetConstant(enc, MVT::i64);
824 // min(15, 31 - shift_amt)
825 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
826 uint64_t enc = 31 - N->getZExtValue();
827 enc = enc > 15 ? 15 : enc;
828 return CurDAG->getTargetConstant(enc, MVT::i64);
831 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
832 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
833 return CurDAG->getTargetConstant(enc, MVT::i64);
836 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
837 uint64_t enc = 63 - N->getZExtValue();
838 return CurDAG->getTargetConstant(enc, MVT::i64);
841 // min(7, 63 - shift_amt)
842 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
843 uint64_t enc = 63 - N->getZExtValue();
844 enc = enc > 7 ? 7 : enc;
845 return CurDAG->getTargetConstant(enc, MVT::i64);
848 // min(15, 63 - shift_amt)
849 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
850 uint64_t enc = 63 - N->getZExtValue();
851 enc = enc > 15 ? 15 : enc;
852 return CurDAG->getTargetConstant(enc, MVT::i64);
855 // min(31, 63 - shift_amt)
856 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
857 uint64_t enc = 63 - N->getZExtValue();
858 enc = enc > 31 ? 31 : enc;
859 return CurDAG->getTargetConstant(enc, MVT::i64);
862 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
863 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
864 (i64 (i32shift_b imm0_31:$imm)))>;
865 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
866 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
867 (i64 (i64shift_b imm0_63:$imm)))>;
869 let AddedComplexity = 10 in {
870 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
871 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
872 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
873 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
876 def : InstAlias<"asr $dst, $src, $shift",
877 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
878 def : InstAlias<"asr $dst, $src, $shift",
879 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
880 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
881 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
882 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
883 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
884 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
886 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
887 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
888 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
889 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
891 def : InstAlias<"lsr $dst, $src, $shift",
892 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
893 def : InstAlias<"lsr $dst, $src, $shift",
894 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
895 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
896 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
897 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
898 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
899 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
901 //===----------------------------------------------------------------------===//
902 // Conditionally set flags instructions.
903 //===----------------------------------------------------------------------===//
904 defm CCMN : CondSetFlagsImm<0, "ccmn">;
905 defm CCMP : CondSetFlagsImm<1, "ccmp">;
907 defm CCMN : CondSetFlagsReg<0, "ccmn">;
908 defm CCMP : CondSetFlagsReg<1, "ccmp">;
910 //===----------------------------------------------------------------------===//
911 // Conditional select instructions.
912 //===----------------------------------------------------------------------===//
913 defm CSEL : CondSelect<0, 0b00, "csel">;
915 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
916 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
917 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
918 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
920 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
921 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
922 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
923 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
924 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
925 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
926 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
927 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
928 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
929 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
930 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
931 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
933 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
934 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
935 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
936 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
937 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
938 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
939 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
940 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
942 // The inverse of the condition code from the alias instruction is what is used
943 // in the aliased instruction. The parser all ready inverts the condition code
944 // for these aliases.
945 def : InstAlias<"cset $dst, $cc",
946 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
947 def : InstAlias<"cset $dst, $cc",
948 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
950 def : InstAlias<"csetm $dst, $cc",
951 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
952 def : InstAlias<"csetm $dst, $cc",
953 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
955 def : InstAlias<"cinc $dst, $src, $cc",
956 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
957 def : InstAlias<"cinc $dst, $src, $cc",
958 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
960 def : InstAlias<"cinv $dst, $src, $cc",
961 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
962 def : InstAlias<"cinv $dst, $src, $cc",
963 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
965 def : InstAlias<"cneg $dst, $src, $cc",
966 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
967 def : InstAlias<"cneg $dst, $src, $cc",
968 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
970 //===----------------------------------------------------------------------===//
971 // PC-relative instructions.
972 //===----------------------------------------------------------------------===//
973 let isReMaterializable = 1 in {
974 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
975 def ADR : ADRI<0, "adr", adrlabel, []>;
976 } // neverHasSideEffects = 1
978 def ADRP : ADRI<1, "adrp", adrplabel,
979 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
980 } // isReMaterializable = 1
982 // page address of a constant pool entry, block address
983 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
984 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
986 //===----------------------------------------------------------------------===//
987 // Unconditional branch (register) instructions.
988 //===----------------------------------------------------------------------===//
990 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
991 def RET : BranchReg<0b0010, "ret", []>;
992 def DRPS : SpecialReturn<0b0101, "drps">;
993 def ERET : SpecialReturn<0b0100, "eret">;
994 } // isReturn = 1, isTerminator = 1, isBarrier = 1
996 // Default to the LR register.
997 def : InstAlias<"ret", (RET LR)>;
999 let isCall = 1, Defs = [LR], Uses = [SP] in {
1000 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1003 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1004 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1005 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1007 // Create a separate pseudo-instruction for codegen to use so that we don't
1008 // flag lr as used in every function. It'll be restored before the RET by the
1009 // epilogue if it's legitimately used.
1010 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1011 let isTerminator = 1;
1016 // This is a directive-like pseudo-instruction. The purpose is to insert an
1017 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1018 // (which in the usual case is a BLR).
1019 let hasSideEffects = 1 in
1020 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1021 let AsmString = ".tlsdesccall $sym";
1024 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
1025 // gets expanded to two MCInsts during lowering.
1026 let isCall = 1, Defs = [LR] in
1028 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
1029 [(AArch64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
1031 def : Pat<(AArch64tlsdesc_call GPR64:$dest, texternalsym:$sym),
1032 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
1033 //===----------------------------------------------------------------------===//
1034 // Conditional branch (immediate) instruction.
1035 //===----------------------------------------------------------------------===//
1036 def Bcc : BranchCond;
1038 //===----------------------------------------------------------------------===//
1039 // Compare-and-branch instructions.
1040 //===----------------------------------------------------------------------===//
1041 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1042 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1044 //===----------------------------------------------------------------------===//
1045 // Test-bit-and-branch instructions.
1046 //===----------------------------------------------------------------------===//
1047 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1048 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1050 //===----------------------------------------------------------------------===//
1051 // Unconditional branch (immediate) instructions.
1052 //===----------------------------------------------------------------------===//
1053 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1054 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1055 } // isBranch, isTerminator, isBarrier
1057 let isCall = 1, Defs = [LR], Uses = [SP] in {
1058 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1060 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1062 //===----------------------------------------------------------------------===//
1063 // Exception generation instructions.
1064 //===----------------------------------------------------------------------===//
1065 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1066 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1067 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1068 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1069 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1070 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1071 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1072 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1074 // DCPSn defaults to an immediate operand of zero if unspecified.
1075 def : InstAlias<"dcps1", (DCPS1 0)>;
1076 def : InstAlias<"dcps2", (DCPS2 0)>;
1077 def : InstAlias<"dcps3", (DCPS3 0)>;
1079 //===----------------------------------------------------------------------===//
1080 // Load instructions.
1081 //===----------------------------------------------------------------------===//
1083 // Pair (indexed, offset)
1084 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1085 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1086 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1087 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1088 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1090 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1092 // Pair (pre-indexed)
1093 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1094 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1095 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1096 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1097 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1099 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1101 // Pair (post-indexed)
1102 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1103 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1104 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1105 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1106 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1108 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1111 // Pair (no allocate)
1112 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1113 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1114 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1115 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1116 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1119 // (register offset)
1123 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1124 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1125 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1126 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1129 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1130 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1131 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1132 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1133 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1135 // Load sign-extended half-word
1136 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1137 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1139 // Load sign-extended byte
1140 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1141 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1143 // Load sign-extended word
1144 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1147 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1149 // For regular load, we do not have any alignment requirement.
1150 // Thus, it is safe to directly map the vector loads with interesting
1151 // addressing modes.
1152 // FIXME: We could do the same for bitconvert to floating point vectors.
1153 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1154 ValueType ScalTy, ValueType VecTy,
1155 Instruction LOADW, Instruction LOADX,
1157 def : Pat<(VecTy (scalar_to_vector (ScalTy
1158 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1159 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1160 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1163 def : Pat<(VecTy (scalar_to_vector (ScalTy
1164 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1165 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1166 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1170 let AddedComplexity = 10 in {
1171 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1172 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1174 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1175 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1177 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1178 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1180 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1181 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1183 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1184 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1186 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1188 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1191 def : Pat <(v1i64 (scalar_to_vector (i64
1192 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1193 ro_Wextend64:$extend))))),
1194 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1196 def : Pat <(v1i64 (scalar_to_vector (i64
1197 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1198 ro_Xextend64:$extend))))),
1199 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1202 // Match all load 64 bits width whose type is compatible with FPR64
1203 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1204 Instruction LOADW, Instruction LOADX> {
1206 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1207 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1209 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1210 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1213 let AddedComplexity = 10 in {
1214 let Predicates = [IsLE] in {
1215 // We must do vector loads with LD1 in big-endian.
1216 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1217 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1218 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1219 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1220 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1223 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1224 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1226 // Match all load 128 bits width whose type is compatible with FPR128
1227 let Predicates = [IsLE] in {
1228 // We must do vector loads with LD1 in big-endian.
1229 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1230 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1231 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1232 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1233 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1234 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1235 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1237 } // AddedComplexity = 10
1240 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1241 Instruction INSTW, Instruction INSTX> {
1242 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1243 (SUBREG_TO_REG (i64 0),
1244 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1247 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1248 (SUBREG_TO_REG (i64 0),
1249 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1253 let AddedComplexity = 10 in {
1254 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1255 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1256 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1258 // zextloadi1 -> zextloadi8
1259 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1261 // extload -> zextload
1262 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1263 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1264 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1266 // extloadi1 -> zextloadi8
1267 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1272 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1273 Instruction INSTW, Instruction INSTX> {
1274 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1275 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1277 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1278 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1282 let AddedComplexity = 10 in {
1283 // extload -> zextload
1284 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1285 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1286 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1288 // zextloadi1 -> zextloadi8
1289 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1293 // (unsigned immediate)
1295 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1297 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1298 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1300 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1301 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1303 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1304 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1305 [(set (f16 FPR16:$Rt),
1306 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1307 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1308 [(set (f32 FPR32:$Rt),
1309 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1310 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1311 [(set (f64 FPR64:$Rt),
1312 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1313 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1314 [(set (f128 FPR128:$Rt),
1315 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1317 // For regular load, we do not have any alignment requirement.
1318 // Thus, it is safe to directly map the vector loads with interesting
1319 // addressing modes.
1320 // FIXME: We could do the same for bitconvert to floating point vectors.
1321 def : Pat <(v8i8 (scalar_to_vector (i32
1322 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1323 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1324 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1325 def : Pat <(v16i8 (scalar_to_vector (i32
1326 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1327 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1328 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1329 def : Pat <(v4i16 (scalar_to_vector (i32
1330 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1331 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1332 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1333 def : Pat <(v8i16 (scalar_to_vector (i32
1334 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1335 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1336 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1337 def : Pat <(v2i32 (scalar_to_vector (i32
1338 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1339 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1340 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1341 def : Pat <(v4i32 (scalar_to_vector (i32
1342 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1343 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1344 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1345 def : Pat <(v1i64 (scalar_to_vector (i64
1346 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1347 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1348 def : Pat <(v2i64 (scalar_to_vector (i64
1349 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1350 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1351 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1353 // Match all load 64 bits width whose type is compatible with FPR64
1354 let Predicates = [IsLE] in {
1355 // We must use LD1 to perform vector loads in big-endian.
1356 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1357 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1358 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1359 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1360 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1361 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1362 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1363 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1364 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1365 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1367 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1368 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1369 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1370 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1372 // Match all load 128 bits width whose type is compatible with FPR128
1373 let Predicates = [IsLE] in {
1374 // We must use LD1 to perform vector loads in big-endian.
1375 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1376 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1377 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1378 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1379 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1380 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1381 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1382 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1383 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1384 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1385 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1386 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1387 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1388 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1390 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1391 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1393 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1395 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1396 uimm12s2:$offset)))]>;
1397 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1399 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1400 uimm12s1:$offset)))]>;
1402 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1403 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1404 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1405 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1407 // zextloadi1 -> zextloadi8
1408 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1409 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1410 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1411 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1413 // extload -> zextload
1414 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1415 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1416 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1417 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1418 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1419 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1420 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1421 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1422 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1423 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1424 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1425 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1426 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1427 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1429 // load sign-extended half-word
1430 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1432 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1433 uimm12s2:$offset)))]>;
1434 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1436 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1437 uimm12s2:$offset)))]>;
1439 // load sign-extended byte
1440 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1442 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1443 uimm12s1:$offset)))]>;
1444 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1446 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1447 uimm12s1:$offset)))]>;
1449 // load sign-extended word
1450 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1452 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1453 uimm12s4:$offset)))]>;
1455 // load zero-extended word
1456 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1457 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1460 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1461 [(AArch64Prefetch imm:$Rt,
1462 (am_indexed64 GPR64sp:$Rn,
1463 uimm12s8:$offset))]>;
1465 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1469 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1470 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1471 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1472 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1473 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1475 // load sign-extended word
1476 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1479 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1480 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1483 // (unscaled immediate)
1484 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1486 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1487 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1489 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1490 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1492 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1493 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1495 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1496 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1497 [(set (f32 FPR32:$Rt),
1498 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1499 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1500 [(set (f64 FPR64:$Rt),
1501 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1502 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1503 [(set (f128 FPR128:$Rt),
1504 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1507 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1509 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1511 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1513 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1515 // Match all load 64 bits width whose type is compatible with FPR64
1516 let Predicates = [IsLE] in {
1517 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1518 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1519 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1520 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1521 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1522 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1523 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1524 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1525 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1526 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1528 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1529 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1530 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1531 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1533 // Match all load 128 bits width whose type is compatible with FPR128
1534 let Predicates = [IsLE] in {
1535 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1536 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1537 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1538 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1539 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1540 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1541 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1542 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1543 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1544 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1545 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1546 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1547 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1548 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1552 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1553 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1554 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1555 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1556 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1557 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1558 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1559 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1560 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1561 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1562 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1563 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1564 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1565 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1567 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1568 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1569 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1570 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1571 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1572 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1573 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1574 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1575 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1576 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1577 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1578 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1579 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1580 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1584 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1586 // Define new assembler match classes as we want to only match these when
1587 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1588 // associate a DiagnosticType either, as we want the diagnostic for the
1589 // canonical form (the scaled operand) to take precedence.
1590 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1591 let Name = "SImm9OffsetFB" # Width;
1592 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1593 let RenderMethod = "addImmOperands";
1596 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1597 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1598 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1599 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1600 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1602 def simm9_offset_fb8 : Operand<i64> {
1603 let ParserMatchClass = SImm9OffsetFB8Operand;
1605 def simm9_offset_fb16 : Operand<i64> {
1606 let ParserMatchClass = SImm9OffsetFB16Operand;
1608 def simm9_offset_fb32 : Operand<i64> {
1609 let ParserMatchClass = SImm9OffsetFB32Operand;
1611 def simm9_offset_fb64 : Operand<i64> {
1612 let ParserMatchClass = SImm9OffsetFB64Operand;
1614 def simm9_offset_fb128 : Operand<i64> {
1615 let ParserMatchClass = SImm9OffsetFB128Operand;
1618 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1619 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1620 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1621 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1622 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1623 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1624 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1625 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1626 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1627 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1628 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1629 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1630 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1631 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1634 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1635 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1636 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1637 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1639 // load sign-extended half-word
1641 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1643 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1645 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1647 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1649 // load sign-extended byte
1651 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1653 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1655 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1657 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1659 // load sign-extended word
1661 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1663 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1665 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1666 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1667 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1668 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1669 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1670 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1671 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1672 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1673 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1674 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1675 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1676 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1677 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1678 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1679 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1682 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1683 [(AArch64Prefetch imm:$Rt,
1684 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1687 // (unscaled immediate, unprivileged)
1688 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1689 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1691 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1692 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1694 // load sign-extended half-word
1695 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1696 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1698 // load sign-extended byte
1699 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1700 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1702 // load sign-extended word
1703 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1706 // (immediate pre-indexed)
1707 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1708 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1709 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1710 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1711 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1712 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1713 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1715 // load sign-extended half-word
1716 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1717 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1719 // load sign-extended byte
1720 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1721 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1723 // load zero-extended byte
1724 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1725 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1727 // load sign-extended word
1728 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1731 // (immediate post-indexed)
1732 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1733 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1734 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1735 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1736 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1737 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1738 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1740 // load sign-extended half-word
1741 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1742 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1744 // load sign-extended byte
1745 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1746 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1748 // load zero-extended byte
1749 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1750 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1752 // load sign-extended word
1753 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1755 //===----------------------------------------------------------------------===//
1756 // Store instructions.
1757 //===----------------------------------------------------------------------===//
1759 // Pair (indexed, offset)
1760 // FIXME: Use dedicated range-checked addressing mode operand here.
1761 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1762 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1763 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1764 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1765 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1767 // Pair (pre-indexed)
1768 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1769 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1770 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1771 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1772 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1774 // Pair (pre-indexed)
1775 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1776 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1777 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1778 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1779 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1781 // Pair (no allocate)
1782 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1783 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1784 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1785 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1786 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1789 // (Register offset)
1792 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1793 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1794 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1795 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1799 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1800 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1801 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1802 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1803 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1805 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1806 Instruction STRW, Instruction STRX> {
1808 def : Pat<(storeop GPR64:$Rt,
1809 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1810 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1811 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1813 def : Pat<(storeop GPR64:$Rt,
1814 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1815 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1816 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1819 let AddedComplexity = 10 in {
1821 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1822 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1823 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1826 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1827 Instruction STRW, Instruction STRX> {
1828 def : Pat<(store (VecTy FPR:$Rt),
1829 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1830 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1832 def : Pat<(store (VecTy FPR:$Rt),
1833 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1834 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1837 let AddedComplexity = 10 in {
1838 // Match all store 64 bits width whose type is compatible with FPR64
1839 let Predicates = [IsLE] in {
1840 // We must use ST1 to store vectors in big-endian.
1841 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1842 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1843 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1844 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1845 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1848 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1849 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1851 // Match all store 128 bits width whose type is compatible with FPR128
1852 let Predicates = [IsLE] in {
1853 // We must use ST1 to store vectors in big-endian.
1854 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1855 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1856 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1857 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1858 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1859 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1860 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
1862 } // AddedComplexity = 10
1865 // (unsigned immediate)
1866 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1868 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1869 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1871 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1872 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1874 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
1875 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1876 [(store (f16 FPR16:$Rt),
1877 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
1878 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1879 [(store (f32 FPR32:$Rt),
1880 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1881 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1882 [(store (f64 FPR64:$Rt),
1883 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1884 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1886 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1887 [(truncstorei16 GPR32:$Rt,
1888 (am_indexed16 GPR64sp:$Rn,
1889 uimm12s2:$offset))]>;
1890 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
1891 [(truncstorei8 GPR32:$Rt,
1892 (am_indexed8 GPR64sp:$Rn,
1893 uimm12s1:$offset))]>;
1895 // Match all store 64 bits width whose type is compatible with FPR64
1896 let AddedComplexity = 10 in {
1897 let Predicates = [IsLE] in {
1898 // We must use ST1 to store vectors in big-endian.
1899 def : Pat<(store (v2f32 FPR64:$Rt),
1900 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1901 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1902 def : Pat<(store (v8i8 FPR64:$Rt),
1903 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1904 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1905 def : Pat<(store (v4i16 FPR64:$Rt),
1906 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1907 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1908 def : Pat<(store (v2i32 FPR64:$Rt),
1909 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1910 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1911 def : Pat<(store (v4f16 FPR64:$Rt),
1912 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1913 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1915 def : Pat<(store (v1f64 FPR64:$Rt),
1916 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1917 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1918 def : Pat<(store (v1i64 FPR64:$Rt),
1919 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1920 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1922 // Match all store 128 bits width whose type is compatible with FPR128
1923 let Predicates = [IsLE] in {
1924 // We must use ST1 to store vectors in big-endian.
1925 def : Pat<(store (v4f32 FPR128:$Rt),
1926 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1927 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1928 def : Pat<(store (v2f64 FPR128:$Rt),
1929 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1930 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1931 def : Pat<(store (v16i8 FPR128:$Rt),
1932 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1933 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1934 def : Pat<(store (v8i16 FPR128:$Rt),
1935 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1936 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1937 def : Pat<(store (v4i32 FPR128:$Rt),
1938 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1939 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1940 def : Pat<(store (v2i64 FPR128:$Rt),
1941 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1942 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1943 def : Pat<(store (v8f16 FPR128:$Rt),
1944 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1945 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1947 def : Pat<(store (f128 FPR128:$Rt),
1948 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1949 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1952 def : Pat<(truncstorei32 GPR64:$Rt,
1953 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
1954 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
1955 def : Pat<(truncstorei16 GPR64:$Rt,
1956 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
1957 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
1958 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
1959 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
1961 } // AddedComplexity = 10
1964 // (unscaled immediate)
1965 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
1967 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1968 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
1970 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1971 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
1973 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1974 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
1975 [(store (f16 FPR16:$Rt),
1976 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1977 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
1978 [(store (f32 FPR32:$Rt),
1979 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1980 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
1981 [(store (f64 FPR64:$Rt),
1982 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1983 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
1984 [(store (f128 FPR128:$Rt),
1985 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
1986 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
1987 [(truncstorei16 GPR32:$Rt,
1988 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1989 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
1990 [(truncstorei8 GPR32:$Rt,
1991 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1993 // Match all store 64 bits width whose type is compatible with FPR64
1994 let Predicates = [IsLE] in {
1995 // We must use ST1 to store vectors in big-endian.
1996 def : Pat<(store (v2f32 FPR64:$Rt),
1997 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1998 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1999 def : Pat<(store (v8i8 FPR64:$Rt),
2000 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2001 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2002 def : Pat<(store (v4i16 FPR64:$Rt),
2003 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2004 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2005 def : Pat<(store (v2i32 FPR64:$Rt),
2006 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2007 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2008 def : Pat<(store (v4f16 FPR64:$Rt),
2009 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2010 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2012 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2013 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2014 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2015 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2017 // Match all store 128 bits width whose type is compatible with FPR128
2018 let Predicates = [IsLE] in {
2019 // We must use ST1 to store vectors in big-endian.
2020 def : Pat<(store (v4f32 FPR128:$Rt),
2021 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2022 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2023 def : Pat<(store (v2f64 FPR128:$Rt),
2024 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2025 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2026 def : Pat<(store (v16i8 FPR128:$Rt),
2027 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2028 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2029 def : Pat<(store (v8i16 FPR128:$Rt),
2030 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2031 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2032 def : Pat<(store (v4i32 FPR128:$Rt),
2033 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2034 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2035 def : Pat<(store (v2i64 FPR128:$Rt),
2036 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2037 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2038 def : Pat<(store (v2f64 FPR128:$Rt),
2039 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2040 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2041 def : Pat<(store (v8f16 FPR128:$Rt),
2042 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2043 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2046 // unscaled i64 truncating stores
2047 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2048 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2049 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2050 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2051 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2052 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2055 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2056 def : InstAlias<"str $Rt, [$Rn, $offset]",
2057 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2058 def : InstAlias<"str $Rt, [$Rn, $offset]",
2059 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2060 def : InstAlias<"str $Rt, [$Rn, $offset]",
2061 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2062 def : InstAlias<"str $Rt, [$Rn, $offset]",
2063 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2064 def : InstAlias<"str $Rt, [$Rn, $offset]",
2065 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2066 def : InstAlias<"str $Rt, [$Rn, $offset]",
2067 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2068 def : InstAlias<"str $Rt, [$Rn, $offset]",
2069 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2071 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2072 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2073 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2074 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2077 // (unscaled immediate, unprivileged)
2078 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2079 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2081 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2082 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2085 // (immediate pre-indexed)
2086 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2087 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2088 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2089 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2090 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2091 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2092 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2094 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2095 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2098 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2099 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2101 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2102 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2104 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2105 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2108 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2109 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2110 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2111 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2112 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2113 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2114 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2115 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2116 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2117 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2118 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2119 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2120 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2121 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2123 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2124 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2125 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2126 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2127 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2128 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2129 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2130 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2131 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2132 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2133 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2134 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2135 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2136 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2139 // (immediate post-indexed)
2140 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2141 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2142 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2143 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2144 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2145 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2146 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2148 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2149 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2152 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2153 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2155 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2156 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2158 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2159 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2162 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2163 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2164 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2165 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2166 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2167 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2168 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2169 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2170 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2171 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2172 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2173 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2174 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2175 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2177 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2178 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2179 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2180 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2181 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2182 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2183 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2184 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2185 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2186 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2187 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2188 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2189 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2190 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2192 //===----------------------------------------------------------------------===//
2193 // Load/store exclusive instructions.
2194 //===----------------------------------------------------------------------===//
2196 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2197 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2198 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2199 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2201 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2202 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2203 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2204 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2206 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2207 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2208 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2209 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2211 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2212 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2213 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2214 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2216 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2217 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2218 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2219 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2221 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2222 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2223 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2224 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2226 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2227 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2229 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2230 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2232 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2233 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2235 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2236 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2238 //===----------------------------------------------------------------------===//
2239 // Scaled floating point to integer conversion instructions.
2240 //===----------------------------------------------------------------------===//
2242 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2243 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2244 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2245 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2246 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2247 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2248 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2249 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2250 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2251 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2252 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2253 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2254 let isCodeGenOnly = 1 in {
2255 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2256 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2257 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2258 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2261 //===----------------------------------------------------------------------===//
2262 // Scaled integer to floating point conversion instructions.
2263 //===----------------------------------------------------------------------===//
2265 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2266 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2268 //===----------------------------------------------------------------------===//
2269 // Unscaled integer to floating point conversion instruction.
2270 //===----------------------------------------------------------------------===//
2272 defm FMOV : UnscaledConversion<"fmov">;
2274 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
2275 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
2277 //===----------------------------------------------------------------------===//
2278 // Floating point conversion instruction.
2279 //===----------------------------------------------------------------------===//
2281 defm FCVT : FPConversion<"fcvt">;
2283 //===----------------------------------------------------------------------===//
2284 // Floating point single operand instructions.
2285 //===----------------------------------------------------------------------===//
2287 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2288 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2289 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2290 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2291 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2292 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2293 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2294 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2296 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2297 (FRINTNDr FPR64:$Rn)>;
2299 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2300 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2301 // <rdar://problem/13715968>
2302 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2303 let hasSideEffects = 1 in {
2304 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2307 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2309 let SchedRW = [WriteFDiv] in {
2310 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2313 //===----------------------------------------------------------------------===//
2314 // Floating point two operand instructions.
2315 //===----------------------------------------------------------------------===//
2317 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2318 let SchedRW = [WriteFDiv] in {
2319 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2321 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2322 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2323 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2324 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2325 let SchedRW = [WriteFMul] in {
2326 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2327 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2329 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2331 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2332 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2333 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2334 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2335 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2336 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2337 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2338 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2340 //===----------------------------------------------------------------------===//
2341 // Floating point three operand instructions.
2342 //===----------------------------------------------------------------------===//
2344 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2345 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2346 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2347 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2348 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2349 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2350 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2352 // The following def pats catch the case where the LHS of an FMA is negated.
2353 // The TriOpFrag above catches the case where the middle operand is negated.
2355 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2356 // the NEON variant.
2357 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2358 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2360 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2361 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2363 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2365 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2366 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2368 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2369 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2371 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2372 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2374 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2375 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2377 //===----------------------------------------------------------------------===//
2378 // Floating point comparison instructions.
2379 //===----------------------------------------------------------------------===//
2381 defm FCMPE : FPComparison<1, "fcmpe">;
2382 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2384 //===----------------------------------------------------------------------===//
2385 // Floating point conditional comparison instructions.
2386 //===----------------------------------------------------------------------===//
2388 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2389 defm FCCMP : FPCondComparison<0, "fccmp">;
2391 //===----------------------------------------------------------------------===//
2392 // Floating point conditional select instruction.
2393 //===----------------------------------------------------------------------===//
2395 defm FCSEL : FPCondSelect<"fcsel">;
2397 // CSEL instructions providing f128 types need to be handled by a
2398 // pseudo-instruction since the eventual code will need to introduce basic
2399 // blocks and control flow.
2400 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2401 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2402 [(set (f128 FPR128:$Rd),
2403 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2404 (i32 imm:$cond), NZCV))]> {
2406 let usesCustomInserter = 1;
2410 //===----------------------------------------------------------------------===//
2411 // Floating point immediate move.
2412 //===----------------------------------------------------------------------===//
2414 let isReMaterializable = 1 in {
2415 defm FMOV : FPMoveImmediate<"fmov">;
2418 //===----------------------------------------------------------------------===//
2419 // Advanced SIMD two vector instructions.
2420 //===----------------------------------------------------------------------===//
2422 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2423 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2424 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2425 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2426 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2427 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2428 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2429 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2430 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2431 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2433 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2434 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2435 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2436 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2437 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2438 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2439 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2440 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2441 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2442 (FCVTLv4i16 V64:$Rn)>;
2443 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2445 (FCVTLv8i16 V128:$Rn)>;
2446 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2447 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2449 (FCVTLv4i32 V128:$Rn)>;
2451 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2452 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2454 (FCVTLv8i16 V128:$Rn)>;
2456 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2457 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2458 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2459 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2460 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2461 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2462 (FCVTNv4i16 V128:$Rn)>;
2463 def : Pat<(concat_vectors V64:$Rd,
2464 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2465 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2466 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2467 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2468 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2469 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2470 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2471 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2472 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2473 int_aarch64_neon_fcvtxn>;
2474 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2475 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2476 let isCodeGenOnly = 1 in {
2477 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2478 int_aarch64_neon_fcvtzs>;
2479 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2480 int_aarch64_neon_fcvtzu>;
2482 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2483 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2484 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2485 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2486 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2487 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2488 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2489 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2490 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2491 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2492 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2493 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2494 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2495 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2496 // Aliases for MVN -> NOT.
2497 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2498 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2499 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2500 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2502 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2503 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2504 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2505 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2506 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2507 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2508 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2510 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2511 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2512 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2513 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2514 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2515 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2516 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2517 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2519 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2520 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2521 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2522 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2523 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2525 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2526 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2527 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2528 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2529 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2530 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2531 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2532 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2533 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2534 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2535 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2536 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2537 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2538 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2539 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2540 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2541 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2542 int_aarch64_neon_uaddlp>;
2543 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2544 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2545 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2546 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2547 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2548 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2550 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2551 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2552 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2553 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2554 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2555 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2557 // Patterns for vector long shift (by element width). These need to match all
2558 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2560 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2561 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2562 (SHLLv8i8 V64:$Rn)>;
2563 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2564 (SHLLv16i8 V128:$Rn)>;
2565 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2566 (SHLLv4i16 V64:$Rn)>;
2567 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2568 (SHLLv8i16 V128:$Rn)>;
2569 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2570 (SHLLv2i32 V64:$Rn)>;
2571 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2572 (SHLLv4i32 V128:$Rn)>;
2575 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2576 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2577 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2579 //===----------------------------------------------------------------------===//
2580 // Advanced SIMD three vector instructions.
2581 //===----------------------------------------------------------------------===//
2583 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2584 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2585 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2586 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2587 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2588 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2589 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2590 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2591 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2592 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2593 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2594 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2595 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2596 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2597 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2598 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2599 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2600 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2601 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2602 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2603 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2604 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2605 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2606 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2607 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2609 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2610 // instruction expects the addend first, while the fma intrinsic puts it last.
2611 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2612 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2613 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2614 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2616 // The following def pats catch the case where the LHS of an FMA is negated.
2617 // The TriOpFrag above catches the case where the middle operand is negated.
2618 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2619 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2621 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2622 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2624 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2625 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2627 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2628 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2629 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2630 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2631 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2632 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2633 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2634 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2635 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2636 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2637 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2638 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2639 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2640 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2641 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2642 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2643 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2644 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2645 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2646 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2647 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2648 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2649 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2650 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2651 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2652 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2653 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2654 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2655 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2656 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2657 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2658 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2659 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2660 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2661 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2662 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2663 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2664 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2665 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2666 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2667 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2668 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2669 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2670 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2671 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2672 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2674 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2675 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2676 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2677 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2678 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2679 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2680 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2681 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2682 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2683 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2684 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2686 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2687 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2688 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2689 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2690 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2691 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2692 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2693 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2695 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2696 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2697 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2698 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2699 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2700 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2701 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2702 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2704 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2705 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2706 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2707 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2708 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2709 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2710 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2711 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2713 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2714 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2715 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2716 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2717 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2718 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2719 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2720 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2722 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2723 "|cmls.8b\t$dst, $src1, $src2}",
2724 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2725 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2726 "|cmls.16b\t$dst, $src1, $src2}",
2727 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2728 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2729 "|cmls.4h\t$dst, $src1, $src2}",
2730 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2731 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2732 "|cmls.8h\t$dst, $src1, $src2}",
2733 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2734 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2735 "|cmls.2s\t$dst, $src1, $src2}",
2736 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2737 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2738 "|cmls.4s\t$dst, $src1, $src2}",
2739 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2740 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2741 "|cmls.2d\t$dst, $src1, $src2}",
2742 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2744 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2745 "|cmlo.8b\t$dst, $src1, $src2}",
2746 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2747 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2748 "|cmlo.16b\t$dst, $src1, $src2}",
2749 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2750 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2751 "|cmlo.4h\t$dst, $src1, $src2}",
2752 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2753 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2754 "|cmlo.8h\t$dst, $src1, $src2}",
2755 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2756 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2757 "|cmlo.2s\t$dst, $src1, $src2}",
2758 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2759 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2760 "|cmlo.4s\t$dst, $src1, $src2}",
2761 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2762 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2763 "|cmlo.2d\t$dst, $src1, $src2}",
2764 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2766 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2767 "|cmle.8b\t$dst, $src1, $src2}",
2768 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2769 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2770 "|cmle.16b\t$dst, $src1, $src2}",
2771 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2772 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2773 "|cmle.4h\t$dst, $src1, $src2}",
2774 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2775 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2776 "|cmle.8h\t$dst, $src1, $src2}",
2777 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2778 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2779 "|cmle.2s\t$dst, $src1, $src2}",
2780 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2781 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2782 "|cmle.4s\t$dst, $src1, $src2}",
2783 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2784 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2785 "|cmle.2d\t$dst, $src1, $src2}",
2786 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2788 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2789 "|cmlt.8b\t$dst, $src1, $src2}",
2790 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2791 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2792 "|cmlt.16b\t$dst, $src1, $src2}",
2793 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2794 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2795 "|cmlt.4h\t$dst, $src1, $src2}",
2796 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2797 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2798 "|cmlt.8h\t$dst, $src1, $src2}",
2799 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2800 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2801 "|cmlt.2s\t$dst, $src1, $src2}",
2802 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2803 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2804 "|cmlt.4s\t$dst, $src1, $src2}",
2805 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2806 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2807 "|cmlt.2d\t$dst, $src1, $src2}",
2808 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2810 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2811 "|fcmle.2s\t$dst, $src1, $src2}",
2812 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2813 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2814 "|fcmle.4s\t$dst, $src1, $src2}",
2815 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2816 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2817 "|fcmle.2d\t$dst, $src1, $src2}",
2818 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2820 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2821 "|fcmlt.2s\t$dst, $src1, $src2}",
2822 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2823 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2824 "|fcmlt.4s\t$dst, $src1, $src2}",
2825 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2826 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2827 "|fcmlt.2d\t$dst, $src1, $src2}",
2828 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2830 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2831 "|facle.2s\t$dst, $src1, $src2}",
2832 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2833 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2834 "|facle.4s\t$dst, $src1, $src2}",
2835 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2836 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2837 "|facle.2d\t$dst, $src1, $src2}",
2838 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2840 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2841 "|faclt.2s\t$dst, $src1, $src2}",
2842 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2843 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2844 "|faclt.4s\t$dst, $src1, $src2}",
2845 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2846 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2847 "|faclt.2d\t$dst, $src1, $src2}",
2848 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2850 //===----------------------------------------------------------------------===//
2851 // Advanced SIMD three scalar instructions.
2852 //===----------------------------------------------------------------------===//
2854 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2855 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
2856 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
2857 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
2858 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
2859 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
2860 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
2861 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
2862 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2863 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2864 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2865 int_aarch64_neon_facge>;
2866 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2867 int_aarch64_neon_facgt>;
2868 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2869 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2870 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2871 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
2872 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
2873 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
2874 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
2875 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
2876 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
2877 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
2878 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
2879 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
2880 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
2881 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
2882 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2883 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
2884 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
2885 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
2886 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
2887 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
2888 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
2890 def : InstAlias<"cmls $dst, $src1, $src2",
2891 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2892 def : InstAlias<"cmle $dst, $src1, $src2",
2893 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2894 def : InstAlias<"cmlo $dst, $src1, $src2",
2895 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2896 def : InstAlias<"cmlt $dst, $src1, $src2",
2897 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2898 def : InstAlias<"fcmle $dst, $src1, $src2",
2899 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2900 def : InstAlias<"fcmle $dst, $src1, $src2",
2901 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2902 def : InstAlias<"fcmlt $dst, $src1, $src2",
2903 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2904 def : InstAlias<"fcmlt $dst, $src1, $src2",
2905 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2906 def : InstAlias<"facle $dst, $src1, $src2",
2907 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2908 def : InstAlias<"facle $dst, $src1, $src2",
2909 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2910 def : InstAlias<"faclt $dst, $src1, $src2",
2911 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2912 def : InstAlias<"faclt $dst, $src1, $src2",
2913 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2915 //===----------------------------------------------------------------------===//
2916 // Advanced SIMD three scalar instructions (mixed operands).
2917 //===----------------------------------------------------------------------===//
2918 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2919 int_aarch64_neon_sqdmulls_scalar>;
2920 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2921 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2923 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
2924 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2925 (i32 FPR32:$Rm))))),
2926 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2927 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
2928 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2929 (i32 FPR32:$Rm))))),
2930 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2932 //===----------------------------------------------------------------------===//
2933 // Advanced SIMD two scalar instructions.
2934 //===----------------------------------------------------------------------===//
2936 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
2937 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
2938 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
2939 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
2940 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
2941 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
2942 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2943 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2944 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2945 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2946 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2947 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2948 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2949 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2950 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2951 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2952 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2953 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2954 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2955 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2956 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2957 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2958 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2959 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2960 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2961 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2962 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2963 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
2964 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2965 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2966 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
2967 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
2968 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2969 int_aarch64_neon_suqadd>;
2970 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
2971 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
2972 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2973 int_aarch64_neon_usqadd>;
2975 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
2977 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
2978 (FCVTASv1i64 FPR64:$Rn)>;
2979 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
2980 (FCVTAUv1i64 FPR64:$Rn)>;
2981 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
2982 (FCVTMSv1i64 FPR64:$Rn)>;
2983 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2984 (FCVTMUv1i64 FPR64:$Rn)>;
2985 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
2986 (FCVTNSv1i64 FPR64:$Rn)>;
2987 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2988 (FCVTNUv1i64 FPR64:$Rn)>;
2989 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
2990 (FCVTPSv1i64 FPR64:$Rn)>;
2991 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2992 (FCVTPUv1i64 FPR64:$Rn)>;
2994 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
2995 (FRECPEv1i32 FPR32:$Rn)>;
2996 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
2997 (FRECPEv1i64 FPR64:$Rn)>;
2998 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
2999 (FRECPEv1i64 FPR64:$Rn)>;
3001 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3002 (FRECPXv1i32 FPR32:$Rn)>;
3003 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3004 (FRECPXv1i64 FPR64:$Rn)>;
3006 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3007 (FRSQRTEv1i32 FPR32:$Rn)>;
3008 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3009 (FRSQRTEv1i64 FPR64:$Rn)>;
3010 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3011 (FRSQRTEv1i64 FPR64:$Rn)>;
3013 // If an integer is about to be converted to a floating point value,
3014 // just load it on the floating point unit.
3015 // Here are the patterns for 8 and 16-bits to float.
3017 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3018 SDPatternOperator loadop, Instruction UCVTF,
3019 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3021 def : Pat<(DstTy (uint_to_fp (SrcTy
3022 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3023 ro.Wext:$extend))))),
3024 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3025 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3028 def : Pat<(DstTy (uint_to_fp (SrcTy
3029 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3030 ro.Wext:$extend))))),
3031 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3032 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3036 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3037 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3038 def : Pat <(f32 (uint_to_fp (i32
3039 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3040 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3041 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3042 def : Pat <(f32 (uint_to_fp (i32
3043 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3044 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3045 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3046 // 16-bits -> float.
3047 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3048 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3049 def : Pat <(f32 (uint_to_fp (i32
3050 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3051 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3052 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3053 def : Pat <(f32 (uint_to_fp (i32
3054 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3055 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3056 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3057 // 32-bits are handled in target specific dag combine:
3058 // performIntToFpCombine.
3059 // 64-bits integer to 32-bits floating point, not possible with
3060 // UCVTF on floating point registers (both source and destination
3061 // must have the same size).
3063 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3064 // 8-bits -> double.
3065 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3066 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3067 def : Pat <(f64 (uint_to_fp (i32
3068 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3069 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3070 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3071 def : Pat <(f64 (uint_to_fp (i32
3072 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3073 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3074 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3075 // 16-bits -> double.
3076 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3077 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3078 def : Pat <(f64 (uint_to_fp (i32
3079 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3080 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3081 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3082 def : Pat <(f64 (uint_to_fp (i32
3083 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3084 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3085 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3086 // 32-bits -> double.
3087 defm : UIntToFPROLoadPat<f64, i32, load,
3088 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3089 def : Pat <(f64 (uint_to_fp (i32
3090 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3091 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3092 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3093 def : Pat <(f64 (uint_to_fp (i32
3094 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3095 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3096 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3097 // 64-bits -> double are handled in target specific dag combine:
3098 // performIntToFpCombine.
3100 //===----------------------------------------------------------------------===//
3101 // Advanced SIMD three different-sized vector instructions.
3102 //===----------------------------------------------------------------------===//
3104 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3105 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3106 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3107 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3108 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3109 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3110 int_aarch64_neon_sabd>;
3111 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3112 int_aarch64_neon_sabd>;
3113 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3114 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3115 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3116 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3117 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3118 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3119 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3120 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3121 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3122 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3123 int_aarch64_neon_sqadd>;
3124 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3125 int_aarch64_neon_sqsub>;
3126 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3127 int_aarch64_neon_sqdmull>;
3128 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3129 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3130 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3131 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3132 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3133 int_aarch64_neon_uabd>;
3134 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3135 int_aarch64_neon_uabd>;
3136 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3137 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3138 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3139 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3140 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3141 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3142 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3143 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3144 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3145 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3146 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3147 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3148 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3150 // Patterns for 64-bit pmull
3151 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3152 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3153 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3154 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3155 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3157 // CodeGen patterns for addhn and subhn instructions, which can actually be
3158 // written in LLVM IR without too much difficulty.
3161 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3162 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3163 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3165 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3166 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3168 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3169 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3170 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3172 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3173 V128:$Rn, V128:$Rm)>;
3174 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3175 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3177 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3178 V128:$Rn, V128:$Rm)>;
3179 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3180 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3182 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3183 V128:$Rn, V128:$Rm)>;
3186 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3187 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3188 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3190 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3191 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3193 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3194 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3195 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3197 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3198 V128:$Rn, V128:$Rm)>;
3199 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3200 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3202 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3203 V128:$Rn, V128:$Rm)>;
3204 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3205 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3207 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3208 V128:$Rn, V128:$Rm)>;
3210 //----------------------------------------------------------------------------
3211 // AdvSIMD bitwise extract from vector instruction.
3212 //----------------------------------------------------------------------------
3214 defm EXT : SIMDBitwiseExtract<"ext">;
3216 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3217 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3218 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3219 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3220 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3221 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3222 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3223 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3224 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3225 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3226 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3227 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3228 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3229 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3230 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3231 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3232 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3233 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3234 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3235 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3237 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3239 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3240 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3241 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3242 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3243 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3244 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3245 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3246 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3247 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3248 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3249 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3250 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3251 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3252 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3255 //----------------------------------------------------------------------------
3256 // AdvSIMD zip vector
3257 //----------------------------------------------------------------------------
3259 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3260 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3261 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3262 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3263 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3264 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3266 //----------------------------------------------------------------------------
3267 // AdvSIMD TBL/TBX instructions
3268 //----------------------------------------------------------------------------
3270 defm TBL : SIMDTableLookup< 0, "tbl">;
3271 defm TBX : SIMDTableLookupTied<1, "tbx">;
3273 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3274 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3275 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3276 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3278 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3279 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3280 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3281 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3282 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3283 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3286 //----------------------------------------------------------------------------
3287 // AdvSIMD scalar CPY instruction
3288 //----------------------------------------------------------------------------
3290 defm CPY : SIMDScalarCPY<"cpy">;
3292 //----------------------------------------------------------------------------
3293 // AdvSIMD scalar pairwise instructions
3294 //----------------------------------------------------------------------------
3296 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3297 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3298 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3299 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3300 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3301 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3302 def : Pat<(i64 (int_aarch64_neon_saddv (v2i64 V128:$Rn))),
3303 (ADDPv2i64p V128:$Rn)>;
3304 def : Pat<(i64 (int_aarch64_neon_uaddv (v2i64 V128:$Rn))),
3305 (ADDPv2i64p V128:$Rn)>;
3306 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3307 (FADDPv2i32p V64:$Rn)>;
3308 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3309 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3310 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3311 (FADDPv2i64p V128:$Rn)>;
3312 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3313 (FMAXNMPv2i32p V64:$Rn)>;
3314 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3315 (FMAXNMPv2i64p V128:$Rn)>;
3316 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3317 (FMAXPv2i32p V64:$Rn)>;
3318 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3319 (FMAXPv2i64p V128:$Rn)>;
3320 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3321 (FMINNMPv2i32p V64:$Rn)>;
3322 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3323 (FMINNMPv2i64p V128:$Rn)>;
3324 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3325 (FMINPv2i32p V64:$Rn)>;
3326 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3327 (FMINPv2i64p V128:$Rn)>;
3329 //----------------------------------------------------------------------------
3330 // AdvSIMD INS/DUP instructions
3331 //----------------------------------------------------------------------------
3333 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3334 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3335 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3336 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3337 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3338 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3339 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3341 def DUPv2i64lane : SIMDDup64FromElement;
3342 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3343 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3344 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3345 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3346 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3347 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3349 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3350 (v2f32 (DUPv2i32lane
3351 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3353 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3354 (v4f32 (DUPv4i32lane
3355 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3357 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3358 (v2f64 (DUPv2i64lane
3359 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3361 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3362 (v4f16 (DUPv4i16lane
3363 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3365 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3366 (v8f16 (DUPv8i16lane
3367 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3370 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3371 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3372 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3373 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3375 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3376 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3377 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3378 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3379 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3380 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3382 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3383 // instruction even if the types don't match: we just have to remap the lane
3384 // carefully. N.b. this trick only applies to truncations.
3385 def VecIndex_x2 : SDNodeXForm<imm, [{
3386 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3388 def VecIndex_x4 : SDNodeXForm<imm, [{
3389 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3391 def VecIndex_x8 : SDNodeXForm<imm, [{
3392 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3395 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3396 ValueType Src128VT, ValueType ScalVT,
3397 Instruction DUP, SDNodeXForm IdxXFORM> {
3398 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3400 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3402 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3404 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3407 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3408 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3409 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3411 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3412 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3413 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3415 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3416 SDNodeXForm IdxXFORM> {
3417 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3419 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3421 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3423 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3426 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3427 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3428 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3430 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3431 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3432 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3434 // SMOV and UMOV definitions, with some extra patterns for convenience
3438 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3439 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3440 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3441 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3442 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3443 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3444 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3445 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3446 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3447 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3448 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3449 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3451 // Extracting i8 or i16 elements will have the zero-extend transformed to
3452 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3453 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3454 // bits of the destination register.
3455 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3457 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3458 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3460 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3464 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3465 (SUBREG_TO_REG (i32 0),
3466 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3467 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3468 (SUBREG_TO_REG (i32 0),
3469 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3471 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3472 (SUBREG_TO_REG (i32 0),
3473 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3474 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3475 (SUBREG_TO_REG (i32 0),
3476 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3478 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3479 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3480 (i32 FPR32:$Rn), ssub))>;
3481 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3482 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3483 (i32 FPR32:$Rn), ssub))>;
3484 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3485 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3486 (i64 FPR64:$Rn), dsub))>;
3488 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3489 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3490 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3491 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3492 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3493 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3495 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3496 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3499 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3501 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3505 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3506 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3508 V128:$Rn, VectorIndexH:$imm,
3509 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3512 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3513 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3516 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3518 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3521 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3522 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3524 V128:$Rn, VectorIndexS:$imm,
3525 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3527 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3528 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3530 V128:$Rn, VectorIndexD:$imm,
3531 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3534 // Copy an element at a constant index in one vector into a constant indexed
3535 // element of another.
3536 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3537 // index type and INS extension
3538 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3539 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3540 VectorIndexB:$idx2)),
3542 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3544 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3545 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3546 VectorIndexH:$idx2)),
3548 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3550 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3551 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3552 VectorIndexS:$idx2)),
3554 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3556 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3557 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3558 VectorIndexD:$idx2)),
3560 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3563 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3564 ValueType VTScal, Instruction INS> {
3565 def : Pat<(VT128 (vector_insert V128:$src,
3566 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3568 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3570 def : Pat<(VT128 (vector_insert V128:$src,
3571 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3573 (INS V128:$src, imm:$Immd,
3574 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3576 def : Pat<(VT64 (vector_insert V64:$src,
3577 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3579 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3580 imm:$Immd, V128:$Rn, imm:$Immn),
3583 def : Pat<(VT64 (vector_insert V64:$src,
3584 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3587 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3588 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3592 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3593 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3594 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3595 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3596 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3597 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3598 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3601 // Floating point vector extractions are codegen'd as either a sequence of
3602 // subregister extractions, possibly fed by an INS if the lane number is
3603 // anything other than zero.
3604 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3605 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3606 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3607 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3608 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3609 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3610 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3611 (f64 (EXTRACT_SUBREG
3612 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3613 V128:$Rn, VectorIndexD:$idx),
3615 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3616 (f32 (EXTRACT_SUBREG
3617 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3618 V128:$Rn, VectorIndexS:$idx),
3620 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3621 (f16 (EXTRACT_SUBREG
3622 (INSvi16lane (v8f16 (IMPLICIT_DEF)), 0,
3623 V128:$Rn, VectorIndexH:$idx),
3626 // All concat_vectors operations are canonicalised to act on i64 vectors for
3627 // AArch64. In the general case we need an instruction, which had just as well be
3629 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3630 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3631 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3632 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3634 def : ConcatPat<v2i64, v1i64>;
3635 def : ConcatPat<v2f64, v1f64>;
3636 def : ConcatPat<v4i32, v2i32>;
3637 def : ConcatPat<v4f32, v2f32>;
3638 def : ConcatPat<v8i16, v4i16>;
3639 def : ConcatPat<v8f16, v4f16>;
3640 def : ConcatPat<v16i8, v8i8>;
3642 // If the high lanes are undef, though, we can just ignore them:
3643 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3644 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3645 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3647 def : ConcatUndefPat<v2i64, v1i64>;
3648 def : ConcatUndefPat<v2f64, v1f64>;
3649 def : ConcatUndefPat<v4i32, v2i32>;
3650 def : ConcatUndefPat<v4f32, v2f32>;
3651 def : ConcatUndefPat<v8i16, v4i16>;
3652 def : ConcatUndefPat<v16i8, v8i8>;
3654 //----------------------------------------------------------------------------
3655 // AdvSIMD across lanes instructions
3656 //----------------------------------------------------------------------------
3658 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3659 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3660 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3661 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3662 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3663 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3664 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3665 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3666 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3667 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3668 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3670 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3671 // If there is a sign extension after this intrinsic, consume it as smov already
3673 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3675 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3676 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3678 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3680 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3681 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3683 // If there is a sign extension after this intrinsic, consume it as smov already
3685 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3687 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3688 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3690 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3692 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3693 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3695 // If there is a sign extension after this intrinsic, consume it as smov already
3697 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3699 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3700 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3702 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3704 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3705 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3707 // If there is a sign extension after this intrinsic, consume it as smov already
3709 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3711 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3712 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3714 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3716 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3717 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3720 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3721 (i32 (EXTRACT_SUBREG
3722 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3723 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3727 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3728 // If there is a masking operation keeping only what has been actually
3729 // generated, consume it.
3730 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3731 (i32 (EXTRACT_SUBREG
3732 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3733 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3735 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3736 (i32 (EXTRACT_SUBREG
3737 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3738 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3740 // If there is a masking operation keeping only what has been actually
3741 // generated, consume it.
3742 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3743 (i32 (EXTRACT_SUBREG
3744 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3745 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3747 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3748 (i32 (EXTRACT_SUBREG
3749 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3750 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3753 // If there is a masking operation keeping only what has been actually
3754 // generated, consume it.
3755 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3756 (i32 (EXTRACT_SUBREG
3757 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3758 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3760 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3761 (i32 (EXTRACT_SUBREG
3762 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3763 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3765 // If there is a masking operation keeping only what has been actually
3766 // generated, consume it.
3767 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3768 (i32 (EXTRACT_SUBREG
3769 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3770 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3772 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3773 (i32 (EXTRACT_SUBREG
3774 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3775 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3778 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3779 (i32 (EXTRACT_SUBREG
3780 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3781 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3786 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3787 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3789 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3790 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3792 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3794 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3795 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3798 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3799 (i32 (EXTRACT_SUBREG
3800 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3801 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3803 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3804 (i32 (EXTRACT_SUBREG
3805 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3806 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3809 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3810 (i64 (EXTRACT_SUBREG
3811 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3812 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3816 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3818 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3819 (i32 (EXTRACT_SUBREG
3820 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3821 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3823 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3824 (i32 (EXTRACT_SUBREG
3825 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3826 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3829 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3830 (i32 (EXTRACT_SUBREG
3831 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3832 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3834 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3835 (i32 (EXTRACT_SUBREG
3836 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3837 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3840 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3841 (i64 (EXTRACT_SUBREG
3842 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3843 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3847 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_aarch64_neon_saddv>;
3848 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3849 def : Pat<(i32 (int_aarch64_neon_saddv (v2i32 V64:$Rn))),
3850 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3852 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_aarch64_neon_uaddv>;
3853 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3854 def : Pat<(i32 (int_aarch64_neon_uaddv (v2i32 V64:$Rn))),
3855 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3857 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_aarch64_neon_smaxv>;
3858 def : Pat<(i32 (int_aarch64_neon_smaxv (v2i32 V64:$Rn))),
3859 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3861 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_aarch64_neon_sminv>;
3862 def : Pat<(i32 (int_aarch64_neon_sminv (v2i32 V64:$Rn))),
3863 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3865 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_aarch64_neon_umaxv>;
3866 def : Pat<(i32 (int_aarch64_neon_umaxv (v2i32 V64:$Rn))),
3867 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3869 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_aarch64_neon_uminv>;
3870 def : Pat<(i32 (int_aarch64_neon_uminv (v2i32 V64:$Rn))),
3871 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3873 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
3874 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
3876 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3877 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
3878 (i64 (EXTRACT_SUBREG
3879 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3880 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3882 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3883 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
3884 (i64 (EXTRACT_SUBREG
3885 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3886 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3889 //------------------------------------------------------------------------------
3890 // AdvSIMD modified immediate instructions
3891 //------------------------------------------------------------------------------
3894 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
3896 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
3898 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3899 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3900 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3901 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3903 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3904 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3905 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3906 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3908 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3909 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3910 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3911 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3913 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3914 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3915 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3916 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3919 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3921 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3922 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3924 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3925 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3927 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3931 // EDIT byte mask: scalar
3932 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3933 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3934 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3935 // The movi_edit node has the immediate value already encoded, so we use
3936 // a plain imm0_255 here.
3937 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
3938 (MOVID imm0_255:$shift)>;
3940 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3941 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3942 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3943 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3945 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3946 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3947 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3948 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3950 // EDIT byte mask: 2d
3952 // The movi_edit node has the immediate value already encoded, so we use
3953 // a plain imm0_255 in the pattern
3954 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3955 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3958 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
3961 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3962 // Complexity is added to break a tie with a plain MOVI.
3963 let AddedComplexity = 1 in {
3964 def : Pat<(f32 fpimm0),
3965 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3967 def : Pat<(f64 fpimm0),
3968 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3972 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3973 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3974 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3975 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3977 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3978 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3979 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3980 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3982 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
3983 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
3985 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3986 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3988 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3989 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3990 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3991 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3993 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3994 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3995 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3996 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3998 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3999 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4000 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4001 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4002 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4003 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4004 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4005 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4007 // EDIT per word: 2s & 4s with MSL shifter
4008 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4009 [(set (v2i32 V64:$Rd),
4010 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4011 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4012 [(set (v4i32 V128:$Rd),
4013 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4015 // Per byte: 8b & 16b
4016 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4018 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4019 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4021 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4025 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4026 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4028 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4029 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4030 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4031 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4033 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4034 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4035 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4036 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4038 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4039 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4040 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4041 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4042 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4043 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4044 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4045 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4047 // EDIT per word: 2s & 4s with MSL shifter
4048 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4049 [(set (v2i32 V64:$Rd),
4050 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4051 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4052 [(set (v4i32 V128:$Rd),
4053 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4055 //----------------------------------------------------------------------------
4056 // AdvSIMD indexed element
4057 //----------------------------------------------------------------------------
4059 let neverHasSideEffects = 1 in {
4060 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
4061 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
4064 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4065 // instruction expects the addend first, while the intrinsic expects it last.
4067 // On the other hand, there are quite a few valid combinatorial options due to
4068 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4069 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4070 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4071 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4072 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4074 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4075 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4076 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4077 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4078 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4079 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4080 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4081 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4083 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4084 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4086 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4087 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4088 VectorIndexS:$idx))),
4089 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4090 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4091 (v2f32 (AArch64duplane32
4092 (v4f32 (insert_subvector undef,
4093 (v2f32 (fneg V64:$Rm)),
4095 VectorIndexS:$idx)))),
4096 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4097 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4098 VectorIndexS:$idx)>;
4099 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4100 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4101 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4102 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4104 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4106 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4107 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4108 VectorIndexS:$idx))),
4109 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4110 VectorIndexS:$idx)>;
4111 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4112 (v4f32 (AArch64duplane32
4113 (v4f32 (insert_subvector undef,
4114 (v2f32 (fneg V64:$Rm)),
4116 VectorIndexS:$idx)))),
4117 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4118 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4119 VectorIndexS:$idx)>;
4120 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4121 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4122 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4123 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4125 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4126 // (DUPLANE from 64-bit would be trivial).
4127 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4128 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4129 VectorIndexD:$idx))),
4131 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4132 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4133 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4134 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4135 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4137 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4138 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4139 (vector_extract (v4f32 (fneg V128:$Rm)),
4140 VectorIndexS:$idx))),
4141 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4142 V128:$Rm, VectorIndexS:$idx)>;
4143 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4144 (vector_extract (v2f32 (fneg V64:$Rm)),
4145 VectorIndexS:$idx))),
4146 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4147 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4149 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4150 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4151 (vector_extract (v2f64 (fneg V128:$Rm)),
4152 VectorIndexS:$idx))),
4153 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4154 V128:$Rm, VectorIndexS:$idx)>;
4157 defm : FMLSIndexedAfterNegPatterns<
4158 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4159 defm : FMLSIndexedAfterNegPatterns<
4160 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4162 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4163 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4165 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4166 (FMULv2i32_indexed V64:$Rn,
4167 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4169 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4170 (FMULv4i32_indexed V128:$Rn,
4171 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4173 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4174 (FMULv2i64_indexed V128:$Rn,
4175 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4178 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4179 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4180 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4181 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4182 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4183 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4184 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4185 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4186 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4187 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4188 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4189 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4190 int_aarch64_neon_smull>;
4191 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4192 int_aarch64_neon_sqadd>;
4193 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4194 int_aarch64_neon_sqsub>;
4195 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4196 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4197 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4198 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4199 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4200 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4201 int_aarch64_neon_umull>;
4203 // A scalar sqdmull with the second operand being a vector lane can be
4204 // handled directly with the indexed instruction encoding.
4205 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4206 (vector_extract (v4i32 V128:$Vm),
4207 VectorIndexS:$idx)),
4208 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4210 //----------------------------------------------------------------------------
4211 // AdvSIMD scalar shift instructions
4212 //----------------------------------------------------------------------------
4213 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4214 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4215 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4216 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4217 // Codegen patterns for the above. We don't put these directly on the
4218 // instructions because TableGen's type inference can't handle the truth.
4219 // Having the same base pattern for fp <--> int totally freaks it out.
4220 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4221 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4222 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4223 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4224 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4225 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4226 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4227 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4228 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4230 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4231 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4233 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4234 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4235 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4236 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4237 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4238 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4239 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4240 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4241 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4242 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4244 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4245 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4247 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4249 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4250 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4251 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4252 int_aarch64_neon_sqrshrn>;
4253 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4254 int_aarch64_neon_sqrshrun>;
4255 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4256 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4257 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4258 int_aarch64_neon_sqshrn>;
4259 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4260 int_aarch64_neon_sqshrun>;
4261 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4262 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4263 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4264 TriOpFrag<(add node:$LHS,
4265 (AArch64srshri node:$MHS, node:$RHS))>>;
4266 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4267 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4268 TriOpFrag<(add node:$LHS,
4269 (AArch64vashr node:$MHS, node:$RHS))>>;
4270 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4271 int_aarch64_neon_uqrshrn>;
4272 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4273 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4274 int_aarch64_neon_uqshrn>;
4275 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4276 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4277 TriOpFrag<(add node:$LHS,
4278 (AArch64urshri node:$MHS, node:$RHS))>>;
4279 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4280 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4281 TriOpFrag<(add node:$LHS,
4282 (AArch64vlshr node:$MHS, node:$RHS))>>;
4284 //----------------------------------------------------------------------------
4285 // AdvSIMD vector shift instructions
4286 //----------------------------------------------------------------------------
4287 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4288 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4289 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4290 int_aarch64_neon_vcvtfxs2fp>;
4291 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4292 int_aarch64_neon_rshrn>;
4293 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4294 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4295 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4296 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4297 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4298 (i32 vecshiftL64:$imm))),
4299 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4300 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4301 int_aarch64_neon_sqrshrn>;
4302 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4303 int_aarch64_neon_sqrshrun>;
4304 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4305 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4306 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4307 int_aarch64_neon_sqshrn>;
4308 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4309 int_aarch64_neon_sqshrun>;
4310 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4311 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4312 (i32 vecshiftR64:$imm))),
4313 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4314 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4315 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4316 TriOpFrag<(add node:$LHS,
4317 (AArch64srshri node:$MHS, node:$RHS))> >;
4318 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4319 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4321 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4322 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4323 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4324 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4325 int_aarch64_neon_vcvtfxu2fp>;
4326 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4327 int_aarch64_neon_uqrshrn>;
4328 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4329 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4330 int_aarch64_neon_uqshrn>;
4331 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4332 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4333 TriOpFrag<(add node:$LHS,
4334 (AArch64urshri node:$MHS, node:$RHS))> >;
4335 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4336 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4337 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4338 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4339 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4341 // SHRN patterns for when a logical right shift was used instead of arithmetic
4342 // (the immediate guarantees no sign bits actually end up in the result so it
4344 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4345 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4346 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4347 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4348 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4349 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4351 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4352 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4353 vecshiftR16Narrow:$imm)))),
4354 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4355 V128:$Rn, vecshiftR16Narrow:$imm)>;
4356 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4357 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4358 vecshiftR32Narrow:$imm)))),
4359 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4360 V128:$Rn, vecshiftR32Narrow:$imm)>;
4361 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4362 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4363 vecshiftR64Narrow:$imm)))),
4364 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4365 V128:$Rn, vecshiftR32Narrow:$imm)>;
4367 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4368 // Anyexts are implemented as zexts.
4369 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4370 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4371 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4372 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4373 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4374 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4375 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4376 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4377 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4378 // Also match an extend from the upper half of a 128 bit source register.
4379 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4380 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4381 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4382 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4383 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4384 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4385 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4386 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4387 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4388 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4389 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4390 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4391 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4392 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4393 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4394 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4395 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4396 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4398 // Vector shift sxtl aliases
4399 def : InstAlias<"sxtl.8h $dst, $src1",
4400 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4401 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4402 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4403 def : InstAlias<"sxtl.4s $dst, $src1",
4404 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4405 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4406 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4407 def : InstAlias<"sxtl.2d $dst, $src1",
4408 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4409 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4410 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4412 // Vector shift sxtl2 aliases
4413 def : InstAlias<"sxtl2.8h $dst, $src1",
4414 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4415 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4416 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4417 def : InstAlias<"sxtl2.4s $dst, $src1",
4418 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4419 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4420 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4421 def : InstAlias<"sxtl2.2d $dst, $src1",
4422 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4423 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4424 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4426 // Vector shift uxtl aliases
4427 def : InstAlias<"uxtl.8h $dst, $src1",
4428 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4429 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4430 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4431 def : InstAlias<"uxtl.4s $dst, $src1",
4432 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4433 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4434 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4435 def : InstAlias<"uxtl.2d $dst, $src1",
4436 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4437 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4438 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4440 // Vector shift uxtl2 aliases
4441 def : InstAlias<"uxtl2.8h $dst, $src1",
4442 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4443 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4444 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4445 def : InstAlias<"uxtl2.4s $dst, $src1",
4446 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4447 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4448 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4449 def : InstAlias<"uxtl2.2d $dst, $src1",
4450 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4451 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4452 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4454 // If an integer is about to be converted to a floating point value,
4455 // just load it on the floating point unit.
4456 // These patterns are more complex because floating point loads do not
4457 // support sign extension.
4458 // The sign extension has to be explicitly added and is only supported for
4459 // one step: byte-to-half, half-to-word, word-to-doubleword.
4460 // SCVTF GPR -> FPR is 9 cycles.
4461 // SCVTF FPR -> FPR is 4 cyclces.
4462 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4463 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4464 // and still being faster.
4465 // However, this is not good for code size.
4466 // 8-bits -> float. 2 sizes step-up.
4467 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4468 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4469 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4474 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4480 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4482 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4483 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4484 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4485 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4486 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4487 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4488 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4489 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4491 // 16-bits -> float. 1 size step-up.
4492 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4493 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4494 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4496 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4500 ssub)))>, Requires<[NotForCodeSize]>;
4502 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4503 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4504 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4505 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4506 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4507 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4508 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4509 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4511 // 32-bits to 32-bits are handled in target specific dag combine:
4512 // performIntToFpCombine.
4513 // 64-bits integer to 32-bits floating point, not possible with
4514 // SCVTF on floating point registers (both source and destination
4515 // must have the same size).
4517 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4518 // 8-bits -> double. 3 size step-up: give up.
4519 // 16-bits -> double. 2 size step.
4520 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4521 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4522 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4527 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4533 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4535 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4536 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4537 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4538 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4539 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4540 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4541 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4542 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4543 // 32-bits -> double. 1 size step-up.
4544 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4545 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4546 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4548 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4552 dsub)))>, Requires<[NotForCodeSize]>;
4554 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4555 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4556 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4557 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4558 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4559 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4560 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4561 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4563 // 64-bits -> double are handled in target specific dag combine:
4564 // performIntToFpCombine.
4567 //----------------------------------------------------------------------------
4568 // AdvSIMD Load-Store Structure
4569 //----------------------------------------------------------------------------
4570 defm LD1 : SIMDLd1Multiple<"ld1">;
4571 defm LD2 : SIMDLd2Multiple<"ld2">;
4572 defm LD3 : SIMDLd3Multiple<"ld3">;
4573 defm LD4 : SIMDLd4Multiple<"ld4">;
4575 defm ST1 : SIMDSt1Multiple<"st1">;
4576 defm ST2 : SIMDSt2Multiple<"st2">;
4577 defm ST3 : SIMDSt3Multiple<"st3">;
4578 defm ST4 : SIMDSt4Multiple<"st4">;
4580 class Ld1Pat<ValueType ty, Instruction INST>
4581 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4583 def : Ld1Pat<v16i8, LD1Onev16b>;
4584 def : Ld1Pat<v8i16, LD1Onev8h>;
4585 def : Ld1Pat<v4i32, LD1Onev4s>;
4586 def : Ld1Pat<v2i64, LD1Onev2d>;
4587 def : Ld1Pat<v8i8, LD1Onev8b>;
4588 def : Ld1Pat<v4i16, LD1Onev4h>;
4589 def : Ld1Pat<v2i32, LD1Onev2s>;
4590 def : Ld1Pat<v1i64, LD1Onev1d>;
4592 class St1Pat<ValueType ty, Instruction INST>
4593 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4594 (INST ty:$Vt, GPR64sp:$Rn)>;
4596 def : St1Pat<v16i8, ST1Onev16b>;
4597 def : St1Pat<v8i16, ST1Onev8h>;
4598 def : St1Pat<v4i32, ST1Onev4s>;
4599 def : St1Pat<v2i64, ST1Onev2d>;
4600 def : St1Pat<v8i8, ST1Onev8b>;
4601 def : St1Pat<v4i16, ST1Onev4h>;
4602 def : St1Pat<v2i32, ST1Onev2s>;
4603 def : St1Pat<v1i64, ST1Onev1d>;
4609 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4610 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4611 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4612 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4613 let mayLoad = 1, neverHasSideEffects = 1 in {
4614 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4615 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4616 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4617 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4618 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4619 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4620 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4621 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4622 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4623 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4624 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4625 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4626 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4627 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4628 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4629 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4632 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4633 (LD1Rv8b GPR64sp:$Rn)>;
4634 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4635 (LD1Rv16b GPR64sp:$Rn)>;
4636 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4637 (LD1Rv4h GPR64sp:$Rn)>;
4638 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4639 (LD1Rv8h GPR64sp:$Rn)>;
4640 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4641 (LD1Rv2s GPR64sp:$Rn)>;
4642 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4643 (LD1Rv4s GPR64sp:$Rn)>;
4644 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4645 (LD1Rv2d GPR64sp:$Rn)>;
4646 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4647 (LD1Rv1d GPR64sp:$Rn)>;
4648 // Grab the floating point version too
4649 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4650 (LD1Rv2s GPR64sp:$Rn)>;
4651 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4652 (LD1Rv4s GPR64sp:$Rn)>;
4653 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4654 (LD1Rv2d GPR64sp:$Rn)>;
4655 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4656 (LD1Rv1d GPR64sp:$Rn)>;
4657 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4658 (LD1Rv4h GPR64sp:$Rn)>;
4659 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4660 (LD1Rv8h GPR64sp:$Rn)>;
4662 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4663 ValueType VTy, ValueType STy, Instruction LD1>
4664 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4665 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4666 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4668 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4669 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4670 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4671 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4672 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4673 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4674 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4676 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4677 ValueType VTy, ValueType STy, Instruction LD1>
4678 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4679 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4681 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4682 VecIndex:$idx, GPR64sp:$Rn),
4685 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4686 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4687 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4688 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4689 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4692 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4693 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4694 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4695 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4698 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4699 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4700 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4701 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4703 let AddedComplexity = 15 in
4704 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4705 ValueType VTy, ValueType STy, Instruction ST1>
4707 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4709 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4711 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4712 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4713 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4714 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4715 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4716 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4717 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
4719 let AddedComplexity = 15 in
4720 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4721 ValueType VTy, ValueType STy, Instruction ST1>
4723 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4725 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4726 VecIndex:$idx, GPR64sp:$Rn)>;
4728 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4729 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4730 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4731 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4732 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
4734 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4735 ValueType VTy, ValueType STy, Instruction ST1,
4737 def : Pat<(scalar_store
4738 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4739 GPR64sp:$Rn, offset),
4740 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4741 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4743 def : Pat<(scalar_store
4744 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4745 GPR64sp:$Rn, GPR64:$Rm),
4746 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4747 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4750 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4751 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4753 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4754 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4755 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4756 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4757 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
4759 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4760 ValueType VTy, ValueType STy, Instruction ST1,
4762 def : Pat<(scalar_store
4763 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4764 GPR64sp:$Rn, offset),
4765 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4767 def : Pat<(scalar_store
4768 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4769 GPR64sp:$Rn, GPR64:$Rm),
4770 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4773 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4775 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4777 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4778 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4779 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4780 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4781 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
4783 let mayStore = 1, neverHasSideEffects = 1 in {
4784 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4785 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4786 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4787 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4788 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4789 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4790 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4791 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4792 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4793 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4794 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4795 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4798 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4799 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4800 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4801 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4803 //----------------------------------------------------------------------------
4804 // Crypto extensions
4805 //----------------------------------------------------------------------------
4807 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
4808 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
4809 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
4810 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
4812 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
4813 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
4814 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
4815 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
4816 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
4817 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
4818 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
4820 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
4821 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
4822 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
4824 //----------------------------------------------------------------------------
4826 //----------------------------------------------------------------------------
4827 // FIXME: Like for X86, these should go in their own separate .td file.
4829 // Any instruction that defines a 32-bit result leaves the high half of the
4830 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4831 // be copying from a truncate. But any other 32-bit operation will zero-extend
4833 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4834 def def32 : PatLeaf<(i32 GPR32:$src), [{
4835 return N->getOpcode() != ISD::TRUNCATE &&
4836 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4837 N->getOpcode() != ISD::CopyFromReg;
4840 // In the case of a 32-bit def that is known to implicitly zero-extend,
4841 // we can use a SUBREG_TO_REG.
4842 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4844 // For an anyext, we don't care what the high bits are, so we can perform an
4845 // INSERT_SUBREF into an IMPLICIT_DEF.
4846 def : Pat<(i64 (anyext GPR32:$src)),
4847 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4849 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4850 // instruction (UBFM) on the enclosing super-reg.
4851 def : Pat<(i64 (zext GPR32:$src)),
4852 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4854 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4855 // containing super-reg.
4856 def : Pat<(i64 (sext GPR32:$src)),
4857 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4858 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4859 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4860 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4861 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4862 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4863 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4864 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4866 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4867 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4868 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4869 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4870 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4871 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4873 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4874 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4875 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4876 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4877 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4878 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4880 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4881 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4882 (i64 (i64shift_a imm0_63:$imm)),
4883 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4885 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4886 // AddedComplexity for the following patterns since we want to match sext + sra
4887 // patterns before we attempt to match a single sra node.
4888 let AddedComplexity = 20 in {
4889 // We support all sext + sra combinations which preserve at least one bit of the
4890 // original value which is to be sign extended. E.g. we support shifts up to
4892 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4893 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4894 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4895 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4897 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4898 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4899 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4900 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4902 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4903 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4904 (i64 imm0_31:$imm), 31)>;
4905 } // AddedComplexity = 20
4907 // To truncate, we can simply extract from a subregister.
4908 def : Pat<(i32 (trunc GPR64sp:$src)),
4909 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4911 // __builtin_trap() uses the BRK instruction on AArch64.
4912 def : Pat<(trap), (BRK 1)>;
4914 // Conversions within AdvSIMD types in the same register size are free.
4915 // But because we need a consistent lane ordering, in big endian many
4916 // conversions require one or more REV instructions.
4918 // Consider a simple memory load followed by a bitconvert then a store.
4920 // v1 = BITCAST v2i32 v0 to v4i16
4923 // In big endian mode every memory access has an implicit byte swap. LDR and
4924 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
4925 // is, they treat the vector as a sequence of elements to be byte-swapped.
4926 // The two pairs of instructions are fundamentally incompatible. We've decided
4927 // to use LD1/ST1 only to simplify compiler implementation.
4929 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
4930 // the original code sequence:
4932 // v1 = REV v2i32 (implicit)
4933 // v2 = BITCAST v2i32 v1 to v4i16
4934 // v3 = REV v4i16 v2 (implicit)
4937 // But this is now broken - the value stored is different to the value loaded
4938 // due to lane reordering. To fix this, on every BITCAST we must perform two
4941 // v1 = REV v2i32 (implicit)
4943 // v3 = BITCAST v2i32 v2 to v4i16
4945 // v5 = REV v4i16 v4 (implicit)
4948 // This means an extra two instructions, but actually in most cases the two REV
4949 // instructions can be combined into one. For example:
4950 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
4952 // There is also no 128-bit REV instruction. This must be synthesized with an
4955 // Most bitconverts require some sort of conversion. The only exceptions are:
4956 // a) Identity conversions - vNfX <-> vNiX
4957 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
4960 let Predicates = [IsLE] in {
4961 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4962 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4963 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4964 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4965 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4967 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4968 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4969 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4970 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4971 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4972 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4973 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
4974 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4975 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4976 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4977 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4978 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4980 let Predicates = [IsBE] in {
4981 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
4982 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4983 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
4984 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4985 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
4986 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4987 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
4988 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4989 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
4990 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4992 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4993 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4994 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4995 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4996 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4997 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4998 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
4999 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5000 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5001 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5003 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5004 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5005 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5006 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5007 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5008 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5009 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5010 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5011 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5013 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5014 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5015 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5016 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5017 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5018 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5019 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5020 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5021 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5022 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5024 let Predicates = [IsLE] in {
5025 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5026 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5027 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5028 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5029 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5031 let Predicates = [IsBE] in {
5032 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5033 (v1i64 (REV64v2i32 FPR64:$src))>;
5034 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5035 (v1i64 (REV64v4i16 FPR64:$src))>;
5036 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5037 (v1i64 (REV64v8i8 FPR64:$src))>;
5038 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5039 (v1i64 (REV64v4i16 FPR64:$src))>;
5040 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5041 (v1i64 (REV64v2i32 FPR64:$src))>;
5043 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5044 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5046 let Predicates = [IsLE] in {
5047 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5048 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5049 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5050 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5051 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5052 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5054 let Predicates = [IsBE] in {
5055 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5056 (v2i32 (REV64v2i32 FPR64:$src))>;
5057 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5058 (v2i32 (REV32v4i16 FPR64:$src))>;
5059 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5060 (v2i32 (REV32v8i8 FPR64:$src))>;
5061 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5062 (v2i32 (REV64v2i32 FPR64:$src))>;
5063 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5064 (v2i32 (REV64v2i32 FPR64:$src))>;
5065 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5066 (v2i32 (REV64v4i16 FPR64:$src))>;
5068 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5070 let Predicates = [IsLE] in {
5071 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5072 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5073 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5074 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5075 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5076 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5077 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5079 let Predicates = [IsBE] in {
5080 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5081 (v4i16 (REV64v4i16 FPR64:$src))>;
5082 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5083 (v4i16 (REV32v4i16 FPR64:$src))>;
5084 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5085 (v4i16 (REV16v8i8 FPR64:$src))>;
5086 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5087 (v4i16 (REV64v4i16 FPR64:$src))>;
5088 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5089 (v4i16 (REV32v4i16 FPR64:$src))>;
5090 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5091 (v4i16 (REV32v4i16 FPR64:$src))>;
5092 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5093 (v4i16 (REV64v4i16 FPR64:$src))>;
5096 let Predicates = [IsLE] in {
5097 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5098 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5099 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5100 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5101 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5102 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5103 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5105 let Predicates = [IsBE] in {
5106 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5107 (v4f16 (REV64v4i16 FPR64:$src))>;
5108 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5109 (v4f16 (REV64v4i16 FPR64:$src))>;
5110 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5111 (v4f16 (REV64v4i16 FPR64:$src))>;
5112 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5113 (v4f16 (REV16v8i8 FPR64:$src))>;
5114 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5115 (v4f16 (REV64v4i16 FPR64:$src))>;
5116 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5117 (v4f16 (REV64v4i16 FPR64:$src))>;
5118 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5119 (v4f16 (REV64v4i16 FPR64:$src))>;
5124 let Predicates = [IsLE] in {
5125 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5126 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5127 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5128 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5129 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5130 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5131 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5133 let Predicates = [IsBE] in {
5134 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5135 (v8i8 (REV64v8i8 FPR64:$src))>;
5136 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5137 (v8i8 (REV32v8i8 FPR64:$src))>;
5138 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5139 (v8i8 (REV16v8i8 FPR64:$src))>;
5140 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5141 (v8i8 (REV64v8i8 FPR64:$src))>;
5142 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5143 (v8i8 (REV32v8i8 FPR64:$src))>;
5144 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5145 (v8i8 (REV64v8i8 FPR64:$src))>;
5146 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5147 (v8i8 (REV16v8i8 FPR64:$src))>;
5150 let Predicates = [IsLE] in {
5151 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5152 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5153 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5154 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5155 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5157 let Predicates = [IsBE] in {
5158 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5159 (f64 (REV64v2i32 FPR64:$src))>;
5160 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5161 (f64 (REV64v4i16 FPR64:$src))>;
5162 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5163 (f64 (REV64v2i32 FPR64:$src))>;
5164 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5165 (f64 (REV64v8i8 FPR64:$src))>;
5166 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5167 (f64 (REV64v4i16 FPR64:$src))>;
5169 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5170 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5172 let Predicates = [IsLE] in {
5173 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5174 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5175 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5176 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5177 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5179 let Predicates = [IsBE] in {
5180 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5181 (v1f64 (REV64v2i32 FPR64:$src))>;
5182 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5183 (v1f64 (REV64v4i16 FPR64:$src))>;
5184 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5185 (v1f64 (REV64v8i8 FPR64:$src))>;
5186 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5187 (v1f64 (REV64v2i32 FPR64:$src))>;
5188 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5189 (v1f64 (REV64v4i16 FPR64:$src))>;
5191 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5192 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5194 let Predicates = [IsLE] in {
5195 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5196 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5197 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5198 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5199 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5200 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5202 let Predicates = [IsBE] in {
5203 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5204 (v2f32 (REV64v2i32 FPR64:$src))>;
5205 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5206 (v2f32 (REV32v4i16 FPR64:$src))>;
5207 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5208 (v2f32 (REV32v8i8 FPR64:$src))>;
5209 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5210 (v2f32 (REV64v2i32 FPR64:$src))>;
5211 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5212 (v2f32 (REV64v2i32 FPR64:$src))>;
5213 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5214 (v2f32 (REV64v4i16 FPR64:$src))>;
5216 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5218 let Predicates = [IsLE] in {
5219 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5220 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5221 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5222 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5223 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5224 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5225 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5227 let Predicates = [IsBE] in {
5228 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5229 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5230 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5231 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5232 (REV64v4i32 FPR128:$src), (i32 8)))>;
5233 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5234 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5235 (REV64v8i16 FPR128:$src), (i32 8)))>;
5236 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5237 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5238 (REV64v8i16 FPR128:$src), (i32 8)))>;
5239 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5240 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5241 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5242 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5243 (REV64v4i32 FPR128:$src), (i32 8)))>;
5244 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5245 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5246 (REV64v16i8 FPR128:$src), (i32 8)))>;
5249 let Predicates = [IsLE] in {
5250 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5251 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5252 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5253 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5254 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5255 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5257 let Predicates = [IsBE] in {
5258 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5259 (v2f64 (EXTv16i8 FPR128:$src,
5260 FPR128:$src, (i32 8)))>;
5261 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5262 (v2f64 (REV64v4i32 FPR128:$src))>;
5263 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5264 (v2f64 (REV64v8i16 FPR128:$src))>;
5265 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5266 (v2f64 (REV64v8i16 FPR128:$src))>;
5267 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5268 (v2f64 (REV64v16i8 FPR128:$src))>;
5269 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5270 (v2f64 (REV64v4i32 FPR128:$src))>;
5272 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5274 let Predicates = [IsLE] in {
5275 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5276 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5277 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5278 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5279 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5280 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5282 let Predicates = [IsBE] in {
5283 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5284 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5285 (REV64v4i32 FPR128:$src), (i32 8)))>;
5286 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5287 (v4f32 (REV32v8i16 FPR128:$src))>;
5288 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5289 (v4f32 (REV32v8i16 FPR128:$src))>;
5290 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5291 (v4f32 (REV32v16i8 FPR128:$src))>;
5292 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5293 (v4f32 (REV64v4i32 FPR128:$src))>;
5294 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5295 (v4f32 (REV64v4i32 FPR128:$src))>;
5297 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5299 let Predicates = [IsLE] in {
5300 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5301 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5302 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5303 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5304 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5305 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5307 let Predicates = [IsBE] in {
5308 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5309 (v2i64 (EXTv16i8 FPR128:$src,
5310 FPR128:$src, (i32 8)))>;
5311 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5312 (v2i64 (REV64v4i32 FPR128:$src))>;
5313 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5314 (v2i64 (REV64v8i16 FPR128:$src))>;
5315 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5316 (v2i64 (REV64v16i8 FPR128:$src))>;
5317 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5318 (v2i64 (REV64v4i32 FPR128:$src))>;
5319 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5320 (v2i64 (REV64v8i16 FPR128:$src))>;
5322 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5324 let Predicates = [IsLE] in {
5325 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5326 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5327 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5328 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5329 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5330 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5332 let Predicates = [IsBE] in {
5333 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5334 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5335 (REV64v4i32 FPR128:$src),
5337 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5338 (v4i32 (REV64v4i32 FPR128:$src))>;
5339 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5340 (v4i32 (REV32v8i16 FPR128:$src))>;
5341 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5342 (v4i32 (REV32v16i8 FPR128:$src))>;
5343 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5344 (v4i32 (REV64v4i32 FPR128:$src))>;
5345 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5346 (v4i32 (REV32v8i16 FPR128:$src))>;
5348 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5350 let Predicates = [IsLE] in {
5351 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5352 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5353 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5354 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5355 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5356 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5357 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5359 let Predicates = [IsBE] in {
5360 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5361 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5362 (REV64v8i16 FPR128:$src),
5364 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5365 (v8i16 (REV64v8i16 FPR128:$src))>;
5366 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5367 (v8i16 (REV32v8i16 FPR128:$src))>;
5368 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5369 (v8i16 (REV16v16i8 FPR128:$src))>;
5370 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5371 (v8i16 (REV64v8i16 FPR128:$src))>;
5372 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5373 (v8i16 (REV32v8i16 FPR128:$src))>;
5374 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5375 (v8i16 (REV32v8i16 FPR128:$src))>;
5378 let Predicates = [IsLE] in {
5379 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5380 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5381 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5382 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5383 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5384 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5385 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5387 let Predicates = [IsBE] in {
5388 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5389 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5390 (REV64v8i16 FPR128:$src),
5392 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5393 (v8f16 (REV64v8i16 FPR128:$src))>;
5394 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5395 (v8f16 (REV32v8i16 FPR128:$src))>;
5396 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5397 (v8f16 (REV64v8i16 FPR128:$src))>;
5398 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5399 (v8f16 (REV16v16i8 FPR128:$src))>;
5400 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5401 (v8f16 (REV64v8i16 FPR128:$src))>;
5402 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5403 (v8f16 (REV32v8i16 FPR128:$src))>;
5406 let Predicates = [IsLE] in {
5407 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5408 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5409 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5410 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5411 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5412 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5413 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5415 let Predicates = [IsBE] in {
5416 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5417 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5418 (REV64v16i8 FPR128:$src),
5420 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5421 (v16i8 (REV64v16i8 FPR128:$src))>;
5422 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5423 (v16i8 (REV32v16i8 FPR128:$src))>;
5424 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5425 (v16i8 (REV16v16i8 FPR128:$src))>;
5426 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5427 (v16i8 (REV64v16i8 FPR128:$src))>;
5428 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5429 (v16i8 (REV32v16i8 FPR128:$src))>;
5430 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5431 (v16i8 (REV16v16i8 FPR128:$src))>;
5434 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5435 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5436 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5437 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5438 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5439 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5440 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5441 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5443 // A 64-bit subvector insert to the first 128-bit vector position
5444 // is a subregister copy that needs no instruction.
5445 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5446 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5447 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5448 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5449 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5450 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5451 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5452 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5453 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5454 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5455 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5456 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5457 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5458 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5460 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5462 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5463 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5464 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5465 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5466 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5467 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5468 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5469 // so we match on v4f32 here, not v2f32. This will also catch adding
5470 // the low two lanes of a true v4f32 vector.
5471 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5472 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5473 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5475 // Scalar 64-bit shifts in FPR64 registers.
5476 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5477 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5478 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5479 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5480 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5481 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5482 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5483 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5485 // Tail call return handling. These are all compiler pseudo-instructions,
5486 // so no encoding information or anything like that.
5487 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5488 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5489 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5492 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5493 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5494 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5495 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5496 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5497 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5499 include "AArch64InstrAtomics.td"