1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
18 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
19 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
20 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
21 def HasNEON : Predicate<"Subtarget->hasNEON()">,
22 AssemblerPredicate<"FeatureNEON", "neon">;
23 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
24 AssemblerPredicate<"FeatureCrypto", "crypto">;
25 def HasCRC : Predicate<"Subtarget->hasCRC()">,
26 AssemblerPredicate<"FeatureCRC", "crc">;
27 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
28 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
29 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
31 //===----------------------------------------------------------------------===//
32 // AArch64-specific DAG Nodes.
35 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
36 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
39 SDTCisInt<0>, SDTCisVT<1, i32>]>;
41 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
42 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
48 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
49 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
56 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
59 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
60 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
61 SDTCisVT<2, OtherVT>]>;
64 def SDT_AArch64CSel : SDTypeProfile<1, 4,
69 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
72 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
73 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
74 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
77 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
78 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
79 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
80 SDTCisInt<2>, SDTCisInt<3>]>;
81 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
82 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
83 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
84 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
86 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
87 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
88 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
89 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
91 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
94 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
95 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
97 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
99 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
102 // Generates the general dynamic sequences, i.e.
103 // adrp x0, :tlsdesc:var
104 // ldr x1, [x0, #:tlsdesc_lo12:var]
105 // add x0, x0, #:tlsdesc_lo12:var
109 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
110 // number of operands (the variable)
111 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
114 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
115 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
116 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
117 SDTCisSameAs<1, 4>]>;
121 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
122 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
123 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
124 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
125 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
128 SDCallSeqEnd<[ SDTCisVT<0, i32>,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
131 def AArch64call : SDNode<"AArch64ISD::CALL",
132 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
135 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
137 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
139 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
141 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
143 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
147 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
148 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
149 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
150 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
151 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
153 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
154 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
155 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
157 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
158 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
160 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
161 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
163 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
165 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
167 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
168 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
170 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
171 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
172 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
173 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
174 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
176 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
177 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
178 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
179 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
180 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
181 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
183 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
184 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
185 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
186 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
187 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
188 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
189 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
191 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
192 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
193 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
194 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
196 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
197 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
198 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
199 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
200 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
201 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
202 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
203 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
205 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
206 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
207 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
209 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
210 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
211 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
212 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
213 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
215 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
216 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
217 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
219 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
220 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
221 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
222 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
223 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
224 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
225 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
227 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
228 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
229 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
230 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
231 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
233 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
234 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
236 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
238 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
239 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
241 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
242 [SDNPHasChain, SDNPSideEffect]>;
244 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
245 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
247 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
248 SDT_AArch64TLSDescCallSeq,
249 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
253 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
254 SDT_AArch64WrapperLarge>;
256 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
258 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
259 SDTCisSameAs<1, 2>]>;
260 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
261 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
263 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
264 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
265 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
266 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
267 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
268 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
270 //===----------------------------------------------------------------------===//
272 //===----------------------------------------------------------------------===//
274 // AArch64 Instruction Predicate Definitions.
276 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
277 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
278 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
279 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
280 def ForCodeSize : Predicate<"ForCodeSize">;
281 def NotForCodeSize : Predicate<"!ForCodeSize">;
283 include "AArch64InstrFormats.td"
285 //===----------------------------------------------------------------------===//
287 //===----------------------------------------------------------------------===//
288 // Miscellaneous instructions.
289 //===----------------------------------------------------------------------===//
291 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
292 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
293 [(AArch64callseq_start timm:$amt)]>;
294 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
295 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
296 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
298 let isReMaterializable = 1, isCodeGenOnly = 1 in {
299 // FIXME: The following pseudo instructions are only needed because remat
300 // cannot handle multiple instructions. When that changes, they can be
301 // removed, along with the AArch64Wrapper node.
303 let AddedComplexity = 10 in
304 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
305 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
308 // The MOVaddr instruction should match only when the add is not folded
309 // into a load or store address.
311 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
312 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
313 tglobaladdr:$low))]>,
314 Sched<[WriteAdrAdr]>;
316 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
317 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
319 Sched<[WriteAdrAdr]>;
321 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
322 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
324 Sched<[WriteAdrAdr]>;
326 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
327 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
328 tblockaddress:$low))]>,
329 Sched<[WriteAdrAdr]>;
331 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
332 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
333 tglobaltlsaddr:$low))]>,
334 Sched<[WriteAdrAdr]>;
336 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
337 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
338 texternalsym:$low))]>,
339 Sched<[WriteAdrAdr]>;
341 } // isReMaterializable, isCodeGenOnly
343 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
344 (LOADgot tglobaltlsaddr:$addr)>;
346 def : Pat<(AArch64LOADgot texternalsym:$addr),
347 (LOADgot texternalsym:$addr)>;
349 def : Pat<(AArch64LOADgot tconstpool:$addr),
350 (LOADgot tconstpool:$addr)>;
352 //===----------------------------------------------------------------------===//
353 // System instructions.
354 //===----------------------------------------------------------------------===//
356 def HINT : HintI<"hint">;
357 def : InstAlias<"nop", (HINT 0b000)>;
358 def : InstAlias<"yield",(HINT 0b001)>;
359 def : InstAlias<"wfe", (HINT 0b010)>;
360 def : InstAlias<"wfi", (HINT 0b011)>;
361 def : InstAlias<"sev", (HINT 0b100)>;
362 def : InstAlias<"sevl", (HINT 0b101)>;
364 // As far as LLVM is concerned this writes to the system's exclusive monitors.
365 let mayLoad = 1, mayStore = 1 in
366 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
368 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
369 // model patterns with sufficiently fine granularity.
370 let mayLoad = ?, mayStore = ? in {
371 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
372 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
374 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
375 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
377 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
378 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
381 def : InstAlias<"clrex", (CLREX 0xf)>;
382 def : InstAlias<"isb", (ISB 0xf)>;
386 def MSRpstate: MSRpstateI;
388 // The thread pointer (on Linux, at least, where this has been implemented) is
390 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
392 // Generic system instructions
393 def SYSxt : SystemXtI<0, "sys">;
394 def SYSLxt : SystemLXtI<1, "sysl">;
396 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
397 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
398 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
400 //===----------------------------------------------------------------------===//
401 // Move immediate instructions.
402 //===----------------------------------------------------------------------===//
404 defm MOVK : InsertImmediate<0b11, "movk">;
405 defm MOVN : MoveImmediate<0b00, "movn">;
407 let PostEncoderMethod = "fixMOVZ" in
408 defm MOVZ : MoveImmediate<0b10, "movz">;
410 // First group of aliases covers an implicit "lsl #0".
411 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
412 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
413 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
414 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
415 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
416 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
418 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
419 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
420 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
421 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
422 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
424 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
425 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
426 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
427 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
429 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
430 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
431 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
432 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
434 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
435 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
437 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
438 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
440 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
441 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
443 // Final group of aliases covers true "mov $Rd, $imm" cases.
444 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
445 int width, int shift> {
446 def _asmoperand : AsmOperandClass {
447 let Name = basename # width # "_lsl" # shift # "MovAlias";
448 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
450 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
453 def _movimm : Operand<i32> {
454 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
457 def : InstAlias<"mov $Rd, $imm",
458 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
461 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
462 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
464 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
465 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
466 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
467 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
469 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
470 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
472 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
473 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
474 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
475 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
477 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
478 isAsCheapAsAMove = 1 in {
479 // FIXME: The following pseudo instructions are only needed because remat
480 // cannot handle multiple instructions. When that changes, we can select
481 // directly to the real instructions and get rid of these pseudos.
484 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
485 [(set GPR32:$dst, imm:$src)]>,
488 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
489 [(set GPR64:$dst, imm:$src)]>,
491 } // isReMaterializable, isCodeGenOnly
493 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
494 // eventual expansion code fewer bits to worry about getting right. Marshalling
495 // the types is a little tricky though:
496 def i64imm_32bit : ImmLeaf<i64, [{
497 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
500 def trunc_imm : SDNodeXForm<imm, [{
501 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32);
504 def : Pat<(i64 i64imm_32bit:$src),
505 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
507 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
508 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
509 return CurDAG->getTargetConstant(
510 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
513 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
514 return CurDAG->getTargetConstant(
515 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
519 def : Pat<(f32 fpimm:$in),
520 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
521 def : Pat<(f64 fpimm:$in),
522 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
525 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
527 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
528 tglobaladdr:$g1, tglobaladdr:$g0),
529 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
530 tglobaladdr:$g2, 32),
531 tglobaladdr:$g1, 16),
532 tglobaladdr:$g0, 0)>;
534 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
535 tblockaddress:$g1, tblockaddress:$g0),
536 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
537 tblockaddress:$g2, 32),
538 tblockaddress:$g1, 16),
539 tblockaddress:$g0, 0)>;
541 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
542 tconstpool:$g1, tconstpool:$g0),
543 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
548 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
549 tjumptable:$g1, tjumptable:$g0),
550 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
556 //===----------------------------------------------------------------------===//
557 // Arithmetic instructions.
558 //===----------------------------------------------------------------------===//
560 // Add/subtract with carry.
561 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
562 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
564 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
565 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
566 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
567 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
570 defm ADD : AddSub<0, "add", add>;
571 defm SUB : AddSub<1, "sub">;
573 def : InstAlias<"mov $dst, $src",
574 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
575 def : InstAlias<"mov $dst, $src",
576 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
577 def : InstAlias<"mov $dst, $src",
578 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
579 def : InstAlias<"mov $dst, $src",
580 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
582 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
583 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
585 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
586 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
587 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
588 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
589 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
590 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
591 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
592 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
593 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
594 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
595 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
596 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
597 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
598 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
599 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
600 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
601 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
603 // Because of the immediate format for add/sub-imm instructions, the
604 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
605 // These patterns capture that transformation.
606 let AddedComplexity = 1 in {
607 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
608 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
609 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
610 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
611 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
612 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
613 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
614 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
617 // Because of the immediate format for add/sub-imm instructions, the
618 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
619 // These patterns capture that transformation.
620 let AddedComplexity = 1 in {
621 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
622 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
623 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
624 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
625 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
626 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
627 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
628 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
631 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
632 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
633 def : InstAlias<"neg $dst, $src$shift",
634 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
635 def : InstAlias<"neg $dst, $src$shift",
636 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
638 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
639 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
640 def : InstAlias<"negs $dst, $src$shift",
641 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
642 def : InstAlias<"negs $dst, $src$shift",
643 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
646 // Unsigned/Signed divide
647 defm UDIV : Div<0, "udiv", udiv>;
648 defm SDIV : Div<1, "sdiv", sdiv>;
649 let isCodeGenOnly = 1 in {
650 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
651 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
655 defm ASRV : Shift<0b10, "asr", sra>;
656 defm LSLV : Shift<0b00, "lsl", shl>;
657 defm LSRV : Shift<0b01, "lsr", srl>;
658 defm RORV : Shift<0b11, "ror", rotr>;
660 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
661 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
662 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
663 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
664 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
665 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
666 def : ShiftAlias<"rorv", RORVWr, GPR32>;
667 def : ShiftAlias<"rorv", RORVXr, GPR64>;
670 let AddedComplexity = 7 in {
671 defm MADD : MulAccum<0, "madd", add>;
672 defm MSUB : MulAccum<1, "msub", sub>;
674 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
675 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
676 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
677 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
679 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
680 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
681 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
682 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
683 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
684 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
685 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
686 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
687 } // AddedComplexity = 7
689 let AddedComplexity = 5 in {
690 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
691 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
692 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
693 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
695 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
696 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
697 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
698 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
700 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
701 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
702 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
703 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
704 } // AddedComplexity = 5
706 def : MulAccumWAlias<"mul", MADDWrrr>;
707 def : MulAccumXAlias<"mul", MADDXrrr>;
708 def : MulAccumWAlias<"mneg", MSUBWrrr>;
709 def : MulAccumXAlias<"mneg", MSUBXrrr>;
710 def : WideMulAccumAlias<"smull", SMADDLrrr>;
711 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
712 def : WideMulAccumAlias<"umull", UMADDLrrr>;
713 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
716 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
717 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
720 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
721 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
722 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
723 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
725 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
726 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
727 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
728 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
731 defm CAS : CompareAndSwap<0, 0, "">;
732 defm CASA : CompareAndSwap<1, 0, "a">;
733 defm CASL : CompareAndSwap<0, 1, "l">;
734 defm CASAL : CompareAndSwap<1, 1, "al">;
737 defm CASP : CompareAndSwapPair<0, 0, "">;
738 defm CASPA : CompareAndSwapPair<1, 0, "a">;
739 defm CASPL : CompareAndSwapPair<0, 1, "l">;
740 defm CASPAL : CompareAndSwapPair<1, 1, "al">;
743 defm SWP : Swap<0, 0, "">;
744 defm SWPA : Swap<1, 0, "a">;
745 defm SWPL : Swap<0, 1, "l">;
746 defm SWPAL : Swap<1, 1, "al">;
748 // v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)
749 defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
750 defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
751 defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;
752 defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;
754 defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">;
755 defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">;
756 defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">;
757 defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">;
759 defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">;
760 defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">;
761 defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">;
762 defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">;
764 defm LDSET : LDOPregister<0b011, "set", 0, 0, "">;
765 defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">;
766 defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">;
767 defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">;
769 defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">;
770 defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">;
771 defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;
772 defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;
774 defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;
775 defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;
776 defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;
777 defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;
779 defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">;
780 defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">;
781 defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">;
782 defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">;
784 defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">;
785 defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">;
786 defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">;
787 defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">;
789 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
790 defm : STOPregister<"stadd","LDADD">; // STADDx
791 defm : STOPregister<"stclr","LDCLR">; // STCLRx
792 defm : STOPregister<"steor","LDEOR">; // STEORx
793 defm : STOPregister<"stset","LDSET">; // STSETx
794 defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx
795 defm : STOPregister<"stsmin","LDSMIN">;// STSMINx
796 defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
797 defm : STOPregister<"stumin","LDUMIN">;// STUMINx
799 //===----------------------------------------------------------------------===//
800 // Logical instructions.
801 //===----------------------------------------------------------------------===//
804 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
805 defm AND : LogicalImm<0b00, "and", and, "bic">;
806 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
807 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
809 // FIXME: these aliases *are* canonical sometimes (when movz can't be
810 // used). Actually, it seems to be working right now, but putting logical_immXX
811 // here is a bit dodgy on the AsmParser side too.
812 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
813 logical_imm32:$imm), 0>;
814 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
815 logical_imm64:$imm), 0>;
819 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
820 defm BICS : LogicalRegS<0b11, 1, "bics",
821 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
822 defm AND : LogicalReg<0b00, 0, "and", and>;
823 defm BIC : LogicalReg<0b00, 1, "bic",
824 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
825 defm EON : LogicalReg<0b10, 1, "eon",
826 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
827 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
828 defm ORN : LogicalReg<0b01, 1, "orn",
829 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
830 defm ORR : LogicalReg<0b01, 0, "orr", or>;
832 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
833 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
835 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
836 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
838 def : InstAlias<"mvn $Wd, $Wm$sh",
839 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
840 def : InstAlias<"mvn $Xd, $Xm$sh",
841 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
843 def : InstAlias<"tst $src1, $src2",
844 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
845 def : InstAlias<"tst $src1, $src2",
846 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
848 def : InstAlias<"tst $src1, $src2",
849 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
850 def : InstAlias<"tst $src1, $src2",
851 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
853 def : InstAlias<"tst $src1, $src2$sh",
854 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
855 def : InstAlias<"tst $src1, $src2$sh",
856 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
859 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
860 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
863 //===----------------------------------------------------------------------===//
864 // One operand data processing instructions.
865 //===----------------------------------------------------------------------===//
867 defm CLS : OneOperandData<0b101, "cls">;
868 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
869 defm RBIT : OneOperandData<0b000, "rbit">;
871 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
872 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
874 def REV16Wr : OneWRegData<0b001, "rev16",
875 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
876 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
878 def : Pat<(cttz GPR32:$Rn),
879 (CLZWr (RBITWr GPR32:$Rn))>;
880 def : Pat<(cttz GPR64:$Rn),
881 (CLZXr (RBITXr GPR64:$Rn))>;
882 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
885 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
889 // Unlike the other one operand instructions, the instructions with the "rev"
890 // mnemonic do *not* just different in the size bit, but actually use different
891 // opcode bits for the different sizes.
892 def REVWr : OneWRegData<0b010, "rev", bswap>;
893 def REVXr : OneXRegData<0b011, "rev", bswap>;
894 def REV32Xr : OneXRegData<0b010, "rev32",
895 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
897 // The bswap commutes with the rotr so we want a pattern for both possible
899 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
900 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
902 //===----------------------------------------------------------------------===//
903 // Bitfield immediate extraction instruction.
904 //===----------------------------------------------------------------------===//
905 let hasSideEffects = 0 in
906 defm EXTR : ExtractImm<"extr">;
907 def : InstAlias<"ror $dst, $src, $shift",
908 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
909 def : InstAlias<"ror $dst, $src, $shift",
910 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
912 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
913 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
914 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
915 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
917 //===----------------------------------------------------------------------===//
918 // Other bitfield immediate instructions.
919 //===----------------------------------------------------------------------===//
920 let hasSideEffects = 0 in {
921 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
922 defm SBFM : BitfieldImm<0b00, "sbfm">;
923 defm UBFM : BitfieldImm<0b10, "ubfm">;
926 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
927 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
928 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
931 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
932 uint64_t enc = 31 - N->getZExtValue();
933 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
936 // min(7, 31 - shift_amt)
937 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
938 uint64_t enc = 31 - N->getZExtValue();
939 enc = enc > 7 ? 7 : enc;
940 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
943 // min(15, 31 - shift_amt)
944 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
945 uint64_t enc = 31 - N->getZExtValue();
946 enc = enc > 15 ? 15 : enc;
947 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
950 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
951 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
952 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
955 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
956 uint64_t enc = 63 - N->getZExtValue();
957 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
960 // min(7, 63 - shift_amt)
961 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
962 uint64_t enc = 63 - N->getZExtValue();
963 enc = enc > 7 ? 7 : enc;
964 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
967 // min(15, 63 - shift_amt)
968 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
969 uint64_t enc = 63 - N->getZExtValue();
970 enc = enc > 15 ? 15 : enc;
971 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
974 // min(31, 63 - shift_amt)
975 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
976 uint64_t enc = 63 - N->getZExtValue();
977 enc = enc > 31 ? 31 : enc;
978 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
981 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
982 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
983 (i64 (i32shift_b imm0_31:$imm)))>;
984 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
985 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
986 (i64 (i64shift_b imm0_63:$imm)))>;
988 let AddedComplexity = 10 in {
989 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
990 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
991 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
992 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
995 def : InstAlias<"asr $dst, $src, $shift",
996 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
997 def : InstAlias<"asr $dst, $src, $shift",
998 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
999 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1000 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1001 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1002 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1003 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1005 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
1006 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1007 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
1008 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1010 def : InstAlias<"lsr $dst, $src, $shift",
1011 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1012 def : InstAlias<"lsr $dst, $src, $shift",
1013 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1014 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1015 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1016 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1017 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1018 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1020 //===----------------------------------------------------------------------===//
1021 // Conditionally set flags instructions.
1022 //===----------------------------------------------------------------------===//
1023 defm CCMN : CondSetFlagsImm<0, "ccmn">;
1024 defm CCMP : CondSetFlagsImm<1, "ccmp">;
1026 defm CCMN : CondSetFlagsReg<0, "ccmn">;
1027 defm CCMP : CondSetFlagsReg<1, "ccmp">;
1029 //===----------------------------------------------------------------------===//
1030 // Conditional select instructions.
1031 //===----------------------------------------------------------------------===//
1032 defm CSEL : CondSelect<0, 0b00, "csel">;
1034 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
1035 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1036 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1037 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1039 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1040 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1041 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1042 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1043 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1044 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1045 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1046 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1047 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1048 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1049 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1050 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1052 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
1053 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
1054 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
1055 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
1056 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
1057 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
1058 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
1059 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
1061 // The inverse of the condition code from the alias instruction is what is used
1062 // in the aliased instruction. The parser all ready inverts the condition code
1063 // for these aliases.
1064 def : InstAlias<"cset $dst, $cc",
1065 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1066 def : InstAlias<"cset $dst, $cc",
1067 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1069 def : InstAlias<"csetm $dst, $cc",
1070 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1071 def : InstAlias<"csetm $dst, $cc",
1072 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1074 def : InstAlias<"cinc $dst, $src, $cc",
1075 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1076 def : InstAlias<"cinc $dst, $src, $cc",
1077 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1079 def : InstAlias<"cinv $dst, $src, $cc",
1080 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1081 def : InstAlias<"cinv $dst, $src, $cc",
1082 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1084 def : InstAlias<"cneg $dst, $src, $cc",
1085 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1086 def : InstAlias<"cneg $dst, $src, $cc",
1087 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1089 //===----------------------------------------------------------------------===//
1090 // PC-relative instructions.
1091 //===----------------------------------------------------------------------===//
1092 let isReMaterializable = 1 in {
1093 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1094 def ADR : ADRI<0, "adr", adrlabel, []>;
1095 } // hasSideEffects = 0
1097 def ADRP : ADRI<1, "adrp", adrplabel,
1098 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1099 } // isReMaterializable = 1
1101 // page address of a constant pool entry, block address
1102 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1103 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1105 //===----------------------------------------------------------------------===//
1106 // Unconditional branch (register) instructions.
1107 //===----------------------------------------------------------------------===//
1109 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1110 def RET : BranchReg<0b0010, "ret", []>;
1111 def DRPS : SpecialReturn<0b0101, "drps">;
1112 def ERET : SpecialReturn<0b0100, "eret">;
1113 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1115 // Default to the LR register.
1116 def : InstAlias<"ret", (RET LR)>;
1118 let isCall = 1, Defs = [LR], Uses = [SP] in {
1119 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1122 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1123 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1124 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1126 // Create a separate pseudo-instruction for codegen to use so that we don't
1127 // flag lr as used in every function. It'll be restored before the RET by the
1128 // epilogue if it's legitimately used.
1129 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1130 let isTerminator = 1;
1135 // This is a directive-like pseudo-instruction. The purpose is to insert an
1136 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1137 // (which in the usual case is a BLR).
1138 let hasSideEffects = 1 in
1139 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1140 let AsmString = ".tlsdesccall $sym";
1143 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
1144 // FIXME: can "hasSideEffects be dropped?
1145 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
1146 isCodeGenOnly = 1 in
1148 : Pseudo<(outs), (ins i64imm:$sym),
1149 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>;
1150 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
1151 (TLSDESC_CALLSEQ texternalsym:$sym)>;
1153 //===----------------------------------------------------------------------===//
1154 // Conditional branch (immediate) instruction.
1155 //===----------------------------------------------------------------------===//
1156 def Bcc : BranchCond;
1158 //===----------------------------------------------------------------------===//
1159 // Compare-and-branch instructions.
1160 //===----------------------------------------------------------------------===//
1161 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1162 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1164 //===----------------------------------------------------------------------===//
1165 // Test-bit-and-branch instructions.
1166 //===----------------------------------------------------------------------===//
1167 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1168 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1170 //===----------------------------------------------------------------------===//
1171 // Unconditional branch (immediate) instructions.
1172 //===----------------------------------------------------------------------===//
1173 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1174 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1175 } // isBranch, isTerminator, isBarrier
1177 let isCall = 1, Defs = [LR], Uses = [SP] in {
1178 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1180 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1182 //===----------------------------------------------------------------------===//
1183 // Exception generation instructions.
1184 //===----------------------------------------------------------------------===//
1185 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1186 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1187 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1188 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1189 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1190 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1191 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1192 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1194 // DCPSn defaults to an immediate operand of zero if unspecified.
1195 def : InstAlias<"dcps1", (DCPS1 0)>;
1196 def : InstAlias<"dcps2", (DCPS2 0)>;
1197 def : InstAlias<"dcps3", (DCPS3 0)>;
1199 //===----------------------------------------------------------------------===//
1200 // Load instructions.
1201 //===----------------------------------------------------------------------===//
1203 // Pair (indexed, offset)
1204 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1205 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1206 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1207 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1208 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1210 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1212 // Pair (pre-indexed)
1213 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1214 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1215 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1216 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1217 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1219 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1221 // Pair (post-indexed)
1222 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1223 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1224 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1225 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1226 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1228 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1231 // Pair (no allocate)
1232 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1233 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1234 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1235 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1236 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1239 // (register offset)
1243 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1244 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1245 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1246 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1249 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1250 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1251 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1252 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1253 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1255 // Load sign-extended half-word
1256 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1257 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1259 // Load sign-extended byte
1260 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1261 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1263 // Load sign-extended word
1264 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1267 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1269 // For regular load, we do not have any alignment requirement.
1270 // Thus, it is safe to directly map the vector loads with interesting
1271 // addressing modes.
1272 // FIXME: We could do the same for bitconvert to floating point vectors.
1273 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1274 ValueType ScalTy, ValueType VecTy,
1275 Instruction LOADW, Instruction LOADX,
1277 def : Pat<(VecTy (scalar_to_vector (ScalTy
1278 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1279 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1280 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1283 def : Pat<(VecTy (scalar_to_vector (ScalTy
1284 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1285 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1286 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1290 let AddedComplexity = 10 in {
1291 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1292 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1294 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1295 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1297 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1298 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1300 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1301 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1303 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1304 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1306 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1308 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1311 def : Pat <(v1i64 (scalar_to_vector (i64
1312 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1313 ro_Wextend64:$extend))))),
1314 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1316 def : Pat <(v1i64 (scalar_to_vector (i64
1317 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1318 ro_Xextend64:$extend))))),
1319 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1322 // Match all load 64 bits width whose type is compatible with FPR64
1323 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1324 Instruction LOADW, Instruction LOADX> {
1326 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1327 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1329 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1330 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1333 let AddedComplexity = 10 in {
1334 let Predicates = [IsLE] in {
1335 // We must do vector loads with LD1 in big-endian.
1336 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1337 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1338 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1339 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1340 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1343 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1344 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1346 // Match all load 128 bits width whose type is compatible with FPR128
1347 let Predicates = [IsLE] in {
1348 // We must do vector loads with LD1 in big-endian.
1349 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1350 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1351 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1352 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1353 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1354 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1355 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1357 } // AddedComplexity = 10
1360 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1361 Instruction INSTW, Instruction INSTX> {
1362 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1363 (SUBREG_TO_REG (i64 0),
1364 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1367 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1368 (SUBREG_TO_REG (i64 0),
1369 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1373 let AddedComplexity = 10 in {
1374 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1375 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1376 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1378 // zextloadi1 -> zextloadi8
1379 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1381 // extload -> zextload
1382 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1383 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1384 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1386 // extloadi1 -> zextloadi8
1387 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1392 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1393 Instruction INSTW, Instruction INSTX> {
1394 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1395 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1397 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1398 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1402 let AddedComplexity = 10 in {
1403 // extload -> zextload
1404 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1405 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1406 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1408 // zextloadi1 -> zextloadi8
1409 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1413 // (unsigned immediate)
1415 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1417 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1418 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1420 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1421 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1423 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1424 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1425 [(set (f16 FPR16:$Rt),
1426 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1427 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1428 [(set (f32 FPR32:$Rt),
1429 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1430 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1431 [(set (f64 FPR64:$Rt),
1432 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1433 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1434 [(set (f128 FPR128:$Rt),
1435 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1437 // For regular load, we do not have any alignment requirement.
1438 // Thus, it is safe to directly map the vector loads with interesting
1439 // addressing modes.
1440 // FIXME: We could do the same for bitconvert to floating point vectors.
1441 def : Pat <(v8i8 (scalar_to_vector (i32
1442 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1443 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1444 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1445 def : Pat <(v16i8 (scalar_to_vector (i32
1446 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1447 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1448 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1449 def : Pat <(v4i16 (scalar_to_vector (i32
1450 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1451 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1452 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1453 def : Pat <(v8i16 (scalar_to_vector (i32
1454 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1455 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1456 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1457 def : Pat <(v2i32 (scalar_to_vector (i32
1458 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1459 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1460 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1461 def : Pat <(v4i32 (scalar_to_vector (i32
1462 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1463 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1464 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1465 def : Pat <(v1i64 (scalar_to_vector (i64
1466 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1467 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1468 def : Pat <(v2i64 (scalar_to_vector (i64
1469 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1470 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1471 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1473 // Match all load 64 bits width whose type is compatible with FPR64
1474 let Predicates = [IsLE] in {
1475 // We must use LD1 to perform vector loads in big-endian.
1476 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1477 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1478 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1479 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1480 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1481 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1482 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1483 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1484 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1485 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1487 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1488 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1489 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1490 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1492 // Match all load 128 bits width whose type is compatible with FPR128
1493 let Predicates = [IsLE] in {
1494 // We must use LD1 to perform vector loads in big-endian.
1495 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1496 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1497 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1498 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1499 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1500 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1501 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1502 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1503 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1504 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1505 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1506 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1507 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1508 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1510 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1511 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1513 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1515 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1516 uimm12s2:$offset)))]>;
1517 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1519 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1520 uimm12s1:$offset)))]>;
1522 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1523 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1524 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1525 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1527 // zextloadi1 -> zextloadi8
1528 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1529 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1530 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1531 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1533 // extload -> zextload
1534 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1535 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1536 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1537 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1538 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1539 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1540 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1541 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1542 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1543 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1544 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1545 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1546 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1547 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1549 // load sign-extended half-word
1550 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1552 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1553 uimm12s2:$offset)))]>;
1554 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1556 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1557 uimm12s2:$offset)))]>;
1559 // load sign-extended byte
1560 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1562 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1563 uimm12s1:$offset)))]>;
1564 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1566 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1567 uimm12s1:$offset)))]>;
1569 // load sign-extended word
1570 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1572 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1573 uimm12s4:$offset)))]>;
1575 // load zero-extended word
1576 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1577 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1580 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1581 [(AArch64Prefetch imm:$Rt,
1582 (am_indexed64 GPR64sp:$Rn,
1583 uimm12s8:$offset))]>;
1585 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1589 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1590 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1591 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1592 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1593 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1595 // load sign-extended word
1596 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1599 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1600 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1603 // (unscaled immediate)
1604 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1606 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1607 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1609 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1610 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1612 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1613 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1615 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1616 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1617 [(set (f32 FPR32:$Rt),
1618 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1619 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1620 [(set (f64 FPR64:$Rt),
1621 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1622 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1623 [(set (f128 FPR128:$Rt),
1624 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1627 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1629 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1631 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1633 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1635 // Match all load 64 bits width whose type is compatible with FPR64
1636 let Predicates = [IsLE] in {
1637 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1638 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1639 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1640 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1641 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1642 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1643 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1644 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1645 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1646 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1648 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1649 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1650 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1651 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1653 // Match all load 128 bits width whose type is compatible with FPR128
1654 let Predicates = [IsLE] in {
1655 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1656 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1657 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1658 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1659 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1660 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1661 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1662 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1663 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1664 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1665 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1666 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1667 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1668 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1672 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1673 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1674 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1675 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1676 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1677 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1678 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1679 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1680 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1681 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1682 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1683 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1684 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1685 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1687 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1688 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1689 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1690 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1691 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1692 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1693 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1694 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1695 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1696 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1697 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1698 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1699 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1700 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1704 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1706 // Define new assembler match classes as we want to only match these when
1707 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1708 // associate a DiagnosticType either, as we want the diagnostic for the
1709 // canonical form (the scaled operand) to take precedence.
1710 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1711 let Name = "SImm9OffsetFB" # Width;
1712 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1713 let RenderMethod = "addImmOperands";
1716 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1717 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1718 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1719 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1720 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1722 def simm9_offset_fb8 : Operand<i64> {
1723 let ParserMatchClass = SImm9OffsetFB8Operand;
1725 def simm9_offset_fb16 : Operand<i64> {
1726 let ParserMatchClass = SImm9OffsetFB16Operand;
1728 def simm9_offset_fb32 : Operand<i64> {
1729 let ParserMatchClass = SImm9OffsetFB32Operand;
1731 def simm9_offset_fb64 : Operand<i64> {
1732 let ParserMatchClass = SImm9OffsetFB64Operand;
1734 def simm9_offset_fb128 : Operand<i64> {
1735 let ParserMatchClass = SImm9OffsetFB128Operand;
1738 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1739 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1740 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1741 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1742 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1743 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1744 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1745 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1746 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1747 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1748 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1749 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1750 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1751 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1754 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1755 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1756 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1757 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1759 // load sign-extended half-word
1761 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1763 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1765 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1767 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1769 // load sign-extended byte
1771 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1773 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1775 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1777 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1779 // load sign-extended word
1781 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1783 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1785 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1786 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1787 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1788 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1789 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1790 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1791 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1792 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1793 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1794 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1795 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1796 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1797 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1798 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1799 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1802 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1803 [(AArch64Prefetch imm:$Rt,
1804 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1807 // (unscaled immediate, unprivileged)
1808 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1809 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1811 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1812 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1814 // load sign-extended half-word
1815 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1816 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1818 // load sign-extended byte
1819 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1820 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1822 // load sign-extended word
1823 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1826 // (immediate pre-indexed)
1827 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1828 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1829 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1830 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1831 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1832 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1833 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1835 // load sign-extended half-word
1836 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1837 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1839 // load sign-extended byte
1840 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1841 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1843 // load zero-extended byte
1844 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1845 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1847 // load sign-extended word
1848 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1851 // (immediate post-indexed)
1852 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1853 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1854 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1855 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1856 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1857 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1858 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1860 // load sign-extended half-word
1861 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1862 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1864 // load sign-extended byte
1865 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1866 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1868 // load zero-extended byte
1869 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1870 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1872 // load sign-extended word
1873 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1875 //===----------------------------------------------------------------------===//
1876 // Store instructions.
1877 //===----------------------------------------------------------------------===//
1879 // Pair (indexed, offset)
1880 // FIXME: Use dedicated range-checked addressing mode operand here.
1881 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1882 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1883 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1884 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1885 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1887 // Pair (pre-indexed)
1888 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1889 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1890 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1891 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1892 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1894 // Pair (pre-indexed)
1895 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1896 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1897 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1898 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1899 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1901 // Pair (no allocate)
1902 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1903 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1904 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1905 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1906 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1909 // (Register offset)
1912 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1913 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1914 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1915 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1919 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1920 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1921 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1922 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1923 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1925 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1926 Instruction STRW, Instruction STRX> {
1928 def : Pat<(storeop GPR64:$Rt,
1929 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1930 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1931 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1933 def : Pat<(storeop GPR64:$Rt,
1934 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1935 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1936 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1939 let AddedComplexity = 10 in {
1941 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1942 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1943 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1946 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1947 Instruction STRW, Instruction STRX> {
1948 def : Pat<(store (VecTy FPR:$Rt),
1949 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1950 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1952 def : Pat<(store (VecTy FPR:$Rt),
1953 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1954 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1957 let AddedComplexity = 10 in {
1958 // Match all store 64 bits width whose type is compatible with FPR64
1959 let Predicates = [IsLE] in {
1960 // We must use ST1 to store vectors in big-endian.
1961 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1962 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1963 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1964 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1965 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1968 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1969 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1971 // Match all store 128 bits width whose type is compatible with FPR128
1972 let Predicates = [IsLE] in {
1973 // We must use ST1 to store vectors in big-endian.
1974 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1975 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1976 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1977 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1978 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1979 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1980 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
1982 } // AddedComplexity = 10
1984 // Match stores from lane 0 to the appropriate subreg's store.
1985 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
1986 ValueType VecTy, ValueType STy,
1987 SubRegIndex SubRegIdx,
1988 Instruction STRW, Instruction STRX> {
1990 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
1991 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1992 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
1993 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1995 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
1996 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1997 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
1998 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2001 let AddedComplexity = 19 in {
2002 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2003 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
2004 defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
2005 defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
2006 defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
2007 defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
2008 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
2012 // (unsigned immediate)
2013 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
2015 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2016 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
2018 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2019 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
2021 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
2022 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
2023 [(store (f16 FPR16:$Rt),
2024 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
2025 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
2026 [(store (f32 FPR32:$Rt),
2027 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2028 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
2029 [(store (f64 FPR64:$Rt),
2030 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2031 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
2033 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
2034 [(truncstorei16 GPR32:$Rt,
2035 (am_indexed16 GPR64sp:$Rn,
2036 uimm12s2:$offset))]>;
2037 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
2038 [(truncstorei8 GPR32:$Rt,
2039 (am_indexed8 GPR64sp:$Rn,
2040 uimm12s1:$offset))]>;
2042 // Match all store 64 bits width whose type is compatible with FPR64
2043 let AddedComplexity = 10 in {
2044 let Predicates = [IsLE] in {
2045 // We must use ST1 to store vectors in big-endian.
2046 def : Pat<(store (v2f32 FPR64:$Rt),
2047 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2048 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2049 def : Pat<(store (v8i8 FPR64:$Rt),
2050 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2051 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2052 def : Pat<(store (v4i16 FPR64:$Rt),
2053 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2054 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2055 def : Pat<(store (v2i32 FPR64:$Rt),
2056 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2057 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2058 def : Pat<(store (v4f16 FPR64:$Rt),
2059 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2060 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2062 def : Pat<(store (v1f64 FPR64:$Rt),
2063 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2064 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2065 def : Pat<(store (v1i64 FPR64:$Rt),
2066 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2067 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2069 // Match all store 128 bits width whose type is compatible with FPR128
2070 let Predicates = [IsLE] in {
2071 // We must use ST1 to store vectors in big-endian.
2072 def : Pat<(store (v4f32 FPR128:$Rt),
2073 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2074 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2075 def : Pat<(store (v2f64 FPR128:$Rt),
2076 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2077 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2078 def : Pat<(store (v16i8 FPR128:$Rt),
2079 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2080 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2081 def : Pat<(store (v8i16 FPR128:$Rt),
2082 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2083 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2084 def : Pat<(store (v4i32 FPR128:$Rt),
2085 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2086 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2087 def : Pat<(store (v2i64 FPR128:$Rt),
2088 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2089 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2090 def : Pat<(store (v8f16 FPR128:$Rt),
2091 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2092 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2094 def : Pat<(store (f128 FPR128:$Rt),
2095 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2096 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2099 def : Pat<(truncstorei32 GPR64:$Rt,
2100 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
2101 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2102 def : Pat<(truncstorei16 GPR64:$Rt,
2103 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2104 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
2105 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
2106 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
2108 } // AddedComplexity = 10
2111 // (unscaled immediate)
2112 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2114 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2115 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2117 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2118 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2120 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2121 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2122 [(store (f16 FPR16:$Rt),
2123 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2124 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2125 [(store (f32 FPR32:$Rt),
2126 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2127 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2128 [(store (f64 FPR64:$Rt),
2129 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2130 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2131 [(store (f128 FPR128:$Rt),
2132 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2133 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2134 [(truncstorei16 GPR32:$Rt,
2135 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2136 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2137 [(truncstorei8 GPR32:$Rt,
2138 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2140 // Match all store 64 bits width whose type is compatible with FPR64
2141 let Predicates = [IsLE] in {
2142 // We must use ST1 to store vectors in big-endian.
2143 def : Pat<(store (v2f32 FPR64:$Rt),
2144 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2145 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2146 def : Pat<(store (v8i8 FPR64:$Rt),
2147 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2148 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2149 def : Pat<(store (v4i16 FPR64:$Rt),
2150 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2151 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2152 def : Pat<(store (v2i32 FPR64:$Rt),
2153 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2154 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2155 def : Pat<(store (v4f16 FPR64:$Rt),
2156 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2157 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2159 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2160 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2161 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2162 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2164 // Match all store 128 bits width whose type is compatible with FPR128
2165 let Predicates = [IsLE] in {
2166 // We must use ST1 to store vectors in big-endian.
2167 def : Pat<(store (v4f32 FPR128:$Rt),
2168 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2169 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2170 def : Pat<(store (v2f64 FPR128:$Rt),
2171 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2172 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2173 def : Pat<(store (v16i8 FPR128:$Rt),
2174 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2175 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2176 def : Pat<(store (v8i16 FPR128:$Rt),
2177 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2178 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2179 def : Pat<(store (v4i32 FPR128:$Rt),
2180 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2181 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2182 def : Pat<(store (v2i64 FPR128:$Rt),
2183 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2184 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2185 def : Pat<(store (v2f64 FPR128:$Rt),
2186 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2187 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2188 def : Pat<(store (v8f16 FPR128:$Rt),
2189 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2190 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2193 // unscaled i64 truncating stores
2194 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2195 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2196 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2197 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2198 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2199 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2202 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2203 def : InstAlias<"str $Rt, [$Rn, $offset]",
2204 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2205 def : InstAlias<"str $Rt, [$Rn, $offset]",
2206 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2207 def : InstAlias<"str $Rt, [$Rn, $offset]",
2208 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2209 def : InstAlias<"str $Rt, [$Rn, $offset]",
2210 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2211 def : InstAlias<"str $Rt, [$Rn, $offset]",
2212 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2213 def : InstAlias<"str $Rt, [$Rn, $offset]",
2214 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2215 def : InstAlias<"str $Rt, [$Rn, $offset]",
2216 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2218 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2219 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2220 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2221 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2224 // (unscaled immediate, unprivileged)
2225 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2226 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2228 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2229 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2232 // (immediate pre-indexed)
2233 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2234 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2235 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2236 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2237 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2238 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2239 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2241 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2242 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2245 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2246 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2248 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2249 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2251 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2252 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2255 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2256 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2257 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2258 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2259 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2260 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2261 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2262 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2263 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2264 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2265 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2266 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2267 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2268 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2270 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2271 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2272 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2273 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2274 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2275 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2276 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2277 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2278 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2279 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2280 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2281 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2282 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2283 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2286 // (immediate post-indexed)
2287 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2288 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2289 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2290 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2291 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2292 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2293 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2295 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2296 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2299 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2300 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2302 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2303 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2305 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2306 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2309 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2310 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2311 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2312 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2313 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2314 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2315 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2316 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2317 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2318 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2319 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2320 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2321 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2322 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2324 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2325 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2326 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2327 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2328 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2329 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2330 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2331 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2332 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2333 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2334 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2335 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2336 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2337 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2339 //===----------------------------------------------------------------------===//
2340 // Load/store exclusive instructions.
2341 //===----------------------------------------------------------------------===//
2343 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2344 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2345 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2346 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2348 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2349 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2350 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2351 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2353 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2354 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2355 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2356 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2358 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2359 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2360 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2361 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2363 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2364 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2365 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2366 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2368 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2369 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2370 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2371 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2373 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2374 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2376 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2377 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2379 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2380 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2382 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2383 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2385 let Predicates = [HasV8_1a] in {
2386 // v8.1a "Limited Order Region" extension load-acquire instructions
2387 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2388 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
2389 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2390 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
2392 // v8.1a "Limited Order Region" extension store-release instructions
2393 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
2394 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
2395 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2396 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
2399 //===----------------------------------------------------------------------===//
2400 // Scaled floating point to integer conversion instructions.
2401 //===----------------------------------------------------------------------===//
2403 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2404 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2405 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2406 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2407 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2408 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2409 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2410 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2411 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2412 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2413 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2414 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2415 let isCodeGenOnly = 1 in {
2416 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2417 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2418 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2419 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2422 //===----------------------------------------------------------------------===//
2423 // Scaled integer to floating point conversion instructions.
2424 //===----------------------------------------------------------------------===//
2426 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2427 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2429 //===----------------------------------------------------------------------===//
2430 // Unscaled integer to floating point conversion instruction.
2431 //===----------------------------------------------------------------------===//
2433 defm FMOV : UnscaledConversion<"fmov">;
2435 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
2436 let isReMaterializable = 1, isCodeGenOnly = 1 in {
2437 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
2438 PseudoInstExpansion<(FMOVWSr FPR32:$Rd, WZR)>,
2440 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
2441 PseudoInstExpansion<(FMOVXDr FPR64:$Rd, XZR)>,
2445 //===----------------------------------------------------------------------===//
2446 // Floating point conversion instruction.
2447 //===----------------------------------------------------------------------===//
2449 defm FCVT : FPConversion<"fcvt">;
2451 //===----------------------------------------------------------------------===//
2452 // Floating point single operand instructions.
2453 //===----------------------------------------------------------------------===//
2455 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2456 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2457 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2458 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2459 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2460 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2461 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2462 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2464 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2465 (FRINTNDr FPR64:$Rn)>;
2467 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2468 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2469 // <rdar://problem/13715968>
2470 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2471 let hasSideEffects = 1 in {
2472 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2475 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2477 let SchedRW = [WriteFDiv] in {
2478 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2481 //===----------------------------------------------------------------------===//
2482 // Floating point two operand instructions.
2483 //===----------------------------------------------------------------------===//
2485 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2486 let SchedRW = [WriteFDiv] in {
2487 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2489 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2490 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2491 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2492 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2493 let SchedRW = [WriteFMul] in {
2494 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2495 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2497 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2499 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2500 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2501 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2502 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2503 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2504 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2505 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2506 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2508 //===----------------------------------------------------------------------===//
2509 // Floating point three operand instructions.
2510 //===----------------------------------------------------------------------===//
2512 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2513 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2514 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2515 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2516 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2517 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2518 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2520 // The following def pats catch the case where the LHS of an FMA is negated.
2521 // The TriOpFrag above catches the case where the middle operand is negated.
2523 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2524 // the NEON variant.
2525 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2526 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2528 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2529 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2531 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2533 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2534 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2536 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2537 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2539 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2540 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2542 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2543 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2545 //===----------------------------------------------------------------------===//
2546 // Floating point comparison instructions.
2547 //===----------------------------------------------------------------------===//
2549 defm FCMPE : FPComparison<1, "fcmpe">;
2550 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2552 //===----------------------------------------------------------------------===//
2553 // Floating point conditional comparison instructions.
2554 //===----------------------------------------------------------------------===//
2556 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2557 defm FCCMP : FPCondComparison<0, "fccmp">;
2559 //===----------------------------------------------------------------------===//
2560 // Floating point conditional select instruction.
2561 //===----------------------------------------------------------------------===//
2563 defm FCSEL : FPCondSelect<"fcsel">;
2565 // CSEL instructions providing f128 types need to be handled by a
2566 // pseudo-instruction since the eventual code will need to introduce basic
2567 // blocks and control flow.
2568 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2569 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2570 [(set (f128 FPR128:$Rd),
2571 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2572 (i32 imm:$cond), NZCV))]> {
2574 let usesCustomInserter = 1;
2578 //===----------------------------------------------------------------------===//
2579 // Floating point immediate move.
2580 //===----------------------------------------------------------------------===//
2582 let isReMaterializable = 1 in {
2583 defm FMOV : FPMoveImmediate<"fmov">;
2586 //===----------------------------------------------------------------------===//
2587 // Advanced SIMD two vector instructions.
2588 //===----------------------------------------------------------------------===//
2590 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2591 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2592 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2593 (ABSv8i8 V64:$src)>;
2594 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2595 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2596 (ABSv4i16 V64:$src)>;
2597 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2598 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2599 (ABSv2i32 V64:$src)>;
2600 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2601 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2602 (ABSv16i8 V128:$src)>;
2603 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2604 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2605 (ABSv8i16 V128:$src)>;
2606 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2607 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2608 (ABSv4i32 V128:$src)>;
2609 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2610 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2611 (ABSv2i64 V128:$src)>;
2613 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2614 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2615 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2616 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2617 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2618 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2619 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2620 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2621 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2623 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2624 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2625 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2626 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2627 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2628 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2629 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2630 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2631 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2632 (FCVTLv4i16 V64:$Rn)>;
2633 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2635 (FCVTLv8i16 V128:$Rn)>;
2636 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2637 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2639 (FCVTLv4i32 V128:$Rn)>;
2641 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2642 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2644 (FCVTLv8i16 V128:$Rn)>;
2646 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2647 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2648 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2649 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2650 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2651 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2652 (FCVTNv4i16 V128:$Rn)>;
2653 def : Pat<(concat_vectors V64:$Rd,
2654 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2655 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2656 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2657 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2658 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2659 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2660 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2661 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2662 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2663 int_aarch64_neon_fcvtxn>;
2664 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2665 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2666 let isCodeGenOnly = 1 in {
2667 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2668 int_aarch64_neon_fcvtzs>;
2669 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2670 int_aarch64_neon_fcvtzu>;
2672 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2673 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2674 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2675 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2676 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2677 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2678 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2679 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2680 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2681 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2682 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2683 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2684 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2685 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2686 // Aliases for MVN -> NOT.
2687 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2688 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2689 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2690 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2692 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2693 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2694 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2695 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2696 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2697 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2698 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2700 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2701 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2702 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2703 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2704 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2705 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2706 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2707 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2709 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2710 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2711 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2712 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2713 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2715 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2716 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2717 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2718 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2719 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2720 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2721 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2722 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2723 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2724 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2725 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2726 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2727 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2728 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2729 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2730 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2731 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2732 int_aarch64_neon_uaddlp>;
2733 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2734 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2735 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2736 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2737 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2738 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2740 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2741 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2742 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2743 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2744 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2745 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2747 // Patterns for vector long shift (by element width). These need to match all
2748 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2750 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2751 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2752 (SHLLv8i8 V64:$Rn)>;
2753 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2754 (SHLLv16i8 V128:$Rn)>;
2755 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2756 (SHLLv4i16 V64:$Rn)>;
2757 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2758 (SHLLv8i16 V128:$Rn)>;
2759 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2760 (SHLLv2i32 V64:$Rn)>;
2761 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2762 (SHLLv4i32 V128:$Rn)>;
2765 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2766 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2767 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2769 //===----------------------------------------------------------------------===//
2770 // Advanced SIMD three vector instructions.
2771 //===----------------------------------------------------------------------===//
2773 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2774 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2775 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2776 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2777 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2778 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2779 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2780 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2781 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2782 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2783 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2784 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2785 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2786 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2787 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2788 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2789 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2790 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2791 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2792 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2793 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2794 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2795 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2796 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2797 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2799 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2800 // instruction expects the addend first, while the fma intrinsic puts it last.
2801 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2802 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2803 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2804 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2806 // The following def pats catch the case where the LHS of an FMA is negated.
2807 // The TriOpFrag above catches the case where the middle operand is negated.
2808 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2809 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2811 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2812 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2814 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2815 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2817 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2818 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2819 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2820 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2821 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2822 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2823 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2824 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2825 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2826 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2827 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2828 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2829 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2830 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2831 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2832 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2833 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2834 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2835 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2836 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2837 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2838 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2839 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2840 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2841 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2842 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2843 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2844 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2845 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2846 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2847 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2848 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2849 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2850 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2851 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2852 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2853 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2854 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2855 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2856 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2857 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2858 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2859 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2860 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2861 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2862 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2863 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
2864 int_aarch64_neon_sqadd>;
2865 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
2866 int_aarch64_neon_sqsub>;
2868 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2869 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2870 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2871 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2872 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2873 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2874 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2875 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2876 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2877 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2878 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2880 def : Pat<(v8i8 (smin V64:$Rn, V64:$Rm)),
2881 (SMINv8i8 V64:$Rn, V64:$Rm)>;
2882 def : Pat<(v4i16 (smin V64:$Rn, V64:$Rm)),
2883 (SMINv4i16 V64:$Rn, V64:$Rm)>;
2884 def : Pat<(v2i32 (smin V64:$Rn, V64:$Rm)),
2885 (SMINv2i32 V64:$Rn, V64:$Rm)>;
2886 def : Pat<(v16i8 (smin V128:$Rn, V128:$Rm)),
2887 (SMINv16i8 V128:$Rn, V128:$Rm)>;
2888 def : Pat<(v8i16 (smin V128:$Rn, V128:$Rm)),
2889 (SMINv8i16 V128:$Rn, V128:$Rm)>;
2890 def : Pat<(v4i32 (smin V128:$Rn, V128:$Rm)),
2891 (SMINv4i32 V128:$Rn, V128:$Rm)>;
2892 def : Pat<(v8i8 (smax V64:$Rn, V64:$Rm)),
2893 (SMAXv8i8 V64:$Rn, V64:$Rm)>;
2894 def : Pat<(v4i16 (smax V64:$Rn, V64:$Rm)),
2895 (SMAXv4i16 V64:$Rn, V64:$Rm)>;
2896 def : Pat<(v2i32 (smax V64:$Rn, V64:$Rm)),
2897 (SMAXv2i32 V64:$Rn, V64:$Rm)>;
2898 def : Pat<(v16i8 (smax V128:$Rn, V128:$Rm)),
2899 (SMAXv16i8 V128:$Rn, V128:$Rm)>;
2900 def : Pat<(v8i16 (smax V128:$Rn, V128:$Rm)),
2901 (SMAXv8i16 V128:$Rn, V128:$Rm)>;
2902 def : Pat<(v4i32 (smax V128:$Rn, V128:$Rm)),
2903 (SMAXv4i32 V128:$Rn, V128:$Rm)>;
2904 def : Pat<(v8i8 (umin V64:$Rn, V64:$Rm)),
2905 (UMINv8i8 V64:$Rn, V64:$Rm)>;
2906 def : Pat<(v4i16 (umin V64:$Rn, V64:$Rm)),
2907 (UMINv4i16 V64:$Rn, V64:$Rm)>;
2908 def : Pat<(v2i32 (umin V64:$Rn, V64:$Rm)),
2909 (UMINv2i32 V64:$Rn, V64:$Rm)>;
2910 def : Pat<(v16i8 (umin V128:$Rn, V128:$Rm)),
2911 (UMINv16i8 V128:$Rn, V128:$Rm)>;
2912 def : Pat<(v8i16 (umin V128:$Rn, V128:$Rm)),
2913 (UMINv8i16 V128:$Rn, V128:$Rm)>;
2914 def : Pat<(v4i32 (umin V128:$Rn, V128:$Rm)),
2915 (UMINv4i32 V128:$Rn, V128:$Rm)>;
2916 def : Pat<(v8i8 (umax V64:$Rn, V64:$Rm)),
2917 (UMAXv8i8 V64:$Rn, V64:$Rm)>;
2918 def : Pat<(v4i16 (umax V64:$Rn, V64:$Rm)),
2919 (UMAXv4i16 V64:$Rn, V64:$Rm)>;
2920 def : Pat<(v2i32 (umax V64:$Rn, V64:$Rm)),
2921 (UMAXv2i32 V64:$Rn, V64:$Rm)>;
2922 def : Pat<(v16i8 (umax V128:$Rn, V128:$Rm)),
2923 (UMAXv16i8 V128:$Rn, V128:$Rm)>;
2924 def : Pat<(v8i16 (umax V128:$Rn, V128:$Rm)),
2925 (UMAXv8i16 V128:$Rn, V128:$Rm)>;
2926 def : Pat<(v4i32 (umax V128:$Rn, V128:$Rm)),
2927 (UMAXv4i32 V128:$Rn, V128:$Rm)>;
2929 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2930 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2931 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2932 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2933 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2934 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2935 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2936 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2938 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2939 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2940 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2941 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2942 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2943 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2944 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2945 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2947 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2948 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2949 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2950 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2951 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2952 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2953 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2954 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2956 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2957 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2958 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2959 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2960 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2961 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2962 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2963 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2965 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2966 "|cmls.8b\t$dst, $src1, $src2}",
2967 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2968 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2969 "|cmls.16b\t$dst, $src1, $src2}",
2970 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2971 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2972 "|cmls.4h\t$dst, $src1, $src2}",
2973 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2974 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2975 "|cmls.8h\t$dst, $src1, $src2}",
2976 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2977 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2978 "|cmls.2s\t$dst, $src1, $src2}",
2979 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2980 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2981 "|cmls.4s\t$dst, $src1, $src2}",
2982 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2983 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2984 "|cmls.2d\t$dst, $src1, $src2}",
2985 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2987 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2988 "|cmlo.8b\t$dst, $src1, $src2}",
2989 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2990 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2991 "|cmlo.16b\t$dst, $src1, $src2}",
2992 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2993 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2994 "|cmlo.4h\t$dst, $src1, $src2}",
2995 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2996 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2997 "|cmlo.8h\t$dst, $src1, $src2}",
2998 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2999 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
3000 "|cmlo.2s\t$dst, $src1, $src2}",
3001 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3002 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
3003 "|cmlo.4s\t$dst, $src1, $src2}",
3004 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3005 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
3006 "|cmlo.2d\t$dst, $src1, $src2}",
3007 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3009 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
3010 "|cmle.8b\t$dst, $src1, $src2}",
3011 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3012 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
3013 "|cmle.16b\t$dst, $src1, $src2}",
3014 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3015 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
3016 "|cmle.4h\t$dst, $src1, $src2}",
3017 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3018 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
3019 "|cmle.8h\t$dst, $src1, $src2}",
3020 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3021 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
3022 "|cmle.2s\t$dst, $src1, $src2}",
3023 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3024 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
3025 "|cmle.4s\t$dst, $src1, $src2}",
3026 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3027 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
3028 "|cmle.2d\t$dst, $src1, $src2}",
3029 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3031 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
3032 "|cmlt.8b\t$dst, $src1, $src2}",
3033 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3034 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
3035 "|cmlt.16b\t$dst, $src1, $src2}",
3036 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3037 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
3038 "|cmlt.4h\t$dst, $src1, $src2}",
3039 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3040 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
3041 "|cmlt.8h\t$dst, $src1, $src2}",
3042 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3043 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
3044 "|cmlt.2s\t$dst, $src1, $src2}",
3045 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3046 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
3047 "|cmlt.4s\t$dst, $src1, $src2}",
3048 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3049 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
3050 "|cmlt.2d\t$dst, $src1, $src2}",
3051 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3053 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
3054 "|fcmle.2s\t$dst, $src1, $src2}",
3055 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3056 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
3057 "|fcmle.4s\t$dst, $src1, $src2}",
3058 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3059 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
3060 "|fcmle.2d\t$dst, $src1, $src2}",
3061 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3063 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
3064 "|fcmlt.2s\t$dst, $src1, $src2}",
3065 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3066 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
3067 "|fcmlt.4s\t$dst, $src1, $src2}",
3068 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3069 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
3070 "|fcmlt.2d\t$dst, $src1, $src2}",
3071 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3073 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
3074 "|facle.2s\t$dst, $src1, $src2}",
3075 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3076 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
3077 "|facle.4s\t$dst, $src1, $src2}",
3078 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3079 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
3080 "|facle.2d\t$dst, $src1, $src2}",
3081 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3083 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
3084 "|faclt.2s\t$dst, $src1, $src2}",
3085 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3086 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
3087 "|faclt.4s\t$dst, $src1, $src2}",
3088 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3089 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
3090 "|faclt.2d\t$dst, $src1, $src2}",
3091 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3093 //===----------------------------------------------------------------------===//
3094 // Advanced SIMD three scalar instructions.
3095 //===----------------------------------------------------------------------===//
3097 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
3098 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
3099 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
3100 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
3101 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
3102 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
3103 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
3104 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
3105 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3106 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
3107 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
3108 int_aarch64_neon_facge>;
3109 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
3110 int_aarch64_neon_facgt>;
3111 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
3112 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
3113 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
3114 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
3115 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
3116 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
3117 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
3118 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
3119 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
3120 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
3121 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
3122 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
3123 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
3124 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
3125 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
3126 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
3127 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
3128 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
3129 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
3130 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
3131 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
3132 let Predicates = [HasV8_1a] in {
3133 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
3134 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
3135 def : Pat<(i32 (int_aarch64_neon_sqadd
3137 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3138 (i32 FPR32:$Rm))))),
3139 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3140 def : Pat<(i32 (int_aarch64_neon_sqsub
3142 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3143 (i32 FPR32:$Rm))))),
3144 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3147 def : InstAlias<"cmls $dst, $src1, $src2",
3148 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3149 def : InstAlias<"cmle $dst, $src1, $src2",
3150 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3151 def : InstAlias<"cmlo $dst, $src1, $src2",
3152 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3153 def : InstAlias<"cmlt $dst, $src1, $src2",
3154 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3155 def : InstAlias<"fcmle $dst, $src1, $src2",
3156 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3157 def : InstAlias<"fcmle $dst, $src1, $src2",
3158 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3159 def : InstAlias<"fcmlt $dst, $src1, $src2",
3160 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3161 def : InstAlias<"fcmlt $dst, $src1, $src2",
3162 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3163 def : InstAlias<"facle $dst, $src1, $src2",
3164 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3165 def : InstAlias<"facle $dst, $src1, $src2",
3166 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3167 def : InstAlias<"faclt $dst, $src1, $src2",
3168 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3169 def : InstAlias<"faclt $dst, $src1, $src2",
3170 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3172 //===----------------------------------------------------------------------===//
3173 // Advanced SIMD three scalar instructions (mixed operands).
3174 //===----------------------------------------------------------------------===//
3175 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3176 int_aarch64_neon_sqdmulls_scalar>;
3177 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
3178 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3180 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3181 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3182 (i32 FPR32:$Rm))))),
3183 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3184 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3185 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3186 (i32 FPR32:$Rm))))),
3187 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3189 //===----------------------------------------------------------------------===//
3190 // Advanced SIMD two scalar instructions.
3191 //===----------------------------------------------------------------------===//
3193 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
3194 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3195 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3196 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3197 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3198 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3199 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3200 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3201 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3202 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3203 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3204 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
3205 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
3206 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
3207 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
3208 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
3209 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
3210 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
3211 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
3212 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3213 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
3214 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
3215 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
3216 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
3217 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
3218 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3219 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3220 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3221 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3222 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3223 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3224 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3225 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3226 int_aarch64_neon_suqadd>;
3227 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3228 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3229 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3230 int_aarch64_neon_usqadd>;
3232 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3234 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3235 (FCVTASv1i64 FPR64:$Rn)>;
3236 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3237 (FCVTAUv1i64 FPR64:$Rn)>;
3238 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3239 (FCVTMSv1i64 FPR64:$Rn)>;
3240 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3241 (FCVTMUv1i64 FPR64:$Rn)>;
3242 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3243 (FCVTNSv1i64 FPR64:$Rn)>;
3244 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3245 (FCVTNUv1i64 FPR64:$Rn)>;
3246 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3247 (FCVTPSv1i64 FPR64:$Rn)>;
3248 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3249 (FCVTPUv1i64 FPR64:$Rn)>;
3251 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3252 (FRECPEv1i32 FPR32:$Rn)>;
3253 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3254 (FRECPEv1i64 FPR64:$Rn)>;
3255 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3256 (FRECPEv1i64 FPR64:$Rn)>;
3258 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3259 (FRECPXv1i32 FPR32:$Rn)>;
3260 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3261 (FRECPXv1i64 FPR64:$Rn)>;
3263 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3264 (FRSQRTEv1i32 FPR32:$Rn)>;
3265 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3266 (FRSQRTEv1i64 FPR64:$Rn)>;
3267 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3268 (FRSQRTEv1i64 FPR64:$Rn)>;
3270 // If an integer is about to be converted to a floating point value,
3271 // just load it on the floating point unit.
3272 // Here are the patterns for 8 and 16-bits to float.
3274 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3275 SDPatternOperator loadop, Instruction UCVTF,
3276 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3278 def : Pat<(DstTy (uint_to_fp (SrcTy
3279 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3280 ro.Wext:$extend))))),
3281 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3282 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3285 def : Pat<(DstTy (uint_to_fp (SrcTy
3286 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3287 ro.Wext:$extend))))),
3288 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3289 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3293 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3294 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3295 def : Pat <(f32 (uint_to_fp (i32
3296 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3297 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3298 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3299 def : Pat <(f32 (uint_to_fp (i32
3300 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3301 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3302 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3303 // 16-bits -> float.
3304 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3305 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3306 def : Pat <(f32 (uint_to_fp (i32
3307 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3308 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3309 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3310 def : Pat <(f32 (uint_to_fp (i32
3311 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3312 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3313 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3314 // 32-bits are handled in target specific dag combine:
3315 // performIntToFpCombine.
3316 // 64-bits integer to 32-bits floating point, not possible with
3317 // UCVTF on floating point registers (both source and destination
3318 // must have the same size).
3320 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3321 // 8-bits -> double.
3322 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3323 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3324 def : Pat <(f64 (uint_to_fp (i32
3325 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3326 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3327 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3328 def : Pat <(f64 (uint_to_fp (i32
3329 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3330 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3331 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3332 // 16-bits -> double.
3333 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3334 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3335 def : Pat <(f64 (uint_to_fp (i32
3336 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3337 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3338 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3339 def : Pat <(f64 (uint_to_fp (i32
3340 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3341 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3342 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3343 // 32-bits -> double.
3344 defm : UIntToFPROLoadPat<f64, i32, load,
3345 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3346 def : Pat <(f64 (uint_to_fp (i32
3347 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3348 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3349 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3350 def : Pat <(f64 (uint_to_fp (i32
3351 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3352 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3353 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3354 // 64-bits -> double are handled in target specific dag combine:
3355 // performIntToFpCombine.
3357 //===----------------------------------------------------------------------===//
3358 // Advanced SIMD three different-sized vector instructions.
3359 //===----------------------------------------------------------------------===//
3361 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3362 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3363 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3364 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3365 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3366 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3367 int_aarch64_neon_sabd>;
3368 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3369 int_aarch64_neon_sabd>;
3370 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3371 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3372 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3373 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3374 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3375 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3376 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3377 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3378 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3379 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3380 int_aarch64_neon_sqadd>;
3381 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3382 int_aarch64_neon_sqsub>;
3383 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3384 int_aarch64_neon_sqdmull>;
3385 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3386 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3387 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3388 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3389 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3390 int_aarch64_neon_uabd>;
3391 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3392 int_aarch64_neon_uabd>;
3393 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3394 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3395 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3396 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3397 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3398 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3399 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3400 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3401 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3402 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3403 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3404 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3405 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3407 // Additional patterns for SMULL and UMULL
3408 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3409 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3410 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3411 (INST8B V64:$Rn, V64:$Rm)>;
3412 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3413 (INST4H V64:$Rn, V64:$Rm)>;
3414 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3415 (INST2S V64:$Rn, V64:$Rm)>;
3418 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3419 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3420 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3421 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3423 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3424 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3425 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3426 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3427 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3428 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3429 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3430 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3431 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3434 defm : Neon_mulacc_widen_patterns<
3435 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3436 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3437 defm : Neon_mulacc_widen_patterns<
3438 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3439 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3440 defm : Neon_mulacc_widen_patterns<
3441 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3442 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3443 defm : Neon_mulacc_widen_patterns<
3444 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3445 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3447 // Patterns for 64-bit pmull
3448 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3449 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3450 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3451 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3452 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3454 // CodeGen patterns for addhn and subhn instructions, which can actually be
3455 // written in LLVM IR without too much difficulty.
3458 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3459 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3460 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3462 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3463 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3465 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3466 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3467 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3469 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3470 V128:$Rn, V128:$Rm)>;
3471 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3472 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3474 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3475 V128:$Rn, V128:$Rm)>;
3476 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3477 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3479 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3480 V128:$Rn, V128:$Rm)>;
3483 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3484 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3485 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3487 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3488 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3490 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3491 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3492 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3494 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3495 V128:$Rn, V128:$Rm)>;
3496 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3497 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3499 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3500 V128:$Rn, V128:$Rm)>;
3501 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3502 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3504 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3505 V128:$Rn, V128:$Rm)>;
3507 //----------------------------------------------------------------------------
3508 // AdvSIMD bitwise extract from vector instruction.
3509 //----------------------------------------------------------------------------
3511 defm EXT : SIMDBitwiseExtract<"ext">;
3513 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3514 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3515 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3516 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3517 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3518 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3519 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3520 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3521 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3522 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3523 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3524 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3525 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3526 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3527 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3528 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3529 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3530 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3531 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3532 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3534 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3536 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3537 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3538 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3539 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3540 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3541 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3542 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3543 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3544 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3545 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3546 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3547 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3548 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3549 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3552 //----------------------------------------------------------------------------
3553 // AdvSIMD zip vector
3554 //----------------------------------------------------------------------------
3556 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3557 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3558 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3559 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3560 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3561 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3563 //----------------------------------------------------------------------------
3564 // AdvSIMD TBL/TBX instructions
3565 //----------------------------------------------------------------------------
3567 defm TBL : SIMDTableLookup< 0, "tbl">;
3568 defm TBX : SIMDTableLookupTied<1, "tbx">;
3570 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3571 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3572 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3573 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3575 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3576 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3577 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3578 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3579 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3580 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3583 //----------------------------------------------------------------------------
3584 // AdvSIMD scalar CPY instruction
3585 //----------------------------------------------------------------------------
3587 defm CPY : SIMDScalarCPY<"cpy">;
3589 //----------------------------------------------------------------------------
3590 // AdvSIMD scalar pairwise instructions
3591 //----------------------------------------------------------------------------
3593 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3594 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3595 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3596 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3597 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3598 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3599 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
3600 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3601 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),
3602 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3603 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3604 (FADDPv2i32p V64:$Rn)>;
3605 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3606 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3607 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3608 (FADDPv2i64p V128:$Rn)>;
3609 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3610 (FMAXNMPv2i32p V64:$Rn)>;
3611 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3612 (FMAXNMPv2i64p V128:$Rn)>;
3613 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3614 (FMAXPv2i32p V64:$Rn)>;
3615 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3616 (FMAXPv2i64p V128:$Rn)>;
3617 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3618 (FMINNMPv2i32p V64:$Rn)>;
3619 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3620 (FMINNMPv2i64p V128:$Rn)>;
3621 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3622 (FMINPv2i32p V64:$Rn)>;
3623 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3624 (FMINPv2i64p V128:$Rn)>;
3626 //----------------------------------------------------------------------------
3627 // AdvSIMD INS/DUP instructions
3628 //----------------------------------------------------------------------------
3630 def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>;
3631 def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>;
3632 def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>;
3633 def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>;
3634 def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>;
3635 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;
3636 def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>;
3638 def DUPv2i64lane : SIMDDup64FromElement;
3639 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3640 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3641 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3642 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3643 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3644 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3646 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3647 (v2f32 (DUPv2i32lane
3648 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3650 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3651 (v4f32 (DUPv4i32lane
3652 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3654 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3655 (v2f64 (DUPv2i64lane
3656 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3658 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3659 (v4f16 (DUPv4i16lane
3660 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3662 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3663 (v8f16 (DUPv8i16lane
3664 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3667 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3668 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3669 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3670 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3672 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3673 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3674 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3675 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3676 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3677 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3679 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3680 // instruction even if the types don't match: we just have to remap the lane
3681 // carefully. N.b. this trick only applies to truncations.
3682 def VecIndex_x2 : SDNodeXForm<imm, [{
3683 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64);
3685 def VecIndex_x4 : SDNodeXForm<imm, [{
3686 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64);
3688 def VecIndex_x8 : SDNodeXForm<imm, [{
3689 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64);
3692 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3693 ValueType Src128VT, ValueType ScalVT,
3694 Instruction DUP, SDNodeXForm IdxXFORM> {
3695 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3697 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3699 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3701 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3704 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3705 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3706 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3708 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3709 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3710 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3712 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3713 SDNodeXForm IdxXFORM> {
3714 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3716 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3718 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3720 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3723 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3724 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3725 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3727 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3728 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3729 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3731 // SMOV and UMOV definitions, with some extra patterns for convenience
3735 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3736 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3737 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3738 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3739 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3740 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3741 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3742 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3743 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3744 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3745 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3746 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3748 // Extracting i8 or i16 elements will have the zero-extend transformed to
3749 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3750 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3751 // bits of the destination register.
3752 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3754 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3755 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3757 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3761 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3762 (SUBREG_TO_REG (i32 0),
3763 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3764 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3765 (SUBREG_TO_REG (i32 0),
3766 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3768 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3769 (SUBREG_TO_REG (i32 0),
3770 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3771 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3772 (SUBREG_TO_REG (i32 0),
3773 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3775 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3776 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3777 (i32 FPR32:$Rn), ssub))>;
3778 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3779 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3780 (i32 FPR32:$Rn), ssub))>;
3781 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3782 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3783 (i64 FPR64:$Rn), dsub))>;
3785 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3786 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3787 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3788 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3789 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3790 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3792 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3793 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3796 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3798 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3802 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3803 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3805 V128:$Rn, VectorIndexH:$imm,
3806 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3809 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3810 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3813 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3815 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3818 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3819 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3821 V128:$Rn, VectorIndexS:$imm,
3822 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3824 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3825 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3827 V128:$Rn, VectorIndexD:$imm,
3828 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3831 // Copy an element at a constant index in one vector into a constant indexed
3832 // element of another.
3833 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3834 // index type and INS extension
3835 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3836 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3837 VectorIndexB:$idx2)),
3839 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3841 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3842 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3843 VectorIndexH:$idx2)),
3845 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3847 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3848 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3849 VectorIndexS:$idx2)),
3851 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3853 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3854 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3855 VectorIndexD:$idx2)),
3857 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3860 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3861 ValueType VTScal, Instruction INS> {
3862 def : Pat<(VT128 (vector_insert V128:$src,
3863 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3865 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3867 def : Pat<(VT128 (vector_insert V128:$src,
3868 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3870 (INS V128:$src, imm:$Immd,
3871 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3873 def : Pat<(VT64 (vector_insert V64:$src,
3874 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3876 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3877 imm:$Immd, V128:$Rn, imm:$Immn),
3880 def : Pat<(VT64 (vector_insert V64:$src,
3881 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3884 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3885 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3889 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3890 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3891 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3894 // Floating point vector extractions are codegen'd as either a sequence of
3895 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
3896 // the lane number is anything other than zero.
3897 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3898 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3899 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3900 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3901 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3902 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3904 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3905 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
3906 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3907 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
3908 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3909 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
3911 // All concat_vectors operations are canonicalised to act on i64 vectors for
3912 // AArch64. In the general case we need an instruction, which had just as well be
3914 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3915 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3916 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3917 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3919 def : ConcatPat<v2i64, v1i64>;
3920 def : ConcatPat<v2f64, v1f64>;
3921 def : ConcatPat<v4i32, v2i32>;
3922 def : ConcatPat<v4f32, v2f32>;
3923 def : ConcatPat<v8i16, v4i16>;
3924 def : ConcatPat<v8f16, v4f16>;
3925 def : ConcatPat<v16i8, v8i8>;
3927 // If the high lanes are undef, though, we can just ignore them:
3928 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3929 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3930 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3932 def : ConcatUndefPat<v2i64, v1i64>;
3933 def : ConcatUndefPat<v2f64, v1f64>;
3934 def : ConcatUndefPat<v4i32, v2i32>;
3935 def : ConcatUndefPat<v4f32, v2f32>;
3936 def : ConcatUndefPat<v8i16, v4i16>;
3937 def : ConcatUndefPat<v16i8, v8i8>;
3939 //----------------------------------------------------------------------------
3940 // AdvSIMD across lanes instructions
3941 //----------------------------------------------------------------------------
3943 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3944 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3945 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3946 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3947 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3948 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3949 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3950 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3951 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3952 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3953 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3955 // Patterns for across-vector intrinsics, that have a node equivalent, that
3956 // returns a vector (with only the low lane defined) instead of a scalar.
3957 // In effect, opNode is the same as (scalar_to_vector (IntNode)).
3958 multiclass SIMDAcrossLanesIntrinsic<string baseOpc,
3959 SDPatternOperator opNode> {
3960 // If a lane instruction caught the vector_extract around opNode, we can
3961 // directly match the latter to the instruction.
3962 def : Pat<(v8i8 (opNode V64:$Rn)),
3963 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3964 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;
3965 def : Pat<(v16i8 (opNode V128:$Rn)),
3966 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3967 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;
3968 def : Pat<(v4i16 (opNode V64:$Rn)),
3969 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3970 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;
3971 def : Pat<(v8i16 (opNode V128:$Rn)),
3972 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3973 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;
3974 def : Pat<(v4i32 (opNode V128:$Rn)),
3975 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3976 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;
3979 // If none did, fallback to the explicit patterns, consuming the vector_extract.
3980 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
3981 (i32 0)), (i64 0))),
3982 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3983 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),
3985 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
3986 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3987 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),
3989 def : Pat<(i32 (vector_extract (insert_subvector undef,
3990 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))),
3991 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3992 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),
3994 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
3995 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3996 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),
3998 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
3999 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4000 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),
4005 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,
4006 SDPatternOperator opNode>
4007 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4008 // If there is a sign extension after this intrinsic, consume it as smov already
4010 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4011 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)),
4013 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4014 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4016 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4017 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),
4019 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4020 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4022 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4023 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)),
4025 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4026 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4028 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4029 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),
4031 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4032 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4036 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
4037 SDPatternOperator opNode>
4038 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4039 // If there is a masking operation keeping only what has been actually
4040 // generated, consume it.
4041 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4042 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)),
4043 (i32 (EXTRACT_SUBREG
4044 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4045 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4047 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
4049 (i32 (EXTRACT_SUBREG
4050 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4051 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4053 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4054 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)),
4055 (i32 (EXTRACT_SUBREG
4056 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4057 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4059 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
4061 (i32 (EXTRACT_SUBREG
4062 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4063 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4067 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;
4068 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4069 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
4070 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4072 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;
4073 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4074 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
4075 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4077 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;
4078 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
4079 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
4081 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
4082 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
4083 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
4085 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;
4086 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
4087 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
4089 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
4090 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
4091 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
4093 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
4094 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4096 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4097 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4099 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4101 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4102 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4105 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4106 (i32 (EXTRACT_SUBREG
4107 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4108 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4110 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4111 (i32 (EXTRACT_SUBREG
4112 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4113 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4116 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4117 (i64 (EXTRACT_SUBREG
4118 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4119 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4123 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
4125 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4126 (i32 (EXTRACT_SUBREG
4127 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4128 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4130 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4131 (i32 (EXTRACT_SUBREG
4132 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4133 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4136 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4137 (i32 (EXTRACT_SUBREG
4138 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4139 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4141 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4142 (i32 (EXTRACT_SUBREG
4143 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4144 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4147 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4148 (i64 (EXTRACT_SUBREG
4149 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4150 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4154 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
4155 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
4157 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
4158 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
4159 (i64 (EXTRACT_SUBREG
4160 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4161 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
4163 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4164 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4165 (i64 (EXTRACT_SUBREG
4166 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4167 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4170 //------------------------------------------------------------------------------
4171 // AdvSIMD modified immediate instructions
4172 //------------------------------------------------------------------------------
4175 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4177 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4179 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4180 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4181 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4182 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4184 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4185 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4186 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4187 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4189 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4190 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4191 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4192 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4194 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4195 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4196 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4197 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4200 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
4202 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4203 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
4205 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4206 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
4208 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4212 // EDIT byte mask: scalar
4213 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4214 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4215 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4216 // The movi_edit node has the immediate value already encoded, so we use
4217 // a plain imm0_255 here.
4218 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4219 (MOVID imm0_255:$shift)>;
4221 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4222 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4223 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4224 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4226 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4227 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4228 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4229 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4231 // EDIT byte mask: 2d
4233 // The movi_edit node has the immediate value already encoded, so we use
4234 // a plain imm0_255 in the pattern
4235 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4236 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
4239 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4242 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4243 // Complexity is added to break a tie with a plain MOVI.
4244 let AddedComplexity = 1 in {
4245 def : Pat<(f32 fpimm0),
4246 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4248 def : Pat<(f64 fpimm0),
4249 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4253 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4254 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4255 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4256 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4258 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4259 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4260 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4261 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4263 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4264 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4266 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4267 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4269 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4270 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4271 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4272 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4274 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4275 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4276 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4277 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4279 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4280 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4281 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4282 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4283 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4284 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4285 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4286 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4288 // EDIT per word: 2s & 4s with MSL shifter
4289 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4290 [(set (v2i32 V64:$Rd),
4291 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4292 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4293 [(set (v4i32 V128:$Rd),
4294 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4296 // Per byte: 8b & 16b
4297 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4299 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4300 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4302 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4306 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4307 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4309 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4310 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4311 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4312 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4314 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4315 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4316 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4317 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4319 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4320 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4321 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4322 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4323 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4324 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4325 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4326 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4328 // EDIT per word: 2s & 4s with MSL shifter
4329 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4330 [(set (v2i32 V64:$Rd),
4331 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4332 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4333 [(set (v4i32 V128:$Rd),
4334 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4336 //----------------------------------------------------------------------------
4337 // AdvSIMD indexed element
4338 //----------------------------------------------------------------------------
4340 let hasSideEffects = 0 in {
4341 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
4342 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
4345 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4346 // instruction expects the addend first, while the intrinsic expects it last.
4348 // On the other hand, there are quite a few valid combinatorial options due to
4349 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4350 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4351 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4352 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4353 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4355 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4356 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4357 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4358 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4359 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4360 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4361 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4362 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4364 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4365 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4367 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4368 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4369 VectorIndexS:$idx))),
4370 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4371 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4372 (v2f32 (AArch64duplane32
4373 (v4f32 (insert_subvector undef,
4374 (v2f32 (fneg V64:$Rm)),
4376 VectorIndexS:$idx)))),
4377 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4378 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4379 VectorIndexS:$idx)>;
4380 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4381 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4382 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4383 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4385 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4387 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4388 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4389 VectorIndexS:$idx))),
4390 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4391 VectorIndexS:$idx)>;
4392 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4393 (v4f32 (AArch64duplane32
4394 (v4f32 (insert_subvector undef,
4395 (v2f32 (fneg V64:$Rm)),
4397 VectorIndexS:$idx)))),
4398 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4399 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4400 VectorIndexS:$idx)>;
4401 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4402 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4403 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4404 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4406 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4407 // (DUPLANE from 64-bit would be trivial).
4408 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4409 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4410 VectorIndexD:$idx))),
4412 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4413 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4414 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4415 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4416 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4418 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4419 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4420 (vector_extract (v4f32 (fneg V128:$Rm)),
4421 VectorIndexS:$idx))),
4422 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4423 V128:$Rm, VectorIndexS:$idx)>;
4424 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4425 (vector_extract (v2f32 (fneg V64:$Rm)),
4426 VectorIndexS:$idx))),
4427 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4428 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4430 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4431 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4432 (vector_extract (v2f64 (fneg V128:$Rm)),
4433 VectorIndexS:$idx))),
4434 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4435 V128:$Rm, VectorIndexS:$idx)>;
4438 defm : FMLSIndexedAfterNegPatterns<
4439 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4440 defm : FMLSIndexedAfterNegPatterns<
4441 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4443 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4444 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4446 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4447 (FMULv2i32_indexed V64:$Rn,
4448 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4450 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4451 (FMULv4i32_indexed V128:$Rn,
4452 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4454 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4455 (FMULv2i64_indexed V128:$Rn,
4456 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4459 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4460 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4461 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4462 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4463 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4464 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4465 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4466 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4467 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4468 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4469 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4470 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4471 int_aarch64_neon_smull>;
4472 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4473 int_aarch64_neon_sqadd>;
4474 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4475 int_aarch64_neon_sqsub>;
4476 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
4477 int_aarch64_neon_sqadd>;
4478 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
4479 int_aarch64_neon_sqsub>;
4480 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4481 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4482 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4483 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4484 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4485 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4486 int_aarch64_neon_umull>;
4488 // A scalar sqdmull with the second operand being a vector lane can be
4489 // handled directly with the indexed instruction encoding.
4490 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4491 (vector_extract (v4i32 V128:$Vm),
4492 VectorIndexS:$idx)),
4493 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4495 //----------------------------------------------------------------------------
4496 // AdvSIMD scalar shift instructions
4497 //----------------------------------------------------------------------------
4498 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4499 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4500 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4501 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4502 // Codegen patterns for the above. We don't put these directly on the
4503 // instructions because TableGen's type inference can't handle the truth.
4504 // Having the same base pattern for fp <--> int totally freaks it out.
4505 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4506 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4507 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4508 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4509 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4510 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4511 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4512 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4513 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4515 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4516 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4518 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4519 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4520 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4521 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4522 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4523 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4524 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4525 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4526 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4527 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4529 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4530 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4532 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4534 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4535 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4536 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4537 int_aarch64_neon_sqrshrn>;
4538 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4539 int_aarch64_neon_sqrshrun>;
4540 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4541 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4542 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4543 int_aarch64_neon_sqshrn>;
4544 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4545 int_aarch64_neon_sqshrun>;
4546 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4547 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4548 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4549 TriOpFrag<(add node:$LHS,
4550 (AArch64srshri node:$MHS, node:$RHS))>>;
4551 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4552 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4553 TriOpFrag<(add node:$LHS,
4554 (AArch64vashr node:$MHS, node:$RHS))>>;
4555 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4556 int_aarch64_neon_uqrshrn>;
4557 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4558 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4559 int_aarch64_neon_uqshrn>;
4560 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4561 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4562 TriOpFrag<(add node:$LHS,
4563 (AArch64urshri node:$MHS, node:$RHS))>>;
4564 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4565 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4566 TriOpFrag<(add node:$LHS,
4567 (AArch64vlshr node:$MHS, node:$RHS))>>;
4569 //----------------------------------------------------------------------------
4570 // AdvSIMD vector shift instructions
4571 //----------------------------------------------------------------------------
4572 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4573 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4574 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4575 int_aarch64_neon_vcvtfxs2fp>;
4576 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4577 int_aarch64_neon_rshrn>;
4578 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4579 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4580 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4581 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4582 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4583 (i32 vecshiftL64:$imm))),
4584 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4585 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4586 int_aarch64_neon_sqrshrn>;
4587 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4588 int_aarch64_neon_sqrshrun>;
4589 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4590 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4591 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4592 int_aarch64_neon_sqshrn>;
4593 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4594 int_aarch64_neon_sqshrun>;
4595 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4596 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4597 (i32 vecshiftR64:$imm))),
4598 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4599 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4600 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4601 TriOpFrag<(add node:$LHS,
4602 (AArch64srshri node:$MHS, node:$RHS))> >;
4603 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4604 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4606 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4607 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4608 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4609 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4610 int_aarch64_neon_vcvtfxu2fp>;
4611 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4612 int_aarch64_neon_uqrshrn>;
4613 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4614 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4615 int_aarch64_neon_uqshrn>;
4616 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4617 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4618 TriOpFrag<(add node:$LHS,
4619 (AArch64urshri node:$MHS, node:$RHS))> >;
4620 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4621 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4622 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4623 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4624 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4626 // SHRN patterns for when a logical right shift was used instead of arithmetic
4627 // (the immediate guarantees no sign bits actually end up in the result so it
4629 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4630 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4631 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4632 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4633 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4634 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4636 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4637 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4638 vecshiftR16Narrow:$imm)))),
4639 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4640 V128:$Rn, vecshiftR16Narrow:$imm)>;
4641 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4642 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4643 vecshiftR32Narrow:$imm)))),
4644 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4645 V128:$Rn, vecshiftR32Narrow:$imm)>;
4646 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4647 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4648 vecshiftR64Narrow:$imm)))),
4649 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4650 V128:$Rn, vecshiftR32Narrow:$imm)>;
4652 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4653 // Anyexts are implemented as zexts.
4654 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4655 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4656 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4657 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4658 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4659 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4660 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4661 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4662 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4663 // Also match an extend from the upper half of a 128 bit source register.
4664 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4665 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4666 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4667 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4668 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4669 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4670 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4671 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4672 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4673 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4674 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4675 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4676 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4677 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4678 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4679 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4680 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4681 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4683 // Vector shift sxtl aliases
4684 def : InstAlias<"sxtl.8h $dst, $src1",
4685 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4686 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4687 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4688 def : InstAlias<"sxtl.4s $dst, $src1",
4689 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4690 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4691 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4692 def : InstAlias<"sxtl.2d $dst, $src1",
4693 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4694 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4695 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4697 // Vector shift sxtl2 aliases
4698 def : InstAlias<"sxtl2.8h $dst, $src1",
4699 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4700 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4701 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4702 def : InstAlias<"sxtl2.4s $dst, $src1",
4703 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4704 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4705 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4706 def : InstAlias<"sxtl2.2d $dst, $src1",
4707 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4708 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4709 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4711 // Vector shift uxtl aliases
4712 def : InstAlias<"uxtl.8h $dst, $src1",
4713 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4714 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4715 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4716 def : InstAlias<"uxtl.4s $dst, $src1",
4717 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4718 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4719 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4720 def : InstAlias<"uxtl.2d $dst, $src1",
4721 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4722 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4723 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4725 // Vector shift uxtl2 aliases
4726 def : InstAlias<"uxtl2.8h $dst, $src1",
4727 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4728 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4729 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4730 def : InstAlias<"uxtl2.4s $dst, $src1",
4731 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4732 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4733 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4734 def : InstAlias<"uxtl2.2d $dst, $src1",
4735 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4736 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4737 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4739 // If an integer is about to be converted to a floating point value,
4740 // just load it on the floating point unit.
4741 // These patterns are more complex because floating point loads do not
4742 // support sign extension.
4743 // The sign extension has to be explicitly added and is only supported for
4744 // one step: byte-to-half, half-to-word, word-to-doubleword.
4745 // SCVTF GPR -> FPR is 9 cycles.
4746 // SCVTF FPR -> FPR is 4 cyclces.
4747 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4748 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4749 // and still being faster.
4750 // However, this is not good for code size.
4751 // 8-bits -> float. 2 sizes step-up.
4752 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4753 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4754 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4759 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4765 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4767 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4768 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4769 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4770 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4771 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4772 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4773 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4774 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4776 // 16-bits -> float. 1 size step-up.
4777 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4778 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4779 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4781 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4785 ssub)))>, Requires<[NotForCodeSize]>;
4787 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4788 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4789 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4790 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4791 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4792 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4793 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4794 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4796 // 32-bits to 32-bits are handled in target specific dag combine:
4797 // performIntToFpCombine.
4798 // 64-bits integer to 32-bits floating point, not possible with
4799 // SCVTF on floating point registers (both source and destination
4800 // must have the same size).
4802 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4803 // 8-bits -> double. 3 size step-up: give up.
4804 // 16-bits -> double. 2 size step.
4805 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4806 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4807 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4812 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4818 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4820 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4821 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4822 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4823 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4824 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4825 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4826 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4827 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4828 // 32-bits -> double. 1 size step-up.
4829 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4830 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4831 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4833 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4837 dsub)))>, Requires<[NotForCodeSize]>;
4839 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4840 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4841 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4842 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4843 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4844 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4845 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4846 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4848 // 64-bits -> double are handled in target specific dag combine:
4849 // performIntToFpCombine.
4852 //----------------------------------------------------------------------------
4853 // AdvSIMD Load-Store Structure
4854 //----------------------------------------------------------------------------
4855 defm LD1 : SIMDLd1Multiple<"ld1">;
4856 defm LD2 : SIMDLd2Multiple<"ld2">;
4857 defm LD3 : SIMDLd3Multiple<"ld3">;
4858 defm LD4 : SIMDLd4Multiple<"ld4">;
4860 defm ST1 : SIMDSt1Multiple<"st1">;
4861 defm ST2 : SIMDSt2Multiple<"st2">;
4862 defm ST3 : SIMDSt3Multiple<"st3">;
4863 defm ST4 : SIMDSt4Multiple<"st4">;
4865 class Ld1Pat<ValueType ty, Instruction INST>
4866 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4868 def : Ld1Pat<v16i8, LD1Onev16b>;
4869 def : Ld1Pat<v8i16, LD1Onev8h>;
4870 def : Ld1Pat<v4i32, LD1Onev4s>;
4871 def : Ld1Pat<v2i64, LD1Onev2d>;
4872 def : Ld1Pat<v8i8, LD1Onev8b>;
4873 def : Ld1Pat<v4i16, LD1Onev4h>;
4874 def : Ld1Pat<v2i32, LD1Onev2s>;
4875 def : Ld1Pat<v1i64, LD1Onev1d>;
4877 class St1Pat<ValueType ty, Instruction INST>
4878 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4879 (INST ty:$Vt, GPR64sp:$Rn)>;
4881 def : St1Pat<v16i8, ST1Onev16b>;
4882 def : St1Pat<v8i16, ST1Onev8h>;
4883 def : St1Pat<v4i32, ST1Onev4s>;
4884 def : St1Pat<v2i64, ST1Onev2d>;
4885 def : St1Pat<v8i8, ST1Onev8b>;
4886 def : St1Pat<v4i16, ST1Onev4h>;
4887 def : St1Pat<v2i32, ST1Onev2s>;
4888 def : St1Pat<v1i64, ST1Onev1d>;
4894 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4895 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4896 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4897 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4898 let mayLoad = 1, hasSideEffects = 0 in {
4899 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4900 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4901 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4902 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4903 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4904 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4905 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4906 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4907 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4908 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4909 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4910 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4911 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4912 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4913 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4914 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4917 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4918 (LD1Rv8b GPR64sp:$Rn)>;
4919 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4920 (LD1Rv16b GPR64sp:$Rn)>;
4921 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4922 (LD1Rv4h GPR64sp:$Rn)>;
4923 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4924 (LD1Rv8h GPR64sp:$Rn)>;
4925 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4926 (LD1Rv2s GPR64sp:$Rn)>;
4927 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4928 (LD1Rv4s GPR64sp:$Rn)>;
4929 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4930 (LD1Rv2d GPR64sp:$Rn)>;
4931 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4932 (LD1Rv1d GPR64sp:$Rn)>;
4933 // Grab the floating point version too
4934 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4935 (LD1Rv2s GPR64sp:$Rn)>;
4936 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4937 (LD1Rv4s GPR64sp:$Rn)>;
4938 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4939 (LD1Rv2d GPR64sp:$Rn)>;
4940 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4941 (LD1Rv1d GPR64sp:$Rn)>;
4942 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4943 (LD1Rv4h GPR64sp:$Rn)>;
4944 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4945 (LD1Rv8h GPR64sp:$Rn)>;
4947 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4948 ValueType VTy, ValueType STy, Instruction LD1>
4949 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4950 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4951 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4953 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4954 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4955 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4956 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4957 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4958 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4959 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4961 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4962 ValueType VTy, ValueType STy, Instruction LD1>
4963 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4964 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4966 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4967 VecIndex:$idx, GPR64sp:$Rn),
4970 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4971 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4972 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4973 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4974 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4977 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4978 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4979 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4980 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4983 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4984 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4985 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4986 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4988 let AddedComplexity = 19 in
4989 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4990 ValueType VTy, ValueType STy, Instruction ST1>
4992 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4994 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4996 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4997 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4998 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4999 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
5000 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
5001 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
5002 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
5004 let AddedComplexity = 19 in
5005 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5006 ValueType VTy, ValueType STy, Instruction ST1>
5008 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5010 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5011 VecIndex:$idx, GPR64sp:$Rn)>;
5013 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
5014 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
5015 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
5016 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
5017 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
5019 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5020 ValueType VTy, ValueType STy, Instruction ST1,
5022 def : Pat<(scalar_store
5023 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5024 GPR64sp:$Rn, offset),
5025 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5026 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5028 def : Pat<(scalar_store
5029 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5030 GPR64sp:$Rn, GPR64:$Rm),
5031 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5032 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5035 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
5036 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
5038 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
5039 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
5040 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
5041 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
5042 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
5044 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5045 ValueType VTy, ValueType STy, Instruction ST1,
5047 def : Pat<(scalar_store
5048 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5049 GPR64sp:$Rn, offset),
5050 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5052 def : Pat<(scalar_store
5053 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5054 GPR64sp:$Rn, GPR64:$Rm),
5055 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5058 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
5060 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
5062 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
5063 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
5064 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
5065 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
5066 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
5068 let mayStore = 1, hasSideEffects = 0 in {
5069 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
5070 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
5071 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
5072 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
5073 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
5074 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
5075 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
5076 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
5077 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
5078 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
5079 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
5080 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
5083 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
5084 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
5085 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
5086 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
5088 //----------------------------------------------------------------------------
5089 // Crypto extensions
5090 //----------------------------------------------------------------------------
5092 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
5093 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
5094 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
5095 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
5097 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
5098 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
5099 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
5100 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
5101 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
5102 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
5103 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
5105 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
5106 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
5107 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
5109 //----------------------------------------------------------------------------
5111 //----------------------------------------------------------------------------
5112 // FIXME: Like for X86, these should go in their own separate .td file.
5114 // Any instruction that defines a 32-bit result leaves the high half of the
5115 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
5116 // be copying from a truncate. But any other 32-bit operation will zero-extend
5118 // FIXME: X86 also checks for CMOV here. Do we need something similar?
5119 def def32 : PatLeaf<(i32 GPR32:$src), [{
5120 return N->getOpcode() != ISD::TRUNCATE &&
5121 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
5122 N->getOpcode() != ISD::CopyFromReg;
5125 // In the case of a 32-bit def that is known to implicitly zero-extend,
5126 // we can use a SUBREG_TO_REG.
5127 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
5129 // For an anyext, we don't care what the high bits are, so we can perform an
5130 // INSERT_SUBREF into an IMPLICIT_DEF.
5131 def : Pat<(i64 (anyext GPR32:$src)),
5132 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
5134 // When we need to explicitly zero-extend, we use an unsigned bitfield move
5135 // instruction (UBFM) on the enclosing super-reg.
5136 def : Pat<(i64 (zext GPR32:$src)),
5137 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5139 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
5140 // containing super-reg.
5141 def : Pat<(i64 (sext GPR32:$src)),
5142 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5143 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
5144 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
5145 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
5146 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
5147 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
5148 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
5149 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
5151 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
5152 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5153 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
5154 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
5155 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5156 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
5158 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
5159 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5160 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
5161 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
5162 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5163 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
5165 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
5166 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5167 (i64 (i64shift_a imm0_63:$imm)),
5168 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
5170 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
5171 // AddedComplexity for the following patterns since we want to match sext + sra
5172 // patterns before we attempt to match a single sra node.
5173 let AddedComplexity = 20 in {
5174 // We support all sext + sra combinations which preserve at least one bit of the
5175 // original value which is to be sign extended. E.g. we support shifts up to
5177 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
5178 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
5179 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
5180 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
5182 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
5183 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
5184 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
5185 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
5187 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
5188 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5189 (i64 imm0_31:$imm), 31)>;
5190 } // AddedComplexity = 20
5192 // To truncate, we can simply extract from a subregister.
5193 def : Pat<(i32 (trunc GPR64sp:$src)),
5194 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5196 // __builtin_trap() uses the BRK instruction on AArch64.
5197 def : Pat<(trap), (BRK 1)>;
5199 // Conversions within AdvSIMD types in the same register size are free.
5200 // But because we need a consistent lane ordering, in big endian many
5201 // conversions require one or more REV instructions.
5203 // Consider a simple memory load followed by a bitconvert then a store.
5205 // v1 = BITCAST v2i32 v0 to v4i16
5208 // In big endian mode every memory access has an implicit byte swap. LDR and
5209 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5210 // is, they treat the vector as a sequence of elements to be byte-swapped.
5211 // The two pairs of instructions are fundamentally incompatible. We've decided
5212 // to use LD1/ST1 only to simplify compiler implementation.
5214 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5215 // the original code sequence:
5217 // v1 = REV v2i32 (implicit)
5218 // v2 = BITCAST v2i32 v1 to v4i16
5219 // v3 = REV v4i16 v2 (implicit)
5222 // But this is now broken - the value stored is different to the value loaded
5223 // due to lane reordering. To fix this, on every BITCAST we must perform two
5226 // v1 = REV v2i32 (implicit)
5228 // v3 = BITCAST v2i32 v2 to v4i16
5230 // v5 = REV v4i16 v4 (implicit)
5233 // This means an extra two instructions, but actually in most cases the two REV
5234 // instructions can be combined into one. For example:
5235 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5237 // There is also no 128-bit REV instruction. This must be synthesized with an
5240 // Most bitconverts require some sort of conversion. The only exceptions are:
5241 // a) Identity conversions - vNfX <-> vNiX
5242 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5245 // Natural vector casts (64 bit)
5246 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5247 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5248 def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5249 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5250 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5251 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5253 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5254 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5255 def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5256 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5257 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5259 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5260 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5261 def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5262 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5263 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5265 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5266 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5267 def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5268 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5269 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5270 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5271 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5273 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5274 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5275 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5276 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5277 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5279 // Natural vector casts (128 bit)
5280 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5281 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5282 def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5283 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5284 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5285 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5287 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5288 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5289 def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5290 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5291 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5293 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5294 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5295 def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5296 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5297 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5299 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5300 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5301 def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5302 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5303 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5304 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5305 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5307 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5308 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5309 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5310 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5311 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5313 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5314 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5315 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5316 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5317 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5319 let Predicates = [IsLE] in {
5320 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5321 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5322 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5323 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5324 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5326 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5327 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5328 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5329 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5330 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5331 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5332 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5333 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5334 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5335 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5336 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5337 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5339 let Predicates = [IsBE] in {
5340 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5341 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5342 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5343 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5344 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5345 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5346 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5347 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5348 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5349 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5351 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5352 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5353 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5354 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5355 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5356 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5357 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5358 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5359 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5360 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5362 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5363 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5364 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5365 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5366 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5367 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5368 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5369 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5370 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5372 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5373 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5374 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5375 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5376 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5377 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5378 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5379 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5380 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5381 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5383 let Predicates = [IsLE] in {
5384 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5385 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5386 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5387 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5388 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5390 let Predicates = [IsBE] in {
5391 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5392 (v1i64 (REV64v2i32 FPR64:$src))>;
5393 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5394 (v1i64 (REV64v4i16 FPR64:$src))>;
5395 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5396 (v1i64 (REV64v8i8 FPR64:$src))>;
5397 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5398 (v1i64 (REV64v4i16 FPR64:$src))>;
5399 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5400 (v1i64 (REV64v2i32 FPR64:$src))>;
5402 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5403 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5405 let Predicates = [IsLE] in {
5406 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5407 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5408 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5409 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5410 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5411 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5413 let Predicates = [IsBE] in {
5414 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5415 (v2i32 (REV64v2i32 FPR64:$src))>;
5416 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5417 (v2i32 (REV32v4i16 FPR64:$src))>;
5418 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5419 (v2i32 (REV32v8i8 FPR64:$src))>;
5420 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5421 (v2i32 (REV64v2i32 FPR64:$src))>;
5422 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5423 (v2i32 (REV64v2i32 FPR64:$src))>;
5424 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5425 (v2i32 (REV64v4i16 FPR64:$src))>;
5427 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5429 let Predicates = [IsLE] in {
5430 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5431 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5432 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5433 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5434 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5435 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5436 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5438 let Predicates = [IsBE] in {
5439 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5440 (v4i16 (REV64v4i16 FPR64:$src))>;
5441 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5442 (v4i16 (REV32v4i16 FPR64:$src))>;
5443 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5444 (v4i16 (REV16v8i8 FPR64:$src))>;
5445 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5446 (v4i16 (REV64v4i16 FPR64:$src))>;
5447 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5448 (v4i16 (REV32v4i16 FPR64:$src))>;
5449 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5450 (v4i16 (REV32v4i16 FPR64:$src))>;
5451 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5452 (v4i16 (REV64v4i16 FPR64:$src))>;
5455 let Predicates = [IsLE] in {
5456 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5457 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5458 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5459 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5460 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5461 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5462 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5464 let Predicates = [IsBE] in {
5465 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5466 (v4f16 (REV64v4i16 FPR64:$src))>;
5467 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5468 (v4f16 (REV64v4i16 FPR64:$src))>;
5469 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5470 (v4f16 (REV64v4i16 FPR64:$src))>;
5471 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5472 (v4f16 (REV16v8i8 FPR64:$src))>;
5473 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5474 (v4f16 (REV64v4i16 FPR64:$src))>;
5475 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5476 (v4f16 (REV64v4i16 FPR64:$src))>;
5477 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5478 (v4f16 (REV64v4i16 FPR64:$src))>;
5483 let Predicates = [IsLE] in {
5484 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5485 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5486 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5487 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5488 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5489 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5490 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5492 let Predicates = [IsBE] in {
5493 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5494 (v8i8 (REV64v8i8 FPR64:$src))>;
5495 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5496 (v8i8 (REV32v8i8 FPR64:$src))>;
5497 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5498 (v8i8 (REV16v8i8 FPR64:$src))>;
5499 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5500 (v8i8 (REV64v8i8 FPR64:$src))>;
5501 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5502 (v8i8 (REV32v8i8 FPR64:$src))>;
5503 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5504 (v8i8 (REV64v8i8 FPR64:$src))>;
5505 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5506 (v8i8 (REV16v8i8 FPR64:$src))>;
5509 let Predicates = [IsLE] in {
5510 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5511 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5512 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5513 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5514 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5516 let Predicates = [IsBE] in {
5517 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5518 (f64 (REV64v2i32 FPR64:$src))>;
5519 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5520 (f64 (REV64v4i16 FPR64:$src))>;
5521 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5522 (f64 (REV64v2i32 FPR64:$src))>;
5523 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5524 (f64 (REV64v8i8 FPR64:$src))>;
5525 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5526 (f64 (REV64v4i16 FPR64:$src))>;
5528 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5529 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5531 let Predicates = [IsLE] in {
5532 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5533 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5534 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5535 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5536 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5538 let Predicates = [IsBE] in {
5539 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5540 (v1f64 (REV64v2i32 FPR64:$src))>;
5541 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5542 (v1f64 (REV64v4i16 FPR64:$src))>;
5543 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5544 (v1f64 (REV64v8i8 FPR64:$src))>;
5545 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5546 (v1f64 (REV64v2i32 FPR64:$src))>;
5547 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5548 (v1f64 (REV64v4i16 FPR64:$src))>;
5550 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5551 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5553 let Predicates = [IsLE] in {
5554 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5555 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5556 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5557 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5558 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5559 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5561 let Predicates = [IsBE] in {
5562 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5563 (v2f32 (REV64v2i32 FPR64:$src))>;
5564 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5565 (v2f32 (REV32v4i16 FPR64:$src))>;
5566 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5567 (v2f32 (REV32v8i8 FPR64:$src))>;
5568 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5569 (v2f32 (REV64v2i32 FPR64:$src))>;
5570 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5571 (v2f32 (REV64v2i32 FPR64:$src))>;
5572 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5573 (v2f32 (REV64v4i16 FPR64:$src))>;
5575 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5577 let Predicates = [IsLE] in {
5578 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5579 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5580 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5581 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5582 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5583 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5584 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5586 let Predicates = [IsBE] in {
5587 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5588 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5589 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5590 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5591 (REV64v4i32 FPR128:$src), (i32 8)))>;
5592 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5593 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5594 (REV64v8i16 FPR128:$src), (i32 8)))>;
5595 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5596 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5597 (REV64v8i16 FPR128:$src), (i32 8)))>;
5598 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5599 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5600 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5601 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5602 (REV64v4i32 FPR128:$src), (i32 8)))>;
5603 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5604 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5605 (REV64v16i8 FPR128:$src), (i32 8)))>;
5608 let Predicates = [IsLE] in {
5609 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5610 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5611 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5612 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5613 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5614 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5616 let Predicates = [IsBE] in {
5617 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5618 (v2f64 (EXTv16i8 FPR128:$src,
5619 FPR128:$src, (i32 8)))>;
5620 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5621 (v2f64 (REV64v4i32 FPR128:$src))>;
5622 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5623 (v2f64 (REV64v8i16 FPR128:$src))>;
5624 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5625 (v2f64 (REV64v8i16 FPR128:$src))>;
5626 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5627 (v2f64 (REV64v16i8 FPR128:$src))>;
5628 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5629 (v2f64 (REV64v4i32 FPR128:$src))>;
5631 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5633 let Predicates = [IsLE] in {
5634 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5635 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5636 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5637 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5638 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5639 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5641 let Predicates = [IsBE] in {
5642 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5643 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5644 (REV64v4i32 FPR128:$src), (i32 8)))>;
5645 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5646 (v4f32 (REV32v8i16 FPR128:$src))>;
5647 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5648 (v4f32 (REV32v8i16 FPR128:$src))>;
5649 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5650 (v4f32 (REV32v16i8 FPR128:$src))>;
5651 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5652 (v4f32 (REV64v4i32 FPR128:$src))>;
5653 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5654 (v4f32 (REV64v4i32 FPR128:$src))>;
5656 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5658 let Predicates = [IsLE] in {
5659 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5660 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5661 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5662 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5663 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5664 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5666 let Predicates = [IsBE] in {
5667 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5668 (v2i64 (EXTv16i8 FPR128:$src,
5669 FPR128:$src, (i32 8)))>;
5670 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5671 (v2i64 (REV64v4i32 FPR128:$src))>;
5672 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5673 (v2i64 (REV64v8i16 FPR128:$src))>;
5674 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5675 (v2i64 (REV64v16i8 FPR128:$src))>;
5676 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5677 (v2i64 (REV64v4i32 FPR128:$src))>;
5678 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5679 (v2i64 (REV64v8i16 FPR128:$src))>;
5681 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5683 let Predicates = [IsLE] in {
5684 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5685 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5686 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5687 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5688 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5689 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5691 let Predicates = [IsBE] in {
5692 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5693 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5694 (REV64v4i32 FPR128:$src),
5696 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5697 (v4i32 (REV64v4i32 FPR128:$src))>;
5698 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5699 (v4i32 (REV32v8i16 FPR128:$src))>;
5700 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5701 (v4i32 (REV32v16i8 FPR128:$src))>;
5702 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5703 (v4i32 (REV64v4i32 FPR128:$src))>;
5704 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5705 (v4i32 (REV32v8i16 FPR128:$src))>;
5707 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5709 let Predicates = [IsLE] in {
5710 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5711 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5712 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5713 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5714 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5715 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5716 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5718 let Predicates = [IsBE] in {
5719 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5720 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5721 (REV64v8i16 FPR128:$src),
5723 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5724 (v8i16 (REV64v8i16 FPR128:$src))>;
5725 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5726 (v8i16 (REV32v8i16 FPR128:$src))>;
5727 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5728 (v8i16 (REV16v16i8 FPR128:$src))>;
5729 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5730 (v8i16 (REV64v8i16 FPR128:$src))>;
5731 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5732 (v8i16 (REV32v8i16 FPR128:$src))>;
5733 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5734 (v8i16 (REV32v8i16 FPR128:$src))>;
5737 let Predicates = [IsLE] in {
5738 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5739 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5740 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5741 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5742 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5743 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5744 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5746 let Predicates = [IsBE] in {
5747 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5748 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5749 (REV64v8i16 FPR128:$src),
5751 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5752 (v8f16 (REV64v8i16 FPR128:$src))>;
5753 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5754 (v8f16 (REV32v8i16 FPR128:$src))>;
5755 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5756 (v8f16 (REV64v8i16 FPR128:$src))>;
5757 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5758 (v8f16 (REV16v16i8 FPR128:$src))>;
5759 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5760 (v8f16 (REV64v8i16 FPR128:$src))>;
5761 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5762 (v8f16 (REV32v8i16 FPR128:$src))>;
5765 let Predicates = [IsLE] in {
5766 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5767 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5768 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5769 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5770 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5771 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5772 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5774 let Predicates = [IsBE] in {
5775 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5776 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5777 (REV64v16i8 FPR128:$src),
5779 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5780 (v16i8 (REV64v16i8 FPR128:$src))>;
5781 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5782 (v16i8 (REV32v16i8 FPR128:$src))>;
5783 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5784 (v16i8 (REV16v16i8 FPR128:$src))>;
5785 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5786 (v16i8 (REV64v16i8 FPR128:$src))>;
5787 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5788 (v16i8 (REV32v16i8 FPR128:$src))>;
5789 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5790 (v16i8 (REV16v16i8 FPR128:$src))>;
5793 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5794 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5795 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5796 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5797 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5798 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5799 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5800 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5802 // A 64-bit subvector insert to the first 128-bit vector position
5803 // is a subregister copy that needs no instruction.
5804 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5805 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5806 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5807 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5808 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5809 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5810 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5811 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5812 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5813 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5814 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5815 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5816 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5817 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5819 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5821 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5822 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5823 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5824 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5825 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5826 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5827 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5828 // so we match on v4f32 here, not v2f32. This will also catch adding
5829 // the low two lanes of a true v4f32 vector.
5830 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5831 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5832 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5834 // Scalar 64-bit shifts in FPR64 registers.
5835 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5836 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5837 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5838 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5839 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5840 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5841 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5842 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5844 // Tail call return handling. These are all compiler pseudo-instructions,
5845 // so no encoding information or anything like that.
5846 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5847 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5848 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5851 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5852 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5853 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5854 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5855 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5856 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5858 include "AArch64InstrAtomics.td"