1 //===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 scalar instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "AArch64InstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Target-specific ISD nodes and profiles
18 //===----------------------------------------------------------------------===//
20 def SDT_A64ret : SDTypeProfile<0, 0, []>;
21 def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain,
25 // (ins NZCV, Condition, Dest)
26 def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>;
27 def A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>;
29 // (outs Result), (ins NZCV, IfTrue, IfFalse, Condition)
30 def SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>,
33 def A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>;
35 // (outs NZCV), (ins LHS, RHS, Condition)
36 def SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
38 def A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>;
41 // (outs GPR64), (ins)
42 def A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
44 // A64 compares don't care about the cond really (they set all flags) so a
45 // simple binary operator is useful.
46 def A64cmp : PatFrag<(ops node:$lhs, node:$rhs),
47 (A64setcc node:$lhs, node:$rhs, cond)>;
50 // When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN
51 // instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C
52 // and V flags can be set differently by this operation. It comes down to
53 // whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are
54 // then everything is fine. If not then the optimization is wrong. Thus general
55 // comparisons are only valid if op2 != 0.
57 // So, finally, the only LLVM-native comparisons that don't mention C and V are
58 // SETEQ and SETNE. They're the only ones we can safely use CMN for in the
59 // absence of information about op2.
60 def equality_cond : PatLeaf<(cond), [{
61 return N->get() == ISD::SETEQ || N->get() == ISD::SETNE;
64 def A64cmn : PatFrag<(ops node:$lhs, node:$rhs),
65 (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>;
67 // There are two layers of indirection here, driven by the following
69 // + TableGen does not know CodeModel or Reloc so that decision should be
70 // made for a variable/address at ISelLowering.
71 // + The output of ISelLowering should be selectable (hence the Wrapper,
72 // rather than a bare target opcode)
73 def SDTAArch64WrapperLarge : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
79 def A64WrapperLarge :SDNode<"AArch64ISD::WrapperLarge", SDTAArch64WrapperLarge>;
81 def SDTAArch64WrapperSmall : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
86 def A64WrapperSmall :SDNode<"AArch64ISD::WrapperSmall", SDTAArch64WrapperSmall>;
89 def SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
90 def A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad,
94 // (A64BFI LHS, RHS, LSB, Width)
95 def SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
100 def A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>;
102 // (A64EXTR HiReg, LoReg, LSB)
103 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
105 def A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
107 // (A64[SU]BFX Field, ImmR, ImmS).
109 // Note that ImmR and ImmS are already encoded for the actual instructions. The
110 // more natural LSB and Width mix together to form ImmR and ImmS, something
111 // which TableGen can't handle.
112 def SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>;
113 def A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>;
115 def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>;
117 //===----------------------------------------------------------------------===//
118 // Call sequence pseudo-instructions
119 //===----------------------------------------------------------------------===//
122 def SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
123 def AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call,
124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
126 def AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call,
127 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
129 // The TLSDESCCALL node is a variant call which goes to an indirectly calculated
130 // destination but needs a relocation against a fixed symbol. As such it has two
131 // certain operands: the callee and the relocated variable.
133 // The TLS ABI only allows it to be selected to a BLR instructin (with
134 // appropriate relocation).
135 def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
137 def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall,
138 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
142 def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>;
143 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart,
144 [SDNPHasChain, SDNPOutGlue]>;
146 def SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>;
147 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
152 // These pseudo-instructions have special semantics by virtue of being passed to
153 // the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by
154 // LowerCall to (in our case) tell the back-end about stack adjustments for
155 // arguments passed on the stack. Here we select those markers to
156 // pseudo-instructions which explicitly set the stack, and finally in the
157 // RegisterInfo we convert them to a true stack adjustment.
158 let Defs = [XSP], Uses = [XSP] in {
159 def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt),
160 [(AArch64callseq_start timm:$amt)]>;
162 def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2),
163 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
166 //===----------------------------------------------------------------------===//
167 // Atomic operation pseudo-instructions
168 //===----------------------------------------------------------------------===//
170 // These get selected from C++ code as a pretty much direct translation from the
171 // generic DAG nodes. The one exception is the AtomicOrdering is added as an
172 // operand so that the eventual lowering can make use of it and choose
173 // acquire/release operations when required.
175 let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in {
176 multiclass AtomicSizes {
177 def _I8 : PseudoInst<(outs GPR32:$dst),
178 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
179 def _I16 : PseudoInst<(outs GPR32:$dst),
180 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
181 def _I32 : PseudoInst<(outs GPR32:$dst),
182 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
183 def _I64 : PseudoInst<(outs GPR64:$dst),
184 (ins GPR64xsp:$ptr, GPR64:$incr, i32imm:$ordering), []>;
188 defm ATOMIC_LOAD_ADD : AtomicSizes;
189 defm ATOMIC_LOAD_SUB : AtomicSizes;
190 defm ATOMIC_LOAD_AND : AtomicSizes;
191 defm ATOMIC_LOAD_OR : AtomicSizes;
192 defm ATOMIC_LOAD_XOR : AtomicSizes;
193 defm ATOMIC_LOAD_NAND : AtomicSizes;
194 defm ATOMIC_SWAP : AtomicSizes;
195 let Defs = [NZCV] in {
196 // These operations need a CMP to calculate the correct value
197 defm ATOMIC_LOAD_MIN : AtomicSizes;
198 defm ATOMIC_LOAD_MAX : AtomicSizes;
199 defm ATOMIC_LOAD_UMIN : AtomicSizes;
200 defm ATOMIC_LOAD_UMAX : AtomicSizes;
203 class AtomicCmpSwap<RegisterClass GPRData>
204 : PseudoInst<(outs GPRData:$dst),
205 (ins GPR64xsp:$ptr, GPRData:$old, GPRData:$new,
206 i32imm:$ordering), []> {
207 let usesCustomInserter = 1;
214 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>;
215 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>;
216 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>;
217 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>;
219 //===----------------------------------------------------------------------===//
220 // Add-subtract (extended register) instructions
221 //===----------------------------------------------------------------------===//
222 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP
224 // The RHS of these operations is conceptually a sign/zero-extended
225 // register, optionally shifted left by 1-4. The extension can be a
226 // NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but
227 // must be specified with one exception:
229 // If one of the registers is sp/wsp then LSL is an alias for UXTW in
230 // 32-bit instructions and UXTX in 64-bit versions, the shift amount
231 // is not optional in that case (but can explicitly be 0), and the
232 // entire suffix can be skipped (e.g. "add sp, x3, x2").
234 multiclass extend_operands<string PREFIX, string Diag> {
235 def _asmoperand : AsmOperandClass {
237 let RenderMethod = "addRegExtendOperands";
238 let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">";
239 let DiagnosticType = "AddSubRegExtend" # Diag;
242 def _operand : Operand<i64>,
243 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> {
244 let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">";
245 let DecoderMethod = "DecodeRegExtendOperand";
246 let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand");
250 defm UXTB : extend_operands<"UXTB", "Small">;
251 defm UXTH : extend_operands<"UXTH", "Small">;
252 defm UXTW : extend_operands<"UXTW", "Small">;
253 defm UXTX : extend_operands<"UXTX", "Large">;
254 defm SXTB : extend_operands<"SXTB", "Small">;
255 defm SXTH : extend_operands<"SXTH", "Small">;
256 defm SXTW : extend_operands<"SXTW", "Small">;
257 defm SXTX : extend_operands<"SXTX", "Large">;
259 def LSL_extasmoperand : AsmOperandClass {
260 let Name = "RegExtendLSL";
261 let RenderMethod = "addRegExtendOperands";
262 let DiagnosticType = "AddSubRegExtendLarge";
265 def LSL_extoperand : Operand<i64> {
266 let ParserMatchClass = LSL_extasmoperand;
270 // The patterns for various sign-extensions are a little ugly and
271 // non-uniform because everything has already been promoted to the
272 // legal i64 and i32 types. We'll wrap the various variants up in a
273 // class for use later.
275 dag uxtb; dag uxth; dag uxtw; dag uxtx;
276 dag sxtb; dag sxth; dag sxtw; dag sxtx;
281 def extends_to_i64 : extend_types {
282 let uxtb = (and (anyext i32:$Rm), 255);
283 let uxth = (and (anyext i32:$Rm), 65535);
284 let uxtw = (zext i32:$Rm);
285 let uxtx = (i64 $Rm);
287 let sxtb = (sext_inreg (anyext i32:$Rm), i8);
288 let sxth = (sext_inreg (anyext i32:$Rm), i16);
289 let sxtw = (sext i32:$Rm);
290 let sxtx = (i64 $Rm);
297 def extends_to_i32 : extend_types {
298 let uxtb = (and i32:$Rm, 255);
299 let uxth = (and i32:$Rm, 65535);
300 let uxtw = (i32 i32:$Rm);
301 let uxtx = (i32 i32:$Rm);
303 let sxtb = (sext_inreg i32:$Rm, i8);
304 let sxth = (sext_inreg i32:$Rm, i16);
305 let sxtw = (i32 i32:$Rm);
306 let sxtx = (i32 i32:$Rm);
312 // Now, six of the extensions supported are easy and uniform: if the source size
313 // is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate
314 // those instructions in one block.
316 // The uxtx/sxtx could potentially be merged in, but three facts dissuaded me:
317 // + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would
319 // + Patterns are very different as well.
320 // + Passing different registers would be ugly (more fields in extend_types
321 // would probably be the best option).
322 multiclass addsub_exts<bit sf, bit op, bit S, string asmop,
323 SDPatternOperator opfrag,
324 dag outs, extend_types exts> {
325 def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000,
326 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
327 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
328 [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
330 def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001,
331 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
332 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
333 [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
335 def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010,
336 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
337 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
338 [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
341 def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100,
342 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
343 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
344 [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
346 def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101,
347 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
348 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
349 [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
351 def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110,
352 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
353 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
354 [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
358 // These two could be merge in with the above, but their patterns aren't really
359 // necessary and the naming-scheme would necessarily break:
360 multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag,
362 def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011,
364 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
365 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
366 [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))],
369 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
371 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),
372 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
373 [/* No Pattern: same as uxtx */],
377 multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {
378 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
380 (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
381 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
382 [/* No pattern: probably same as uxtw */],
385 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,
387 (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
388 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
389 [/* No Pattern: probably same as uxtw */],
393 class SetRD<RegisterClass RC, SDPatternOperator op>
394 : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>;
395 class SetNZCV<SDPatternOperator op>
396 : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>;
398 defm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
399 (outs GPR64xsp:$Rd), extends_to_i64>,
400 addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
401 (outs GPR64xsp:$Rd)>;
402 defm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>,
403 (outs GPR32wsp:$Rd), extends_to_i32>,
404 addsub_wxtx< 0b0, 0b0, "add\t$Rd, ",
405 (outs GPR32wsp:$Rd)>;
406 defm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
407 (outs GPR64xsp:$Rd), extends_to_i64>,
408 addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
409 (outs GPR64xsp:$Rd)>;
410 defm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>,
411 (outs GPR32wsp:$Rd), extends_to_i32>,
412 addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ",
413 (outs GPR32wsp:$Rd)>;
415 let Defs = [NZCV] in {
416 defm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
417 (outs GPR64:$Rd), extends_to_i64>,
418 addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
420 defm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>,
421 (outs GPR32:$Rd), extends_to_i32>,
422 addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ",
424 defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
425 (outs GPR64:$Rd), extends_to_i64>,
426 addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
428 defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>,
429 (outs GPR32:$Rd), extends_to_i32>,
430 addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ",
434 let Rd = 0b11111, isCompare = 1 in {
435 defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
436 (outs), extends_to_i64>,
437 addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
438 defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
439 (outs), extends_to_i32>,
440 addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>;
441 defm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
442 (outs), extends_to_i64>,
443 addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>;
444 defm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
445 (outs), extends_to_i32>,
446 addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>;
450 // Now patterns for the operation without a shift being needed. No patterns are
451 // created for uxtx/sxtx since they're non-uniform and it's expected that
452 // add/sub (shifted register) will handle those cases anyway.
453 multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop,
455 def : Pat<(nodeop exts.ty:$Rn, exts.uxtb),
456 (!cast<Instruction>(prefix # "w_uxtb") $Rn, $Rm, 0)>;
457 def : Pat<(nodeop exts.ty:$Rn, exts.uxth),
458 (!cast<Instruction>(prefix # "w_uxth") $Rn, $Rm, 0)>;
459 def : Pat<(nodeop exts.ty:$Rn, exts.uxtw),
460 (!cast<Instruction>(prefix # "w_uxtw") $Rn, $Rm, 0)>;
462 def : Pat<(nodeop exts.ty:$Rn, exts.sxtb),
463 (!cast<Instruction>(prefix # "w_sxtb") $Rn, $Rm, 0)>;
464 def : Pat<(nodeop exts.ty:$Rn, exts.sxth),
465 (!cast<Instruction>(prefix # "w_sxth") $Rn, $Rm, 0)>;
466 def : Pat<(nodeop exts.ty:$Rn, exts.sxtw),
467 (!cast<Instruction>(prefix # "w_sxtw") $Rn, $Rm, 0)>;
470 defm : addsubext_noshift_patterns<"ADDxx", add, extends_to_i64>;
471 defm : addsubext_noshift_patterns<"ADDww", add, extends_to_i32>;
472 defm : addsubext_noshift_patterns<"SUBxx", sub, extends_to_i64>;
473 defm : addsubext_noshift_patterns<"SUBww", sub, extends_to_i32>;
475 defm : addsubext_noshift_patterns<"CMNx", A64cmn, extends_to_i64>;
476 defm : addsubext_noshift_patterns<"CMNw", A64cmn, extends_to_i32>;
477 defm : addsubext_noshift_patterns<"CMPx", A64cmp, extends_to_i64>;
478 defm : addsubext_noshift_patterns<"CMPw", A64cmp, extends_to_i32>;
480 // An extend of "lsl #imm" is valid if and only if one of Rn and Rd is
481 // sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the
482 // operation. Also permitted in this case is complete omission of the argument,
483 // which implies "lsl #0".
484 multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd,
485 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
486 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
487 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
489 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"),
490 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
494 defm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
495 defm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
496 defm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>;
497 defm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>;
498 defm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
499 defm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
500 defm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>;
501 defm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>;
503 // Rd cannot be sp for flag-setting variants so only half of the aliases are
505 defm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>;
506 defm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>;
507 defm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>;
508 defm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>;
510 // CMP unfortunately has to be different because the instruction doesn't have a
512 multiclass cmp_lsl_aliases<string asmop, Instruction inst,
513 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
514 def : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
515 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
517 def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"),
518 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
521 defm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>;
522 defm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>;
523 defm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>;
524 defm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>;
526 //===----------------------------------------------------------------------===//
527 // Add-subtract (immediate) instructions
528 //===----------------------------------------------------------------------===//
529 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV
531 // These instructions accept a 12-bit unsigned immediate, optionally shifted
532 // left by 12 bits. Official assembly format specifies a 12 bit immediate with
533 // one of "", "LSL #0", "LSL #12" supplementary operands.
535 // There are surprisingly few ways to make this work with TableGen, so this
536 // implementation has separate instructions for the "LSL #0" and "LSL #12"
539 // If the MCInst retained a single combined immediate (which could be 0x123000,
540 // for example) then both components (imm & shift) would have to be delegated to
541 // a single assembly operand. This would entail a separate operand parser
542 // (because the LSL would have to live in the same AArch64Operand as the
543 // immediate to be accessible); assembly parsing is rather complex and
544 // error-prone C++ code.
546 // By splitting the immediate, we can delegate handling this optional operand to
547 // an InstAlias. Supporting functions to generate the correct MCInst are still
548 // required, but these are essentially trivial and parsing can remain generic.
550 // Rejected plans with rationale:
551 // ------------------------------
553 // In an ideal world you'de have two first class immediate operands (in
554 // InOperandList, specifying imm12 and shift). Unfortunately this is not
555 // selectable by any means I could discover.
557 // An Instruction with two MCOperands hidden behind a single entry in
558 // InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional,
559 // but required more C++ code to handle encoding/decoding. Parsing (the intended
560 // main beneficiary) ended up equally complex because of the optional nature of
563 // Attempting to circumvent the need for a custom OperandParser above by giving
564 // InstAliases without the "lsl #0" failed. add/sub could be accommodated but
565 // the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands
566 // should be parsed: there was no way to accommodate an "lsl #12".
568 let ParserMethod = "ParseImmWithLSLOperand",
569 RenderMethod = "addImmWithLSLOperands" in {
570 // Derived PredicateMethod fields are different for each
571 def addsubimm_lsl0_asmoperand : AsmOperandClass {
572 let Name = "AddSubImmLSL0";
573 // If an error is reported against this operand, instruction could also be a
575 let DiagnosticType = "AddSubSecondSource";
578 def addsubimm_lsl12_asmoperand : AsmOperandClass {
579 let Name = "AddSubImmLSL12";
580 let DiagnosticType = "AddSubSecondSource";
584 def shr_12_XFORM : SDNodeXForm<imm, [{
585 return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32);
588 def shr_12_neg_XFORM : SDNodeXForm<imm, [{
589 return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32);
592 def neg_XFORM : SDNodeXForm<imm, [{
593 return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32);
597 multiclass addsub_imm_operands<ValueType ty> {
598 let PrintMethod = "printAddSubImmLSL0Operand",
599 EncoderMethod = "getAddSubImmOpValue",
600 ParserMatchClass = addsubimm_lsl0_asmoperand in {
601 def _posimm_lsl0 : Operand<ty>,
602 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>;
603 def _negimm_lsl0 : Operand<ty>,
604 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }],
608 let PrintMethod = "printAddSubImmLSL12Operand",
609 EncoderMethod = "getAddSubImmOpValue",
610 ParserMatchClass = addsubimm_lsl12_asmoperand in {
611 def _posimm_lsl12 : Operand<ty>,
612 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }],
615 def _negimm_lsl12 : Operand<ty>,
616 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }],
621 // The add operands don't need any transformation
622 defm addsubimm_operand_i32 : addsub_imm_operands<i32>;
623 defm addsubimm_operand_i64 : addsub_imm_operands<i64>;
625 multiclass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift,
626 string asmop, string cmpasmop,
627 Operand imm_operand, Operand cmp_imm_operand,
628 RegisterClass GPR, RegisterClass GPRsp,
629 AArch64Reg ZR, ValueType Ty> {
630 // All registers for non-S variants allow SP
631 def _s : A64I_addsubimm<sf, op, 0b0, shift,
633 (ins GPRsp:$Rn, imm_operand:$Imm12),
634 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
635 [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],
639 // S variants can read SP but would write to ZR
640 def _S : A64I_addsubimm<sf, op, 0b1, shift,
642 (ins GPRsp:$Rn, imm_operand:$Imm12),
643 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
644 [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],
649 // Note that the pattern here for ADDS is subtle. Canonically CMP
650 // a, b becomes SUBS a, b. If b < 0 then this is equivalent to
651 // ADDS a, (-b). This is not true in general.
652 def _cmp : A64I_addsubimm<sf, op, 0b1, shift,
653 (outs), (ins GPRsp:$Rn, imm_operand:$Imm12),
654 !strconcat(cmpasmop, " $Rn, $Imm12"),
656 (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
665 multiclass addsubimm_shifts<string prefix, bit sf, bit op,
666 string asmop, string cmpasmop, string operand, string cmpoperand,
667 RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR,
669 defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00,
671 !cast<Operand>(operand # "_lsl0"),
672 !cast<Operand>(cmpoperand # "_lsl0"),
675 defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01,
677 !cast<Operand>(operand # "_lsl12"),
678 !cast<Operand>(cmpoperand # "_lsl12"),
682 defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn",
683 "addsubimm_operand_i32_posimm",
684 "addsubimm_operand_i32_negimm",
685 GPR32, GPR32wsp, WZR, i32>;
686 defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn",
687 "addsubimm_operand_i64_posimm",
688 "addsubimm_operand_i64_negimm",
689 GPR64, GPR64xsp, XZR, i64>;
690 defm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp",
691 "addsubimm_operand_i32_negimm",
692 "addsubimm_operand_i32_posimm",
693 GPR32, GPR32wsp, WZR, i32>;
694 defm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp",
695 "addsubimm_operand_i64_negimm",
696 "addsubimm_operand_i64_posimm",
697 GPR64, GPR64xsp, XZR, i64>;
699 multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> {
700 def _fromsp : InstAlias<"mov $Rd, $Rn",
701 (addop GPRsp:$Rd, SP:$Rn, 0),
704 def _tosp : InstAlias<"mov $Rd, $Rn",
705 (addop SP:$Rd, GPRsp:$Rn, 0),
709 // Recall Rxsp is a RegisterClass containing *just* xsp.
710 defm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>;
711 defm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>;
713 //===----------------------------------------------------------------------===//
714 // Add-subtract (shifted register) instructions
715 //===----------------------------------------------------------------------===//
716 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS
718 //===-------------------------------
719 // 1. The "shifed register" operands. Shared with logical insts.
720 //===-------------------------------
722 multiclass shift_operands<string prefix, string form> {
723 def _asmoperand_i32 : AsmOperandClass {
724 let Name = "Shift" # form # "i32";
725 let RenderMethod = "addShiftOperands";
726 let PredicateMethod = "isShift<A64SE::" # form # ", false>";
727 let DiagnosticType = "AddSubRegShift32";
730 // Note that the operand type is intentionally i64 because the DAGCombiner
731 // puts these into a canonical form.
732 def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
734 = !cast<AsmOperandClass>(prefix # "_asmoperand_i32");
735 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
736 let DecoderMethod = "Decode32BitShiftOperand";
739 def _asmoperand_i64 : AsmOperandClass {
740 let Name = "Shift" # form # "i64";
741 let RenderMethod = "addShiftOperands";
742 let PredicateMethod = "isShift<A64SE::" # form # ", true>";
743 let DiagnosticType = "AddSubRegShift64";
746 def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
748 = !cast<AsmOperandClass>(prefix # "_asmoperand_i64");
749 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
753 defm lsl_operand : shift_operands<"lsl_operand", "LSL">;
754 defm lsr_operand : shift_operands<"lsr_operand", "LSR">;
755 defm asr_operand : shift_operands<"asr_operand", "ASR">;
757 // Not used for add/sub, but defined here for completeness. The "logical
758 // (shifted register)" instructions *do* have an ROR variant.
759 defm ror_operand : shift_operands<"ror_operand", "ROR">;
761 //===-------------------------------
762 // 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions.
763 //===-------------------------------
765 // N.b. the commutable parameter is just !N. It will be first against the wall
766 // when the revolution comes.
767 multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable,
768 string asmop, SDPatternOperator opfrag, ValueType ty,
769 RegisterClass GPR, list<Register> defs> {
770 let isCommutable = commutable, Defs = defs in {
771 def _lsl : A64I_addsubshift<sf, op, s, 0b00,
773 (ins GPR:$Rn, GPR:$Rm,
774 !cast<Operand>("lsl_operand_" # ty):$Imm6),
775 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
776 [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
777 !cast<Operand>("lsl_operand_" # ty):$Imm6))
781 def _lsr : A64I_addsubshift<sf, op, s, 0b01,
783 (ins GPR:$Rn, GPR:$Rm,
784 !cast<Operand>("lsr_operand_" # ty):$Imm6),
785 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
786 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
787 !cast<Operand>("lsr_operand_" # ty):$Imm6))
791 def _asr : A64I_addsubshift<sf, op, s, 0b10,
793 (ins GPR:$Rn, GPR:$Rm,
794 !cast<Operand>("asr_operand_" # ty):$Imm6),
795 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
796 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
797 !cast<Operand>("asr_operand_" # ty):$Imm6))
803 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
804 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
807 def : Pat<(opfrag ty:$Rn, ty:$Rm),
808 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
811 multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable,
812 string asmop, SDPatternOperator opfrag,
813 list<Register> defs> {
814 defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s,
815 commutable, asmop, opfrag, i64, GPR64, defs>;
816 defm www : addsub_shifts<prefix # "www", 0b0, op, s,
817 commutable, asmop, opfrag, i32, GPR32, defs>;
821 defm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>;
822 defm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>;
824 defm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>;
825 defm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>;
827 //===-------------------------------
828 // 1. The NEG/NEGS aliases
829 //===-------------------------------
831 multiclass neg_alias<Instruction INST, RegisterClass GPR, Register ZR,
832 ValueType ty, Operand shift_operand, SDNode shiftop> {
833 def : InstAlias<"neg $Rd, $Rm, $Imm6",
834 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
836 def : Pat<(sub 0, (shiftop ty:$Rm, shift_operand:$Imm6)),
837 (INST ZR, $Rm, shift_operand:$Imm6)>;
840 defm : neg_alias<SUBwww_lsl, GPR32, WZR, i32, lsl_operand_i32, shl>;
841 defm : neg_alias<SUBwww_lsr, GPR32, WZR, i32, lsr_operand_i32, srl>;
842 defm : neg_alias<SUBwww_asr, GPR32, WZR, i32, asr_operand_i32, sra>;
843 def : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
844 def : Pat<(sub 0, i32:$Rm), (SUBwww_lsl WZR, $Rm, 0)>;
846 defm : neg_alias<SUBxxx_lsl, GPR64, XZR, i64, lsl_operand_i64, shl>;
847 defm : neg_alias<SUBxxx_lsr, GPR64, XZR, i64, lsr_operand_i64, srl>;
848 defm : neg_alias<SUBxxx_asr, GPR64, XZR, i64, asr_operand_i64, sra>;
849 def : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
850 def : Pat<(sub 0, i64:$Rm), (SUBxxx_lsl XZR, $Rm, 0)>;
852 // NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to
854 class negs_alias<Instruction INST, RegisterClass GPR,
855 Register ZR, Operand shift_operand, SDNode shiftop>
856 : InstAlias<"negs $Rd, $Rm, $Imm6",
857 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
859 def : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>;
860 def : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>;
861 def : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>;
862 def : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
864 def : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>;
865 def : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>;
866 def : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>;
867 def : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
869 //===-------------------------------
870 // 1. The CMP/CMN aliases
871 //===-------------------------------
873 multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable,
874 string asmop, SDPatternOperator opfrag, ValueType ty,
876 let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in {
877 def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00,
879 (ins GPR:$Rn, GPR:$Rm,
880 !cast<Operand>("lsl_operand_" # ty):$Imm6),
881 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
882 [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm,
883 !cast<Operand>("lsl_operand_" # ty):$Imm6))
887 def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01,
889 (ins GPR:$Rn, GPR:$Rm,
890 !cast<Operand>("lsr_operand_" # ty):$Imm6),
891 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
892 [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm,
893 !cast<Operand>("lsr_operand_" # ty):$Imm6))
897 def _asr : A64I_addsubshift<sf, op, 0b1, 0b10,
899 (ins GPR:$Rn, GPR:$Rm,
900 !cast<Operand>("asr_operand_" # ty):$Imm6),
901 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
902 [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm,
903 !cast<Operand>("asr_operand_" # ty):$Imm6))
909 : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
910 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
912 def : Pat<(opfrag ty:$Rn, ty:$Rm),
913 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
916 defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, i32, GPR32>;
917 defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, i64, GPR64>;
919 defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, i32, GPR32>;
920 defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, i64, GPR64>;
922 //===----------------------------------------------------------------------===//
923 // Add-subtract (with carry) instructions
924 //===----------------------------------------------------------------------===//
925 // Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS
927 multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> {
928 let Uses = [NZCV] in {
929 def www : A64I_addsubcarry<0b0, op, s, 0b000000,
930 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
931 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
934 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,
935 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
936 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
941 let isCommutable = 1 in {
942 defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">;
945 defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">;
947 let Defs = [NZCV] in {
948 let isCommutable = 1 in {
949 defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">;
952 defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">;
955 def : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>;
956 def : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
957 def : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>;
958 def : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
960 // Note that adde and sube can form a chain longer than two (e.g. for 256-bit
961 // addition). So the flag-setting instructions are appropriate.
962 def : Pat<(adde i32:$Rn, i32:$Rm), (ADCSwww $Rn, $Rm)>;
963 def : Pat<(adde i64:$Rn, i64:$Rm), (ADCSxxx $Rn, $Rm)>;
964 def : Pat<(sube i32:$Rn, i32:$Rm), (SBCSwww $Rn, $Rm)>;
965 def : Pat<(sube i64:$Rn, i64:$Rm), (SBCSxxx $Rn, $Rm)>;
967 //===----------------------------------------------------------------------===//
969 //===----------------------------------------------------------------------===//
970 // Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL,
973 // Because of the rather complicated nearly-overlapping aliases, the decoding of
974 // this range of instructions is handled manually. The architectural
975 // instructions are BFM, SBFM and UBFM but a disassembler should never produce
978 // In the end, the best option was to use BFM instructions for decoding under
979 // almost all circumstances, but to create aliasing *Instructions* for each of
980 // the canonical forms and specify a completely custom decoder which would
981 // substitute the correct MCInst as needed.
983 // This also simplifies instruction selection, parsing etc because the MCInsts
984 // have a shape that's closer to their use in code.
986 //===-------------------------------
987 // 1. The architectural BFM instructions
988 //===-------------------------------
990 def uimm5_asmoperand : AsmOperandClass {
992 let PredicateMethod = "isUImm<5>";
993 let RenderMethod = "addImmOperands";
994 let DiagnosticType = "UImm5";
997 def uimm6_asmoperand : AsmOperandClass {
999 let PredicateMethod = "isUImm<6>";
1000 let RenderMethod = "addImmOperands";
1001 let DiagnosticType = "UImm6";
1004 def bitfield32_imm : Operand<i64>,
1005 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> {
1006 let ParserMatchClass = uimm5_asmoperand;
1008 let DecoderMethod = "DecodeBitfield32ImmOperand";
1012 def bitfield64_imm : Operand<i64>,
1013 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
1014 let ParserMatchClass = uimm6_asmoperand;
1016 // Default decoder works in 64-bit case: the 6-bit field can take any value.
1019 multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> {
1020 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1021 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1022 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1024 let DecoderMethod = "DecodeBitfieldInstruction";
1027 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1028 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1029 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1031 let DecoderMethod = "DecodeBitfieldInstruction";
1035 defm SBFM : A64I_bitfieldSizes<0b00, "sbfm">;
1036 defm UBFM : A64I_bitfieldSizes<0b10, "ubfm">;
1038 // BFM instructions modify the destination register rather than defining it
1041 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1042 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1043 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1044 let DecoderMethod = "DecodeBitfieldInstruction";
1045 let Constraints = "$src = $Rd";
1049 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1050 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1051 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1052 let DecoderMethod = "DecodeBitfieldInstruction";
1053 let Constraints = "$src = $Rd";
1057 //===-------------------------------
1058 // 2. Extend aliases to 64-bit dest
1059 //===-------------------------------
1061 // Unfortunately the extensions that end up as 64-bits cannot be handled by an
1062 // instruction alias: their syntax is (for example) "SXTB x0, w0", which needs
1063 // to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is
1064 // not capable of such a map as far as I'm aware
1066 // Note that these instructions are strictly more specific than the
1067 // BFM ones (in ImmR) so they can handle their own decoding.
1068 class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, ValueType dty,
1069 string asmop, bits<6> imms, dag pattern>
1070 : A64I_bitfield<sf, opc, sf,
1071 (outs GPRDest:$Rd), (ins GPR32:$Rn),
1072 !strconcat(asmop, "\t$Rd, $Rn"),
1073 [(set dty:$Rd, pattern)], NoItinerary> {
1074 let ImmR = 0b000000;
1078 // Signed extensions
1079 def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtb", 7,
1080 (sext_inreg (anyext i32:$Rn), i8)>;
1081 def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxtb", 7,
1082 (sext_inreg i32:$Rn, i8)>;
1083 def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxth", 15,
1084 (sext_inreg (anyext i32:$Rn), i16)>;
1085 def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxth", 15,
1086 (sext_inreg i32:$Rn, i16)>;
1087 def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtw", 31, (sext i32:$Rn)>;
1089 // Unsigned extensions
1090 def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxtb", 7,
1091 (and i32:$Rn, 255)>;
1092 def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxth", 15,
1093 (and i32:$Rn, 65535)>;
1095 // The 64-bit unsigned variants are not strictly architectural but recommended
1097 let isAsmParserOnly = 1 in {
1098 def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxtb", 7,
1099 (and (anyext i32:$Rn), 255)>;
1100 def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxth", 15,
1101 (and (anyext i32:$Rn), 65535)>;
1104 // Extra patterns for when the source register is actually 64-bits
1105 // too. There's no architectural difference here, it's just LLVM
1106 // shinanigans. There's no need for equivalent zero-extension patterns
1107 // because they'll already be caught by logical (immediate) matching.
1108 def : Pat<(sext_inreg i64:$Rn, i8),
1109 (SXTBxw (EXTRACT_SUBREG $Rn, sub_32))>;
1110 def : Pat<(sext_inreg i64:$Rn, i16),
1111 (SXTHxw (EXTRACT_SUBREG $Rn, sub_32))>;
1112 def : Pat<(sext_inreg i64:$Rn, i32),
1113 (SXTWxw (EXTRACT_SUBREG $Rn, sub_32))>;
1116 //===-------------------------------
1117 // 3. Aliases for ASR and LSR (the simple shifts)
1118 //===-------------------------------
1120 // These also handle their own decoding because ImmS being set makes
1121 // them take precedence over BFM.
1122 multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> {
1123 def wwi : A64I_bitfield<0b0, opc, 0b0,
1124 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
1125 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1126 [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))],
1131 def xxi : A64I_bitfield<0b1, opc, 0b1,
1132 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
1133 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1134 [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))],
1141 defm ASR : A64I_shift<0b00, "asr", sra>;
1142 defm LSR : A64I_shift<0b10, "lsr", srl>;
1144 //===-------------------------------
1145 // 4. Aliases for LSL
1146 //===-------------------------------
1148 // Unfortunately LSL and subsequent aliases are much more complicated. We need
1149 // to be able to say certain output instruction fields depend in a complex
1150 // manner on combinations of input assembly fields).
1152 // MIOperandInfo *might* have been able to do it, but at the cost of
1153 // significantly more C++ code.
1155 // N.b. contrary to usual practice these operands store the shift rather than
1156 // the machine bits in an MCInst. The complexity overhead of consistency
1157 // outweighed the benefits in this case (custom asmparser, printer and selection
1158 // vs custom encoder).
1159 def bitfield32_lsl_imm : Operand<i64>,
1160 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1161 let ParserMatchClass = uimm5_asmoperand;
1162 let EncoderMethod = "getBitfield32LSLOpValue";
1165 def bitfield64_lsl_imm : Operand<i64>,
1166 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1167 let ParserMatchClass = uimm6_asmoperand;
1168 let EncoderMethod = "getBitfield64LSLOpValue";
1171 class A64I_bitfield_lsl<bit sf, RegisterClass GPR, ValueType ty,
1173 : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),
1174 "lsl\t$Rd, $Rn, $FullImm",
1175 [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))],
1178 let ImmR = FullImm{5-0};
1179 let ImmS = FullImm{11-6};
1181 // No disassembler allowed because it would overlap with BFM which does the
1183 let isAsmParserOnly = 1;
1186 def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, i32, bitfield32_lsl_imm>;
1187 def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, i64, bitfield64_lsl_imm>;
1189 //===-------------------------------
1190 // 5. Aliases for bitfield extract instructions
1191 //===-------------------------------
1193 def bfx32_width_asmoperand : AsmOperandClass {
1194 let Name = "BFX32Width";
1195 let PredicateMethod = "isBitfieldWidth<32>";
1196 let RenderMethod = "addBFXWidthOperands";
1197 let DiagnosticType = "Width32";
1200 def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> {
1201 let PrintMethod = "printBFXWidthOperand";
1202 let ParserMatchClass = bfx32_width_asmoperand;
1205 def bfx64_width_asmoperand : AsmOperandClass {
1206 let Name = "BFX64Width";
1207 let PredicateMethod = "isBitfieldWidth<64>";
1208 let RenderMethod = "addBFXWidthOperands";
1209 let DiagnosticType = "Width64";
1212 def bfx64_width : Operand<i64> {
1213 let PrintMethod = "printBFXWidthOperand";
1214 let ParserMatchClass = bfx64_width_asmoperand;
1218 multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> {
1219 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1220 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1221 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1222 [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))],
1224 // As above, no disassembler allowed.
1225 let isAsmParserOnly = 1;
1228 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1229 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1230 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1231 [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))],
1233 // As above, no disassembler allowed.
1234 let isAsmParserOnly = 1;
1238 defm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>;
1239 defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>;
1241 // Again, variants based on BFM modify Rd so need it as an input too.
1242 def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1243 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1244 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1245 // As above, no disassembler allowed.
1246 let isAsmParserOnly = 1;
1247 let Constraints = "$src = $Rd";
1250 def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1251 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1252 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1253 // As above, no disassembler allowed.
1254 let isAsmParserOnly = 1;
1255 let Constraints = "$src = $Rd";
1258 // SBFX instructions can do a 1-instruction sign-extension of boolean values.
1259 def : Pat<(sext_inreg i64:$Rn, i1), (SBFXxxii $Rn, 0, 0)>;
1260 def : Pat<(sext_inreg i32:$Rn, i1), (SBFXwwii $Rn, 0, 0)>;
1261 def : Pat<(i64 (sext_inreg (anyext i32:$Rn), i1)),
1262 (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>;
1264 // UBFX makes sense as an implementation of a 64-bit zero-extension too. Could
1265 // use either 64-bit or 32-bit variant, but 32-bit might be more efficient.
1266 def : Pat<(zext i32:$Rn), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31),
1269 //===-------------------------------
1270 // 6. Aliases for bitfield insert instructions
1271 //===-------------------------------
1273 def bfi32_lsb_asmoperand : AsmOperandClass {
1274 let Name = "BFI32LSB";
1275 let PredicateMethod = "isUImm<5>";
1276 let RenderMethod = "addBFILSBOperands<32>";
1277 let DiagnosticType = "UImm5";
1280 def bfi32_lsb : Operand<i64>,
1281 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1282 let PrintMethod = "printBFILSBOperand<32>";
1283 let ParserMatchClass = bfi32_lsb_asmoperand;
1286 def bfi64_lsb_asmoperand : AsmOperandClass {
1287 let Name = "BFI64LSB";
1288 let PredicateMethod = "isUImm<6>";
1289 let RenderMethod = "addBFILSBOperands<64>";
1290 let DiagnosticType = "UImm6";
1293 def bfi64_lsb : Operand<i64>,
1294 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1295 let PrintMethod = "printBFILSBOperand<64>";
1296 let ParserMatchClass = bfi64_lsb_asmoperand;
1299 // Width verification is performed during conversion so width operand can be
1300 // shared between 32/64-bit cases. Still needed for the print method though
1301 // because ImmR encodes "width - 1".
1302 def bfi32_width_asmoperand : AsmOperandClass {
1303 let Name = "BFI32Width";
1304 let PredicateMethod = "isBitfieldWidth<32>";
1305 let RenderMethod = "addBFIWidthOperands";
1306 let DiagnosticType = "Width32";
1309 def bfi32_width : Operand<i64>,
1310 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> {
1311 let PrintMethod = "printBFIWidthOperand";
1312 let ParserMatchClass = bfi32_width_asmoperand;
1315 def bfi64_width_asmoperand : AsmOperandClass {
1316 let Name = "BFI64Width";
1317 let PredicateMethod = "isBitfieldWidth<64>";
1318 let RenderMethod = "addBFIWidthOperands";
1319 let DiagnosticType = "Width64";
1322 def bfi64_width : Operand<i64>,
1323 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> {
1324 let PrintMethod = "printBFIWidthOperand";
1325 let ParserMatchClass = bfi64_width_asmoperand;
1328 multiclass A64I_bitfield_insert<bits<2> opc, string asmop> {
1329 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1330 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1331 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1333 // As above, no disassembler allowed.
1334 let isAsmParserOnly = 1;
1337 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1338 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1339 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1341 // As above, no disassembler allowed.
1342 let isAsmParserOnly = 1;
1346 defm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">;
1347 defm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">;
1350 def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1351 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1352 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1353 // As above, no disassembler allowed.
1354 let isAsmParserOnly = 1;
1355 let Constraints = "$src = $Rd";
1358 def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1359 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1360 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1361 // As above, no disassembler allowed.
1362 let isAsmParserOnly = 1;
1363 let Constraints = "$src = $Rd";
1366 //===----------------------------------------------------------------------===//
1367 // Compare and branch (immediate)
1368 //===----------------------------------------------------------------------===//
1369 // Contains: CBZ, CBNZ
1371 class label_asmoperand<int width, int scale> : AsmOperandClass {
1372 let Name = "Label" # width # "_" # scale;
1373 let PredicateMethod = "isLabel<" # width # "," # scale # ">";
1374 let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">";
1375 let DiagnosticType = "Label";
1378 def label_wid19_scal4_asmoperand : label_asmoperand<19, 4>;
1380 // All conditional immediate branches are the same really: 19 signed bits scaled
1381 // by the instruction-size (4).
1382 def bcc_target : Operand<OtherVT> {
1383 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
1384 let ParserMatchClass = label_wid19_scal4_asmoperand;
1385 let PrintMethod = "printLabelOperand<19, 4>";
1386 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>";
1387 let OperandType = "OPERAND_PCREL";
1390 multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> {
1391 let isBranch = 1, isTerminator = 1 in {
1392 def x : A64I_cmpbr<0b1, op,
1394 (ins GPR64:$Rt, bcc_target:$Label),
1395 !strconcat(asmop,"\t$Rt, $Label"),
1396 [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],
1399 def w : A64I_cmpbr<0b0, op,
1401 (ins GPR32:$Rt, bcc_target:$Label),
1402 !strconcat(asmop,"\t$Rt, $Label"),
1403 [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],
1408 defm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{
1409 return Imm == A64CC::EQ;
1411 defm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{
1412 return Imm == A64CC::NE;
1415 //===----------------------------------------------------------------------===//
1416 // Conditional branch (immediate) instructions
1417 //===----------------------------------------------------------------------===//
1420 def cond_code_asmoperand : AsmOperandClass {
1421 let Name = "CondCode";
1422 let DiagnosticType = "CondCode";
1425 def cond_code : Operand<i32>, ImmLeaf<i32, [{
1426 return Imm >= 0 && Imm <= 15;
1428 let PrintMethod = "printCondCodeOperand";
1429 let ParserMatchClass = cond_code_asmoperand;
1432 def Bcc : A64I_condbr<0b0, 0b0, (outs),
1433 (ins cond_code:$Cond, bcc_target:$Label),
1434 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
1438 let isTerminator = 1;
1441 //===----------------------------------------------------------------------===//
1442 // Conditional compare (immediate) instructions
1443 //===----------------------------------------------------------------------===//
1444 // Contains: CCMN, CCMP
1446 def uimm4_asmoperand : AsmOperandClass {
1448 let PredicateMethod = "isUImm<4>";
1449 let RenderMethod = "addImmOperands";
1450 let DiagnosticType = "UImm4";
1453 def uimm4 : Operand<i32> {
1454 let ParserMatchClass = uimm4_asmoperand;
1457 def uimm5 : Operand<i32> {
1458 let ParserMatchClass = uimm5_asmoperand;
1461 // The only difference between this operand and the one for instructions like
1462 // B.cc is that it's parsed manually. The other get parsed implicitly as part of
1463 // the mnemonic handling.
1464 def cond_code_op_asmoperand : AsmOperandClass {
1465 let Name = "CondCodeOp";
1466 let RenderMethod = "addCondCodeOperands";
1467 let PredicateMethod = "isCondCode";
1468 let ParserMethod = "ParseCondCodeOperand";
1469 let DiagnosticType = "CondCode";
1472 def cond_code_op : Operand<i32> {
1473 let PrintMethod = "printCondCodeOperand";
1474 let ParserMatchClass = cond_code_op_asmoperand;
1477 class A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1478 : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),
1479 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
1480 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
1485 def CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">;
1486 def CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">;
1487 def CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">;
1488 def CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">;
1490 //===----------------------------------------------------------------------===//
1491 // Conditional compare (register) instructions
1492 //===----------------------------------------------------------------------===//
1493 // Contains: CCMN, CCMP
1495 class A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1496 : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1,
1498 (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
1499 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
1504 def CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">;
1505 def CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">;
1506 def CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">;
1507 def CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">;
1509 //===----------------------------------------------------------------------===//
1510 // Conditional select instructions
1511 //===----------------------------------------------------------------------===//
1512 // Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG
1514 // Condition code which is encoded as the inversion (semantically rather than
1515 // bitwise) in the instruction.
1516 def inv_cond_code_op_asmoperand : AsmOperandClass {
1517 let Name = "InvCondCodeOp";
1518 let RenderMethod = "addInvCondCodeOperands";
1519 let PredicateMethod = "isCondCode";
1520 let ParserMethod = "ParseCondCodeOperand";
1521 let DiagnosticType = "CondCode";
1524 def inv_cond_code_op : Operand<i32> {
1525 let ParserMatchClass = inv_cond_code_op_asmoperand;
1528 // Having a separate operand for the selectable use-case is debatable, but gives
1529 // consistency with cond_code.
1530 def inv_cond_XFORM : SDNodeXForm<imm, [{
1531 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue());
1532 return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32);
1536 : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>;
1539 multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
1540 SDPatternOperator select> {
1541 let Uses = [NZCV] in {
1542 def wwwc : A64I_condsel<0b0, op, 0b0, op2,
1544 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
1545 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1546 [(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
1550 def xxxc : A64I_condsel<0b1, op, 0b0, op2,
1552 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
1553 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1554 [(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
1560 : PatFrag<(ops node:$lhs, node:$rhs),
1561 (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>;
1563 class complex_select<SDPatternOperator opnode>
1564 : PatFrag<(ops node:$lhs, node:$rhs),
1565 (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>;
1568 defm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>;
1569 defm CSINC : A64I_condselSizes<0b0, 0b01, "csinc",
1570 complex_select<PatFrag<(ops node:$val),
1571 (add node:$val, 1)>>>;
1572 defm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>;
1573 defm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>;
1575 // Now the instruction aliases, which fit nicely into LLVM's model:
1577 def : InstAlias<"cset $Rd, $Cond",
1578 (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1579 def : InstAlias<"cset $Rd, $Cond",
1580 (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1581 def : InstAlias<"csetm $Rd, $Cond",
1582 (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1583 def : InstAlias<"csetm $Rd, $Cond",
1584 (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1585 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1586 (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1587 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1588 (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1589 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1590 (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1591 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1592 (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1593 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1594 (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1595 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1596 (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1598 // Finally some helper patterns.
1600 // For CSET (a.k.a. zero-extension of icmp)
1601 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1602 (CSINCwwwc WZR, WZR, cond_code:$Cond)>;
1603 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1604 (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>;
1606 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1607 (CSINCxxxc XZR, XZR, cond_code:$Cond)>;
1608 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1609 (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>;
1611 // For CSETM (a.k.a. sign-extension of icmp)
1612 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1613 (CSINVwwwc WZR, WZR, cond_code:$Cond)>;
1614 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1615 (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>;
1617 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1618 (CSINVxxxc XZR, XZR, cond_code:$Cond)>;
1619 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1620 (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>;
1622 // CINC, CINV and CNEG get dealt with automatically, which leaves the issue of
1623 // commutativity. The instructions are to complex for isCommutable to be used,
1624 // so we have to create the patterns manually:
1626 // No commutable pattern for CSEL since the commuted version is isomorphic.
1629 def :Pat<(A64select_cc NZCV, (add i32:$Rm, 1), i32:$Rn, inv_cond_code:$Cond),
1630 (CSINCwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1631 def :Pat<(A64select_cc NZCV, (add i64:$Rm, 1), i64:$Rn, inv_cond_code:$Cond),
1632 (CSINCxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1635 def :Pat<(A64select_cc NZCV, (not i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1636 (CSINVwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1637 def :Pat<(A64select_cc NZCV, (not i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1638 (CSINVxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1641 def :Pat<(A64select_cc NZCV, (ineg i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1642 (CSNEGwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1643 def :Pat<(A64select_cc NZCV, (ineg i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1644 (CSNEGxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1646 //===----------------------------------------------------------------------===//
1647 // Data Processing (1 source) instructions
1648 //===----------------------------------------------------------------------===//
1649 // Contains: RBIT, REV16, REV, REV32, CLZ, CLS.
1651 // We define an unary operator which always fails. We will use this to
1652 // define unary operators that cannot be matched.
1654 class A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop,
1655 list<dag> patterns, RegisterClass GPRrc,
1656 InstrItinClass itin>:
1661 !strconcat(asmop, "\t$Rd, $Rn"),
1667 multiclass A64I_dp_1src <bits<6> opcode, string asmop> {
1668 let hasSideEffects = 0 in {
1669 def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>;
1670 def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>;
1674 defm RBIT : A64I_dp_1src<0b000000, "rbit">;
1675 defm CLS : A64I_dp_1src<0b000101, "cls">;
1676 defm CLZ : A64I_dp_1src<0b000100, "clz">;
1678 def : Pat<(ctlz i32:$Rn), (CLZww $Rn)>;
1679 def : Pat<(ctlz i64:$Rn), (CLZxx $Rn)>;
1680 def : Pat<(ctlz_zero_undef i32:$Rn), (CLZww $Rn)>;
1681 def : Pat<(ctlz_zero_undef i64:$Rn), (CLZxx $Rn)>;
1683 def : Pat<(cttz i32:$Rn), (CLZww (RBITww $Rn))>;
1684 def : Pat<(cttz i64:$Rn), (CLZxx (RBITxx $Rn))>;
1685 def : Pat<(cttz_zero_undef i32:$Rn), (CLZww (RBITww $Rn))>;
1686 def : Pat<(cttz_zero_undef i64:$Rn), (CLZxx (RBITxx $Rn))>;
1689 def REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev",
1690 [(set i32:$Rd, (bswap i32:$Rn))],
1691 GPR32, NoItinerary>;
1692 def REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev",
1693 [(set i64:$Rd, (bswap i64:$Rn))],
1694 GPR64, NoItinerary>;
1695 def REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32",
1696 [(set i64:$Rd, (bswap (rotr i64:$Rn, (i64 32))))],
1697 GPR64, NoItinerary>;
1698 def REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16",
1699 [(set i32:$Rd, (bswap (rotr i32:$Rn, (i64 16))))],
1702 def REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>;
1704 //===----------------------------------------------------------------------===//
1705 // Data Processing (2 sources) instructions
1706 //===----------------------------------------------------------------------===//
1707 // Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL,
1711 class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns,
1712 RegisterClass GPRsp,
1713 InstrItinClass itin>:
1717 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
1719 (ins GPRsp:$Rn, GPRsp:$Rm),
1723 multiclass dp_2src_crc<bit c, string asmop> {
1724 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
1725 !strconcat(asmop, "b"), [], GPR32, NoItinerary>;
1726 def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1},
1727 !strconcat(asmop, "h"), [], GPR32, NoItinerary>;
1728 def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0},
1729 !strconcat(asmop, "w"), [], GPR32, NoItinerary>;
1730 def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
1731 !strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
1732 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
1736 multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
1737 def www : dp_2src_impl<0b0,
1741 (op i32:$Rn, (i64 (zext i32:$Rm))))],
1744 def xxx : dp_2src_impl<0b1,
1747 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1753 multiclass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> {
1754 def www : dp_2src_impl<0b0,
1757 [(set i32:$Rd, (op i32:$Rn, i32:$Rm))],
1760 def xxx : dp_2src_impl<0b1,
1763 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1768 // Here we define the data processing 2 source instructions.
1769 defm CRC32 : dp_2src_crc<0b0, "crc32">;
1770 defm CRC32C : dp_2src_crc<0b1, "crc32c">;
1772 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1773 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1775 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1776 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1777 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1778 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1780 // Extra patterns for an incoming 64-bit value for a 32-bit
1781 // operation. Since the LLVM operations are undefined (as in C) if the
1782 // RHS is out of range, it's perfectly permissible to discard the high
1783 // bits of the GPR64.
1784 def : Pat<(shl i32:$Rn, i64:$Rm),
1785 (LSLVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1786 def : Pat<(srl i32:$Rn, i64:$Rm),
1787 (LSRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1788 def : Pat<(sra i32:$Rn, i64:$Rm),
1789 (ASRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1790 def : Pat<(rotr i32:$Rn, i64:$Rm),
1791 (RORVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1793 // Here we define the aliases for the data processing 2 source instructions.
1794 def LSL_mnemonic : MnemonicAlias<"lslv", "lsl">;
1795 def LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">;
1796 def ASR_menmonic : MnemonicAlias<"asrv", "asr">;
1797 def ROR_menmonic : MnemonicAlias<"rorv", "ror">;
1799 //===----------------------------------------------------------------------===//
1800 // Data Processing (3 sources) instructions
1801 //===----------------------------------------------------------------------===//
1802 // Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH
1803 // + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL
1805 class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg,
1806 ValueType AccTy, RegisterClass SrcReg,
1807 string asmop, dag pattern>
1808 : A64I_dp3<sf, opcode,
1809 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
1810 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
1811 [(set AccTy:$Rd, pattern)], NoItinerary> {
1812 RegisterClass AccGPR = AccReg;
1813 RegisterClass SrcGPR = SrcReg;
1816 def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, i32, GPR32, "madd",
1817 (add i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1818 def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, i64, GPR64, "madd",
1819 (add i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1821 def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, i32, GPR32, "msub",
1822 (sub i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1823 def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, i64, GPR64, "msub",
1824 (sub i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1826 def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, i64, GPR32, "smaddl",
1827 (add i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1828 def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, i64, GPR32, "smsubl",
1829 (sub i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1831 def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, i64, GPR32, "umaddl",
1832 (add i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1833 def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, i64, GPR32, "umsubl",
1834 (sub i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1836 let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in {
1837 def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd),
1838 (ins GPR64:$Rn, GPR64:$Rm),
1839 "umulh\t$Rd, $Rn, $Rm",
1840 [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))],
1843 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
1844 (ins GPR64:$Rn, GPR64:$Rm),
1845 "smulh\t$Rd, $Rn, $Rm",
1846 [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))],
1850 multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,
1851 Register ZR, dag pattern> {
1852 def : InstAlias<asmop # " $Rd, $Rn, $Rm",
1853 (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
1855 def : Pat<pattern, (INST $Rn, $Rm, ZR)>;
1858 defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul i32:$Rn, i32:$Rm)>;
1859 defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul i64:$Rn, i64:$Rm)>;
1861 defm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR,
1862 (sub 0, (mul i32:$Rn, i32:$Rm))>;
1863 defm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR,
1864 (sub 0, (mul i64:$Rn, i64:$Rm))>;
1866 defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR,
1867 (mul (i64 (sext i32:$Rn)), (sext i32:$Rm))>;
1868 defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR,
1869 (sub 0, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1871 defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR,
1872 (mul (i64 (zext i32:$Rn)), (zext i32:$Rm))>;
1873 defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR,
1874 (sub 0, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1877 //===----------------------------------------------------------------------===//
1878 // Exception generation
1879 //===----------------------------------------------------------------------===//
1880 // Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3
1882 def uimm16_asmoperand : AsmOperandClass {
1883 let Name = "UImm16";
1884 let PredicateMethod = "isUImm<16>";
1885 let RenderMethod = "addImmOperands";
1886 let DiagnosticType = "UImm16";
1889 def uimm16 : Operand<i32> {
1890 let ParserMatchClass = uimm16_asmoperand;
1893 class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop>
1894 : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),
1895 !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {
1897 let isTerminator = 1;
1900 def SVCi : A64I_exceptImpl<0b000, 0b01, "svc">;
1901 def HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">;
1902 def SMCi : A64I_exceptImpl<0b000, 0b11, "smc">;
1903 def BRKi : A64I_exceptImpl<0b001, 0b00, "brk">;
1904 def HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">;
1906 def DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">;
1907 def DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">;
1908 def DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">;
1910 // The immediate is optional for the DCPS instructions, defaulting to 0.
1911 def : InstAlias<"dcps1", (DCPS1i 0)>;
1912 def : InstAlias<"dcps2", (DCPS2i 0)>;
1913 def : InstAlias<"dcps3", (DCPS3i 0)>;
1915 //===----------------------------------------------------------------------===//
1916 // Extract (immediate)
1917 //===----------------------------------------------------------------------===//
1918 // Contains: EXTR + alias ROR
1920 def EXTRwwwi : A64I_extract<0b0, 0b000, 0b0,
1922 (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB),
1923 "extr\t$Rd, $Rn, $Rm, $LSB",
1925 (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))],
1927 def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
1929 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
1930 "extr\t$Rd, $Rn, $Rm, $LSB",
1932 (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))],
1935 def : InstAlias<"ror $Rd, $Rs, $LSB",
1936 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;
1937 def : InstAlias<"ror $Rd, $Rs, $LSB",
1938 (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>;
1940 def : Pat<(rotr i32:$Rn, bitfield32_imm:$LSB),
1941 (EXTRwwwi $Rn, $Rn, bitfield32_imm:$LSB)>;
1942 def : Pat<(rotr i64:$Rn, bitfield64_imm:$LSB),
1943 (EXTRxxxi $Rn, $Rn, bitfield64_imm:$LSB)>;
1945 //===----------------------------------------------------------------------===//
1946 // Floating-point compare instructions
1947 //===----------------------------------------------------------------------===//
1948 // Contains: FCMP, FCMPE
1950 def fpzero_asmoperand : AsmOperandClass {
1951 let Name = "FPZero";
1952 let ParserMethod = "ParseFPImmOperand";
1953 let DiagnosticType = "FPZero";
1956 def fpz32 : Operand<f32>,
1957 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
1958 let ParserMatchClass = fpzero_asmoperand;
1959 let PrintMethod = "printFPZeroOperand";
1960 let DecoderMethod = "DecodeFPZeroOperand";
1963 def fpz64 : Operand<f64>,
1964 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
1965 let ParserMatchClass = fpzero_asmoperand;
1966 let PrintMethod = "printFPZeroOperand";
1967 let DecoderMethod = "DecodeFPZeroOperand";
1970 multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {
1971 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
1972 (outs), ins, "fcmp\t$Rn, $Rm", [pattern],
1977 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
1978 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> {
1983 defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm),
1984 (set NZCV, (A64cmp f32:$Rn, f32:$Rm))>;
1985 defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm),
1986 (set NZCV, (A64cmp f64:$Rn, f64:$Rm))>;
1988 // What would be Rm should be written as 0; note that even though it's called
1989 // "$Rm" here to fit in with the InstrFormats, it's actually an immediate.
1990 defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm),
1991 (set NZCV, (A64cmp f32:$Rn, fpz32:$Rm))>;
1993 defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm),
1994 (set NZCV, (A64cmp f64:$Rn, fpz64:$Rm))>;
1997 //===----------------------------------------------------------------------===//
1998 // Floating-point conditional compare instructions
1999 //===----------------------------------------------------------------------===//
2000 // Contains: FCCMP, FCCMPE
2002 class A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop>
2003 : A64I_fpccmp<0b0, 0b0, type, op,
2005 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
2006 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
2011 def FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">;
2012 def FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">;
2013 def FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">;
2014 def FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">;
2016 //===----------------------------------------------------------------------===//
2017 // Floating-point conditional select instructions
2018 //===----------------------------------------------------------------------===//
2021 let Uses = [NZCV] in {
2022 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
2023 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
2024 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2026 (simple_select f32:$Rn, f32:$Rm))],
2030 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
2031 (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond),
2032 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2034 (simple_select f64:$Rn, f64:$Rm))],
2038 //===----------------------------------------------------------------------===//
2039 // Floating-point data-processing (1 source)
2040 //===----------------------------------------------------------------------===//
2041 // Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI].
2043 def FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val),
2044 [{ (void)N; return false; }]>;
2046 // First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d"
2047 // syntax. Default to no pattern because most are odd enough not to have one.
2048 multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr,
2049 SDPatternOperator opnode = FPNoUnop> {
2050 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
2051 !strconcat(asmstr, "\t$Rd, $Rn"),
2052 [(set f32:$Rd, (opnode f32:$Rn))],
2055 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
2056 !strconcat(asmstr, "\t$Rd, $Rn"),
2057 [(set f64:$Rd, (opnode f64:$Rn))],
2061 defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;
2062 defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;
2063 defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;
2064 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
2066 defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;
2067 defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;
2068 defm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>;
2069 defm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>;
2070 defm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">;
2071 defm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>;
2072 defm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>;
2074 // The FCVT instrucitons have different source and destination register-types,
2075 // but the fields are uniform everywhere a D-register (say) crops up. Package
2076 // this information in a Record.
2077 class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> {
2078 RegisterClass Class = rc;
2084 def FCVT16 : FCVTRegType<FPR16, 0b11, f16>;
2085 def FCVT32 : FCVTRegType<FPR32, 0b00, f32>;
2086 def FCVT64 : FCVTRegType<FPR64, 0b01, f64>;
2088 class A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode>
2089 : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0},
2090 {0,0,0,1, DestReg.t1, DestReg.t0},
2091 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
2093 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>;
2095 def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>;
2096 def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>;
2097 def FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>;
2098 def FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>;
2099 def FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>;
2100 def FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>;
2103 //===----------------------------------------------------------------------===//
2104 // Floating-point data-processing (2 sources) instructions
2105 //===----------------------------------------------------------------------===//
2106 // Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
2108 def FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs),
2109 [{ (void)N; return false; }]>;
2111 multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr,
2112 SDPatternOperator opnode> {
2113 def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode,
2115 (ins FPR32:$Rn, FPR32:$Rm),
2116 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2117 [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))],
2120 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
2122 (ins FPR64:$Rn, FPR64:$Rm),
2123 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2124 [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))],
2128 let isCommutable = 1 in {
2129 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
2130 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;
2132 // No patterns for these.
2133 defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>;
2134 defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>;
2135 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;
2136 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;
2138 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2139 PatFrag<(ops node:$lhs, node:$rhs),
2140 (fneg (fmul node:$lhs, node:$rhs))> >;
2143 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
2144 defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;
2146 //===----------------------------------------------------------------------===//
2147 // Floating-point data-processing (3 sources) instructions
2148 //===----------------------------------------------------------------------===//
2149 // Contains: FMADD, FMSUB, FNMADD, FNMSUB
2151 def fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2152 (fma (fneg node:$Rn), node:$Rm, node:$Ra)>;
2153 def fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2154 (fma node:$Rn, node:$Rm, (fneg node:$Ra))>;
2155 def fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2156 (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>;
2158 class A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT,
2159 bits<2> type, bit o1, bit o0, SDPatternOperator fmakind>
2160 : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd),
2161 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
2162 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
2163 [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))],
2166 def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
2167 def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;
2168 def FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>;
2169 def FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>;
2171 def FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>;
2172 def FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>;
2173 def FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>;
2174 def FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>;
2176 //===----------------------------------------------------------------------===//
2177 // Floating-point <-> fixed-point conversion instructions
2178 //===----------------------------------------------------------------------===//
2179 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2181 // #1-#32 allowed, encoded as "64 - <specified imm>
2182 def fixedpos_asmoperand_i32 : AsmOperandClass {
2183 let Name = "CVTFixedPos32";
2184 let RenderMethod = "addCVTFixedPosOperands";
2185 let PredicateMethod = "isCVTFixedPos<32>";
2186 let DiagnosticType = "CVTFixedPos32";
2189 // Also encoded as "64 - <specified imm>" but #1-#64 allowed.
2190 def fixedpos_asmoperand_i64 : AsmOperandClass {
2191 let Name = "CVTFixedPos64";
2192 let RenderMethod = "addCVTFixedPosOperands";
2193 let PredicateMethod = "isCVTFixedPos<64>";
2194 let DiagnosticType = "CVTFixedPos64";
2197 // We need the cartesian product of f32/f64 i32/i64 operands for
2199 // + Selection needs to use operands of correct floating type
2200 // + Assembly parsing and decoding depend on integer width
2201 class cvtfix_i32_op<ValueType FloatVT>
2203 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> {
2204 let ParserMatchClass = fixedpos_asmoperand_i32;
2205 let DecoderMethod = "DecodeCVT32FixedPosOperand";
2206 let PrintMethod = "printCVTFixedPosOperand";
2209 class cvtfix_i64_op<ValueType FloatVT>
2211 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> {
2212 let ParserMatchClass = fixedpos_asmoperand_i64;
2213 let PrintMethod = "printCVTFixedPosOperand";
2216 // Because of the proliferation of weird operands, it's not really
2217 // worth going for a multiclass here. Oh well.
2219 class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode,
2220 RegisterClass GPR, RegisterClass FPR,
2221 ValueType DstTy, ValueType SrcTy,
2222 Operand scale_op, string asmop, SDNode cvtop>
2223 : A64I_fpfixed<sf, 0b0, type, 0b11, opcode,
2224 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
2225 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2226 [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))],
2229 def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32,
2230 cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>;
2231 def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32, i64, f32,
2232 cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>;
2233 def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32, i32, f32,
2234 cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>;
2235 def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32, i64, f32,
2236 cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>;
2238 def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64, i32, f64,
2239 cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>;
2240 def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64, i64, f64,
2241 cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>;
2242 def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64, i32, f64,
2243 cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>;
2244 def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64, i64, f64,
2245 cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>;
2248 class A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode,
2249 RegisterClass FPR, RegisterClass GPR,
2250 ValueType DstTy, ValueType SrcTy,
2251 Operand scale_op, string asmop, SDNode cvtop>
2252 : A64I_fpfixed<sf, 0b0, type, 0b00, opcode,
2253 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
2254 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2255 [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))],
2258 def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32,
2259 cvtfix_i32_op<f32>, "scvtf", sint_to_fp>;
2260 def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64, f32, i64,
2261 cvtfix_i64_op<f32>, "scvtf", sint_to_fp>;
2262 def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32, f32, i32,
2263 cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>;
2264 def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64, f32, i64,
2265 cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>;
2266 def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32, f64, i32,
2267 cvtfix_i32_op<f64>, "scvtf", sint_to_fp>;
2268 def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64, f64, i64,
2269 cvtfix_i64_op<f64>, "scvtf", sint_to_fp>;
2270 def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32, f64, i32,
2271 cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>;
2272 def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64, f64, i64,
2273 cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>;
2275 //===----------------------------------------------------------------------===//
2276 // Floating-point <-> integer conversion instructions
2277 //===----------------------------------------------------------------------===//
2278 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2280 class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode,
2281 RegisterClass DestPR, RegisterClass SrcPR, string asmop>
2282 : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),
2283 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;
2285 multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {
2286 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
2287 GPR32, FPR32, asmop # "s">;
2288 def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0},
2289 GPR64, FPR32, asmop # "s">;
2290 def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1},
2291 GPR32, FPR32, asmop # "u">;
2292 def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1},
2293 GPR64, FPR32, asmop # "u">;
2295 def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0},
2296 GPR32, FPR64, asmop # "s">;
2297 def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0},
2298 GPR64, FPR64, asmop # "s">;
2299 def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1},
2300 GPR32, FPR64, asmop # "u">;
2301 def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1},
2302 GPR64, FPR64, asmop # "u">;
2305 defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">;
2306 defm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">;
2307 defm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">;
2308 defm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">;
2309 defm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">;
2311 def : Pat<(i32 (fp_to_sint f32:$Rn)), (FCVTZSws $Rn)>;
2312 def : Pat<(i64 (fp_to_sint f32:$Rn)), (FCVTZSxs $Rn)>;
2313 def : Pat<(i32 (fp_to_uint f32:$Rn)), (FCVTZUws $Rn)>;
2314 def : Pat<(i64 (fp_to_uint f32:$Rn)), (FCVTZUxs $Rn)>;
2315 def : Pat<(i32 (fp_to_sint f64:$Rn)), (FCVTZSwd $Rn)>;
2316 def : Pat<(i64 (fp_to_sint f64:$Rn)), (FCVTZSxd $Rn)>;
2317 def : Pat<(i32 (fp_to_uint f64:$Rn)), (FCVTZUwd $Rn)>;
2318 def : Pat<(i64 (fp_to_uint f64:$Rn)), (FCVTZUxd $Rn)>;
2320 multiclass A64I_inttofp<bit o0, string asmop> {
2321 def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>;
2322 def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>;
2323 def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>;
2324 def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>;
2327 defm S : A64I_inttofp<0b0, "scvtf">;
2328 defm U : A64I_inttofp<0b1, "ucvtf">;
2330 def : Pat<(f32 (sint_to_fp i32:$Rn)), (SCVTFsw $Rn)>;
2331 def : Pat<(f32 (sint_to_fp i64:$Rn)), (SCVTFsx $Rn)>;
2332 def : Pat<(f64 (sint_to_fp i32:$Rn)), (SCVTFdw $Rn)>;
2333 def : Pat<(f64 (sint_to_fp i64:$Rn)), (SCVTFdx $Rn)>;
2334 def : Pat<(f32 (uint_to_fp i32:$Rn)), (UCVTFsw $Rn)>;
2335 def : Pat<(f32 (uint_to_fp i64:$Rn)), (UCVTFsx $Rn)>;
2336 def : Pat<(f64 (uint_to_fp i32:$Rn)), (UCVTFdw $Rn)>;
2337 def : Pat<(f64 (uint_to_fp i64:$Rn)), (UCVTFdx $Rn)>;
2339 def FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">;
2340 def FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">;
2341 def FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">;
2342 def FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">;
2344 def : Pat<(i32 (bitconvert f32:$Rn)), (FMOVws $Rn)>;
2345 def : Pat<(f32 (bitconvert i32:$Rn)), (FMOVsw $Rn)>;
2346 def : Pat<(i64 (bitconvert f64:$Rn)), (FMOVxd $Rn)>;
2347 def : Pat<(f64 (bitconvert i64:$Rn)), (FMOVdx $Rn)>;
2349 def lane1_asmoperand : AsmOperandClass {
2351 let RenderMethod = "addImmOperands";
2352 let DiagnosticType = "Lane1";
2355 def lane1 : Operand<i32> {
2356 let ParserMatchClass = lane1_asmoperand;
2357 let PrintMethod = "printBareImmOperand";
2360 let DecoderMethod = "DecodeFMOVLaneInstruction" in {
2361 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
2362 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
2363 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;
2365 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,
2366 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),
2367 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>;
2370 def : InstAlias<"fmov $Rd, $Rn.2d[$Lane]",
2371 (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>;
2373 def : InstAlias<"fmov $Rd.2d[$Lane], $Rn",
2374 (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>;
2376 //===----------------------------------------------------------------------===//
2377 // Floating-point immediate instructions
2378 //===----------------------------------------------------------------------===//
2381 def fpimm_asmoperand : AsmOperandClass {
2382 let Name = "FMOVImm";
2383 let ParserMethod = "ParseFPImmOperand";
2384 let DiagnosticType = "FPImm";
2387 // The MCOperand for these instructions are the encoded 8-bit values.
2388 def SDXF_fpimm : SDNodeXForm<fpimm, [{
2390 A64Imms::isFPImm(N->getValueAPF(), Imm8);
2391 return CurDAG->getTargetConstant(Imm8, MVT::i32);
2394 class fmov_operand<ValueType FT>
2396 PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }],
2398 let PrintMethod = "printFPImmOperand";
2399 let ParserMatchClass = fpimm_asmoperand;
2402 def fmov32_operand : fmov_operand<f32>;
2403 def fmov64_operand : fmov_operand<f64>;
2405 class A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT,
2406 Operand fmov_operand>
2407 : A64I_fpimm<0b0, 0b0, type, 0b00000,
2409 (ins fmov_operand:$Imm8),
2411 [(set VT:$Rd, fmov_operand:$Imm8)],
2414 def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
2415 def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;
2417 //===----------------------------------------------------------------------===//
2418 // Load-register (literal) instructions
2419 //===----------------------------------------------------------------------===//
2420 // Contains: LDR, LDRSW, PRFM
2422 def ldrlit_label_asmoperand : AsmOperandClass {
2423 let Name = "LoadLitLabel";
2424 let RenderMethod = "addLabelOperands<19, 4>";
2425 let DiagnosticType = "Label";
2428 def ldrlit_label : Operand<i64> {
2429 let EncoderMethod = "getLoadLitLabelOpValue";
2431 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
2432 let PrintMethod = "printLabelOperand<19, 4>";
2433 let ParserMatchClass = ldrlit_label_asmoperand;
2434 let OperandType = "OPERAND_PCREL";
2437 // Various instructions take an immediate value (which can always be used),
2438 // where some numbers have a symbolic name to make things easier. These operands
2439 // and the associated functions abstract away the differences.
2440 multiclass namedimm<string prefix, string mapper> {
2441 def _asmoperand : AsmOperandClass {
2442 let Name = "NamedImm" # prefix;
2443 let PredicateMethod = "isUImm";
2444 let RenderMethod = "addImmOperands";
2445 let ParserMethod = "ParseNamedImmOperand<" # mapper # ">";
2446 let DiagnosticType = "NamedImm_" # prefix;
2449 def _op : Operand<i32> {
2450 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
2451 let PrintMethod = "printNamedImmOperand<" # mapper # ">";
2452 let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">";
2456 defm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">;
2458 class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg,
2459 list<dag> patterns = []>
2460 : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
2461 "ldr\t$Rt, $Imm19", patterns, NoItinerary>;
2463 let mayLoad = 1 in {
2464 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
2465 def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>;
2468 def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>;
2469 def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>;
2471 let mayLoad = 1 in {
2472 def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>;
2475 def LDRSWx_lit : A64I_LDRlit<0b10, 0b0,
2477 (ins ldrlit_label:$Imm19),
2478 "ldrsw\t$Rt, $Imm19",
2481 def PRFM_lit : A64I_LDRlit<0b11, 0b0,
2482 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
2483 "prfm\t$Rt, $Imm19",
2487 //===----------------------------------------------------------------------===//
2488 // Load-store exclusive instructions
2489 //===----------------------------------------------------------------------===//
2490 // Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB,
2491 // STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB,
2492 // STLRH, STLR, LDARB, LDARH, LDAR
2494 // Since these instructions have the undefined register bits set to 1 in
2495 // their canonical form, we need a post encoder method to set those bits
2496 // to 1 when encoding these instructions. We do this using the
2497 // fixLoadStoreExclusive function. This function has template parameters:
2499 // fixLoadStoreExclusive<int hasRs, int hasRt2>
2501 // hasRs indicates that the instruction uses the Rs field, so we won't set
2502 // it to 1 (and the same for Rt2). We don't need template parameters for
2503 // the other register fiels since Rt and Rn are always used.
2505 // This operand parses a GPR64xsp register, followed by an optional immediate
2507 def GPR64xsp0_asmoperand : AsmOperandClass {
2508 let Name = "GPR64xsp0";
2509 let PredicateMethod = "isWrappedReg";
2510 let RenderMethod = "addRegOperands";
2511 let ParserMethod = "ParseLSXAddressOperand";
2512 // Diagnostics are provided by ParserMethod
2515 def GPR64xsp0 : RegisterOperand<GPR64xsp> {
2516 let ParserMatchClass = GPR64xsp0_asmoperand;
2519 //===----------------------------------
2520 // Store-exclusive (releasing & normal)
2521 //===----------------------------------
2523 class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2524 dag ins, list<dag> pat,
2525 InstrItinClass itin> :
2526 A64I_LDSTex_stn <size,
2527 opcode{2}, 0, opcode{1}, opcode{0},
2529 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
2532 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
2535 multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
2536 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2537 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2540 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2541 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2544 def _word: A64I_SRexs_impl<0b10, opcode, asmstr,
2545 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2548 def _dword: A64I_SRexs_impl<0b11, opcode, asmstr,
2549 (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2553 defm STXR : A64I_SRex<"stxr", 0b000, "STXR">;
2554 defm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">;
2556 //===----------------------------------
2558 //===----------------------------------
2560 class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2561 dag ins, list<dag> pat,
2562 InstrItinClass itin> :
2563 A64I_LDSTex_tn <size,
2564 opcode{2}, 1, opcode{1}, opcode{0},
2566 !strconcat(asm, "\t$Rt, [$Rn]"),
2569 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2572 multiclass A64I_LRex<string asmstr, bits<3> opcode> {
2573 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2574 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2577 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2578 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2581 def _word: A64I_LRexs_impl<0b10, opcode, asmstr,
2582 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2585 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,
2586 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn),
2590 defm LDXR : A64I_LRex<"ldxr", 0b000>;
2591 defm LDAXR : A64I_LRex<"ldaxr", 0b001>;
2592 defm LDAR : A64I_LRex<"ldar", 0b101>;
2594 class acquiring_load<PatFrag base>
2595 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
2596 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2597 return Ordering == Acquire || Ordering == SequentiallyConsistent;
2600 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
2601 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
2602 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
2603 def atomic_load_acquire_64 : acquiring_load<atomic_load_64>;
2605 def : Pat<(atomic_load_acquire_8 i64:$Rn), (LDAR_byte $Rn)>;
2606 def : Pat<(atomic_load_acquire_16 i64:$Rn), (LDAR_hword $Rn)>;
2607 def : Pat<(atomic_load_acquire_32 i64:$Rn), (LDAR_word $Rn)>;
2608 def : Pat<(atomic_load_acquire_64 i64:$Rn), (LDAR_dword $Rn)>;
2610 //===----------------------------------
2611 // Store-release (no exclusivity)
2612 //===----------------------------------
2614 class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2615 dag ins, list<dag> pat,
2616 InstrItinClass itin> :
2617 A64I_LDSTex_tn <size,
2618 opcode{2}, 0, opcode{1}, opcode{0},
2620 !strconcat(asm, "\t$Rt, [$Rn]"),
2623 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2626 class releasing_store<PatFrag base>
2627 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
2628 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2629 return Ordering == Release || Ordering == SequentiallyConsistent;
2632 def atomic_store_release_8 : releasing_store<atomic_store_8>;
2633 def atomic_store_release_16 : releasing_store<atomic_store_16>;
2634 def atomic_store_release_32 : releasing_store<atomic_store_32>;
2635 def atomic_store_release_64 : releasing_store<atomic_store_64>;
2637 multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> {
2638 def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2639 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2640 [(atomic_store_release_8 i64:$Rn, i32:$Rt)],
2643 def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2644 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2645 [(atomic_store_release_16 i64:$Rn, i32:$Rt)],
2648 def _word: A64I_SLexs_impl<0b10, opcode, asmstr,
2649 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2650 [(atomic_store_release_32 i64:$Rn, i32:$Rt)],
2653 def _dword: A64I_SLexs_impl<0b11, opcode, asmstr,
2654 (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2655 [(atomic_store_release_64 i64:$Rn, i64:$Rt)],
2659 defm STLR : A64I_SLex<"stlr", 0b101, "STLR">;
2661 //===----------------------------------
2662 // Store-exclusive pair (releasing & normal)
2663 //===----------------------------------
2665 class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2666 dag ins, list<dag> pat,
2667 InstrItinClass itin> :
2668 A64I_LDSTex_stt2n <size,
2669 opcode{2}, 0, opcode{1}, opcode{0},
2671 !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"),
2677 multiclass A64I_SPex<string asmstr, bits<3> opcode> {
2678 def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs),
2679 (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2,
2683 def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs),
2684 (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2,
2689 defm STXP : A64I_SPex<"stxp", 0b010>;
2690 defm STLXP : A64I_SPex<"stlxp", 0b011>;
2692 //===----------------------------------
2693 // Load-exclusive pair (acquiring & normal)
2694 //===----------------------------------
2696 class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2697 dag ins, list<dag> pat,
2698 InstrItinClass itin> :
2699 A64I_LDSTex_tt2n <size,
2700 opcode{2}, 1, opcode{1}, opcode{0},
2702 !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"),
2705 let DecoderMethod = "DecodeLoadPairExclusiveInstruction";
2706 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
2709 multiclass A64I_LPex<string asmstr, bits<3> opcode> {
2710 def _word: A64I_LPexs_impl<0b10, opcode, asmstr,
2711 (outs GPR32:$Rt, GPR32:$Rt2),
2712 (ins GPR64xsp0:$Rn),
2715 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
2716 (outs GPR64:$Rt, GPR64:$Rt2),
2717 (ins GPR64xsp0:$Rn),
2721 defm LDXP : A64I_LPex<"ldxp", 0b010>;
2722 defm LDAXP : A64I_LPex<"ldaxp", 0b011>;
2724 //===----------------------------------------------------------------------===//
2725 // Load-store register (unscaled immediate) instructions
2726 //===----------------------------------------------------------------------===//
2727 // Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM
2731 //===----------------------------------------------------------------------===//
2732 // Load-store register (register offset) instructions
2733 //===----------------------------------------------------------------------===//
2734 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2738 //===----------------------------------------------------------------------===//
2739 // Load-store register (unsigned immediate) instructions
2740 //===----------------------------------------------------------------------===//
2741 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2745 //===----------------------------------------------------------------------===//
2746 // Load-store register (immediate post-indexed) instructions
2747 //===----------------------------------------------------------------------===//
2748 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2752 //===----------------------------------------------------------------------===//
2753 // Load-store register (immediate pre-indexed) instructions
2754 //===----------------------------------------------------------------------===//
2755 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2757 // Note that patterns are much later on in a completely separate section (they
2758 // need ADRPxi to be defined).
2760 //===-------------------------------
2761 // 1. Various operands needed
2762 //===-------------------------------
2764 //===-------------------------------
2765 // 1.1 Unsigned 12-bit immediate operands
2766 //===-------------------------------
2767 // The addressing mode for these instructions consists of an unsigned 12-bit
2768 // immediate which is scaled by the size of the memory access.
2770 // We represent this in the MC layer by two operands:
2771 // 1. A base register.
2772 // 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]"
2773 // would have '1' in this field.
2774 // This means that separate functions are needed for converting representations
2775 // which *are* aware of the intended access size.
2777 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
2778 // know the access size via some means. An isolated operand does not have this
2779 // information unless told from here, which means we need separate tablegen
2780 // Operands for each access size. This multiclass takes care of instantiating
2781 // the correct template functions in the rest of the backend.
2783 //===-------------------------------
2784 // 1.1 Unsigned 12-bit immediate operands
2785 //===-------------------------------
2787 multiclass offsets_uimm12<int MemSize, string prefix> {
2788 def uimm12_asmoperand : AsmOperandClass {
2789 let Name = "OffsetUImm12_" # MemSize;
2790 let PredicateMethod = "isOffsetUImm12<" # MemSize # ">";
2791 let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">";
2792 let DiagnosticType = "LoadStoreUImm12_" # MemSize;
2795 // Pattern is really no more than an ImmLeaf, but predicated on MemSize which
2796 // complicates things beyond TableGen's ken.
2797 def uimm12 : Operand<i64>,
2798 ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> {
2799 let ParserMatchClass
2800 = !cast<AsmOperandClass>(prefix # uimm12_asmoperand);
2802 let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">";
2803 let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">";
2807 defm byte_ : offsets_uimm12<1, "byte_">;
2808 defm hword_ : offsets_uimm12<2, "hword_">;
2809 defm word_ : offsets_uimm12<4, "word_">;
2810 defm dword_ : offsets_uimm12<8, "dword_">;
2811 defm qword_ : offsets_uimm12<16, "qword_">;
2813 //===-------------------------------
2814 // 1.1 Signed 9-bit immediate operands
2815 //===-------------------------------
2817 // The MCInst is expected to store the bit-wise encoding of the value,
2818 // which amounts to lopping off the extended sign bits.
2819 def SDXF_simm9 : SDNodeXForm<imm, [{
2820 return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32);
2823 def simm9_asmoperand : AsmOperandClass {
2825 let PredicateMethod = "isSImm<9>";
2826 let RenderMethod = "addSImmOperands<9>";
2827 let DiagnosticType = "LoadStoreSImm9";
2830 def simm9 : Operand<i64>,
2831 ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }],
2833 let PrintMethod = "printOffsetSImm9Operand";
2834 let ParserMatchClass = simm9_asmoperand;
2838 //===-------------------------------
2839 // 1.3 Register offset extensions
2840 //===-------------------------------
2842 // The assembly-syntax for these addressing-modes is:
2843 // [<Xn|SP>, <R><m> {, <extend> {<amount>}}]
2845 // The essential semantics are:
2846 // + <amount> is a shift: #<log(transfer size)> or #0
2847 // + <R> can be W or X.
2848 // + If <R> is W, <extend> can be UXTW or SXTW
2849 // + If <R> is X, <extend> can be LSL or SXTX
2851 // The trickiest of those constraints is that Rm can be either GPR32 or GPR64,
2852 // which will need separate instructions for LLVM type-consistency. We'll also
2853 // need separate operands, of course.
2854 multiclass regexts<int MemSize, int RmSize, RegisterClass GPR,
2855 string Rm, string prefix> {
2856 def regext_asmoperand : AsmOperandClass {
2857 let Name = "AddrRegExtend_" # MemSize # "_" # Rm;
2858 let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">";
2859 let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">";
2860 let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize;
2863 def regext : Operand<i64> {
2865 = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">";
2867 let DecoderMethod = "DecodeAddrRegExtendOperand";
2868 let ParserMatchClass
2869 = !cast<AsmOperandClass>(prefix # regext_asmoperand);
2873 multiclass regexts_wx<int MemSize, string prefix> {
2874 // Rm is an X-register if LSL or SXTX are specified as the shift.
2875 defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">;
2877 // Rm is a W-register if UXTW or SXTW are specified as the shift.
2878 defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">;
2881 defm byte_ : regexts_wx<1, "byte_">;
2882 defm hword_ : regexts_wx<2, "hword_">;
2883 defm word_ : regexts_wx<4, "word_">;
2884 defm dword_ : regexts_wx<8, "dword_">;
2885 defm qword_ : regexts_wx<16, "qword_">;
2888 //===------------------------------
2889 // 2. The instructions themselves.
2890 //===------------------------------
2892 // We have the following instructions to implement:
2893 // | | B | H | W | X |
2894 // |-----------------+-------+-------+-------+--------|
2895 // | unsigned str | STRB | STRH | STR | STR |
2896 // | unsigned ldr | LDRB | LDRH | LDR | LDR |
2897 // | signed ldr to W | LDRSB | LDRSH | - | - |
2898 // | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) |
2900 // This will instantiate the LDR/STR instructions you'd expect to use for an
2901 // unsigned datatype (first two rows above) or floating-point register, which is
2902 // reasonably uniform across all access sizes.
2905 //===------------------------------
2906 // 2.1 Regular instructions
2907 //===------------------------------
2909 // This class covers the basic unsigned or irrelevantly-signed loads and stores,
2910 // to general-purpose and floating-point registers.
2912 class AddrParams<string prefix> {
2913 Operand uimm12 = !cast<Operand>(prefix # "_uimm12");
2915 Operand regextWm = !cast<Operand>(prefix # "_Wm_regext");
2916 Operand regextXm = !cast<Operand>(prefix # "_Xm_regext");
2919 def byte_addrparams : AddrParams<"byte">;
2920 def hword_addrparams : AddrParams<"hword">;
2921 def word_addrparams : AddrParams<"word">;
2922 def dword_addrparams : AddrParams<"dword">;
2923 def qword_addrparams : AddrParams<"qword">;
2925 multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
2926 bit high_opc, string asmsuffix,
2927 RegisterClass GPR, AddrParams params> {
2928 // Unsigned immediate
2929 def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
2930 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
2931 "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
2935 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
2936 (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2938 def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},
2939 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
2940 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
2944 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
2945 (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2947 // Register offset (four of these: load/store and Wm/Xm).
2948 let mayLoad = 1 in {
2949 def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0,
2951 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
2952 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2955 def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1,
2957 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
2958 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2961 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",
2962 (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
2965 let mayStore = 1 in {
2966 def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0,
2967 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
2968 params.regextWm:$Ext),
2969 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2972 def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1,
2973 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm,
2974 params.regextXm:$Ext),
2975 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2978 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]",
2979 (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn,
2982 // Unaligned immediate
2983 def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
2984 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
2985 "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
2989 def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
2990 (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2992 def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},
2993 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
2994 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
2998 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
2999 (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3002 def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0},
3003 (outs GPR64xsp:$Rn_wb),
3004 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3005 "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3007 let Constraints = "$Rn = $Rn_wb";
3010 // Decoder only needed for unpredictability checking (FIXME).
3011 let DecoderMethod = "DecodeSingleIndexedInstruction";
3014 def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1},
3015 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3016 (ins GPR64xsp:$Rn, simm9:$SImm9),
3017 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3020 let Constraints = "$Rn = $Rn_wb";
3021 let DecoderMethod = "DecodeSingleIndexedInstruction";
3025 def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0},
3026 (outs GPR64xsp:$Rn_wb),
3027 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3028 "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3030 let Constraints = "$Rn = $Rn_wb";
3033 // Decoder only needed for unpredictability checking (FIXME).
3034 let DecoderMethod = "DecodeSingleIndexedInstruction";
3037 def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1},
3038 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3039 (ins GPR64xsp:$Rn, simm9:$SImm9),
3040 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3043 let Constraints = "$Rn = $Rn_wb";
3044 let DecoderMethod = "DecodeSingleIndexedInstruction";
3049 // STRB/LDRB: First define the instructions
3051 : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>;
3055 : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>;
3058 // STR/LDR to/from a W register
3060 : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>;
3062 // STR/LDR to/from an X register
3064 : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>;
3066 // STR/LDR to/from a B register
3068 : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>;
3070 // STR/LDR to/from an H register
3072 : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>;
3074 // STR/LDR to/from an S register
3076 : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>;
3077 // STR/LDR to/from a D register
3079 : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>;
3080 // STR/LDR to/from a Q register
3082 : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128,
3085 //===------------------------------
3087 //===------------------------------
3089 // Byte and half-word signed loads can both go into either an X or a W register,
3090 // so it's worth factoring out. Signed word loads don't fit because there is no
3092 multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
3095 def w : A64I_LSunsigimm<size, 0b0, 0b11,
3097 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3098 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3102 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3103 (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3105 def x : A64I_LSunsigimm<size, 0b0, 0b10,
3107 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3108 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3112 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3113 (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3116 let mayLoad = 1 in {
3117 def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0,
3119 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3120 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3123 def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1,
3125 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3126 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3129 def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0,
3131 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3132 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3135 def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1,
3137 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3138 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3141 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3142 (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,
3145 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3146 (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn,
3150 let mayLoad = 1 in {
3152 def w_U : A64I_LSunalimm<size, 0b0, 0b11,
3154 (ins GPR64xsp:$Rn, simm9:$SImm9),
3155 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3158 def x_U : A64I_LSunalimm<size, 0b0, 0b10,
3160 (ins GPR64xsp:$Rn, simm9:$SImm9),
3161 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3166 def w_PostInd : A64I_LSpostind<size, 0b0, 0b11,
3167 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3168 (ins GPR64xsp:$Rn, simm9:$SImm9),
3169 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3171 let Constraints = "$Rn = $Rn_wb";
3172 let DecoderMethod = "DecodeSingleIndexedInstruction";
3175 def x_PostInd : A64I_LSpostind<size, 0b0, 0b10,
3176 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3177 (ins GPR64xsp:$Rn, simm9:$SImm9),
3178 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3180 let Constraints = "$Rn = $Rn_wb";
3181 let DecoderMethod = "DecodeSingleIndexedInstruction";
3185 def w_PreInd : A64I_LSpreind<size, 0b0, 0b11,
3186 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3187 (ins GPR64xsp:$Rn, simm9:$SImm9),
3188 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3190 let Constraints = "$Rn = $Rn_wb";
3191 let DecoderMethod = "DecodeSingleIndexedInstruction";
3194 def x_PreInd : A64I_LSpreind<size, 0b0, 0b10,
3195 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3196 (ins GPR64xsp:$Rn, simm9:$SImm9),
3197 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3199 let Constraints = "$Rn = $Rn_wb";
3200 let DecoderMethod = "DecodeSingleIndexedInstruction";
3202 } // let mayLoad = 1
3206 defm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">;
3208 defm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">;
3210 // LDRSW: load a 32-bit register, sign-extending to 64-bits.
3212 : A64I_LSunsigimm<0b10, 0b0, 0b10,
3214 (ins GPR64xsp:$Rn, word_uimm12:$UImm12),
3215 "ldrsw\t$Rt, [$Rn, $UImm12]",
3219 def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3221 let mayLoad = 1 in {
3222 def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0,
3224 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
3225 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3228 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,
3230 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),
3231 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3234 def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",
3235 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;
3239 : A64I_LSunalimm<0b10, 0b0, 0b10,
3241 (ins GPR64xsp:$Rn, simm9:$SImm9),
3242 "ldursw\t$Rt, [$Rn, $SImm9]",
3246 def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3249 : A64I_LSpostind<0b10, 0b0, 0b10,
3250 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3251 (ins GPR64xsp:$Rn, simm9:$SImm9),
3252 "ldrsw\t$Rt, [$Rn], $SImm9",
3255 let Constraints = "$Rn = $Rn_wb";
3256 let DecoderMethod = "DecodeSingleIndexedInstruction";
3259 def LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10,
3260 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3261 (ins GPR64xsp:$Rn, simm9:$SImm9),
3262 "ldrsw\t$Rt, [$Rn, $SImm9]!",
3265 let Constraints = "$Rn = $Rn_wb";
3266 let DecoderMethod = "DecodeSingleIndexedInstruction";
3269 //===------------------------------
3270 // 2.4 Prefetch operations
3271 //===------------------------------
3273 def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
3274 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
3275 "prfm\t$Rt, [$Rn, $UImm12]",
3279 def : InstAlias<"prfm $Rt, [$Rn]",
3280 (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3282 let mayLoad = 1 in {
3283 def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs),
3284 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3285 GPR32:$Rm, dword_Wm_regext:$Ext),
3286 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3288 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),
3289 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3290 GPR64:$Rm, dword_Xm_regext:$Ext),
3291 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3295 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
3296 (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn,
3300 def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
3301 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3302 "prfum\t$Rt, [$Rn, $SImm9]",
3306 def : InstAlias<"prfum $Rt, [$Rn]",
3307 (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3309 //===----------------------------------------------------------------------===//
3310 // Load-store register (unprivileged) instructions
3311 //===----------------------------------------------------------------------===//
3312 // Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH
3314 // These instructions very much mirror the "unscaled immediate" loads, but since
3315 // there are no floating-point variants we need to split them out into their own
3316 // section to avoid instantiation of "ldtr d0, [sp]" etc.
3318 multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR,
3320 def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,
3321 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3322 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3327 def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]",
3328 (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3330 def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,
3331 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3332 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3337 def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]",
3338 (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3342 // STTRB/LDTRB: First define the instructions
3343 defm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">;
3346 defm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">;
3348 // STTR/LDTR to/from a W register
3349 defm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">;
3351 // STTR/LDTR to/from an X register
3352 defm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">;
3354 // Now a class for the signed instructions that can go to either 32 or 64
3356 multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> {
3357 let mayLoad = 1 in {
3358 def w : A64I_LSunpriv<size, 0b0, 0b11,
3360 (ins GPR64xsp:$Rn, simm9:$SImm9),
3361 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3364 def x : A64I_LSunpriv<size, 0b0, 0b10,
3366 (ins GPR64xsp:$Rn, simm9:$SImm9),
3367 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3371 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3372 (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3374 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3375 (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3380 defm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">;
3382 defm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">;
3384 // And finally LDTRSW which only goes to 64 bits.
3385 def LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10,
3387 (ins GPR64xsp:$Rn, simm9:$SImm9),
3388 "ldtrsw\t$Rt, [$Rn, $SImm9]",
3392 def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3394 //===----------------------------------------------------------------------===//
3395 // Load-store register pair (offset) instructions
3396 //===----------------------------------------------------------------------===//
3400 //===----------------------------------------------------------------------===//
3401 // Load-store register pair (post-indexed) instructions
3402 //===----------------------------------------------------------------------===//
3403 // Contains: STP, LDP, LDPSW
3407 //===----------------------------------------------------------------------===//
3408 // Load-store register pair (pre-indexed) instructions
3409 //===----------------------------------------------------------------------===//
3410 // Contains: STP, LDP, LDPSW
3414 //===----------------------------------------------------------------------===//
3415 // Load-store non-temporal register pair (offset) instructions
3416 //===----------------------------------------------------------------------===//
3417 // Contains: STNP, LDNP
3420 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
3421 // know the access size via some means. An isolated operand does not have this
3422 // information unless told from here, which means we need separate tablegen
3423 // Operands for each access size. This multiclass takes care of instantiating
3424 // the correct template functions in the rest of the backend.
3426 multiclass offsets_simm7<string MemSize, string prefix> {
3427 // The bare signed 7-bit immediate is used in post-indexed instructions, but
3428 // because of the scaling performed a generic "simm7" operand isn't
3429 // appropriate here either.
3430 def simm7_asmoperand : AsmOperandClass {
3431 let Name = "SImm7_Scaled" # MemSize;
3432 let PredicateMethod = "isSImm7Scaled<" # MemSize # ">";
3433 let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">";
3434 let DiagnosticType = "LoadStoreSImm7_" # MemSize;
3437 def simm7 : Operand<i64> {
3438 let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">";
3439 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand");
3443 defm word_ : offsets_simm7<"4", "word_">;
3444 defm dword_ : offsets_simm7<"8", "dword_">;
3445 defm qword_ : offsets_simm7<"16", "qword_">;
3447 multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
3448 Operand simm7, string prefix> {
3449 def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),
3450 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3451 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3453 let DecoderMethod = "DecodeLDSTPairInstruction";
3455 def : InstAlias<"stp $Rt, $Rt2, [$Rn]",
3456 (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt,
3457 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3459 def _LDR : A64I_LSPoffset<opc, v, 0b1,
3460 (outs SomeReg:$Rt, SomeReg:$Rt2),
3461 (ins GPR64xsp:$Rn, simm7:$SImm7),
3462 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3464 let DecoderMethod = "DecodeLDSTPairInstruction";
3466 def : InstAlias<"ldp $Rt, $Rt2, [$Rn]",
3467 (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt,
3468 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3470 def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0,
3471 (outs GPR64xsp:$Rn_wb),
3472 (ins SomeReg:$Rt, SomeReg:$Rt2,
3475 "stp\t$Rt, $Rt2, [$Rn], $SImm7",
3478 let Constraints = "$Rn = $Rn_wb";
3480 // Decoder only needed for unpredictability checking (FIXME).
3481 let DecoderMethod = "DecodeLDSTPairInstruction";
3484 def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1,
3485 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3486 (ins GPR64xsp:$Rn, simm7:$SImm7),
3487 "ldp\t$Rt, $Rt2, [$Rn], $SImm7",
3490 let Constraints = "$Rn = $Rn_wb";
3491 let DecoderMethod = "DecodeLDSTPairInstruction";
3494 def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
3495 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3496 "stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3499 let Constraints = "$Rn = $Rn_wb";
3500 let DecoderMethod = "DecodeLDSTPairInstruction";
3503 def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1,
3504 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3505 (ins GPR64xsp:$Rn, simm7:$SImm7),
3506 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3509 let Constraints = "$Rn = $Rn_wb";
3510 let DecoderMethod = "DecodeLDSTPairInstruction";
3513 def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
3514 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3515 "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3517 let DecoderMethod = "DecodeLDSTPairInstruction";
3519 def : InstAlias<"stnp $Rt, $Rt2, [$Rn]",
3520 (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt,
3521 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3523 def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,
3524 (outs SomeReg:$Rt, SomeReg:$Rt2),
3525 (ins GPR64xsp:$Rn, simm7:$SImm7),
3526 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3528 let DecoderMethod = "DecodeLDSTPairInstruction";
3530 def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]",
3531 (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt,
3532 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3537 defm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">;
3538 defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">;
3539 defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">;
3540 defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">;
3541 defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7,
3545 def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
3546 (outs GPR64:$Rt, GPR64:$Rt2),
3547 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3548 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3550 let DecoderMethod = "DecodeLDSTPairInstruction";
3552 def : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]",
3553 (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>;
3555 def LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1,
3556 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3557 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3558 "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
3561 let Constraints = "$Rn = $Rn_wb";
3562 let DecoderMethod = "DecodeLDSTPairInstruction";
3565 def LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1,
3566 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3567 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3568 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
3571 let Constraints = "$Rn = $Rn_wb";
3572 let DecoderMethod = "DecodeLDSTPairInstruction";
3575 //===----------------------------------------------------------------------===//
3576 // Logical (immediate) instructions
3577 //===----------------------------------------------------------------------===//
3578 // Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV
3580 multiclass logical_imm_operands<string prefix, string note,
3581 int size, ValueType VT> {
3582 def _asmoperand : AsmOperandClass {
3583 let Name = "LogicalImm" # note # size;
3584 let PredicateMethod = "isLogicalImm" # note # "<" # size # ">";
3585 let RenderMethod = "addLogicalImmOperands<" # size # ">";
3586 let DiagnosticType = "LogicalSecondSource";
3590 : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> {
3591 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3592 let PrintMethod = "printLogicalImmOperand<" # size # ">";
3593 let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">";
3597 defm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>;
3598 defm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>;
3600 // The mov versions only differ in assembly parsing, where they
3601 // exclude values representable with either MOVZ or MOVN.
3602 defm logical_imm32_mov
3603 : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>;
3604 defm logical_imm64_mov
3605 : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>;
3608 multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> {
3609 def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd),
3610 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3611 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3613 (opnode i32:$Rn, logical_imm32_operand:$Imm))],
3616 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
3617 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3618 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3620 (opnode i64:$Rn, logical_imm64_operand:$Imm))],
3624 defm AND : A64I_logimmSizes<0b00, "and", and>;
3625 defm ORR : A64I_logimmSizes<0b01, "orr", or>;
3626 defm EOR : A64I_logimmSizes<0b10, "eor", xor>;
3628 let Defs = [NZCV] in {
3629 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
3630 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3631 "ands\t$Rd, $Rn, $Imm",
3634 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),
3635 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3636 "ands\t$Rd, $Rn, $Imm",
3641 def : InstAlias<"tst $Rn, $Imm",
3642 (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>;
3643 def : InstAlias<"tst $Rn, $Imm",
3644 (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>;
3645 def : InstAlias<"mov $Rd, $Imm",
3646 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>;
3647 def : InstAlias<"mov $Rd, $Imm",
3648 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>;
3650 //===----------------------------------------------------------------------===//
3651 // Logical (shifted register) instructions
3652 //===----------------------------------------------------------------------===//
3653 // Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV
3655 // Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS"
3656 // behaves differently for unsigned comparisons, so we defensively only allow
3657 // signed or n/a as the operand. In practice "unsigned greater than 0" is "not
3658 // equal to 0" and LLVM gives us this.
3659 def signed_cond : PatLeaf<(cond), [{
3660 return !isUnsignedIntSetCC(N->get());
3664 // These instructions share their "shift" operands with add/sub (shifted
3665 // register instructions). They are defined there.
3667 // N.b. the commutable parameter is just !N. It will be first against the wall
3668 // when the revolution comes.
3669 multiclass logical_shifts<string prefix, bit sf, bits<2> opc,
3670 bit N, bit commutable,
3671 string asmop, SDPatternOperator opfrag, ValueType ty,
3672 RegisterClass GPR, list<Register> defs> {
3673 let isCommutable = commutable, Defs = defs in {
3674 def _lsl : A64I_logicalshift<sf, opc, 0b00, N,
3676 (ins GPR:$Rn, GPR:$Rm,
3677 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3678 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3679 [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
3680 !cast<Operand>("lsl_operand_" # ty):$Imm6))
3684 def _lsr : A64I_logicalshift<sf, opc, 0b01, N,
3686 (ins GPR:$Rn, GPR:$Rm,
3687 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3688 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3689 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
3690 !cast<Operand>("lsr_operand_" # ty):$Imm6))
3694 def _asr : A64I_logicalshift<sf, opc, 0b10, N,
3696 (ins GPR:$Rn, GPR:$Rm,
3697 !cast<Operand>("asr_operand_" # ty):$Imm6),
3698 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3699 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
3700 !cast<Operand>("asr_operand_" # ty):$Imm6))
3704 def _ror : A64I_logicalshift<sf, opc, 0b11, N,
3706 (ins GPR:$Rn, GPR:$Rm,
3707 !cast<Operand>("ror_operand_" # ty):$Imm6),
3708 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3709 [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm,
3710 !cast<Operand>("ror_operand_" # ty):$Imm6))
3716 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
3717 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
3720 def : Pat<(opfrag ty:$Rn, ty:$Rm),
3721 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
3724 multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable,
3725 string asmop, SDPatternOperator opfrag,
3726 list<Register> defs> {
3727 defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N,
3728 commutable, asmop, opfrag, i64, GPR64, defs>;
3729 defm www : logical_shifts<prefix # "www", 0b0, opc, N,
3730 commutable, asmop, opfrag, i32, GPR32, defs>;
3734 defm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>;
3735 defm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>;
3736 defm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>;
3737 defm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands",
3738 PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs),
3739 [{ (void)N; return false; }]>,
3742 defm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic",
3743 PatFrag<(ops node:$lhs, node:$rhs),
3744 (and node:$lhs, (not node:$rhs))>, []>;
3745 defm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn",
3746 PatFrag<(ops node:$lhs, node:$rhs),
3747 (or node:$lhs, (not node:$rhs))>, []>;
3748 defm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon",
3749 PatFrag<(ops node:$lhs, node:$rhs),
3750 (xor node:$lhs, (not node:$rhs))>, []>;
3751 defm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics",
3752 PatFrag<(ops node:$lhs, node:$rhs),
3753 (and node:$lhs, (not node:$rhs)),
3754 [{ (void)N; return false; }]>,
3757 multiclass tst_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
3758 let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in {
3759 def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0,
3761 (ins GPR:$Rn, GPR:$Rm,
3762 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3763 "tst\t$Rn, $Rm, $Imm6",
3764 [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm,
3765 !cast<Operand>("lsl_operand_" # ty):$Imm6)),
3770 def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0,
3772 (ins GPR:$Rn, GPR:$Rm,
3773 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3774 "tst\t$Rn, $Rm, $Imm6",
3775 [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm,
3776 !cast<Operand>("lsr_operand_" # ty):$Imm6)),
3780 def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0,
3782 (ins GPR:$Rn, GPR:$Rm,
3783 !cast<Operand>("asr_operand_" # ty):$Imm6),
3784 "tst\t$Rn, $Rm, $Imm6",
3785 [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm,
3786 !cast<Operand>("asr_operand_" # ty):$Imm6)),
3790 def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0,
3792 (ins GPR:$Rn, GPR:$Rm,
3793 !cast<Operand>("ror_operand_" # ty):$Imm6),
3794 "tst\t$Rn, $Rm, $Imm6",
3795 [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm,
3796 !cast<Operand>("ror_operand_" # ty):$Imm6)),
3801 def _noshift : InstAlias<"tst $Rn, $Rm",
3802 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3804 def : Pat<(A64setcc (and ty:$Rn, ty:$Rm), 0, signed_cond),
3805 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
3808 defm TSTxx : tst_shifts<"TSTxx", 0b1, i64, GPR64>;
3809 defm TSTww : tst_shifts<"TSTww", 0b0, i32, GPR32>;
3812 multiclass mvn_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
3813 let isCommutable = 0, Rn = 0b11111 in {
3814 def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1,
3817 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3818 "mvn\t$Rd, $Rm, $Imm6",
3819 [(set ty:$Rd, (not (shl ty:$Rm,
3820 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
3824 def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1,
3827 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3828 "mvn\t$Rd, $Rm, $Imm6",
3829 [(set ty:$Rd, (not (srl ty:$Rm,
3830 !cast<Operand>("lsr_operand_" # ty):$Imm6)))],
3833 def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1,
3836 !cast<Operand>("asr_operand_" # ty):$Imm6),
3837 "mvn\t$Rd, $Rm, $Imm6",
3838 [(set ty:$Rd, (not (sra ty:$Rm,
3839 !cast<Operand>("asr_operand_" # ty):$Imm6)))],
3842 def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1,
3845 !cast<Operand>("ror_operand_" # ty):$Imm6),
3846 "mvn\t$Rd, $Rm, $Imm6",
3847 [(set ty:$Rd, (not (rotr ty:$Rm,
3848 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
3852 def _noshift : InstAlias<"mvn $Rn, $Rm",
3853 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3855 def : Pat<(not ty:$Rm),
3856 (!cast<Instruction>(prefix # "_lsl") $Rm, 0)>;
3859 defm MVNxx : mvn_shifts<"MVNxx", 0b1, i64, GPR64>;
3860 defm MVNww : mvn_shifts<"MVNww", 0b0, i32, GPR32>;
3862 def MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
3863 def MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
3865 //===----------------------------------------------------------------------===//
3866 // Move wide (immediate) instructions
3867 //===----------------------------------------------------------------------===//
3868 // Contains: MOVN, MOVZ, MOVK + MOV aliases
3870 // A wide variety of different relocations are needed for variants of these
3871 // instructions, so it turns out that we need a different operand for all of
3873 multiclass movw_operands<string prefix, string instname, int width> {
3874 def _imm_asmoperand : AsmOperandClass {
3875 let Name = instname # width # "Shifted" # shift;
3876 let PredicateMethod = "is" # instname # width # "Imm";
3877 let RenderMethod = "addMoveWideImmOperands";
3878 let ParserMethod = "ParseImmWithLSLOperand";
3879 let DiagnosticType = "MOVWUImm16";
3882 def _imm : Operand<i64> {
3883 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand");
3884 let PrintMethod = "printMoveWideImmOperand";
3885 let EncoderMethod = "getMoveWideImmOpValue";
3886 let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">";
3888 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
3892 defm movn32 : movw_operands<"movn32", "MOVN", 32>;
3893 defm movn64 : movw_operands<"movn64", "MOVN", 64>;
3894 defm movz32 : movw_operands<"movz32", "MOVZ", 32>;
3895 defm movz64 : movw_operands<"movz64", "MOVZ", 64>;
3896 defm movk32 : movw_operands<"movk32", "MOVK", 32>;
3897 defm movk64 : movw_operands<"movk64", "MOVK", 64>;
3899 multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit,
3902 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
3903 !strconcat(asmop, "\t$Rd, $FullImm"),
3906 let UImm16 = FullImm{15-0};
3907 let Shift = FullImm{17-16};
3910 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
3911 !strconcat(asmop, "\t$Rd, $FullImm"),
3914 let UImm16 = FullImm{15-0};
3915 let Shift = FullImm{17-16};
3919 let isMoveImm = 1, isReMaterializable = 1,
3920 isAsCheapAsAMove = 1, hasSideEffects = 0 in {
3921 defm MOVN : A64I_movwSizes<0b00, "movn",
3922 (ins movn32_imm:$FullImm),
3923 (ins movn64_imm:$FullImm)>;
3925 // Some relocations are able to convert between a MOVZ and a MOVN. If these
3926 // are applied the instruction must be emitted with the corresponding bits as
3927 // 0, which means a MOVZ needs to override that bit from the default.
3928 let PostEncoderMethod = "fixMOVZ" in
3929 defm MOVZ : A64I_movwSizes<0b10, "movz",
3930 (ins movz32_imm:$FullImm),
3931 (ins movz64_imm:$FullImm)>;
3934 let Constraints = "$src = $Rd" in
3935 defm MOVK : A64I_movwSizes<0b11, "movk",
3936 (ins GPR32:$src, movk32_imm:$FullImm),
3937 (ins GPR64:$src, movk64_imm:$FullImm)>;
3940 // And now the "MOV" aliases. These also need their own operands because what
3941 // they accept is completely different to what the base instructions accept.
3942 multiclass movalias_operand<string prefix, string basename,
3943 string immpredicate, int width> {
3944 def _asmoperand : AsmOperandClass {
3945 let Name = basename # width # "MovAlias";
3947 = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">";
3949 = "addMoveWideMovAliasOperands<" # width # ", "
3950 # "A64Imms::" # immpredicate # ">";
3953 def _movimm : Operand<i64> {
3954 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3956 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
3960 defm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>;
3961 defm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>;
3962 defm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>;
3963 defm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>;
3965 // FIXME: these are officially canonical aliases, but TableGen is too limited to
3966 // print them at the moment. I believe in this case an "AliasPredicate" method
3967 // will need to be implemented. to allow it, as well as the more generally
3968 // useful handling of non-register, non-constant operands.
3969 class movalias<Instruction INST, RegisterClass GPR, Operand operand>
3970 : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>;
3972 def : movalias<MOVZwii, GPR32, movz32_movimm>;
3973 def : movalias<MOVZxii, GPR64, movz64_movimm>;
3974 def : movalias<MOVNwii, GPR32, movn32_movimm>;
3975 def : movalias<MOVNxii, GPR64, movn64_movimm>;
3977 def movw_addressref_g0 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<0>">;
3978 def movw_addressref_g1 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<1>">;
3979 def movw_addressref_g2 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<2>">;
3980 def movw_addressref_g3 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<3>">;
3982 def : Pat<(A64WrapperLarge movw_addressref_g3:$G3, movw_addressref_g2:$G2,
3983 movw_addressref_g1:$G1, movw_addressref_g0:$G0),
3984 (MOVKxii (MOVKxii (MOVKxii (MOVZxii movw_addressref_g3:$G3),
3985 movw_addressref_g2:$G2),
3986 movw_addressref_g1:$G1),
3987 movw_addressref_g0:$G0)>;
3989 //===----------------------------------------------------------------------===//
3990 // PC-relative addressing instructions
3991 //===----------------------------------------------------------------------===//
3992 // Contains: ADR, ADRP
3994 def adr_label : Operand<i64> {
3995 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>";
3997 // This label is a 21-bit offset from PC, unscaled
3998 let PrintMethod = "printLabelOperand<21, 1>";
3999 let ParserMatchClass = label_asmoperand<21, 1>;
4000 let OperandType = "OPERAND_PCREL";
4003 def adrp_label_asmoperand : AsmOperandClass {
4004 let Name = "AdrpLabel";
4005 let RenderMethod = "addLabelOperands<21, 4096>";
4006 let DiagnosticType = "Label";
4009 def adrp_label : Operand<i64> {
4010 let EncoderMethod = "getAdrpLabelOpValue";
4012 // This label is a 21-bit offset from PC, scaled by the page-size: 4096.
4013 let PrintMethod = "printLabelOperand<21, 4096>";
4014 let ParserMatchClass = adrp_label_asmoperand;
4015 let OperandType = "OPERAND_PCREL";
4018 let hasSideEffects = 0 in {
4019 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
4020 "adr\t$Rd, $Label", [], NoItinerary>;
4022 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),
4023 "adrp\t$Rd, $Label", [], NoItinerary>;
4026 //===----------------------------------------------------------------------===//
4027 // System instructions
4028 //===----------------------------------------------------------------------===//
4029 // Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS
4030 // + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL
4032 // Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values.
4033 def uimm3_asmoperand : AsmOperandClass {
4035 let PredicateMethod = "isUImm<3>";
4036 let RenderMethod = "addImmOperands";
4037 let DiagnosticType = "UImm3";
4040 def uimm3 : Operand<i32> {
4041 let ParserMatchClass = uimm3_asmoperand;
4044 // The HINT alias can accept a simple unsigned 7-bit immediate.
4045 def uimm7_asmoperand : AsmOperandClass {
4047 let PredicateMethod = "isUImm<7>";
4048 let RenderMethod = "addImmOperands";
4049 let DiagnosticType = "UImm7";
4052 def uimm7 : Operand<i32> {
4053 let ParserMatchClass = uimm7_asmoperand;
4056 // Multiclass namedimm is defined with the prefetch operands. Most of these fit
4057 // into the NamedImmMapper scheme well: they either accept a named operand or
4058 // any immediate under a particular value (which may be 0, implying no immediate
4060 defm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">;
4061 defm isb : namedimm<"isb", "A64ISB::ISBMapper">;
4062 defm ic : namedimm<"ic", "A64IC::ICMapper">;
4063 defm dc : namedimm<"dc", "A64DC::DCMapper">;
4064 defm at : namedimm<"at", "A64AT::ATMapper">;
4065 defm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">;
4067 // However, MRS and MSR are more complicated for a few reasons:
4068 // * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an
4069 // implementation-defined effect
4070 // * Most registers are shared, but some are read-only or write-only.
4071 // * There is a variant of MSR which accepts the same register name (SPSel),
4072 // but which would have a different encoding.
4074 // In principle these could be resolved in with more complicated subclasses of
4075 // NamedImmMapper, however that imposes an overhead on other "named
4076 // immediates". Both in concrete terms with virtual tables and in unnecessary
4079 // The solution adopted here is to take the MRS/MSR Mappers out of the usual
4080 // hierarchy (they're not derived from NamedImmMapper) and to add logic for
4081 // their special situation.
4082 def mrs_asmoperand : AsmOperandClass {
4084 let ParserMethod = "ParseSysRegOperand";
4085 let DiagnosticType = "MRS";
4088 def mrs_op : Operand<i32> {
4089 let ParserMatchClass = mrs_asmoperand;
4090 let PrintMethod = "printMRSOperand";
4091 let DecoderMethod = "DecodeMRSOperand";
4094 def msr_asmoperand : AsmOperandClass {
4095 let Name = "MSRWithReg";
4097 // Note that SPSel is valid for both this and the pstate operands, but with
4098 // different immediate encodings. This is why these operands provide a string
4099 // AArch64Operand rather than an immediate. The overlap is small enough that
4100 // it could be resolved with hackery now, but who can say in future?
4101 let ParserMethod = "ParseSysRegOperand";
4102 let DiagnosticType = "MSR";
4105 def msr_op : Operand<i32> {
4106 let ParserMatchClass = msr_asmoperand;
4107 let PrintMethod = "printMSROperand";
4108 let DecoderMethod = "DecodeMSROperand";
4111 def pstate_asmoperand : AsmOperandClass {
4112 let Name = "MSRPState";
4113 // See comment above about parser.
4114 let ParserMethod = "ParseSysRegOperand";
4115 let DiagnosticType = "MSR";
4118 def pstate_op : Operand<i32> {
4119 let ParserMatchClass = pstate_asmoperand;
4120 let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>";
4121 let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>";
4124 // When <CRn> is specified, an assembler should accept something like "C4", not
4125 // the usual "#4" immediate.
4126 def CRx_asmoperand : AsmOperandClass {
4128 let PredicateMethod = "isUImm<4>";
4129 let RenderMethod = "addImmOperands";
4130 let ParserMethod = "ParseCRxOperand";
4131 // Diagnostics are handled in all cases by ParseCRxOperand.
4134 def CRx : Operand<i32> {
4135 let ParserMatchClass = CRx_asmoperand;
4136 let PrintMethod = "printCRxOperand";
4140 // Finally, we can start defining the instructions.
4142 // HINT is straightforward, with a few aliases.
4143 def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7",
4146 let CRm = UImm7{6-3};
4147 let Op2 = UImm7{2-0};
4155 def : InstAlias<"nop", (HINTi 0)>;
4156 def : InstAlias<"yield", (HINTi 1)>;
4157 def : InstAlias<"wfe", (HINTi 2)>;
4158 def : InstAlias<"wfi", (HINTi 3)>;
4159 def : InstAlias<"sev", (HINTi 4)>;
4160 def : InstAlias<"sevl", (HINTi 5)>;
4162 // Quite a few instructions then follow a similar pattern of fixing common
4163 // fields in the bitpattern, we'll define a helper-class for them.
4164 class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2,
4165 Operand operand, string asmop>
4166 : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"),
4176 def CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">;
4177 def DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">;
4178 def DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">;
4179 def ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">;
4181 def : InstAlias<"clrex", (CLREXi 0b1111)>;
4182 def : InstAlias<"isb", (ISBi 0b1111)>;
4184 // (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP
4185 // configurations at least.
4186 def : Pat<(atomic_fence imm, imm), (DMBi 0xb)>;
4188 // Any SYS bitpattern can be represented with a complex and opaque "SYS"
4190 def SYSiccix : A64I_system<0b0, (outs),
4191 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm,
4192 uimm3:$Op2, GPR64:$Rt),
4193 "sys\t$Op1, $CRn, $CRm, $Op2, $Rt",
4198 // You can skip the Xt argument whether it makes sense or not for the generic
4200 def : InstAlias<"sys $Op1, $CRn, $CRm, $Op2",
4201 (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>;
4204 // But many have aliases, which obviously don't fit into
4205 class SYSalias<dag ins, string asmstring>
4206 : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> {
4207 let isAsmParserOnly = 1;
4211 let Op1 = SysOp{13-11};
4212 let CRn = SysOp{10-7};
4213 let CRm = SysOp{6-3};
4214 let Op2 = SysOp{2-0};
4217 def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">;
4219 def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> {
4223 def DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">;
4224 def ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">;
4226 def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">;
4228 def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> {
4233 def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt),
4234 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2),
4235 "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2",
4240 // The instructions themselves are rather simple for MSR and MRS.
4241 def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt),
4242 "msr\t$SysReg, $Rt", [], NoItinerary> {
4244 let Op0 = SysReg{15-14};
4245 let Op1 = SysReg{13-11};
4246 let CRn = SysReg{10-7};
4247 let CRm = SysReg{6-3};
4248 let Op2 = SysReg{2-0};
4251 def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg),
4252 "mrs\t$Rt, $SysReg", [], NoItinerary> {
4254 let Op0 = SysReg{15-14};
4255 let Op1 = SysReg{13-11};
4256 let CRn = SysReg{10-7};
4257 let CRm = SysReg{6-3};
4258 let Op2 = SysReg{2-0};
4261 def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm),
4262 "msr\t$PState, $CRm", [], NoItinerary> {
4266 let Op1 = PState{5-3};
4268 let Op2 = PState{2-0};
4272 //===----------------------------------------------------------------------===//
4273 // Test & branch (immediate) instructions
4274 //===----------------------------------------------------------------------===//
4275 // Contains: TBZ, TBNZ
4277 // The bit to test is a simple unsigned 6-bit immediate in the X-register
4279 def uimm6 : Operand<i64> {
4280 let ParserMatchClass = uimm6_asmoperand;
4283 def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>;
4285 def tbimm_target : Operand<OtherVT> {
4286 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>";
4288 // This label is a 14-bit offset from PC, scaled by the instruction-width: 4.
4289 let PrintMethod = "printLabelOperand<14, 4>";
4290 let ParserMatchClass = label_wid14_scal4_asmoperand;
4292 let OperandType = "OPERAND_PCREL";
4295 def A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>;
4296 def A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>;
4298 // These instructions correspond to patterns involving "and" with a power of
4299 // two, which we need to be able to select.
4300 def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">;
4301 def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">;
4303 let isBranch = 1, isTerminator = 1 in {
4304 def TBZxii : A64I_TBimm<0b0, (outs),
4305 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4306 "tbz\t$Rt, $Imm, $Label",
4307 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4311 def TBNZxii : A64I_TBimm<0b1, (outs),
4312 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4313 "tbnz\t$Rt, $Imm, $Label",
4314 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4319 // Note, these instructions overlap with the above 64-bit patterns. This is
4320 // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both
4321 // do the same thing and are both permitted assembly. They also both have
4322 // sensible DAG patterns.
4323 def TBZwii : A64I_TBimm<0b0, (outs),
4324 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4325 "tbz\t$Rt, $Imm, $Label",
4326 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4332 def TBNZwii : A64I_TBimm<0b1, (outs),
4333 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4334 "tbnz\t$Rt, $Imm, $Label",
4335 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4342 //===----------------------------------------------------------------------===//
4343 // Unconditional branch (immediate) instructions
4344 //===----------------------------------------------------------------------===//
4347 def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>;
4349 def bimm_target : Operand<OtherVT> {
4350 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>";
4352 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4353 let PrintMethod = "printLabelOperand<26, 4>";
4354 let ParserMatchClass = label_wid26_scal4_asmoperand;
4356 let OperandType = "OPERAND_PCREL";
4359 def blimm_target : Operand<i64> {
4360 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>";
4362 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4363 let PrintMethod = "printLabelOperand<26, 4>";
4364 let ParserMatchClass = label_wid26_scal4_asmoperand;
4366 let OperandType = "OPERAND_PCREL";
4369 class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type>
4370 : A64I_Bimm<op, (outs), (ins lbl_type:$Label),
4371 !strconcat(asmop, "\t$Label"), patterns,
4374 let isBranch = 1 in {
4375 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
4376 let isTerminator = 1;
4380 def BLimm : A64I_BimmImpl<0b1, "bl",
4381 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4387 def : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>;
4389 //===----------------------------------------------------------------------===//
4390 // Unconditional branch (register) instructions
4391 //===----------------------------------------------------------------------===//
4392 // Contains: BR, BLR, RET, ERET, DRP.
4394 // Most of the notional opcode fields in the A64I_Breg format are fixed in A64
4396 class A64I_BregImpl<bits<4> opc,
4397 dag outs, dag ins, string asmstr, list<dag> patterns,
4398 InstrItinClass itin = NoItinerary>
4399 : A64I_Breg<opc, 0b11111, 0b000000, 0b00000,
4400 outs, ins, asmstr, patterns, itin> {
4402 let isIndirectBranch = 1;
4405 // Note that these are not marked isCall or isReturn because as far as LLVM is
4406 // concerned they're not. "ret" is just another jump unless it has been selected
4407 // by LLVM as the function's return.
4409 let isBranch = 1 in {
4410 def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn),
4411 "br\t$Rn", [(brind i64:$Rn)]> {
4413 let isTerminator = 1;
4416 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4417 "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
4423 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
4426 let isTerminator = 1;
4430 // Create a separate pseudo-instruction for codegen to use so that we don't
4431 // flag x30 as used in every function. It'll be restored before the RET by the
4432 // epilogue if it's legitimately used.
4433 def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> {
4434 let isTerminator = 1;
4439 def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> {
4442 let isTerminator = 1;
4446 def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> {
4452 def RETAlias : InstAlias<"ret", (RETx X30)>;
4455 //===----------------------------------------------------------------------===//
4456 // Address generation patterns
4457 //===----------------------------------------------------------------------===//
4459 // Primary method of address generation for the small/absolute memory model is
4460 // an ADRP/ADR pair:
4461 // ADRP x0, some_variable
4462 // ADD x0, x0, #:lo12:some_variable
4464 // The load/store elision of the ADD is accomplished when selecting
4465 // addressing-modes. This just mops up the cases where that doesn't work and we
4466 // really need an address in some register.
4468 // This wrapper applies a LO12 modifier to the address. Otherwise we could just
4469 // use the same address.
4471 class ADRP_ADD<SDNode Wrapper, SDNode addrop>
4472 : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)),
4473 (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>;
4475 def : ADRP_ADD<A64WrapperSmall, tblockaddress>;
4476 def : ADRP_ADD<A64WrapperSmall, texternalsym>;
4477 def : ADRP_ADD<A64WrapperSmall, tglobaladdr>;
4478 def : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>;
4479 def : ADRP_ADD<A64WrapperSmall, tjumptable>;
4481 //===----------------------------------------------------------------------===//
4482 // GOT access patterns
4483 //===----------------------------------------------------------------------===//
4485 class GOTLoadSmall<SDNode addrfrag>
4486 : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)),
4487 (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>;
4489 def : GOTLoadSmall<texternalsym>;
4490 def : GOTLoadSmall<tglobaladdr>;
4491 def : GOTLoadSmall<tglobaltlsaddr>;
4493 //===----------------------------------------------------------------------===//
4494 // Tail call handling
4495 //===----------------------------------------------------------------------===//
4497 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in {
4499 : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff),
4500 [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>;
4503 : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff),
4504 [(AArch64tcret i64:$dst, (i32 timm:$FPDiff))]>;
4507 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
4509 def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [],
4510 (Bimm bimm_target:$Label)>;
4512 def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [],
4517 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
4518 (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>;
4520 //===----------------------------------------------------------------------===//
4521 // Thread local storage
4522 //===----------------------------------------------------------------------===//
4524 // This is a pseudo-instruction representing the ".tlsdesccall" directive in
4525 // assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the
4526 // current location. It should always be immediately followed by a BLR
4527 // instruction, and is intended solely for relaxation by the linker.
4529 def : Pat<(A64threadpointer), (MRSxi 0xde82)>;
4531 def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> {
4532 let hasSideEffects = 1;
4535 def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var),
4536 [(A64tlsdesc_blr i64:$Rn, tglobaltlsaddr:$Var)]> {
4541 def : Pat<(A64tlsdesc_blr i64:$Rn, texternalsym:$Var),
4542 (TLSDESC_BLRx $Rn, texternalsym:$Var)>;
4544 //===----------------------------------------------------------------------===//
4545 // Bitfield patterns
4546 //===----------------------------------------------------------------------===//
4548 def bfi32_lsb_to_immr : SDNodeXForm<imm, [{
4549 return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64);
4552 def bfi64_lsb_to_immr : SDNodeXForm<imm, [{
4553 return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64);
4556 def bfi_width_to_imms : SDNodeXForm<imm, [{
4557 return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64);
4561 // The simpler patterns deal with cases where no AND mask is actually needed
4562 // (either all bits are used or the low 32 bits are used).
4563 let AddedComplexity = 10 in {
4565 def : Pat<(A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4567 (bfi64_lsb_to_immr (i64 imm:$ImmR)),
4568 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4570 def : Pat<(A64Bfi i32:$src, i32:$Rn, imm:$ImmR, imm:$ImmS),
4572 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4573 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4576 def : Pat<(and (A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4578 (SUBREG_TO_REG (i64 0),
4579 (BFIwwii (EXTRACT_SUBREG $src, sub_32),
4580 (EXTRACT_SUBREG $Rn, sub_32),
4581 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4582 (bfi_width_to_imms (i64 imm:$ImmS))),
4587 //===----------------------------------------------------------------------===//
4588 // Miscellaneous patterns
4589 //===----------------------------------------------------------------------===//
4591 // Truncation from 64 to 32-bits just involves renaming your register.
4592 def : Pat<(i32 (trunc i64:$val)), (EXTRACT_SUBREG $val, sub_32)>;
4594 // Similarly, extension where we don't care about the high bits is
4596 def : Pat<(i64 (anyext i32:$val)),
4597 (INSERT_SUBREG (IMPLICIT_DEF), $val, sub_32)>;
4599 // SELECT instructions providing f128 types need to be handled by a
4600 // pseudo-instruction since the eventual code will need to introduce basic
4601 // blocks and control flow.
4602 def F128CSEL : PseudoInst<(outs FPR128:$Rd),
4603 (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond),
4604 [(set f128:$Rd, (simple_select f128:$Rn, f128:$Rm))]> {
4606 let usesCustomInserter = 1;
4609 //===----------------------------------------------------------------------===//
4610 // Load/store patterns
4611 //===----------------------------------------------------------------------===//
4613 // There are lots of patterns here, because we need to allow at least three
4614 // parameters to vary independently.
4615 // 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ...
4616 // 2. LLVM source: zextloadi8, anyextloadi8, ...
4617 // 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ...
4619 // The biggest problem turns out to be the address-generation variable. At the
4620 // point of instantiation we need to produce two DAGs, one for the pattern and
4621 // one for the instruction. Doing this at the lowest level of classes doesn't
4624 // Consider the simple uimm12 addressing mode, and the desire to match both (add
4625 // GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the
4626 // instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or
4627 // "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this
4628 // operation, and PatFrags are for selection not output.
4630 // As a result, the address-generation patterns are the final
4631 // instantiations. However, we do still need to vary the operand for the address
4632 // further down (At the point we're deciding A64WrapperSmall, we don't know
4633 // the memory width of the operation).
4635 //===------------------------------
4636 // 1. Basic infrastructural defs
4637 //===------------------------------
4639 // First, some simple classes for !foreach and !subst to use:
4650 // You can't use !subst on an actual immediate, but you *can* use it on an
4651 // operand record that happens to match a single immediate. So we do.
4652 def imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>;
4653 def imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>;
4654 def imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>;
4655 def imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>;
4656 def imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>;
4658 // If the low bits of a pointer are known to be 0 then an "or" is just as good
4659 // as addition for computing an offset. This fragment forwards that check for
4661 def add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),
4663 return CurDAG->isBaseWithConstantOffset(SDValue(N, 0));
4666 // Load/store (unsigned immediate) operations with relocations against global
4667 // symbols (for lo12) are only valid if those symbols have correct alignment
4668 // (since the immediate offset is divided by the access scale, it can't have a
4671 // The guaranteed alignment is provided as part of the WrapperSmall
4672 // operation, and checked against one of these.
4673 def any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>;
4674 def min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>;
4675 def min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>;
4676 def min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>;
4677 def min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>;
4679 // "Normal" load/store instructions can be used on atomic operations, provided
4680 // the ordering parameter is at most "monotonic". Anything above that needs
4681 // special handling with acquire/release instructions.
4682 class simple_load<PatFrag base>
4683 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4684 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4687 def atomic_load_simple_i8 : simple_load<atomic_load_8>;
4688 def atomic_load_simple_i16 : simple_load<atomic_load_16>;
4689 def atomic_load_simple_i32 : simple_load<atomic_load_32>;
4690 def atomic_load_simple_i64 : simple_load<atomic_load_64>;
4692 class simple_store<PatFrag base>
4693 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4694 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4697 def atomic_store_simple_i8 : simple_store<atomic_store_8>;
4698 def atomic_store_simple_i16 : simple_store<atomic_store_16>;
4699 def atomic_store_simple_i32 : simple_store<atomic_store_32>;
4700 def atomic_store_simple_i64 : simple_store<atomic_store_64>;
4702 //===------------------------------
4703 // 2. UImm12 and SImm9
4704 //===------------------------------
4706 // These instructions have two operands providing the address so they can be
4707 // treated similarly for most purposes.
4709 //===------------------------------
4710 // 2.1 Base patterns covering extend/truncate semantics
4711 //===------------------------------
4713 // Atomic patterns can be shared between integer operations of all sizes, a
4714 // quick multiclass here allows reuse.
4715 multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4716 dag Offset, dag address, ValueType transty,
4718 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4719 (LOAD Base, Offset)>;
4721 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
4722 (STORE $Rt, Base, Offset)>;
4725 // Instructions accessing a memory chunk smaller than a register (or, in a
4726 // pinch, the same size) have a characteristic set of patterns they want to
4727 // match: extending loads and truncating stores. This class deals with the
4728 // sign-neutral version of those patterns.
4730 // It will be instantiated across multiple addressing-modes.
4731 multiclass ls_small_pats<Instruction LOAD, Instruction STORE,
4732 dag Base, dag Offset,
4733 dag address, ValueType sty>
4734 : ls_atomic_pats<LOAD, STORE, Base, Offset, address, i32, sty> {
4735 def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>;
4737 def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>;
4739 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4740 // register was actually set.
4741 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4742 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4744 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
4745 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4747 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
4748 (STORE $Rt, Base, Offset)>;
4750 // For truncating store from 64-bits, we have to manually tell LLVM to
4751 // ignore the high bits of the x register.
4752 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
4753 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
4756 // Next come patterns for sign-extending loads.
4757 multiclass load_signed_pats<string T, string U, dag Base, dag Offset,
4758 dag address, ValueType sty> {
4759 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
4760 (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>;
4762 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
4763 (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>;
4767 // and finally "natural-width" loads and stores come next.
4768 multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4769 dag Offset, dag address, ValueType sty> {
4770 def : Pat<(sty (load address)), (LOAD Base, Offset)>;
4771 def : Pat<(store sty:$Rt, address), (STORE $Rt, Base, Offset)>;
4774 // Integer operations also get atomic instructions to select for.
4775 multiclass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4776 dag Offset, dag address, ValueType sty>
4777 : ls_neutral_pats<LOAD, STORE, Base, Offset, address, sty>,
4778 ls_atomic_pats<LOAD, STORE, Base, Offset, address, sty, sty>;
4780 //===------------------------------
4781 // 2.2. Addressing-mode instantiations
4782 //===------------------------------
4784 multiclass uimm12_pats<dag address, dag Base, dag Offset> {
4785 defm : ls_small_pats<LS8_LDR, LS8_STR, Base,
4786 !foreach(decls.pattern, Offset,
4787 !subst(OFFSET, byte_uimm12, decls.pattern)),
4788 !foreach(decls.pattern, address,
4789 !subst(OFFSET, byte_uimm12,
4790 !subst(ALIGN, any_align, decls.pattern))),
4792 defm : ls_small_pats<LS16_LDR, LS16_STR, Base,
4793 !foreach(decls.pattern, Offset,
4794 !subst(OFFSET, hword_uimm12, decls.pattern)),
4795 !foreach(decls.pattern, address,
4796 !subst(OFFSET, hword_uimm12,
4797 !subst(ALIGN, min_align2, decls.pattern))),
4799 defm : ls_small_pats<LS32_LDR, LS32_STR, Base,
4800 !foreach(decls.pattern, Offset,
4801 !subst(OFFSET, word_uimm12, decls.pattern)),
4802 !foreach(decls.pattern, address,
4803 !subst(OFFSET, word_uimm12,
4804 !subst(ALIGN, min_align4, decls.pattern))),
4807 defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base,
4808 !foreach(decls.pattern, Offset,
4809 !subst(OFFSET, word_uimm12, decls.pattern)),
4810 !foreach(decls.pattern, address,
4811 !subst(OFFSET, word_uimm12,
4812 !subst(ALIGN, min_align4, decls.pattern))),
4815 defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base,
4816 !foreach(decls.pattern, Offset,
4817 !subst(OFFSET, dword_uimm12, decls.pattern)),
4818 !foreach(decls.pattern, address,
4819 !subst(OFFSET, dword_uimm12,
4820 !subst(ALIGN, min_align8, decls.pattern))),
4823 defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base,
4824 !foreach(decls.pattern, Offset,
4825 !subst(OFFSET, hword_uimm12, decls.pattern)),
4826 !foreach(decls.pattern, address,
4827 !subst(OFFSET, hword_uimm12,
4828 !subst(ALIGN, min_align2, decls.pattern))),
4831 defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base,
4832 !foreach(decls.pattern, Offset,
4833 !subst(OFFSET, word_uimm12, decls.pattern)),
4834 !foreach(decls.pattern, address,
4835 !subst(OFFSET, word_uimm12,
4836 !subst(ALIGN, min_align4, decls.pattern))),
4839 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
4840 !foreach(decls.pattern, Offset,
4841 !subst(OFFSET, dword_uimm12, decls.pattern)),
4842 !foreach(decls.pattern, address,
4843 !subst(OFFSET, dword_uimm12,
4844 !subst(ALIGN, min_align8, decls.pattern))),
4847 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
4848 !foreach(decls.pattern, Offset,
4849 !subst(OFFSET, qword_uimm12, decls.pattern)),
4850 !foreach(decls.pattern, address,
4851 !subst(OFFSET, qword_uimm12,
4852 !subst(ALIGN, min_align16, decls.pattern))),
4855 defm : load_signed_pats<"B", "", Base,
4856 !foreach(decls.pattern, Offset,
4857 !subst(OFFSET, byte_uimm12, decls.pattern)),
4858 !foreach(decls.pattern, address,
4859 !subst(OFFSET, byte_uimm12,
4860 !subst(ALIGN, any_align, decls.pattern))),
4863 defm : load_signed_pats<"H", "", Base,
4864 !foreach(decls.pattern, Offset,
4865 !subst(OFFSET, hword_uimm12, decls.pattern)),
4866 !foreach(decls.pattern, address,
4867 !subst(OFFSET, hword_uimm12,
4868 !subst(ALIGN, min_align2, decls.pattern))),
4871 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
4872 !subst(OFFSET, word_uimm12,
4873 !subst(ALIGN, min_align4, decls.pattern)))),
4874 (LDRSWx Base, !foreach(decls.pattern, Offset,
4875 !subst(OFFSET, word_uimm12, decls.pattern)))>;
4878 // Straightforward patterns of last resort: a pointer with or without an
4879 // appropriate offset.
4880 defm : uimm12_pats<(i64 i64:$Rn), (i64 i64:$Rn), (i64 0)>;
4881 defm : uimm12_pats<(add i64:$Rn, OFFSET:$UImm12),
4882 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
4884 // The offset could be hidden behind an "or", of course:
4885 defm : uimm12_pats<(add_like_or i64:$Rn, OFFSET:$UImm12),
4886 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
4888 // Global addresses under the small-absolute model should use these
4889 // instructions. There are ELF relocations specifically for it.
4890 defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN),
4891 (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>;
4893 defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12,
4895 (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>;
4897 // External symbols that make it this far should also get standard relocations.
4898 defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12,
4900 (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>;
4902 defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
4903 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
4905 // We also want to use uimm12 instructions for local variables at the moment.
4906 def tframeindex_XFORM : SDNodeXForm<frameindex, [{
4907 int FI = cast<FrameIndexSDNode>(N)->getIndex();
4908 return CurDAG->getTargetFrameIndex(FI, MVT::i64);
4911 defm : uimm12_pats<(i64 frameindex:$Rn),
4912 (tframeindex_XFORM tframeindex:$Rn), (i64 0)>;
4914 // These can be much simpler than uimm12 because we don't to change the operand
4915 // type (e.g. LDURB and LDURH take the same operands).
4916 multiclass simm9_pats<dag address, dag Base, dag Offset> {
4917 defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>;
4918 defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>;
4920 defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address, i32>;
4921 defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address, i64>;
4923 defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address, f16>;
4924 defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address, f32>;
4925 defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address, f64>;
4926 defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address,
4929 def : Pat<(i64 (zextloadi32 address)),
4930 (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>;
4932 def : Pat<(truncstorei32 i64:$Rt, address),
4933 (LS32_STUR (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
4935 defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>;
4936 defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>;
4937 def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>;
4940 defm : simm9_pats<(add i64:$Rn, simm9:$SImm9),
4941 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
4943 defm : simm9_pats<(add_like_or i64:$Rn, simm9:$SImm9),
4944 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
4947 //===------------------------------
4948 // 3. Register offset patterns
4949 //===------------------------------
4951 // Atomic patterns can be shared between integer operations of all sizes, a
4952 // quick multiclass here allows reuse.
4953 multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4954 dag Offset, dag Extend, dag address,
4955 ValueType transty, ValueType sty> {
4956 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4957 (LOAD Base, Offset, Extend)>;
4959 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
4960 (STORE $Rt, Base, Offset, Extend)>;
4963 // The register offset instructions take three operands giving the instruction,
4964 // and have an annoying split between instructions where Rm is 32-bit and
4965 // 64-bit. So we need a special hierarchy to describe them. Other than that the
4966 // same operations should be supported as for simm9 and uimm12 addressing.
4968 multiclass ro_small_pats<Instruction LOAD, Instruction STORE,
4969 dag Base, dag Offset, dag Extend,
4970 dag address, ValueType sty>
4971 : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, i32, sty> {
4972 def : Pat<(!cast<SDNode>(zextload # sty) address),
4973 (LOAD Base, Offset, Extend)>;
4975 def : Pat<(!cast<SDNode>(extload # sty) address),
4976 (LOAD Base, Offset, Extend)>;
4978 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4979 // register was actually set.
4980 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4981 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
4983 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
4984 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
4986 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
4987 (STORE $Rt, Base, Offset, Extend)>;
4989 // For truncating store from 64-bits, we have to manually tell LLVM to
4990 // ignore the high bits of the x register.
4991 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
4992 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset, Extend)>;
4996 // Next come patterns for sign-extending loads.
4997 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
4998 dag address, ValueType sty> {
4999 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
5000 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
5001 Base, Offset, Extend)>;
5003 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
5004 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
5005 Base, Offset, Extend)>;
5008 // and finally "natural-width" loads and stores come next.
5009 multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE,
5010 dag Base, dag Offset, dag Extend, dag address,
5012 def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>;
5013 def : Pat<(store sty:$Rt, address),
5014 (STORE $Rt, Base, Offset, Extend)>;
5017 multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE,
5018 dag Base, dag Offset, dag Extend, dag address,
5020 : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, sty>,
5021 ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, sty, sty>;
5023 multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset,
5025 defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"),
5026 !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"),
5027 Base, Offset, Extend,
5028 !foreach(decls.pattern, address,
5029 !subst(SHIFT, imm_eq0, decls.pattern)),
5031 defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"),
5032 !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"),
5033 Base, Offset, Extend,
5034 !foreach(decls.pattern, address,
5035 !subst(SHIFT, imm_eq1, decls.pattern)),
5037 defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5038 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5039 Base, Offset, Extend,
5040 !foreach(decls.pattern, address,
5041 !subst(SHIFT, imm_eq2, decls.pattern)),
5044 defm : ro_int_neutral_pats<
5045 !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5046 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5047 Base, Offset, Extend,
5048 !foreach(decls.pattern, address,
5049 !subst(SHIFT, imm_eq2, decls.pattern)),
5052 defm : ro_int_neutral_pats<
5053 !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
5054 !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
5055 Base, Offset, Extend,
5056 !foreach(decls.pattern, address,
5057 !subst(SHIFT, imm_eq3, decls.pattern)),
5060 defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"),
5061 !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"),
5062 Base, Offset, Extend,
5063 !foreach(decls.pattern, address,
5064 !subst(SHIFT, imm_eq1, decls.pattern)),
5067 defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"),
5068 !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"),
5069 Base, Offset, Extend,
5070 !foreach(decls.pattern, address,
5071 !subst(SHIFT, imm_eq2, decls.pattern)),
5074 defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"),
5075 !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"),
5076 Base, Offset, Extend,
5077 !foreach(decls.pattern, address,
5078 !subst(SHIFT, imm_eq3, decls.pattern)),
5081 defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"),
5082 !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"),
5083 Base, Offset, Extend,
5084 !foreach(decls.pattern, address,
5085 !subst(SHIFT, imm_eq4, decls.pattern)),
5088 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,
5089 !foreach(decls.pattern, address,
5090 !subst(SHIFT, imm_eq0, decls.pattern)),
5093 defm : ro_signed_pats<"H", Rm, Base, Offset, Extend,
5094 !foreach(decls.pattern, address,
5095 !subst(SHIFT, imm_eq1, decls.pattern)),
5098 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
5099 !subst(SHIFT, imm_eq2, decls.pattern))),
5100 (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset")
5101 Base, Offset, Extend)>;
5105 // Finally we're in a position to tell LLVM exactly what addresses are reachable
5106 // using register-offset instructions. Essentially a base plus a possibly
5107 // extended, possibly shifted (by access size) offset.
5109 defm : regoff_pats<"Wm", (add i64:$Rn, (sext i32:$Rm)),
5110 (i64 i64:$Rn), (i32 i32:$Rm), (i64 6)>;
5112 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (sext i32:$Rm), SHIFT)),
5113 (i64 i64:$Rn), (i32 i32:$Rm), (i64 7)>;
5115 defm : regoff_pats<"Wm", (add i64:$Rn, (zext i32:$Rm)),
5116 (i64 i64:$Rn), (i32 i32:$Rm), (i64 2)>;
5118 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (zext i32:$Rm), SHIFT)),
5119 (i64 i64:$Rn), (i32 i32:$Rm), (i64 3)>;
5121 defm : regoff_pats<"Xm", (add i64:$Rn, i64:$Rm),
5122 (i64 i64:$Rn), (i64 i64:$Rm), (i64 2)>;
5124 defm : regoff_pats<"Xm", (add i64:$Rn, (shl i64:$Rm, SHIFT)),
5125 (i64 i64:$Rn), (i64 i64:$Rm), (i64 3)>;