1 //===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 scalar instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto","crypto">;
24 // Use fused MAC if more precision in FP computation is allowed.
25 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
26 " FPOpFusion::Fast)">;
27 include "AArch64InstrFormats.td"
29 //===----------------------------------------------------------------------===//
30 // AArch64 specific pattern fragments.
32 // An 'fmul' node with a single use.
33 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
34 return N->hasOneUse();
38 //===----------------------------------------------------------------------===//
39 // Target-specific ISD nodes and profiles
40 //===----------------------------------------------------------------------===//
42 def SDT_A64ret : SDTypeProfile<0, 0, []>;
43 def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain,
47 // (ins NZCV, Condition, Dest)
48 def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>;
49 def A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>;
51 // (outs Result), (ins NZCV, IfTrue, IfFalse, Condition)
52 def SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>,
55 def A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>;
57 // (outs NZCV), (ins LHS, RHS, Condition)
58 def SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
60 def A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>;
63 // (outs GPR64), (ins)
64 def A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
66 // A64 compares don't care about the cond really (they set all flags) so a
67 // simple binary operator is useful.
68 def A64cmp : PatFrag<(ops node:$lhs, node:$rhs),
69 (A64setcc node:$lhs, node:$rhs, cond)>;
72 // When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN
73 // instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C
74 // and V flags can be set differently by this operation. It comes down to
75 // whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are
76 // then everything is fine. If not then the optimization is wrong. Thus general
77 // comparisons are only valid if op2 != 0.
79 // So, finally, the only LLVM-native comparisons that don't mention C and V are
80 // SETEQ and SETNE. They're the only ones we can safely use CMN for in the
81 // absence of information about op2.
82 def equality_cond : PatLeaf<(cond), [{
83 return N->get() == ISD::SETEQ || N->get() == ISD::SETNE;
86 def A64cmn : PatFrag<(ops node:$lhs, node:$rhs),
87 (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>;
89 // There are two layers of indirection here, driven by the following
91 // + TableGen does not know CodeModel or Reloc so that decision should be
92 // made for a variable/address at ISelLowering.
93 // + The output of ISelLowering should be selectable (hence the Wrapper,
94 // rather than a bare target opcode)
95 def SDTAArch64WrapperLarge : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
101 def A64WrapperLarge :SDNode<"AArch64ISD::WrapperLarge", SDTAArch64WrapperLarge>;
103 def SDTAArch64WrapperSmall : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
108 def A64WrapperSmall :SDNode<"AArch64ISD::WrapperSmall", SDTAArch64WrapperSmall>;
111 def SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
112 def A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad,
116 // (A64BFI LHS, RHS, LSB, Width)
117 def SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
122 def A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>;
124 // (A64EXTR HiReg, LoReg, LSB)
125 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
127 def A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
129 // (A64[SU]BFX Field, ImmR, ImmS).
131 // Note that ImmR and ImmS are already encoded for the actual instructions. The
132 // more natural LSB and Width mix together to form ImmR and ImmS, something
133 // which TableGen can't handle.
134 def SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>;
135 def A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>;
137 def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>;
139 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
141 //===----------------------------------------------------------------------===//
142 // Call sequence pseudo-instructions
143 //===----------------------------------------------------------------------===//
146 def SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
147 def AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
150 def AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call,
151 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
153 // The TLSDESCCALL node is a variant call which goes to an indirectly calculated
154 // destination but needs a relocation against a fixed symbol. As such it has two
155 // certain operands: the callee and the relocated variable.
157 // The TLS ABI only allows it to be selected to a BLR instructin (with
158 // appropriate relocation).
159 def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
161 def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall,
162 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
166 def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>;
167 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart,
168 [SDNPHasChain, SDNPOutGlue]>;
170 def SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>;
171 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd,
172 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
176 // These pseudo-instructions have special semantics by virtue of being passed to
177 // the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by
178 // LowerCall to (in our case) tell the back-end about stack adjustments for
179 // arguments passed on the stack. Here we select those markers to
180 // pseudo-instructions which explicitly set the stack, and finally in the
181 // RegisterInfo we convert them to a true stack adjustment.
182 let Defs = [XSP], Uses = [XSP] in {
183 def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt),
184 [(AArch64callseq_start timm:$amt)]>;
186 def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2),
187 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
190 //===----------------------------------------------------------------------===//
191 // Atomic operation pseudo-instructions
192 //===----------------------------------------------------------------------===//
194 // These get selected from C++ code as a pretty much direct translation from the
195 // generic DAG nodes. The one exception is the AtomicOrdering is added as an
196 // operand so that the eventual lowering can make use of it and choose
197 // acquire/release operations when required.
199 let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in {
200 multiclass AtomicSizes {
201 def _I8 : PseudoInst<(outs GPR32:$dst),
202 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
203 def _I16 : PseudoInst<(outs GPR32:$dst),
204 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
205 def _I32 : PseudoInst<(outs GPR32:$dst),
206 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
207 def _I64 : PseudoInst<(outs GPR64:$dst),
208 (ins GPR64xsp:$ptr, GPR64:$incr, i32imm:$ordering), []>;
212 defm ATOMIC_LOAD_ADD : AtomicSizes;
213 defm ATOMIC_LOAD_SUB : AtomicSizes;
214 defm ATOMIC_LOAD_AND : AtomicSizes;
215 defm ATOMIC_LOAD_OR : AtomicSizes;
216 defm ATOMIC_LOAD_XOR : AtomicSizes;
217 defm ATOMIC_LOAD_NAND : AtomicSizes;
218 defm ATOMIC_SWAP : AtomicSizes;
219 let Defs = [NZCV] in {
220 // These operations need a CMP to calculate the correct value
221 defm ATOMIC_LOAD_MIN : AtomicSizes;
222 defm ATOMIC_LOAD_MAX : AtomicSizes;
223 defm ATOMIC_LOAD_UMIN : AtomicSizes;
224 defm ATOMIC_LOAD_UMAX : AtomicSizes;
227 class AtomicCmpSwap<RegisterClass GPRData>
228 : PseudoInst<(outs GPRData:$dst),
229 (ins GPR64xsp:$ptr, GPRData:$old, GPRData:$new,
230 i32imm:$ordering), []> {
231 let usesCustomInserter = 1;
238 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>;
239 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>;
240 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>;
241 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>;
243 //===----------------------------------------------------------------------===//
244 // Add-subtract (extended register) instructions
245 //===----------------------------------------------------------------------===//
246 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP
248 // The RHS of these operations is conceptually a sign/zero-extended
249 // register, optionally shifted left by 1-4. The extension can be a
250 // NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but
251 // must be specified with one exception:
253 // If one of the registers is sp/wsp then LSL is an alias for UXTW in
254 // 32-bit instructions and UXTX in 64-bit versions, the shift amount
255 // is not optional in that case (but can explicitly be 0), and the
256 // entire suffix can be skipped (e.g. "add sp, x3, x2").
258 multiclass extend_operands<string PREFIX, string Diag> {
259 def _asmoperand : AsmOperandClass {
261 let RenderMethod = "addRegExtendOperands";
262 let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">";
263 let DiagnosticType = "AddSubRegExtend" # Diag;
266 def _operand : Operand<i64>,
267 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> {
268 let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">";
269 let DecoderMethod = "DecodeRegExtendOperand";
270 let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand");
274 defm UXTB : extend_operands<"UXTB", "Small">;
275 defm UXTH : extend_operands<"UXTH", "Small">;
276 defm UXTW : extend_operands<"UXTW", "Small">;
277 defm UXTX : extend_operands<"UXTX", "Large">;
278 defm SXTB : extend_operands<"SXTB", "Small">;
279 defm SXTH : extend_operands<"SXTH", "Small">;
280 defm SXTW : extend_operands<"SXTW", "Small">;
281 defm SXTX : extend_operands<"SXTX", "Large">;
283 def LSL_extasmoperand : AsmOperandClass {
284 let Name = "RegExtendLSL";
285 let RenderMethod = "addRegExtendOperands";
286 let DiagnosticType = "AddSubRegExtendLarge";
289 def LSL_extoperand : Operand<i64> {
290 let ParserMatchClass = LSL_extasmoperand;
294 // The patterns for various sign-extensions are a little ugly and
295 // non-uniform because everything has already been promoted to the
296 // legal i64 and i32 types. We'll wrap the various variants up in a
297 // class for use later.
299 dag uxtb; dag uxth; dag uxtw; dag uxtx;
300 dag sxtb; dag sxth; dag sxtw; dag sxtx;
305 def extends_to_i64 : extend_types {
306 let uxtb = (and (anyext i32:$Rm), 255);
307 let uxth = (and (anyext i32:$Rm), 65535);
308 let uxtw = (zext i32:$Rm);
309 let uxtx = (i64 $Rm);
311 let sxtb = (sext_inreg (anyext i32:$Rm), i8);
312 let sxth = (sext_inreg (anyext i32:$Rm), i16);
313 let sxtw = (sext i32:$Rm);
314 let sxtx = (i64 $Rm);
321 def extends_to_i32 : extend_types {
322 let uxtb = (and i32:$Rm, 255);
323 let uxth = (and i32:$Rm, 65535);
324 let uxtw = (i32 i32:$Rm);
325 let uxtx = (i32 i32:$Rm);
327 let sxtb = (sext_inreg i32:$Rm, i8);
328 let sxth = (sext_inreg i32:$Rm, i16);
329 let sxtw = (i32 i32:$Rm);
330 let sxtx = (i32 i32:$Rm);
336 // Now, six of the extensions supported are easy and uniform: if the source size
337 // is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate
338 // those instructions in one block.
340 // The uxtx/sxtx could potentially be merged in, but three facts dissuaded me:
341 // + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would
343 // + Patterns are very different as well.
344 // + Passing different registers would be ugly (more fields in extend_types
345 // would probably be the best option).
346 multiclass addsub_exts<bit sf, bit op, bit S, string asmop,
347 SDPatternOperator opfrag,
348 dag outs, extend_types exts> {
349 def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000,
350 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
351 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
352 [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
354 def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001,
355 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
356 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
357 [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
359 def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010,
360 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
361 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
362 [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
365 def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100,
366 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
367 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
368 [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
370 def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101,
371 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
372 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
373 [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
375 def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110,
376 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
377 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
378 [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
382 // These two could be merge in with the above, but their patterns aren't really
383 // necessary and the naming-scheme would necessarily break:
384 multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag,
386 def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011,
388 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
389 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
390 [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))],
393 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
395 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),
396 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
397 [/* No Pattern: same as uxtx */],
401 multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {
402 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
404 (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
405 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
406 [/* No pattern: probably same as uxtw */],
409 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,
411 (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
412 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
413 [/* No Pattern: probably same as uxtw */],
417 class SetRD<RegisterClass RC, SDPatternOperator op>
418 : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>;
419 class SetNZCV<SDPatternOperator op>
420 : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>;
422 defm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
423 (outs GPR64xsp:$Rd), extends_to_i64>,
424 addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
425 (outs GPR64xsp:$Rd)>;
426 defm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>,
427 (outs GPR32wsp:$Rd), extends_to_i32>,
428 addsub_wxtx< 0b0, 0b0, "add\t$Rd, ",
429 (outs GPR32wsp:$Rd)>;
430 defm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
431 (outs GPR64xsp:$Rd), extends_to_i64>,
432 addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
433 (outs GPR64xsp:$Rd)>;
434 defm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>,
435 (outs GPR32wsp:$Rd), extends_to_i32>,
436 addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ",
437 (outs GPR32wsp:$Rd)>;
439 let Defs = [NZCV] in {
440 defm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
441 (outs GPR64:$Rd), extends_to_i64>,
442 addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
444 defm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>,
445 (outs GPR32:$Rd), extends_to_i32>,
446 addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ",
448 defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
449 (outs GPR64:$Rd), extends_to_i64>,
450 addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
452 defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>,
453 (outs GPR32:$Rd), extends_to_i32>,
454 addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ",
458 let Rd = 0b11111, isCompare = 1 in {
459 defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
460 (outs), extends_to_i64>,
461 addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
462 defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
463 (outs), extends_to_i32>,
464 addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>;
465 defm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
466 (outs), extends_to_i64>,
467 addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>;
468 defm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
469 (outs), extends_to_i32>,
470 addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>;
474 // Now patterns for the operation without a shift being needed. No patterns are
475 // created for uxtx/sxtx since they're non-uniform and it's expected that
476 // add/sub (shifted register) will handle those cases anyway.
477 multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop,
479 def : Pat<(nodeop exts.ty:$Rn, exts.uxtb),
480 (!cast<Instruction>(prefix # "w_uxtb") $Rn, $Rm, 0)>;
481 def : Pat<(nodeop exts.ty:$Rn, exts.uxth),
482 (!cast<Instruction>(prefix # "w_uxth") $Rn, $Rm, 0)>;
483 def : Pat<(nodeop exts.ty:$Rn, exts.uxtw),
484 (!cast<Instruction>(prefix # "w_uxtw") $Rn, $Rm, 0)>;
486 def : Pat<(nodeop exts.ty:$Rn, exts.sxtb),
487 (!cast<Instruction>(prefix # "w_sxtb") $Rn, $Rm, 0)>;
488 def : Pat<(nodeop exts.ty:$Rn, exts.sxth),
489 (!cast<Instruction>(prefix # "w_sxth") $Rn, $Rm, 0)>;
490 def : Pat<(nodeop exts.ty:$Rn, exts.sxtw),
491 (!cast<Instruction>(prefix # "w_sxtw") $Rn, $Rm, 0)>;
494 defm : addsubext_noshift_patterns<"ADDxx", add, extends_to_i64>;
495 defm : addsubext_noshift_patterns<"ADDww", add, extends_to_i32>;
496 defm : addsubext_noshift_patterns<"SUBxx", sub, extends_to_i64>;
497 defm : addsubext_noshift_patterns<"SUBww", sub, extends_to_i32>;
499 defm : addsubext_noshift_patterns<"CMNx", A64cmn, extends_to_i64>;
500 defm : addsubext_noshift_patterns<"CMNw", A64cmn, extends_to_i32>;
501 defm : addsubext_noshift_patterns<"CMPx", A64cmp, extends_to_i64>;
502 defm : addsubext_noshift_patterns<"CMPw", A64cmp, extends_to_i32>;
504 // An extend of "lsl #imm" is valid if and only if one of Rn and Rd is
505 // sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the
506 // operation. Also permitted in this case is complete omission of the argument,
507 // which implies "lsl #0".
508 multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd,
509 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
510 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
511 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
513 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"),
514 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
518 defm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
519 defm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
520 defm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>;
521 defm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>;
522 defm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
523 defm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
524 defm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>;
525 defm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>;
527 // Rd cannot be sp for flag-setting variants so only half of the aliases are
529 defm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>;
530 defm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>;
531 defm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>;
532 defm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>;
534 // CMP unfortunately has to be different because the instruction doesn't have a
536 multiclass cmp_lsl_aliases<string asmop, Instruction inst,
537 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
538 def : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
539 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
541 def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"),
542 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
545 defm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>;
546 defm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>;
547 defm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>;
548 defm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>;
550 //===----------------------------------------------------------------------===//
551 // Add-subtract (immediate) instructions
552 //===----------------------------------------------------------------------===//
553 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV
555 // These instructions accept a 12-bit unsigned immediate, optionally shifted
556 // left by 12 bits. Official assembly format specifies a 12 bit immediate with
557 // one of "", "LSL #0", "LSL #12" supplementary operands.
559 // There are surprisingly few ways to make this work with TableGen, so this
560 // implementation has separate instructions for the "LSL #0" and "LSL #12"
563 // If the MCInst retained a single combined immediate (which could be 0x123000,
564 // for example) then both components (imm & shift) would have to be delegated to
565 // a single assembly operand. This would entail a separate operand parser
566 // (because the LSL would have to live in the same AArch64Operand as the
567 // immediate to be accessible); assembly parsing is rather complex and
568 // error-prone C++ code.
570 // By splitting the immediate, we can delegate handling this optional operand to
571 // an InstAlias. Supporting functions to generate the correct MCInst are still
572 // required, but these are essentially trivial and parsing can remain generic.
574 // Rejected plans with rationale:
575 // ------------------------------
577 // In an ideal world you'de have two first class immediate operands (in
578 // InOperandList, specifying imm12 and shift). Unfortunately this is not
579 // selectable by any means I could discover.
581 // An Instruction with two MCOperands hidden behind a single entry in
582 // InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional,
583 // but required more C++ code to handle encoding/decoding. Parsing (the intended
584 // main beneficiary) ended up equally complex because of the optional nature of
587 // Attempting to circumvent the need for a custom OperandParser above by giving
588 // InstAliases without the "lsl #0" failed. add/sub could be accommodated but
589 // the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands
590 // should be parsed: there was no way to accommodate an "lsl #12".
592 let ParserMethod = "ParseImmWithLSLOperand",
593 RenderMethod = "addImmWithLSLOperands" in {
594 // Derived PredicateMethod fields are different for each
595 def addsubimm_lsl0_asmoperand : AsmOperandClass {
596 let Name = "AddSubImmLSL0";
597 // If an error is reported against this operand, instruction could also be a
599 let DiagnosticType = "AddSubSecondSource";
602 def addsubimm_lsl12_asmoperand : AsmOperandClass {
603 let Name = "AddSubImmLSL12";
604 let DiagnosticType = "AddSubSecondSource";
608 def shr_12_XFORM : SDNodeXForm<imm, [{
609 return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32);
612 def shr_12_neg_XFORM : SDNodeXForm<imm, [{
613 return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32);
616 def neg_XFORM : SDNodeXForm<imm, [{
617 return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32);
621 multiclass addsub_imm_operands<ValueType ty> {
622 let PrintMethod = "printAddSubImmLSL0Operand",
623 EncoderMethod = "getAddSubImmOpValue",
624 ParserMatchClass = addsubimm_lsl0_asmoperand in {
625 def _posimm_lsl0 : Operand<ty>,
626 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>;
627 def _negimm_lsl0 : Operand<ty>,
628 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }],
632 let PrintMethod = "printAddSubImmLSL12Operand",
633 EncoderMethod = "getAddSubImmOpValue",
634 ParserMatchClass = addsubimm_lsl12_asmoperand in {
635 def _posimm_lsl12 : Operand<ty>,
636 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }],
639 def _negimm_lsl12 : Operand<ty>,
640 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }],
645 // The add operands don't need any transformation
646 defm addsubimm_operand_i32 : addsub_imm_operands<i32>;
647 defm addsubimm_operand_i64 : addsub_imm_operands<i64>;
649 multiclass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift,
650 string asmop, string cmpasmop,
651 Operand imm_operand, Operand cmp_imm_operand,
652 RegisterClass GPR, RegisterClass GPRsp,
653 AArch64Reg ZR, ValueType Ty> {
654 // All registers for non-S variants allow SP
655 def _s : A64I_addsubimm<sf, op, 0b0, shift,
657 (ins GPRsp:$Rn, imm_operand:$Imm12),
658 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
659 [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],
663 // S variants can read SP but would write to ZR
664 def _S : A64I_addsubimm<sf, op, 0b1, shift,
666 (ins GPRsp:$Rn, imm_operand:$Imm12),
667 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
668 [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],
673 // Note that the pattern here for ADDS is subtle. Canonically CMP
674 // a, b becomes SUBS a, b. If b < 0 then this is equivalent to
675 // ADDS a, (-b). This is not true in general.
676 def _cmp : A64I_addsubimm<sf, op, 0b1, shift,
677 (outs), (ins GPRsp:$Rn, imm_operand:$Imm12),
678 !strconcat(cmpasmop, " $Rn, $Imm12"),
680 (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
689 multiclass addsubimm_shifts<string prefix, bit sf, bit op,
690 string asmop, string cmpasmop, string operand, string cmpoperand,
691 RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR,
693 defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00,
695 !cast<Operand>(operand # "_lsl0"),
696 !cast<Operand>(cmpoperand # "_lsl0"),
699 defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01,
701 !cast<Operand>(operand # "_lsl12"),
702 !cast<Operand>(cmpoperand # "_lsl12"),
706 defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn",
707 "addsubimm_operand_i32_posimm",
708 "addsubimm_operand_i32_negimm",
709 GPR32, GPR32wsp, WZR, i32>;
710 defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn",
711 "addsubimm_operand_i64_posimm",
712 "addsubimm_operand_i64_negimm",
713 GPR64, GPR64xsp, XZR, i64>;
714 defm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp",
715 "addsubimm_operand_i32_negimm",
716 "addsubimm_operand_i32_posimm",
717 GPR32, GPR32wsp, WZR, i32>;
718 defm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp",
719 "addsubimm_operand_i64_negimm",
720 "addsubimm_operand_i64_posimm",
721 GPR64, GPR64xsp, XZR, i64>;
723 multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> {
724 def _fromsp : InstAlias<"mov $Rd, $Rn",
725 (addop GPRsp:$Rd, SP:$Rn, 0),
728 def _tosp : InstAlias<"mov $Rd, $Rn",
729 (addop SP:$Rd, GPRsp:$Rn, 0),
733 // Recall Rxsp is a RegisterClass containing *just* xsp.
734 defm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>;
735 defm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>;
737 //===----------------------------------------------------------------------===//
738 // Add-subtract (shifted register) instructions
739 //===----------------------------------------------------------------------===//
740 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS
742 //===-------------------------------
743 // 1. The "shifed register" operands. Shared with logical insts.
744 //===-------------------------------
746 multiclass shift_operands<string prefix, string form> {
747 def _asmoperand_i32 : AsmOperandClass {
748 let Name = "Shift" # form # "i32";
749 let RenderMethod = "addShiftOperands";
750 let PredicateMethod = "isShift<A64SE::" # form # ", false>";
751 let DiagnosticType = "AddSubRegShift32";
754 // Note that the operand type is intentionally i64 because the DAGCombiner
755 // puts these into a canonical form.
756 def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
758 = !cast<AsmOperandClass>(prefix # "_asmoperand_i32");
759 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
760 let DecoderMethod = "Decode32BitShiftOperand";
763 def _asmoperand_i64 : AsmOperandClass {
764 let Name = "Shift" # form # "i64";
765 let RenderMethod = "addShiftOperands";
766 let PredicateMethod = "isShift<A64SE::" # form # ", true>";
767 let DiagnosticType = "AddSubRegShift64";
770 def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
772 = !cast<AsmOperandClass>(prefix # "_asmoperand_i64");
773 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
777 defm lsl_operand : shift_operands<"lsl_operand", "LSL">;
778 defm lsr_operand : shift_operands<"lsr_operand", "LSR">;
779 defm asr_operand : shift_operands<"asr_operand", "ASR">;
781 // Not used for add/sub, but defined here for completeness. The "logical
782 // (shifted register)" instructions *do* have an ROR variant.
783 defm ror_operand : shift_operands<"ror_operand", "ROR">;
785 //===-------------------------------
786 // 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions.
787 //===-------------------------------
789 // N.b. the commutable parameter is just !N. It will be first against the wall
790 // when the revolution comes.
791 multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable,
792 string asmop, SDPatternOperator opfrag, ValueType ty,
793 RegisterClass GPR, list<Register> defs> {
794 let isCommutable = commutable, Defs = defs in {
795 def _lsl : A64I_addsubshift<sf, op, s, 0b00,
797 (ins GPR:$Rn, GPR:$Rm,
798 !cast<Operand>("lsl_operand_" # ty):$Imm6),
799 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
800 [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
801 !cast<Operand>("lsl_operand_" # ty):$Imm6))
805 def _lsr : A64I_addsubshift<sf, op, s, 0b01,
807 (ins GPR:$Rn, GPR:$Rm,
808 !cast<Operand>("lsr_operand_" # ty):$Imm6),
809 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
810 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
811 !cast<Operand>("lsr_operand_" # ty):$Imm6))
815 def _asr : A64I_addsubshift<sf, op, s, 0b10,
817 (ins GPR:$Rn, GPR:$Rm,
818 !cast<Operand>("asr_operand_" # ty):$Imm6),
819 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
820 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
821 !cast<Operand>("asr_operand_" # ty):$Imm6))
827 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
828 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
831 def : Pat<(opfrag ty:$Rn, ty:$Rm),
832 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
835 multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable,
836 string asmop, SDPatternOperator opfrag,
837 list<Register> defs> {
838 defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s,
839 commutable, asmop, opfrag, i64, GPR64, defs>;
840 defm www : addsub_shifts<prefix # "www", 0b0, op, s,
841 commutable, asmop, opfrag, i32, GPR32, defs>;
845 defm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>;
846 defm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>;
848 defm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>;
849 defm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>;
851 //===-------------------------------
852 // 1. The NEG/NEGS aliases
853 //===-------------------------------
855 multiclass neg_alias<Instruction INST, RegisterClass GPR, Register ZR,
856 ValueType ty, Operand shift_operand, SDNode shiftop> {
857 def : InstAlias<"neg $Rd, $Rm, $Imm6",
858 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
860 def : Pat<(sub 0, (shiftop ty:$Rm, shift_operand:$Imm6)),
861 (INST ZR, $Rm, shift_operand:$Imm6)>;
864 defm : neg_alias<SUBwww_lsl, GPR32, WZR, i32, lsl_operand_i32, shl>;
865 defm : neg_alias<SUBwww_lsr, GPR32, WZR, i32, lsr_operand_i32, srl>;
866 defm : neg_alias<SUBwww_asr, GPR32, WZR, i32, asr_operand_i32, sra>;
867 def : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
868 def : Pat<(sub 0, i32:$Rm), (SUBwww_lsl WZR, $Rm, 0)>;
870 defm : neg_alias<SUBxxx_lsl, GPR64, XZR, i64, lsl_operand_i64, shl>;
871 defm : neg_alias<SUBxxx_lsr, GPR64, XZR, i64, lsr_operand_i64, srl>;
872 defm : neg_alias<SUBxxx_asr, GPR64, XZR, i64, asr_operand_i64, sra>;
873 def : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
874 def : Pat<(sub 0, i64:$Rm), (SUBxxx_lsl XZR, $Rm, 0)>;
876 // NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to
878 class negs_alias<Instruction INST, RegisterClass GPR,
879 Register ZR, Operand shift_operand, SDNode shiftop>
880 : InstAlias<"negs $Rd, $Rm, $Imm6",
881 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
883 def : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>;
884 def : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>;
885 def : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>;
886 def : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
888 def : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>;
889 def : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>;
890 def : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>;
891 def : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
893 //===-------------------------------
894 // 1. The CMP/CMN aliases
895 //===-------------------------------
897 multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable,
898 string asmop, SDPatternOperator opfrag, ValueType ty,
900 let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in {
901 def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00,
903 (ins GPR:$Rn, GPR:$Rm,
904 !cast<Operand>("lsl_operand_" # ty):$Imm6),
905 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
906 [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm,
907 !cast<Operand>("lsl_operand_" # ty):$Imm6))
911 def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01,
913 (ins GPR:$Rn, GPR:$Rm,
914 !cast<Operand>("lsr_operand_" # ty):$Imm6),
915 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
916 [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm,
917 !cast<Operand>("lsr_operand_" # ty):$Imm6))
921 def _asr : A64I_addsubshift<sf, op, 0b1, 0b10,
923 (ins GPR:$Rn, GPR:$Rm,
924 !cast<Operand>("asr_operand_" # ty):$Imm6),
925 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
926 [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm,
927 !cast<Operand>("asr_operand_" # ty):$Imm6))
933 : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
934 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
936 def : Pat<(opfrag ty:$Rn, ty:$Rm),
937 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
940 defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, i32, GPR32>;
941 defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, i64, GPR64>;
943 defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, i32, GPR32>;
944 defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, i64, GPR64>;
946 //===----------------------------------------------------------------------===//
947 // Add-subtract (with carry) instructions
948 //===----------------------------------------------------------------------===//
949 // Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS
951 multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> {
952 let Uses = [NZCV] in {
953 def www : A64I_addsubcarry<0b0, op, s, 0b000000,
954 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
955 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
958 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,
959 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
960 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
965 let isCommutable = 1 in {
966 defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">;
969 defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">;
971 let Defs = [NZCV] in {
972 let isCommutable = 1 in {
973 defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">;
976 defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">;
979 def : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>;
980 def : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
981 def : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>;
982 def : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
984 // Note that adde and sube can form a chain longer than two (e.g. for 256-bit
985 // addition). So the flag-setting instructions are appropriate.
986 def : Pat<(adde i32:$Rn, i32:$Rm), (ADCSwww $Rn, $Rm)>;
987 def : Pat<(adde i64:$Rn, i64:$Rm), (ADCSxxx $Rn, $Rm)>;
988 def : Pat<(sube i32:$Rn, i32:$Rm), (SBCSwww $Rn, $Rm)>;
989 def : Pat<(sube i64:$Rn, i64:$Rm), (SBCSxxx $Rn, $Rm)>;
991 //===----------------------------------------------------------------------===//
993 //===----------------------------------------------------------------------===//
994 // Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL,
997 // Because of the rather complicated nearly-overlapping aliases, the decoding of
998 // this range of instructions is handled manually. The architectural
999 // instructions are BFM, SBFM and UBFM but a disassembler should never produce
1002 // In the end, the best option was to use BFM instructions for decoding under
1003 // almost all circumstances, but to create aliasing *Instructions* for each of
1004 // the canonical forms and specify a completely custom decoder which would
1005 // substitute the correct MCInst as needed.
1007 // This also simplifies instruction selection, parsing etc because the MCInsts
1008 // have a shape that's closer to their use in code.
1010 //===-------------------------------
1011 // 1. The architectural BFM instructions
1012 //===-------------------------------
1014 def uimm5_asmoperand : AsmOperandClass {
1016 let PredicateMethod = "isUImm<5>";
1017 let RenderMethod = "addImmOperands";
1018 let DiagnosticType = "UImm5";
1021 def uimm6_asmoperand : AsmOperandClass {
1023 let PredicateMethod = "isUImm<6>";
1024 let RenderMethod = "addImmOperands";
1025 let DiagnosticType = "UImm6";
1028 def bitfield32_imm : Operand<i64>,
1029 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> {
1030 let ParserMatchClass = uimm5_asmoperand;
1032 let DecoderMethod = "DecodeBitfield32ImmOperand";
1036 def bitfield64_imm : Operand<i64>,
1037 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
1038 let ParserMatchClass = uimm6_asmoperand;
1040 // Default decoder works in 64-bit case: the 6-bit field can take any value.
1043 multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> {
1044 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1045 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1046 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1048 let DecoderMethod = "DecodeBitfieldInstruction";
1051 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1052 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1053 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1055 let DecoderMethod = "DecodeBitfieldInstruction";
1059 defm SBFM : A64I_bitfieldSizes<0b00, "sbfm">;
1060 defm UBFM : A64I_bitfieldSizes<0b10, "ubfm">;
1062 // BFM instructions modify the destination register rather than defining it
1065 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1066 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1067 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1068 let DecoderMethod = "DecodeBitfieldInstruction";
1069 let Constraints = "$src = $Rd";
1073 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1074 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1075 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1076 let DecoderMethod = "DecodeBitfieldInstruction";
1077 let Constraints = "$src = $Rd";
1081 //===-------------------------------
1082 // 2. Extend aliases to 64-bit dest
1083 //===-------------------------------
1085 // Unfortunately the extensions that end up as 64-bits cannot be handled by an
1086 // instruction alias: their syntax is (for example) "SXTB x0, w0", which needs
1087 // to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is
1088 // not capable of such a map as far as I'm aware
1090 // Note that these instructions are strictly more specific than the
1091 // BFM ones (in ImmR) so they can handle their own decoding.
1092 class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, ValueType dty,
1093 string asmop, bits<6> imms, dag pattern>
1094 : A64I_bitfield<sf, opc, sf,
1095 (outs GPRDest:$Rd), (ins GPR32:$Rn),
1096 !strconcat(asmop, "\t$Rd, $Rn"),
1097 [(set dty:$Rd, pattern)], NoItinerary> {
1098 let ImmR = 0b000000;
1102 // Signed extensions
1103 def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtb", 7,
1104 (sext_inreg (anyext i32:$Rn), i8)>;
1105 def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxtb", 7,
1106 (sext_inreg i32:$Rn, i8)>;
1107 def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxth", 15,
1108 (sext_inreg (anyext i32:$Rn), i16)>;
1109 def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxth", 15,
1110 (sext_inreg i32:$Rn, i16)>;
1111 def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtw", 31, (sext i32:$Rn)>;
1113 // Unsigned extensions
1114 def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxtb", 7,
1115 (and i32:$Rn, 255)>;
1116 def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxth", 15,
1117 (and i32:$Rn, 65535)>;
1119 // The 64-bit unsigned variants are not strictly architectural but recommended
1121 let isAsmParserOnly = 1 in {
1122 def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxtb", 7,
1123 (and (anyext i32:$Rn), 255)>;
1124 def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxth", 15,
1125 (and (anyext i32:$Rn), 65535)>;
1128 // Extra patterns for when the source register is actually 64-bits
1129 // too. There's no architectural difference here, it's just LLVM
1130 // shinanigans. There's no need for equivalent zero-extension patterns
1131 // because they'll already be caught by logical (immediate) matching.
1132 def : Pat<(sext_inreg i64:$Rn, i8),
1133 (SXTBxw (EXTRACT_SUBREG $Rn, sub_32))>;
1134 def : Pat<(sext_inreg i64:$Rn, i16),
1135 (SXTHxw (EXTRACT_SUBREG $Rn, sub_32))>;
1136 def : Pat<(sext_inreg i64:$Rn, i32),
1137 (SXTWxw (EXTRACT_SUBREG $Rn, sub_32))>;
1140 //===-------------------------------
1141 // 3. Aliases for ASR and LSR (the simple shifts)
1142 //===-------------------------------
1144 // These also handle their own decoding because ImmS being set makes
1145 // them take precedence over BFM.
1146 multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> {
1147 def wwi : A64I_bitfield<0b0, opc, 0b0,
1148 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
1149 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1150 [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))],
1155 def xxi : A64I_bitfield<0b1, opc, 0b1,
1156 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
1157 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1158 [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))],
1165 defm ASR : A64I_shift<0b00, "asr", sra>;
1166 defm LSR : A64I_shift<0b10, "lsr", srl>;
1168 //===-------------------------------
1169 // 4. Aliases for LSL
1170 //===-------------------------------
1172 // Unfortunately LSL and subsequent aliases are much more complicated. We need
1173 // to be able to say certain output instruction fields depend in a complex
1174 // manner on combinations of input assembly fields).
1176 // MIOperandInfo *might* have been able to do it, but at the cost of
1177 // significantly more C++ code.
1179 // N.b. contrary to usual practice these operands store the shift rather than
1180 // the machine bits in an MCInst. The complexity overhead of consistency
1181 // outweighed the benefits in this case (custom asmparser, printer and selection
1182 // vs custom encoder).
1183 def bitfield32_lsl_imm : Operand<i64>,
1184 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1185 let ParserMatchClass = uimm5_asmoperand;
1186 let EncoderMethod = "getBitfield32LSLOpValue";
1189 def bitfield64_lsl_imm : Operand<i64>,
1190 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1191 let ParserMatchClass = uimm6_asmoperand;
1192 let EncoderMethod = "getBitfield64LSLOpValue";
1195 class A64I_bitfield_lsl<bit sf, RegisterClass GPR, ValueType ty,
1197 : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),
1198 "lsl\t$Rd, $Rn, $FullImm",
1199 [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))],
1202 let ImmR = FullImm{5-0};
1203 let ImmS = FullImm{11-6};
1205 // No disassembler allowed because it would overlap with BFM which does the
1207 let isAsmParserOnly = 1;
1210 def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, i32, bitfield32_lsl_imm>;
1211 def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, i64, bitfield64_lsl_imm>;
1213 //===-------------------------------
1214 // 5. Aliases for bitfield extract instructions
1215 //===-------------------------------
1217 def bfx32_width_asmoperand : AsmOperandClass {
1218 let Name = "BFX32Width";
1219 let PredicateMethod = "isBitfieldWidth<32>";
1220 let RenderMethod = "addBFXWidthOperands";
1221 let DiagnosticType = "Width32";
1224 def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> {
1225 let PrintMethod = "printBFXWidthOperand";
1226 let ParserMatchClass = bfx32_width_asmoperand;
1229 def bfx64_width_asmoperand : AsmOperandClass {
1230 let Name = "BFX64Width";
1231 let PredicateMethod = "isBitfieldWidth<64>";
1232 let RenderMethod = "addBFXWidthOperands";
1233 let DiagnosticType = "Width64";
1236 def bfx64_width : Operand<i64> {
1237 let PrintMethod = "printBFXWidthOperand";
1238 let ParserMatchClass = bfx64_width_asmoperand;
1242 multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> {
1243 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1244 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1245 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1246 [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))],
1248 // As above, no disassembler allowed.
1249 let isAsmParserOnly = 1;
1252 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1253 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1254 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1255 [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))],
1257 // As above, no disassembler allowed.
1258 let isAsmParserOnly = 1;
1262 defm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>;
1263 defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>;
1265 // Again, variants based on BFM modify Rd so need it as an input too.
1266 def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1267 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1268 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1269 // As above, no disassembler allowed.
1270 let isAsmParserOnly = 1;
1271 let Constraints = "$src = $Rd";
1274 def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1275 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1276 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1277 // As above, no disassembler allowed.
1278 let isAsmParserOnly = 1;
1279 let Constraints = "$src = $Rd";
1282 // SBFX instructions can do a 1-instruction sign-extension of boolean values.
1283 def : Pat<(sext_inreg i64:$Rn, i1), (SBFXxxii $Rn, 0, 0)>;
1284 def : Pat<(sext_inreg i32:$Rn, i1), (SBFXwwii $Rn, 0, 0)>;
1285 def : Pat<(i64 (sext_inreg (anyext i32:$Rn), i1)),
1286 (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>;
1288 // UBFX makes sense as an implementation of a 64-bit zero-extension too. Could
1289 // use either 64-bit or 32-bit variant, but 32-bit might be more efficient.
1290 def : Pat<(i64 (zext i32:$Rn)), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31),
1293 //===-------------------------------
1294 // 6. Aliases for bitfield insert instructions
1295 //===-------------------------------
1297 def bfi32_lsb_asmoperand : AsmOperandClass {
1298 let Name = "BFI32LSB";
1299 let PredicateMethod = "isUImm<5>";
1300 let RenderMethod = "addBFILSBOperands<32>";
1301 let DiagnosticType = "UImm5";
1304 def bfi32_lsb : Operand<i64>,
1305 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1306 let PrintMethod = "printBFILSBOperand<32>";
1307 let ParserMatchClass = bfi32_lsb_asmoperand;
1310 def bfi64_lsb_asmoperand : AsmOperandClass {
1311 let Name = "BFI64LSB";
1312 let PredicateMethod = "isUImm<6>";
1313 let RenderMethod = "addBFILSBOperands<64>";
1314 let DiagnosticType = "UImm6";
1317 def bfi64_lsb : Operand<i64>,
1318 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1319 let PrintMethod = "printBFILSBOperand<64>";
1320 let ParserMatchClass = bfi64_lsb_asmoperand;
1323 // Width verification is performed during conversion so width operand can be
1324 // shared between 32/64-bit cases. Still needed for the print method though
1325 // because ImmR encodes "width - 1".
1326 def bfi32_width_asmoperand : AsmOperandClass {
1327 let Name = "BFI32Width";
1328 let PredicateMethod = "isBitfieldWidth<32>";
1329 let RenderMethod = "addBFIWidthOperands";
1330 let DiagnosticType = "Width32";
1333 def bfi32_width : Operand<i64>,
1334 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> {
1335 let PrintMethod = "printBFIWidthOperand";
1336 let ParserMatchClass = bfi32_width_asmoperand;
1339 def bfi64_width_asmoperand : AsmOperandClass {
1340 let Name = "BFI64Width";
1341 let PredicateMethod = "isBitfieldWidth<64>";
1342 let RenderMethod = "addBFIWidthOperands";
1343 let DiagnosticType = "Width64";
1346 def bfi64_width : Operand<i64>,
1347 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> {
1348 let PrintMethod = "printBFIWidthOperand";
1349 let ParserMatchClass = bfi64_width_asmoperand;
1352 multiclass A64I_bitfield_insert<bits<2> opc, string asmop> {
1353 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1354 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1355 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1357 // As above, no disassembler allowed.
1358 let isAsmParserOnly = 1;
1361 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1362 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1363 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1365 // As above, no disassembler allowed.
1366 let isAsmParserOnly = 1;
1370 defm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">;
1371 defm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">;
1374 def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1375 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1376 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1377 // As above, no disassembler allowed.
1378 let isAsmParserOnly = 1;
1379 let Constraints = "$src = $Rd";
1382 def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1383 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1384 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1385 // As above, no disassembler allowed.
1386 let isAsmParserOnly = 1;
1387 let Constraints = "$src = $Rd";
1390 //===----------------------------------------------------------------------===//
1391 // Compare and branch (immediate)
1392 //===----------------------------------------------------------------------===//
1393 // Contains: CBZ, CBNZ
1395 class label_asmoperand<int width, int scale> : AsmOperandClass {
1396 let Name = "Label" # width # "_" # scale;
1397 let PredicateMethod = "isLabel<" # width # "," # scale # ">";
1398 let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">";
1399 let DiagnosticType = "Label";
1402 def label_wid19_scal4_asmoperand : label_asmoperand<19, 4>;
1404 // All conditional immediate branches are the same really: 19 signed bits scaled
1405 // by the instruction-size (4).
1406 def bcc_target : Operand<OtherVT> {
1407 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
1408 let ParserMatchClass = label_wid19_scal4_asmoperand;
1409 let PrintMethod = "printLabelOperand<19, 4>";
1410 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>";
1411 let OperandType = "OPERAND_PCREL";
1414 multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> {
1415 let isBranch = 1, isTerminator = 1 in {
1416 def x : A64I_cmpbr<0b1, op,
1418 (ins GPR64:$Rt, bcc_target:$Label),
1419 !strconcat(asmop,"\t$Rt, $Label"),
1420 [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],
1423 def w : A64I_cmpbr<0b0, op,
1425 (ins GPR32:$Rt, bcc_target:$Label),
1426 !strconcat(asmop,"\t$Rt, $Label"),
1427 [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],
1432 defm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{
1433 return Imm == A64CC::EQ;
1435 defm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{
1436 return Imm == A64CC::NE;
1439 //===----------------------------------------------------------------------===//
1440 // Conditional branch (immediate) instructions
1441 //===----------------------------------------------------------------------===//
1444 def cond_code_asmoperand : AsmOperandClass {
1445 let Name = "CondCode";
1446 let DiagnosticType = "CondCode";
1449 def cond_code : Operand<i32>, ImmLeaf<i32, [{
1450 return Imm >= 0 && Imm <= 15;
1452 let PrintMethod = "printCondCodeOperand";
1453 let ParserMatchClass = cond_code_asmoperand;
1456 def Bcc : A64I_condbr<0b0, 0b0, (outs),
1457 (ins cond_code:$Cond, bcc_target:$Label),
1458 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
1462 let isTerminator = 1;
1465 //===----------------------------------------------------------------------===//
1466 // Conditional compare (immediate) instructions
1467 //===----------------------------------------------------------------------===//
1468 // Contains: CCMN, CCMP
1470 def uimm4_asmoperand : AsmOperandClass {
1472 let PredicateMethod = "isUImm<4>";
1473 let RenderMethod = "addImmOperands";
1474 let DiagnosticType = "UImm4";
1477 def uimm4 : Operand<i32> {
1478 let ParserMatchClass = uimm4_asmoperand;
1481 def uimm5 : Operand<i32> {
1482 let ParserMatchClass = uimm5_asmoperand;
1485 // The only difference between this operand and the one for instructions like
1486 // B.cc is that it's parsed manually. The other get parsed implicitly as part of
1487 // the mnemonic handling.
1488 def cond_code_op_asmoperand : AsmOperandClass {
1489 let Name = "CondCodeOp";
1490 let RenderMethod = "addCondCodeOperands";
1491 let PredicateMethod = "isCondCode";
1492 let ParserMethod = "ParseCondCodeOperand";
1493 let DiagnosticType = "CondCode";
1496 def cond_code_op : Operand<i32> {
1497 let PrintMethod = "printCondCodeOperand";
1498 let ParserMatchClass = cond_code_op_asmoperand;
1501 class A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1502 : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),
1503 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
1504 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
1509 def CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">;
1510 def CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">;
1511 def CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">;
1512 def CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">;
1514 //===----------------------------------------------------------------------===//
1515 // Conditional compare (register) instructions
1516 //===----------------------------------------------------------------------===//
1517 // Contains: CCMN, CCMP
1519 class A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1520 : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1,
1522 (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
1523 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
1528 def CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">;
1529 def CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">;
1530 def CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">;
1531 def CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">;
1533 //===----------------------------------------------------------------------===//
1534 // Conditional select instructions
1535 //===----------------------------------------------------------------------===//
1536 // Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG
1538 // Condition code which is encoded as the inversion (semantically rather than
1539 // bitwise) in the instruction.
1540 def inv_cond_code_op_asmoperand : AsmOperandClass {
1541 let Name = "InvCondCodeOp";
1542 let RenderMethod = "addInvCondCodeOperands";
1543 let PredicateMethod = "isCondCode";
1544 let ParserMethod = "ParseCondCodeOperand";
1545 let DiagnosticType = "CondCode";
1548 def inv_cond_code_op : Operand<i32> {
1549 let ParserMatchClass = inv_cond_code_op_asmoperand;
1552 // Having a separate operand for the selectable use-case is debatable, but gives
1553 // consistency with cond_code.
1554 def inv_cond_XFORM : SDNodeXForm<imm, [{
1555 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue());
1556 return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32);
1560 : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>;
1563 multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
1564 SDPatternOperator select> {
1565 let Uses = [NZCV] in {
1566 def wwwc : A64I_condsel<0b0, op, 0b0, op2,
1568 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
1569 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1570 [(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
1574 def xxxc : A64I_condsel<0b1, op, 0b0, op2,
1576 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
1577 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1578 [(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
1584 : PatFrag<(ops node:$lhs, node:$rhs),
1585 (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>;
1587 class complex_select<SDPatternOperator opnode>
1588 : PatFrag<(ops node:$lhs, node:$rhs),
1589 (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>;
1592 defm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>;
1593 defm CSINC : A64I_condselSizes<0b0, 0b01, "csinc",
1594 complex_select<PatFrag<(ops node:$val),
1595 (add node:$val, 1)>>>;
1596 defm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>;
1597 defm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>;
1599 // Now the instruction aliases, which fit nicely into LLVM's model:
1601 def : InstAlias<"cset $Rd, $Cond",
1602 (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1603 def : InstAlias<"cset $Rd, $Cond",
1604 (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1605 def : InstAlias<"csetm $Rd, $Cond",
1606 (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1607 def : InstAlias<"csetm $Rd, $Cond",
1608 (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1609 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1610 (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1611 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1612 (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1613 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1614 (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1615 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1616 (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1617 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1618 (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1619 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1620 (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1622 // Finally some helper patterns.
1624 // For CSET (a.k.a. zero-extension of icmp)
1625 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1626 (CSINCwwwc WZR, WZR, cond_code:$Cond)>;
1627 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1628 (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>;
1630 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1631 (CSINCxxxc XZR, XZR, cond_code:$Cond)>;
1632 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1633 (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>;
1635 // For CSETM (a.k.a. sign-extension of icmp)
1636 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1637 (CSINVwwwc WZR, WZR, cond_code:$Cond)>;
1638 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1639 (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>;
1641 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1642 (CSINVxxxc XZR, XZR, cond_code:$Cond)>;
1643 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1644 (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>;
1646 // CINC, CINV and CNEG get dealt with automatically, which leaves the issue of
1647 // commutativity. The instructions are to complex for isCommutable to be used,
1648 // so we have to create the patterns manually:
1650 // No commutable pattern for CSEL since the commuted version is isomorphic.
1653 def :Pat<(A64select_cc NZCV, (add i32:$Rm, 1), i32:$Rn, inv_cond_code:$Cond),
1654 (CSINCwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1655 def :Pat<(A64select_cc NZCV, (add i64:$Rm, 1), i64:$Rn, inv_cond_code:$Cond),
1656 (CSINCxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1659 def :Pat<(A64select_cc NZCV, (not i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1660 (CSINVwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1661 def :Pat<(A64select_cc NZCV, (not i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1662 (CSINVxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1665 def :Pat<(A64select_cc NZCV, (ineg i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1666 (CSNEGwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1667 def :Pat<(A64select_cc NZCV, (ineg i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1668 (CSNEGxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1670 //===----------------------------------------------------------------------===//
1671 // Data Processing (1 source) instructions
1672 //===----------------------------------------------------------------------===//
1673 // Contains: RBIT, REV16, REV, REV32, CLZ, CLS.
1675 // We define an unary operator which always fails. We will use this to
1676 // define unary operators that cannot be matched.
1678 class A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop,
1679 list<dag> patterns, RegisterClass GPRrc,
1680 InstrItinClass itin>:
1685 !strconcat(asmop, "\t$Rd, $Rn"),
1691 multiclass A64I_dp_1src <bits<6> opcode, string asmop> {
1692 let hasSideEffects = 0 in {
1693 def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>;
1694 def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>;
1698 defm RBIT : A64I_dp_1src<0b000000, "rbit">;
1699 defm CLS : A64I_dp_1src<0b000101, "cls">;
1700 defm CLZ : A64I_dp_1src<0b000100, "clz">;
1702 def : Pat<(ctlz i32:$Rn), (CLZww $Rn)>;
1703 def : Pat<(ctlz i64:$Rn), (CLZxx $Rn)>;
1704 def : Pat<(ctlz_zero_undef i32:$Rn), (CLZww $Rn)>;
1705 def : Pat<(ctlz_zero_undef i64:$Rn), (CLZxx $Rn)>;
1707 def : Pat<(cttz i32:$Rn), (CLZww (RBITww $Rn))>;
1708 def : Pat<(cttz i64:$Rn), (CLZxx (RBITxx $Rn))>;
1709 def : Pat<(cttz_zero_undef i32:$Rn), (CLZww (RBITww $Rn))>;
1710 def : Pat<(cttz_zero_undef i64:$Rn), (CLZxx (RBITxx $Rn))>;
1713 def REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev",
1714 [(set i32:$Rd, (bswap i32:$Rn))],
1715 GPR32, NoItinerary>;
1716 def REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev",
1717 [(set i64:$Rd, (bswap i64:$Rn))],
1718 GPR64, NoItinerary>;
1719 def REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32",
1720 [(set i64:$Rd, (bswap (rotr i64:$Rn, (i64 32))))],
1721 GPR64, NoItinerary>;
1722 def REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16",
1723 [(set i32:$Rd, (bswap (rotr i32:$Rn, (i64 16))))],
1726 def REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>;
1728 //===----------------------------------------------------------------------===//
1729 // Data Processing (2 sources) instructions
1730 //===----------------------------------------------------------------------===//
1731 // Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL,
1735 class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns,
1736 RegisterClass GPRsp,
1737 InstrItinClass itin>:
1741 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
1743 (ins GPRsp:$Rn, GPRsp:$Rm),
1747 multiclass dp_2src_crc<bit c, string asmop> {
1748 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
1749 !strconcat(asmop, "b"), [], GPR32, NoItinerary>;
1750 def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1},
1751 !strconcat(asmop, "h"), [], GPR32, NoItinerary>;
1752 def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0},
1753 !strconcat(asmop, "w"), [], GPR32, NoItinerary>;
1754 def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
1755 !strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
1756 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
1760 multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
1761 def www : dp_2src_impl<0b0,
1765 (op i32:$Rn, (i64 (zext i32:$Rm))))],
1768 def xxx : dp_2src_impl<0b1,
1771 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1777 multiclass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> {
1778 def www : dp_2src_impl<0b0,
1781 [(set i32:$Rd, (op i32:$Rn, i32:$Rm))],
1784 def xxx : dp_2src_impl<0b1,
1787 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1792 // Here we define the data processing 2 source instructions.
1793 defm CRC32 : dp_2src_crc<0b0, "crc32">;
1794 defm CRC32C : dp_2src_crc<0b1, "crc32c">;
1796 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1797 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1799 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1800 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1801 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1802 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1804 // Extra patterns for an incoming 64-bit value for a 32-bit
1805 // operation. Since the LLVM operations are undefined (as in C) if the
1806 // RHS is out of range, it's perfectly permissible to discard the high
1807 // bits of the GPR64.
1808 def : Pat<(shl i32:$Rn, i64:$Rm),
1809 (LSLVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1810 def : Pat<(srl i32:$Rn, i64:$Rm),
1811 (LSRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1812 def : Pat<(sra i32:$Rn, i64:$Rm),
1813 (ASRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1814 def : Pat<(rotr i32:$Rn, i64:$Rm),
1815 (RORVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1817 // Here we define the aliases for the data processing 2 source instructions.
1818 def LSL_mnemonic : MnemonicAlias<"lslv", "lsl">;
1819 def LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">;
1820 def ASR_menmonic : MnemonicAlias<"asrv", "asr">;
1821 def ROR_menmonic : MnemonicAlias<"rorv", "ror">;
1823 //===----------------------------------------------------------------------===//
1824 // Data Processing (3 sources) instructions
1825 //===----------------------------------------------------------------------===//
1826 // Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH
1827 // + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL
1829 class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg,
1830 ValueType AccTy, RegisterClass SrcReg,
1831 string asmop, dag pattern>
1832 : A64I_dp3<sf, opcode,
1833 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
1834 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
1835 [(set AccTy:$Rd, pattern)], NoItinerary> {
1836 RegisterClass AccGPR = AccReg;
1837 RegisterClass SrcGPR = SrcReg;
1840 def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, i32, GPR32, "madd",
1841 (add i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1842 def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, i64, GPR64, "madd",
1843 (add i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1845 def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, i32, GPR32, "msub",
1846 (sub i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1847 def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, i64, GPR64, "msub",
1848 (sub i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1850 def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, i64, GPR32, "smaddl",
1851 (add i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1852 def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, i64, GPR32, "smsubl",
1853 (sub i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1855 def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, i64, GPR32, "umaddl",
1856 (add i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1857 def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, i64, GPR32, "umsubl",
1858 (sub i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1860 let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in {
1861 def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd),
1862 (ins GPR64:$Rn, GPR64:$Rm),
1863 "umulh\t$Rd, $Rn, $Rm",
1864 [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))],
1867 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
1868 (ins GPR64:$Rn, GPR64:$Rm),
1869 "smulh\t$Rd, $Rn, $Rm",
1870 [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))],
1874 multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,
1875 Register ZR, dag pattern> {
1876 def : InstAlias<asmop # " $Rd, $Rn, $Rm",
1877 (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
1879 def : Pat<pattern, (INST $Rn, $Rm, ZR)>;
1882 defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul i32:$Rn, i32:$Rm)>;
1883 defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul i64:$Rn, i64:$Rm)>;
1885 defm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR,
1886 (sub 0, (mul i32:$Rn, i32:$Rm))>;
1887 defm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR,
1888 (sub 0, (mul i64:$Rn, i64:$Rm))>;
1890 defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR,
1891 (mul (i64 (sext i32:$Rn)), (sext i32:$Rm))>;
1892 defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR,
1893 (sub 0, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1895 defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR,
1896 (mul (i64 (zext i32:$Rn)), (zext i32:$Rm))>;
1897 defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR,
1898 (sub 0, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1901 //===----------------------------------------------------------------------===//
1902 // Exception generation
1903 //===----------------------------------------------------------------------===//
1904 // Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3
1906 def uimm16_asmoperand : AsmOperandClass {
1907 let Name = "UImm16";
1908 let PredicateMethod = "isUImm<16>";
1909 let RenderMethod = "addImmOperands";
1910 let DiagnosticType = "UImm16";
1913 def uimm16 : Operand<i32> {
1914 let ParserMatchClass = uimm16_asmoperand;
1917 class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop>
1918 : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),
1919 !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {
1921 let isTerminator = 1;
1924 def SVCi : A64I_exceptImpl<0b000, 0b01, "svc">;
1925 def HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">;
1926 def SMCi : A64I_exceptImpl<0b000, 0b11, "smc">;
1927 def BRKi : A64I_exceptImpl<0b001, 0b00, "brk">;
1928 def HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">;
1930 def DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">;
1931 def DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">;
1932 def DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">;
1934 // The immediate is optional for the DCPS instructions, defaulting to 0.
1935 def : InstAlias<"dcps1", (DCPS1i 0)>;
1936 def : InstAlias<"dcps2", (DCPS2i 0)>;
1937 def : InstAlias<"dcps3", (DCPS3i 0)>;
1939 //===----------------------------------------------------------------------===//
1940 // Extract (immediate)
1941 //===----------------------------------------------------------------------===//
1942 // Contains: EXTR + alias ROR
1944 def EXTRwwwi : A64I_extract<0b0, 0b000, 0b0,
1946 (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB),
1947 "extr\t$Rd, $Rn, $Rm, $LSB",
1949 (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))],
1951 def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
1953 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
1954 "extr\t$Rd, $Rn, $Rm, $LSB",
1956 (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))],
1959 def : InstAlias<"ror $Rd, $Rs, $LSB",
1960 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;
1961 def : InstAlias<"ror $Rd, $Rs, $LSB",
1962 (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>;
1964 def : Pat<(rotr i32:$Rn, bitfield32_imm:$LSB),
1965 (EXTRwwwi $Rn, $Rn, bitfield32_imm:$LSB)>;
1966 def : Pat<(rotr i64:$Rn, bitfield64_imm:$LSB),
1967 (EXTRxxxi $Rn, $Rn, bitfield64_imm:$LSB)>;
1969 //===----------------------------------------------------------------------===//
1970 // Floating-point compare instructions
1971 //===----------------------------------------------------------------------===//
1972 // Contains: FCMP, FCMPE
1974 def fpzero_asmoperand : AsmOperandClass {
1975 let Name = "FPZero";
1976 let ParserMethod = "ParseFPImmOperand";
1977 let DiagnosticType = "FPZero";
1980 def fpz32 : Operand<f32>,
1981 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
1982 let ParserMatchClass = fpzero_asmoperand;
1983 let PrintMethod = "printFPZeroOperand";
1984 let DecoderMethod = "DecodeFPZeroOperand";
1987 def fpz64 : Operand<f64>,
1988 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
1989 let ParserMatchClass = fpzero_asmoperand;
1990 let PrintMethod = "printFPZeroOperand";
1991 let DecoderMethod = "DecodeFPZeroOperand";
1994 def fpz64movi : Operand<i64>,
1995 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
1996 let ParserMatchClass = fpzero_asmoperand;
1997 let PrintMethod = "printFPZeroOperand";
1998 let DecoderMethod = "DecodeFPZeroOperand";
2001 multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {
2002 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
2003 (outs), ins, "fcmp\t$Rn, $Rm", [pattern],
2008 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
2009 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> {
2014 defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm),
2015 (set NZCV, (A64cmp f32:$Rn, f32:$Rm))>;
2016 defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm),
2017 (set NZCV, (A64cmp f64:$Rn, f64:$Rm))>;
2019 // What would be Rm should be written as 0; note that even though it's called
2020 // "$Rm" here to fit in with the InstrFormats, it's actually an immediate.
2021 defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm),
2022 (set NZCV, (A64cmp f32:$Rn, fpz32:$Rm))>;
2024 defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm),
2025 (set NZCV, (A64cmp f64:$Rn, fpz64:$Rm))>;
2028 //===----------------------------------------------------------------------===//
2029 // Floating-point conditional compare instructions
2030 //===----------------------------------------------------------------------===//
2031 // Contains: FCCMP, FCCMPE
2033 class A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop>
2034 : A64I_fpccmp<0b0, 0b0, type, op,
2036 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
2037 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
2042 def FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">;
2043 def FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">;
2044 def FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">;
2045 def FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">;
2047 //===----------------------------------------------------------------------===//
2048 // Floating-point conditional select instructions
2049 //===----------------------------------------------------------------------===//
2052 let Uses = [NZCV] in {
2053 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
2054 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
2055 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2057 (simple_select f32:$Rn, f32:$Rm))],
2061 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
2062 (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond),
2063 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2065 (simple_select f64:$Rn, f64:$Rm))],
2069 //===----------------------------------------------------------------------===//
2070 // Floating-point data-processing (1 source)
2071 //===----------------------------------------------------------------------===//
2072 // Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI].
2074 def FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val),
2075 [{ (void)N; return false; }]>;
2077 // First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d"
2078 // syntax. Default to no pattern because most are odd enough not to have one.
2079 multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr,
2080 SDPatternOperator opnode = FPNoUnop> {
2081 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
2082 !strconcat(asmstr, "\t$Rd, $Rn"),
2083 [(set f32:$Rd, (opnode f32:$Rn))],
2086 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
2087 !strconcat(asmstr, "\t$Rd, $Rn"),
2088 [(set f64:$Rd, (opnode f64:$Rn))],
2092 defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;
2093 defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;
2094 defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;
2095 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
2097 defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;
2098 defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;
2099 defm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>;
2100 defm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>;
2101 defm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">;
2102 defm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>;
2103 defm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>;
2105 // The FCVT instrucitons have different source and destination register-types,
2106 // but the fields are uniform everywhere a D-register (say) crops up. Package
2107 // this information in a Record.
2108 class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> {
2109 RegisterClass Class = rc;
2115 def FCVT16 : FCVTRegType<FPR16, 0b11, f16>;
2116 def FCVT32 : FCVTRegType<FPR32, 0b00, f32>;
2117 def FCVT64 : FCVTRegType<FPR64, 0b01, f64>;
2119 class A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode>
2120 : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0},
2121 {0,0,0,1, DestReg.t1, DestReg.t0},
2122 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
2124 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>;
2126 def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>;
2127 def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>;
2128 def FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>;
2129 def FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>;
2130 def FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>;
2131 def FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>;
2134 //===----------------------------------------------------------------------===//
2135 // Floating-point data-processing (2 sources) instructions
2136 //===----------------------------------------------------------------------===//
2137 // Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
2139 def FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs),
2140 [{ (void)N; return false; }]>;
2142 multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr,
2143 SDPatternOperator opnode> {
2144 def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode,
2146 (ins FPR32:$Rn, FPR32:$Rm),
2147 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2148 [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))],
2151 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
2153 (ins FPR64:$Rn, FPR64:$Rm),
2154 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2155 [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))],
2159 let isCommutable = 1 in {
2160 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
2161 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;
2163 // No patterns for these.
2164 defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>;
2165 defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>;
2166 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;
2167 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;
2169 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2170 PatFrag<(ops node:$lhs, node:$rhs),
2171 (fneg (fmul node:$lhs, node:$rhs))> >;
2174 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
2175 defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;
2177 //===----------------------------------------------------------------------===//
2178 // Floating-point data-processing (3 sources) instructions
2179 //===----------------------------------------------------------------------===//
2180 // Contains: FMADD, FMSUB, FNMADD, FNMSUB
2182 def fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2183 (fma (fneg node:$Rn), node:$Rm, node:$Ra)>;
2184 def fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2185 (fma node:$Rn, node:$Rm, (fneg node:$Ra))>;
2186 def fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2187 (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>;
2189 class A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT,
2190 bits<2> type, bit o1, bit o0, SDPatternOperator fmakind>
2191 : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd),
2192 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
2193 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
2194 [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))],
2197 def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
2198 def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;
2199 def FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>;
2200 def FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>;
2202 def FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>;
2203 def FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>;
2204 def FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>;
2205 def FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>;
2207 // Extra patterns for when we're allowed to optimise separate multiplication and
2209 let Predicates = [HasFPARMv8, UseFusedMAC] in {
2210 def : Pat<(f32 (fadd FPR32:$Ra, (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)))),
2211 (FMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2212 def : Pat<(f32 (fsub FPR32:$Ra, (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)))),
2213 (FMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2214 def : Pat<(f32 (fsub (f32 (fneg FPR32:$Ra)), (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)))),
2215 (FNMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2216 def : Pat<(f32 (fsub (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)), FPR32:$Ra)),
2217 (FNMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2219 def : Pat<(f64 (fadd FPR64:$Ra, (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)))),
2220 (FMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2221 def : Pat<(f64 (fsub FPR64:$Ra, (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)))),
2222 (FMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2223 def : Pat<(f64 (fsub (f64 (fneg FPR64:$Ra)), (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)))),
2224 (FNMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2225 def : Pat<(f64 (fsub (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)), FPR64:$Ra)),
2226 (FNMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2230 //===----------------------------------------------------------------------===//
2231 // Floating-point <-> fixed-point conversion instructions
2232 //===----------------------------------------------------------------------===//
2233 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2235 // #1-#32 allowed, encoded as "64 - <specified imm>
2236 def fixedpos_asmoperand_i32 : AsmOperandClass {
2237 let Name = "CVTFixedPos32";
2238 let RenderMethod = "addCVTFixedPosOperands";
2239 let PredicateMethod = "isCVTFixedPos<32>";
2240 let DiagnosticType = "CVTFixedPos32";
2243 // Also encoded as "64 - <specified imm>" but #1-#64 allowed.
2244 def fixedpos_asmoperand_i64 : AsmOperandClass {
2245 let Name = "CVTFixedPos64";
2246 let RenderMethod = "addCVTFixedPosOperands";
2247 let PredicateMethod = "isCVTFixedPos<64>";
2248 let DiagnosticType = "CVTFixedPos64";
2251 // We need the cartesian product of f32/f64 i32/i64 operands for
2253 // + Selection needs to use operands of correct floating type
2254 // + Assembly parsing and decoding depend on integer width
2255 class cvtfix_i32_op<ValueType FloatVT>
2257 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> {
2258 let ParserMatchClass = fixedpos_asmoperand_i32;
2259 let DecoderMethod = "DecodeCVT32FixedPosOperand";
2260 let PrintMethod = "printCVTFixedPosOperand";
2263 class cvtfix_i64_op<ValueType FloatVT>
2265 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> {
2266 let ParserMatchClass = fixedpos_asmoperand_i64;
2267 let PrintMethod = "printCVTFixedPosOperand";
2270 // Because of the proliferation of weird operands, it's not really
2271 // worth going for a multiclass here. Oh well.
2273 class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode,
2274 RegisterClass GPR, RegisterClass FPR,
2275 ValueType DstTy, ValueType SrcTy,
2276 Operand scale_op, string asmop, SDNode cvtop>
2277 : A64I_fpfixed<sf, 0b0, type, 0b11, opcode,
2278 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
2279 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2280 [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))],
2283 def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32,
2284 cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>;
2285 def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32, i64, f32,
2286 cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>;
2287 def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32, i32, f32,
2288 cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>;
2289 def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32, i64, f32,
2290 cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>;
2292 def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64, i32, f64,
2293 cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>;
2294 def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64, i64, f64,
2295 cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>;
2296 def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64, i32, f64,
2297 cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>;
2298 def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64, i64, f64,
2299 cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>;
2302 class A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode,
2303 RegisterClass FPR, RegisterClass GPR,
2304 ValueType DstTy, ValueType SrcTy,
2305 Operand scale_op, string asmop, SDNode cvtop>
2306 : A64I_fpfixed<sf, 0b0, type, 0b00, opcode,
2307 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
2308 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2309 [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))],
2312 def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32,
2313 cvtfix_i32_op<f32>, "scvtf", sint_to_fp>;
2314 def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64, f32, i64,
2315 cvtfix_i64_op<f32>, "scvtf", sint_to_fp>;
2316 def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32, f32, i32,
2317 cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>;
2318 def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64, f32, i64,
2319 cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>;
2320 def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32, f64, i32,
2321 cvtfix_i32_op<f64>, "scvtf", sint_to_fp>;
2322 def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64, f64, i64,
2323 cvtfix_i64_op<f64>, "scvtf", sint_to_fp>;
2324 def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32, f64, i32,
2325 cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>;
2326 def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64, f64, i64,
2327 cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>;
2329 //===----------------------------------------------------------------------===//
2330 // Floating-point <-> integer conversion instructions
2331 //===----------------------------------------------------------------------===//
2332 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2334 class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode,
2335 RegisterClass DestPR, RegisterClass SrcPR, string asmop>
2336 : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),
2337 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;
2339 multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {
2340 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
2341 GPR32, FPR32, asmop # "s">;
2342 def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0},
2343 GPR64, FPR32, asmop # "s">;
2344 def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1},
2345 GPR32, FPR32, asmop # "u">;
2346 def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1},
2347 GPR64, FPR32, asmop # "u">;
2349 def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0},
2350 GPR32, FPR64, asmop # "s">;
2351 def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0},
2352 GPR64, FPR64, asmop # "s">;
2353 def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1},
2354 GPR32, FPR64, asmop # "u">;
2355 def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1},
2356 GPR64, FPR64, asmop # "u">;
2359 defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">;
2360 defm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">;
2361 defm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">;
2362 defm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">;
2363 defm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">;
2365 let Predicates = [HasFPARMv8] in {
2366 def : Pat<(i32 (fp_to_sint f32:$Rn)), (FCVTZSws $Rn)>;
2367 def : Pat<(i64 (fp_to_sint f32:$Rn)), (FCVTZSxs $Rn)>;
2368 def : Pat<(i32 (fp_to_uint f32:$Rn)), (FCVTZUws $Rn)>;
2369 def : Pat<(i64 (fp_to_uint f32:$Rn)), (FCVTZUxs $Rn)>;
2370 def : Pat<(i32 (fp_to_sint f64:$Rn)), (FCVTZSwd $Rn)>;
2371 def : Pat<(i64 (fp_to_sint f64:$Rn)), (FCVTZSxd $Rn)>;
2372 def : Pat<(i32 (fp_to_uint f64:$Rn)), (FCVTZUwd $Rn)>;
2373 def : Pat<(i64 (fp_to_uint f64:$Rn)), (FCVTZUxd $Rn)>;
2376 multiclass A64I_inttofp<bit o0, string asmop> {
2377 def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>;
2378 def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>;
2379 def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>;
2380 def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>;
2383 defm S : A64I_inttofp<0b0, "scvtf">;
2384 defm U : A64I_inttofp<0b1, "ucvtf">;
2386 let Predicates = [HasFPARMv8] in {
2387 def : Pat<(f32 (sint_to_fp i32:$Rn)), (SCVTFsw $Rn)>;
2388 def : Pat<(f32 (sint_to_fp i64:$Rn)), (SCVTFsx $Rn)>;
2389 def : Pat<(f64 (sint_to_fp i32:$Rn)), (SCVTFdw $Rn)>;
2390 def : Pat<(f64 (sint_to_fp i64:$Rn)), (SCVTFdx $Rn)>;
2391 def : Pat<(f32 (uint_to_fp i32:$Rn)), (UCVTFsw $Rn)>;
2392 def : Pat<(f32 (uint_to_fp i64:$Rn)), (UCVTFsx $Rn)>;
2393 def : Pat<(f64 (uint_to_fp i32:$Rn)), (UCVTFdw $Rn)>;
2394 def : Pat<(f64 (uint_to_fp i64:$Rn)), (UCVTFdx $Rn)>;
2397 def FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">;
2398 def FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">;
2399 def FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">;
2400 def FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">;
2402 let Predicates = [HasFPARMv8] in {
2403 def : Pat<(i32 (bitconvert f32:$Rn)), (FMOVws $Rn)>;
2404 def : Pat<(f32 (bitconvert i32:$Rn)), (FMOVsw $Rn)>;
2405 def : Pat<(i64 (bitconvert f64:$Rn)), (FMOVxd $Rn)>;
2406 def : Pat<(f64 (bitconvert i64:$Rn)), (FMOVdx $Rn)>;
2409 def lane1_asmoperand : AsmOperandClass {
2411 let RenderMethod = "addImmOperands";
2412 let DiagnosticType = "Lane1";
2415 def lane1 : Operand<i32> {
2416 let ParserMatchClass = lane1_asmoperand;
2417 let PrintMethod = "printBareImmOperand";
2420 let DecoderMethod = "DecodeFMOVLaneInstruction" in {
2421 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
2422 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
2423 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;
2425 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,
2426 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),
2427 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>;
2430 let Predicates = [HasFPARMv8] in {
2431 def : InstAlias<"fmov $Rd, $Rn.2d[$Lane]",
2432 (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>;
2434 def : InstAlias<"fmov $Rd.2d[$Lane], $Rn",
2435 (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>;
2438 //===----------------------------------------------------------------------===//
2439 // Floating-point immediate instructions
2440 //===----------------------------------------------------------------------===//
2443 def fpimm_asmoperand : AsmOperandClass {
2444 let Name = "FMOVImm";
2445 let ParserMethod = "ParseFPImmOperand";
2446 let DiagnosticType = "FPImm";
2449 // The MCOperand for these instructions are the encoded 8-bit values.
2450 def SDXF_fpimm : SDNodeXForm<fpimm, [{
2452 A64Imms::isFPImm(N->getValueAPF(), Imm8);
2453 return CurDAG->getTargetConstant(Imm8, MVT::i32);
2456 class fmov_operand<ValueType FT>
2458 PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }],
2460 let PrintMethod = "printFPImmOperand";
2461 let ParserMatchClass = fpimm_asmoperand;
2464 def fmov32_operand : fmov_operand<f32>;
2465 def fmov64_operand : fmov_operand<f64>;
2467 class A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT,
2468 Operand fmov_operand>
2469 : A64I_fpimm<0b0, 0b0, type, 0b00000,
2471 (ins fmov_operand:$Imm8),
2473 [(set VT:$Rd, fmov_operand:$Imm8)],
2476 def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
2477 def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;
2479 //===----------------------------------------------------------------------===//
2480 // Load-register (literal) instructions
2481 //===----------------------------------------------------------------------===//
2482 // Contains: LDR, LDRSW, PRFM
2484 def ldrlit_label_asmoperand : AsmOperandClass {
2485 let Name = "LoadLitLabel";
2486 let RenderMethod = "addLabelOperands<19, 4>";
2487 let DiagnosticType = "Label";
2490 def ldrlit_label : Operand<i64> {
2491 let EncoderMethod = "getLoadLitLabelOpValue";
2493 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
2494 let PrintMethod = "printLabelOperand<19, 4>";
2495 let ParserMatchClass = ldrlit_label_asmoperand;
2496 let OperandType = "OPERAND_PCREL";
2499 // Various instructions take an immediate value (which can always be used),
2500 // where some numbers have a symbolic name to make things easier. These operands
2501 // and the associated functions abstract away the differences.
2502 multiclass namedimm<string prefix, string mapper> {
2503 def _asmoperand : AsmOperandClass {
2504 let Name = "NamedImm" # prefix;
2505 let PredicateMethod = "isUImm";
2506 let RenderMethod = "addImmOperands";
2507 let ParserMethod = "ParseNamedImmOperand<" # mapper # ">";
2508 let DiagnosticType = "NamedImm_" # prefix;
2511 def _op : Operand<i32> {
2512 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
2513 let PrintMethod = "printNamedImmOperand<" # mapper # ">";
2514 let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">";
2518 defm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">;
2520 class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg,
2521 list<dag> patterns = []>
2522 : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
2523 "ldr\t$Rt, $Imm19", patterns, NoItinerary>;
2525 let mayLoad = 1 in {
2526 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
2527 def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>;
2530 let Predicates = [HasFPARMv8] in {
2531 def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>;
2532 def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>;
2535 let mayLoad = 1 in {
2536 let Predicates = [HasFPARMv8] in {
2537 def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>;
2541 def LDRSWx_lit : A64I_LDRlit<0b10, 0b0,
2543 (ins ldrlit_label:$Imm19),
2544 "ldrsw\t$Rt, $Imm19",
2547 def PRFM_lit : A64I_LDRlit<0b11, 0b0,
2548 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
2549 "prfm\t$Rt, $Imm19",
2553 //===----------------------------------------------------------------------===//
2554 // Load-store exclusive instructions
2555 //===----------------------------------------------------------------------===//
2556 // Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB,
2557 // STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB,
2558 // STLRH, STLR, LDARB, LDARH, LDAR
2560 // Since these instructions have the undefined register bits set to 1 in
2561 // their canonical form, we need a post encoder method to set those bits
2562 // to 1 when encoding these instructions. We do this using the
2563 // fixLoadStoreExclusive function. This function has template parameters:
2565 // fixLoadStoreExclusive<int hasRs, int hasRt2>
2567 // hasRs indicates that the instruction uses the Rs field, so we won't set
2568 // it to 1 (and the same for Rt2). We don't need template parameters for
2569 // the other register fiels since Rt and Rn are always used.
2571 // This operand parses a GPR64xsp register, followed by an optional immediate
2573 def GPR64xsp0_asmoperand : AsmOperandClass {
2574 let Name = "GPR64xsp0";
2575 let PredicateMethod = "isWrappedReg";
2576 let RenderMethod = "addRegOperands";
2577 let ParserMethod = "ParseLSXAddressOperand";
2578 // Diagnostics are provided by ParserMethod
2581 def GPR64xsp0 : RegisterOperand<GPR64xsp> {
2582 let ParserMatchClass = GPR64xsp0_asmoperand;
2585 //===----------------------------------
2586 // Store-exclusive (releasing & normal)
2587 //===----------------------------------
2589 class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2590 dag ins, list<dag> pat,
2591 InstrItinClass itin> :
2592 A64I_LDSTex_stn <size,
2593 opcode{2}, 0, opcode{1}, opcode{0},
2595 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
2598 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
2601 multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
2602 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2603 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2606 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2607 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2610 def _word: A64I_SRexs_impl<0b10, opcode, asmstr,
2611 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2614 def _dword: A64I_SRexs_impl<0b11, opcode, asmstr,
2615 (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2619 defm STXR : A64I_SRex<"stxr", 0b000, "STXR">;
2620 defm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">;
2622 //===----------------------------------
2624 //===----------------------------------
2626 class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2627 dag ins, list<dag> pat,
2628 InstrItinClass itin> :
2629 A64I_LDSTex_tn <size,
2630 opcode{2}, 1, opcode{1}, opcode{0},
2632 !strconcat(asm, "\t$Rt, [$Rn]"),
2635 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2638 multiclass A64I_LRex<string asmstr, bits<3> opcode> {
2639 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2640 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2643 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2644 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2647 def _word: A64I_LRexs_impl<0b10, opcode, asmstr,
2648 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2651 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,
2652 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn),
2656 defm LDXR : A64I_LRex<"ldxr", 0b000>;
2657 defm LDAXR : A64I_LRex<"ldaxr", 0b001>;
2658 defm LDAR : A64I_LRex<"ldar", 0b101>;
2660 class acquiring_load<PatFrag base>
2661 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
2662 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2663 return Ordering == Acquire || Ordering == SequentiallyConsistent;
2666 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
2667 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
2668 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
2669 def atomic_load_acquire_64 : acquiring_load<atomic_load_64>;
2671 def : Pat<(atomic_load_acquire_8 i64:$Rn), (LDAR_byte $Rn)>;
2672 def : Pat<(atomic_load_acquire_16 i64:$Rn), (LDAR_hword $Rn)>;
2673 def : Pat<(atomic_load_acquire_32 i64:$Rn), (LDAR_word $Rn)>;
2674 def : Pat<(atomic_load_acquire_64 i64:$Rn), (LDAR_dword $Rn)>;
2676 //===----------------------------------
2677 // Store-release (no exclusivity)
2678 //===----------------------------------
2680 class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2681 dag ins, list<dag> pat,
2682 InstrItinClass itin> :
2683 A64I_LDSTex_tn <size,
2684 opcode{2}, 0, opcode{1}, opcode{0},
2686 !strconcat(asm, "\t$Rt, [$Rn]"),
2689 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2692 class releasing_store<PatFrag base>
2693 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
2694 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2695 return Ordering == Release || Ordering == SequentiallyConsistent;
2698 def atomic_store_release_8 : releasing_store<atomic_store_8>;
2699 def atomic_store_release_16 : releasing_store<atomic_store_16>;
2700 def atomic_store_release_32 : releasing_store<atomic_store_32>;
2701 def atomic_store_release_64 : releasing_store<atomic_store_64>;
2703 multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> {
2704 def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2705 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2706 [(atomic_store_release_8 i64:$Rn, i32:$Rt)],
2709 def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2710 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2711 [(atomic_store_release_16 i64:$Rn, i32:$Rt)],
2714 def _word: A64I_SLexs_impl<0b10, opcode, asmstr,
2715 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2716 [(atomic_store_release_32 i64:$Rn, i32:$Rt)],
2719 def _dword: A64I_SLexs_impl<0b11, opcode, asmstr,
2720 (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2721 [(atomic_store_release_64 i64:$Rn, i64:$Rt)],
2725 defm STLR : A64I_SLex<"stlr", 0b101, "STLR">;
2727 //===----------------------------------
2728 // Store-exclusive pair (releasing & normal)
2729 //===----------------------------------
2731 class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2732 dag ins, list<dag> pat,
2733 InstrItinClass itin> :
2734 A64I_LDSTex_stt2n <size,
2735 opcode{2}, 0, opcode{1}, opcode{0},
2737 !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"),
2743 multiclass A64I_SPex<string asmstr, bits<3> opcode> {
2744 def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs),
2745 (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2,
2749 def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs),
2750 (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2,
2755 defm STXP : A64I_SPex<"stxp", 0b010>;
2756 defm STLXP : A64I_SPex<"stlxp", 0b011>;
2758 //===----------------------------------
2759 // Load-exclusive pair (acquiring & normal)
2760 //===----------------------------------
2762 class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2763 dag ins, list<dag> pat,
2764 InstrItinClass itin> :
2765 A64I_LDSTex_tt2n <size,
2766 opcode{2}, 1, opcode{1}, opcode{0},
2768 !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"),
2771 let DecoderMethod = "DecodeLoadPairExclusiveInstruction";
2772 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
2775 multiclass A64I_LPex<string asmstr, bits<3> opcode> {
2776 def _word: A64I_LPexs_impl<0b10, opcode, asmstr,
2777 (outs GPR32:$Rt, GPR32:$Rt2),
2778 (ins GPR64xsp0:$Rn),
2781 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
2782 (outs GPR64:$Rt, GPR64:$Rt2),
2783 (ins GPR64xsp0:$Rn),
2787 defm LDXP : A64I_LPex<"ldxp", 0b010>;
2788 defm LDAXP : A64I_LPex<"ldaxp", 0b011>;
2790 //===----------------------------------------------------------------------===//
2791 // Load-store register (unscaled immediate) instructions
2792 //===----------------------------------------------------------------------===//
2793 // Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM
2797 //===----------------------------------------------------------------------===//
2798 // Load-store register (register offset) instructions
2799 //===----------------------------------------------------------------------===//
2800 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2804 //===----------------------------------------------------------------------===//
2805 // Load-store register (unsigned immediate) instructions
2806 //===----------------------------------------------------------------------===//
2807 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2811 //===----------------------------------------------------------------------===//
2812 // Load-store register (immediate post-indexed) instructions
2813 //===----------------------------------------------------------------------===//
2814 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2818 //===----------------------------------------------------------------------===//
2819 // Load-store register (immediate pre-indexed) instructions
2820 //===----------------------------------------------------------------------===//
2821 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2823 // Note that patterns are much later on in a completely separate section (they
2824 // need ADRPxi to be defined).
2826 //===-------------------------------
2827 // 1. Various operands needed
2828 //===-------------------------------
2830 //===-------------------------------
2831 // 1.1 Unsigned 12-bit immediate operands
2832 //===-------------------------------
2833 // The addressing mode for these instructions consists of an unsigned 12-bit
2834 // immediate which is scaled by the size of the memory access.
2836 // We represent this in the MC layer by two operands:
2837 // 1. A base register.
2838 // 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]"
2839 // would have '1' in this field.
2840 // This means that separate functions are needed for converting representations
2841 // which *are* aware of the intended access size.
2843 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
2844 // know the access size via some means. An isolated operand does not have this
2845 // information unless told from here, which means we need separate tablegen
2846 // Operands for each access size. This multiclass takes care of instantiating
2847 // the correct template functions in the rest of the backend.
2849 //===-------------------------------
2850 // 1.1 Unsigned 12-bit immediate operands
2851 //===-------------------------------
2853 multiclass offsets_uimm12<int MemSize, string prefix> {
2854 def uimm12_asmoperand : AsmOperandClass {
2855 let Name = "OffsetUImm12_" # MemSize;
2856 let PredicateMethod = "isOffsetUImm12<" # MemSize # ">";
2857 let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">";
2858 let DiagnosticType = "LoadStoreUImm12_" # MemSize;
2861 // Pattern is really no more than an ImmLeaf, but predicated on MemSize which
2862 // complicates things beyond TableGen's ken.
2863 def uimm12 : Operand<i64>,
2864 ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> {
2865 let ParserMatchClass
2866 = !cast<AsmOperandClass>(prefix # uimm12_asmoperand);
2868 let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">";
2869 let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">";
2873 defm byte_ : offsets_uimm12<1, "byte_">;
2874 defm hword_ : offsets_uimm12<2, "hword_">;
2875 defm word_ : offsets_uimm12<4, "word_">;
2876 defm dword_ : offsets_uimm12<8, "dword_">;
2877 defm qword_ : offsets_uimm12<16, "qword_">;
2879 //===-------------------------------
2880 // 1.1 Signed 9-bit immediate operands
2881 //===-------------------------------
2883 // The MCInst is expected to store the bit-wise encoding of the value,
2884 // which amounts to lopping off the extended sign bits.
2885 def SDXF_simm9 : SDNodeXForm<imm, [{
2886 return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32);
2889 def simm9_asmoperand : AsmOperandClass {
2891 let PredicateMethod = "isSImm<9>";
2892 let RenderMethod = "addSImmOperands<9>";
2893 let DiagnosticType = "LoadStoreSImm9";
2896 def simm9 : Operand<i64>,
2897 ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }],
2899 let PrintMethod = "printOffsetSImm9Operand";
2900 let ParserMatchClass = simm9_asmoperand;
2904 //===-------------------------------
2905 // 1.3 Register offset extensions
2906 //===-------------------------------
2908 // The assembly-syntax for these addressing-modes is:
2909 // [<Xn|SP>, <R><m> {, <extend> {<amount>}}]
2911 // The essential semantics are:
2912 // + <amount> is a shift: #<log(transfer size)> or #0
2913 // + <R> can be W or X.
2914 // + If <R> is W, <extend> can be UXTW or SXTW
2915 // + If <R> is X, <extend> can be LSL or SXTX
2917 // The trickiest of those constraints is that Rm can be either GPR32 or GPR64,
2918 // which will need separate instructions for LLVM type-consistency. We'll also
2919 // need separate operands, of course.
2920 multiclass regexts<int MemSize, int RmSize, RegisterClass GPR,
2921 string Rm, string prefix> {
2922 def regext_asmoperand : AsmOperandClass {
2923 let Name = "AddrRegExtend_" # MemSize # "_" # Rm;
2924 let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">";
2925 let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">";
2926 let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize;
2929 def regext : Operand<i64> {
2931 = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">";
2933 let DecoderMethod = "DecodeAddrRegExtendOperand";
2934 let ParserMatchClass
2935 = !cast<AsmOperandClass>(prefix # regext_asmoperand);
2939 multiclass regexts_wx<int MemSize, string prefix> {
2940 // Rm is an X-register if LSL or SXTX are specified as the shift.
2941 defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">;
2943 // Rm is a W-register if UXTW or SXTW are specified as the shift.
2944 defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">;
2947 defm byte_ : regexts_wx<1, "byte_">;
2948 defm hword_ : regexts_wx<2, "hword_">;
2949 defm word_ : regexts_wx<4, "word_">;
2950 defm dword_ : regexts_wx<8, "dword_">;
2951 defm qword_ : regexts_wx<16, "qword_">;
2954 //===------------------------------
2955 // 2. The instructions themselves.
2956 //===------------------------------
2958 // We have the following instructions to implement:
2959 // | | B | H | W | X |
2960 // |-----------------+-------+-------+-------+--------|
2961 // | unsigned str | STRB | STRH | STR | STR |
2962 // | unsigned ldr | LDRB | LDRH | LDR | LDR |
2963 // | signed ldr to W | LDRSB | LDRSH | - | - |
2964 // | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) |
2966 // This will instantiate the LDR/STR instructions you'd expect to use for an
2967 // unsigned datatype (first two rows above) or floating-point register, which is
2968 // reasonably uniform across all access sizes.
2971 //===------------------------------
2972 // 2.1 Regular instructions
2973 //===------------------------------
2975 // This class covers the basic unsigned or irrelevantly-signed loads and stores,
2976 // to general-purpose and floating-point registers.
2978 class AddrParams<string prefix> {
2979 Operand uimm12 = !cast<Operand>(prefix # "_uimm12");
2981 Operand regextWm = !cast<Operand>(prefix # "_Wm_regext");
2982 Operand regextXm = !cast<Operand>(prefix # "_Xm_regext");
2985 def byte_addrparams : AddrParams<"byte">;
2986 def hword_addrparams : AddrParams<"hword">;
2987 def word_addrparams : AddrParams<"word">;
2988 def dword_addrparams : AddrParams<"dword">;
2989 def qword_addrparams : AddrParams<"qword">;
2991 multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
2992 bit high_opc, string asmsuffix,
2993 RegisterClass GPR, AddrParams params> {
2994 // Unsigned immediate
2995 def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
2996 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
2997 "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
3001 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
3002 (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3004 def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},
3005 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3006 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
3010 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
3011 (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3013 // Register offset (four of these: load/store and Wm/Xm).
3014 let mayLoad = 1 in {
3015 def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0,
3017 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3018 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3021 def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1,
3023 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3024 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3027 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",
3028 (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
3031 let mayStore = 1 in {
3032 def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0,
3033 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
3034 params.regextWm:$Ext),
3035 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3038 def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1,
3039 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm,
3040 params.regextXm:$Ext),
3041 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3044 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]",
3045 (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn,
3048 // Unaligned immediate
3049 def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
3050 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3051 "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3055 def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
3056 (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3058 def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},
3059 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3060 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3064 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
3065 (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3068 def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0},
3069 (outs GPR64xsp:$Rn_wb),
3070 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3071 "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3073 let Constraints = "$Rn = $Rn_wb";
3076 // Decoder only needed for unpredictability checking (FIXME).
3077 let DecoderMethod = "DecodeSingleIndexedInstruction";
3080 def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1},
3081 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3082 (ins GPR64xsp:$Rn, simm9:$SImm9),
3083 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3086 let Constraints = "$Rn = $Rn_wb";
3087 let DecoderMethod = "DecodeSingleIndexedInstruction";
3091 def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0},
3092 (outs GPR64xsp:$Rn_wb),
3093 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3094 "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3096 let Constraints = "$Rn = $Rn_wb";
3099 // Decoder only needed for unpredictability checking (FIXME).
3100 let DecoderMethod = "DecodeSingleIndexedInstruction";
3103 def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1},
3104 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3105 (ins GPR64xsp:$Rn, simm9:$SImm9),
3106 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3109 let Constraints = "$Rn = $Rn_wb";
3110 let DecoderMethod = "DecodeSingleIndexedInstruction";
3115 // STRB/LDRB: First define the instructions
3117 : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>;
3121 : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>;
3124 // STR/LDR to/from a W register
3126 : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>;
3128 // STR/LDR to/from an X register
3130 : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>;
3132 let Predicates = [HasFPARMv8] in {
3133 // STR/LDR to/from a B register
3135 : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>;
3137 // STR/LDR to/from an H register
3139 : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>;
3141 // STR/LDR to/from an S register
3143 : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>;
3144 // STR/LDR to/from a D register
3146 : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>;
3147 // STR/LDR to/from a Q register
3149 : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128,
3153 //===------------------------------
3155 //===------------------------------
3157 // Byte and half-word signed loads can both go into either an X or a W register,
3158 // so it's worth factoring out. Signed word loads don't fit because there is no
3160 multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
3163 def w : A64I_LSunsigimm<size, 0b0, 0b11,
3165 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3166 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3170 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3171 (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3173 def x : A64I_LSunsigimm<size, 0b0, 0b10,
3175 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3176 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3180 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3181 (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3184 let mayLoad = 1 in {
3185 def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0,
3187 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3188 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3191 def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1,
3193 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3194 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3197 def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0,
3199 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3200 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3203 def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1,
3205 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3206 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3209 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3210 (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,
3213 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3214 (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn,
3218 let mayLoad = 1 in {
3220 def w_U : A64I_LSunalimm<size, 0b0, 0b11,
3222 (ins GPR64xsp:$Rn, simm9:$SImm9),
3223 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3226 def x_U : A64I_LSunalimm<size, 0b0, 0b10,
3228 (ins GPR64xsp:$Rn, simm9:$SImm9),
3229 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3234 def w_PostInd : A64I_LSpostind<size, 0b0, 0b11,
3235 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3236 (ins GPR64xsp:$Rn, simm9:$SImm9),
3237 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3239 let Constraints = "$Rn = $Rn_wb";
3240 let DecoderMethod = "DecodeSingleIndexedInstruction";
3243 def x_PostInd : A64I_LSpostind<size, 0b0, 0b10,
3244 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3245 (ins GPR64xsp:$Rn, simm9:$SImm9),
3246 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3248 let Constraints = "$Rn = $Rn_wb";
3249 let DecoderMethod = "DecodeSingleIndexedInstruction";
3253 def w_PreInd : A64I_LSpreind<size, 0b0, 0b11,
3254 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3255 (ins GPR64xsp:$Rn, simm9:$SImm9),
3256 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3258 let Constraints = "$Rn = $Rn_wb";
3259 let DecoderMethod = "DecodeSingleIndexedInstruction";
3262 def x_PreInd : A64I_LSpreind<size, 0b0, 0b10,
3263 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3264 (ins GPR64xsp:$Rn, simm9:$SImm9),
3265 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3267 let Constraints = "$Rn = $Rn_wb";
3268 let DecoderMethod = "DecodeSingleIndexedInstruction";
3270 } // let mayLoad = 1
3274 defm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">;
3276 defm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">;
3278 // LDRSW: load a 32-bit register, sign-extending to 64-bits.
3280 : A64I_LSunsigimm<0b10, 0b0, 0b10,
3282 (ins GPR64xsp:$Rn, word_uimm12:$UImm12),
3283 "ldrsw\t$Rt, [$Rn, $UImm12]",
3287 def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3289 let mayLoad = 1 in {
3290 def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0,
3292 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
3293 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3296 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,
3298 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),
3299 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3302 def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",
3303 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;
3307 : A64I_LSunalimm<0b10, 0b0, 0b10,
3309 (ins GPR64xsp:$Rn, simm9:$SImm9),
3310 "ldursw\t$Rt, [$Rn, $SImm9]",
3314 def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3317 : A64I_LSpostind<0b10, 0b0, 0b10,
3318 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3319 (ins GPR64xsp:$Rn, simm9:$SImm9),
3320 "ldrsw\t$Rt, [$Rn], $SImm9",
3323 let Constraints = "$Rn = $Rn_wb";
3324 let DecoderMethod = "DecodeSingleIndexedInstruction";
3327 def LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10,
3328 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3329 (ins GPR64xsp:$Rn, simm9:$SImm9),
3330 "ldrsw\t$Rt, [$Rn, $SImm9]!",
3333 let Constraints = "$Rn = $Rn_wb";
3334 let DecoderMethod = "DecodeSingleIndexedInstruction";
3337 //===------------------------------
3338 // 2.4 Prefetch operations
3339 //===------------------------------
3341 def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
3342 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
3343 "prfm\t$Rt, [$Rn, $UImm12]",
3347 def : InstAlias<"prfm $Rt, [$Rn]",
3348 (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3350 let mayLoad = 1 in {
3351 def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs),
3352 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3353 GPR32:$Rm, dword_Wm_regext:$Ext),
3354 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3356 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),
3357 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3358 GPR64:$Rm, dword_Xm_regext:$Ext),
3359 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3363 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
3364 (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn,
3368 def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
3369 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3370 "prfum\t$Rt, [$Rn, $SImm9]",
3374 def : InstAlias<"prfum $Rt, [$Rn]",
3375 (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3377 //===----------------------------------------------------------------------===//
3378 // Load-store register (unprivileged) instructions
3379 //===----------------------------------------------------------------------===//
3380 // Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH
3382 // These instructions very much mirror the "unscaled immediate" loads, but since
3383 // there are no floating-point variants we need to split them out into their own
3384 // section to avoid instantiation of "ldtr d0, [sp]" etc.
3386 multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR,
3388 def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,
3389 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3390 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3395 def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]",
3396 (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3398 def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,
3399 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3400 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3405 def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]",
3406 (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3410 // STTRB/LDTRB: First define the instructions
3411 defm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">;
3414 defm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">;
3416 // STTR/LDTR to/from a W register
3417 defm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">;
3419 // STTR/LDTR to/from an X register
3420 defm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">;
3422 // Now a class for the signed instructions that can go to either 32 or 64
3424 multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> {
3425 let mayLoad = 1 in {
3426 def w : A64I_LSunpriv<size, 0b0, 0b11,
3428 (ins GPR64xsp:$Rn, simm9:$SImm9),
3429 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3432 def x : A64I_LSunpriv<size, 0b0, 0b10,
3434 (ins GPR64xsp:$Rn, simm9:$SImm9),
3435 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3439 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3440 (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3442 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3443 (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3448 defm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">;
3450 defm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">;
3452 // And finally LDTRSW which only goes to 64 bits.
3453 def LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10,
3455 (ins GPR64xsp:$Rn, simm9:$SImm9),
3456 "ldtrsw\t$Rt, [$Rn, $SImm9]",
3460 def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3462 //===----------------------------------------------------------------------===//
3463 // Load-store register pair (offset) instructions
3464 //===----------------------------------------------------------------------===//
3468 //===----------------------------------------------------------------------===//
3469 // Load-store register pair (post-indexed) instructions
3470 //===----------------------------------------------------------------------===//
3471 // Contains: STP, LDP, LDPSW
3475 //===----------------------------------------------------------------------===//
3476 // Load-store register pair (pre-indexed) instructions
3477 //===----------------------------------------------------------------------===//
3478 // Contains: STP, LDP, LDPSW
3482 //===----------------------------------------------------------------------===//
3483 // Load-store non-temporal register pair (offset) instructions
3484 //===----------------------------------------------------------------------===//
3485 // Contains: STNP, LDNP
3488 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
3489 // know the access size via some means. An isolated operand does not have this
3490 // information unless told from here, which means we need separate tablegen
3491 // Operands for each access size. This multiclass takes care of instantiating
3492 // the correct template functions in the rest of the backend.
3494 multiclass offsets_simm7<string MemSize, string prefix> {
3495 // The bare signed 7-bit immediate is used in post-indexed instructions, but
3496 // because of the scaling performed a generic "simm7" operand isn't
3497 // appropriate here either.
3498 def simm7_asmoperand : AsmOperandClass {
3499 let Name = "SImm7_Scaled" # MemSize;
3500 let PredicateMethod = "isSImm7Scaled<" # MemSize # ">";
3501 let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">";
3502 let DiagnosticType = "LoadStoreSImm7_" # MemSize;
3505 def simm7 : Operand<i64> {
3506 let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">";
3507 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand");
3511 defm word_ : offsets_simm7<"4", "word_">;
3512 defm dword_ : offsets_simm7<"8", "dword_">;
3513 defm qword_ : offsets_simm7<"16", "qword_">;
3515 multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
3516 Operand simm7, string prefix> {
3517 def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),
3518 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3519 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3521 let DecoderMethod = "DecodeLDSTPairInstruction";
3523 def : InstAlias<"stp $Rt, $Rt2, [$Rn]",
3524 (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt,
3525 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3527 def _LDR : A64I_LSPoffset<opc, v, 0b1,
3528 (outs SomeReg:$Rt, SomeReg:$Rt2),
3529 (ins GPR64xsp:$Rn, simm7:$SImm7),
3530 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3532 let DecoderMethod = "DecodeLDSTPairInstruction";
3534 def : InstAlias<"ldp $Rt, $Rt2, [$Rn]",
3535 (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt,
3536 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3538 def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0,
3539 (outs GPR64xsp:$Rn_wb),
3540 (ins SomeReg:$Rt, SomeReg:$Rt2,
3543 "stp\t$Rt, $Rt2, [$Rn], $SImm7",
3546 let Constraints = "$Rn = $Rn_wb";
3548 // Decoder only needed for unpredictability checking (FIXME).
3549 let DecoderMethod = "DecodeLDSTPairInstruction";
3552 def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1,
3553 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3554 (ins GPR64xsp:$Rn, simm7:$SImm7),
3555 "ldp\t$Rt, $Rt2, [$Rn], $SImm7",
3558 let Constraints = "$Rn = $Rn_wb";
3559 let DecoderMethod = "DecodeLDSTPairInstruction";
3562 def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
3563 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3564 "stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3567 let Constraints = "$Rn = $Rn_wb";
3568 let DecoderMethod = "DecodeLDSTPairInstruction";
3571 def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1,
3572 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3573 (ins GPR64xsp:$Rn, simm7:$SImm7),
3574 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3577 let Constraints = "$Rn = $Rn_wb";
3578 let DecoderMethod = "DecodeLDSTPairInstruction";
3581 def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
3582 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3583 "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3585 let DecoderMethod = "DecodeLDSTPairInstruction";
3587 def : InstAlias<"stnp $Rt, $Rt2, [$Rn]",
3588 (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt,
3589 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3591 def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,
3592 (outs SomeReg:$Rt, SomeReg:$Rt2),
3593 (ins GPR64xsp:$Rn, simm7:$SImm7),
3594 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3596 let DecoderMethod = "DecodeLDSTPairInstruction";
3598 def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]",
3599 (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt,
3600 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3605 defm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">;
3606 defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">;
3608 let Predicates = [HasFPARMv8] in {
3609 defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">;
3610 defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">;
3611 defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7,
3616 def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
3617 (outs GPR64:$Rt, GPR64:$Rt2),
3618 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3619 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3621 let DecoderMethod = "DecodeLDSTPairInstruction";
3623 def : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]",
3624 (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>;
3626 def LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1,
3627 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3628 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3629 "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
3632 let Constraints = "$Rn = $Rn_wb";
3633 let DecoderMethod = "DecodeLDSTPairInstruction";
3636 def LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1,
3637 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3638 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3639 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
3642 let Constraints = "$Rn = $Rn_wb";
3643 let DecoderMethod = "DecodeLDSTPairInstruction";
3646 //===----------------------------------------------------------------------===//
3647 // Logical (immediate) instructions
3648 //===----------------------------------------------------------------------===//
3649 // Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV
3651 multiclass logical_imm_operands<string prefix, string note,
3652 int size, ValueType VT> {
3653 def _asmoperand : AsmOperandClass {
3654 let Name = "LogicalImm" # note # size;
3655 let PredicateMethod = "isLogicalImm" # note # "<" # size # ">";
3656 let RenderMethod = "addLogicalImmOperands<" # size # ">";
3657 let DiagnosticType = "LogicalSecondSource";
3661 : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> {
3662 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3663 let PrintMethod = "printLogicalImmOperand<" # size # ">";
3664 let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">";
3668 defm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>;
3669 defm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>;
3671 // The mov versions only differ in assembly parsing, where they
3672 // exclude values representable with either MOVZ or MOVN.
3673 defm logical_imm32_mov
3674 : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>;
3675 defm logical_imm64_mov
3676 : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>;
3679 multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> {
3680 def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd),
3681 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3682 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3684 (opnode i32:$Rn, logical_imm32_operand:$Imm))],
3687 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
3688 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3689 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3691 (opnode i64:$Rn, logical_imm64_operand:$Imm))],
3695 defm AND : A64I_logimmSizes<0b00, "and", and>;
3696 defm ORR : A64I_logimmSizes<0b01, "orr", or>;
3697 defm EOR : A64I_logimmSizes<0b10, "eor", xor>;
3699 let Defs = [NZCV] in {
3700 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
3701 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3702 "ands\t$Rd, $Rn, $Imm",
3705 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),
3706 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3707 "ands\t$Rd, $Rn, $Imm",
3712 def : InstAlias<"tst $Rn, $Imm",
3713 (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>;
3714 def : InstAlias<"tst $Rn, $Imm",
3715 (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>;
3716 def : InstAlias<"mov $Rd, $Imm",
3717 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>;
3718 def : InstAlias<"mov $Rd, $Imm",
3719 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>;
3721 //===----------------------------------------------------------------------===//
3722 // Logical (shifted register) instructions
3723 //===----------------------------------------------------------------------===//
3724 // Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV
3726 // Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS"
3727 // behaves differently for unsigned comparisons, so we defensively only allow
3728 // signed or n/a as the operand. In practice "unsigned greater than 0" is "not
3729 // equal to 0" and LLVM gives us this.
3730 def signed_cond : PatLeaf<(cond), [{
3731 return !isUnsignedIntSetCC(N->get());
3735 // These instructions share their "shift" operands with add/sub (shifted
3736 // register instructions). They are defined there.
3738 // N.b. the commutable parameter is just !N. It will be first against the wall
3739 // when the revolution comes.
3740 multiclass logical_shifts<string prefix, bit sf, bits<2> opc,
3741 bit N, bit commutable,
3742 string asmop, SDPatternOperator opfrag, ValueType ty,
3743 RegisterClass GPR, list<Register> defs> {
3744 let isCommutable = commutable, Defs = defs in {
3745 def _lsl : A64I_logicalshift<sf, opc, 0b00, N,
3747 (ins GPR:$Rn, GPR:$Rm,
3748 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3749 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3750 [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
3751 !cast<Operand>("lsl_operand_" # ty):$Imm6))
3755 def _lsr : A64I_logicalshift<sf, opc, 0b01, N,
3757 (ins GPR:$Rn, GPR:$Rm,
3758 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3759 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3760 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
3761 !cast<Operand>("lsr_operand_" # ty):$Imm6))
3765 def _asr : A64I_logicalshift<sf, opc, 0b10, N,
3767 (ins GPR:$Rn, GPR:$Rm,
3768 !cast<Operand>("asr_operand_" # ty):$Imm6),
3769 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3770 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
3771 !cast<Operand>("asr_operand_" # ty):$Imm6))
3775 def _ror : A64I_logicalshift<sf, opc, 0b11, N,
3777 (ins GPR:$Rn, GPR:$Rm,
3778 !cast<Operand>("ror_operand_" # ty):$Imm6),
3779 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3780 [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm,
3781 !cast<Operand>("ror_operand_" # ty):$Imm6))
3787 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
3788 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
3791 def : Pat<(opfrag ty:$Rn, ty:$Rm),
3792 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
3795 multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable,
3796 string asmop, SDPatternOperator opfrag,
3797 list<Register> defs> {
3798 defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N,
3799 commutable, asmop, opfrag, i64, GPR64, defs>;
3800 defm www : logical_shifts<prefix # "www", 0b0, opc, N,
3801 commutable, asmop, opfrag, i32, GPR32, defs>;
3805 defm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>;
3806 defm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>;
3807 defm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>;
3808 defm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands",
3809 PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs),
3810 [{ (void)N; return false; }]>,
3813 defm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic",
3814 PatFrag<(ops node:$lhs, node:$rhs),
3815 (and node:$lhs, (not node:$rhs))>, []>;
3816 defm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn",
3817 PatFrag<(ops node:$lhs, node:$rhs),
3818 (or node:$lhs, (not node:$rhs))>, []>;
3819 defm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon",
3820 PatFrag<(ops node:$lhs, node:$rhs),
3821 (xor node:$lhs, (not node:$rhs))>, []>;
3822 defm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics",
3823 PatFrag<(ops node:$lhs, node:$rhs),
3824 (and node:$lhs, (not node:$rhs)),
3825 [{ (void)N; return false; }]>,
3828 multiclass tst_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
3829 let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in {
3830 def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0,
3832 (ins GPR:$Rn, GPR:$Rm,
3833 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3834 "tst\t$Rn, $Rm, $Imm6",
3835 [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm,
3836 !cast<Operand>("lsl_operand_" # ty):$Imm6)),
3841 def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0,
3843 (ins GPR:$Rn, GPR:$Rm,
3844 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3845 "tst\t$Rn, $Rm, $Imm6",
3846 [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm,
3847 !cast<Operand>("lsr_operand_" # ty):$Imm6)),
3851 def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0,
3853 (ins GPR:$Rn, GPR:$Rm,
3854 !cast<Operand>("asr_operand_" # ty):$Imm6),
3855 "tst\t$Rn, $Rm, $Imm6",
3856 [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm,
3857 !cast<Operand>("asr_operand_" # ty):$Imm6)),
3861 def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0,
3863 (ins GPR:$Rn, GPR:$Rm,
3864 !cast<Operand>("ror_operand_" # ty):$Imm6),
3865 "tst\t$Rn, $Rm, $Imm6",
3866 [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm,
3867 !cast<Operand>("ror_operand_" # ty):$Imm6)),
3872 def _noshift : InstAlias<"tst $Rn, $Rm",
3873 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3875 def : Pat<(A64setcc (and ty:$Rn, ty:$Rm), 0, signed_cond),
3876 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
3879 defm TSTxx : tst_shifts<"TSTxx", 0b1, i64, GPR64>;
3880 defm TSTww : tst_shifts<"TSTww", 0b0, i32, GPR32>;
3883 multiclass mvn_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
3884 let isCommutable = 0, Rn = 0b11111 in {
3885 def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1,
3888 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3889 "mvn\t$Rd, $Rm, $Imm6",
3890 [(set ty:$Rd, (not (shl ty:$Rm,
3891 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
3895 def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1,
3898 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3899 "mvn\t$Rd, $Rm, $Imm6",
3900 [(set ty:$Rd, (not (srl ty:$Rm,
3901 !cast<Operand>("lsr_operand_" # ty):$Imm6)))],
3904 def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1,
3907 !cast<Operand>("asr_operand_" # ty):$Imm6),
3908 "mvn\t$Rd, $Rm, $Imm6",
3909 [(set ty:$Rd, (not (sra ty:$Rm,
3910 !cast<Operand>("asr_operand_" # ty):$Imm6)))],
3913 def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1,
3916 !cast<Operand>("ror_operand_" # ty):$Imm6),
3917 "mvn\t$Rd, $Rm, $Imm6",
3918 [(set ty:$Rd, (not (rotr ty:$Rm,
3919 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
3923 def _noshift : InstAlias<"mvn $Rn, $Rm",
3924 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3926 def : Pat<(not ty:$Rm),
3927 (!cast<Instruction>(prefix # "_lsl") $Rm, 0)>;
3930 defm MVNxx : mvn_shifts<"MVNxx", 0b1, i64, GPR64>;
3931 defm MVNww : mvn_shifts<"MVNww", 0b0, i32, GPR32>;
3933 def MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
3934 def MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
3936 //===----------------------------------------------------------------------===//
3937 // Move wide (immediate) instructions
3938 //===----------------------------------------------------------------------===//
3939 // Contains: MOVN, MOVZ, MOVK + MOV aliases
3941 // A wide variety of different relocations are needed for variants of these
3942 // instructions, so it turns out that we need a different operand for all of
3944 multiclass movw_operands<string prefix, string instname, int width> {
3945 def _imm_asmoperand : AsmOperandClass {
3946 let Name = instname # width # "Shifted" # shift;
3947 let PredicateMethod = "is" # instname # width # "Imm";
3948 let RenderMethod = "addMoveWideImmOperands";
3949 let ParserMethod = "ParseImmWithLSLOperand";
3950 let DiagnosticType = "MOVWUImm16";
3953 def _imm : Operand<i64> {
3954 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand");
3955 let PrintMethod = "printMoveWideImmOperand";
3956 let EncoderMethod = "getMoveWideImmOpValue";
3957 let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">";
3959 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
3963 defm movn32 : movw_operands<"movn32", "MOVN", 32>;
3964 defm movn64 : movw_operands<"movn64", "MOVN", 64>;
3965 defm movz32 : movw_operands<"movz32", "MOVZ", 32>;
3966 defm movz64 : movw_operands<"movz64", "MOVZ", 64>;
3967 defm movk32 : movw_operands<"movk32", "MOVK", 32>;
3968 defm movk64 : movw_operands<"movk64", "MOVK", 64>;
3970 multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit,
3973 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
3974 !strconcat(asmop, "\t$Rd, $FullImm"),
3977 let UImm16 = FullImm{15-0};
3978 let Shift = FullImm{17-16};
3981 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
3982 !strconcat(asmop, "\t$Rd, $FullImm"),
3985 let UImm16 = FullImm{15-0};
3986 let Shift = FullImm{17-16};
3990 let isMoveImm = 1, isReMaterializable = 1,
3991 isAsCheapAsAMove = 1, hasSideEffects = 0 in {
3992 defm MOVN : A64I_movwSizes<0b00, "movn",
3993 (ins movn32_imm:$FullImm),
3994 (ins movn64_imm:$FullImm)>;
3996 // Some relocations are able to convert between a MOVZ and a MOVN. If these
3997 // are applied the instruction must be emitted with the corresponding bits as
3998 // 0, which means a MOVZ needs to override that bit from the default.
3999 let PostEncoderMethod = "fixMOVZ" in
4000 defm MOVZ : A64I_movwSizes<0b10, "movz",
4001 (ins movz32_imm:$FullImm),
4002 (ins movz64_imm:$FullImm)>;
4005 let Constraints = "$src = $Rd" in
4006 defm MOVK : A64I_movwSizes<0b11, "movk",
4007 (ins GPR32:$src, movk32_imm:$FullImm),
4008 (ins GPR64:$src, movk64_imm:$FullImm)>;
4011 // And now the "MOV" aliases. These also need their own operands because what
4012 // they accept is completely different to what the base instructions accept.
4013 multiclass movalias_operand<string prefix, string basename,
4014 string immpredicate, int width> {
4015 def _asmoperand : AsmOperandClass {
4016 let Name = basename # width # "MovAlias";
4018 = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">";
4020 = "addMoveWideMovAliasOperands<" # width # ", "
4021 # "A64Imms::" # immpredicate # ">";
4024 def _movimm : Operand<i64> {
4025 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
4027 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
4031 defm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>;
4032 defm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>;
4033 defm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>;
4034 defm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>;
4036 // FIXME: these are officially canonical aliases, but TableGen is too limited to
4037 // print them at the moment. I believe in this case an "AliasPredicate" method
4038 // will need to be implemented. to allow it, as well as the more generally
4039 // useful handling of non-register, non-constant operands.
4040 class movalias<Instruction INST, RegisterClass GPR, Operand operand>
4041 : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>;
4043 def : movalias<MOVZwii, GPR32, movz32_movimm>;
4044 def : movalias<MOVZxii, GPR64, movz64_movimm>;
4045 def : movalias<MOVNwii, GPR32, movn32_movimm>;
4046 def : movalias<MOVNxii, GPR64, movn64_movimm>;
4048 def movw_addressref_g0 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<0>">;
4049 def movw_addressref_g1 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<1>">;
4050 def movw_addressref_g2 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<2>">;
4051 def movw_addressref_g3 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<3>">;
4053 def : Pat<(A64WrapperLarge movw_addressref_g3:$G3, movw_addressref_g2:$G2,
4054 movw_addressref_g1:$G1, movw_addressref_g0:$G0),
4055 (MOVKxii (MOVKxii (MOVKxii (MOVZxii movw_addressref_g3:$G3),
4056 movw_addressref_g2:$G2),
4057 movw_addressref_g1:$G1),
4058 movw_addressref_g0:$G0)>;
4060 //===----------------------------------------------------------------------===//
4061 // PC-relative addressing instructions
4062 //===----------------------------------------------------------------------===//
4063 // Contains: ADR, ADRP
4065 def adr_label : Operand<i64> {
4066 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>";
4068 // This label is a 21-bit offset from PC, unscaled
4069 let PrintMethod = "printLabelOperand<21, 1>";
4070 let ParserMatchClass = label_asmoperand<21, 1>;
4071 let OperandType = "OPERAND_PCREL";
4074 def adrp_label_asmoperand : AsmOperandClass {
4075 let Name = "AdrpLabel";
4076 let RenderMethod = "addLabelOperands<21, 4096>";
4077 let DiagnosticType = "Label";
4080 def adrp_label : Operand<i64> {
4081 let EncoderMethod = "getAdrpLabelOpValue";
4083 // This label is a 21-bit offset from PC, scaled by the page-size: 4096.
4084 let PrintMethod = "printLabelOperand<21, 4096>";
4085 let ParserMatchClass = adrp_label_asmoperand;
4086 let OperandType = "OPERAND_PCREL";
4089 let hasSideEffects = 0 in {
4090 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
4091 "adr\t$Rd, $Label", [], NoItinerary>;
4093 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),
4094 "adrp\t$Rd, $Label", [], NoItinerary>;
4097 //===----------------------------------------------------------------------===//
4098 // System instructions
4099 //===----------------------------------------------------------------------===//
4100 // Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS
4101 // + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL
4103 // Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values.
4104 def uimm3_asmoperand : AsmOperandClass {
4106 let PredicateMethod = "isUImm<3>";
4107 let RenderMethod = "addImmOperands";
4108 let DiagnosticType = "UImm3";
4111 def uimm3 : Operand<i32> {
4112 let ParserMatchClass = uimm3_asmoperand;
4115 // The HINT alias can accept a simple unsigned 7-bit immediate.
4116 def uimm7_asmoperand : AsmOperandClass {
4118 let PredicateMethod = "isUImm<7>";
4119 let RenderMethod = "addImmOperands";
4120 let DiagnosticType = "UImm7";
4123 def uimm7 : Operand<i32> {
4124 let ParserMatchClass = uimm7_asmoperand;
4127 // Multiclass namedimm is defined with the prefetch operands. Most of these fit
4128 // into the NamedImmMapper scheme well: they either accept a named operand or
4129 // any immediate under a particular value (which may be 0, implying no immediate
4131 defm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">;
4132 defm isb : namedimm<"isb", "A64ISB::ISBMapper">;
4133 defm ic : namedimm<"ic", "A64IC::ICMapper">;
4134 defm dc : namedimm<"dc", "A64DC::DCMapper">;
4135 defm at : namedimm<"at", "A64AT::ATMapper">;
4136 defm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">;
4138 // However, MRS and MSR are more complicated for a few reasons:
4139 // * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an
4140 // implementation-defined effect
4141 // * Most registers are shared, but some are read-only or write-only.
4142 // * There is a variant of MSR which accepts the same register name (SPSel),
4143 // but which would have a different encoding.
4145 // In principle these could be resolved in with more complicated subclasses of
4146 // NamedImmMapper, however that imposes an overhead on other "named
4147 // immediates". Both in concrete terms with virtual tables and in unnecessary
4150 // The solution adopted here is to take the MRS/MSR Mappers out of the usual
4151 // hierarchy (they're not derived from NamedImmMapper) and to add logic for
4152 // their special situation.
4153 def mrs_asmoperand : AsmOperandClass {
4155 let ParserMethod = "ParseSysRegOperand";
4156 let DiagnosticType = "MRS";
4159 def mrs_op : Operand<i32> {
4160 let ParserMatchClass = mrs_asmoperand;
4161 let PrintMethod = "printMRSOperand";
4162 let DecoderMethod = "DecodeMRSOperand";
4165 def msr_asmoperand : AsmOperandClass {
4166 let Name = "MSRWithReg";
4168 // Note that SPSel is valid for both this and the pstate operands, but with
4169 // different immediate encodings. This is why these operands provide a string
4170 // AArch64Operand rather than an immediate. The overlap is small enough that
4171 // it could be resolved with hackery now, but who can say in future?
4172 let ParserMethod = "ParseSysRegOperand";
4173 let DiagnosticType = "MSR";
4176 def msr_op : Operand<i32> {
4177 let ParserMatchClass = msr_asmoperand;
4178 let PrintMethod = "printMSROperand";
4179 let DecoderMethod = "DecodeMSROperand";
4182 def pstate_asmoperand : AsmOperandClass {
4183 let Name = "MSRPState";
4184 // See comment above about parser.
4185 let ParserMethod = "ParseSysRegOperand";
4186 let DiagnosticType = "MSR";
4189 def pstate_op : Operand<i32> {
4190 let ParserMatchClass = pstate_asmoperand;
4191 let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>";
4192 let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>";
4195 // When <CRn> is specified, an assembler should accept something like "C4", not
4196 // the usual "#4" immediate.
4197 def CRx_asmoperand : AsmOperandClass {
4199 let PredicateMethod = "isUImm<4>";
4200 let RenderMethod = "addImmOperands";
4201 let ParserMethod = "ParseCRxOperand";
4202 // Diagnostics are handled in all cases by ParseCRxOperand.
4205 def CRx : Operand<i32> {
4206 let ParserMatchClass = CRx_asmoperand;
4207 let PrintMethod = "printCRxOperand";
4211 // Finally, we can start defining the instructions.
4213 // HINT is straightforward, with a few aliases.
4214 def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7",
4217 let CRm = UImm7{6-3};
4218 let Op2 = UImm7{2-0};
4226 def : InstAlias<"nop", (HINTi 0)>;
4227 def : InstAlias<"yield", (HINTi 1)>;
4228 def : InstAlias<"wfe", (HINTi 2)>;
4229 def : InstAlias<"wfi", (HINTi 3)>;
4230 def : InstAlias<"sev", (HINTi 4)>;
4231 def : InstAlias<"sevl", (HINTi 5)>;
4233 // Quite a few instructions then follow a similar pattern of fixing common
4234 // fields in the bitpattern, we'll define a helper-class for them.
4235 class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2,
4236 Operand operand, string asmop>
4237 : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"),
4247 def CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">;
4248 def DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">;
4249 def DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">;
4250 def ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">;
4252 def : InstAlias<"clrex", (CLREXi 0b1111)>;
4253 def : InstAlias<"isb", (ISBi 0b1111)>;
4255 // (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP
4256 // configurations at least.
4257 def : Pat<(atomic_fence imm, imm), (DMBi 0xb)>;
4259 // Any SYS bitpattern can be represented with a complex and opaque "SYS"
4261 def SYSiccix : A64I_system<0b0, (outs),
4262 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm,
4263 uimm3:$Op2, GPR64:$Rt),
4264 "sys\t$Op1, $CRn, $CRm, $Op2, $Rt",
4269 // You can skip the Xt argument whether it makes sense or not for the generic
4271 def : InstAlias<"sys $Op1, $CRn, $CRm, $Op2",
4272 (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>;
4275 // But many have aliases, which obviously don't fit into
4276 class SYSalias<dag ins, string asmstring>
4277 : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> {
4278 let isAsmParserOnly = 1;
4282 let Op1 = SysOp{13-11};
4283 let CRn = SysOp{10-7};
4284 let CRm = SysOp{6-3};
4285 let Op2 = SysOp{2-0};
4288 def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">;
4290 def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> {
4294 def DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">;
4295 def ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">;
4297 def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">;
4299 def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> {
4304 def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt),
4305 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2),
4306 "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2",
4311 // The instructions themselves are rather simple for MSR and MRS.
4312 def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt),
4313 "msr\t$SysReg, $Rt", [], NoItinerary> {
4315 let Op0 = SysReg{15-14};
4316 let Op1 = SysReg{13-11};
4317 let CRn = SysReg{10-7};
4318 let CRm = SysReg{6-3};
4319 let Op2 = SysReg{2-0};
4322 def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg),
4323 "mrs\t$Rt, $SysReg", [], NoItinerary> {
4325 let Op0 = SysReg{15-14};
4326 let Op1 = SysReg{13-11};
4327 let CRn = SysReg{10-7};
4328 let CRm = SysReg{6-3};
4329 let Op2 = SysReg{2-0};
4332 def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm),
4333 "msr\t$PState, $CRm", [], NoItinerary> {
4337 let Op1 = PState{5-3};
4339 let Op2 = PState{2-0};
4343 //===----------------------------------------------------------------------===//
4344 // Test & branch (immediate) instructions
4345 //===----------------------------------------------------------------------===//
4346 // Contains: TBZ, TBNZ
4348 // The bit to test is a simple unsigned 6-bit immediate in the X-register
4350 def uimm6 : Operand<i64> {
4351 let ParserMatchClass = uimm6_asmoperand;
4354 def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>;
4356 def tbimm_target : Operand<OtherVT> {
4357 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>";
4359 // This label is a 14-bit offset from PC, scaled by the instruction-width: 4.
4360 let PrintMethod = "printLabelOperand<14, 4>";
4361 let ParserMatchClass = label_wid14_scal4_asmoperand;
4363 let OperandType = "OPERAND_PCREL";
4366 def A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>;
4367 def A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>;
4369 // These instructions correspond to patterns involving "and" with a power of
4370 // two, which we need to be able to select.
4371 def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">;
4372 def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">;
4374 let isBranch = 1, isTerminator = 1 in {
4375 def TBZxii : A64I_TBimm<0b0, (outs),
4376 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4377 "tbz\t$Rt, $Imm, $Label",
4378 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4382 def TBNZxii : A64I_TBimm<0b1, (outs),
4383 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4384 "tbnz\t$Rt, $Imm, $Label",
4385 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4390 // Note, these instructions overlap with the above 64-bit patterns. This is
4391 // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both
4392 // do the same thing and are both permitted assembly. They also both have
4393 // sensible DAG patterns.
4394 def TBZwii : A64I_TBimm<0b0, (outs),
4395 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4396 "tbz\t$Rt, $Imm, $Label",
4397 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4403 def TBNZwii : A64I_TBimm<0b1, (outs),
4404 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4405 "tbnz\t$Rt, $Imm, $Label",
4406 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4413 //===----------------------------------------------------------------------===//
4414 // Unconditional branch (immediate) instructions
4415 //===----------------------------------------------------------------------===//
4418 def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>;
4420 def bimm_target : Operand<OtherVT> {
4421 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>";
4423 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4424 let PrintMethod = "printLabelOperand<26, 4>";
4425 let ParserMatchClass = label_wid26_scal4_asmoperand;
4427 let OperandType = "OPERAND_PCREL";
4430 def blimm_target : Operand<i64> {
4431 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>";
4433 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4434 let PrintMethod = "printLabelOperand<26, 4>";
4435 let ParserMatchClass = label_wid26_scal4_asmoperand;
4437 let OperandType = "OPERAND_PCREL";
4440 class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type>
4441 : A64I_Bimm<op, (outs), (ins lbl_type:$Label),
4442 !strconcat(asmop, "\t$Label"), patterns,
4445 let isBranch = 1 in {
4446 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
4447 let isTerminator = 1;
4451 def BLimm : A64I_BimmImpl<0b1, "bl",
4452 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4458 def : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>;
4460 //===----------------------------------------------------------------------===//
4461 // Unconditional branch (register) instructions
4462 //===----------------------------------------------------------------------===//
4463 // Contains: BR, BLR, RET, ERET, DRP.
4465 // Most of the notional opcode fields in the A64I_Breg format are fixed in A64
4467 class A64I_BregImpl<bits<4> opc,
4468 dag outs, dag ins, string asmstr, list<dag> patterns,
4469 InstrItinClass itin = NoItinerary>
4470 : A64I_Breg<opc, 0b11111, 0b000000, 0b00000,
4471 outs, ins, asmstr, patterns, itin> {
4473 let isIndirectBranch = 1;
4476 // Note that these are not marked isCall or isReturn because as far as LLVM is
4477 // concerned they're not. "ret" is just another jump unless it has been selected
4478 // by LLVM as the function's return.
4480 let isBranch = 1 in {
4481 def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn),
4482 "br\t$Rn", [(brind i64:$Rn)]> {
4484 let isTerminator = 1;
4487 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4488 "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
4494 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
4497 let isTerminator = 1;
4501 // Create a separate pseudo-instruction for codegen to use so that we don't
4502 // flag x30 as used in every function. It'll be restored before the RET by the
4503 // epilogue if it's legitimately used.
4504 def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> {
4505 let isTerminator = 1;
4510 def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> {
4513 let isTerminator = 1;
4517 def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> {
4523 def RETAlias : InstAlias<"ret", (RETx X30)>;
4526 //===----------------------------------------------------------------------===//
4527 // Address generation patterns
4528 //===----------------------------------------------------------------------===//
4530 // Primary method of address generation for the small/absolute memory model is
4531 // an ADRP/ADR pair:
4532 // ADRP x0, some_variable
4533 // ADD x0, x0, #:lo12:some_variable
4535 // The load/store elision of the ADD is accomplished when selecting
4536 // addressing-modes. This just mops up the cases where that doesn't work and we
4537 // really need an address in some register.
4539 // This wrapper applies a LO12 modifier to the address. Otherwise we could just
4540 // use the same address.
4542 class ADRP_ADD<SDNode Wrapper, SDNode addrop>
4543 : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)),
4544 (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>;
4546 def : ADRP_ADD<A64WrapperSmall, tblockaddress>;
4547 def : ADRP_ADD<A64WrapperSmall, texternalsym>;
4548 def : ADRP_ADD<A64WrapperSmall, tglobaladdr>;
4549 def : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>;
4550 def : ADRP_ADD<A64WrapperSmall, tjumptable>;
4551 def : ADRP_ADD<A64WrapperSmall, tconstpool>;
4553 //===----------------------------------------------------------------------===//
4554 // GOT access patterns
4555 //===----------------------------------------------------------------------===//
4557 class GOTLoadSmall<SDNode addrfrag>
4558 : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)),
4559 (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>;
4561 def : GOTLoadSmall<texternalsym>;
4562 def : GOTLoadSmall<tglobaladdr>;
4563 def : GOTLoadSmall<tglobaltlsaddr>;
4565 //===----------------------------------------------------------------------===//
4566 // Tail call handling
4567 //===----------------------------------------------------------------------===//
4569 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in {
4571 : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff),
4572 [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>;
4575 : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff),
4576 [(AArch64tcret i64:$dst, (i32 timm:$FPDiff))]>;
4579 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
4581 def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [],
4582 (Bimm bimm_target:$Label)>;
4584 def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [],
4589 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
4590 (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>;
4592 //===----------------------------------------------------------------------===//
4593 // Thread local storage
4594 //===----------------------------------------------------------------------===//
4596 // This is a pseudo-instruction representing the ".tlsdesccall" directive in
4597 // assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the
4598 // current location. It should always be immediately followed by a BLR
4599 // instruction, and is intended solely for relaxation by the linker.
4601 def : Pat<(A64threadpointer), (MRSxi 0xde82)>;
4603 def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> {
4604 let hasSideEffects = 1;
4607 def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var),
4608 [(A64tlsdesc_blr i64:$Rn, tglobaltlsaddr:$Var)]> {
4613 def : Pat<(A64tlsdesc_blr i64:$Rn, texternalsym:$Var),
4614 (TLSDESC_BLRx $Rn, texternalsym:$Var)>;
4616 //===----------------------------------------------------------------------===//
4617 // Bitfield patterns
4618 //===----------------------------------------------------------------------===//
4620 def bfi32_lsb_to_immr : SDNodeXForm<imm, [{
4621 return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64);
4624 def bfi64_lsb_to_immr : SDNodeXForm<imm, [{
4625 return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64);
4628 def bfi_width_to_imms : SDNodeXForm<imm, [{
4629 return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64);
4633 // The simpler patterns deal with cases where no AND mask is actually needed
4634 // (either all bits are used or the low 32 bits are used).
4635 let AddedComplexity = 10 in {
4637 def : Pat<(A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4639 (bfi64_lsb_to_immr (i64 imm:$ImmR)),
4640 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4642 def : Pat<(A64Bfi i32:$src, i32:$Rn, imm:$ImmR, imm:$ImmS),
4644 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4645 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4648 def : Pat<(and (A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4650 (SUBREG_TO_REG (i64 0),
4651 (BFIwwii (EXTRACT_SUBREG $src, sub_32),
4652 (EXTRACT_SUBREG $Rn, sub_32),
4653 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4654 (bfi_width_to_imms (i64 imm:$ImmS))),
4659 //===----------------------------------------------------------------------===//
4660 // Miscellaneous patterns
4661 //===----------------------------------------------------------------------===//
4663 // Truncation from 64 to 32-bits just involves renaming your register.
4664 def : Pat<(i32 (trunc i64:$val)), (EXTRACT_SUBREG $val, sub_32)>;
4666 // Similarly, extension where we don't care about the high bits is
4668 def : Pat<(i64 (anyext i32:$val)),
4669 (INSERT_SUBREG (IMPLICIT_DEF), $val, sub_32)>;
4671 // SELECT instructions providing f128 types need to be handled by a
4672 // pseudo-instruction since the eventual code will need to introduce basic
4673 // blocks and control flow.
4674 def F128CSEL : PseudoInst<(outs FPR128:$Rd),
4675 (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond),
4676 [(set f128:$Rd, (simple_select f128:$Rn, f128:$Rm))]> {
4678 let usesCustomInserter = 1;
4681 //===----------------------------------------------------------------------===//
4682 // Load/store patterns
4683 //===----------------------------------------------------------------------===//
4685 // There are lots of patterns here, because we need to allow at least three
4686 // parameters to vary independently.
4687 // 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ...
4688 // 2. LLVM source: zextloadi8, anyextloadi8, ...
4689 // 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ...
4691 // The biggest problem turns out to be the address-generation variable. At the
4692 // point of instantiation we need to produce two DAGs, one for the pattern and
4693 // one for the instruction. Doing this at the lowest level of classes doesn't
4696 // Consider the simple uimm12 addressing mode, and the desire to match both (add
4697 // GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the
4698 // instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or
4699 // "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this
4700 // operation, and PatFrags are for selection not output.
4702 // As a result, the address-generation patterns are the final
4703 // instantiations. However, we do still need to vary the operand for the address
4704 // further down (At the point we're deciding A64WrapperSmall, we don't know
4705 // the memory width of the operation).
4707 //===------------------------------
4708 // 1. Basic infrastructural defs
4709 //===------------------------------
4711 // First, some simple classes for !foreach and !subst to use:
4722 // You can't use !subst on an actual immediate, but you *can* use it on an
4723 // operand record that happens to match a single immediate. So we do.
4724 def imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>;
4725 def imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>;
4726 def imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>;
4727 def imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>;
4728 def imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>;
4730 // If the low bits of a pointer are known to be 0 then an "or" is just as good
4731 // as addition for computing an offset. This fragment forwards that check for
4733 def add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),
4735 return CurDAG->isBaseWithConstantOffset(SDValue(N, 0));
4738 // Load/store (unsigned immediate) operations with relocations against global
4739 // symbols (for lo12) are only valid if those symbols have correct alignment
4740 // (since the immediate offset is divided by the access scale, it can't have a
4743 // The guaranteed alignment is provided as part of the WrapperSmall
4744 // operation, and checked against one of these.
4745 def any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>;
4746 def min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>;
4747 def min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>;
4748 def min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>;
4749 def min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>;
4751 // "Normal" load/store instructions can be used on atomic operations, provided
4752 // the ordering parameter is at most "monotonic". Anything above that needs
4753 // special handling with acquire/release instructions.
4754 class simple_load<PatFrag base>
4755 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4756 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4759 def atomic_load_simple_i8 : simple_load<atomic_load_8>;
4760 def atomic_load_simple_i16 : simple_load<atomic_load_16>;
4761 def atomic_load_simple_i32 : simple_load<atomic_load_32>;
4762 def atomic_load_simple_i64 : simple_load<atomic_load_64>;
4764 class simple_store<PatFrag base>
4765 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4766 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4769 def atomic_store_simple_i8 : simple_store<atomic_store_8>;
4770 def atomic_store_simple_i16 : simple_store<atomic_store_16>;
4771 def atomic_store_simple_i32 : simple_store<atomic_store_32>;
4772 def atomic_store_simple_i64 : simple_store<atomic_store_64>;
4774 //===------------------------------
4775 // 2. UImm12 and SImm9
4776 //===------------------------------
4778 // These instructions have two operands providing the address so they can be
4779 // treated similarly for most purposes.
4781 //===------------------------------
4782 // 2.1 Base patterns covering extend/truncate semantics
4783 //===------------------------------
4785 // Atomic patterns can be shared between integer operations of all sizes, a
4786 // quick multiclass here allows reuse.
4787 multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4788 dag Offset, dag address, ValueType transty,
4790 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4791 (LOAD Base, Offset)>;
4793 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
4794 (STORE $Rt, Base, Offset)>;
4797 // Instructions accessing a memory chunk smaller than a register (or, in a
4798 // pinch, the same size) have a characteristic set of patterns they want to
4799 // match: extending loads and truncating stores. This class deals with the
4800 // sign-neutral version of those patterns.
4802 // It will be instantiated across multiple addressing-modes.
4803 multiclass ls_small_pats<Instruction LOAD, Instruction STORE,
4804 dag Base, dag Offset,
4805 dag address, ValueType sty>
4806 : ls_atomic_pats<LOAD, STORE, Base, Offset, address, i32, sty> {
4807 def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>;
4809 def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>;
4811 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4812 // register was actually set.
4813 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4814 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4816 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
4817 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4819 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
4820 (STORE $Rt, Base, Offset)>;
4822 // For truncating store from 64-bits, we have to manually tell LLVM to
4823 // ignore the high bits of the x register.
4824 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
4825 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
4828 // Next come patterns for sign-extending loads.
4829 multiclass load_signed_pats<string T, string U, dag Base, dag Offset,
4830 dag address, ValueType sty> {
4831 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
4832 (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>;
4834 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
4835 (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>;
4839 // and finally "natural-width" loads and stores come next.
4840 multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4841 dag Offset, dag address, ValueType sty> {
4842 def : Pat<(sty (load address)), (LOAD Base, Offset)>;
4843 def : Pat<(store sty:$Rt, address), (STORE $Rt, Base, Offset)>;
4846 // Integer operations also get atomic instructions to select for.
4847 multiclass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4848 dag Offset, dag address, ValueType sty>
4849 : ls_neutral_pats<LOAD, STORE, Base, Offset, address, sty>,
4850 ls_atomic_pats<LOAD, STORE, Base, Offset, address, sty, sty>;
4852 //===------------------------------
4853 // 2.2. Addressing-mode instantiations
4854 //===------------------------------
4856 multiclass uimm12_pats<dag address, dag Base, dag Offset> {
4857 defm : ls_small_pats<LS8_LDR, LS8_STR, Base,
4858 !foreach(decls.pattern, Offset,
4859 !subst(OFFSET, byte_uimm12, decls.pattern)),
4860 !foreach(decls.pattern, address,
4861 !subst(OFFSET, byte_uimm12,
4862 !subst(ALIGN, any_align, decls.pattern))),
4864 defm : ls_small_pats<LS16_LDR, LS16_STR, Base,
4865 !foreach(decls.pattern, Offset,
4866 !subst(OFFSET, hword_uimm12, decls.pattern)),
4867 !foreach(decls.pattern, address,
4868 !subst(OFFSET, hword_uimm12,
4869 !subst(ALIGN, min_align2, decls.pattern))),
4871 defm : ls_small_pats<LS32_LDR, LS32_STR, Base,
4872 !foreach(decls.pattern, Offset,
4873 !subst(OFFSET, word_uimm12, decls.pattern)),
4874 !foreach(decls.pattern, address,
4875 !subst(OFFSET, word_uimm12,
4876 !subst(ALIGN, min_align4, decls.pattern))),
4879 defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base,
4880 !foreach(decls.pattern, Offset,
4881 !subst(OFFSET, word_uimm12, decls.pattern)),
4882 !foreach(decls.pattern, address,
4883 !subst(OFFSET, word_uimm12,
4884 !subst(ALIGN, min_align4, decls.pattern))),
4887 defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base,
4888 !foreach(decls.pattern, Offset,
4889 !subst(OFFSET, dword_uimm12, decls.pattern)),
4890 !foreach(decls.pattern, address,
4891 !subst(OFFSET, dword_uimm12,
4892 !subst(ALIGN, min_align8, decls.pattern))),
4895 defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base,
4896 !foreach(decls.pattern, Offset,
4897 !subst(OFFSET, hword_uimm12, decls.pattern)),
4898 !foreach(decls.pattern, address,
4899 !subst(OFFSET, hword_uimm12,
4900 !subst(ALIGN, min_align2, decls.pattern))),
4903 defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base,
4904 !foreach(decls.pattern, Offset,
4905 !subst(OFFSET, word_uimm12, decls.pattern)),
4906 !foreach(decls.pattern, address,
4907 !subst(OFFSET, word_uimm12,
4908 !subst(ALIGN, min_align4, decls.pattern))),
4911 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
4912 !foreach(decls.pattern, Offset,
4913 !subst(OFFSET, dword_uimm12, decls.pattern)),
4914 !foreach(decls.pattern, address,
4915 !subst(OFFSET, dword_uimm12,
4916 !subst(ALIGN, min_align8, decls.pattern))),
4919 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
4920 !foreach(decls.pattern, Offset,
4921 !subst(OFFSET, qword_uimm12, decls.pattern)),
4922 !foreach(decls.pattern, address,
4923 !subst(OFFSET, qword_uimm12,
4924 !subst(ALIGN, min_align16, decls.pattern))),
4927 defm : load_signed_pats<"B", "", Base,
4928 !foreach(decls.pattern, Offset,
4929 !subst(OFFSET, byte_uimm12, decls.pattern)),
4930 !foreach(decls.pattern, address,
4931 !subst(OFFSET, byte_uimm12,
4932 !subst(ALIGN, any_align, decls.pattern))),
4935 defm : load_signed_pats<"H", "", Base,
4936 !foreach(decls.pattern, Offset,
4937 !subst(OFFSET, hword_uimm12, decls.pattern)),
4938 !foreach(decls.pattern, address,
4939 !subst(OFFSET, hword_uimm12,
4940 !subst(ALIGN, min_align2, decls.pattern))),
4943 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
4944 !subst(OFFSET, word_uimm12,
4945 !subst(ALIGN, min_align4, decls.pattern)))),
4946 (LDRSWx Base, !foreach(decls.pattern, Offset,
4947 !subst(OFFSET, word_uimm12, decls.pattern)))>;
4950 // Straightforward patterns of last resort: a pointer with or without an
4951 // appropriate offset.
4952 defm : uimm12_pats<(i64 i64:$Rn), (i64 i64:$Rn), (i64 0)>;
4953 defm : uimm12_pats<(add i64:$Rn, OFFSET:$UImm12),
4954 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
4956 // The offset could be hidden behind an "or", of course:
4957 defm : uimm12_pats<(add_like_or i64:$Rn, OFFSET:$UImm12),
4958 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
4960 // Global addresses under the small-absolute model should use these
4961 // instructions. There are ELF relocations specifically for it.
4962 defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN),
4963 (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>;
4965 defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12,
4967 (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>;
4969 // External symbols that make it this far should also get standard relocations.
4970 defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12,
4972 (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>;
4974 defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
4975 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
4977 // We also want to use uimm12 instructions for local variables at the moment.
4978 def tframeindex_XFORM : SDNodeXForm<frameindex, [{
4979 int FI = cast<FrameIndexSDNode>(N)->getIndex();
4980 return CurDAG->getTargetFrameIndex(FI, MVT::i64);
4983 defm : uimm12_pats<(i64 frameindex:$Rn),
4984 (tframeindex_XFORM tframeindex:$Rn), (i64 0)>;
4986 // These can be much simpler than uimm12 because we don't to change the operand
4987 // type (e.g. LDURB and LDURH take the same operands).
4988 multiclass simm9_pats<dag address, dag Base, dag Offset> {
4989 defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>;
4990 defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>;
4992 defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address, i32>;
4993 defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address, i64>;
4995 defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address, f16>;
4996 defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address, f32>;
4997 defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address, f64>;
4998 defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address,
5001 def : Pat<(i64 (zextloadi32 address)),
5002 (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>;
5004 def : Pat<(truncstorei32 i64:$Rt, address),
5005 (LS32_STUR (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
5007 defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>;
5008 defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>;
5009 def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>;
5012 defm : simm9_pats<(add i64:$Rn, simm9:$SImm9),
5013 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
5015 defm : simm9_pats<(add_like_or i64:$Rn, simm9:$SImm9),
5016 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
5019 //===------------------------------
5020 // 3. Register offset patterns
5021 //===------------------------------
5023 // Atomic patterns can be shared between integer operations of all sizes, a
5024 // quick multiclass here allows reuse.
5025 multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
5026 dag Offset, dag Extend, dag address,
5027 ValueType transty, ValueType sty> {
5028 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
5029 (LOAD Base, Offset, Extend)>;
5031 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
5032 (STORE $Rt, Base, Offset, Extend)>;
5035 // The register offset instructions take three operands giving the instruction,
5036 // and have an annoying split between instructions where Rm is 32-bit and
5037 // 64-bit. So we need a special hierarchy to describe them. Other than that the
5038 // same operations should be supported as for simm9 and uimm12 addressing.
5040 multiclass ro_small_pats<Instruction LOAD, Instruction STORE,
5041 dag Base, dag Offset, dag Extend,
5042 dag address, ValueType sty>
5043 : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, i32, sty> {
5044 def : Pat<(!cast<SDNode>(zextload # sty) address),
5045 (LOAD Base, Offset, Extend)>;
5047 def : Pat<(!cast<SDNode>(extload # sty) address),
5048 (LOAD Base, Offset, Extend)>;
5050 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
5051 // register was actually set.
5052 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
5053 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
5055 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
5056 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
5058 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
5059 (STORE $Rt, Base, Offset, Extend)>;
5061 // For truncating store from 64-bits, we have to manually tell LLVM to
5062 // ignore the high bits of the x register.
5063 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
5064 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset, Extend)>;
5068 // Next come patterns for sign-extending loads.
5069 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
5070 dag address, ValueType sty> {
5071 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
5072 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
5073 Base, Offset, Extend)>;
5075 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
5076 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
5077 Base, Offset, Extend)>;
5080 // and finally "natural-width" loads and stores come next.
5081 multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE,
5082 dag Base, dag Offset, dag Extend, dag address,
5084 def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>;
5085 def : Pat<(store sty:$Rt, address),
5086 (STORE $Rt, Base, Offset, Extend)>;
5089 multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE,
5090 dag Base, dag Offset, dag Extend, dag address,
5092 : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, sty>,
5093 ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, sty, sty>;
5095 multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset,
5097 defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"),
5098 !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"),
5099 Base, Offset, Extend,
5100 !foreach(decls.pattern, address,
5101 !subst(SHIFT, imm_eq0, decls.pattern)),
5103 defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"),
5104 !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"),
5105 Base, Offset, Extend,
5106 !foreach(decls.pattern, address,
5107 !subst(SHIFT, imm_eq1, decls.pattern)),
5109 defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5110 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5111 Base, Offset, Extend,
5112 !foreach(decls.pattern, address,
5113 !subst(SHIFT, imm_eq2, decls.pattern)),
5116 defm : ro_int_neutral_pats<
5117 !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5118 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5119 Base, Offset, Extend,
5120 !foreach(decls.pattern, address,
5121 !subst(SHIFT, imm_eq2, decls.pattern)),
5124 defm : ro_int_neutral_pats<
5125 !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
5126 !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
5127 Base, Offset, Extend,
5128 !foreach(decls.pattern, address,
5129 !subst(SHIFT, imm_eq3, decls.pattern)),
5132 defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"),
5133 !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"),
5134 Base, Offset, Extend,
5135 !foreach(decls.pattern, address,
5136 !subst(SHIFT, imm_eq1, decls.pattern)),
5139 defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"),
5140 !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"),
5141 Base, Offset, Extend,
5142 !foreach(decls.pattern, address,
5143 !subst(SHIFT, imm_eq2, decls.pattern)),
5146 defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"),
5147 !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"),
5148 Base, Offset, Extend,
5149 !foreach(decls.pattern, address,
5150 !subst(SHIFT, imm_eq3, decls.pattern)),
5153 defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"),
5154 !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"),
5155 Base, Offset, Extend,
5156 !foreach(decls.pattern, address,
5157 !subst(SHIFT, imm_eq4, decls.pattern)),
5160 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,
5161 !foreach(decls.pattern, address,
5162 !subst(SHIFT, imm_eq0, decls.pattern)),
5165 defm : ro_signed_pats<"H", Rm, Base, Offset, Extend,
5166 !foreach(decls.pattern, address,
5167 !subst(SHIFT, imm_eq1, decls.pattern)),
5170 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
5171 !subst(SHIFT, imm_eq2, decls.pattern))),
5172 (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset")
5173 Base, Offset, Extend)>;
5177 // Finally we're in a position to tell LLVM exactly what addresses are reachable
5178 // using register-offset instructions. Essentially a base plus a possibly
5179 // extended, possibly shifted (by access size) offset.
5181 defm : regoff_pats<"Wm", (add i64:$Rn, (sext i32:$Rm)),
5182 (i64 i64:$Rn), (i32 i32:$Rm), (i64 6)>;
5184 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (sext i32:$Rm), SHIFT)),
5185 (i64 i64:$Rn), (i32 i32:$Rm), (i64 7)>;
5187 defm : regoff_pats<"Wm", (add i64:$Rn, (zext i32:$Rm)),
5188 (i64 i64:$Rn), (i32 i32:$Rm), (i64 2)>;
5190 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (zext i32:$Rm), SHIFT)),
5191 (i64 i64:$Rn), (i32 i32:$Rm), (i64 3)>;
5193 defm : regoff_pats<"Xm", (add i64:$Rn, i64:$Rm),
5194 (i64 i64:$Rn), (i64 i64:$Rm), (i64 2)>;
5196 defm : regoff_pats<"Xm", (add i64:$Rn, (shl i64:$Rm, SHIFT)),
5197 (i64 i64:$Rn), (i64 i64:$Rm), (i64 3)>;
5199 //===----------------------------------------------------------------------===//
5200 // Advanced SIMD (NEON) Support
5203 include "AArch64InstrNEON.td"