1 //===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 scalar instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "AArch64InstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Target-specific ISD nodes and profiles
18 //===----------------------------------------------------------------------===//
20 def SDT_A64ret : SDTypeProfile<0, 0, []>;
21 def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain,
25 // (ins NZCV, Condition, Dest)
26 def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>;
27 def A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>;
29 // (outs Result), (ins NZCV, IfTrue, IfFalse, Condition)
30 def SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>,
33 def A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>;
35 // (outs NZCV), (ins LHS, RHS, Condition)
36 def SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
38 def A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>;
41 // (outs GPR64), (ins)
42 def A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
44 // A64 compares don't care about the cond really (they set all flags) so a
45 // simple binary operator is useful.
46 def A64cmp : PatFrag<(ops node:$lhs, node:$rhs),
47 (A64setcc node:$lhs, node:$rhs, cond)>;
50 // When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN
51 // instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C
52 // and V flags can be set differently by this operation. It comes down to
53 // whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are
54 // then everything is fine. If not then the optimization is wrong. Thus general
55 // comparisons are only valid if op2 != 0.
57 // So, finally, the only LLVM-native comparisons that don't mention C and V are
58 // SETEQ and SETNE. They're the only ones we can safely use CMN for in the
59 // absence of information about op2.
60 def equality_cond : PatLeaf<(cond), [{
61 return N->get() == ISD::SETEQ || N->get() == ISD::SETNE;
64 def A64cmn : PatFrag<(ops node:$lhs, node:$rhs),
65 (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>;
67 // There are two layers of indirection here, driven by the following
69 // + TableGen does not know CodeModel or Reloc so that decision should be
70 // made for a variable/address at ISelLowering.
71 // + The output of ISelLowering should be selectable (hence the Wrapper,
72 // rather than a bare target opcode)
73 def SDTAArch64Wrapper : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
78 def A64WrapperSmall : SDNode<"AArch64ISD::WrapperSmall", SDTAArch64Wrapper>;
81 def SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
82 def A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad,
86 // (A64BFI LHS, RHS, LSB, Width)
87 def SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
92 def A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>;
94 // (A64EXTR HiReg, LoReg, LSB)
95 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
97 def A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
99 // (A64[SU]BFX Field, ImmR, ImmS).
101 // Note that ImmR and ImmS are already encoded for the actual instructions. The
102 // more natural LSB and Width mix together to form ImmR and ImmS, something
103 // which TableGen can't handle.
104 def SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>;
105 def A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>;
107 def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>;
109 //===----------------------------------------------------------------------===//
110 // Call sequence pseudo-instructions
111 //===----------------------------------------------------------------------===//
114 def SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
115 def AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
118 def AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call,
119 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
121 // The TLSDESCCALL node is a variant call which goes to an indirectly calculated
122 // destination but needs a relocation against a fixed symbol. As such it has two
123 // certain operands: the callee and the relocated variable.
125 // The TLS ABI only allows it to be selected to a BLR instructin (with
126 // appropriate relocation).
127 def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
129 def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall,
130 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
134 def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>;
135 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart,
136 [SDNPHasChain, SDNPOutGlue]>;
138 def SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>;
139 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
144 // These pseudo-instructions have special semantics by virtue of being passed to
145 // the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by
146 // LowerCall to (in our case) tell the back-end about stack adjustments for
147 // arguments passed on the stack. Here we select those markers to
148 // pseudo-instructions which explicitly set the stack, and finally in the
149 // RegisterInfo we convert them to a true stack adjustment.
150 let Defs = [XSP], Uses = [XSP] in {
151 def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt),
152 [(AArch64callseq_start timm:$amt)]>;
154 def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2),
155 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
158 //===----------------------------------------------------------------------===//
159 // Atomic operation pseudo-instructions
160 //===----------------------------------------------------------------------===//
162 // These get selected from C++ code as a pretty much direct translation from the
163 // generic DAG nodes. The one exception is the AtomicOrdering is added as an
164 // operand so that the eventual lowering can make use of it and choose
165 // acquire/release operations when required.
167 let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in {
168 multiclass AtomicSizes {
169 def _I8 : PseudoInst<(outs GPR32:$dst),
170 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
171 def _I16 : PseudoInst<(outs GPR32:$dst),
172 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
173 def _I32 : PseudoInst<(outs GPR32:$dst),
174 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
175 def _I64 : PseudoInst<(outs GPR64:$dst),
176 (ins GPR64xsp:$ptr, GPR64:$incr, i32imm:$ordering), []>;
180 defm ATOMIC_LOAD_ADD : AtomicSizes;
181 defm ATOMIC_LOAD_SUB : AtomicSizes;
182 defm ATOMIC_LOAD_AND : AtomicSizes;
183 defm ATOMIC_LOAD_OR : AtomicSizes;
184 defm ATOMIC_LOAD_XOR : AtomicSizes;
185 defm ATOMIC_LOAD_NAND : AtomicSizes;
186 defm ATOMIC_SWAP : AtomicSizes;
187 let Defs = [NZCV] in {
188 // These operations need a CMP to calculate the correct value
189 defm ATOMIC_LOAD_MIN : AtomicSizes;
190 defm ATOMIC_LOAD_MAX : AtomicSizes;
191 defm ATOMIC_LOAD_UMIN : AtomicSizes;
192 defm ATOMIC_LOAD_UMAX : AtomicSizes;
195 class AtomicCmpSwap<RegisterClass GPRData>
196 : PseudoInst<(outs GPRData:$dst),
197 (ins GPR64xsp:$ptr, GPRData:$old, GPRData:$new,
198 i32imm:$ordering), []> {
199 let usesCustomInserter = 1;
206 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>;
207 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>;
208 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>;
209 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>;
211 //===----------------------------------------------------------------------===//
212 // Add-subtract (extended register) instructions
213 //===----------------------------------------------------------------------===//
214 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP
216 // The RHS of these operations is conceptually a sign/zero-extended
217 // register, optionally shifted left by 1-4. The extension can be a
218 // NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but
219 // must be specified with one exception:
221 // If one of the registers is sp/wsp then LSL is an alias for UXTW in
222 // 32-bit instructions and UXTX in 64-bit versions, the shift amount
223 // is not optional in that case (but can explicitly be 0), and the
224 // entire suffix can be skipped (e.g. "add sp, x3, x2").
226 multiclass extend_operands<string PREFIX, string Diag> {
227 def _asmoperand : AsmOperandClass {
229 let RenderMethod = "addRegExtendOperands";
230 let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">";
231 let DiagnosticType = "AddSubRegExtend" # Diag;
234 def _operand : Operand<i64>,
235 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> {
236 let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">";
237 let DecoderMethod = "DecodeRegExtendOperand";
238 let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand");
242 defm UXTB : extend_operands<"UXTB", "Small">;
243 defm UXTH : extend_operands<"UXTH", "Small">;
244 defm UXTW : extend_operands<"UXTW", "Small">;
245 defm UXTX : extend_operands<"UXTX", "Large">;
246 defm SXTB : extend_operands<"SXTB", "Small">;
247 defm SXTH : extend_operands<"SXTH", "Small">;
248 defm SXTW : extend_operands<"SXTW", "Small">;
249 defm SXTX : extend_operands<"SXTX", "Large">;
251 def LSL_extasmoperand : AsmOperandClass {
252 let Name = "RegExtendLSL";
253 let RenderMethod = "addRegExtendOperands";
254 let DiagnosticType = "AddSubRegExtendLarge";
257 def LSL_extoperand : Operand<i64> {
258 let ParserMatchClass = LSL_extasmoperand;
262 // The patterns for various sign-extensions are a little ugly and
263 // non-uniform because everything has already been promoted to the
264 // legal i64 and i32 types. We'll wrap the various variants up in a
265 // class for use later.
267 dag uxtb; dag uxth; dag uxtw; dag uxtx;
268 dag sxtb; dag sxth; dag sxtw; dag sxtx;
273 def extends_to_i64 : extend_types {
274 let uxtb = (and (anyext i32:$Rm), 255);
275 let uxth = (and (anyext i32:$Rm), 65535);
276 let uxtw = (zext i32:$Rm);
277 let uxtx = (i64 $Rm);
279 let sxtb = (sext_inreg (anyext i32:$Rm), i8);
280 let sxth = (sext_inreg (anyext i32:$Rm), i16);
281 let sxtw = (sext i32:$Rm);
282 let sxtx = (i64 $Rm);
289 def extends_to_i32 : extend_types {
290 let uxtb = (and i32:$Rm, 255);
291 let uxth = (and i32:$Rm, 65535);
292 let uxtw = (i32 i32:$Rm);
293 let uxtx = (i32 i32:$Rm);
295 let sxtb = (sext_inreg i32:$Rm, i8);
296 let sxth = (sext_inreg i32:$Rm, i16);
297 let sxtw = (i32 i32:$Rm);
298 let sxtx = (i32 i32:$Rm);
304 // Now, six of the extensions supported are easy and uniform: if the source size
305 // is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate
306 // those instructions in one block.
308 // The uxtx/sxtx could potentially be merged in, but three facts dissuaded me:
309 // + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would
311 // + Patterns are very different as well.
312 // + Passing different registers would be ugly (more fields in extend_types
313 // would probably be the best option).
314 multiclass addsub_exts<bit sf, bit op, bit S, string asmop,
315 SDPatternOperator opfrag,
316 dag outs, extend_types exts> {
317 def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000,
318 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
319 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
320 [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
322 def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001,
323 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
324 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
325 [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
327 def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010,
328 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
329 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
330 [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
333 def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100,
334 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
335 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
336 [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
338 def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101,
339 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
340 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
341 [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
343 def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110,
344 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
345 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
346 [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
350 // These two could be merge in with the above, but their patterns aren't really
351 // necessary and the naming-scheme would necessarily break:
352 multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag,
354 def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011,
356 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
357 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
358 [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))],
361 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
363 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),
364 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
365 [/* No Pattern: same as uxtx */],
369 multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {
370 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
372 (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
373 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
374 [/* No pattern: probably same as uxtw */],
377 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,
379 (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
380 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
381 [/* No Pattern: probably same as uxtw */],
385 class SetRD<RegisterClass RC, SDPatternOperator op>
386 : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>;
387 class SetNZCV<SDPatternOperator op>
388 : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>;
390 defm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
391 (outs GPR64xsp:$Rd), extends_to_i64>,
392 addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
393 (outs GPR64xsp:$Rd)>;
394 defm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>,
395 (outs GPR32wsp:$Rd), extends_to_i32>,
396 addsub_wxtx< 0b0, 0b0, "add\t$Rd, ",
397 (outs GPR32wsp:$Rd)>;
398 defm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
399 (outs GPR64xsp:$Rd), extends_to_i64>,
400 addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
401 (outs GPR64xsp:$Rd)>;
402 defm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>,
403 (outs GPR32wsp:$Rd), extends_to_i32>,
404 addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ",
405 (outs GPR32wsp:$Rd)>;
407 let Defs = [NZCV] in {
408 defm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
409 (outs GPR64:$Rd), extends_to_i64>,
410 addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
412 defm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>,
413 (outs GPR32:$Rd), extends_to_i32>,
414 addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ",
416 defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
417 (outs GPR64:$Rd), extends_to_i64>,
418 addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
420 defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>,
421 (outs GPR32:$Rd), extends_to_i32>,
422 addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ",
426 let Rd = 0b11111, isCompare = 1 in {
427 defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
428 (outs), extends_to_i64>,
429 addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
430 defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
431 (outs), extends_to_i32>,
432 addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>;
433 defm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
434 (outs), extends_to_i64>,
435 addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>;
436 defm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
437 (outs), extends_to_i32>,
438 addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>;
442 // Now patterns for the operation without a shift being needed. No patterns are
443 // created for uxtx/sxtx since they're non-uniform and it's expected that
444 // add/sub (shifted register) will handle those cases anyway.
445 multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop,
447 def : Pat<(nodeop exts.ty:$Rn, exts.uxtb),
448 (!cast<Instruction>(prefix # "w_uxtb") $Rn, $Rm, 0)>;
449 def : Pat<(nodeop exts.ty:$Rn, exts.uxth),
450 (!cast<Instruction>(prefix # "w_uxth") $Rn, $Rm, 0)>;
451 def : Pat<(nodeop exts.ty:$Rn, exts.uxtw),
452 (!cast<Instruction>(prefix # "w_uxtw") $Rn, $Rm, 0)>;
454 def : Pat<(nodeop exts.ty:$Rn, exts.sxtb),
455 (!cast<Instruction>(prefix # "w_sxtb") $Rn, $Rm, 0)>;
456 def : Pat<(nodeop exts.ty:$Rn, exts.sxth),
457 (!cast<Instruction>(prefix # "w_sxth") $Rn, $Rm, 0)>;
458 def : Pat<(nodeop exts.ty:$Rn, exts.sxtw),
459 (!cast<Instruction>(prefix # "w_sxtw") $Rn, $Rm, 0)>;
462 defm : addsubext_noshift_patterns<"ADDxx", add, extends_to_i64>;
463 defm : addsubext_noshift_patterns<"ADDww", add, extends_to_i32>;
464 defm : addsubext_noshift_patterns<"SUBxx", sub, extends_to_i64>;
465 defm : addsubext_noshift_patterns<"SUBww", sub, extends_to_i32>;
467 defm : addsubext_noshift_patterns<"CMNx", A64cmn, extends_to_i64>;
468 defm : addsubext_noshift_patterns<"CMNw", A64cmn, extends_to_i32>;
469 defm : addsubext_noshift_patterns<"CMPx", A64cmp, extends_to_i64>;
470 defm : addsubext_noshift_patterns<"CMPw", A64cmp, extends_to_i32>;
472 // An extend of "lsl #imm" is valid if and only if one of Rn and Rd is
473 // sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the
474 // operation. Also permitted in this case is complete omission of the argument,
475 // which implies "lsl #0".
476 multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd,
477 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
478 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
479 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
481 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"),
482 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
486 defm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
487 defm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
488 defm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>;
489 defm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>;
490 defm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
491 defm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
492 defm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>;
493 defm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>;
495 // Rd cannot be sp for flag-setting variants so only half of the aliases are
497 defm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>;
498 defm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>;
499 defm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>;
500 defm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>;
502 // CMP unfortunately has to be different because the instruction doesn't have a
504 multiclass cmp_lsl_aliases<string asmop, Instruction inst,
505 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
506 def : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
507 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
509 def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"),
510 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
513 defm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>;
514 defm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>;
515 defm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>;
516 defm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>;
518 //===----------------------------------------------------------------------===//
519 // Add-subtract (immediate) instructions
520 //===----------------------------------------------------------------------===//
521 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV
523 // These instructions accept a 12-bit unsigned immediate, optionally shifted
524 // left by 12 bits. Official assembly format specifies a 12 bit immediate with
525 // one of "", "LSL #0", "LSL #12" supplementary operands.
527 // There are surprisingly few ways to make this work with TableGen, so this
528 // implementation has separate instructions for the "LSL #0" and "LSL #12"
531 // If the MCInst retained a single combined immediate (which could be 0x123000,
532 // for example) then both components (imm & shift) would have to be delegated to
533 // a single assembly operand. This would entail a separate operand parser
534 // (because the LSL would have to live in the same AArch64Operand as the
535 // immediate to be accessible); assembly parsing is rather complex and
536 // error-prone C++ code.
538 // By splitting the immediate, we can delegate handling this optional operand to
539 // an InstAlias. Supporting functions to generate the correct MCInst are still
540 // required, but these are essentially trivial and parsing can remain generic.
542 // Rejected plans with rationale:
543 // ------------------------------
545 // In an ideal world you'de have two first class immediate operands (in
546 // InOperandList, specifying imm12 and shift). Unfortunately this is not
547 // selectable by any means I could discover.
549 // An Instruction with two MCOperands hidden behind a single entry in
550 // InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional,
551 // but required more C++ code to handle encoding/decoding. Parsing (the intended
552 // main beneficiary) ended up equally complex because of the optional nature of
555 // Attempting to circumvent the need for a custom OperandParser above by giving
556 // InstAliases without the "lsl #0" failed. add/sub could be accommodated but
557 // the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands
558 // should be parsed: there was no way to accommodate an "lsl #12".
560 let ParserMethod = "ParseImmWithLSLOperand",
561 RenderMethod = "addImmWithLSLOperands" in {
562 // Derived PredicateMethod fields are different for each
563 def addsubimm_lsl0_asmoperand : AsmOperandClass {
564 let Name = "AddSubImmLSL0";
565 // If an error is reported against this operand, instruction could also be a
567 let DiagnosticType = "AddSubSecondSource";
570 def addsubimm_lsl12_asmoperand : AsmOperandClass {
571 let Name = "AddSubImmLSL12";
572 let DiagnosticType = "AddSubSecondSource";
576 def shr_12_XFORM : SDNodeXForm<imm, [{
577 return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32);
580 def shr_12_neg_XFORM : SDNodeXForm<imm, [{
581 return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32);
584 def neg_XFORM : SDNodeXForm<imm, [{
585 return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32);
589 multiclass addsub_imm_operands<ValueType ty> {
590 let PrintMethod = "printAddSubImmLSL0Operand",
591 EncoderMethod = "getAddSubImmOpValue",
592 ParserMatchClass = addsubimm_lsl0_asmoperand in {
593 def _posimm_lsl0 : Operand<ty>,
594 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>;
595 def _negimm_lsl0 : Operand<ty>,
596 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }],
600 let PrintMethod = "printAddSubImmLSL12Operand",
601 EncoderMethod = "getAddSubImmOpValue",
602 ParserMatchClass = addsubimm_lsl12_asmoperand in {
603 def _posimm_lsl12 : Operand<ty>,
604 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }],
607 def _negimm_lsl12 : Operand<ty>,
608 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }],
613 // The add operands don't need any transformation
614 defm addsubimm_operand_i32 : addsub_imm_operands<i32>;
615 defm addsubimm_operand_i64 : addsub_imm_operands<i64>;
617 multiclass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift,
618 string asmop, string cmpasmop,
619 Operand imm_operand, Operand cmp_imm_operand,
620 RegisterClass GPR, RegisterClass GPRsp,
621 AArch64Reg ZR, ValueType Ty> {
622 // All registers for non-S variants allow SP
623 def _s : A64I_addsubimm<sf, op, 0b0, shift,
625 (ins GPRsp:$Rn, imm_operand:$Imm12),
626 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
627 [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],
631 // S variants can read SP but would write to ZR
632 def _S : A64I_addsubimm<sf, op, 0b1, shift,
634 (ins GPRsp:$Rn, imm_operand:$Imm12),
635 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
636 [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],
641 // Note that the pattern here for ADDS is subtle. Canonically CMP
642 // a, b becomes SUBS a, b. If b < 0 then this is equivalent to
643 // ADDS a, (-b). This is not true in general.
644 def _cmp : A64I_addsubimm<sf, op, 0b1, shift,
645 (outs), (ins GPRsp:$Rn, imm_operand:$Imm12),
646 !strconcat(cmpasmop, " $Rn, $Imm12"),
648 (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
657 multiclass addsubimm_shifts<string prefix, bit sf, bit op,
658 string asmop, string cmpasmop, string operand, string cmpoperand,
659 RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR,
661 defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00,
663 !cast<Operand>(operand # "_lsl0"),
664 !cast<Operand>(cmpoperand # "_lsl0"),
667 defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01,
669 !cast<Operand>(operand # "_lsl12"),
670 !cast<Operand>(cmpoperand # "_lsl12"),
674 defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn",
675 "addsubimm_operand_i32_posimm",
676 "addsubimm_operand_i32_negimm",
677 GPR32, GPR32wsp, WZR, i32>;
678 defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn",
679 "addsubimm_operand_i64_posimm",
680 "addsubimm_operand_i64_negimm",
681 GPR64, GPR64xsp, XZR, i64>;
682 defm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp",
683 "addsubimm_operand_i32_negimm",
684 "addsubimm_operand_i32_posimm",
685 GPR32, GPR32wsp, WZR, i32>;
686 defm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp",
687 "addsubimm_operand_i64_negimm",
688 "addsubimm_operand_i64_posimm",
689 GPR64, GPR64xsp, XZR, i64>;
691 multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> {
692 def _fromsp : InstAlias<"mov $Rd, $Rn",
693 (addop GPRsp:$Rd, SP:$Rn, 0),
696 def _tosp : InstAlias<"mov $Rd, $Rn",
697 (addop SP:$Rd, GPRsp:$Rn, 0),
701 // Recall Rxsp is a RegisterClass containing *just* xsp.
702 defm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>;
703 defm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>;
705 //===----------------------------------------------------------------------===//
706 // Add-subtract (shifted register) instructions
707 //===----------------------------------------------------------------------===//
708 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS
710 //===-------------------------------
711 // 1. The "shifed register" operands. Shared with logical insts.
712 //===-------------------------------
714 multiclass shift_operands<string prefix, string form> {
715 def _asmoperand_i32 : AsmOperandClass {
716 let Name = "Shift" # form # "i32";
717 let RenderMethod = "addShiftOperands";
718 let PredicateMethod = "isShift<A64SE::" # form # ", false>";
719 let DiagnosticType = "AddSubRegShift32";
722 // Note that the operand type is intentionally i64 because the DAGCombiner
723 // puts these into a canonical form.
724 def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
726 = !cast<AsmOperandClass>(prefix # "_asmoperand_i32");
727 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
728 let DecoderMethod = "Decode32BitShiftOperand";
731 def _asmoperand_i64 : AsmOperandClass {
732 let Name = "Shift" # form # "i64";
733 let RenderMethod = "addShiftOperands";
734 let PredicateMethod = "isShift<A64SE::" # form # ", true>";
735 let DiagnosticType = "AddSubRegShift64";
738 def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
740 = !cast<AsmOperandClass>(prefix # "_asmoperand_i64");
741 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
745 defm lsl_operand : shift_operands<"lsl_operand", "LSL">;
746 defm lsr_operand : shift_operands<"lsr_operand", "LSR">;
747 defm asr_operand : shift_operands<"asr_operand", "ASR">;
749 // Not used for add/sub, but defined here for completeness. The "logical
750 // (shifted register)" instructions *do* have an ROR variant.
751 defm ror_operand : shift_operands<"ror_operand", "ROR">;
753 //===-------------------------------
754 // 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions.
755 //===-------------------------------
757 // N.b. the commutable parameter is just !N. It will be first against the wall
758 // when the revolution comes.
759 multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable,
760 string asmop, SDPatternOperator opfrag, ValueType ty,
761 RegisterClass GPR, list<Register> defs> {
762 let isCommutable = commutable, Defs = defs in {
763 def _lsl : A64I_addsubshift<sf, op, s, 0b00,
765 (ins GPR:$Rn, GPR:$Rm,
766 !cast<Operand>("lsl_operand_" # ty):$Imm6),
767 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
768 [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
769 !cast<Operand>("lsl_operand_" # ty):$Imm6))
773 def _lsr : A64I_addsubshift<sf, op, s, 0b01,
775 (ins GPR:$Rn, GPR:$Rm,
776 !cast<Operand>("lsr_operand_" # ty):$Imm6),
777 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
778 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
779 !cast<Operand>("lsr_operand_" # ty):$Imm6))
783 def _asr : A64I_addsubshift<sf, op, s, 0b10,
785 (ins GPR:$Rn, GPR:$Rm,
786 !cast<Operand>("asr_operand_" # ty):$Imm6),
787 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
788 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
789 !cast<Operand>("asr_operand_" # ty):$Imm6))
795 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
796 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
799 def : Pat<(opfrag ty:$Rn, ty:$Rm),
800 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
803 multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable,
804 string asmop, SDPatternOperator opfrag,
805 list<Register> defs> {
806 defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s,
807 commutable, asmop, opfrag, i64, GPR64, defs>;
808 defm www : addsub_shifts<prefix # "www", 0b0, op, s,
809 commutable, asmop, opfrag, i32, GPR32, defs>;
813 defm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>;
814 defm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>;
816 defm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>;
817 defm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>;
819 //===-------------------------------
820 // 1. The NEG/NEGS aliases
821 //===-------------------------------
823 multiclass neg_alias<Instruction INST, RegisterClass GPR, Register ZR,
824 ValueType ty, Operand shift_operand, SDNode shiftop> {
825 def : InstAlias<"neg $Rd, $Rm, $Imm6",
826 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
828 def : Pat<(sub 0, (shiftop ty:$Rm, shift_operand:$Imm6)),
829 (INST ZR, $Rm, shift_operand:$Imm6)>;
832 defm : neg_alias<SUBwww_lsl, GPR32, WZR, i32, lsl_operand_i32, shl>;
833 defm : neg_alias<SUBwww_lsr, GPR32, WZR, i32, lsr_operand_i32, srl>;
834 defm : neg_alias<SUBwww_asr, GPR32, WZR, i32, asr_operand_i32, sra>;
835 def : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
836 def : Pat<(sub 0, i32:$Rm), (SUBwww_lsl WZR, $Rm, 0)>;
838 defm : neg_alias<SUBxxx_lsl, GPR64, XZR, i64, lsl_operand_i64, shl>;
839 defm : neg_alias<SUBxxx_lsr, GPR64, XZR, i64, lsr_operand_i64, srl>;
840 defm : neg_alias<SUBxxx_asr, GPR64, XZR, i64, asr_operand_i64, sra>;
841 def : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
842 def : Pat<(sub 0, i64:$Rm), (SUBxxx_lsl XZR, $Rm, 0)>;
844 // NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to
846 class negs_alias<Instruction INST, RegisterClass GPR,
847 Register ZR, Operand shift_operand, SDNode shiftop>
848 : InstAlias<"negs $Rd, $Rm, $Imm6",
849 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
851 def : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>;
852 def : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>;
853 def : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>;
854 def : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
856 def : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>;
857 def : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>;
858 def : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>;
859 def : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
861 //===-------------------------------
862 // 1. The CMP/CMN aliases
863 //===-------------------------------
865 multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable,
866 string asmop, SDPatternOperator opfrag, ValueType ty,
868 let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in {
869 def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00,
871 (ins GPR:$Rn, GPR:$Rm,
872 !cast<Operand>("lsl_operand_" # ty):$Imm6),
873 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
874 [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm,
875 !cast<Operand>("lsl_operand_" # ty):$Imm6))
879 def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01,
881 (ins GPR:$Rn, GPR:$Rm,
882 !cast<Operand>("lsr_operand_" # ty):$Imm6),
883 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
884 [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm,
885 !cast<Operand>("lsr_operand_" # ty):$Imm6))
889 def _asr : A64I_addsubshift<sf, op, 0b1, 0b10,
891 (ins GPR:$Rn, GPR:$Rm,
892 !cast<Operand>("asr_operand_" # ty):$Imm6),
893 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
894 [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm,
895 !cast<Operand>("asr_operand_" # ty):$Imm6))
901 : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
902 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
904 def : Pat<(opfrag ty:$Rn, ty:$Rm),
905 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
908 defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, i32, GPR32>;
909 defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, i64, GPR64>;
911 defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, i32, GPR32>;
912 defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, i64, GPR64>;
914 //===----------------------------------------------------------------------===//
915 // Add-subtract (with carry) instructions
916 //===----------------------------------------------------------------------===//
917 // Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS
919 multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> {
920 let Uses = [NZCV] in {
921 def www : A64I_addsubcarry<0b0, op, s, 0b000000,
922 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
923 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
926 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,
927 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
928 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
933 let isCommutable = 1 in {
934 defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">;
937 defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">;
939 let Defs = [NZCV] in {
940 let isCommutable = 1 in {
941 defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">;
944 defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">;
947 def : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>;
948 def : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
949 def : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>;
950 def : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
952 // Note that adde and sube can form a chain longer than two (e.g. for 256-bit
953 // addition). So the flag-setting instructions are appropriate.
954 def : Pat<(adde i32:$Rn, i32:$Rm), (ADCSwww $Rn, $Rm)>;
955 def : Pat<(adde i64:$Rn, i64:$Rm), (ADCSxxx $Rn, $Rm)>;
956 def : Pat<(sube i32:$Rn, i32:$Rm), (SBCSwww $Rn, $Rm)>;
957 def : Pat<(sube i64:$Rn, i64:$Rm), (SBCSxxx $Rn, $Rm)>;
959 //===----------------------------------------------------------------------===//
961 //===----------------------------------------------------------------------===//
962 // Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL,
965 // Because of the rather complicated nearly-overlapping aliases, the decoding of
966 // this range of instructions is handled manually. The architectural
967 // instructions are BFM, SBFM and UBFM but a disassembler should never produce
970 // In the end, the best option was to use BFM instructions for decoding under
971 // almost all circumstances, but to create aliasing *Instructions* for each of
972 // the canonical forms and specify a completely custom decoder which would
973 // substitute the correct MCInst as needed.
975 // This also simplifies instruction selection, parsing etc because the MCInsts
976 // have a shape that's closer to their use in code.
978 //===-------------------------------
979 // 1. The architectural BFM instructions
980 //===-------------------------------
982 def uimm5_asmoperand : AsmOperandClass {
984 let PredicateMethod = "isUImm<5>";
985 let RenderMethod = "addImmOperands";
986 let DiagnosticType = "UImm5";
989 def uimm6_asmoperand : AsmOperandClass {
991 let PredicateMethod = "isUImm<6>";
992 let RenderMethod = "addImmOperands";
993 let DiagnosticType = "UImm6";
996 def bitfield32_imm : Operand<i64>,
997 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> {
998 let ParserMatchClass = uimm5_asmoperand;
1000 let DecoderMethod = "DecodeBitfield32ImmOperand";
1004 def bitfield64_imm : Operand<i64>,
1005 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
1006 let ParserMatchClass = uimm6_asmoperand;
1008 // Default decoder works in 64-bit case: the 6-bit field can take any value.
1011 multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> {
1012 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1013 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1014 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1016 let DecoderMethod = "DecodeBitfieldInstruction";
1019 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1020 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1021 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1023 let DecoderMethod = "DecodeBitfieldInstruction";
1027 defm SBFM : A64I_bitfieldSizes<0b00, "sbfm">;
1028 defm UBFM : A64I_bitfieldSizes<0b10, "ubfm">;
1030 // BFM instructions modify the destination register rather than defining it
1033 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1034 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1035 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1036 let DecoderMethod = "DecodeBitfieldInstruction";
1037 let Constraints = "$src = $Rd";
1041 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1042 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1043 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1044 let DecoderMethod = "DecodeBitfieldInstruction";
1045 let Constraints = "$src = $Rd";
1049 //===-------------------------------
1050 // 2. Extend aliases to 64-bit dest
1051 //===-------------------------------
1053 // Unfortunately the extensions that end up as 64-bits cannot be handled by an
1054 // instruction alias: their syntax is (for example) "SXTB x0, w0", which needs
1055 // to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is
1056 // not capable of such a map as far as I'm aware
1058 // Note that these instructions are strictly more specific than the
1059 // BFM ones (in ImmR) so they can handle their own decoding.
1060 class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, ValueType dty,
1061 string asmop, bits<6> imms, dag pattern>
1062 : A64I_bitfield<sf, opc, sf,
1063 (outs GPRDest:$Rd), (ins GPR32:$Rn),
1064 !strconcat(asmop, "\t$Rd, $Rn"),
1065 [(set dty:$Rd, pattern)], NoItinerary> {
1066 let ImmR = 0b000000;
1070 // Signed extensions
1071 def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtb", 7,
1072 (sext_inreg (anyext i32:$Rn), i8)>;
1073 def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxtb", 7,
1074 (sext_inreg i32:$Rn, i8)>;
1075 def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxth", 15,
1076 (sext_inreg (anyext i32:$Rn), i16)>;
1077 def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxth", 15,
1078 (sext_inreg i32:$Rn, i16)>;
1079 def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtw", 31, (sext i32:$Rn)>;
1081 // Unsigned extensions
1082 def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxtb", 7,
1083 (and i32:$Rn, 255)>;
1084 def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxth", 15,
1085 (and i32:$Rn, 65535)>;
1087 // The 64-bit unsigned variants are not strictly architectural but recommended
1089 let isAsmParserOnly = 1 in {
1090 def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxtb", 7,
1091 (and (anyext i32:$Rn), 255)>;
1092 def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxth", 15,
1093 (and (anyext i32:$Rn), 65535)>;
1096 // Extra patterns for when the source register is actually 64-bits
1097 // too. There's no architectural difference here, it's just LLVM
1098 // shinanigans. There's no need for equivalent zero-extension patterns
1099 // because they'll already be caught by logical (immediate) matching.
1100 def : Pat<(sext_inreg i64:$Rn, i8),
1101 (SXTBxw (EXTRACT_SUBREG $Rn, sub_32))>;
1102 def : Pat<(sext_inreg i64:$Rn, i16),
1103 (SXTHxw (EXTRACT_SUBREG $Rn, sub_32))>;
1104 def : Pat<(sext_inreg i64:$Rn, i32),
1105 (SXTWxw (EXTRACT_SUBREG $Rn, sub_32))>;
1108 //===-------------------------------
1109 // 3. Aliases for ASR and LSR (the simple shifts)
1110 //===-------------------------------
1112 // These also handle their own decoding because ImmS being set makes
1113 // them take precedence over BFM.
1114 multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> {
1115 def wwi : A64I_bitfield<0b0, opc, 0b0,
1116 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
1117 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1118 [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))],
1123 def xxi : A64I_bitfield<0b1, opc, 0b1,
1124 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
1125 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1126 [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))],
1133 defm ASR : A64I_shift<0b00, "asr", sra>;
1134 defm LSR : A64I_shift<0b10, "lsr", srl>;
1136 //===-------------------------------
1137 // 4. Aliases for LSL
1138 //===-------------------------------
1140 // Unfortunately LSL and subsequent aliases are much more complicated. We need
1141 // to be able to say certain output instruction fields depend in a complex
1142 // manner on combinations of input assembly fields).
1144 // MIOperandInfo *might* have been able to do it, but at the cost of
1145 // significantly more C++ code.
1147 // N.b. contrary to usual practice these operands store the shift rather than
1148 // the machine bits in an MCInst. The complexity overhead of consistency
1149 // outweighed the benefits in this case (custom asmparser, printer and selection
1150 // vs custom encoder).
1151 def bitfield32_lsl_imm : Operand<i64>,
1152 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1153 let ParserMatchClass = uimm5_asmoperand;
1154 let EncoderMethod = "getBitfield32LSLOpValue";
1157 def bitfield64_lsl_imm : Operand<i64>,
1158 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1159 let ParserMatchClass = uimm6_asmoperand;
1160 let EncoderMethod = "getBitfield64LSLOpValue";
1163 class A64I_bitfield_lsl<bit sf, RegisterClass GPR, ValueType ty,
1165 : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),
1166 "lsl\t$Rd, $Rn, $FullImm",
1167 [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))],
1170 let ImmR = FullImm{5-0};
1171 let ImmS = FullImm{11-6};
1173 // No disassembler allowed because it would overlap with BFM which does the
1175 let isAsmParserOnly = 1;
1178 def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, i32, bitfield32_lsl_imm>;
1179 def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, i64, bitfield64_lsl_imm>;
1181 //===-------------------------------
1182 // 5. Aliases for bitfield extract instructions
1183 //===-------------------------------
1185 def bfx32_width_asmoperand : AsmOperandClass {
1186 let Name = "BFX32Width";
1187 let PredicateMethod = "isBitfieldWidth<32>";
1188 let RenderMethod = "addBFXWidthOperands";
1189 let DiagnosticType = "Width32";
1192 def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> {
1193 let PrintMethod = "printBFXWidthOperand";
1194 let ParserMatchClass = bfx32_width_asmoperand;
1197 def bfx64_width_asmoperand : AsmOperandClass {
1198 let Name = "BFX64Width";
1199 let PredicateMethod = "isBitfieldWidth<64>";
1200 let RenderMethod = "addBFXWidthOperands";
1201 let DiagnosticType = "Width64";
1204 def bfx64_width : Operand<i64> {
1205 let PrintMethod = "printBFXWidthOperand";
1206 let ParserMatchClass = bfx64_width_asmoperand;
1210 multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> {
1211 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1212 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1213 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1214 [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))],
1216 // As above, no disassembler allowed.
1217 let isAsmParserOnly = 1;
1220 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1221 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1222 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1223 [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))],
1225 // As above, no disassembler allowed.
1226 let isAsmParserOnly = 1;
1230 defm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>;
1231 defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>;
1233 // Again, variants based on BFM modify Rd so need it as an input too.
1234 def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1235 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1236 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1237 // As above, no disassembler allowed.
1238 let isAsmParserOnly = 1;
1239 let Constraints = "$src = $Rd";
1242 def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1243 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1244 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1245 // As above, no disassembler allowed.
1246 let isAsmParserOnly = 1;
1247 let Constraints = "$src = $Rd";
1250 // SBFX instructions can do a 1-instruction sign-extension of boolean values.
1251 def : Pat<(sext_inreg i64:$Rn, i1), (SBFXxxii $Rn, 0, 0)>;
1252 def : Pat<(sext_inreg i32:$Rn, i1), (SBFXwwii $Rn, 0, 0)>;
1253 def : Pat<(i64 (sext_inreg (anyext i32:$Rn), i1)),
1254 (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>;
1256 // UBFX makes sense as an implementation of a 64-bit zero-extension too. Could
1257 // use either 64-bit or 32-bit variant, but 32-bit might be more efficient.
1258 def : Pat<(zext i32:$Rn), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31),
1261 //===-------------------------------
1262 // 6. Aliases for bitfield insert instructions
1263 //===-------------------------------
1265 def bfi32_lsb_asmoperand : AsmOperandClass {
1266 let Name = "BFI32LSB";
1267 let PredicateMethod = "isUImm<5>";
1268 let RenderMethod = "addBFILSBOperands<32>";
1269 let DiagnosticType = "UImm5";
1272 def bfi32_lsb : Operand<i64>,
1273 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1274 let PrintMethod = "printBFILSBOperand<32>";
1275 let ParserMatchClass = bfi32_lsb_asmoperand;
1278 def bfi64_lsb_asmoperand : AsmOperandClass {
1279 let Name = "BFI64LSB";
1280 let PredicateMethod = "isUImm<6>";
1281 let RenderMethod = "addBFILSBOperands<64>";
1282 let DiagnosticType = "UImm6";
1285 def bfi64_lsb : Operand<i64>,
1286 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1287 let PrintMethod = "printBFILSBOperand<64>";
1288 let ParserMatchClass = bfi64_lsb_asmoperand;
1291 // Width verification is performed during conversion so width operand can be
1292 // shared between 32/64-bit cases. Still needed for the print method though
1293 // because ImmR encodes "width - 1".
1294 def bfi32_width_asmoperand : AsmOperandClass {
1295 let Name = "BFI32Width";
1296 let PredicateMethod = "isBitfieldWidth<32>";
1297 let RenderMethod = "addBFIWidthOperands";
1298 let DiagnosticType = "Width32";
1301 def bfi32_width : Operand<i64>,
1302 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> {
1303 let PrintMethod = "printBFIWidthOperand";
1304 let ParserMatchClass = bfi32_width_asmoperand;
1307 def bfi64_width_asmoperand : AsmOperandClass {
1308 let Name = "BFI64Width";
1309 let PredicateMethod = "isBitfieldWidth<64>";
1310 let RenderMethod = "addBFIWidthOperands";
1311 let DiagnosticType = "Width64";
1314 def bfi64_width : Operand<i64>,
1315 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> {
1316 let PrintMethod = "printBFIWidthOperand";
1317 let ParserMatchClass = bfi64_width_asmoperand;
1320 multiclass A64I_bitfield_insert<bits<2> opc, string asmop> {
1321 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1322 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1323 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1325 // As above, no disassembler allowed.
1326 let isAsmParserOnly = 1;
1329 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1330 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1331 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1333 // As above, no disassembler allowed.
1334 let isAsmParserOnly = 1;
1338 defm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">;
1339 defm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">;
1342 def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1343 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1344 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1345 // As above, no disassembler allowed.
1346 let isAsmParserOnly = 1;
1347 let Constraints = "$src = $Rd";
1350 def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1351 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1352 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1353 // As above, no disassembler allowed.
1354 let isAsmParserOnly = 1;
1355 let Constraints = "$src = $Rd";
1358 //===----------------------------------------------------------------------===//
1359 // Compare and branch (immediate)
1360 //===----------------------------------------------------------------------===//
1361 // Contains: CBZ, CBNZ
1363 class label_asmoperand<int width, int scale> : AsmOperandClass {
1364 let Name = "Label" # width # "_" # scale;
1365 let PredicateMethod = "isLabel<" # width # "," # scale # ">";
1366 let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">";
1367 let DiagnosticType = "Label";
1370 def label_wid19_scal4_asmoperand : label_asmoperand<19, 4>;
1372 // All conditional immediate branches are the same really: 19 signed bits scaled
1373 // by the instruction-size (4).
1374 def bcc_target : Operand<OtherVT> {
1375 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
1376 let ParserMatchClass = label_wid19_scal4_asmoperand;
1377 let PrintMethod = "printLabelOperand<19, 4>";
1378 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>";
1379 let OperandType = "OPERAND_PCREL";
1382 multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> {
1383 let isBranch = 1, isTerminator = 1 in {
1384 def x : A64I_cmpbr<0b1, op,
1386 (ins GPR64:$Rt, bcc_target:$Label),
1387 !strconcat(asmop,"\t$Rt, $Label"),
1388 [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],
1391 def w : A64I_cmpbr<0b0, op,
1393 (ins GPR32:$Rt, bcc_target:$Label),
1394 !strconcat(asmop,"\t$Rt, $Label"),
1395 [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],
1400 defm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{
1401 return Imm == A64CC::EQ;
1403 defm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{
1404 return Imm == A64CC::NE;
1407 //===----------------------------------------------------------------------===//
1408 // Conditional branch (immediate) instructions
1409 //===----------------------------------------------------------------------===//
1412 def cond_code_asmoperand : AsmOperandClass {
1413 let Name = "CondCode";
1414 let DiagnosticType = "CondCode";
1417 def cond_code : Operand<i32>, ImmLeaf<i32, [{
1418 return Imm >= 0 && Imm <= 15;
1420 let PrintMethod = "printCondCodeOperand";
1421 let ParserMatchClass = cond_code_asmoperand;
1424 def Bcc : A64I_condbr<0b0, 0b0, (outs),
1425 (ins cond_code:$Cond, bcc_target:$Label),
1426 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
1430 let isTerminator = 1;
1433 //===----------------------------------------------------------------------===//
1434 // Conditional compare (immediate) instructions
1435 //===----------------------------------------------------------------------===//
1436 // Contains: CCMN, CCMP
1438 def uimm4_asmoperand : AsmOperandClass {
1440 let PredicateMethod = "isUImm<4>";
1441 let RenderMethod = "addImmOperands";
1442 let DiagnosticType = "UImm4";
1445 def uimm4 : Operand<i32> {
1446 let ParserMatchClass = uimm4_asmoperand;
1449 def uimm5 : Operand<i32> {
1450 let ParserMatchClass = uimm5_asmoperand;
1453 // The only difference between this operand and the one for instructions like
1454 // B.cc is that it's parsed manually. The other get parsed implicitly as part of
1455 // the mnemonic handling.
1456 def cond_code_op_asmoperand : AsmOperandClass {
1457 let Name = "CondCodeOp";
1458 let RenderMethod = "addCondCodeOperands";
1459 let PredicateMethod = "isCondCode";
1460 let ParserMethod = "ParseCondCodeOperand";
1461 let DiagnosticType = "CondCode";
1464 def cond_code_op : Operand<i32> {
1465 let PrintMethod = "printCondCodeOperand";
1466 let ParserMatchClass = cond_code_op_asmoperand;
1469 class A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1470 : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),
1471 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
1472 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
1477 def CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">;
1478 def CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">;
1479 def CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">;
1480 def CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">;
1482 //===----------------------------------------------------------------------===//
1483 // Conditional compare (register) instructions
1484 //===----------------------------------------------------------------------===//
1485 // Contains: CCMN, CCMP
1487 class A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1488 : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1,
1490 (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
1491 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
1496 def CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">;
1497 def CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">;
1498 def CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">;
1499 def CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">;
1501 //===----------------------------------------------------------------------===//
1502 // Conditional select instructions
1503 //===----------------------------------------------------------------------===//
1504 // Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG
1506 // Condition code which is encoded as the inversion (semantically rather than
1507 // bitwise) in the instruction.
1508 def inv_cond_code_op_asmoperand : AsmOperandClass {
1509 let Name = "InvCondCodeOp";
1510 let RenderMethod = "addInvCondCodeOperands";
1511 let PredicateMethod = "isCondCode";
1512 let ParserMethod = "ParseCondCodeOperand";
1513 let DiagnosticType = "CondCode";
1516 def inv_cond_code_op : Operand<i32> {
1517 let ParserMatchClass = inv_cond_code_op_asmoperand;
1520 // Having a separate operand for the selectable use-case is debatable, but gives
1521 // consistency with cond_code.
1522 def inv_cond_XFORM : SDNodeXForm<imm, [{
1523 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue());
1524 return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32);
1528 : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>;
1531 multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
1532 SDPatternOperator select> {
1533 let Uses = [NZCV] in {
1534 def wwwc : A64I_condsel<0b0, op, 0b0, op2,
1536 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
1537 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1538 [(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
1542 def xxxc : A64I_condsel<0b1, op, 0b0, op2,
1544 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
1545 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1546 [(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
1552 : PatFrag<(ops node:$lhs, node:$rhs),
1553 (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>;
1555 class complex_select<SDPatternOperator opnode>
1556 : PatFrag<(ops node:$lhs, node:$rhs),
1557 (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>;
1560 defm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>;
1561 defm CSINC : A64I_condselSizes<0b0, 0b01, "csinc",
1562 complex_select<PatFrag<(ops node:$val),
1563 (add node:$val, 1)>>>;
1564 defm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>;
1565 defm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>;
1567 // Now the instruction aliases, which fit nicely into LLVM's model:
1569 def : InstAlias<"cset $Rd, $Cond",
1570 (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1571 def : InstAlias<"cset $Rd, $Cond",
1572 (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1573 def : InstAlias<"csetm $Rd, $Cond",
1574 (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1575 def : InstAlias<"csetm $Rd, $Cond",
1576 (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1577 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1578 (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1579 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1580 (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1581 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1582 (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1583 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1584 (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1585 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1586 (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1587 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1588 (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1590 // Finally some helper patterns.
1592 // For CSET (a.k.a. zero-extension of icmp)
1593 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1594 (CSINCwwwc WZR, WZR, cond_code:$Cond)>;
1595 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1596 (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>;
1598 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1599 (CSINCxxxc XZR, XZR, cond_code:$Cond)>;
1600 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1601 (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>;
1603 // For CSETM (a.k.a. sign-extension of icmp)
1604 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1605 (CSINVwwwc WZR, WZR, cond_code:$Cond)>;
1606 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1607 (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>;
1609 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1610 (CSINVxxxc XZR, XZR, cond_code:$Cond)>;
1611 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1612 (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>;
1614 // CINC, CINV and CNEG get dealt with automatically, which leaves the issue of
1615 // commutativity. The instructions are to complex for isCommutable to be used,
1616 // so we have to create the patterns manually:
1618 // No commutable pattern for CSEL since the commuted version is isomorphic.
1621 def :Pat<(A64select_cc NZCV, (add i32:$Rm, 1), i32:$Rn, inv_cond_code:$Cond),
1622 (CSINCwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1623 def :Pat<(A64select_cc NZCV, (add i64:$Rm, 1), i64:$Rn, inv_cond_code:$Cond),
1624 (CSINCxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1627 def :Pat<(A64select_cc NZCV, (not i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1628 (CSINVwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1629 def :Pat<(A64select_cc NZCV, (not i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1630 (CSINVxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1633 def :Pat<(A64select_cc NZCV, (ineg i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1634 (CSNEGwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1635 def :Pat<(A64select_cc NZCV, (ineg i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1636 (CSNEGxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1638 //===----------------------------------------------------------------------===//
1639 // Data Processing (1 source) instructions
1640 //===----------------------------------------------------------------------===//
1641 // Contains: RBIT, REV16, REV, REV32, CLZ, CLS.
1643 // We define an unary operator which always fails. We will use this to
1644 // define unary operators that cannot be matched.
1646 class A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop,
1647 list<dag> patterns, RegisterClass GPRrc,
1648 InstrItinClass itin>:
1653 !strconcat(asmop, "\t$Rd, $Rn"),
1659 multiclass A64I_dp_1src <bits<6> opcode, string asmop> {
1660 let hasSideEffects = 0 in {
1661 def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>;
1662 def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>;
1666 defm RBIT : A64I_dp_1src<0b000000, "rbit">;
1667 defm CLS : A64I_dp_1src<0b000101, "cls">;
1668 defm CLZ : A64I_dp_1src<0b000100, "clz">;
1670 def : Pat<(ctlz i32:$Rn), (CLZww $Rn)>;
1671 def : Pat<(ctlz i64:$Rn), (CLZxx $Rn)>;
1672 def : Pat<(ctlz_zero_undef i32:$Rn), (CLZww $Rn)>;
1673 def : Pat<(ctlz_zero_undef i64:$Rn), (CLZxx $Rn)>;
1675 def : Pat<(cttz i32:$Rn), (CLZww (RBITww $Rn))>;
1676 def : Pat<(cttz i64:$Rn), (CLZxx (RBITxx $Rn))>;
1677 def : Pat<(cttz_zero_undef i32:$Rn), (CLZww (RBITww $Rn))>;
1678 def : Pat<(cttz_zero_undef i64:$Rn), (CLZxx (RBITxx $Rn))>;
1681 def REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev",
1682 [(set i32:$Rd, (bswap i32:$Rn))],
1683 GPR32, NoItinerary>;
1684 def REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev",
1685 [(set i64:$Rd, (bswap i64:$Rn))],
1686 GPR64, NoItinerary>;
1687 def REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32",
1688 [(set i64:$Rd, (bswap (rotr i64:$Rn, (i64 32))))],
1689 GPR64, NoItinerary>;
1690 def REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16",
1691 [(set i32:$Rd, (bswap (rotr i32:$Rn, (i64 16))))],
1694 def REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>;
1696 //===----------------------------------------------------------------------===//
1697 // Data Processing (2 sources) instructions
1698 //===----------------------------------------------------------------------===//
1699 // Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL,
1703 class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns,
1704 RegisterClass GPRsp,
1705 InstrItinClass itin>:
1709 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
1711 (ins GPRsp:$Rn, GPRsp:$Rm),
1715 multiclass dp_2src_crc<bit c, string asmop> {
1716 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
1717 !strconcat(asmop, "b"), [], GPR32, NoItinerary>;
1718 def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1},
1719 !strconcat(asmop, "h"), [], GPR32, NoItinerary>;
1720 def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0},
1721 !strconcat(asmop, "w"), [], GPR32, NoItinerary>;
1722 def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
1723 !strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
1724 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
1728 multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
1729 def www : dp_2src_impl<0b0,
1733 (op i32:$Rn, (i64 (zext i32:$Rm))))],
1736 def xxx : dp_2src_impl<0b1,
1739 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1745 multiclass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> {
1746 def www : dp_2src_impl<0b0,
1749 [(set i32:$Rd, (op i32:$Rn, i32:$Rm))],
1752 def xxx : dp_2src_impl<0b1,
1755 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1760 // Here we define the data processing 2 source instructions.
1761 defm CRC32 : dp_2src_crc<0b0, "crc32">;
1762 defm CRC32C : dp_2src_crc<0b1, "crc32c">;
1764 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1765 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1767 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1768 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1769 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1770 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1772 // Extra patterns for an incoming 64-bit value for a 32-bit
1773 // operation. Since the LLVM operations are undefined (as in C) if the
1774 // RHS is out of range, it's perfectly permissible to discard the high
1775 // bits of the GPR64.
1776 def : Pat<(shl i32:$Rn, i64:$Rm),
1777 (LSLVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1778 def : Pat<(srl i32:$Rn, i64:$Rm),
1779 (LSRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1780 def : Pat<(sra i32:$Rn, i64:$Rm),
1781 (ASRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1782 def : Pat<(rotr i32:$Rn, i64:$Rm),
1783 (RORVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1785 // Here we define the aliases for the data processing 2 source instructions.
1786 def LSL_mnemonic : MnemonicAlias<"lslv", "lsl">;
1787 def LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">;
1788 def ASR_menmonic : MnemonicAlias<"asrv", "asr">;
1789 def ROR_menmonic : MnemonicAlias<"rorv", "ror">;
1791 //===----------------------------------------------------------------------===//
1792 // Data Processing (3 sources) instructions
1793 //===----------------------------------------------------------------------===//
1794 // Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH
1795 // + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL
1797 class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg,
1798 ValueType AccTy, RegisterClass SrcReg,
1799 string asmop, dag pattern>
1800 : A64I_dp3<sf, opcode,
1801 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
1802 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
1803 [(set AccTy:$Rd, pattern)], NoItinerary> {
1804 RegisterClass AccGPR = AccReg;
1805 RegisterClass SrcGPR = SrcReg;
1808 def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, i32, GPR32, "madd",
1809 (add i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1810 def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, i64, GPR64, "madd",
1811 (add i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1813 def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, i32, GPR32, "msub",
1814 (sub i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1815 def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, i64, GPR64, "msub",
1816 (sub i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1818 def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, i64, GPR32, "smaddl",
1819 (add i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1820 def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, i64, GPR32, "smsubl",
1821 (sub i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1823 def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, i64, GPR32, "umaddl",
1824 (add i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1825 def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, i64, GPR32, "umsubl",
1826 (sub i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1828 let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in {
1829 def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd),
1830 (ins GPR64:$Rn, GPR64:$Rm),
1831 "umulh\t$Rd, $Rn, $Rm",
1832 [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))],
1835 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
1836 (ins GPR64:$Rn, GPR64:$Rm),
1837 "smulh\t$Rd, $Rn, $Rm",
1838 [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))],
1842 multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,
1843 Register ZR, dag pattern> {
1844 def : InstAlias<asmop # " $Rd, $Rn, $Rm",
1845 (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
1847 def : Pat<pattern, (INST $Rn, $Rm, ZR)>;
1850 defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul i32:$Rn, i32:$Rm)>;
1851 defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul i64:$Rn, i64:$Rm)>;
1853 defm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR,
1854 (sub 0, (mul i32:$Rn, i32:$Rm))>;
1855 defm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR,
1856 (sub 0, (mul i64:$Rn, i64:$Rm))>;
1858 defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR,
1859 (mul (i64 (sext i32:$Rn)), (sext i32:$Rm))>;
1860 defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR,
1861 (sub 0, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1863 defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR,
1864 (mul (i64 (zext i32:$Rn)), (zext i32:$Rm))>;
1865 defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR,
1866 (sub 0, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1869 //===----------------------------------------------------------------------===//
1870 // Exception generation
1871 //===----------------------------------------------------------------------===//
1872 // Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3
1874 def uimm16_asmoperand : AsmOperandClass {
1875 let Name = "UImm16";
1876 let PredicateMethod = "isUImm<16>";
1877 let RenderMethod = "addImmOperands";
1878 let DiagnosticType = "UImm16";
1881 def uimm16 : Operand<i32> {
1882 let ParserMatchClass = uimm16_asmoperand;
1885 class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop>
1886 : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),
1887 !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {
1889 let isTerminator = 1;
1892 def SVCi : A64I_exceptImpl<0b000, 0b01, "svc">;
1893 def HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">;
1894 def SMCi : A64I_exceptImpl<0b000, 0b11, "smc">;
1895 def BRKi : A64I_exceptImpl<0b001, 0b00, "brk">;
1896 def HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">;
1898 def DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">;
1899 def DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">;
1900 def DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">;
1902 // The immediate is optional for the DCPS instructions, defaulting to 0.
1903 def : InstAlias<"dcps1", (DCPS1i 0)>;
1904 def : InstAlias<"dcps2", (DCPS2i 0)>;
1905 def : InstAlias<"dcps3", (DCPS3i 0)>;
1907 //===----------------------------------------------------------------------===//
1908 // Extract (immediate)
1909 //===----------------------------------------------------------------------===//
1910 // Contains: EXTR + alias ROR
1912 def EXTRwwwi : A64I_extract<0b0, 0b000, 0b0,
1914 (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB),
1915 "extr\t$Rd, $Rn, $Rm, $LSB",
1917 (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))],
1919 def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
1921 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
1922 "extr\t$Rd, $Rn, $Rm, $LSB",
1924 (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))],
1927 def : InstAlias<"ror $Rd, $Rs, $LSB",
1928 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;
1929 def : InstAlias<"ror $Rd, $Rs, $LSB",
1930 (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>;
1932 def : Pat<(rotr i32:$Rn, bitfield32_imm:$LSB),
1933 (EXTRwwwi $Rn, $Rn, bitfield32_imm:$LSB)>;
1934 def : Pat<(rotr i64:$Rn, bitfield64_imm:$LSB),
1935 (EXTRxxxi $Rn, $Rn, bitfield64_imm:$LSB)>;
1937 //===----------------------------------------------------------------------===//
1938 // Floating-point compare instructions
1939 //===----------------------------------------------------------------------===//
1940 // Contains: FCMP, FCMPE
1942 def fpzero_asmoperand : AsmOperandClass {
1943 let Name = "FPZero";
1944 let ParserMethod = "ParseFPImmOperand";
1945 let DiagnosticType = "FPZero";
1948 def fpz32 : Operand<f32>,
1949 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
1950 let ParserMatchClass = fpzero_asmoperand;
1951 let PrintMethod = "printFPZeroOperand";
1952 let DecoderMethod = "DecodeFPZeroOperand";
1955 def fpz64 : Operand<f64>,
1956 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
1957 let ParserMatchClass = fpzero_asmoperand;
1958 let PrintMethod = "printFPZeroOperand";
1959 let DecoderMethod = "DecodeFPZeroOperand";
1962 multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {
1963 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
1964 (outs), ins, "fcmp\t$Rn, $Rm", [pattern],
1969 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
1970 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> {
1975 defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm),
1976 (set NZCV, (A64cmp f32:$Rn, f32:$Rm))>;
1977 defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm),
1978 (set NZCV, (A64cmp f64:$Rn, f64:$Rm))>;
1980 // What would be Rm should be written as 0; note that even though it's called
1981 // "$Rm" here to fit in with the InstrFormats, it's actually an immediate.
1982 defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm),
1983 (set NZCV, (A64cmp f32:$Rn, fpz32:$Rm))>;
1985 defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm),
1986 (set NZCV, (A64cmp f64:$Rn, fpz64:$Rm))>;
1989 //===----------------------------------------------------------------------===//
1990 // Floating-point conditional compare instructions
1991 //===----------------------------------------------------------------------===//
1992 // Contains: FCCMP, FCCMPE
1994 class A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop>
1995 : A64I_fpccmp<0b0, 0b0, type, op,
1997 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
1998 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
2003 def FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">;
2004 def FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">;
2005 def FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">;
2006 def FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">;
2008 //===----------------------------------------------------------------------===//
2009 // Floating-point conditional select instructions
2010 //===----------------------------------------------------------------------===//
2013 let Uses = [NZCV] in {
2014 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
2015 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
2016 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2018 (simple_select f32:$Rn, f32:$Rm))],
2022 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
2023 (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond),
2024 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2026 (simple_select f64:$Rn, f64:$Rm))],
2030 //===----------------------------------------------------------------------===//
2031 // Floating-point data-processing (1 source)
2032 //===----------------------------------------------------------------------===//
2033 // Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI].
2035 def FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val),
2036 [{ (void)N; return false; }]>;
2038 // First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d"
2039 // syntax. Default to no pattern because most are odd enough not to have one.
2040 multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr,
2041 SDPatternOperator opnode = FPNoUnop> {
2042 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
2043 !strconcat(asmstr, "\t$Rd, $Rn"),
2044 [(set f32:$Rd, (opnode f32:$Rn))],
2047 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
2048 !strconcat(asmstr, "\t$Rd, $Rn"),
2049 [(set f64:$Rd, (opnode f64:$Rn))],
2053 defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;
2054 defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;
2055 defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;
2056 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
2058 defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;
2059 defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;
2060 defm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>;
2061 defm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>;
2062 defm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">;
2063 defm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>;
2064 defm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>;
2066 // The FCVT instrucitons have different source and destination register-types,
2067 // but the fields are uniform everywhere a D-register (say) crops up. Package
2068 // this information in a Record.
2069 class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> {
2070 RegisterClass Class = rc;
2076 def FCVT16 : FCVTRegType<FPR16, 0b11, f16>;
2077 def FCVT32 : FCVTRegType<FPR32, 0b00, f32>;
2078 def FCVT64 : FCVTRegType<FPR64, 0b01, f64>;
2080 class A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode>
2081 : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0},
2082 {0,0,0,1, DestReg.t1, DestReg.t0},
2083 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
2085 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>;
2087 def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>;
2088 def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>;
2089 def FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>;
2090 def FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>;
2091 def FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>;
2092 def FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>;
2095 //===----------------------------------------------------------------------===//
2096 // Floating-point data-processing (2 sources) instructions
2097 //===----------------------------------------------------------------------===//
2098 // Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
2100 def FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs),
2101 [{ (void)N; return false; }]>;
2103 multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr,
2104 SDPatternOperator opnode> {
2105 def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode,
2107 (ins FPR32:$Rn, FPR32:$Rm),
2108 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2109 [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))],
2112 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
2114 (ins FPR64:$Rn, FPR64:$Rm),
2115 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2116 [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))],
2120 let isCommutable = 1 in {
2121 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
2122 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;
2124 // No patterns for these.
2125 defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>;
2126 defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>;
2127 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;
2128 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;
2130 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2131 PatFrag<(ops node:$lhs, node:$rhs),
2132 (fneg (fmul node:$lhs, node:$rhs))> >;
2135 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
2136 defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;
2138 //===----------------------------------------------------------------------===//
2139 // Floating-point data-processing (3 sources) instructions
2140 //===----------------------------------------------------------------------===//
2141 // Contains: FMADD, FMSUB, FNMADD, FNMSUB
2143 def fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2144 (fma (fneg node:$Rn), node:$Rm, node:$Ra)>;
2145 def fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2146 (fma node:$Rn, node:$Rm, (fneg node:$Ra))>;
2147 def fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2148 (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>;
2150 class A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT,
2151 bits<2> type, bit o1, bit o0, SDPatternOperator fmakind>
2152 : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd),
2153 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
2154 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
2155 [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))],
2158 def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
2159 def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;
2160 def FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>;
2161 def FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>;
2163 def FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>;
2164 def FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>;
2165 def FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>;
2166 def FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>;
2168 //===----------------------------------------------------------------------===//
2169 // Floating-point <-> fixed-point conversion instructions
2170 //===----------------------------------------------------------------------===//
2171 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2173 // #1-#32 allowed, encoded as "64 - <specified imm>
2174 def fixedpos_asmoperand_i32 : AsmOperandClass {
2175 let Name = "CVTFixedPos32";
2176 let RenderMethod = "addCVTFixedPosOperands";
2177 let PredicateMethod = "isCVTFixedPos<32>";
2178 let DiagnosticType = "CVTFixedPos32";
2181 // Also encoded as "64 - <specified imm>" but #1-#64 allowed.
2182 def fixedpos_asmoperand_i64 : AsmOperandClass {
2183 let Name = "CVTFixedPos64";
2184 let RenderMethod = "addCVTFixedPosOperands";
2185 let PredicateMethod = "isCVTFixedPos<64>";
2186 let DiagnosticType = "CVTFixedPos64";
2189 // We need the cartesian product of f32/f64 i32/i64 operands for
2191 // + Selection needs to use operands of correct floating type
2192 // + Assembly parsing and decoding depend on integer width
2193 class cvtfix_i32_op<ValueType FloatVT>
2195 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> {
2196 let ParserMatchClass = fixedpos_asmoperand_i32;
2197 let DecoderMethod = "DecodeCVT32FixedPosOperand";
2198 let PrintMethod = "printCVTFixedPosOperand";
2201 class cvtfix_i64_op<ValueType FloatVT>
2203 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> {
2204 let ParserMatchClass = fixedpos_asmoperand_i64;
2205 let PrintMethod = "printCVTFixedPosOperand";
2208 // Because of the proliferation of weird operands, it's not really
2209 // worth going for a multiclass here. Oh well.
2211 class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode,
2212 RegisterClass GPR, RegisterClass FPR,
2213 ValueType DstTy, ValueType SrcTy,
2214 Operand scale_op, string asmop, SDNode cvtop>
2215 : A64I_fpfixed<sf, 0b0, type, 0b11, opcode,
2216 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
2217 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2218 [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))],
2221 def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32,
2222 cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>;
2223 def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32, i64, f32,
2224 cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>;
2225 def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32, i32, f32,
2226 cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>;
2227 def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32, i64, f32,
2228 cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>;
2230 def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64, i32, f64,
2231 cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>;
2232 def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64, i64, f64,
2233 cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>;
2234 def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64, i32, f64,
2235 cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>;
2236 def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64, i64, f64,
2237 cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>;
2240 class A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode,
2241 RegisterClass FPR, RegisterClass GPR,
2242 ValueType DstTy, ValueType SrcTy,
2243 Operand scale_op, string asmop, SDNode cvtop>
2244 : A64I_fpfixed<sf, 0b0, type, 0b00, opcode,
2245 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
2246 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2247 [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))],
2250 def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32,
2251 cvtfix_i32_op<f32>, "scvtf", sint_to_fp>;
2252 def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64, f32, i64,
2253 cvtfix_i64_op<f32>, "scvtf", sint_to_fp>;
2254 def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32, f32, i32,
2255 cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>;
2256 def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64, f32, i64,
2257 cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>;
2258 def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32, f64, i32,
2259 cvtfix_i32_op<f64>, "scvtf", sint_to_fp>;
2260 def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64, f64, i64,
2261 cvtfix_i64_op<f64>, "scvtf", sint_to_fp>;
2262 def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32, f64, i32,
2263 cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>;
2264 def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64, f64, i64,
2265 cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>;
2267 //===----------------------------------------------------------------------===//
2268 // Floating-point <-> integer conversion instructions
2269 //===----------------------------------------------------------------------===//
2270 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2272 class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode,
2273 RegisterClass DestPR, RegisterClass SrcPR, string asmop>
2274 : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),
2275 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;
2277 multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {
2278 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
2279 GPR32, FPR32, asmop # "s">;
2280 def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0},
2281 GPR64, FPR32, asmop # "s">;
2282 def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1},
2283 GPR32, FPR32, asmop # "u">;
2284 def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1},
2285 GPR64, FPR32, asmop # "u">;
2287 def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0},
2288 GPR32, FPR64, asmop # "s">;
2289 def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0},
2290 GPR64, FPR64, asmop # "s">;
2291 def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1},
2292 GPR32, FPR64, asmop # "u">;
2293 def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1},
2294 GPR64, FPR64, asmop # "u">;
2297 defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">;
2298 defm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">;
2299 defm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">;
2300 defm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">;
2301 defm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">;
2303 def : Pat<(i32 (fp_to_sint f32:$Rn)), (FCVTZSws $Rn)>;
2304 def : Pat<(i64 (fp_to_sint f32:$Rn)), (FCVTZSxs $Rn)>;
2305 def : Pat<(i32 (fp_to_uint f32:$Rn)), (FCVTZUws $Rn)>;
2306 def : Pat<(i64 (fp_to_uint f32:$Rn)), (FCVTZUxs $Rn)>;
2307 def : Pat<(i32 (fp_to_sint f64:$Rn)), (FCVTZSwd $Rn)>;
2308 def : Pat<(i64 (fp_to_sint f64:$Rn)), (FCVTZSxd $Rn)>;
2309 def : Pat<(i32 (fp_to_uint f64:$Rn)), (FCVTZUwd $Rn)>;
2310 def : Pat<(i64 (fp_to_uint f64:$Rn)), (FCVTZUxd $Rn)>;
2312 multiclass A64I_inttofp<bit o0, string asmop> {
2313 def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>;
2314 def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>;
2315 def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>;
2316 def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>;
2319 defm S : A64I_inttofp<0b0, "scvtf">;
2320 defm U : A64I_inttofp<0b1, "ucvtf">;
2322 def : Pat<(f32 (sint_to_fp i32:$Rn)), (SCVTFsw $Rn)>;
2323 def : Pat<(f32 (sint_to_fp i64:$Rn)), (SCVTFsx $Rn)>;
2324 def : Pat<(f64 (sint_to_fp i32:$Rn)), (SCVTFdw $Rn)>;
2325 def : Pat<(f64 (sint_to_fp i64:$Rn)), (SCVTFdx $Rn)>;
2326 def : Pat<(f32 (uint_to_fp i32:$Rn)), (UCVTFsw $Rn)>;
2327 def : Pat<(f32 (uint_to_fp i64:$Rn)), (UCVTFsx $Rn)>;
2328 def : Pat<(f64 (uint_to_fp i32:$Rn)), (UCVTFdw $Rn)>;
2329 def : Pat<(f64 (uint_to_fp i64:$Rn)), (UCVTFdx $Rn)>;
2331 def FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">;
2332 def FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">;
2333 def FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">;
2334 def FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">;
2336 def : Pat<(i32 (bitconvert f32:$Rn)), (FMOVws $Rn)>;
2337 def : Pat<(f32 (bitconvert i32:$Rn)), (FMOVsw $Rn)>;
2338 def : Pat<(i64 (bitconvert f64:$Rn)), (FMOVxd $Rn)>;
2339 def : Pat<(f64 (bitconvert i64:$Rn)), (FMOVdx $Rn)>;
2341 def lane1_asmoperand : AsmOperandClass {
2343 let RenderMethod = "addImmOperands";
2344 let DiagnosticType = "Lane1";
2347 def lane1 : Operand<i32> {
2348 let ParserMatchClass = lane1_asmoperand;
2349 let PrintMethod = "printBareImmOperand";
2352 let DecoderMethod = "DecodeFMOVLaneInstruction" in {
2353 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
2354 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
2355 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;
2357 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,
2358 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),
2359 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>;
2362 def : InstAlias<"fmov $Rd, $Rn.2d[$Lane]",
2363 (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>;
2365 def : InstAlias<"fmov $Rd.2d[$Lane], $Rn",
2366 (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>;
2368 //===----------------------------------------------------------------------===//
2369 // Floating-point immediate instructions
2370 //===----------------------------------------------------------------------===//
2373 def fpimm_asmoperand : AsmOperandClass {
2374 let Name = "FMOVImm";
2375 let ParserMethod = "ParseFPImmOperand";
2376 let DiagnosticType = "FPImm";
2379 // The MCOperand for these instructions are the encoded 8-bit values.
2380 def SDXF_fpimm : SDNodeXForm<fpimm, [{
2382 A64Imms::isFPImm(N->getValueAPF(), Imm8);
2383 return CurDAG->getTargetConstant(Imm8, MVT::i32);
2386 class fmov_operand<ValueType FT>
2388 PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }],
2390 let PrintMethod = "printFPImmOperand";
2391 let ParserMatchClass = fpimm_asmoperand;
2394 def fmov32_operand : fmov_operand<f32>;
2395 def fmov64_operand : fmov_operand<f64>;
2397 class A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT,
2398 Operand fmov_operand>
2399 : A64I_fpimm<0b0, 0b0, type, 0b00000,
2401 (ins fmov_operand:$Imm8),
2403 [(set VT:$Rd, fmov_operand:$Imm8)],
2406 def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
2407 def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;
2409 //===----------------------------------------------------------------------===//
2410 // Load-register (literal) instructions
2411 //===----------------------------------------------------------------------===//
2412 // Contains: LDR, LDRSW, PRFM
2414 def ldrlit_label_asmoperand : AsmOperandClass {
2415 let Name = "LoadLitLabel";
2416 let RenderMethod = "addLabelOperands<19, 4>";
2417 let DiagnosticType = "Label";
2420 def ldrlit_label : Operand<i64> {
2421 let EncoderMethod = "getLoadLitLabelOpValue";
2423 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
2424 let PrintMethod = "printLabelOperand<19, 4>";
2425 let ParserMatchClass = ldrlit_label_asmoperand;
2426 let OperandType = "OPERAND_PCREL";
2429 // Various instructions take an immediate value (which can always be used),
2430 // where some numbers have a symbolic name to make things easier. These operands
2431 // and the associated functions abstract away the differences.
2432 multiclass namedimm<string prefix, string mapper> {
2433 def _asmoperand : AsmOperandClass {
2434 let Name = "NamedImm" # prefix;
2435 let PredicateMethod = "isUImm";
2436 let RenderMethod = "addImmOperands";
2437 let ParserMethod = "ParseNamedImmOperand<" # mapper # ">";
2438 let DiagnosticType = "NamedImm_" # prefix;
2441 def _op : Operand<i32> {
2442 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
2443 let PrintMethod = "printNamedImmOperand<" # mapper # ">";
2444 let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">";
2448 defm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">;
2450 class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg,
2451 list<dag> patterns = []>
2452 : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
2453 "ldr\t$Rt, $Imm19", patterns, NoItinerary>;
2455 let mayLoad = 1 in {
2456 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
2457 def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>;
2460 def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>;
2461 def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>;
2463 let mayLoad = 1 in {
2464 def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>;
2467 def LDRSWx_lit : A64I_LDRlit<0b10, 0b0,
2469 (ins ldrlit_label:$Imm19),
2470 "ldrsw\t$Rt, $Imm19",
2473 def PRFM_lit : A64I_LDRlit<0b11, 0b0,
2474 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
2475 "prfm\t$Rt, $Imm19",
2479 //===----------------------------------------------------------------------===//
2480 // Load-store exclusive instructions
2481 //===----------------------------------------------------------------------===//
2482 // Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB,
2483 // STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB,
2484 // STLRH, STLR, LDARB, LDARH, LDAR
2486 // Since these instructions have the undefined register bits set to 1 in
2487 // their canonical form, we need a post encoder method to set those bits
2488 // to 1 when encoding these instructions. We do this using the
2489 // fixLoadStoreExclusive function. This function has template parameters:
2491 // fixLoadStoreExclusive<int hasRs, int hasRt2>
2493 // hasRs indicates that the instruction uses the Rs field, so we won't set
2494 // it to 1 (and the same for Rt2). We don't need template parameters for
2495 // the other register fiels since Rt and Rn are always used.
2497 // This operand parses a GPR64xsp register, followed by an optional immediate
2499 def GPR64xsp0_asmoperand : AsmOperandClass {
2500 let Name = "GPR64xsp0";
2501 let PredicateMethod = "isWrappedReg";
2502 let RenderMethod = "addRegOperands";
2503 let ParserMethod = "ParseLSXAddressOperand";
2504 // Diagnostics are provided by ParserMethod
2507 def GPR64xsp0 : RegisterOperand<GPR64xsp> {
2508 let ParserMatchClass = GPR64xsp0_asmoperand;
2511 //===----------------------------------
2512 // Store-exclusive (releasing & normal)
2513 //===----------------------------------
2515 class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2516 dag ins, list<dag> pat,
2517 InstrItinClass itin> :
2518 A64I_LDSTex_stn <size,
2519 opcode{2}, 0, opcode{1}, opcode{0},
2521 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
2524 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
2527 multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
2528 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2529 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2532 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2533 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2536 def _word: A64I_SRexs_impl<0b10, opcode, asmstr,
2537 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2540 def _dword: A64I_SRexs_impl<0b11, opcode, asmstr,
2541 (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2545 defm STXR : A64I_SRex<"stxr", 0b000, "STXR">;
2546 defm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">;
2548 //===----------------------------------
2550 //===----------------------------------
2552 class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2553 dag ins, list<dag> pat,
2554 InstrItinClass itin> :
2555 A64I_LDSTex_tn <size,
2556 opcode{2}, 1, opcode{1}, opcode{0},
2558 !strconcat(asm, "\t$Rt, [$Rn]"),
2561 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2564 multiclass A64I_LRex<string asmstr, bits<3> opcode> {
2565 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2566 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2569 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2570 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2573 def _word: A64I_LRexs_impl<0b10, opcode, asmstr,
2574 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2577 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,
2578 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn),
2582 defm LDXR : A64I_LRex<"ldxr", 0b000>;
2583 defm LDAXR : A64I_LRex<"ldaxr", 0b001>;
2584 defm LDAR : A64I_LRex<"ldar", 0b101>;
2586 class acquiring_load<PatFrag base>
2587 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
2588 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2589 return Ordering == Acquire || Ordering == SequentiallyConsistent;
2592 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
2593 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
2594 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
2595 def atomic_load_acquire_64 : acquiring_load<atomic_load_64>;
2597 def : Pat<(atomic_load_acquire_8 i64:$Rn), (LDAR_byte $Rn)>;
2598 def : Pat<(atomic_load_acquire_16 i64:$Rn), (LDAR_hword $Rn)>;
2599 def : Pat<(atomic_load_acquire_32 i64:$Rn), (LDAR_word $Rn)>;
2600 def : Pat<(atomic_load_acquire_64 i64:$Rn), (LDAR_dword $Rn)>;
2602 //===----------------------------------
2603 // Store-release (no exclusivity)
2604 //===----------------------------------
2606 class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2607 dag ins, list<dag> pat,
2608 InstrItinClass itin> :
2609 A64I_LDSTex_tn <size,
2610 opcode{2}, 0, opcode{1}, opcode{0},
2612 !strconcat(asm, "\t$Rt, [$Rn]"),
2615 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2618 class releasing_store<PatFrag base>
2619 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
2620 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2621 return Ordering == Release || Ordering == SequentiallyConsistent;
2624 def atomic_store_release_8 : releasing_store<atomic_store_8>;
2625 def atomic_store_release_16 : releasing_store<atomic_store_16>;
2626 def atomic_store_release_32 : releasing_store<atomic_store_32>;
2627 def atomic_store_release_64 : releasing_store<atomic_store_64>;
2629 multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> {
2630 def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2631 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2632 [(atomic_store_release_8 i64:$Rn, i32:$Rt)],
2635 def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2636 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2637 [(atomic_store_release_16 i64:$Rn, i32:$Rt)],
2640 def _word: A64I_SLexs_impl<0b10, opcode, asmstr,
2641 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2642 [(atomic_store_release_32 i64:$Rn, i32:$Rt)],
2645 def _dword: A64I_SLexs_impl<0b11, opcode, asmstr,
2646 (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2647 [(atomic_store_release_64 i64:$Rn, i64:$Rt)],
2651 defm STLR : A64I_SLex<"stlr", 0b101, "STLR">;
2653 //===----------------------------------
2654 // Store-exclusive pair (releasing & normal)
2655 //===----------------------------------
2657 class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2658 dag ins, list<dag> pat,
2659 InstrItinClass itin> :
2660 A64I_LDSTex_stt2n <size,
2661 opcode{2}, 0, opcode{1}, opcode{0},
2663 !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"),
2669 multiclass A64I_SPex<string asmstr, bits<3> opcode> {
2670 def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs),
2671 (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2,
2675 def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs),
2676 (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2,
2681 defm STXP : A64I_SPex<"stxp", 0b010>;
2682 defm STLXP : A64I_SPex<"stlxp", 0b011>;
2684 //===----------------------------------
2685 // Load-exclusive pair (acquiring & normal)
2686 //===----------------------------------
2688 class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2689 dag ins, list<dag> pat,
2690 InstrItinClass itin> :
2691 A64I_LDSTex_tt2n <size,
2692 opcode{2}, 1, opcode{1}, opcode{0},
2694 !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"),
2697 let DecoderMethod = "DecodeLoadPairExclusiveInstruction";
2698 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
2701 multiclass A64I_LPex<string asmstr, bits<3> opcode> {
2702 def _word: A64I_LPexs_impl<0b10, opcode, asmstr,
2703 (outs GPR32:$Rt, GPR32:$Rt2),
2704 (ins GPR64xsp0:$Rn),
2707 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
2708 (outs GPR64:$Rt, GPR64:$Rt2),
2709 (ins GPR64xsp0:$Rn),
2713 defm LDXP : A64I_LPex<"ldxp", 0b010>;
2714 defm LDAXP : A64I_LPex<"ldaxp", 0b011>;
2716 //===----------------------------------------------------------------------===//
2717 // Load-store register (unscaled immediate) instructions
2718 //===----------------------------------------------------------------------===//
2719 // Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM
2723 //===----------------------------------------------------------------------===//
2724 // Load-store register (register offset) instructions
2725 //===----------------------------------------------------------------------===//
2726 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2730 //===----------------------------------------------------------------------===//
2731 // Load-store register (unsigned immediate) instructions
2732 //===----------------------------------------------------------------------===//
2733 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2737 //===----------------------------------------------------------------------===//
2738 // Load-store register (immediate post-indexed) instructions
2739 //===----------------------------------------------------------------------===//
2740 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2744 //===----------------------------------------------------------------------===//
2745 // Load-store register (immediate pre-indexed) instructions
2746 //===----------------------------------------------------------------------===//
2747 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2749 // Note that patterns are much later on in a completely separate section (they
2750 // need ADRPxi to be defined).
2752 //===-------------------------------
2753 // 1. Various operands needed
2754 //===-------------------------------
2756 //===-------------------------------
2757 // 1.1 Unsigned 12-bit immediate operands
2758 //===-------------------------------
2759 // The addressing mode for these instructions consists of an unsigned 12-bit
2760 // immediate which is scaled by the size of the memory access.
2762 // We represent this in the MC layer by two operands:
2763 // 1. A base register.
2764 // 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]"
2765 // would have '1' in this field.
2766 // This means that separate functions are needed for converting representations
2767 // which *are* aware of the intended access size.
2769 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
2770 // know the access size via some means. An isolated operand does not have this
2771 // information unless told from here, which means we need separate tablegen
2772 // Operands for each access size. This multiclass takes care of instantiating
2773 // the correct template functions in the rest of the backend.
2775 //===-------------------------------
2776 // 1.1 Unsigned 12-bit immediate operands
2777 //===-------------------------------
2779 multiclass offsets_uimm12<int MemSize, string prefix> {
2780 def uimm12_asmoperand : AsmOperandClass {
2781 let Name = "OffsetUImm12_" # MemSize;
2782 let PredicateMethod = "isOffsetUImm12<" # MemSize # ">";
2783 let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">";
2784 let DiagnosticType = "LoadStoreUImm12_" # MemSize;
2787 // Pattern is really no more than an ImmLeaf, but predicated on MemSize which
2788 // complicates things beyond TableGen's ken.
2789 def uimm12 : Operand<i64>,
2790 ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> {
2791 let ParserMatchClass
2792 = !cast<AsmOperandClass>(prefix # uimm12_asmoperand);
2794 let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">";
2795 let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">";
2799 defm byte_ : offsets_uimm12<1, "byte_">;
2800 defm hword_ : offsets_uimm12<2, "hword_">;
2801 defm word_ : offsets_uimm12<4, "word_">;
2802 defm dword_ : offsets_uimm12<8, "dword_">;
2803 defm qword_ : offsets_uimm12<16, "qword_">;
2805 //===-------------------------------
2806 // 1.1 Signed 9-bit immediate operands
2807 //===-------------------------------
2809 // The MCInst is expected to store the bit-wise encoding of the value,
2810 // which amounts to lopping off the extended sign bits.
2811 def SDXF_simm9 : SDNodeXForm<imm, [{
2812 return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32);
2815 def simm9_asmoperand : AsmOperandClass {
2817 let PredicateMethod = "isSImm<9>";
2818 let RenderMethod = "addSImmOperands<9>";
2819 let DiagnosticType = "LoadStoreSImm9";
2822 def simm9 : Operand<i64>,
2823 ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }],
2825 let PrintMethod = "printOffsetSImm9Operand";
2826 let ParserMatchClass = simm9_asmoperand;
2830 //===-------------------------------
2831 // 1.3 Register offset extensions
2832 //===-------------------------------
2834 // The assembly-syntax for these addressing-modes is:
2835 // [<Xn|SP>, <R><m> {, <extend> {<amount>}}]
2837 // The essential semantics are:
2838 // + <amount> is a shift: #<log(transfer size)> or #0
2839 // + <R> can be W or X.
2840 // + If <R> is W, <extend> can be UXTW or SXTW
2841 // + If <R> is X, <extend> can be LSL or SXTX
2843 // The trickiest of those constraints is that Rm can be either GPR32 or GPR64,
2844 // which will need separate instructions for LLVM type-consistency. We'll also
2845 // need separate operands, of course.
2846 multiclass regexts<int MemSize, int RmSize, RegisterClass GPR,
2847 string Rm, string prefix> {
2848 def regext_asmoperand : AsmOperandClass {
2849 let Name = "AddrRegExtend_" # MemSize # "_" # Rm;
2850 let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">";
2851 let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">";
2852 let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize;
2855 def regext : Operand<i64> {
2857 = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">";
2859 let DecoderMethod = "DecodeAddrRegExtendOperand";
2860 let ParserMatchClass
2861 = !cast<AsmOperandClass>(prefix # regext_asmoperand);
2865 multiclass regexts_wx<int MemSize, string prefix> {
2866 // Rm is an X-register if LSL or SXTX are specified as the shift.
2867 defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">;
2869 // Rm is a W-register if UXTW or SXTW are specified as the shift.
2870 defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">;
2873 defm byte_ : regexts_wx<1, "byte_">;
2874 defm hword_ : regexts_wx<2, "hword_">;
2875 defm word_ : regexts_wx<4, "word_">;
2876 defm dword_ : regexts_wx<8, "dword_">;
2877 defm qword_ : regexts_wx<16, "qword_">;
2880 //===------------------------------
2881 // 2. The instructions themselves.
2882 //===------------------------------
2884 // We have the following instructions to implement:
2885 // | | B | H | W | X |
2886 // |-----------------+-------+-------+-------+--------|
2887 // | unsigned str | STRB | STRH | STR | STR |
2888 // | unsigned ldr | LDRB | LDRH | LDR | LDR |
2889 // | signed ldr to W | LDRSB | LDRSH | - | - |
2890 // | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) |
2892 // This will instantiate the LDR/STR instructions you'd expect to use for an
2893 // unsigned datatype (first two rows above) or floating-point register, which is
2894 // reasonably uniform across all access sizes.
2897 //===------------------------------
2898 // 2.1 Regular instructions
2899 //===------------------------------
2901 // This class covers the basic unsigned or irrelevantly-signed loads and stores,
2902 // to general-purpose and floating-point registers.
2904 class AddrParams<string prefix> {
2905 Operand uimm12 = !cast<Operand>(prefix # "_uimm12");
2907 Operand regextWm = !cast<Operand>(prefix # "_Wm_regext");
2908 Operand regextXm = !cast<Operand>(prefix # "_Xm_regext");
2911 def byte_addrparams : AddrParams<"byte">;
2912 def hword_addrparams : AddrParams<"hword">;
2913 def word_addrparams : AddrParams<"word">;
2914 def dword_addrparams : AddrParams<"dword">;
2915 def qword_addrparams : AddrParams<"qword">;
2917 multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
2918 bit high_opc, string asmsuffix,
2919 RegisterClass GPR, AddrParams params> {
2920 // Unsigned immediate
2921 def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
2922 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
2923 "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
2927 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
2928 (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2930 def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},
2931 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
2932 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
2936 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
2937 (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2939 // Register offset (four of these: load/store and Wm/Xm).
2940 let mayLoad = 1 in {
2941 def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0,
2943 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
2944 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2947 def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1,
2949 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
2950 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2953 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",
2954 (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
2957 let mayStore = 1 in {
2958 def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0,
2959 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
2960 params.regextWm:$Ext),
2961 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2964 def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1,
2965 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm,
2966 params.regextXm:$Ext),
2967 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2970 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]",
2971 (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn,
2974 // Unaligned immediate
2975 def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
2976 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
2977 "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
2981 def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
2982 (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2984 def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},
2985 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
2986 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
2990 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
2991 (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2994 def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0},
2995 (outs GPR64xsp:$Rn_wb),
2996 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
2997 "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
2999 let Constraints = "$Rn = $Rn_wb";
3002 // Decoder only needed for unpredictability checking (FIXME).
3003 let DecoderMethod = "DecodeSingleIndexedInstruction";
3006 def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1},
3007 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3008 (ins GPR64xsp:$Rn, simm9:$SImm9),
3009 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3012 let Constraints = "$Rn = $Rn_wb";
3013 let DecoderMethod = "DecodeSingleIndexedInstruction";
3017 def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0},
3018 (outs GPR64xsp:$Rn_wb),
3019 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3020 "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3022 let Constraints = "$Rn = $Rn_wb";
3025 // Decoder only needed for unpredictability checking (FIXME).
3026 let DecoderMethod = "DecodeSingleIndexedInstruction";
3029 def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1},
3030 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3031 (ins GPR64xsp:$Rn, simm9:$SImm9),
3032 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3035 let Constraints = "$Rn = $Rn_wb";
3036 let DecoderMethod = "DecodeSingleIndexedInstruction";
3041 // STRB/LDRB: First define the instructions
3043 : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>;
3047 : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>;
3050 // STR/LDR to/from a W register
3052 : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>;
3054 // STR/LDR to/from an X register
3056 : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>;
3058 // STR/LDR to/from a B register
3060 : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>;
3062 // STR/LDR to/from an H register
3064 : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>;
3066 // STR/LDR to/from an S register
3068 : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>;
3069 // STR/LDR to/from a D register
3071 : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>;
3072 // STR/LDR to/from a Q register
3074 : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128,
3077 //===------------------------------
3079 //===------------------------------
3081 // Byte and half-word signed loads can both go into either an X or a W register,
3082 // so it's worth factoring out. Signed word loads don't fit because there is no
3084 multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
3087 def w : A64I_LSunsigimm<size, 0b0, 0b11,
3089 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3090 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3094 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3095 (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3097 def x : A64I_LSunsigimm<size, 0b0, 0b10,
3099 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3100 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3104 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3105 (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3108 let mayLoad = 1 in {
3109 def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0,
3111 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3112 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3115 def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1,
3117 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3118 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3121 def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0,
3123 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3124 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3127 def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1,
3129 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3130 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3133 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3134 (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,
3137 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3138 (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn,
3142 let mayLoad = 1 in {
3144 def w_U : A64I_LSunalimm<size, 0b0, 0b11,
3146 (ins GPR64xsp:$Rn, simm9:$SImm9),
3147 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3150 def x_U : A64I_LSunalimm<size, 0b0, 0b10,
3152 (ins GPR64xsp:$Rn, simm9:$SImm9),
3153 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3158 def w_PostInd : A64I_LSpostind<size, 0b0, 0b11,
3159 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3160 (ins GPR64xsp:$Rn, simm9:$SImm9),
3161 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3163 let Constraints = "$Rn = $Rn_wb";
3164 let DecoderMethod = "DecodeSingleIndexedInstruction";
3167 def x_PostInd : A64I_LSpostind<size, 0b0, 0b10,
3168 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3169 (ins GPR64xsp:$Rn, simm9:$SImm9),
3170 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3172 let Constraints = "$Rn = $Rn_wb";
3173 let DecoderMethod = "DecodeSingleIndexedInstruction";
3177 def w_PreInd : A64I_LSpreind<size, 0b0, 0b11,
3178 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3179 (ins GPR64xsp:$Rn, simm9:$SImm9),
3180 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3182 let Constraints = "$Rn = $Rn_wb";
3183 let DecoderMethod = "DecodeSingleIndexedInstruction";
3186 def x_PreInd : A64I_LSpreind<size, 0b0, 0b10,
3187 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3188 (ins GPR64xsp:$Rn, simm9:$SImm9),
3189 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3191 let Constraints = "$Rn = $Rn_wb";
3192 let DecoderMethod = "DecodeSingleIndexedInstruction";
3194 } // let mayLoad = 1
3198 defm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">;
3200 defm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">;
3202 // LDRSW: load a 32-bit register, sign-extending to 64-bits.
3204 : A64I_LSunsigimm<0b10, 0b0, 0b10,
3206 (ins GPR64xsp:$Rn, word_uimm12:$UImm12),
3207 "ldrsw\t$Rt, [$Rn, $UImm12]",
3211 def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3213 let mayLoad = 1 in {
3214 def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0,
3216 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
3217 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3220 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,
3222 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),
3223 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3226 def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",
3227 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;
3231 : A64I_LSunalimm<0b10, 0b0, 0b10,
3233 (ins GPR64xsp:$Rn, simm9:$SImm9),
3234 "ldursw\t$Rt, [$Rn, $SImm9]",
3238 def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3241 : A64I_LSpostind<0b10, 0b0, 0b10,
3242 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3243 (ins GPR64xsp:$Rn, simm9:$SImm9),
3244 "ldrsw\t$Rt, [$Rn], $SImm9",
3247 let Constraints = "$Rn = $Rn_wb";
3248 let DecoderMethod = "DecodeSingleIndexedInstruction";
3251 def LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10,
3252 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3253 (ins GPR64xsp:$Rn, simm9:$SImm9),
3254 "ldrsw\t$Rt, [$Rn, $SImm9]!",
3257 let Constraints = "$Rn = $Rn_wb";
3258 let DecoderMethod = "DecodeSingleIndexedInstruction";
3261 //===------------------------------
3262 // 2.4 Prefetch operations
3263 //===------------------------------
3265 def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
3266 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
3267 "prfm\t$Rt, [$Rn, $UImm12]",
3271 def : InstAlias<"prfm $Rt, [$Rn]",
3272 (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3274 let mayLoad = 1 in {
3275 def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs),
3276 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3277 GPR32:$Rm, dword_Wm_regext:$Ext),
3278 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3280 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),
3281 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3282 GPR64:$Rm, dword_Xm_regext:$Ext),
3283 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3287 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
3288 (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn,
3292 def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
3293 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3294 "prfum\t$Rt, [$Rn, $SImm9]",
3298 def : InstAlias<"prfum $Rt, [$Rn]",
3299 (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3301 //===----------------------------------------------------------------------===//
3302 // Load-store register (unprivileged) instructions
3303 //===----------------------------------------------------------------------===//
3304 // Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH
3306 // These instructions very much mirror the "unscaled immediate" loads, but since
3307 // there are no floating-point variants we need to split them out into their own
3308 // section to avoid instantiation of "ldtr d0, [sp]" etc.
3310 multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR,
3312 def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,
3313 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3314 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3319 def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]",
3320 (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3322 def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,
3323 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3324 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3329 def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]",
3330 (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3334 // STTRB/LDTRB: First define the instructions
3335 defm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">;
3338 defm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">;
3340 // STTR/LDTR to/from a W register
3341 defm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">;
3343 // STTR/LDTR to/from an X register
3344 defm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">;
3346 // Now a class for the signed instructions that can go to either 32 or 64
3348 multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> {
3349 let mayLoad = 1 in {
3350 def w : A64I_LSunpriv<size, 0b0, 0b11,
3352 (ins GPR64xsp:$Rn, simm9:$SImm9),
3353 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3356 def x : A64I_LSunpriv<size, 0b0, 0b10,
3358 (ins GPR64xsp:$Rn, simm9:$SImm9),
3359 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3363 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3364 (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3366 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3367 (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3372 defm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">;
3374 defm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">;
3376 // And finally LDTRSW which only goes to 64 bits.
3377 def LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10,
3379 (ins GPR64xsp:$Rn, simm9:$SImm9),
3380 "ldtrsw\t$Rt, [$Rn, $SImm9]",
3384 def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3386 //===----------------------------------------------------------------------===//
3387 // Load-store register pair (offset) instructions
3388 //===----------------------------------------------------------------------===//
3392 //===----------------------------------------------------------------------===//
3393 // Load-store register pair (post-indexed) instructions
3394 //===----------------------------------------------------------------------===//
3395 // Contains: STP, LDP, LDPSW
3399 //===----------------------------------------------------------------------===//
3400 // Load-store register pair (pre-indexed) instructions
3401 //===----------------------------------------------------------------------===//
3402 // Contains: STP, LDP, LDPSW
3406 //===----------------------------------------------------------------------===//
3407 // Load-store non-temporal register pair (offset) instructions
3408 //===----------------------------------------------------------------------===//
3409 // Contains: STNP, LDNP
3412 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
3413 // know the access size via some means. An isolated operand does not have this
3414 // information unless told from here, which means we need separate tablegen
3415 // Operands for each access size. This multiclass takes care of instantiating
3416 // the correct template functions in the rest of the backend.
3418 multiclass offsets_simm7<string MemSize, string prefix> {
3419 // The bare signed 7-bit immediate is used in post-indexed instructions, but
3420 // because of the scaling performed a generic "simm7" operand isn't
3421 // appropriate here either.
3422 def simm7_asmoperand : AsmOperandClass {
3423 let Name = "SImm7_Scaled" # MemSize;
3424 let PredicateMethod = "isSImm7Scaled<" # MemSize # ">";
3425 let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">";
3426 let DiagnosticType = "LoadStoreSImm7_" # MemSize;
3429 def simm7 : Operand<i64> {
3430 let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">";
3431 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand");
3435 defm word_ : offsets_simm7<"4", "word_">;
3436 defm dword_ : offsets_simm7<"8", "dword_">;
3437 defm qword_ : offsets_simm7<"16", "qword_">;
3439 multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
3440 Operand simm7, string prefix> {
3441 def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),
3442 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3443 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3445 let DecoderMethod = "DecodeLDSTPairInstruction";
3447 def : InstAlias<"stp $Rt, $Rt2, [$Rn]",
3448 (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt,
3449 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3451 def _LDR : A64I_LSPoffset<opc, v, 0b1,
3452 (outs SomeReg:$Rt, SomeReg:$Rt2),
3453 (ins GPR64xsp:$Rn, simm7:$SImm7),
3454 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3456 let DecoderMethod = "DecodeLDSTPairInstruction";
3458 def : InstAlias<"ldp $Rt, $Rt2, [$Rn]",
3459 (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt,
3460 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3462 def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0,
3463 (outs GPR64xsp:$Rn_wb),
3464 (ins SomeReg:$Rt, SomeReg:$Rt2,
3467 "stp\t$Rt, $Rt2, [$Rn], $SImm7",
3470 let Constraints = "$Rn = $Rn_wb";
3472 // Decoder only needed for unpredictability checking (FIXME).
3473 let DecoderMethod = "DecodeLDSTPairInstruction";
3476 def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1,
3477 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3478 (ins GPR64xsp:$Rn, simm7:$SImm7),
3479 "ldp\t$Rt, $Rt2, [$Rn], $SImm7",
3482 let Constraints = "$Rn = $Rn_wb";
3483 let DecoderMethod = "DecodeLDSTPairInstruction";
3486 def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
3487 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3488 "stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3491 let Constraints = "$Rn = $Rn_wb";
3492 let DecoderMethod = "DecodeLDSTPairInstruction";
3495 def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1,
3496 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3497 (ins GPR64xsp:$Rn, simm7:$SImm7),
3498 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3501 let Constraints = "$Rn = $Rn_wb";
3502 let DecoderMethod = "DecodeLDSTPairInstruction";
3505 def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
3506 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3507 "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3509 let DecoderMethod = "DecodeLDSTPairInstruction";
3511 def : InstAlias<"stnp $Rt, $Rt2, [$Rn]",
3512 (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt,
3513 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3515 def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,
3516 (outs SomeReg:$Rt, SomeReg:$Rt2),
3517 (ins GPR64xsp:$Rn, simm7:$SImm7),
3518 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3520 let DecoderMethod = "DecodeLDSTPairInstruction";
3522 def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]",
3523 (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt,
3524 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3529 defm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">;
3530 defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">;
3531 defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">;
3532 defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">;
3533 defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7,
3537 def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
3538 (outs GPR64:$Rt, GPR64:$Rt2),
3539 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3540 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3542 let DecoderMethod = "DecodeLDSTPairInstruction";
3544 def : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]",
3545 (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>;
3547 def LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1,
3548 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3549 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3550 "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
3553 let Constraints = "$Rn = $Rn_wb";
3554 let DecoderMethod = "DecodeLDSTPairInstruction";
3557 def LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1,
3558 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3559 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3560 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
3563 let Constraints = "$Rn = $Rn_wb";
3564 let DecoderMethod = "DecodeLDSTPairInstruction";
3567 //===----------------------------------------------------------------------===//
3568 // Logical (immediate) instructions
3569 //===----------------------------------------------------------------------===//
3570 // Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV
3572 multiclass logical_imm_operands<string prefix, string note,
3573 int size, ValueType VT> {
3574 def _asmoperand : AsmOperandClass {
3575 let Name = "LogicalImm" # note # size;
3576 let PredicateMethod = "isLogicalImm" # note # "<" # size # ">";
3577 let RenderMethod = "addLogicalImmOperands<" # size # ">";
3578 let DiagnosticType = "LogicalSecondSource";
3582 : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> {
3583 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3584 let PrintMethod = "printLogicalImmOperand<" # size # ">";
3585 let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">";
3589 defm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>;
3590 defm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>;
3592 // The mov versions only differ in assembly parsing, where they
3593 // exclude values representable with either MOVZ or MOVN.
3594 defm logical_imm32_mov
3595 : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>;
3596 defm logical_imm64_mov
3597 : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>;
3600 multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> {
3601 def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd),
3602 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3603 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3605 (opnode i32:$Rn, logical_imm32_operand:$Imm))],
3608 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
3609 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3610 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3612 (opnode i64:$Rn, logical_imm64_operand:$Imm))],
3616 defm AND : A64I_logimmSizes<0b00, "and", and>;
3617 defm ORR : A64I_logimmSizes<0b01, "orr", or>;
3618 defm EOR : A64I_logimmSizes<0b10, "eor", xor>;
3620 let Defs = [NZCV] in {
3621 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
3622 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3623 "ands\t$Rd, $Rn, $Imm",
3626 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),
3627 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3628 "ands\t$Rd, $Rn, $Imm",
3633 def : InstAlias<"tst $Rn, $Imm",
3634 (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>;
3635 def : InstAlias<"tst $Rn, $Imm",
3636 (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>;
3637 def : InstAlias<"mov $Rd, $Imm",
3638 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>;
3639 def : InstAlias<"mov $Rd, $Imm",
3640 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>;
3642 //===----------------------------------------------------------------------===//
3643 // Logical (shifted register) instructions
3644 //===----------------------------------------------------------------------===//
3645 // Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV
3647 // Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS"
3648 // behaves differently for unsigned comparisons, so we defensively only allow
3649 // signed or n/a as the operand. In practice "unsigned greater than 0" is "not
3650 // equal to 0" and LLVM gives us this.
3651 def signed_cond : PatLeaf<(cond), [{
3652 return !isUnsignedIntSetCC(N->get());
3656 // These instructions share their "shift" operands with add/sub (shifted
3657 // register instructions). They are defined there.
3659 // N.b. the commutable parameter is just !N. It will be first against the wall
3660 // when the revolution comes.
3661 multiclass logical_shifts<string prefix, bit sf, bits<2> opc,
3662 bit N, bit commutable,
3663 string asmop, SDPatternOperator opfrag, ValueType ty,
3664 RegisterClass GPR, list<Register> defs> {
3665 let isCommutable = commutable, Defs = defs in {
3666 def _lsl : A64I_logicalshift<sf, opc, 0b00, N,
3668 (ins GPR:$Rn, GPR:$Rm,
3669 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3670 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3671 [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
3672 !cast<Operand>("lsl_operand_" # ty):$Imm6))
3676 def _lsr : A64I_logicalshift<sf, opc, 0b01, N,
3678 (ins GPR:$Rn, GPR:$Rm,
3679 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3680 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3681 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
3682 !cast<Operand>("lsr_operand_" # ty):$Imm6))
3686 def _asr : A64I_logicalshift<sf, opc, 0b10, N,
3688 (ins GPR:$Rn, GPR:$Rm,
3689 !cast<Operand>("asr_operand_" # ty):$Imm6),
3690 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3691 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
3692 !cast<Operand>("asr_operand_" # ty):$Imm6))
3696 def _ror : A64I_logicalshift<sf, opc, 0b11, N,
3698 (ins GPR:$Rn, GPR:$Rm,
3699 !cast<Operand>("ror_operand_" # ty):$Imm6),
3700 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3701 [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm,
3702 !cast<Operand>("ror_operand_" # ty):$Imm6))
3708 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
3709 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
3712 def : Pat<(opfrag ty:$Rn, ty:$Rm),
3713 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
3716 multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable,
3717 string asmop, SDPatternOperator opfrag,
3718 list<Register> defs> {
3719 defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N,
3720 commutable, asmop, opfrag, i64, GPR64, defs>;
3721 defm www : logical_shifts<prefix # "www", 0b0, opc, N,
3722 commutable, asmop, opfrag, i32, GPR32, defs>;
3726 defm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>;
3727 defm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>;
3728 defm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>;
3729 defm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands",
3730 PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs),
3731 [{ (void)N; return false; }]>,
3734 defm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic",
3735 PatFrag<(ops node:$lhs, node:$rhs),
3736 (and node:$lhs, (not node:$rhs))>, []>;
3737 defm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn",
3738 PatFrag<(ops node:$lhs, node:$rhs),
3739 (or node:$lhs, (not node:$rhs))>, []>;
3740 defm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon",
3741 PatFrag<(ops node:$lhs, node:$rhs),
3742 (xor node:$lhs, (not node:$rhs))>, []>;
3743 defm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics",
3744 PatFrag<(ops node:$lhs, node:$rhs),
3745 (and node:$lhs, (not node:$rhs)),
3746 [{ (void)N; return false; }]>,
3749 multiclass tst_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
3750 let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in {
3751 def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0,
3753 (ins GPR:$Rn, GPR:$Rm,
3754 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3755 "tst\t$Rn, $Rm, $Imm6",
3756 [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm,
3757 !cast<Operand>("lsl_operand_" # ty):$Imm6)),
3762 def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0,
3764 (ins GPR:$Rn, GPR:$Rm,
3765 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3766 "tst\t$Rn, $Rm, $Imm6",
3767 [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm,
3768 !cast<Operand>("lsr_operand_" # ty):$Imm6)),
3772 def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0,
3774 (ins GPR:$Rn, GPR:$Rm,
3775 !cast<Operand>("asr_operand_" # ty):$Imm6),
3776 "tst\t$Rn, $Rm, $Imm6",
3777 [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm,
3778 !cast<Operand>("asr_operand_" # ty):$Imm6)),
3782 def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0,
3784 (ins GPR:$Rn, GPR:$Rm,
3785 !cast<Operand>("ror_operand_" # ty):$Imm6),
3786 "tst\t$Rn, $Rm, $Imm6",
3787 [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm,
3788 !cast<Operand>("ror_operand_" # ty):$Imm6)),
3793 def _noshift : InstAlias<"tst $Rn, $Rm",
3794 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3796 def : Pat<(A64setcc (and ty:$Rn, ty:$Rm), 0, signed_cond),
3797 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
3800 defm TSTxx : tst_shifts<"TSTxx", 0b1, i64, GPR64>;
3801 defm TSTww : tst_shifts<"TSTww", 0b0, i32, GPR32>;
3804 multiclass mvn_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
3805 let isCommutable = 0, Rn = 0b11111 in {
3806 def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1,
3809 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3810 "mvn\t$Rd, $Rm, $Imm6",
3811 [(set ty:$Rd, (not (shl ty:$Rm,
3812 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
3816 def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1,
3819 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3820 "mvn\t$Rd, $Rm, $Imm6",
3821 [(set ty:$Rd, (not (srl ty:$Rm,
3822 !cast<Operand>("lsr_operand_" # ty):$Imm6)))],
3825 def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1,
3828 !cast<Operand>("asr_operand_" # ty):$Imm6),
3829 "mvn\t$Rd, $Rm, $Imm6",
3830 [(set ty:$Rd, (not (sra ty:$Rm,
3831 !cast<Operand>("asr_operand_" # ty):$Imm6)))],
3834 def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1,
3837 !cast<Operand>("ror_operand_" # ty):$Imm6),
3838 "mvn\t$Rd, $Rm, $Imm6",
3839 [(set ty:$Rd, (not (rotr ty:$Rm,
3840 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
3844 def _noshift : InstAlias<"mvn $Rn, $Rm",
3845 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3847 def : Pat<(not ty:$Rm),
3848 (!cast<Instruction>(prefix # "_lsl") $Rm, 0)>;
3851 defm MVNxx : mvn_shifts<"MVNxx", 0b1, i64, GPR64>;
3852 defm MVNww : mvn_shifts<"MVNww", 0b0, i32, GPR32>;
3854 def MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
3855 def MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
3857 //===----------------------------------------------------------------------===//
3858 // Move wide (immediate) instructions
3859 //===----------------------------------------------------------------------===//
3860 // Contains: MOVN, MOVZ, MOVK + MOV aliases
3862 // A wide variety of different relocations are needed for variants of these
3863 // instructions, so it turns out that we need a different operand for all of
3865 multiclass movw_operands<string prefix, string instname, int width> {
3866 def _imm_asmoperand : AsmOperandClass {
3867 let Name = instname # width # "Shifted" # shift;
3868 let PredicateMethod = "is" # instname # width # "Imm";
3869 let RenderMethod = "addMoveWideImmOperands";
3870 let ParserMethod = "ParseImmWithLSLOperand";
3871 let DiagnosticType = "MOVWUImm16";
3874 def _imm : Operand<i32> {
3875 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand");
3876 let PrintMethod = "printMoveWideImmOperand";
3877 let EncoderMethod = "getMoveWideImmOpValue";
3878 let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">";
3880 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
3884 defm movn32 : movw_operands<"movn32", "MOVN", 32>;
3885 defm movn64 : movw_operands<"movn64", "MOVN", 64>;
3886 defm movz32 : movw_operands<"movz32", "MOVZ", 32>;
3887 defm movz64 : movw_operands<"movz64", "MOVZ", 64>;
3888 defm movk32 : movw_operands<"movk32", "MOVK", 32>;
3889 defm movk64 : movw_operands<"movk64", "MOVK", 64>;
3891 multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit,
3894 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
3895 !strconcat(asmop, "\t$Rd, $FullImm"),
3898 let UImm16 = FullImm{15-0};
3899 let Shift = FullImm{17-16};
3902 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
3903 !strconcat(asmop, "\t$Rd, $FullImm"),
3906 let UImm16 = FullImm{15-0};
3907 let Shift = FullImm{17-16};
3911 let isMoveImm = 1, isReMaterializable = 1,
3912 isAsCheapAsAMove = 1, hasSideEffects = 0 in {
3913 defm MOVN : A64I_movwSizes<0b00, "movn",
3914 (ins movn32_imm:$FullImm),
3915 (ins movn64_imm:$FullImm)>;
3917 // Some relocations are able to convert between a MOVZ and a MOVN. If these
3918 // are applied the instruction must be emitted with the corresponding bits as
3919 // 0, which means a MOVZ needs to override that bit from the default.
3920 let PostEncoderMethod = "fixMOVZ" in
3921 defm MOVZ : A64I_movwSizes<0b10, "movz",
3922 (ins movz32_imm:$FullImm),
3923 (ins movz64_imm:$FullImm)>;
3926 let Constraints = "$src = $Rd" in
3927 defm MOVK : A64I_movwSizes<0b11, "movk",
3928 (ins GPR32:$src, movk32_imm:$FullImm),
3929 (ins GPR64:$src, movk64_imm:$FullImm)>;
3932 // And now the "MOV" aliases. These also need their own operands because what
3933 // they accept is completely different to what the base instructions accept.
3934 multiclass movalias_operand<string prefix, string basename,
3935 string immpredicate, int width> {
3936 def _asmoperand : AsmOperandClass {
3937 let Name = basename # width # "MovAlias";
3939 = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">";
3941 = "addMoveWideMovAliasOperands<" # width # ", "
3942 # "A64Imms::" # immpredicate # ">";
3945 def _movimm : Operand<i32> {
3946 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3948 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
3952 defm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>;
3953 defm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>;
3954 defm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>;
3955 defm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>;
3957 // FIXME: these are officially canonical aliases, but TableGen is too limited to
3958 // print them at the moment. I believe in this case an "AliasPredicate" method
3959 // will need to be implemented. to allow it, as well as the more generally
3960 // useful handling of non-register, non-constant operands.
3961 class movalias<Instruction INST, RegisterClass GPR, Operand operand>
3962 : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>;
3964 def : movalias<MOVZwii, GPR32, movz32_movimm>;
3965 def : movalias<MOVZxii, GPR64, movz64_movimm>;
3966 def : movalias<MOVNwii, GPR32, movn32_movimm>;
3967 def : movalias<MOVNxii, GPR64, movn64_movimm>;
3969 //===----------------------------------------------------------------------===//
3970 // PC-relative addressing instructions
3971 //===----------------------------------------------------------------------===//
3972 // Contains: ADR, ADRP
3974 def adr_label : Operand<i64> {
3975 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>";
3977 // This label is a 21-bit offset from PC, unscaled
3978 let PrintMethod = "printLabelOperand<21, 1>";
3979 let ParserMatchClass = label_asmoperand<21, 1>;
3980 let OperandType = "OPERAND_PCREL";
3983 def adrp_label_asmoperand : AsmOperandClass {
3984 let Name = "AdrpLabel";
3985 let RenderMethod = "addLabelOperands<21, 4096>";
3986 let DiagnosticType = "Label";
3989 def adrp_label : Operand<i64> {
3990 let EncoderMethod = "getAdrpLabelOpValue";
3992 // This label is a 21-bit offset from PC, scaled by the page-size: 4096.
3993 let PrintMethod = "printLabelOperand<21, 4096>";
3994 let ParserMatchClass = adrp_label_asmoperand;
3995 let OperandType = "OPERAND_PCREL";
3998 let hasSideEffects = 0 in {
3999 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
4000 "adr\t$Rd, $Label", [], NoItinerary>;
4002 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),
4003 "adrp\t$Rd, $Label", [], NoItinerary>;
4006 //===----------------------------------------------------------------------===//
4007 // System instructions
4008 //===----------------------------------------------------------------------===//
4009 // Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS
4010 // + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL
4012 // Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values.
4013 def uimm3_asmoperand : AsmOperandClass {
4015 let PredicateMethod = "isUImm<3>";
4016 let RenderMethod = "addImmOperands";
4017 let DiagnosticType = "UImm3";
4020 def uimm3 : Operand<i32> {
4021 let ParserMatchClass = uimm3_asmoperand;
4024 // The HINT alias can accept a simple unsigned 7-bit immediate.
4025 def uimm7_asmoperand : AsmOperandClass {
4027 let PredicateMethod = "isUImm<7>";
4028 let RenderMethod = "addImmOperands";
4029 let DiagnosticType = "UImm7";
4032 def uimm7 : Operand<i32> {
4033 let ParserMatchClass = uimm7_asmoperand;
4036 // Multiclass namedimm is defined with the prefetch operands. Most of these fit
4037 // into the NamedImmMapper scheme well: they either accept a named operand or
4038 // any immediate under a particular value (which may be 0, implying no immediate
4040 defm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">;
4041 defm isb : namedimm<"isb", "A64ISB::ISBMapper">;
4042 defm ic : namedimm<"ic", "A64IC::ICMapper">;
4043 defm dc : namedimm<"dc", "A64DC::DCMapper">;
4044 defm at : namedimm<"at", "A64AT::ATMapper">;
4045 defm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">;
4047 // However, MRS and MSR are more complicated for a few reasons:
4048 // * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an
4049 // implementation-defined effect
4050 // * Most registers are shared, but some are read-only or write-only.
4051 // * There is a variant of MSR which accepts the same register name (SPSel),
4052 // but which would have a different encoding.
4054 // In principle these could be resolved in with more complicated subclasses of
4055 // NamedImmMapper, however that imposes an overhead on other "named
4056 // immediates". Both in concrete terms with virtual tables and in unnecessary
4059 // The solution adopted here is to take the MRS/MSR Mappers out of the usual
4060 // hierarchy (they're not derived from NamedImmMapper) and to add logic for
4061 // their special situation.
4062 def mrs_asmoperand : AsmOperandClass {
4064 let ParserMethod = "ParseSysRegOperand";
4065 let DiagnosticType = "MRS";
4068 def mrs_op : Operand<i32> {
4069 let ParserMatchClass = mrs_asmoperand;
4070 let PrintMethod = "printMRSOperand";
4071 let DecoderMethod = "DecodeMRSOperand";
4074 def msr_asmoperand : AsmOperandClass {
4075 let Name = "MSRWithReg";
4077 // Note that SPSel is valid for both this and the pstate operands, but with
4078 // different immediate encodings. This is why these operands provide a string
4079 // AArch64Operand rather than an immediate. The overlap is small enough that
4080 // it could be resolved with hackery now, but who can say in future?
4081 let ParserMethod = "ParseSysRegOperand";
4082 let DiagnosticType = "MSR";
4085 def msr_op : Operand<i32> {
4086 let ParserMatchClass = msr_asmoperand;
4087 let PrintMethod = "printMSROperand";
4088 let DecoderMethod = "DecodeMSROperand";
4091 def pstate_asmoperand : AsmOperandClass {
4092 let Name = "MSRPState";
4093 // See comment above about parser.
4094 let ParserMethod = "ParseSysRegOperand";
4095 let DiagnosticType = "MSR";
4098 def pstate_op : Operand<i32> {
4099 let ParserMatchClass = pstate_asmoperand;
4100 let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>";
4101 let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>";
4104 // When <CRn> is specified, an assembler should accept something like "C4", not
4105 // the usual "#4" immediate.
4106 def CRx_asmoperand : AsmOperandClass {
4108 let PredicateMethod = "isUImm<4>";
4109 let RenderMethod = "addImmOperands";
4110 let ParserMethod = "ParseCRxOperand";
4111 // Diagnostics are handled in all cases by ParseCRxOperand.
4114 def CRx : Operand<i32> {
4115 let ParserMatchClass = CRx_asmoperand;
4116 let PrintMethod = "printCRxOperand";
4120 // Finally, we can start defining the instructions.
4122 // HINT is straightforward, with a few aliases.
4123 def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7",
4126 let CRm = UImm7{6-3};
4127 let Op2 = UImm7{2-0};
4135 def : InstAlias<"nop", (HINTi 0)>;
4136 def : InstAlias<"yield", (HINTi 1)>;
4137 def : InstAlias<"wfe", (HINTi 2)>;
4138 def : InstAlias<"wfi", (HINTi 3)>;
4139 def : InstAlias<"sev", (HINTi 4)>;
4140 def : InstAlias<"sevl", (HINTi 5)>;
4142 // Quite a few instructions then follow a similar pattern of fixing common
4143 // fields in the bitpattern, we'll define a helper-class for them.
4144 class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2,
4145 Operand operand, string asmop>
4146 : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"),
4156 def CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">;
4157 def DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">;
4158 def DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">;
4159 def ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">;
4161 def : InstAlias<"clrex", (CLREXi 0b1111)>;
4162 def : InstAlias<"isb", (ISBi 0b1111)>;
4164 // (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP
4165 // configurations at least.
4166 def : Pat<(atomic_fence imm, imm), (DMBi 0xb)>;
4168 // Any SYS bitpattern can be represented with a complex and opaque "SYS"
4170 def SYSiccix : A64I_system<0b0, (outs),
4171 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm,
4172 uimm3:$Op2, GPR64:$Rt),
4173 "sys\t$Op1, $CRn, $CRm, $Op2, $Rt",
4178 // You can skip the Xt argument whether it makes sense or not for the generic
4180 def : InstAlias<"sys $Op1, $CRn, $CRm, $Op2",
4181 (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>;
4184 // But many have aliases, which obviously don't fit into
4185 class SYSalias<dag ins, string asmstring>
4186 : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> {
4187 let isAsmParserOnly = 1;
4191 let Op1 = SysOp{13-11};
4192 let CRn = SysOp{10-7};
4193 let CRm = SysOp{6-3};
4194 let Op2 = SysOp{2-0};
4197 def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">;
4199 def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> {
4203 def DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">;
4204 def ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">;
4206 def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">;
4208 def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> {
4213 def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt),
4214 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2),
4215 "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2",
4220 // The instructions themselves are rather simple for MSR and MRS.
4221 def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt),
4222 "msr\t$SysReg, $Rt", [], NoItinerary> {
4224 let Op0 = SysReg{15-14};
4225 let Op1 = SysReg{13-11};
4226 let CRn = SysReg{10-7};
4227 let CRm = SysReg{6-3};
4228 let Op2 = SysReg{2-0};
4231 def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg),
4232 "mrs\t$Rt, $SysReg", [], NoItinerary> {
4234 let Op0 = SysReg{15-14};
4235 let Op1 = SysReg{13-11};
4236 let CRn = SysReg{10-7};
4237 let CRm = SysReg{6-3};
4238 let Op2 = SysReg{2-0};
4241 def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm),
4242 "msr\t$PState, $CRm", [], NoItinerary> {
4246 let Op1 = PState{5-3};
4248 let Op2 = PState{2-0};
4252 //===----------------------------------------------------------------------===//
4253 // Test & branch (immediate) instructions
4254 //===----------------------------------------------------------------------===//
4255 // Contains: TBZ, TBNZ
4257 // The bit to test is a simple unsigned 6-bit immediate in the X-register
4259 def uimm6 : Operand<i64> {
4260 let ParserMatchClass = uimm6_asmoperand;
4263 def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>;
4265 def tbimm_target : Operand<OtherVT> {
4266 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>";
4268 // This label is a 14-bit offset from PC, scaled by the instruction-width: 4.
4269 let PrintMethod = "printLabelOperand<14, 4>";
4270 let ParserMatchClass = label_wid14_scal4_asmoperand;
4272 let OperandType = "OPERAND_PCREL";
4275 def A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>;
4276 def A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>;
4278 // These instructions correspond to patterns involving "and" with a power of
4279 // two, which we need to be able to select.
4280 def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">;
4281 def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">;
4283 let isBranch = 1, isTerminator = 1 in {
4284 def TBZxii : A64I_TBimm<0b0, (outs),
4285 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4286 "tbz\t$Rt, $Imm, $Label",
4287 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4291 def TBNZxii : A64I_TBimm<0b1, (outs),
4292 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4293 "tbnz\t$Rt, $Imm, $Label",
4294 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4299 // Note, these instructions overlap with the above 64-bit patterns. This is
4300 // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both
4301 // do the same thing and are both permitted assembly. They also both have
4302 // sensible DAG patterns.
4303 def TBZwii : A64I_TBimm<0b0, (outs),
4304 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4305 "tbz\t$Rt, $Imm, $Label",
4306 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4312 def TBNZwii : A64I_TBimm<0b1, (outs),
4313 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4314 "tbnz\t$Rt, $Imm, $Label",
4315 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4322 //===----------------------------------------------------------------------===//
4323 // Unconditional branch (immediate) instructions
4324 //===----------------------------------------------------------------------===//
4327 def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>;
4329 def bimm_target : Operand<OtherVT> {
4330 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>";
4332 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4333 let PrintMethod = "printLabelOperand<26, 4>";
4334 let ParserMatchClass = label_wid26_scal4_asmoperand;
4336 let OperandType = "OPERAND_PCREL";
4339 def blimm_target : Operand<i64> {
4340 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>";
4342 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4343 let PrintMethod = "printLabelOperand<26, 4>";
4344 let ParserMatchClass = label_wid26_scal4_asmoperand;
4346 let OperandType = "OPERAND_PCREL";
4349 class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type>
4350 : A64I_Bimm<op, (outs), (ins lbl_type:$Label),
4351 !strconcat(asmop, "\t$Label"), patterns,
4354 let isBranch = 1 in {
4355 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
4356 let isTerminator = 1;
4360 def BLimm : A64I_BimmImpl<0b1, "bl",
4361 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4367 def : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>;
4369 //===----------------------------------------------------------------------===//
4370 // Unconditional branch (register) instructions
4371 //===----------------------------------------------------------------------===//
4372 // Contains: BR, BLR, RET, ERET, DRP.
4374 // Most of the notional opcode fields in the A64I_Breg format are fixed in A64
4376 class A64I_BregImpl<bits<4> opc,
4377 dag outs, dag ins, string asmstr, list<dag> patterns,
4378 InstrItinClass itin = NoItinerary>
4379 : A64I_Breg<opc, 0b11111, 0b000000, 0b00000,
4380 outs, ins, asmstr, patterns, itin> {
4382 let isIndirectBranch = 1;
4385 // Note that these are not marked isCall or isReturn because as far as LLVM is
4386 // concerned they're not. "ret" is just another jump unless it has been selected
4387 // by LLVM as the function's return.
4389 let isBranch = 1 in {
4390 def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn),
4391 "br\t$Rn", [(brind i64:$Rn)]> {
4393 let isTerminator = 1;
4396 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4397 "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
4403 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
4406 let isTerminator = 1;
4410 // Create a separate pseudo-instruction for codegen to use so that we don't
4411 // flag x30 as used in every function. It'll be restored before the RET by the
4412 // epilogue if it's legitimately used.
4413 def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> {
4414 let isTerminator = 1;
4419 def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> {
4422 let isTerminator = 1;
4426 def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> {
4432 def RETAlias : InstAlias<"ret", (RETx X30)>;
4435 //===----------------------------------------------------------------------===//
4436 // Address generation patterns
4437 //===----------------------------------------------------------------------===//
4439 // Primary method of address generation for the small/absolute memory model is
4440 // an ADRP/ADR pair:
4441 // ADRP x0, some_variable
4442 // ADD x0, x0, #:lo12:some_variable
4444 // The load/store elision of the ADD is accomplished when selecting
4445 // addressing-modes. This just mops up the cases where that doesn't work and we
4446 // really need an address in some register.
4448 // This wrapper applies a LO12 modifier to the address. Otherwise we could just
4449 // use the same address.
4451 class ADRP_ADD<SDNode Wrapper, SDNode addrop>
4452 : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)),
4453 (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>;
4455 def : ADRP_ADD<A64WrapperSmall, tblockaddress>;
4456 def : ADRP_ADD<A64WrapperSmall, texternalsym>;
4457 def : ADRP_ADD<A64WrapperSmall, tglobaladdr>;
4458 def : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>;
4459 def : ADRP_ADD<A64WrapperSmall, tjumptable>;
4461 //===----------------------------------------------------------------------===//
4462 // GOT access patterns
4463 //===----------------------------------------------------------------------===//
4465 class GOTLoadSmall<SDNode addrfrag>
4466 : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)),
4467 (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>;
4469 def : GOTLoadSmall<texternalsym>;
4470 def : GOTLoadSmall<tglobaladdr>;
4471 def : GOTLoadSmall<tglobaltlsaddr>;
4473 //===----------------------------------------------------------------------===//
4474 // Tail call handling
4475 //===----------------------------------------------------------------------===//
4477 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in {
4479 : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff),
4480 [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>;
4483 : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff),
4484 [(AArch64tcret i64:$dst, (i32 timm:$FPDiff))]>;
4487 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
4489 def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [],
4490 (Bimm bimm_target:$Label)>;
4492 def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [],
4497 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
4498 (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>;
4500 //===----------------------------------------------------------------------===//
4501 // Thread local storage
4502 //===----------------------------------------------------------------------===//
4504 // This is a pseudo-instruction representing the ".tlsdesccall" directive in
4505 // assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the
4506 // current location. It should always be immediately followed by a BLR
4507 // instruction, and is intended solely for relaxation by the linker.
4509 def : Pat<(A64threadpointer), (MRSxi 0xde82)>;
4511 def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> {
4512 let hasSideEffects = 1;
4515 def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var),
4516 [(A64tlsdesc_blr i64:$Rn, tglobaltlsaddr:$Var)]> {
4521 def : Pat<(A64tlsdesc_blr i64:$Rn, texternalsym:$Var),
4522 (TLSDESC_BLRx $Rn, texternalsym:$Var)>;
4524 //===----------------------------------------------------------------------===//
4525 // Bitfield patterns
4526 //===----------------------------------------------------------------------===//
4528 def bfi32_lsb_to_immr : SDNodeXForm<imm, [{
4529 return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64);
4532 def bfi64_lsb_to_immr : SDNodeXForm<imm, [{
4533 return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64);
4536 def bfi_width_to_imms : SDNodeXForm<imm, [{
4537 return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64);
4541 // The simpler patterns deal with cases where no AND mask is actually needed
4542 // (either all bits are used or the low 32 bits are used).
4543 let AddedComplexity = 10 in {
4545 def : Pat<(A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4547 (bfi64_lsb_to_immr (i64 imm:$ImmR)),
4548 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4550 def : Pat<(A64Bfi i32:$src, i32:$Rn, imm:$ImmR, imm:$ImmS),
4552 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4553 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4556 def : Pat<(and (A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4558 (SUBREG_TO_REG (i64 0),
4559 (BFIwwii (EXTRACT_SUBREG $src, sub_32),
4560 (EXTRACT_SUBREG $Rn, sub_32),
4561 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4562 (bfi_width_to_imms (i64 imm:$ImmS))),
4567 //===----------------------------------------------------------------------===//
4568 // Miscellaneous patterns
4569 //===----------------------------------------------------------------------===//
4571 // Truncation from 64 to 32-bits just involves renaming your register.
4572 def : Pat<(i32 (trunc i64:$val)), (EXTRACT_SUBREG $val, sub_32)>;
4574 // Similarly, extension where we don't care about the high bits is
4576 def : Pat<(i64 (anyext i32:$val)),
4577 (INSERT_SUBREG (IMPLICIT_DEF), $val, sub_32)>;
4579 // SELECT instructions providing f128 types need to be handled by a
4580 // pseudo-instruction since the eventual code will need to introduce basic
4581 // blocks and control flow.
4582 def F128CSEL : PseudoInst<(outs FPR128:$Rd),
4583 (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond),
4584 [(set f128:$Rd, (simple_select f128:$Rn, f128:$Rm))]> {
4586 let usesCustomInserter = 1;
4589 //===----------------------------------------------------------------------===//
4590 // Load/store patterns
4591 //===----------------------------------------------------------------------===//
4593 // There are lots of patterns here, because we need to allow at least three
4594 // parameters to vary independently.
4595 // 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ...
4596 // 2. LLVM source: zextloadi8, anyextloadi8, ...
4597 // 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ...
4599 // The biggest problem turns out to be the address-generation variable. At the
4600 // point of instantiation we need to produce two DAGs, one for the pattern and
4601 // one for the instruction. Doing this at the lowest level of classes doesn't
4604 // Consider the simple uimm12 addressing mode, and the desire to match both (add
4605 // GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the
4606 // instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or
4607 // "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this
4608 // operation, and PatFrags are for selection not output.
4610 // As a result, the address-generation patterns are the final
4611 // instantiations. However, we do still need to vary the operand for the address
4612 // further down (At the point we're deciding A64WrapperSmall, we don't know
4613 // the memory width of the operation).
4615 //===------------------------------
4616 // 1. Basic infrastructural defs
4617 //===------------------------------
4619 // First, some simple classes for !foreach and !subst to use:
4630 // You can't use !subst on an actual immediate, but you *can* use it on an
4631 // operand record that happens to match a single immediate. So we do.
4632 def imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>;
4633 def imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>;
4634 def imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>;
4635 def imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>;
4636 def imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>;
4638 // If the low bits of a pointer are known to be 0 then an "or" is just as good
4639 // as addition for computing an offset. This fragment forwards that check for
4641 def add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),
4643 return CurDAG->isBaseWithConstantOffset(SDValue(N, 0));
4646 // Load/store (unsigned immediate) operations with relocations against global
4647 // symbols (for lo12) are only valid if those symbols have correct alignment
4648 // (since the immediate offset is divided by the access scale, it can't have a
4651 // The guaranteed alignment is provided as part of the WrapperSmall
4652 // operation, and checked against one of these.
4653 def any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>;
4654 def min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>;
4655 def min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>;
4656 def min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>;
4657 def min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>;
4659 // "Normal" load/store instructions can be used on atomic operations, provided
4660 // the ordering parameter is at most "monotonic". Anything above that needs
4661 // special handling with acquire/release instructions.
4662 class simple_load<PatFrag base>
4663 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4664 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4667 def atomic_load_simple_i8 : simple_load<atomic_load_8>;
4668 def atomic_load_simple_i16 : simple_load<atomic_load_16>;
4669 def atomic_load_simple_i32 : simple_load<atomic_load_32>;
4670 def atomic_load_simple_i64 : simple_load<atomic_load_64>;
4672 class simple_store<PatFrag base>
4673 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4674 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4677 def atomic_store_simple_i8 : simple_store<atomic_store_8>;
4678 def atomic_store_simple_i16 : simple_store<atomic_store_16>;
4679 def atomic_store_simple_i32 : simple_store<atomic_store_32>;
4680 def atomic_store_simple_i64 : simple_store<atomic_store_64>;
4682 //===------------------------------
4683 // 2. UImm12 and SImm9
4684 //===------------------------------
4686 // These instructions have two operands providing the address so they can be
4687 // treated similarly for most purposes.
4689 //===------------------------------
4690 // 2.1 Base patterns covering extend/truncate semantics
4691 //===------------------------------
4693 // Atomic patterns can be shared between integer operations of all sizes, a
4694 // quick multiclass here allows reuse.
4695 multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4696 dag Offset, dag address, ValueType transty,
4698 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4699 (LOAD Base, Offset)>;
4701 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
4702 (STORE $Rt, Base, Offset)>;
4705 // Instructions accessing a memory chunk smaller than a register (or, in a
4706 // pinch, the same size) have a characteristic set of patterns they want to
4707 // match: extending loads and truncating stores. This class deals with the
4708 // sign-neutral version of those patterns.
4710 // It will be instantiated across multiple addressing-modes.
4711 multiclass ls_small_pats<Instruction LOAD, Instruction STORE,
4712 dag Base, dag Offset,
4713 dag address, ValueType sty>
4714 : ls_atomic_pats<LOAD, STORE, Base, Offset, address, i32, sty> {
4715 def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>;
4717 def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>;
4719 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4720 // register was actually set.
4721 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4722 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4724 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
4725 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4727 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
4728 (STORE $Rt, Base, Offset)>;
4730 // For truncating store from 64-bits, we have to manually tell LLVM to
4731 // ignore the high bits of the x register.
4732 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
4733 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
4736 // Next come patterns for sign-extending loads.
4737 multiclass load_signed_pats<string T, string U, dag Base, dag Offset,
4738 dag address, ValueType sty> {
4739 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
4740 (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>;
4742 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
4743 (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>;
4747 // and finally "natural-width" loads and stores come next.
4748 multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4749 dag Offset, dag address, ValueType sty> {
4750 def : Pat<(sty (load address)), (LOAD Base, Offset)>;
4751 def : Pat<(store sty:$Rt, address), (STORE $Rt, Base, Offset)>;
4754 // Integer operations also get atomic instructions to select for.
4755 multiclass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4756 dag Offset, dag address, ValueType sty>
4757 : ls_neutral_pats<LOAD, STORE, Base, Offset, address, sty>,
4758 ls_atomic_pats<LOAD, STORE, Base, Offset, address, sty, sty>;
4760 //===------------------------------
4761 // 2.2. Addressing-mode instantiations
4762 //===------------------------------
4764 multiclass uimm12_pats<dag address, dag Base, dag Offset> {
4765 defm : ls_small_pats<LS8_LDR, LS8_STR, Base,
4766 !foreach(decls.pattern, Offset,
4767 !subst(OFFSET, byte_uimm12, decls.pattern)),
4768 !foreach(decls.pattern, address,
4769 !subst(OFFSET, byte_uimm12,
4770 !subst(ALIGN, any_align, decls.pattern))),
4772 defm : ls_small_pats<LS16_LDR, LS16_STR, Base,
4773 !foreach(decls.pattern, Offset,
4774 !subst(OFFSET, hword_uimm12, decls.pattern)),
4775 !foreach(decls.pattern, address,
4776 !subst(OFFSET, hword_uimm12,
4777 !subst(ALIGN, min_align2, decls.pattern))),
4779 defm : ls_small_pats<LS32_LDR, LS32_STR, Base,
4780 !foreach(decls.pattern, Offset,
4781 !subst(OFFSET, word_uimm12, decls.pattern)),
4782 !foreach(decls.pattern, address,
4783 !subst(OFFSET, word_uimm12,
4784 !subst(ALIGN, min_align4, decls.pattern))),
4787 defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base,
4788 !foreach(decls.pattern, Offset,
4789 !subst(OFFSET, word_uimm12, decls.pattern)),
4790 !foreach(decls.pattern, address,
4791 !subst(OFFSET, word_uimm12,
4792 !subst(ALIGN, min_align4, decls.pattern))),
4795 defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base,
4796 !foreach(decls.pattern, Offset,
4797 !subst(OFFSET, dword_uimm12, decls.pattern)),
4798 !foreach(decls.pattern, address,
4799 !subst(OFFSET, dword_uimm12,
4800 !subst(ALIGN, min_align8, decls.pattern))),
4803 defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base,
4804 !foreach(decls.pattern, Offset,
4805 !subst(OFFSET, hword_uimm12, decls.pattern)),
4806 !foreach(decls.pattern, address,
4807 !subst(OFFSET, hword_uimm12,
4808 !subst(ALIGN, min_align2, decls.pattern))),
4811 defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base,
4812 !foreach(decls.pattern, Offset,
4813 !subst(OFFSET, word_uimm12, decls.pattern)),
4814 !foreach(decls.pattern, address,
4815 !subst(OFFSET, word_uimm12,
4816 !subst(ALIGN, min_align4, decls.pattern))),
4819 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
4820 !foreach(decls.pattern, Offset,
4821 !subst(OFFSET, dword_uimm12, decls.pattern)),
4822 !foreach(decls.pattern, address,
4823 !subst(OFFSET, dword_uimm12,
4824 !subst(ALIGN, min_align8, decls.pattern))),
4827 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
4828 !foreach(decls.pattern, Offset,
4829 !subst(OFFSET, qword_uimm12, decls.pattern)),
4830 !foreach(decls.pattern, address,
4831 !subst(OFFSET, qword_uimm12,
4832 !subst(ALIGN, min_align16, decls.pattern))),
4835 defm : load_signed_pats<"B", "", Base,
4836 !foreach(decls.pattern, Offset,
4837 !subst(OFFSET, byte_uimm12, decls.pattern)),
4838 !foreach(decls.pattern, address,
4839 !subst(OFFSET, byte_uimm12,
4840 !subst(ALIGN, any_align, decls.pattern))),
4843 defm : load_signed_pats<"H", "", Base,
4844 !foreach(decls.pattern, Offset,
4845 !subst(OFFSET, hword_uimm12, decls.pattern)),
4846 !foreach(decls.pattern, address,
4847 !subst(OFFSET, hword_uimm12,
4848 !subst(ALIGN, min_align2, decls.pattern))),
4851 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
4852 !subst(OFFSET, word_uimm12,
4853 !subst(ALIGN, min_align4, decls.pattern)))),
4854 (LDRSWx Base, !foreach(decls.pattern, Offset,
4855 !subst(OFFSET, word_uimm12, decls.pattern)))>;
4858 // Straightforward patterns of last resort: a pointer with or without an
4859 // appropriate offset.
4860 defm : uimm12_pats<(i64 i64:$Rn), (i64 i64:$Rn), (i64 0)>;
4861 defm : uimm12_pats<(add i64:$Rn, OFFSET:$UImm12),
4862 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
4864 // The offset could be hidden behind an "or", of course:
4865 defm : uimm12_pats<(add_like_or i64:$Rn, OFFSET:$UImm12),
4866 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
4868 // Global addresses under the small-absolute model should use these
4869 // instructions. There are ELF relocations specifically for it.
4870 defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN),
4871 (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>;
4873 defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12,
4875 (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>;
4877 // External symbols that make it this far should also get standard relocations.
4878 defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12,
4880 (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>;
4882 defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
4883 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
4885 // We also want to use uimm12 instructions for local variables at the moment.
4886 def tframeindex_XFORM : SDNodeXForm<frameindex, [{
4887 int FI = cast<FrameIndexSDNode>(N)->getIndex();
4888 return CurDAG->getTargetFrameIndex(FI, MVT::i64);
4891 defm : uimm12_pats<(i64 frameindex:$Rn),
4892 (tframeindex_XFORM tframeindex:$Rn), (i64 0)>;
4894 // These can be much simpler than uimm12 because we don't to change the operand
4895 // type (e.g. LDURB and LDURH take the same operands).
4896 multiclass simm9_pats<dag address, dag Base, dag Offset> {
4897 defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>;
4898 defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>;
4900 defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address, i32>;
4901 defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address, i64>;
4903 defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address, f16>;
4904 defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address, f32>;
4905 defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address, f64>;
4906 defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address,
4909 def : Pat<(i64 (zextloadi32 address)),
4910 (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>;
4912 def : Pat<(truncstorei32 i64:$Rt, address),
4913 (LS32_STUR (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
4915 defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>;
4916 defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>;
4917 def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>;
4920 defm : simm9_pats<(add i64:$Rn, simm9:$SImm9),
4921 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
4923 defm : simm9_pats<(add_like_or i64:$Rn, simm9:$SImm9),
4924 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
4927 //===------------------------------
4928 // 3. Register offset patterns
4929 //===------------------------------
4931 // Atomic patterns can be shared between integer operations of all sizes, a
4932 // quick multiclass here allows reuse.
4933 multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4934 dag Offset, dag Extend, dag address,
4935 ValueType transty, ValueType sty> {
4936 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4937 (LOAD Base, Offset, Extend)>;
4939 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
4940 (STORE $Rt, Base, Offset, Extend)>;
4943 // The register offset instructions take three operands giving the instruction,
4944 // and have an annoying split between instructions where Rm is 32-bit and
4945 // 64-bit. So we need a special hierarchy to describe them. Other than that the
4946 // same operations should be supported as for simm9 and uimm12 addressing.
4948 multiclass ro_small_pats<Instruction LOAD, Instruction STORE,
4949 dag Base, dag Offset, dag Extend,
4950 dag address, ValueType sty>
4951 : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, i32, sty> {
4952 def : Pat<(!cast<SDNode>(zextload # sty) address),
4953 (LOAD Base, Offset, Extend)>;
4955 def : Pat<(!cast<SDNode>(extload # sty) address),
4956 (LOAD Base, Offset, Extend)>;
4958 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4959 // register was actually set.
4960 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4961 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
4963 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
4964 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
4966 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
4967 (STORE $Rt, Base, Offset, Extend)>;
4969 // For truncating store from 64-bits, we have to manually tell LLVM to
4970 // ignore the high bits of the x register.
4971 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
4972 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset, Extend)>;
4976 // Next come patterns for sign-extending loads.
4977 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
4978 dag address, ValueType sty> {
4979 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
4980 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
4981 Base, Offset, Extend)>;
4983 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
4984 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
4985 Base, Offset, Extend)>;
4988 // and finally "natural-width" loads and stores come next.
4989 multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE,
4990 dag Base, dag Offset, dag Extend, dag address,
4992 def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>;
4993 def : Pat<(store sty:$Rt, address),
4994 (STORE $Rt, Base, Offset, Extend)>;
4997 multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE,
4998 dag Base, dag Offset, dag Extend, dag address,
5000 : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, sty>,
5001 ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, sty, sty>;
5003 multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset,
5005 defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"),
5006 !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"),
5007 Base, Offset, Extend,
5008 !foreach(decls.pattern, address,
5009 !subst(SHIFT, imm_eq0, decls.pattern)),
5011 defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"),
5012 !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"),
5013 Base, Offset, Extend,
5014 !foreach(decls.pattern, address,
5015 !subst(SHIFT, imm_eq1, decls.pattern)),
5017 defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5018 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5019 Base, Offset, Extend,
5020 !foreach(decls.pattern, address,
5021 !subst(SHIFT, imm_eq2, decls.pattern)),
5024 defm : ro_int_neutral_pats<
5025 !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5026 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5027 Base, Offset, Extend,
5028 !foreach(decls.pattern, address,
5029 !subst(SHIFT, imm_eq2, decls.pattern)),
5032 defm : ro_int_neutral_pats<
5033 !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
5034 !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
5035 Base, Offset, Extend,
5036 !foreach(decls.pattern, address,
5037 !subst(SHIFT, imm_eq3, decls.pattern)),
5040 defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"),
5041 !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"),
5042 Base, Offset, Extend,
5043 !foreach(decls.pattern, address,
5044 !subst(SHIFT, imm_eq1, decls.pattern)),
5047 defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"),
5048 !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"),
5049 Base, Offset, Extend,
5050 !foreach(decls.pattern, address,
5051 !subst(SHIFT, imm_eq2, decls.pattern)),
5054 defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"),
5055 !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"),
5056 Base, Offset, Extend,
5057 !foreach(decls.pattern, address,
5058 !subst(SHIFT, imm_eq3, decls.pattern)),
5061 defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"),
5062 !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"),
5063 Base, Offset, Extend,
5064 !foreach(decls.pattern, address,
5065 !subst(SHIFT, imm_eq4, decls.pattern)),
5068 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,
5069 !foreach(decls.pattern, address,
5070 !subst(SHIFT, imm_eq0, decls.pattern)),
5073 defm : ro_signed_pats<"H", Rm, Base, Offset, Extend,
5074 !foreach(decls.pattern, address,
5075 !subst(SHIFT, imm_eq1, decls.pattern)),
5078 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
5079 !subst(SHIFT, imm_eq2, decls.pattern))),
5080 (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset")
5081 Base, Offset, Extend)>;
5085 // Finally we're in a position to tell LLVM exactly what addresses are reachable
5086 // using register-offset instructions. Essentially a base plus a possibly
5087 // extended, possibly shifted (by access size) offset.
5089 defm : regoff_pats<"Wm", (add i64:$Rn, (sext i32:$Rm)),
5090 (i64 i64:$Rn), (i32 i32:$Rm), (i64 6)>;
5092 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (sext i32:$Rm), SHIFT)),
5093 (i64 i64:$Rn), (i32 i32:$Rm), (i64 7)>;
5095 defm : regoff_pats<"Wm", (add i64:$Rn, (zext i32:$Rm)),
5096 (i64 i64:$Rn), (i32 i32:$Rm), (i64 2)>;
5098 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (zext i32:$Rm), SHIFT)),
5099 (i64 i64:$Rn), (i32 i32:$Rm), (i64 3)>;
5101 defm : regoff_pats<"Xm", (add i64:$Rn, i64:$Rm),
5102 (i64 i64:$Rn), (i64 i64:$Rm), (i64 2)>;
5104 defm : regoff_pats<"Xm", (add i64:$Rn, (shl i64:$Rm, SHIFT)),
5105 (i64 i64:$Rn), (i64 i64:$Rm), (i64 3)>;