1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
18 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
19 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
20 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
21 def HasNEON : Predicate<"Subtarget->hasNEON()">,
22 AssemblerPredicate<"FeatureNEON", "neon">;
23 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
24 AssemblerPredicate<"FeatureCrypto", "crypto">;
25 def HasCRC : Predicate<"Subtarget->hasCRC()">,
26 AssemblerPredicate<"FeatureCRC", "crc">;
27 def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">;
28 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
29 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
30 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
32 //===----------------------------------------------------------------------===//
33 // AArch64-specific DAG Nodes.
36 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
37 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
43 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
49 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
50 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
57 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
58 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
60 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
61 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
62 SDTCisVT<2, OtherVT>]>;
65 def SDT_AArch64CSel : SDTypeProfile<1, 4,
70 def SDT_AArch64CCMP : SDTypeProfile<1, 5,
77 def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
84 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
87 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
88 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
89 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
92 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
93 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
94 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
95 SDTCisInt<2>, SDTCisInt<3>]>;
96 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
97 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
98 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
99 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
101 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
102 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
103 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
104 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
106 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
109 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
110 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
112 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
114 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
117 // Generates the general dynamic sequences, i.e.
118 // adrp x0, :tlsdesc:var
119 // ldr x1, [x0, #:tlsdesc_lo12:var]
120 // add x0, x0, #:tlsdesc_lo12:var
124 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
125 // number of operands (the variable)
126 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
129 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
130 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
131 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
132 SDTCisSameAs<1, 4>]>;
136 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
137 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
138 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
139 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
140 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
141 [SDNPHasChain, SDNPOutGlue]>;
142 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
143 SDCallSeqEnd<[ SDTCisVT<0, i32>,
145 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
146 def AArch64call : SDNode<"AArch64ISD::CALL",
147 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
150 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
152 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
154 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
156 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
158 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
162 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
163 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
164 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
165 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
166 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
167 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
168 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
169 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
170 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
172 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
173 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
175 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
176 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
178 def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>;
179 def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>;
180 def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>;
182 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
184 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
186 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
187 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
188 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
189 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
190 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
192 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
193 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
194 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
195 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
196 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
197 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
199 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
200 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
201 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
202 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
203 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
204 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
205 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
207 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
208 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
209 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
210 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
212 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
213 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
214 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
215 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
216 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
217 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
218 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
219 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
221 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
222 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
223 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
225 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
226 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
227 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
228 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
229 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
231 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
232 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
233 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
235 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
236 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
237 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
238 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
239 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
240 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
241 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
243 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
244 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
245 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
246 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
247 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
249 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
250 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
252 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
254 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
255 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
257 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
258 [SDNPHasChain, SDNPSideEffect]>;
260 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
261 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
263 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
264 SDT_AArch64TLSDescCallSeq,
265 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
269 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
270 SDT_AArch64WrapperLarge>;
272 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
274 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
275 SDTCisSameAs<1, 2>]>;
276 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
277 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
279 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
280 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
281 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
282 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
283 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
284 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
286 //===----------------------------------------------------------------------===//
288 //===----------------------------------------------------------------------===//
290 // AArch64 Instruction Predicate Definitions.
292 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
293 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
294 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
295 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
296 def ForCodeSize : Predicate<"ForCodeSize">;
297 def NotForCodeSize : Predicate<"!ForCodeSize">;
299 include "AArch64InstrFormats.td"
301 //===----------------------------------------------------------------------===//
303 //===----------------------------------------------------------------------===//
304 // Miscellaneous instructions.
305 //===----------------------------------------------------------------------===//
307 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
308 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
309 [(AArch64callseq_start timm:$amt)]>;
310 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
311 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
312 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
314 let isReMaterializable = 1, isCodeGenOnly = 1 in {
315 // FIXME: The following pseudo instructions are only needed because remat
316 // cannot handle multiple instructions. When that changes, they can be
317 // removed, along with the AArch64Wrapper node.
319 let AddedComplexity = 10 in
320 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
321 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
324 // The MOVaddr instruction should match only when the add is not folded
325 // into a load or store address.
327 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
328 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
329 tglobaladdr:$low))]>,
330 Sched<[WriteAdrAdr]>;
332 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
333 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
335 Sched<[WriteAdrAdr]>;
337 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
338 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
340 Sched<[WriteAdrAdr]>;
342 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
343 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
344 tblockaddress:$low))]>,
345 Sched<[WriteAdrAdr]>;
347 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
348 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
349 tglobaltlsaddr:$low))]>,
350 Sched<[WriteAdrAdr]>;
352 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
353 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
354 texternalsym:$low))]>,
355 Sched<[WriteAdrAdr]>;
357 } // isReMaterializable, isCodeGenOnly
359 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
360 (LOADgot tglobaltlsaddr:$addr)>;
362 def : Pat<(AArch64LOADgot texternalsym:$addr),
363 (LOADgot texternalsym:$addr)>;
365 def : Pat<(AArch64LOADgot tconstpool:$addr),
366 (LOADgot tconstpool:$addr)>;
368 //===----------------------------------------------------------------------===//
369 // System instructions.
370 //===----------------------------------------------------------------------===//
372 def HINT : HintI<"hint">;
373 def : InstAlias<"nop", (HINT 0b000)>;
374 def : InstAlias<"yield",(HINT 0b001)>;
375 def : InstAlias<"wfe", (HINT 0b010)>;
376 def : InstAlias<"wfi", (HINT 0b011)>;
377 def : InstAlias<"sev", (HINT 0b100)>;
378 def : InstAlias<"sevl", (HINT 0b101)>;
380 // As far as LLVM is concerned this writes to the system's exclusive monitors.
381 let mayLoad = 1, mayStore = 1 in
382 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
384 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
385 // model patterns with sufficiently fine granularity.
386 let mayLoad = ?, mayStore = ? in {
387 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
388 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
390 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
391 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
393 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
394 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
397 def : InstAlias<"clrex", (CLREX 0xf)>;
398 def : InstAlias<"isb", (ISB 0xf)>;
402 def MSRpstateImm1 : MSRpstateImm0_1;
403 def MSRpstateImm4 : MSRpstateImm0_15;
405 // The thread pointer (on Linux, at least, where this has been implemented) is
407 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
409 // The cycle counter PMC register is PMCCNTR_EL0.
410 let Predicates = [HasPerfMon] in
411 def : Pat<(readcyclecounter), (MRS 0xdce8)>;
413 // Generic system instructions
414 def SYSxt : SystemXtI<0, "sys">;
415 def SYSLxt : SystemLXtI<1, "sysl">;
417 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
418 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
419 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
421 //===----------------------------------------------------------------------===//
422 // Move immediate instructions.
423 //===----------------------------------------------------------------------===//
425 defm MOVK : InsertImmediate<0b11, "movk">;
426 defm MOVN : MoveImmediate<0b00, "movn">;
428 let PostEncoderMethod = "fixMOVZ" in
429 defm MOVZ : MoveImmediate<0b10, "movz">;
431 // First group of aliases covers an implicit "lsl #0".
432 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
433 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
434 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
435 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
436 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
437 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
439 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
440 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
441 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
442 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
443 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
445 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
446 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
447 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
448 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
450 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
451 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
452 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
453 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
455 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
456 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
458 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
459 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
461 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
462 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
464 // Final group of aliases covers true "mov $Rd, $imm" cases.
465 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
466 int width, int shift> {
467 def _asmoperand : AsmOperandClass {
468 let Name = basename # width # "_lsl" # shift # "MovAlias";
469 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
471 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
474 def _movimm : Operand<i32> {
475 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
478 def : InstAlias<"mov $Rd, $imm",
479 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
482 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
483 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
485 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
486 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
487 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
488 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
490 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
491 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
493 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
494 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
495 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
496 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
498 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
499 isAsCheapAsAMove = 1 in {
500 // FIXME: The following pseudo instructions are only needed because remat
501 // cannot handle multiple instructions. When that changes, we can select
502 // directly to the real instructions and get rid of these pseudos.
505 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
506 [(set GPR32:$dst, imm:$src)]>,
509 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
510 [(set GPR64:$dst, imm:$src)]>,
512 } // isReMaterializable, isCodeGenOnly
514 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
515 // eventual expansion code fewer bits to worry about getting right. Marshalling
516 // the types is a little tricky though:
517 def i64imm_32bit : ImmLeaf<i64, [{
518 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
521 def trunc_imm : SDNodeXForm<imm, [{
522 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32);
525 def : Pat<(i64 i64imm_32bit:$src),
526 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
528 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
529 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
530 return CurDAG->getTargetConstant(
531 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
534 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
535 return CurDAG->getTargetConstant(
536 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
540 def : Pat<(f32 fpimm:$in),
541 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
542 def : Pat<(f64 fpimm:$in),
543 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
546 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
548 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
549 tglobaladdr:$g1, tglobaladdr:$g0),
550 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
551 tglobaladdr:$g2, 32),
552 tglobaladdr:$g1, 16),
553 tglobaladdr:$g0, 0)>;
555 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
556 tblockaddress:$g1, tblockaddress:$g0),
557 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
558 tblockaddress:$g2, 32),
559 tblockaddress:$g1, 16),
560 tblockaddress:$g0, 0)>;
562 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
563 tconstpool:$g1, tconstpool:$g0),
564 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
569 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
570 tjumptable:$g1, tjumptable:$g0),
571 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
577 //===----------------------------------------------------------------------===//
578 // Arithmetic instructions.
579 //===----------------------------------------------------------------------===//
581 // Add/subtract with carry.
582 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
583 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
585 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
586 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
587 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
588 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
591 defm ADD : AddSub<0, "add", "sub", add>;
592 defm SUB : AddSub<1, "sub", "add">;
594 def : InstAlias<"mov $dst, $src",
595 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
596 def : InstAlias<"mov $dst, $src",
597 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
598 def : InstAlias<"mov $dst, $src",
599 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
600 def : InstAlias<"mov $dst, $src",
601 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
603 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;
604 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">;
606 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
607 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
608 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
609 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
610 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
611 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
612 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
613 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
614 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
615 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
616 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
617 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
618 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
619 let AddedComplexity = 1 in {
620 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
621 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
622 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
623 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
626 // Because of the immediate format for add/sub-imm instructions, the
627 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
628 // These patterns capture that transformation.
629 let AddedComplexity = 1 in {
630 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
631 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
632 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
633 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
634 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
635 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
636 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
637 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
640 // Because of the immediate format for add/sub-imm instructions, the
641 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
642 // These patterns capture that transformation.
643 let AddedComplexity = 1 in {
644 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
645 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
646 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
647 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
648 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
649 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
650 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
651 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
654 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
655 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
656 def : InstAlias<"neg $dst, $src$shift",
657 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
658 def : InstAlias<"neg $dst, $src$shift",
659 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
661 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
662 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
663 def : InstAlias<"negs $dst, $src$shift",
664 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
665 def : InstAlias<"negs $dst, $src$shift",
666 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
669 // Unsigned/Signed divide
670 defm UDIV : Div<0, "udiv", udiv>;
671 defm SDIV : Div<1, "sdiv", sdiv>;
672 let isCodeGenOnly = 1 in {
673 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
674 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
678 defm ASRV : Shift<0b10, "asr", sra>;
679 defm LSLV : Shift<0b00, "lsl", shl>;
680 defm LSRV : Shift<0b01, "lsr", srl>;
681 defm RORV : Shift<0b11, "ror", rotr>;
683 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
684 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
685 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
686 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
687 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
688 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
689 def : ShiftAlias<"rorv", RORVWr, GPR32>;
690 def : ShiftAlias<"rorv", RORVXr, GPR64>;
693 let AddedComplexity = 7 in {
694 defm MADD : MulAccum<0, "madd", add>;
695 defm MSUB : MulAccum<1, "msub", sub>;
697 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
698 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
699 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
700 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
702 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
703 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
704 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
705 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
706 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
707 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
708 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
709 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
710 } // AddedComplexity = 7
712 let AddedComplexity = 5 in {
713 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
714 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
715 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
716 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
718 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
719 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
720 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
721 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
723 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
724 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
725 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
726 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
727 } // AddedComplexity = 5
729 def : MulAccumWAlias<"mul", MADDWrrr>;
730 def : MulAccumXAlias<"mul", MADDXrrr>;
731 def : MulAccumWAlias<"mneg", MSUBWrrr>;
732 def : MulAccumXAlias<"mneg", MSUBXrrr>;
733 def : WideMulAccumAlias<"smull", SMADDLrrr>;
734 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
735 def : WideMulAccumAlias<"umull", UMADDLrrr>;
736 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
739 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
740 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
743 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
744 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
745 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
746 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
748 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
749 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
750 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
751 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
754 defm CAS : CompareAndSwap<0, 0, "">;
755 defm CASA : CompareAndSwap<1, 0, "a">;
756 defm CASL : CompareAndSwap<0, 1, "l">;
757 defm CASAL : CompareAndSwap<1, 1, "al">;
760 defm CASP : CompareAndSwapPair<0, 0, "">;
761 defm CASPA : CompareAndSwapPair<1, 0, "a">;
762 defm CASPL : CompareAndSwapPair<0, 1, "l">;
763 defm CASPAL : CompareAndSwapPair<1, 1, "al">;
766 defm SWP : Swap<0, 0, "">;
767 defm SWPA : Swap<1, 0, "a">;
768 defm SWPL : Swap<0, 1, "l">;
769 defm SWPAL : Swap<1, 1, "al">;
771 // v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)
772 defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
773 defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
774 defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;
775 defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;
777 defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">;
778 defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">;
779 defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">;
780 defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">;
782 defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">;
783 defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">;
784 defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">;
785 defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">;
787 defm LDSET : LDOPregister<0b011, "set", 0, 0, "">;
788 defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">;
789 defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">;
790 defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">;
792 defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">;
793 defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">;
794 defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;
795 defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;
797 defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;
798 defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;
799 defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;
800 defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;
802 defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">;
803 defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">;
804 defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">;
805 defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">;
807 defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">;
808 defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">;
809 defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">;
810 defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">;
812 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
813 defm : STOPregister<"stadd","LDADD">; // STADDx
814 defm : STOPregister<"stclr","LDCLR">; // STCLRx
815 defm : STOPregister<"steor","LDEOR">; // STEORx
816 defm : STOPregister<"stset","LDSET">; // STSETx
817 defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx
818 defm : STOPregister<"stsmin","LDSMIN">;// STSMINx
819 defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
820 defm : STOPregister<"stumin","LDUMIN">;// STUMINx
822 //===----------------------------------------------------------------------===//
823 // Logical instructions.
824 //===----------------------------------------------------------------------===//
827 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
828 defm AND : LogicalImm<0b00, "and", and, "bic">;
829 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
830 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
832 // FIXME: these aliases *are* canonical sometimes (when movz can't be
833 // used). Actually, it seems to be working right now, but putting logical_immXX
834 // here is a bit dodgy on the AsmParser side too.
835 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
836 logical_imm32:$imm), 0>;
837 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
838 logical_imm64:$imm), 0>;
842 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
843 defm BICS : LogicalRegS<0b11, 1, "bics",
844 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
845 defm AND : LogicalReg<0b00, 0, "and", and>;
846 defm BIC : LogicalReg<0b00, 1, "bic",
847 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
848 defm EON : LogicalReg<0b10, 1, "eon",
849 BinOpFrag<(not (xor node:$LHS, node:$RHS))>>;
850 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
851 defm ORN : LogicalReg<0b01, 1, "orn",
852 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
853 defm ORR : LogicalReg<0b01, 0, "orr", or>;
855 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
856 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
858 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
859 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
861 def : InstAlias<"mvn $Wd, $Wm$sh",
862 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
863 def : InstAlias<"mvn $Xd, $Xm$sh",
864 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
866 def : InstAlias<"tst $src1, $src2",
867 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
868 def : InstAlias<"tst $src1, $src2",
869 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
871 def : InstAlias<"tst $src1, $src2",
872 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
873 def : InstAlias<"tst $src1, $src2",
874 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
876 def : InstAlias<"tst $src1, $src2$sh",
877 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
878 def : InstAlias<"tst $src1, $src2$sh",
879 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
882 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
883 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
886 //===----------------------------------------------------------------------===//
887 // One operand data processing instructions.
888 //===----------------------------------------------------------------------===//
890 defm CLS : OneOperandData<0b101, "cls">;
891 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
892 defm RBIT : OneOperandData<0b000, "rbit">;
894 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
895 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
897 def REV16Wr : OneWRegData<0b001, "rev16",
898 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
899 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
901 def : Pat<(cttz GPR32:$Rn),
902 (CLZWr (RBITWr GPR32:$Rn))>;
903 def : Pat<(cttz GPR64:$Rn),
904 (CLZXr (RBITXr GPR64:$Rn))>;
905 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
908 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
912 // Unlike the other one operand instructions, the instructions with the "rev"
913 // mnemonic do *not* just different in the size bit, but actually use different
914 // opcode bits for the different sizes.
915 def REVWr : OneWRegData<0b010, "rev", bswap>;
916 def REVXr : OneXRegData<0b011, "rev", bswap>;
917 def REV32Xr : OneXRegData<0b010, "rev32",
918 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
920 def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
922 // The bswap commutes with the rotr so we want a pattern for both possible
924 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
925 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
927 //===----------------------------------------------------------------------===//
928 // Bitfield immediate extraction instruction.
929 //===----------------------------------------------------------------------===//
930 let hasSideEffects = 0 in
931 defm EXTR : ExtractImm<"extr">;
932 def : InstAlias<"ror $dst, $src, $shift",
933 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
934 def : InstAlias<"ror $dst, $src, $shift",
935 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
937 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
938 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
939 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
940 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
942 //===----------------------------------------------------------------------===//
943 // Other bitfield immediate instructions.
944 //===----------------------------------------------------------------------===//
945 let hasSideEffects = 0 in {
946 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
947 defm SBFM : BitfieldImm<0b00, "sbfm">;
948 defm UBFM : BitfieldImm<0b10, "ubfm">;
951 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
952 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
953 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
956 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
957 uint64_t enc = 31 - N->getZExtValue();
958 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
961 // min(7, 31 - shift_amt)
962 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
963 uint64_t enc = 31 - N->getZExtValue();
964 enc = enc > 7 ? 7 : enc;
965 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
968 // min(15, 31 - shift_amt)
969 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
970 uint64_t enc = 31 - N->getZExtValue();
971 enc = enc > 15 ? 15 : enc;
972 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
975 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
976 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
977 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
980 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
981 uint64_t enc = 63 - N->getZExtValue();
982 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
985 // min(7, 63 - shift_amt)
986 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
987 uint64_t enc = 63 - N->getZExtValue();
988 enc = enc > 7 ? 7 : enc;
989 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
992 // min(15, 63 - shift_amt)
993 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
994 uint64_t enc = 63 - N->getZExtValue();
995 enc = enc > 15 ? 15 : enc;
996 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
999 // min(31, 63 - shift_amt)
1000 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
1001 uint64_t enc = 63 - N->getZExtValue();
1002 enc = enc > 31 ? 31 : enc;
1003 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1006 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
1007 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
1008 (i64 (i32shift_b imm0_31:$imm)))>;
1009 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
1010 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
1011 (i64 (i64shift_b imm0_63:$imm)))>;
1013 let AddedComplexity = 10 in {
1014 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
1015 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1016 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
1017 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1020 def : InstAlias<"asr $dst, $src, $shift",
1021 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1022 def : InstAlias<"asr $dst, $src, $shift",
1023 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1024 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1025 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1026 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1027 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1028 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1030 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
1031 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1032 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
1033 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1035 def : InstAlias<"lsr $dst, $src, $shift",
1036 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1037 def : InstAlias<"lsr $dst, $src, $shift",
1038 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1039 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1040 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1041 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1042 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1043 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1045 //===----------------------------------------------------------------------===//
1046 // Conditional comparison instructions.
1047 //===----------------------------------------------------------------------===//
1048 defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>;
1049 defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>;
1051 //===----------------------------------------------------------------------===//
1052 // Conditional select instructions.
1053 //===----------------------------------------------------------------------===//
1054 defm CSEL : CondSelect<0, 0b00, "csel">;
1056 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
1057 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1058 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1059 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1061 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1062 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1063 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1064 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1065 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1066 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1067 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1068 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1069 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1070 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1071 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1072 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1074 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
1075 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
1076 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
1077 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
1078 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
1079 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
1080 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
1081 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
1083 // The inverse of the condition code from the alias instruction is what is used
1084 // in the aliased instruction. The parser all ready inverts the condition code
1085 // for these aliases.
1086 def : InstAlias<"cset $dst, $cc",
1087 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1088 def : InstAlias<"cset $dst, $cc",
1089 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1091 def : InstAlias<"csetm $dst, $cc",
1092 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1093 def : InstAlias<"csetm $dst, $cc",
1094 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1096 def : InstAlias<"cinc $dst, $src, $cc",
1097 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1098 def : InstAlias<"cinc $dst, $src, $cc",
1099 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1101 def : InstAlias<"cinv $dst, $src, $cc",
1102 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1103 def : InstAlias<"cinv $dst, $src, $cc",
1104 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1106 def : InstAlias<"cneg $dst, $src, $cc",
1107 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1108 def : InstAlias<"cneg $dst, $src, $cc",
1109 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1111 //===----------------------------------------------------------------------===//
1112 // PC-relative instructions.
1113 //===----------------------------------------------------------------------===//
1114 let isReMaterializable = 1 in {
1115 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1116 def ADR : ADRI<0, "adr", adrlabel, []>;
1117 } // hasSideEffects = 0
1119 def ADRP : ADRI<1, "adrp", adrplabel,
1120 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1121 } // isReMaterializable = 1
1123 // page address of a constant pool entry, block address
1124 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1125 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1127 //===----------------------------------------------------------------------===//
1128 // Unconditional branch (register) instructions.
1129 //===----------------------------------------------------------------------===//
1131 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1132 def RET : BranchReg<0b0010, "ret", []>;
1133 def DRPS : SpecialReturn<0b0101, "drps">;
1134 def ERET : SpecialReturn<0b0100, "eret">;
1135 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1137 // Default to the LR register.
1138 def : InstAlias<"ret", (RET LR)>;
1140 let isCall = 1, Defs = [LR], Uses = [SP] in {
1141 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1144 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1145 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1146 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1148 // Create a separate pseudo-instruction for codegen to use so that we don't
1149 // flag lr as used in every function. It'll be restored before the RET by the
1150 // epilogue if it's legitimately used.
1151 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1152 let isTerminator = 1;
1157 // This is a directive-like pseudo-instruction. The purpose is to insert an
1158 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1159 // (which in the usual case is a BLR).
1160 let hasSideEffects = 1 in
1161 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1162 let AsmString = ".tlsdesccall $sym";
1165 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
1166 // FIXME: can "hasSideEffects be dropped?
1167 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
1168 isCodeGenOnly = 1 in
1170 : Pseudo<(outs), (ins i64imm:$sym),
1171 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>;
1172 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
1173 (TLSDESC_CALLSEQ texternalsym:$sym)>;
1175 //===----------------------------------------------------------------------===//
1176 // Conditional branch (immediate) instruction.
1177 //===----------------------------------------------------------------------===//
1178 def Bcc : BranchCond;
1180 //===----------------------------------------------------------------------===//
1181 // Compare-and-branch instructions.
1182 //===----------------------------------------------------------------------===//
1183 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1184 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1186 //===----------------------------------------------------------------------===//
1187 // Test-bit-and-branch instructions.
1188 //===----------------------------------------------------------------------===//
1189 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1190 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1192 //===----------------------------------------------------------------------===//
1193 // Unconditional branch (immediate) instructions.
1194 //===----------------------------------------------------------------------===//
1195 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1196 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1197 } // isBranch, isTerminator, isBarrier
1199 let isCall = 1, Defs = [LR], Uses = [SP] in {
1200 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1202 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1204 //===----------------------------------------------------------------------===//
1205 // Exception generation instructions.
1206 //===----------------------------------------------------------------------===//
1207 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1208 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1209 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1210 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1211 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1212 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1213 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1214 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1216 // DCPSn defaults to an immediate operand of zero if unspecified.
1217 def : InstAlias<"dcps1", (DCPS1 0)>;
1218 def : InstAlias<"dcps2", (DCPS2 0)>;
1219 def : InstAlias<"dcps3", (DCPS3 0)>;
1221 //===----------------------------------------------------------------------===//
1222 // Load instructions.
1223 //===----------------------------------------------------------------------===//
1225 // Pair (indexed, offset)
1226 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1227 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1228 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1229 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1230 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1232 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1234 // Pair (pre-indexed)
1235 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1236 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1237 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1238 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1239 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1241 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1243 // Pair (post-indexed)
1244 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1245 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1246 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1247 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1248 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1250 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1253 // Pair (no allocate)
1254 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1255 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1256 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1257 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1258 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1261 // (register offset)
1265 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1266 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1267 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1268 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1271 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1272 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1273 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1274 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1275 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1277 // Load sign-extended half-word
1278 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1279 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1281 // Load sign-extended byte
1282 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1283 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1285 // Load sign-extended word
1286 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1289 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1291 // For regular load, we do not have any alignment requirement.
1292 // Thus, it is safe to directly map the vector loads with interesting
1293 // addressing modes.
1294 // FIXME: We could do the same for bitconvert to floating point vectors.
1295 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1296 ValueType ScalTy, ValueType VecTy,
1297 Instruction LOADW, Instruction LOADX,
1299 def : Pat<(VecTy (scalar_to_vector (ScalTy
1300 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1301 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1302 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1305 def : Pat<(VecTy (scalar_to_vector (ScalTy
1306 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1307 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1308 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1312 let AddedComplexity = 10 in {
1313 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1314 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1316 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1317 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1319 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1320 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1322 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1323 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1325 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1326 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1328 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1330 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1333 def : Pat <(v1i64 (scalar_to_vector (i64
1334 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1335 ro_Wextend64:$extend))))),
1336 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1338 def : Pat <(v1i64 (scalar_to_vector (i64
1339 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1340 ro_Xextend64:$extend))))),
1341 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1344 // Match all load 64 bits width whose type is compatible with FPR64
1345 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1346 Instruction LOADW, Instruction LOADX> {
1348 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1349 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1351 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1352 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1355 let AddedComplexity = 10 in {
1356 let Predicates = [IsLE] in {
1357 // We must do vector loads with LD1 in big-endian.
1358 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1359 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1360 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1361 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1362 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1365 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1366 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1368 // Match all load 128 bits width whose type is compatible with FPR128
1369 let Predicates = [IsLE] in {
1370 // We must do vector loads with LD1 in big-endian.
1371 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1372 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1373 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1374 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1375 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1376 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1377 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1379 } // AddedComplexity = 10
1382 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1383 Instruction INSTW, Instruction INSTX> {
1384 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1385 (SUBREG_TO_REG (i64 0),
1386 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1389 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1390 (SUBREG_TO_REG (i64 0),
1391 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1395 let AddedComplexity = 10 in {
1396 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1397 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1398 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1400 // zextloadi1 -> zextloadi8
1401 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1403 // extload -> zextload
1404 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1405 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1406 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1408 // extloadi1 -> zextloadi8
1409 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1414 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1415 Instruction INSTW, Instruction INSTX> {
1416 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1417 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1419 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1420 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1424 let AddedComplexity = 10 in {
1425 // extload -> zextload
1426 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1427 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1428 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1430 // zextloadi1 -> zextloadi8
1431 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1435 // (unsigned immediate)
1437 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1439 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1440 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1442 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1443 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1445 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1446 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1447 [(set (f16 FPR16:$Rt),
1448 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1449 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1450 [(set (f32 FPR32:$Rt),
1451 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1452 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1453 [(set (f64 FPR64:$Rt),
1454 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1455 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1456 [(set (f128 FPR128:$Rt),
1457 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1459 // For regular load, we do not have any alignment requirement.
1460 // Thus, it is safe to directly map the vector loads with interesting
1461 // addressing modes.
1462 // FIXME: We could do the same for bitconvert to floating point vectors.
1463 def : Pat <(v8i8 (scalar_to_vector (i32
1464 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1465 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1466 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1467 def : Pat <(v16i8 (scalar_to_vector (i32
1468 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1469 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1470 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1471 def : Pat <(v4i16 (scalar_to_vector (i32
1472 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1473 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1474 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1475 def : Pat <(v8i16 (scalar_to_vector (i32
1476 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1477 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1478 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1479 def : Pat <(v2i32 (scalar_to_vector (i32
1480 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1481 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1482 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1483 def : Pat <(v4i32 (scalar_to_vector (i32
1484 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1485 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1486 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1487 def : Pat <(v1i64 (scalar_to_vector (i64
1488 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1489 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1490 def : Pat <(v2i64 (scalar_to_vector (i64
1491 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1492 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1493 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1495 // Match all load 64 bits width whose type is compatible with FPR64
1496 let Predicates = [IsLE] in {
1497 // We must use LD1 to perform vector loads in big-endian.
1498 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1499 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1500 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1501 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1502 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1503 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1504 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1505 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1506 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1507 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1509 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1510 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1511 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1512 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1514 // Match all load 128 bits width whose type is compatible with FPR128
1515 let Predicates = [IsLE] in {
1516 // We must use LD1 to perform vector loads in big-endian.
1517 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1518 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1519 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1520 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1521 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1522 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1523 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1524 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1525 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1526 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1527 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1528 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1529 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1530 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1532 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1533 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1535 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1537 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1538 uimm12s2:$offset)))]>;
1539 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1541 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1542 uimm12s1:$offset)))]>;
1544 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1545 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1546 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1547 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1549 // zextloadi1 -> zextloadi8
1550 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1551 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1552 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1553 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1555 // extload -> zextload
1556 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1557 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1558 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1559 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1560 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1561 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1562 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1563 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1564 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1565 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1566 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1567 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1568 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1569 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1571 // load sign-extended half-word
1572 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1574 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1575 uimm12s2:$offset)))]>;
1576 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1578 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1579 uimm12s2:$offset)))]>;
1581 // load sign-extended byte
1582 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1584 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1585 uimm12s1:$offset)))]>;
1586 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1588 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1589 uimm12s1:$offset)))]>;
1591 // load sign-extended word
1592 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1594 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1595 uimm12s4:$offset)))]>;
1597 // load zero-extended word
1598 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1599 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1602 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1603 [(AArch64Prefetch imm:$Rt,
1604 (am_indexed64 GPR64sp:$Rn,
1605 uimm12s8:$offset))]>;
1607 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1611 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1612 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1613 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1614 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1615 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1617 // load sign-extended word
1618 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1621 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1622 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1625 // (unscaled immediate)
1626 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1628 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1629 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1631 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1632 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1634 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1635 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1637 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1638 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1639 [(set (f32 FPR32:$Rt),
1640 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1641 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1642 [(set (f64 FPR64:$Rt),
1643 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1644 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1645 [(set (f128 FPR128:$Rt),
1646 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1649 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1651 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1653 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1655 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1657 // Match all load 64 bits width whose type is compatible with FPR64
1658 let Predicates = [IsLE] in {
1659 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1660 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1661 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1662 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1663 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1664 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1665 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1666 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1667 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1668 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1670 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1671 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1672 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1673 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1675 // Match all load 128 bits width whose type is compatible with FPR128
1676 let Predicates = [IsLE] in {
1677 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1678 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1679 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1680 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1681 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1682 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1683 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1684 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1685 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1686 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1687 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1688 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1689 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1690 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1694 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1695 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1696 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1697 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1698 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1699 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1700 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1701 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1702 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1703 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1704 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1705 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1706 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1707 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1709 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1710 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1711 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1712 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1713 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1714 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1715 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1716 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1717 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1718 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1719 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1720 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1721 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1722 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1726 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1728 // Define new assembler match classes as we want to only match these when
1729 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1730 // associate a DiagnosticType either, as we want the diagnostic for the
1731 // canonical form (the scaled operand) to take precedence.
1732 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1733 let Name = "SImm9OffsetFB" # Width;
1734 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1735 let RenderMethod = "addImmOperands";
1738 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1739 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1740 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1741 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1742 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1744 def simm9_offset_fb8 : Operand<i64> {
1745 let ParserMatchClass = SImm9OffsetFB8Operand;
1747 def simm9_offset_fb16 : Operand<i64> {
1748 let ParserMatchClass = SImm9OffsetFB16Operand;
1750 def simm9_offset_fb32 : Operand<i64> {
1751 let ParserMatchClass = SImm9OffsetFB32Operand;
1753 def simm9_offset_fb64 : Operand<i64> {
1754 let ParserMatchClass = SImm9OffsetFB64Operand;
1756 def simm9_offset_fb128 : Operand<i64> {
1757 let ParserMatchClass = SImm9OffsetFB128Operand;
1760 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1761 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1762 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1763 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1764 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1765 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1766 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1767 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1768 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1769 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1770 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1771 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1772 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1773 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1776 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1777 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1778 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1779 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1781 // load sign-extended half-word
1783 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1785 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1787 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1789 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1791 // load sign-extended byte
1793 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1795 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1797 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1799 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1801 // load sign-extended word
1803 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1805 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1807 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1808 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1809 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1810 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1811 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1812 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1813 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1814 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1815 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1816 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1817 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1818 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1819 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1820 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1821 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1824 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1825 [(AArch64Prefetch imm:$Rt,
1826 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1829 // (unscaled immediate, unprivileged)
1830 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1831 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1833 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1834 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1836 // load sign-extended half-word
1837 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1838 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1840 // load sign-extended byte
1841 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1842 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1844 // load sign-extended word
1845 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1848 // (immediate pre-indexed)
1849 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1850 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1851 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1852 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1853 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1854 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1855 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1857 // load sign-extended half-word
1858 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1859 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1861 // load sign-extended byte
1862 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1863 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1865 // load zero-extended byte
1866 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1867 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1869 // load sign-extended word
1870 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1873 // (immediate post-indexed)
1874 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1875 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1876 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1877 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1878 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1879 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1880 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1882 // load sign-extended half-word
1883 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1884 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1886 // load sign-extended byte
1887 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1888 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1890 // load zero-extended byte
1891 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1892 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1894 // load sign-extended word
1895 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1897 //===----------------------------------------------------------------------===//
1898 // Store instructions.
1899 //===----------------------------------------------------------------------===//
1901 // Pair (indexed, offset)
1902 // FIXME: Use dedicated range-checked addressing mode operand here.
1903 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1904 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1905 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1906 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1907 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1909 // Pair (pre-indexed)
1910 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1911 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1912 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1913 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1914 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1916 // Pair (pre-indexed)
1917 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1918 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1919 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1920 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1921 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1923 // Pair (no allocate)
1924 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1925 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1926 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1927 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1928 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1931 // (Register offset)
1934 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1935 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1936 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1937 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1941 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1942 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1943 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1944 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1945 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1947 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1948 Instruction STRW, Instruction STRX> {
1950 def : Pat<(storeop GPR64:$Rt,
1951 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1952 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1953 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1955 def : Pat<(storeop GPR64:$Rt,
1956 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1957 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1958 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1961 let AddedComplexity = 10 in {
1963 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1964 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1965 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1968 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1969 Instruction STRW, Instruction STRX> {
1970 def : Pat<(store (VecTy FPR:$Rt),
1971 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1972 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1974 def : Pat<(store (VecTy FPR:$Rt),
1975 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1976 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1979 let AddedComplexity = 10 in {
1980 // Match all store 64 bits width whose type is compatible with FPR64
1981 let Predicates = [IsLE] in {
1982 // We must use ST1 to store vectors in big-endian.
1983 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1984 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1985 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1986 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1987 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1990 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1991 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1993 // Match all store 128 bits width whose type is compatible with FPR128
1994 let Predicates = [IsLE] in {
1995 // We must use ST1 to store vectors in big-endian.
1996 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1997 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1998 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1999 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
2000 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
2001 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
2002 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
2004 } // AddedComplexity = 10
2006 // Match stores from lane 0 to the appropriate subreg's store.
2007 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
2008 ValueType VecTy, ValueType STy,
2009 SubRegIndex SubRegIdx,
2010 Instruction STRW, Instruction STRX> {
2012 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2013 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
2014 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2015 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
2017 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2018 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
2019 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2020 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2023 let AddedComplexity = 19 in {
2024 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2025 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
2026 defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
2027 defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
2028 defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
2029 defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
2030 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
2034 // (unsigned immediate)
2035 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
2037 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2038 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
2040 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2041 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
2043 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
2044 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
2045 [(store (f16 FPR16:$Rt),
2046 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
2047 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
2048 [(store (f32 FPR32:$Rt),
2049 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2050 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
2051 [(store (f64 FPR64:$Rt),
2052 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2053 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
2055 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
2056 [(truncstorei16 GPR32:$Rt,
2057 (am_indexed16 GPR64sp:$Rn,
2058 uimm12s2:$offset))]>;
2059 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
2060 [(truncstorei8 GPR32:$Rt,
2061 (am_indexed8 GPR64sp:$Rn,
2062 uimm12s1:$offset))]>;
2064 // Match all store 64 bits width whose type is compatible with FPR64
2065 let AddedComplexity = 10 in {
2066 let Predicates = [IsLE] in {
2067 // We must use ST1 to store vectors in big-endian.
2068 def : Pat<(store (v2f32 FPR64:$Rt),
2069 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2070 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2071 def : Pat<(store (v8i8 FPR64:$Rt),
2072 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2073 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2074 def : Pat<(store (v4i16 FPR64:$Rt),
2075 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2076 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2077 def : Pat<(store (v2i32 FPR64:$Rt),
2078 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2079 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2080 def : Pat<(store (v4f16 FPR64:$Rt),
2081 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2082 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2084 def : Pat<(store (v1f64 FPR64:$Rt),
2085 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2086 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2087 def : Pat<(store (v1i64 FPR64:$Rt),
2088 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2089 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2091 // Match all store 128 bits width whose type is compatible with FPR128
2092 let Predicates = [IsLE] in {
2093 // We must use ST1 to store vectors in big-endian.
2094 def : Pat<(store (v4f32 FPR128:$Rt),
2095 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2096 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2097 def : Pat<(store (v2f64 FPR128:$Rt),
2098 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2099 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2100 def : Pat<(store (v16i8 FPR128:$Rt),
2101 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2102 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2103 def : Pat<(store (v8i16 FPR128:$Rt),
2104 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2105 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2106 def : Pat<(store (v4i32 FPR128:$Rt),
2107 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2108 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2109 def : Pat<(store (v2i64 FPR128:$Rt),
2110 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2111 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2112 def : Pat<(store (v8f16 FPR128:$Rt),
2113 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2114 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2116 def : Pat<(store (f128 FPR128:$Rt),
2117 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2118 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2121 def : Pat<(truncstorei32 GPR64:$Rt,
2122 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
2123 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2124 def : Pat<(truncstorei16 GPR64:$Rt,
2125 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2126 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
2127 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
2128 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
2130 } // AddedComplexity = 10
2133 // (unscaled immediate)
2134 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2136 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2137 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2139 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2140 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2142 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2143 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2144 [(store (f16 FPR16:$Rt),
2145 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2146 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2147 [(store (f32 FPR32:$Rt),
2148 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2149 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2150 [(store (f64 FPR64:$Rt),
2151 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2152 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2153 [(store (f128 FPR128:$Rt),
2154 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2155 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2156 [(truncstorei16 GPR32:$Rt,
2157 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2158 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2159 [(truncstorei8 GPR32:$Rt,
2160 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2162 // Match all store 64 bits width whose type is compatible with FPR64
2163 let Predicates = [IsLE] in {
2164 // We must use ST1 to store vectors in big-endian.
2165 def : Pat<(store (v2f32 FPR64:$Rt),
2166 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2167 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2168 def : Pat<(store (v8i8 FPR64:$Rt),
2169 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2170 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2171 def : Pat<(store (v4i16 FPR64:$Rt),
2172 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2173 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2174 def : Pat<(store (v2i32 FPR64:$Rt),
2175 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2176 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2177 def : Pat<(store (v4f16 FPR64:$Rt),
2178 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2179 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2181 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2182 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2183 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2184 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2186 // Match all store 128 bits width whose type is compatible with FPR128
2187 let Predicates = [IsLE] in {
2188 // We must use ST1 to store vectors in big-endian.
2189 def : Pat<(store (v4f32 FPR128:$Rt),
2190 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2191 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2192 def : Pat<(store (v2f64 FPR128:$Rt),
2193 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2194 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2195 def : Pat<(store (v16i8 FPR128:$Rt),
2196 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2197 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2198 def : Pat<(store (v8i16 FPR128:$Rt),
2199 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2200 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2201 def : Pat<(store (v4i32 FPR128:$Rt),
2202 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2203 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2204 def : Pat<(store (v2i64 FPR128:$Rt),
2205 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2206 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2207 def : Pat<(store (v2f64 FPR128:$Rt),
2208 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2209 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2210 def : Pat<(store (v8f16 FPR128:$Rt),
2211 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2212 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2215 // unscaled i64 truncating stores
2216 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2217 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2218 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2219 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2220 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2221 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2224 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2225 def : InstAlias<"str $Rt, [$Rn, $offset]",
2226 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2227 def : InstAlias<"str $Rt, [$Rn, $offset]",
2228 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2229 def : InstAlias<"str $Rt, [$Rn, $offset]",
2230 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2231 def : InstAlias<"str $Rt, [$Rn, $offset]",
2232 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2233 def : InstAlias<"str $Rt, [$Rn, $offset]",
2234 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2235 def : InstAlias<"str $Rt, [$Rn, $offset]",
2236 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2237 def : InstAlias<"str $Rt, [$Rn, $offset]",
2238 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2240 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2241 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2242 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2243 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2246 // (unscaled immediate, unprivileged)
2247 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2248 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2250 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2251 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2254 // (immediate pre-indexed)
2255 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2256 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2257 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2258 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2259 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2260 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2261 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2263 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2264 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2267 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2268 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2270 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2271 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2273 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2274 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2277 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2278 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2279 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2280 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2281 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2282 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2283 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2284 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2285 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2286 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2287 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2288 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2289 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2290 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2292 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2293 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2294 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2295 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2296 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2297 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2298 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2299 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2300 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2301 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2302 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2303 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2304 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2305 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2308 // (immediate post-indexed)
2309 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2310 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2311 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2312 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2313 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2314 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2315 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2317 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2318 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2321 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2322 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2324 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2325 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2327 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2328 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2331 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2332 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2333 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2334 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2335 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2336 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2337 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2338 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2339 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2340 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2341 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2342 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2343 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2344 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2346 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2347 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2348 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2349 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2350 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2351 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2352 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2353 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2354 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2355 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2356 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2357 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2358 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2359 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2361 //===----------------------------------------------------------------------===//
2362 // Load/store exclusive instructions.
2363 //===----------------------------------------------------------------------===//
2365 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2366 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2367 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2368 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2370 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2371 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2372 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2373 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2375 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2376 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2377 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2378 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2380 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2381 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2382 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2383 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2385 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2386 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2387 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2388 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2390 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2391 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2392 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2393 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2395 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2396 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2398 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2399 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2401 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2402 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2404 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2405 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2407 let Predicates = [HasV8_1a] in {
2408 // v8.1a "Limited Order Region" extension load-acquire instructions
2409 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2410 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
2411 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2412 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
2414 // v8.1a "Limited Order Region" extension store-release instructions
2415 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
2416 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
2417 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2418 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
2421 //===----------------------------------------------------------------------===//
2422 // Scaled floating point to integer conversion instructions.
2423 //===----------------------------------------------------------------------===//
2425 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2426 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2427 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2428 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2429 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2430 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2431 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2432 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2433 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2434 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2435 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2436 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2437 let isCodeGenOnly = 1 in {
2438 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2439 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2440 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2441 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2444 multiclass FPToIntegerPats<SDNode to_int, SDNode round, string INST> {
2445 def : Pat<(i32 (to_int (round f32:$Rn))),
2446 (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
2447 def : Pat<(i64 (to_int (round f32:$Rn))),
2448 (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
2449 def : Pat<(i32 (to_int (round f64:$Rn))),
2450 (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
2451 def : Pat<(i64 (to_int (round f64:$Rn))),
2452 (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
2455 defm : FPToIntegerPats<fp_to_sint, fceil, "FCVTPS">;
2456 defm : FPToIntegerPats<fp_to_uint, fceil, "FCVTPU">;
2457 defm : FPToIntegerPats<fp_to_sint, ffloor, "FCVTMS">;
2458 defm : FPToIntegerPats<fp_to_uint, ffloor, "FCVTMU">;
2459 defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">;
2460 defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
2461 defm : FPToIntegerPats<fp_to_sint, frnd, "FCVTAS">;
2462 defm : FPToIntegerPats<fp_to_uint, frnd, "FCVTAU">;
2464 //===----------------------------------------------------------------------===//
2465 // Scaled integer to floating point conversion instructions.
2466 //===----------------------------------------------------------------------===//
2468 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2469 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2471 //===----------------------------------------------------------------------===//
2472 // Unscaled integer to floating point conversion instruction.
2473 //===----------------------------------------------------------------------===//
2475 defm FMOV : UnscaledConversion<"fmov">;
2477 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
2478 let isReMaterializable = 1, isCodeGenOnly = 1 in {
2479 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
2480 PseudoInstExpansion<(FMOVWSr FPR32:$Rd, WZR)>,
2482 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
2483 PseudoInstExpansion<(FMOVXDr FPR64:$Rd, XZR)>,
2487 //===----------------------------------------------------------------------===//
2488 // Floating point conversion instruction.
2489 //===----------------------------------------------------------------------===//
2491 defm FCVT : FPConversion<"fcvt">;
2493 //===----------------------------------------------------------------------===//
2494 // Floating point single operand instructions.
2495 //===----------------------------------------------------------------------===//
2497 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2498 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2499 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2500 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2501 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2502 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2503 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2504 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2506 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2507 (FRINTNDr FPR64:$Rn)>;
2509 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2510 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2512 let SchedRW = [WriteFDiv] in {
2513 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2516 //===----------------------------------------------------------------------===//
2517 // Floating point two operand instructions.
2518 //===----------------------------------------------------------------------===//
2520 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2521 let SchedRW = [WriteFDiv] in {
2522 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2524 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>;
2525 defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>;
2526 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>;
2527 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;
2528 let SchedRW = [WriteFMul] in {
2529 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2530 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2532 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2534 def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2535 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2536 def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2537 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2538 def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2539 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2540 def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2541 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2543 //===----------------------------------------------------------------------===//
2544 // Floating point three operand instructions.
2545 //===----------------------------------------------------------------------===//
2547 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2548 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2549 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2550 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2551 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2552 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2553 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2555 // The following def pats catch the case where the LHS of an FMA is negated.
2556 // The TriOpFrag above catches the case where the middle operand is negated.
2558 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2559 // the NEON variant.
2560 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2561 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2563 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2564 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2566 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2568 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2569 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2571 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2572 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2574 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2575 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2577 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2578 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2580 //===----------------------------------------------------------------------===//
2581 // Floating point comparison instructions.
2582 //===----------------------------------------------------------------------===//
2584 defm FCMPE : FPComparison<1, "fcmpe">;
2585 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2587 //===----------------------------------------------------------------------===//
2588 // Floating point conditional comparison instructions.
2589 //===----------------------------------------------------------------------===//
2591 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2592 defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>;
2594 //===----------------------------------------------------------------------===//
2595 // Floating point conditional select instruction.
2596 //===----------------------------------------------------------------------===//
2598 defm FCSEL : FPCondSelect<"fcsel">;
2600 // CSEL instructions providing f128 types need to be handled by a
2601 // pseudo-instruction since the eventual code will need to introduce basic
2602 // blocks and control flow.
2603 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2604 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2605 [(set (f128 FPR128:$Rd),
2606 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2607 (i32 imm:$cond), NZCV))]> {
2609 let usesCustomInserter = 1;
2613 //===----------------------------------------------------------------------===//
2614 // Floating point immediate move.
2615 //===----------------------------------------------------------------------===//
2617 let isReMaterializable = 1 in {
2618 defm FMOV : FPMoveImmediate<"fmov">;
2621 //===----------------------------------------------------------------------===//
2622 // Advanced SIMD two vector instructions.
2623 //===----------------------------------------------------------------------===//
2625 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
2627 // Match UABDL in log2-shuffle patterns.
2628 def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))),
2629 (v8i16 (add (sub (zext (v8i8 V64:$opA)),
2630 (zext (v8i8 V64:$opB))),
2631 (AArch64vashr v8i16:$src, (i32 15))))),
2632 (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>;
2633 def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))),
2634 (v8i16 (add (sub (zext (extract_high_v16i8 V128:$opA)),
2635 (zext (extract_high_v16i8 V128:$opB))),
2636 (AArch64vashr v8i16:$src, (i32 15))))),
2637 (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>;
2638 def : Pat<(xor (v4i32 (AArch64vashr v4i32:$src, (i32 31))),
2639 (v4i32 (add (sub (zext (v4i16 V64:$opA)),
2640 (zext (v4i16 V64:$opB))),
2641 (AArch64vashr v4i32:$src, (i32 31))))),
2642 (UABDLv4i16_v4i32 V64:$opA, V64:$opB)>;
2643 def : Pat<(xor (v4i32 (AArch64vashr v4i32:$src, (i32 31))),
2644 (v4i32 (add (sub (zext (extract_high_v8i16 V128:$opA)),
2645 (zext (extract_high_v8i16 V128:$opB))),
2646 (AArch64vashr v4i32:$src, (i32 31))))),
2647 (UABDLv8i16_v4i32 V128:$opA, V128:$opB)>;
2648 def : Pat<(xor (v2i64 (AArch64vashr v2i64:$src, (i32 63))),
2649 (v2i64 (add (sub (zext (v2i32 V64:$opA)),
2650 (zext (v2i32 V64:$opB))),
2651 (AArch64vashr v2i64:$src, (i32 63))))),
2652 (UABDLv2i32_v2i64 V64:$opA, V64:$opB)>;
2653 def : Pat<(xor (v2i64 (AArch64vashr v2i64:$src, (i32 63))),
2654 (v2i64 (add (sub (zext (extract_high_v4i32 V128:$opA)),
2655 (zext (extract_high_v4i32 V128:$opB))),
2656 (AArch64vashr v2i64:$src, (i32 63))))),
2657 (UABDLv4i32_v2i64 V128:$opA, V128:$opB)>;
2659 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2660 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2661 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2662 (ABSv8i8 V64:$src)>;
2663 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2664 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2665 (ABSv4i16 V64:$src)>;
2666 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2667 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2668 (ABSv2i32 V64:$src)>;
2669 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2670 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2671 (ABSv16i8 V128:$src)>;
2672 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2673 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2674 (ABSv8i16 V128:$src)>;
2675 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2676 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2677 (ABSv4i32 V128:$src)>;
2678 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2679 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2680 (ABSv2i64 V128:$src)>;
2682 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2683 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2684 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2685 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2686 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2687 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2688 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2689 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2690 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2692 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2693 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2694 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2695 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2696 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2697 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2698 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2699 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2700 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2701 (FCVTLv4i16 V64:$Rn)>;
2702 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2704 (FCVTLv8i16 V128:$Rn)>;
2705 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2706 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2708 (FCVTLv4i32 V128:$Rn)>;
2710 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2711 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2713 (FCVTLv8i16 V128:$Rn)>;
2715 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2716 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2717 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2718 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2719 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2720 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2721 (FCVTNv4i16 V128:$Rn)>;
2722 def : Pat<(concat_vectors V64:$Rd,
2723 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2724 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2725 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2726 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2727 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2728 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2729 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2730 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2731 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2732 int_aarch64_neon_fcvtxn>;
2733 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2734 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2735 let isCodeGenOnly = 1 in {
2736 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2737 int_aarch64_neon_fcvtzs>;
2738 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2739 int_aarch64_neon_fcvtzu>;
2741 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2742 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2743 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2744 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2745 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2746 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2747 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2748 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2749 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2750 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2751 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2752 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2753 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2754 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2755 // Aliases for MVN -> NOT.
2756 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2757 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2758 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2759 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2761 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2762 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2763 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2764 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2765 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2766 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2767 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2769 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2770 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2771 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2772 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2773 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2774 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2775 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2776 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2778 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2779 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2780 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2781 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2782 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2784 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2785 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2786 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2787 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2788 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2789 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2790 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2791 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2792 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2793 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2794 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2795 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2796 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2797 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2798 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2799 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2800 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2801 int_aarch64_neon_uaddlp>;
2802 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2803 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2804 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2805 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2806 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2807 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2809 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2810 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2811 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2812 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2813 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2814 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2816 // Patterns for vector long shift (by element width). These need to match all
2817 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2819 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2820 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2821 (SHLLv8i8 V64:$Rn)>;
2822 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2823 (SHLLv16i8 V128:$Rn)>;
2824 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2825 (SHLLv4i16 V64:$Rn)>;
2826 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2827 (SHLLv8i16 V128:$Rn)>;
2828 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2829 (SHLLv2i32 V64:$Rn)>;
2830 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2831 (SHLLv4i32 V128:$Rn)>;
2834 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2835 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2836 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2838 //===----------------------------------------------------------------------===//
2839 // Advanced SIMD three vector instructions.
2840 //===----------------------------------------------------------------------===//
2842 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2843 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2844 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2845 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2846 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2847 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2848 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2849 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2850 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2851 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2852 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2853 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2854 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2855 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2856 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2857 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2858 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2859 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2860 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", fmaxnum>;
2861 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2862 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", fmaxnan>;
2863 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2864 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", fminnum>;
2865 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2866 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", fminnan>;
2868 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2869 // instruction expects the addend first, while the fma intrinsic puts it last.
2870 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2871 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2872 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2873 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2875 // The following def pats catch the case where the LHS of an FMA is negated.
2876 // The TriOpFrag above catches the case where the middle operand is negated.
2877 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2878 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2880 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2881 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2883 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2884 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2886 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2887 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2888 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2889 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2890 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2891 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2892 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2893 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2894 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2895 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2896 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2897 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2898 TriOpFrag<(add node:$LHS, (sabsdiff node:$MHS, node:$RHS))> >;
2899 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", sabsdiff>;
2900 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2901 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2902 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2903 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", smax>;
2904 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2905 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>;
2906 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2907 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2908 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2909 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2910 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2911 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2912 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2913 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2914 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2915 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2916 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2917 TriOpFrag<(add node:$LHS, (uabsdiff node:$MHS, node:$RHS))> >;
2918 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", uabsdiff>;
2919 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2920 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2921 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2922 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", umax>;
2923 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2924 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", umin>;
2925 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2926 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2927 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2928 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2929 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2930 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2931 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2932 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
2933 int_aarch64_neon_sqadd>;
2934 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
2935 int_aarch64_neon_sqsub>;
2937 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2938 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2939 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2940 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2941 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2942 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2943 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2944 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2945 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2946 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2947 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2950 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2951 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2952 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2953 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2954 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2955 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2956 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2957 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2959 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2960 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2961 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2962 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2963 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2964 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2965 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2966 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2968 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2969 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2970 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2971 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2972 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2973 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2974 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2975 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2977 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2978 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2979 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2980 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2981 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2982 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2983 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2984 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2986 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2987 "|cmls.8b\t$dst, $src1, $src2}",
2988 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2989 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2990 "|cmls.16b\t$dst, $src1, $src2}",
2991 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2992 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2993 "|cmls.4h\t$dst, $src1, $src2}",
2994 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2995 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2996 "|cmls.8h\t$dst, $src1, $src2}",
2997 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2998 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2999 "|cmls.2s\t$dst, $src1, $src2}",
3000 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3001 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
3002 "|cmls.4s\t$dst, $src1, $src2}",
3003 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3004 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
3005 "|cmls.2d\t$dst, $src1, $src2}",
3006 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3008 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
3009 "|cmlo.8b\t$dst, $src1, $src2}",
3010 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3011 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
3012 "|cmlo.16b\t$dst, $src1, $src2}",
3013 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3014 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
3015 "|cmlo.4h\t$dst, $src1, $src2}",
3016 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3017 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
3018 "|cmlo.8h\t$dst, $src1, $src2}",
3019 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3020 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
3021 "|cmlo.2s\t$dst, $src1, $src2}",
3022 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3023 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
3024 "|cmlo.4s\t$dst, $src1, $src2}",
3025 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3026 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
3027 "|cmlo.2d\t$dst, $src1, $src2}",
3028 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3030 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
3031 "|cmle.8b\t$dst, $src1, $src2}",
3032 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3033 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
3034 "|cmle.16b\t$dst, $src1, $src2}",
3035 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3036 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
3037 "|cmle.4h\t$dst, $src1, $src2}",
3038 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3039 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
3040 "|cmle.8h\t$dst, $src1, $src2}",
3041 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3042 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
3043 "|cmle.2s\t$dst, $src1, $src2}",
3044 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3045 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
3046 "|cmle.4s\t$dst, $src1, $src2}",
3047 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3048 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
3049 "|cmle.2d\t$dst, $src1, $src2}",
3050 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3052 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
3053 "|cmlt.8b\t$dst, $src1, $src2}",
3054 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3055 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
3056 "|cmlt.16b\t$dst, $src1, $src2}",
3057 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3058 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
3059 "|cmlt.4h\t$dst, $src1, $src2}",
3060 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3061 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
3062 "|cmlt.8h\t$dst, $src1, $src2}",
3063 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3064 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
3065 "|cmlt.2s\t$dst, $src1, $src2}",
3066 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3067 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
3068 "|cmlt.4s\t$dst, $src1, $src2}",
3069 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3070 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
3071 "|cmlt.2d\t$dst, $src1, $src2}",
3072 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3074 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
3075 "|fcmle.2s\t$dst, $src1, $src2}",
3076 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3077 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
3078 "|fcmle.4s\t$dst, $src1, $src2}",
3079 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3080 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
3081 "|fcmle.2d\t$dst, $src1, $src2}",
3082 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3084 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
3085 "|fcmlt.2s\t$dst, $src1, $src2}",
3086 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3087 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
3088 "|fcmlt.4s\t$dst, $src1, $src2}",
3089 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3090 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
3091 "|fcmlt.2d\t$dst, $src1, $src2}",
3092 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3094 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
3095 "|facle.2s\t$dst, $src1, $src2}",
3096 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3097 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
3098 "|facle.4s\t$dst, $src1, $src2}",
3099 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3100 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
3101 "|facle.2d\t$dst, $src1, $src2}",
3102 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3104 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
3105 "|faclt.2s\t$dst, $src1, $src2}",
3106 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3107 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
3108 "|faclt.4s\t$dst, $src1, $src2}",
3109 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3110 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
3111 "|faclt.2d\t$dst, $src1, $src2}",
3112 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3114 //===----------------------------------------------------------------------===//
3115 // Advanced SIMD three scalar instructions.
3116 //===----------------------------------------------------------------------===//
3118 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
3119 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
3120 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
3121 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
3122 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
3123 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
3124 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
3125 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
3126 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3127 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
3128 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
3129 int_aarch64_neon_facge>;
3130 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
3131 int_aarch64_neon_facgt>;
3132 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
3133 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
3134 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
3135 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
3136 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
3137 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
3138 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
3139 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
3140 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
3141 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
3142 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
3143 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
3144 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
3145 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
3146 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
3147 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
3148 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
3149 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
3150 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
3151 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
3152 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
3153 let Predicates = [HasV8_1a] in {
3154 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
3155 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
3156 def : Pat<(i32 (int_aarch64_neon_sqadd
3158 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3159 (i32 FPR32:$Rm))))),
3160 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3161 def : Pat<(i32 (int_aarch64_neon_sqsub
3163 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3164 (i32 FPR32:$Rm))))),
3165 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3168 def : InstAlias<"cmls $dst, $src1, $src2",
3169 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3170 def : InstAlias<"cmle $dst, $src1, $src2",
3171 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3172 def : InstAlias<"cmlo $dst, $src1, $src2",
3173 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3174 def : InstAlias<"cmlt $dst, $src1, $src2",
3175 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3176 def : InstAlias<"fcmle $dst, $src1, $src2",
3177 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3178 def : InstAlias<"fcmle $dst, $src1, $src2",
3179 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3180 def : InstAlias<"fcmlt $dst, $src1, $src2",
3181 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3182 def : InstAlias<"fcmlt $dst, $src1, $src2",
3183 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3184 def : InstAlias<"facle $dst, $src1, $src2",
3185 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3186 def : InstAlias<"facle $dst, $src1, $src2",
3187 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3188 def : InstAlias<"faclt $dst, $src1, $src2",
3189 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3190 def : InstAlias<"faclt $dst, $src1, $src2",
3191 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3193 //===----------------------------------------------------------------------===//
3194 // Advanced SIMD three scalar instructions (mixed operands).
3195 //===----------------------------------------------------------------------===//
3196 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3197 int_aarch64_neon_sqdmulls_scalar>;
3198 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
3199 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3201 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3202 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3203 (i32 FPR32:$Rm))))),
3204 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3205 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3206 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3207 (i32 FPR32:$Rm))))),
3208 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3210 //===----------------------------------------------------------------------===//
3211 // Advanced SIMD two scalar instructions.
3212 //===----------------------------------------------------------------------===//
3214 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
3215 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3216 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3217 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3218 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3219 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3220 defm FCMEQ : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3221 defm FCMGE : SIMDFPCmpTwoScalar<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3222 defm FCMGT : SIMDFPCmpTwoScalar<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3223 defm FCMLE : SIMDFPCmpTwoScalar<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3224 defm FCMLT : SIMDFPCmpTwoScalar<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3225 defm FCVTAS : SIMDFPTwoScalar< 0, 0, 0b11100, "fcvtas">;
3226 defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau">;
3227 defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms">;
3228 defm FCVTMU : SIMDFPTwoScalar< 1, 0, 0b11011, "fcvtmu">;
3229 defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns">;
3230 defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu">;
3231 defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps">;
3232 defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu">;
3233 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3234 defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">;
3235 defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">;
3236 defm FRECPE : SIMDFPTwoScalar< 0, 1, 0b11101, "frecpe">;
3237 defm FRECPX : SIMDFPTwoScalar< 0, 1, 0b11111, "frecpx">;
3238 defm FRSQRTE : SIMDFPTwoScalar< 1, 1, 0b11101, "frsqrte">;
3239 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3240 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3241 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3242 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3243 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3244 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3245 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3246 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3247 int_aarch64_neon_suqadd>;
3248 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3249 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3250 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3251 int_aarch64_neon_usqadd>;
3253 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3255 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3256 (FCVTASv1i64 FPR64:$Rn)>;
3257 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3258 (FCVTAUv1i64 FPR64:$Rn)>;
3259 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3260 (FCVTMSv1i64 FPR64:$Rn)>;
3261 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3262 (FCVTMUv1i64 FPR64:$Rn)>;
3263 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3264 (FCVTNSv1i64 FPR64:$Rn)>;
3265 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3266 (FCVTNUv1i64 FPR64:$Rn)>;
3267 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3268 (FCVTPSv1i64 FPR64:$Rn)>;
3269 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3270 (FCVTPUv1i64 FPR64:$Rn)>;
3272 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3273 (FRECPEv1i32 FPR32:$Rn)>;
3274 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3275 (FRECPEv1i64 FPR64:$Rn)>;
3276 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3277 (FRECPEv1i64 FPR64:$Rn)>;
3279 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3280 (FRECPXv1i32 FPR32:$Rn)>;
3281 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3282 (FRECPXv1i64 FPR64:$Rn)>;
3284 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3285 (FRSQRTEv1i32 FPR32:$Rn)>;
3286 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3287 (FRSQRTEv1i64 FPR64:$Rn)>;
3288 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3289 (FRSQRTEv1i64 FPR64:$Rn)>;
3291 // If an integer is about to be converted to a floating point value,
3292 // just load it on the floating point unit.
3293 // Here are the patterns for 8 and 16-bits to float.
3295 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3296 SDPatternOperator loadop, Instruction UCVTF,
3297 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3299 def : Pat<(DstTy (uint_to_fp (SrcTy
3300 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3301 ro.Wext:$extend))))),
3302 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3303 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3306 def : Pat<(DstTy (uint_to_fp (SrcTy
3307 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3308 ro.Wext:$extend))))),
3309 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3310 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3314 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3315 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3316 def : Pat <(f32 (uint_to_fp (i32
3317 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3318 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3319 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3320 def : Pat <(f32 (uint_to_fp (i32
3321 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3322 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3323 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3324 // 16-bits -> float.
3325 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3326 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3327 def : Pat <(f32 (uint_to_fp (i32
3328 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3329 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3330 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3331 def : Pat <(f32 (uint_to_fp (i32
3332 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3333 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3334 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3335 // 32-bits are handled in target specific dag combine:
3336 // performIntToFpCombine.
3337 // 64-bits integer to 32-bits floating point, not possible with
3338 // UCVTF on floating point registers (both source and destination
3339 // must have the same size).
3341 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3342 // 8-bits -> double.
3343 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3344 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3345 def : Pat <(f64 (uint_to_fp (i32
3346 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3347 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3348 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3349 def : Pat <(f64 (uint_to_fp (i32
3350 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3351 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3352 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3353 // 16-bits -> double.
3354 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3355 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3356 def : Pat <(f64 (uint_to_fp (i32
3357 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3358 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3359 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3360 def : Pat <(f64 (uint_to_fp (i32
3361 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3362 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3363 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3364 // 32-bits -> double.
3365 defm : UIntToFPROLoadPat<f64, i32, load,
3366 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3367 def : Pat <(f64 (uint_to_fp (i32
3368 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3369 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3370 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3371 def : Pat <(f64 (uint_to_fp (i32
3372 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3373 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3374 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3375 // 64-bits -> double are handled in target specific dag combine:
3376 // performIntToFpCombine.
3378 //===----------------------------------------------------------------------===//
3379 // Advanced SIMD three different-sized vector instructions.
3380 //===----------------------------------------------------------------------===//
3382 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3383 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3384 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3385 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3386 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3387 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3389 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3391 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3392 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3393 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3394 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3395 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3396 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3397 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3398 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3399 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3400 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3401 int_aarch64_neon_sqadd>;
3402 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3403 int_aarch64_neon_sqsub>;
3404 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3405 int_aarch64_neon_sqdmull>;
3406 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3407 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3408 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3409 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3410 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3412 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3413 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3414 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3415 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3416 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3417 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3418 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3419 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3420 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3421 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3422 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3423 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3424 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3426 // Additional patterns for SMULL and UMULL
3427 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3428 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3429 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3430 (INST8B V64:$Rn, V64:$Rm)>;
3431 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3432 (INST4H V64:$Rn, V64:$Rm)>;
3433 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3434 (INST2S V64:$Rn, V64:$Rm)>;
3437 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3438 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3439 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3440 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3442 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3443 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3444 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3445 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3446 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3447 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3448 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3449 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3450 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3453 defm : Neon_mulacc_widen_patterns<
3454 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3455 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3456 defm : Neon_mulacc_widen_patterns<
3457 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3458 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3459 defm : Neon_mulacc_widen_patterns<
3460 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3461 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3462 defm : Neon_mulacc_widen_patterns<
3463 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3464 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3466 // Patterns for 64-bit pmull
3467 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3468 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3469 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3470 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3471 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3473 // CodeGen patterns for addhn and subhn instructions, which can actually be
3474 // written in LLVM IR without too much difficulty.
3477 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3478 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3479 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3481 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3482 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3484 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3485 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3486 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3488 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3489 V128:$Rn, V128:$Rm)>;
3490 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3491 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3493 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3494 V128:$Rn, V128:$Rm)>;
3495 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3496 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3498 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3499 V128:$Rn, V128:$Rm)>;
3502 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3503 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3504 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3506 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3507 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3509 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3510 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3511 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3513 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3514 V128:$Rn, V128:$Rm)>;
3515 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3516 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3518 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3519 V128:$Rn, V128:$Rm)>;
3520 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3521 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3523 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3524 V128:$Rn, V128:$Rm)>;
3526 //----------------------------------------------------------------------------
3527 // AdvSIMD bitwise extract from vector instruction.
3528 //----------------------------------------------------------------------------
3530 defm EXT : SIMDBitwiseExtract<"ext">;
3532 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3533 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3534 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3535 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3536 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3537 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3538 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3539 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3540 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3541 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3542 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3543 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3544 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3545 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3546 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3547 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3548 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3549 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3550 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3551 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3553 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3555 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3556 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3557 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3558 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3559 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3560 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3561 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3562 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3563 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3564 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3565 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3566 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3567 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3568 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3571 //----------------------------------------------------------------------------
3572 // AdvSIMD zip vector
3573 //----------------------------------------------------------------------------
3575 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3576 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3577 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3578 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3579 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3580 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3582 //----------------------------------------------------------------------------
3583 // AdvSIMD TBL/TBX instructions
3584 //----------------------------------------------------------------------------
3586 defm TBL : SIMDTableLookup< 0, "tbl">;
3587 defm TBX : SIMDTableLookupTied<1, "tbx">;
3589 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3590 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3591 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3592 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3594 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3595 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3596 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3597 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3598 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3599 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3602 //----------------------------------------------------------------------------
3603 // AdvSIMD scalar CPY instruction
3604 //----------------------------------------------------------------------------
3606 defm CPY : SIMDScalarCPY<"cpy">;
3608 //----------------------------------------------------------------------------
3609 // AdvSIMD scalar pairwise instructions
3610 //----------------------------------------------------------------------------
3612 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3613 defm FADDP : SIMDFPPairwiseScalar<1, 0, 0b01101, "faddp">;
3614 defm FMAXNMP : SIMDFPPairwiseScalar<1, 0, 0b01100, "fmaxnmp">;
3615 defm FMAXP : SIMDFPPairwiseScalar<1, 0, 0b01111, "fmaxp">;
3616 defm FMINNMP : SIMDFPPairwiseScalar<1, 1, 0b01100, "fminnmp">;
3617 defm FMINP : SIMDFPPairwiseScalar<1, 1, 0b01111, "fminp">;
3618 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
3619 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3620 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),
3621 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3622 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3623 (FADDPv2i32p V64:$Rn)>;
3624 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3625 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3626 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3627 (FADDPv2i64p V128:$Rn)>;
3628 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3629 (FMAXNMPv2i32p V64:$Rn)>;
3630 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3631 (FMAXNMPv2i64p V128:$Rn)>;
3632 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3633 (FMAXPv2i32p V64:$Rn)>;
3634 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3635 (FMAXPv2i64p V128:$Rn)>;
3636 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3637 (FMINNMPv2i32p V64:$Rn)>;
3638 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3639 (FMINNMPv2i64p V128:$Rn)>;
3640 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3641 (FMINPv2i32p V64:$Rn)>;
3642 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3643 (FMINPv2i64p V128:$Rn)>;
3645 //----------------------------------------------------------------------------
3646 // AdvSIMD INS/DUP instructions
3647 //----------------------------------------------------------------------------
3649 def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>;
3650 def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>;
3651 def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>;
3652 def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>;
3653 def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>;
3654 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;
3655 def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>;
3657 def DUPv2i64lane : SIMDDup64FromElement;
3658 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3659 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3660 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3661 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3662 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3663 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3665 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3666 (v2f32 (DUPv2i32lane
3667 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3669 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3670 (v4f32 (DUPv4i32lane
3671 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3673 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3674 (v2f64 (DUPv2i64lane
3675 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3677 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3678 (v4f16 (DUPv4i16lane
3679 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3681 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3682 (v8f16 (DUPv8i16lane
3683 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3686 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3687 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3688 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3689 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3691 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3692 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3693 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3694 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3695 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3696 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3698 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3699 // instruction even if the types don't match: we just have to remap the lane
3700 // carefully. N.b. this trick only applies to truncations.
3701 def VecIndex_x2 : SDNodeXForm<imm, [{
3702 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64);
3704 def VecIndex_x4 : SDNodeXForm<imm, [{
3705 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64);
3707 def VecIndex_x8 : SDNodeXForm<imm, [{
3708 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64);
3711 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3712 ValueType Src128VT, ValueType ScalVT,
3713 Instruction DUP, SDNodeXForm IdxXFORM> {
3714 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3716 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3718 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3720 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3723 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3724 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3725 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3727 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3728 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3729 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3731 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3732 SDNodeXForm IdxXFORM> {
3733 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3735 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3737 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3739 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3742 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3743 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3744 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3746 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3747 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3748 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3750 // SMOV and UMOV definitions, with some extra patterns for convenience
3754 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3755 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3756 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3757 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3758 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3759 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3760 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3761 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3762 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3763 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3764 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3765 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3767 // Extracting i8 or i16 elements will have the zero-extend transformed to
3768 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3769 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3770 // bits of the destination register.
3771 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3773 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3774 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3776 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3780 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3781 (SUBREG_TO_REG (i32 0),
3782 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3783 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3784 (SUBREG_TO_REG (i32 0),
3785 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3787 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3788 (SUBREG_TO_REG (i32 0),
3789 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3790 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3791 (SUBREG_TO_REG (i32 0),
3792 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3794 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3795 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3796 (i32 FPR32:$Rn), ssub))>;
3797 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3798 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3799 (i32 FPR32:$Rn), ssub))>;
3800 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3801 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3802 (i64 FPR64:$Rn), dsub))>;
3804 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3805 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3806 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3807 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3808 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3809 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3811 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3812 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3815 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3817 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3821 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3822 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3824 V128:$Rn, VectorIndexH:$imm,
3825 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3828 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3829 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3832 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3834 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3837 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3838 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3840 V128:$Rn, VectorIndexS:$imm,
3841 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3843 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3844 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3846 V128:$Rn, VectorIndexD:$imm,
3847 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3850 // Copy an element at a constant index in one vector into a constant indexed
3851 // element of another.
3852 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3853 // index type and INS extension
3854 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3855 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3856 VectorIndexB:$idx2)),
3858 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3860 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3861 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3862 VectorIndexH:$idx2)),
3864 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3866 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3867 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3868 VectorIndexS:$idx2)),
3870 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3872 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3873 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3874 VectorIndexD:$idx2)),
3876 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3879 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3880 ValueType VTScal, Instruction INS> {
3881 def : Pat<(VT128 (vector_insert V128:$src,
3882 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3884 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3886 def : Pat<(VT128 (vector_insert V128:$src,
3887 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3889 (INS V128:$src, imm:$Immd,
3890 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3892 def : Pat<(VT64 (vector_insert V64:$src,
3893 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3895 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3896 imm:$Immd, V128:$Rn, imm:$Immn),
3899 def : Pat<(VT64 (vector_insert V64:$src,
3900 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3903 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3904 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3908 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3909 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3910 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3913 // Floating point vector extractions are codegen'd as either a sequence of
3914 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
3915 // the lane number is anything other than zero.
3916 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3917 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3918 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3919 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3920 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3921 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3923 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3924 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
3925 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3926 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
3927 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3928 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
3930 // All concat_vectors operations are canonicalised to act on i64 vectors for
3931 // AArch64. In the general case we need an instruction, which had just as well be
3933 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3934 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3935 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3936 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3938 def : ConcatPat<v2i64, v1i64>;
3939 def : ConcatPat<v2f64, v1f64>;
3940 def : ConcatPat<v4i32, v2i32>;
3941 def : ConcatPat<v4f32, v2f32>;
3942 def : ConcatPat<v8i16, v4i16>;
3943 def : ConcatPat<v8f16, v4f16>;
3944 def : ConcatPat<v16i8, v8i8>;
3946 // If the high lanes are undef, though, we can just ignore them:
3947 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3948 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3949 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3951 def : ConcatUndefPat<v2i64, v1i64>;
3952 def : ConcatUndefPat<v2f64, v1f64>;
3953 def : ConcatUndefPat<v4i32, v2i32>;
3954 def : ConcatUndefPat<v4f32, v2f32>;
3955 def : ConcatUndefPat<v8i16, v4i16>;
3956 def : ConcatUndefPat<v16i8, v8i8>;
3958 //----------------------------------------------------------------------------
3959 // AdvSIMD across lanes instructions
3960 //----------------------------------------------------------------------------
3962 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3963 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3964 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3965 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3966 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3967 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3968 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3969 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3970 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3971 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3972 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3974 // Patterns for across-vector intrinsics, that have a node equivalent, that
3975 // returns a vector (with only the low lane defined) instead of a scalar.
3976 // In effect, opNode is the same as (scalar_to_vector (IntNode)).
3977 multiclass SIMDAcrossLanesIntrinsic<string baseOpc,
3978 SDPatternOperator opNode> {
3979 // If a lane instruction caught the vector_extract around opNode, we can
3980 // directly match the latter to the instruction.
3981 def : Pat<(v8i8 (opNode V64:$Rn)),
3982 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3983 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;
3984 def : Pat<(v16i8 (opNode V128:$Rn)),
3985 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3986 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;
3987 def : Pat<(v4i16 (opNode V64:$Rn)),
3988 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3989 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;
3990 def : Pat<(v8i16 (opNode V128:$Rn)),
3991 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3992 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;
3993 def : Pat<(v4i32 (opNode V128:$Rn)),
3994 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3995 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;
3998 // If none did, fallback to the explicit patterns, consuming the vector_extract.
3999 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
4000 (i32 0)), (i64 0))),
4001 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
4002 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),
4004 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
4005 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4006 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),
4008 def : Pat<(i32 (vector_extract (insert_subvector undef,
4009 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))),
4010 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
4011 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),
4013 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
4014 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4015 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),
4017 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
4018 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4019 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),
4024 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,
4025 SDPatternOperator opNode>
4026 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4027 // If there is a sign extension after this intrinsic, consume it as smov already
4029 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4030 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)),
4032 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4033 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4035 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4036 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),
4038 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4039 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4041 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4042 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)),
4044 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4045 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4047 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4048 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),
4050 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4051 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4055 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
4056 SDPatternOperator opNode>
4057 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4058 // If there is a masking operation keeping only what has been actually
4059 // generated, consume it.
4060 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4061 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)),
4062 (i32 (EXTRACT_SUBREG
4063 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4064 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4066 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
4068 (i32 (EXTRACT_SUBREG
4069 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4070 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4072 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4073 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)),
4074 (i32 (EXTRACT_SUBREG
4075 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4076 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4078 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
4080 (i32 (EXTRACT_SUBREG
4081 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4082 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4086 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;
4087 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4088 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
4089 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4091 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;
4092 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4093 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
4094 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4096 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;
4097 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
4098 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
4100 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
4101 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
4102 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
4104 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;
4105 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
4106 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
4108 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
4109 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
4110 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
4112 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
4113 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4115 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4116 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4118 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4120 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4121 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4124 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4125 (i32 (EXTRACT_SUBREG
4126 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4127 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4129 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4130 (i32 (EXTRACT_SUBREG
4131 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4132 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4135 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4136 (i64 (EXTRACT_SUBREG
4137 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4138 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4142 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
4144 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4145 (i32 (EXTRACT_SUBREG
4146 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4147 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4149 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4150 (i32 (EXTRACT_SUBREG
4151 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4152 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4155 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4156 (i32 (EXTRACT_SUBREG
4157 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4158 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4160 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4161 (i32 (EXTRACT_SUBREG
4162 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4163 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4166 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4167 (i64 (EXTRACT_SUBREG
4168 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4169 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4173 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
4174 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
4176 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
4177 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
4178 (i64 (EXTRACT_SUBREG
4179 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4180 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
4182 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4183 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4184 (i64 (EXTRACT_SUBREG
4185 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4186 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4189 //------------------------------------------------------------------------------
4190 // AdvSIMD modified immediate instructions
4191 //------------------------------------------------------------------------------
4194 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4196 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4198 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4199 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4200 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4201 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4203 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4204 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4205 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4206 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4208 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4209 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4210 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4211 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4213 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4214 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4215 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4216 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4219 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
4221 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4222 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
4224 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4225 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
4227 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4231 // EDIT byte mask: scalar
4232 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4233 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4234 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4235 // The movi_edit node has the immediate value already encoded, so we use
4236 // a plain imm0_255 here.
4237 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4238 (MOVID imm0_255:$shift)>;
4240 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4241 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4242 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4243 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4245 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4246 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4247 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4248 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4250 // EDIT byte mask: 2d
4252 // The movi_edit node has the immediate value already encoded, so we use
4253 // a plain imm0_255 in the pattern
4254 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4255 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
4258 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4261 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4262 // Complexity is added to break a tie with a plain MOVI.
4263 let AddedComplexity = 1 in {
4264 def : Pat<(f32 fpimm0),
4265 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4267 def : Pat<(f64 fpimm0),
4268 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4272 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4273 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4274 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4275 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4277 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4278 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4279 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4280 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4282 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4283 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4285 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4286 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4288 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4289 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4290 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4291 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4293 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4294 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4295 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4296 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4298 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4299 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4300 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4301 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4302 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4303 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4304 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4305 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4307 // EDIT per word: 2s & 4s with MSL shifter
4308 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4309 [(set (v2i32 V64:$Rd),
4310 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4311 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4312 [(set (v4i32 V128:$Rd),
4313 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4315 // Per byte: 8b & 16b
4316 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4318 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4319 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4321 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4325 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4326 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4328 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4329 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4330 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4331 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4333 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4334 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4335 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4336 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4338 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4339 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4340 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4341 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4342 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4343 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4344 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4345 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4347 // EDIT per word: 2s & 4s with MSL shifter
4348 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4349 [(set (v2i32 V64:$Rd),
4350 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4351 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4352 [(set (v4i32 V128:$Rd),
4353 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4355 //----------------------------------------------------------------------------
4356 // AdvSIMD indexed element
4357 //----------------------------------------------------------------------------
4359 let hasSideEffects = 0 in {
4360 defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">;
4361 defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">;
4364 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4365 // instruction expects the addend first, while the intrinsic expects it last.
4367 // On the other hand, there are quite a few valid combinatorial options due to
4368 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4369 defm : SIMDFPIndexedTiedPatterns<"FMLA",
4370 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4371 defm : SIMDFPIndexedTiedPatterns<"FMLA",
4372 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4374 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4375 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4376 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4377 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4378 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4379 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4380 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4381 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4383 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4384 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4386 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4387 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4388 VectorIndexS:$idx))),
4389 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4390 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4391 (v2f32 (AArch64duplane32
4392 (v4f32 (insert_subvector undef,
4393 (v2f32 (fneg V64:$Rm)),
4395 VectorIndexS:$idx)))),
4396 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4397 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4398 VectorIndexS:$idx)>;
4399 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4400 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4401 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4402 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4404 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4406 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4407 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4408 VectorIndexS:$idx))),
4409 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4410 VectorIndexS:$idx)>;
4411 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4412 (v4f32 (AArch64duplane32
4413 (v4f32 (insert_subvector undef,
4414 (v2f32 (fneg V64:$Rm)),
4416 VectorIndexS:$idx)))),
4417 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4418 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4419 VectorIndexS:$idx)>;
4420 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4421 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4422 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4423 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4425 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4426 // (DUPLANE from 64-bit would be trivial).
4427 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4428 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4429 VectorIndexD:$idx))),
4431 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4432 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4433 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4434 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4435 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4437 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4438 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4439 (vector_extract (v4f32 (fneg V128:$Rm)),
4440 VectorIndexS:$idx))),
4441 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4442 V128:$Rm, VectorIndexS:$idx)>;
4443 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4444 (vector_extract (v4f32 (insert_subvector undef,
4445 (v2f32 (fneg V64:$Rm)),
4447 VectorIndexS:$idx))),
4448 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4449 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4451 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4452 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4453 (vector_extract (v2f64 (fneg V128:$Rm)),
4454 VectorIndexS:$idx))),
4455 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4456 V128:$Rm, VectorIndexS:$idx)>;
4459 defm : FMLSIndexedAfterNegPatterns<
4460 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4461 defm : FMLSIndexedAfterNegPatterns<
4462 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4464 defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4465 defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", fmul>;
4467 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4468 (FMULv2i32_indexed V64:$Rn,
4469 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4471 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4472 (FMULv4i32_indexed V128:$Rn,
4473 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4475 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4476 (FMULv2i64_indexed V128:$Rn,
4477 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4480 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4481 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4482 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4483 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4484 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4485 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4486 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4487 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4488 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4489 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4490 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4491 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4492 int_aarch64_neon_smull>;
4493 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4494 int_aarch64_neon_sqadd>;
4495 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4496 int_aarch64_neon_sqsub>;
4497 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
4498 int_aarch64_neon_sqadd>;
4499 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
4500 int_aarch64_neon_sqsub>;
4501 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4502 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4503 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4504 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4505 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4506 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4507 int_aarch64_neon_umull>;
4509 // A scalar sqdmull with the second operand being a vector lane can be
4510 // handled directly with the indexed instruction encoding.
4511 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4512 (vector_extract (v4i32 V128:$Vm),
4513 VectorIndexS:$idx)),
4514 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4516 //----------------------------------------------------------------------------
4517 // AdvSIMD scalar shift instructions
4518 //----------------------------------------------------------------------------
4519 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4520 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4521 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4522 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4523 // Codegen patterns for the above. We don't put these directly on the
4524 // instructions because TableGen's type inference can't handle the truth.
4525 // Having the same base pattern for fp <--> int totally freaks it out.
4526 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4527 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4528 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4529 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4530 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4531 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4532 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4533 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4534 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4536 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4537 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4539 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4540 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4541 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4542 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4543 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4544 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4545 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4546 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4547 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4548 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4550 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4551 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4553 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4555 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4556 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4557 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4558 int_aarch64_neon_sqrshrn>;
4559 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4560 int_aarch64_neon_sqrshrun>;
4561 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4562 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4563 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4564 int_aarch64_neon_sqshrn>;
4565 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4566 int_aarch64_neon_sqshrun>;
4567 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4568 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4569 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4570 TriOpFrag<(add node:$LHS,
4571 (AArch64srshri node:$MHS, node:$RHS))>>;
4572 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4573 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4574 TriOpFrag<(add node:$LHS,
4575 (AArch64vashr node:$MHS, node:$RHS))>>;
4576 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4577 int_aarch64_neon_uqrshrn>;
4578 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4579 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4580 int_aarch64_neon_uqshrn>;
4581 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4582 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4583 TriOpFrag<(add node:$LHS,
4584 (AArch64urshri node:$MHS, node:$RHS))>>;
4585 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4586 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4587 TriOpFrag<(add node:$LHS,
4588 (AArch64vlshr node:$MHS, node:$RHS))>>;
4590 //----------------------------------------------------------------------------
4591 // AdvSIMD vector shift instructions
4592 //----------------------------------------------------------------------------
4593 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4594 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4595 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4596 int_aarch64_neon_vcvtfxs2fp>;
4597 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4598 int_aarch64_neon_rshrn>;
4599 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4600 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4601 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4602 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4603 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4604 (i32 vecshiftL64:$imm))),
4605 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4606 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4607 int_aarch64_neon_sqrshrn>;
4608 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4609 int_aarch64_neon_sqrshrun>;
4610 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4611 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4612 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4613 int_aarch64_neon_sqshrn>;
4614 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4615 int_aarch64_neon_sqshrun>;
4616 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4617 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4618 (i32 vecshiftR64:$imm))),
4619 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4620 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4621 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4622 TriOpFrag<(add node:$LHS,
4623 (AArch64srshri node:$MHS, node:$RHS))> >;
4624 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4625 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4627 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4628 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4629 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4630 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4631 int_aarch64_neon_vcvtfxu2fp>;
4632 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4633 int_aarch64_neon_uqrshrn>;
4634 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4635 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4636 int_aarch64_neon_uqshrn>;
4637 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4638 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4639 TriOpFrag<(add node:$LHS,
4640 (AArch64urshri node:$MHS, node:$RHS))> >;
4641 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4642 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4643 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4644 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4645 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4647 // SHRN patterns for when a logical right shift was used instead of arithmetic
4648 // (the immediate guarantees no sign bits actually end up in the result so it
4650 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4651 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4652 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4653 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4654 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4655 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4657 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4658 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4659 vecshiftR16Narrow:$imm)))),
4660 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4661 V128:$Rn, vecshiftR16Narrow:$imm)>;
4662 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4663 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4664 vecshiftR32Narrow:$imm)))),
4665 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4666 V128:$Rn, vecshiftR32Narrow:$imm)>;
4667 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4668 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4669 vecshiftR64Narrow:$imm)))),
4670 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4671 V128:$Rn, vecshiftR32Narrow:$imm)>;
4673 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4674 // Anyexts are implemented as zexts.
4675 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4676 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4677 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4678 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4679 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4680 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4681 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4682 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4683 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4684 // Also match an extend from the upper half of a 128 bit source register.
4685 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4686 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4687 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4688 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4689 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4690 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4691 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4692 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4693 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4694 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4695 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4696 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4697 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4698 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4699 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4700 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4701 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4702 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4704 // Vector shift sxtl aliases
4705 def : InstAlias<"sxtl.8h $dst, $src1",
4706 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4707 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4708 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4709 def : InstAlias<"sxtl.4s $dst, $src1",
4710 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4711 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4712 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4713 def : InstAlias<"sxtl.2d $dst, $src1",
4714 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4715 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4716 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4718 // Vector shift sxtl2 aliases
4719 def : InstAlias<"sxtl2.8h $dst, $src1",
4720 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4721 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4722 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4723 def : InstAlias<"sxtl2.4s $dst, $src1",
4724 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4725 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4726 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4727 def : InstAlias<"sxtl2.2d $dst, $src1",
4728 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4729 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4730 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4732 // Vector shift uxtl aliases
4733 def : InstAlias<"uxtl.8h $dst, $src1",
4734 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4735 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4736 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4737 def : InstAlias<"uxtl.4s $dst, $src1",
4738 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4739 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4740 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4741 def : InstAlias<"uxtl.2d $dst, $src1",
4742 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4743 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4744 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4746 // Vector shift uxtl2 aliases
4747 def : InstAlias<"uxtl2.8h $dst, $src1",
4748 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4749 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4750 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4751 def : InstAlias<"uxtl2.4s $dst, $src1",
4752 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4753 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4754 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4755 def : InstAlias<"uxtl2.2d $dst, $src1",
4756 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4757 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4758 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4760 // If an integer is about to be converted to a floating point value,
4761 // just load it on the floating point unit.
4762 // These patterns are more complex because floating point loads do not
4763 // support sign extension.
4764 // The sign extension has to be explicitly added and is only supported for
4765 // one step: byte-to-half, half-to-word, word-to-doubleword.
4766 // SCVTF GPR -> FPR is 9 cycles.
4767 // SCVTF FPR -> FPR is 4 cyclces.
4768 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4769 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4770 // and still being faster.
4771 // However, this is not good for code size.
4772 // 8-bits -> float. 2 sizes step-up.
4773 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4774 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4775 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4780 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4786 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4788 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4789 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4790 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4791 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4792 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4793 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4794 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4795 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4797 // 16-bits -> float. 1 size step-up.
4798 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4799 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4800 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4802 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4806 ssub)))>, Requires<[NotForCodeSize]>;
4808 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4809 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4810 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4811 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4812 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4813 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4814 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4815 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4817 // 32-bits to 32-bits are handled in target specific dag combine:
4818 // performIntToFpCombine.
4819 // 64-bits integer to 32-bits floating point, not possible with
4820 // SCVTF on floating point registers (both source and destination
4821 // must have the same size).
4823 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4824 // 8-bits -> double. 3 size step-up: give up.
4825 // 16-bits -> double. 2 size step.
4826 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4827 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4828 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4833 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4839 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4841 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4842 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4843 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4844 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4845 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4846 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4847 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4848 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4849 // 32-bits -> double. 1 size step-up.
4850 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4851 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4852 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4854 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4858 dsub)))>, Requires<[NotForCodeSize]>;
4860 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4861 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4862 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4863 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4864 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4865 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4866 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4867 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4869 // 64-bits -> double are handled in target specific dag combine:
4870 // performIntToFpCombine.
4873 //----------------------------------------------------------------------------
4874 // AdvSIMD Load-Store Structure
4875 //----------------------------------------------------------------------------
4876 defm LD1 : SIMDLd1Multiple<"ld1">;
4877 defm LD2 : SIMDLd2Multiple<"ld2">;
4878 defm LD3 : SIMDLd3Multiple<"ld3">;
4879 defm LD4 : SIMDLd4Multiple<"ld4">;
4881 defm ST1 : SIMDSt1Multiple<"st1">;
4882 defm ST2 : SIMDSt2Multiple<"st2">;
4883 defm ST3 : SIMDSt3Multiple<"st3">;
4884 defm ST4 : SIMDSt4Multiple<"st4">;
4886 class Ld1Pat<ValueType ty, Instruction INST>
4887 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4889 def : Ld1Pat<v16i8, LD1Onev16b>;
4890 def : Ld1Pat<v8i16, LD1Onev8h>;
4891 def : Ld1Pat<v4i32, LD1Onev4s>;
4892 def : Ld1Pat<v2i64, LD1Onev2d>;
4893 def : Ld1Pat<v8i8, LD1Onev8b>;
4894 def : Ld1Pat<v4i16, LD1Onev4h>;
4895 def : Ld1Pat<v2i32, LD1Onev2s>;
4896 def : Ld1Pat<v1i64, LD1Onev1d>;
4898 class St1Pat<ValueType ty, Instruction INST>
4899 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4900 (INST ty:$Vt, GPR64sp:$Rn)>;
4902 def : St1Pat<v16i8, ST1Onev16b>;
4903 def : St1Pat<v8i16, ST1Onev8h>;
4904 def : St1Pat<v4i32, ST1Onev4s>;
4905 def : St1Pat<v2i64, ST1Onev2d>;
4906 def : St1Pat<v8i8, ST1Onev8b>;
4907 def : St1Pat<v4i16, ST1Onev4h>;
4908 def : St1Pat<v2i32, ST1Onev2s>;
4909 def : St1Pat<v1i64, ST1Onev1d>;
4915 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4916 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4917 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4918 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4919 let mayLoad = 1, hasSideEffects = 0 in {
4920 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4921 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4922 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4923 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4924 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4925 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4926 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4927 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4928 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4929 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4930 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4931 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4932 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4933 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4934 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4935 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4938 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4939 (LD1Rv8b GPR64sp:$Rn)>;
4940 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4941 (LD1Rv16b GPR64sp:$Rn)>;
4942 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4943 (LD1Rv4h GPR64sp:$Rn)>;
4944 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4945 (LD1Rv8h GPR64sp:$Rn)>;
4946 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4947 (LD1Rv2s GPR64sp:$Rn)>;
4948 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4949 (LD1Rv4s GPR64sp:$Rn)>;
4950 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4951 (LD1Rv2d GPR64sp:$Rn)>;
4952 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4953 (LD1Rv1d GPR64sp:$Rn)>;
4954 // Grab the floating point version too
4955 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4956 (LD1Rv2s GPR64sp:$Rn)>;
4957 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4958 (LD1Rv4s GPR64sp:$Rn)>;
4959 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4960 (LD1Rv2d GPR64sp:$Rn)>;
4961 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4962 (LD1Rv1d GPR64sp:$Rn)>;
4963 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4964 (LD1Rv4h GPR64sp:$Rn)>;
4965 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4966 (LD1Rv8h GPR64sp:$Rn)>;
4968 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4969 ValueType VTy, ValueType STy, Instruction LD1>
4970 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4971 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4972 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4974 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4975 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4976 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4977 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4978 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4979 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4980 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4982 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4983 ValueType VTy, ValueType STy, Instruction LD1>
4984 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4985 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4987 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4988 VecIndex:$idx, GPR64sp:$Rn),
4991 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4992 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4993 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4994 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4995 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4998 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4999 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
5000 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
5001 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
5004 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
5005 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
5006 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
5007 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
5009 let AddedComplexity = 19 in
5010 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5011 ValueType VTy, ValueType STy, Instruction ST1>
5013 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5015 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
5017 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
5018 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
5019 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
5020 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
5021 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
5022 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
5023 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
5025 let AddedComplexity = 19 in
5026 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5027 ValueType VTy, ValueType STy, Instruction ST1>
5029 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5031 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5032 VecIndex:$idx, GPR64sp:$Rn)>;
5034 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
5035 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
5036 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
5037 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
5038 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
5040 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5041 ValueType VTy, ValueType STy, Instruction ST1,
5043 def : Pat<(scalar_store
5044 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5045 GPR64sp:$Rn, offset),
5046 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5047 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5049 def : Pat<(scalar_store
5050 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5051 GPR64sp:$Rn, GPR64:$Rm),
5052 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5053 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5056 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
5057 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
5059 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
5060 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
5061 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
5062 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
5063 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
5065 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5066 ValueType VTy, ValueType STy, Instruction ST1,
5068 def : Pat<(scalar_store
5069 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5070 GPR64sp:$Rn, offset),
5071 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5073 def : Pat<(scalar_store
5074 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5075 GPR64sp:$Rn, GPR64:$Rm),
5076 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5079 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
5081 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
5083 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
5084 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
5085 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
5086 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
5087 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
5089 let mayStore = 1, hasSideEffects = 0 in {
5090 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
5091 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
5092 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
5093 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
5094 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
5095 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
5096 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
5097 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
5098 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
5099 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
5100 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
5101 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
5104 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
5105 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
5106 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
5107 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
5109 //----------------------------------------------------------------------------
5110 // Crypto extensions
5111 //----------------------------------------------------------------------------
5113 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
5114 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
5115 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
5116 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
5118 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
5119 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
5120 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
5121 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
5122 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
5123 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
5124 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
5126 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
5127 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
5128 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
5130 //----------------------------------------------------------------------------
5132 //----------------------------------------------------------------------------
5133 // FIXME: Like for X86, these should go in their own separate .td file.
5135 // Any instruction that defines a 32-bit result leaves the high half of the
5136 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
5137 // be copying from a truncate. But any other 32-bit operation will zero-extend
5139 // FIXME: X86 also checks for CMOV here. Do we need something similar?
5140 def def32 : PatLeaf<(i32 GPR32:$src), [{
5141 return N->getOpcode() != ISD::TRUNCATE &&
5142 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
5143 N->getOpcode() != ISD::CopyFromReg;
5146 // In the case of a 32-bit def that is known to implicitly zero-extend,
5147 // we can use a SUBREG_TO_REG.
5148 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
5150 // For an anyext, we don't care what the high bits are, so we can perform an
5151 // INSERT_SUBREF into an IMPLICIT_DEF.
5152 def : Pat<(i64 (anyext GPR32:$src)),
5153 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
5155 // When we need to explicitly zero-extend, we use a 32-bit MOV instruction and
5156 // then assert the extension has happened.
5157 def : Pat<(i64 (zext GPR32:$src)),
5158 (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>;
5160 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
5161 // containing super-reg.
5162 def : Pat<(i64 (sext GPR32:$src)),
5163 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5164 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
5165 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
5166 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
5167 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
5168 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
5169 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
5170 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
5172 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
5173 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5174 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
5175 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
5176 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5177 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
5179 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
5180 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5181 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
5182 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
5183 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5184 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
5186 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
5187 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5188 (i64 (i64shift_a imm0_63:$imm)),
5189 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
5191 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
5192 // AddedComplexity for the following patterns since we want to match sext + sra
5193 // patterns before we attempt to match a single sra node.
5194 let AddedComplexity = 20 in {
5195 // We support all sext + sra combinations which preserve at least one bit of the
5196 // original value which is to be sign extended. E.g. we support shifts up to
5198 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
5199 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
5200 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
5201 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
5203 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
5204 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
5205 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
5206 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
5208 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
5209 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5210 (i64 imm0_31:$imm), 31)>;
5211 } // AddedComplexity = 20
5213 // To truncate, we can simply extract from a subregister.
5214 def : Pat<(i32 (trunc GPR64sp:$src)),
5215 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5217 // __builtin_trap() uses the BRK instruction on AArch64.
5218 def : Pat<(trap), (BRK 1)>;
5220 // Conversions within AdvSIMD types in the same register size are free.
5221 // But because we need a consistent lane ordering, in big endian many
5222 // conversions require one or more REV instructions.
5224 // Consider a simple memory load followed by a bitconvert then a store.
5226 // v1 = BITCAST v2i32 v0 to v4i16
5229 // In big endian mode every memory access has an implicit byte swap. LDR and
5230 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5231 // is, they treat the vector as a sequence of elements to be byte-swapped.
5232 // The two pairs of instructions are fundamentally incompatible. We've decided
5233 // to use LD1/ST1 only to simplify compiler implementation.
5235 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5236 // the original code sequence:
5238 // v1 = REV v2i32 (implicit)
5239 // v2 = BITCAST v2i32 v1 to v4i16
5240 // v3 = REV v4i16 v2 (implicit)
5243 // But this is now broken - the value stored is different to the value loaded
5244 // due to lane reordering. To fix this, on every BITCAST we must perform two
5247 // v1 = REV v2i32 (implicit)
5249 // v3 = BITCAST v2i32 v2 to v4i16
5251 // v5 = REV v4i16 v4 (implicit)
5254 // This means an extra two instructions, but actually in most cases the two REV
5255 // instructions can be combined into one. For example:
5256 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5258 // There is also no 128-bit REV instruction. This must be synthesized with an
5261 // Most bitconverts require some sort of conversion. The only exceptions are:
5262 // a) Identity conversions - vNfX <-> vNiX
5263 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5266 // Natural vector casts (64 bit)
5267 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5268 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5269 def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5270 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5271 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5272 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5274 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5275 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5276 def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5277 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5278 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5280 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5281 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5282 def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5283 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5284 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5286 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5287 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5288 def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5289 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5290 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5291 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5292 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5294 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5295 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5296 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5297 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5298 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5300 // Natural vector casts (128 bit)
5301 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5302 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5303 def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5304 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5305 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5306 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5307 def : Pat<(v2f64 (AArch64NvCast (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5309 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5310 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5311 def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5312 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5313 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5314 def : Pat<(v4f32 (AArch64NvCast (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5315 def : Pat<(v2f64 (AArch64NvCast (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5317 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5318 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5319 def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5320 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5321 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5322 def : Pat<(v4f32 (AArch64NvCast (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5323 def : Pat<(v2f64 (AArch64NvCast (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5325 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5326 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5327 def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5328 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5329 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5330 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5331 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5333 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5334 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5335 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5336 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5337 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5338 def : Pat<(v8f16 (AArch64NvCast (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5339 def : Pat<(v2f64 (AArch64NvCast (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5341 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5342 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5343 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5344 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5345 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5346 def : Pat<(v8f16 (AArch64NvCast (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5347 def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5349 let Predicates = [IsLE] in {
5350 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5351 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5352 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5353 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5354 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5356 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5357 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5358 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5359 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5360 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5361 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5362 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5363 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5364 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5365 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5366 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5367 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5369 let Predicates = [IsBE] in {
5370 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5371 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5372 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5373 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5374 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5375 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5376 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5377 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5378 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5379 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5381 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5382 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5383 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5384 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5385 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5386 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5387 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5388 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5389 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5390 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5392 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5393 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5394 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5395 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5396 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5397 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5398 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5399 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5400 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5402 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5403 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5404 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5405 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5406 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5407 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5408 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5409 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5410 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5411 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5413 let Predicates = [IsLE] in {
5414 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5415 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5416 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5417 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5418 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5420 let Predicates = [IsBE] in {
5421 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5422 (v1i64 (REV64v2i32 FPR64:$src))>;
5423 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5424 (v1i64 (REV64v4i16 FPR64:$src))>;
5425 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5426 (v1i64 (REV64v8i8 FPR64:$src))>;
5427 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5428 (v1i64 (REV64v4i16 FPR64:$src))>;
5429 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5430 (v1i64 (REV64v2i32 FPR64:$src))>;
5432 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5433 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5435 let Predicates = [IsLE] in {
5436 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5437 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5438 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5439 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5440 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5441 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5443 let Predicates = [IsBE] in {
5444 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5445 (v2i32 (REV64v2i32 FPR64:$src))>;
5446 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5447 (v2i32 (REV32v4i16 FPR64:$src))>;
5448 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5449 (v2i32 (REV32v8i8 FPR64:$src))>;
5450 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5451 (v2i32 (REV64v2i32 FPR64:$src))>;
5452 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5453 (v2i32 (REV64v2i32 FPR64:$src))>;
5454 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5455 (v2i32 (REV64v4i16 FPR64:$src))>;
5457 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5459 let Predicates = [IsLE] in {
5460 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5461 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5462 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5463 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5464 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5465 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5466 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5468 let Predicates = [IsBE] in {
5469 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5470 (v4i16 (REV64v4i16 FPR64:$src))>;
5471 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5472 (v4i16 (REV32v4i16 FPR64:$src))>;
5473 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5474 (v4i16 (REV16v8i8 FPR64:$src))>;
5475 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5476 (v4i16 (REV64v4i16 FPR64:$src))>;
5477 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5478 (v4i16 (REV32v4i16 FPR64:$src))>;
5479 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5480 (v4i16 (REV32v4i16 FPR64:$src))>;
5481 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5482 (v4i16 (REV64v4i16 FPR64:$src))>;
5485 let Predicates = [IsLE] in {
5486 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5487 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5488 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5489 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5490 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5491 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5492 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5494 let Predicates = [IsBE] in {
5495 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5496 (v4f16 (REV64v4i16 FPR64:$src))>;
5497 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5498 (v4f16 (REV64v4i16 FPR64:$src))>;
5499 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5500 (v4f16 (REV64v4i16 FPR64:$src))>;
5501 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5502 (v4f16 (REV16v8i8 FPR64:$src))>;
5503 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5504 (v4f16 (REV64v4i16 FPR64:$src))>;
5505 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5506 (v4f16 (REV64v4i16 FPR64:$src))>;
5507 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5508 (v4f16 (REV64v4i16 FPR64:$src))>;
5513 let Predicates = [IsLE] in {
5514 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5515 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5516 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5517 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5518 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5519 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5520 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5522 let Predicates = [IsBE] in {
5523 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5524 (v8i8 (REV64v8i8 FPR64:$src))>;
5525 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5526 (v8i8 (REV32v8i8 FPR64:$src))>;
5527 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5528 (v8i8 (REV16v8i8 FPR64:$src))>;
5529 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5530 (v8i8 (REV64v8i8 FPR64:$src))>;
5531 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5532 (v8i8 (REV32v8i8 FPR64:$src))>;
5533 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5534 (v8i8 (REV64v8i8 FPR64:$src))>;
5535 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5536 (v8i8 (REV16v8i8 FPR64:$src))>;
5539 let Predicates = [IsLE] in {
5540 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5541 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5542 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5543 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5544 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5546 let Predicates = [IsBE] in {
5547 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5548 (f64 (REV64v2i32 FPR64:$src))>;
5549 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5550 (f64 (REV64v4i16 FPR64:$src))>;
5551 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5552 (f64 (REV64v2i32 FPR64:$src))>;
5553 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5554 (f64 (REV64v8i8 FPR64:$src))>;
5555 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5556 (f64 (REV64v4i16 FPR64:$src))>;
5558 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5559 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5561 let Predicates = [IsLE] in {
5562 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5563 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5564 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5565 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5566 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5568 let Predicates = [IsBE] in {
5569 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5570 (v1f64 (REV64v2i32 FPR64:$src))>;
5571 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5572 (v1f64 (REV64v4i16 FPR64:$src))>;
5573 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5574 (v1f64 (REV64v8i8 FPR64:$src))>;
5575 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5576 (v1f64 (REV64v2i32 FPR64:$src))>;
5577 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5578 (v1f64 (REV64v4i16 FPR64:$src))>;
5580 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5581 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5583 let Predicates = [IsLE] in {
5584 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5585 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5586 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5587 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5588 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5589 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5591 let Predicates = [IsBE] in {
5592 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5593 (v2f32 (REV64v2i32 FPR64:$src))>;
5594 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5595 (v2f32 (REV32v4i16 FPR64:$src))>;
5596 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5597 (v2f32 (REV32v8i8 FPR64:$src))>;
5598 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5599 (v2f32 (REV64v2i32 FPR64:$src))>;
5600 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5601 (v2f32 (REV64v2i32 FPR64:$src))>;
5602 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5603 (v2f32 (REV64v4i16 FPR64:$src))>;
5605 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5607 let Predicates = [IsLE] in {
5608 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5609 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5610 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5611 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5612 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5613 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5614 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5616 let Predicates = [IsBE] in {
5617 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5618 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5619 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5620 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5621 (REV64v4i32 FPR128:$src), (i32 8)))>;
5622 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5623 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5624 (REV64v8i16 FPR128:$src), (i32 8)))>;
5625 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5626 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5627 (REV64v8i16 FPR128:$src), (i32 8)))>;
5628 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5629 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5630 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5631 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5632 (REV64v4i32 FPR128:$src), (i32 8)))>;
5633 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5634 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5635 (REV64v16i8 FPR128:$src), (i32 8)))>;
5638 let Predicates = [IsLE] in {
5639 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5640 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5641 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5642 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5643 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5644 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5646 let Predicates = [IsBE] in {
5647 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5648 (v2f64 (EXTv16i8 FPR128:$src,
5649 FPR128:$src, (i32 8)))>;
5650 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5651 (v2f64 (REV64v4i32 FPR128:$src))>;
5652 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5653 (v2f64 (REV64v8i16 FPR128:$src))>;
5654 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5655 (v2f64 (REV64v8i16 FPR128:$src))>;
5656 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5657 (v2f64 (REV64v16i8 FPR128:$src))>;
5658 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5659 (v2f64 (REV64v4i32 FPR128:$src))>;
5661 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5663 let Predicates = [IsLE] in {
5664 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5665 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5666 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5667 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5668 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5669 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5671 let Predicates = [IsBE] in {
5672 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5673 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5674 (REV64v4i32 FPR128:$src), (i32 8)))>;
5675 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5676 (v4f32 (REV32v8i16 FPR128:$src))>;
5677 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5678 (v4f32 (REV32v8i16 FPR128:$src))>;
5679 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5680 (v4f32 (REV32v16i8 FPR128:$src))>;
5681 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5682 (v4f32 (REV64v4i32 FPR128:$src))>;
5683 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5684 (v4f32 (REV64v4i32 FPR128:$src))>;
5686 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5688 let Predicates = [IsLE] in {
5689 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5690 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5691 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5692 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5693 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5694 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5696 let Predicates = [IsBE] in {
5697 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5698 (v2i64 (EXTv16i8 FPR128:$src,
5699 FPR128:$src, (i32 8)))>;
5700 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5701 (v2i64 (REV64v4i32 FPR128:$src))>;
5702 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5703 (v2i64 (REV64v8i16 FPR128:$src))>;
5704 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5705 (v2i64 (REV64v16i8 FPR128:$src))>;
5706 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5707 (v2i64 (REV64v4i32 FPR128:$src))>;
5708 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5709 (v2i64 (REV64v8i16 FPR128:$src))>;
5711 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5713 let Predicates = [IsLE] in {
5714 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5715 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5716 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5717 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5718 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5719 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5721 let Predicates = [IsBE] in {
5722 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5723 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5724 (REV64v4i32 FPR128:$src),
5726 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5727 (v4i32 (REV64v4i32 FPR128:$src))>;
5728 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5729 (v4i32 (REV32v8i16 FPR128:$src))>;
5730 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5731 (v4i32 (REV32v16i8 FPR128:$src))>;
5732 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5733 (v4i32 (REV64v4i32 FPR128:$src))>;
5734 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5735 (v4i32 (REV32v8i16 FPR128:$src))>;
5737 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5739 let Predicates = [IsLE] in {
5740 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5741 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5742 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5743 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5744 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5745 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5746 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5748 let Predicates = [IsBE] in {
5749 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5750 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5751 (REV64v8i16 FPR128:$src),
5753 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5754 (v8i16 (REV64v8i16 FPR128:$src))>;
5755 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5756 (v8i16 (REV32v8i16 FPR128:$src))>;
5757 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5758 (v8i16 (REV16v16i8 FPR128:$src))>;
5759 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5760 (v8i16 (REV64v8i16 FPR128:$src))>;
5761 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5762 (v8i16 (REV32v8i16 FPR128:$src))>;
5763 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5764 (v8i16 (REV32v8i16 FPR128:$src))>;
5767 let Predicates = [IsLE] in {
5768 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5769 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5770 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5771 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5772 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5773 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5774 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5776 let Predicates = [IsBE] in {
5777 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5778 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5779 (REV64v8i16 FPR128:$src),
5781 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5782 (v8f16 (REV64v8i16 FPR128:$src))>;
5783 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5784 (v8f16 (REV32v8i16 FPR128:$src))>;
5785 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5786 (v8f16 (REV64v8i16 FPR128:$src))>;
5787 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5788 (v8f16 (REV16v16i8 FPR128:$src))>;
5789 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5790 (v8f16 (REV64v8i16 FPR128:$src))>;
5791 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5792 (v8f16 (REV32v8i16 FPR128:$src))>;
5795 let Predicates = [IsLE] in {
5796 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5797 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5798 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5799 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5800 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5801 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5802 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5804 let Predicates = [IsBE] in {
5805 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5806 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5807 (REV64v16i8 FPR128:$src),
5809 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5810 (v16i8 (REV64v16i8 FPR128:$src))>;
5811 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5812 (v16i8 (REV32v16i8 FPR128:$src))>;
5813 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5814 (v16i8 (REV16v16i8 FPR128:$src))>;
5815 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5816 (v16i8 (REV64v16i8 FPR128:$src))>;
5817 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5818 (v16i8 (REV32v16i8 FPR128:$src))>;
5819 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5820 (v16i8 (REV16v16i8 FPR128:$src))>;
5823 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))),
5824 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5825 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))),
5826 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5827 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))),
5828 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5829 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))),
5830 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5831 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))),
5832 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5833 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))),
5834 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5835 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))),
5836 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5838 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5839 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5840 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5841 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5842 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5843 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5844 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5845 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5847 // A 64-bit subvector insert to the first 128-bit vector position
5848 // is a subregister copy that needs no instruction.
5849 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5850 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5851 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5852 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5853 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5854 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5855 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5856 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5857 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5858 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5859 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5860 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5861 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5862 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5864 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5866 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5867 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5868 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5869 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5870 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5871 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5872 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5873 // so we match on v4f32 here, not v2f32. This will also catch adding
5874 // the low two lanes of a true v4f32 vector.
5875 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5876 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5877 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5879 // Scalar 64-bit shifts in FPR64 registers.
5880 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5881 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5882 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5883 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5884 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5885 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5886 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5887 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5889 // Patterns for nontemporal/no-allocate stores.
5890 // We have to resort to tricks to turn a single-input store into a store pair,
5891 // because there is no single-input nontemporal store, only STNP.
5892 let Predicates = [IsLE] in {
5893 let AddedComplexity = 15 in {
5894 class NTStore128Pat<ValueType VT> :
5895 Pat<(nontemporalstore (VT FPR128:$Rt),
5896 (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),
5897 (STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub),
5898 (CPYi64 FPR128:$Rt, (i64 1)),
5899 GPR64sp:$Rn, simm7s8:$offset)>;
5901 def : NTStore128Pat<v2i64>;
5902 def : NTStore128Pat<v4i32>;
5903 def : NTStore128Pat<v8i16>;
5904 def : NTStore128Pat<v16i8>;
5906 class NTStore64Pat<ValueType VT> :
5907 Pat<(nontemporalstore (VT FPR64:$Rt),
5908 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),
5909 (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub),
5910 (CPYi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)),
5911 GPR64sp:$Rn, simm7s4:$offset)>;
5913 // FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64?
5914 def : NTStore64Pat<v1f64>;
5915 def : NTStore64Pat<v1i64>;
5916 def : NTStore64Pat<v2i32>;
5917 def : NTStore64Pat<v4i16>;
5918 def : NTStore64Pat<v8i8>;
5920 def : Pat<(nontemporalstore GPR64:$Rt,
5921 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),
5922 (STNPWi (EXTRACT_SUBREG GPR64:$Rt, sub_32),
5923 (EXTRACT_SUBREG (UBFMXri GPR64:$Rt, 0, 31), sub_32),
5924 GPR64sp:$Rn, simm7s4:$offset)>;
5925 } // AddedComplexity=10
5926 } // Predicates = [IsLE]
5928 // Tail call return handling. These are all compiler pseudo-instructions,
5929 // so no encoding information or anything like that.
5930 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5931 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5932 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5935 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5936 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5937 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5938 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5939 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5940 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5942 include "AArch64InstrAtomics.td"