1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
18 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
19 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
20 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
21 def HasNEON : Predicate<"Subtarget->hasNEON()">,
22 AssemblerPredicate<"FeatureNEON", "neon">;
23 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
24 AssemblerPredicate<"FeatureCrypto", "crypto">;
25 def HasCRC : Predicate<"Subtarget->hasCRC()">,
26 AssemblerPredicate<"FeatureCRC", "crc">;
27 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
28 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
29 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
31 //===----------------------------------------------------------------------===//
32 // AArch64-specific DAG Nodes.
35 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
36 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
39 SDTCisInt<0>, SDTCisVT<1, i32>]>;
41 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
42 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
48 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
49 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
56 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
59 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
60 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
61 SDTCisVT<2, OtherVT>]>;
64 def SDT_AArch64CSel : SDTypeProfile<1, 4,
69 def SDT_AArch64CCMP : SDTypeProfile<1, 5,
76 def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
83 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
86 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
87 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
88 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
91 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
92 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
93 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
94 SDTCisInt<2>, SDTCisInt<3>]>;
95 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
96 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
97 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
98 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
100 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
101 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
102 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
103 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
105 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
108 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
109 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
111 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
113 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
116 // Generates the general dynamic sequences, i.e.
117 // adrp x0, :tlsdesc:var
118 // ldr x1, [x0, #:tlsdesc_lo12:var]
119 // add x0, x0, #:tlsdesc_lo12:var
123 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
124 // number of operands (the variable)
125 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
128 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
129 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
130 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
131 SDTCisSameAs<1, 4>]>;
135 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
136 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
137 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
138 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
139 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
140 [SDNPHasChain, SDNPOutGlue]>;
141 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
142 SDCallSeqEnd<[ SDTCisVT<0, i32>,
144 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
145 def AArch64call : SDNode<"AArch64ISD::CALL",
146 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
147 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
149 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
151 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
153 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
155 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
157 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
161 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
162 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
163 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
164 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
165 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
166 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
167 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
168 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
169 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
171 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
172 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
174 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
175 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
177 def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>;
178 def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>;
179 def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>;
181 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
183 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
185 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
186 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
188 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
189 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
190 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
191 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
192 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
194 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
195 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
196 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
197 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
198 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
199 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
201 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
202 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
203 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
204 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
205 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
206 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
207 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
209 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
210 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
211 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
212 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
214 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
215 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
216 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
217 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
218 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
219 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
220 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
221 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
223 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
224 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
225 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
227 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
228 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
229 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
230 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
231 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
233 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
234 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
235 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
237 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
238 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
239 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
240 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
241 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
242 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
243 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
245 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
246 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
247 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
248 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
249 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
251 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
252 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
254 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
256 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
257 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
259 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
260 [SDNPHasChain, SDNPSideEffect]>;
262 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
263 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
265 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
266 SDT_AArch64TLSDescCallSeq,
267 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
271 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
272 SDT_AArch64WrapperLarge>;
274 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
276 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
277 SDTCisSameAs<1, 2>]>;
278 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
279 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
281 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
282 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
283 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
284 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
285 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
286 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
288 //===----------------------------------------------------------------------===//
290 //===----------------------------------------------------------------------===//
292 // AArch64 Instruction Predicate Definitions.
294 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
295 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
296 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
297 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
298 def ForCodeSize : Predicate<"ForCodeSize">;
299 def NotForCodeSize : Predicate<"!ForCodeSize">;
301 include "AArch64InstrFormats.td"
303 //===----------------------------------------------------------------------===//
305 //===----------------------------------------------------------------------===//
306 // Miscellaneous instructions.
307 //===----------------------------------------------------------------------===//
309 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
310 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
311 [(AArch64callseq_start timm:$amt)]>;
312 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
313 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
314 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
316 let isReMaterializable = 1, isCodeGenOnly = 1 in {
317 // FIXME: The following pseudo instructions are only needed because remat
318 // cannot handle multiple instructions. When that changes, they can be
319 // removed, along with the AArch64Wrapper node.
321 let AddedComplexity = 10 in
322 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
323 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
326 // The MOVaddr instruction should match only when the add is not folded
327 // into a load or store address.
329 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
330 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
331 tglobaladdr:$low))]>,
332 Sched<[WriteAdrAdr]>;
334 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
335 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
337 Sched<[WriteAdrAdr]>;
339 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
340 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
342 Sched<[WriteAdrAdr]>;
344 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
345 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
346 tblockaddress:$low))]>,
347 Sched<[WriteAdrAdr]>;
349 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
350 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
351 tglobaltlsaddr:$low))]>,
352 Sched<[WriteAdrAdr]>;
354 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
355 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
356 texternalsym:$low))]>,
357 Sched<[WriteAdrAdr]>;
359 } // isReMaterializable, isCodeGenOnly
361 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
362 (LOADgot tglobaltlsaddr:$addr)>;
364 def : Pat<(AArch64LOADgot texternalsym:$addr),
365 (LOADgot texternalsym:$addr)>;
367 def : Pat<(AArch64LOADgot tconstpool:$addr),
368 (LOADgot tconstpool:$addr)>;
370 //===----------------------------------------------------------------------===//
371 // System instructions.
372 //===----------------------------------------------------------------------===//
374 def HINT : HintI<"hint">;
375 def : InstAlias<"nop", (HINT 0b000)>;
376 def : InstAlias<"yield",(HINT 0b001)>;
377 def : InstAlias<"wfe", (HINT 0b010)>;
378 def : InstAlias<"wfi", (HINT 0b011)>;
379 def : InstAlias<"sev", (HINT 0b100)>;
380 def : InstAlias<"sevl", (HINT 0b101)>;
382 // As far as LLVM is concerned this writes to the system's exclusive monitors.
383 let mayLoad = 1, mayStore = 1 in
384 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
386 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
387 // model patterns with sufficiently fine granularity.
388 let mayLoad = ?, mayStore = ? in {
389 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
390 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
392 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
393 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
395 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
396 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
399 def : InstAlias<"clrex", (CLREX 0xf)>;
400 def : InstAlias<"isb", (ISB 0xf)>;
404 def MSRpstate: MSRpstateI;
406 // The thread pointer (on Linux, at least, where this has been implemented) is
408 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
410 // Generic system instructions
411 def SYSxt : SystemXtI<0, "sys">;
412 def SYSLxt : SystemLXtI<1, "sysl">;
414 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
415 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
416 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
418 //===----------------------------------------------------------------------===//
419 // Move immediate instructions.
420 //===----------------------------------------------------------------------===//
422 defm MOVK : InsertImmediate<0b11, "movk">;
423 defm MOVN : MoveImmediate<0b00, "movn">;
425 let PostEncoderMethod = "fixMOVZ" in
426 defm MOVZ : MoveImmediate<0b10, "movz">;
428 // First group of aliases covers an implicit "lsl #0".
429 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
430 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
431 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
432 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
433 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
434 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
436 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
437 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
438 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
439 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
440 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
442 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
443 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
444 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
445 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
447 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
448 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
449 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
450 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
452 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
453 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
455 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
456 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
458 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
459 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
461 // Final group of aliases covers true "mov $Rd, $imm" cases.
462 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
463 int width, int shift> {
464 def _asmoperand : AsmOperandClass {
465 let Name = basename # width # "_lsl" # shift # "MovAlias";
466 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
468 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
471 def _movimm : Operand<i32> {
472 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
475 def : InstAlias<"mov $Rd, $imm",
476 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
479 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
480 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
482 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
483 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
484 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
485 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
487 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
488 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
490 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
491 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
492 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
493 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
495 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
496 isAsCheapAsAMove = 1 in {
497 // FIXME: The following pseudo instructions are only needed because remat
498 // cannot handle multiple instructions. When that changes, we can select
499 // directly to the real instructions and get rid of these pseudos.
502 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
503 [(set GPR32:$dst, imm:$src)]>,
506 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
507 [(set GPR64:$dst, imm:$src)]>,
509 } // isReMaterializable, isCodeGenOnly
511 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
512 // eventual expansion code fewer bits to worry about getting right. Marshalling
513 // the types is a little tricky though:
514 def i64imm_32bit : ImmLeaf<i64, [{
515 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
518 def trunc_imm : SDNodeXForm<imm, [{
519 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32);
522 def : Pat<(i64 i64imm_32bit:$src),
523 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
525 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
526 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
527 return CurDAG->getTargetConstant(
528 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
531 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
532 return CurDAG->getTargetConstant(
533 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
537 def : Pat<(f32 fpimm:$in),
538 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
539 def : Pat<(f64 fpimm:$in),
540 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
543 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
545 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
546 tglobaladdr:$g1, tglobaladdr:$g0),
547 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
548 tglobaladdr:$g2, 32),
549 tglobaladdr:$g1, 16),
550 tglobaladdr:$g0, 0)>;
552 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
553 tblockaddress:$g1, tblockaddress:$g0),
554 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
555 tblockaddress:$g2, 32),
556 tblockaddress:$g1, 16),
557 tblockaddress:$g0, 0)>;
559 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
560 tconstpool:$g1, tconstpool:$g0),
561 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
566 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
567 tjumptable:$g1, tjumptable:$g0),
568 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
574 //===----------------------------------------------------------------------===//
575 // Arithmetic instructions.
576 //===----------------------------------------------------------------------===//
578 // Add/subtract with carry.
579 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
580 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
582 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
583 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
584 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
585 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
588 defm ADD : AddSub<0, "add", add>;
589 defm SUB : AddSub<1, "sub">;
591 def : InstAlias<"mov $dst, $src",
592 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
593 def : InstAlias<"mov $dst, $src",
594 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
595 def : InstAlias<"mov $dst, $src",
596 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
597 def : InstAlias<"mov $dst, $src",
598 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
600 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
601 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
603 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
604 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
605 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
606 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
607 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
608 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
609 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
610 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
611 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
612 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
613 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
614 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
615 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
616 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
617 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
618 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
619 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
621 // Because of the immediate format for add/sub-imm instructions, the
622 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
623 // These patterns capture that transformation.
624 let AddedComplexity = 1 in {
625 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
626 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
627 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
628 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
629 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
630 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
631 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
632 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
635 // Because of the immediate format for add/sub-imm instructions, the
636 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
637 // These patterns capture that transformation.
638 let AddedComplexity = 1 in {
639 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
640 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
641 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
642 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
643 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
644 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
645 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
646 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
649 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
650 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
651 def : InstAlias<"neg $dst, $src$shift",
652 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
653 def : InstAlias<"neg $dst, $src$shift",
654 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
656 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
657 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
658 def : InstAlias<"negs $dst, $src$shift",
659 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
660 def : InstAlias<"negs $dst, $src$shift",
661 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
664 // Unsigned/Signed divide
665 defm UDIV : Div<0, "udiv", udiv>;
666 defm SDIV : Div<1, "sdiv", sdiv>;
667 let isCodeGenOnly = 1 in {
668 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
669 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
673 defm ASRV : Shift<0b10, "asr", sra>;
674 defm LSLV : Shift<0b00, "lsl", shl>;
675 defm LSRV : Shift<0b01, "lsr", srl>;
676 defm RORV : Shift<0b11, "ror", rotr>;
678 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
679 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
680 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
681 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
682 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
683 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
684 def : ShiftAlias<"rorv", RORVWr, GPR32>;
685 def : ShiftAlias<"rorv", RORVXr, GPR64>;
688 let AddedComplexity = 7 in {
689 defm MADD : MulAccum<0, "madd", add>;
690 defm MSUB : MulAccum<1, "msub", sub>;
692 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
693 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
694 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
695 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
697 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
698 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
699 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
700 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
701 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
702 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
703 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
704 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
705 } // AddedComplexity = 7
707 let AddedComplexity = 5 in {
708 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
709 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
710 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
711 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
713 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
714 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
715 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
716 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
718 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
719 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
720 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
721 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
722 } // AddedComplexity = 5
724 def : MulAccumWAlias<"mul", MADDWrrr>;
725 def : MulAccumXAlias<"mul", MADDXrrr>;
726 def : MulAccumWAlias<"mneg", MSUBWrrr>;
727 def : MulAccumXAlias<"mneg", MSUBXrrr>;
728 def : WideMulAccumAlias<"smull", SMADDLrrr>;
729 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
730 def : WideMulAccumAlias<"umull", UMADDLrrr>;
731 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
734 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
735 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
738 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
739 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
740 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
741 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
743 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
744 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
745 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
746 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
749 defm CAS : CompareAndSwap<0, 0, "">;
750 defm CASA : CompareAndSwap<1, 0, "a">;
751 defm CASL : CompareAndSwap<0, 1, "l">;
752 defm CASAL : CompareAndSwap<1, 1, "al">;
755 defm CASP : CompareAndSwapPair<0, 0, "">;
756 defm CASPA : CompareAndSwapPair<1, 0, "a">;
757 defm CASPL : CompareAndSwapPair<0, 1, "l">;
758 defm CASPAL : CompareAndSwapPair<1, 1, "al">;
761 defm SWP : Swap<0, 0, "">;
762 defm SWPA : Swap<1, 0, "a">;
763 defm SWPL : Swap<0, 1, "l">;
764 defm SWPAL : Swap<1, 1, "al">;
766 // v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)
767 defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
768 defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
769 defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;
770 defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;
772 defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">;
773 defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">;
774 defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">;
775 defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">;
777 defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">;
778 defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">;
779 defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">;
780 defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">;
782 defm LDSET : LDOPregister<0b011, "set", 0, 0, "">;
783 defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">;
784 defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">;
785 defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">;
787 defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">;
788 defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">;
789 defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;
790 defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;
792 defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;
793 defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;
794 defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;
795 defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;
797 defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">;
798 defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">;
799 defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">;
800 defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">;
802 defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">;
803 defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">;
804 defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">;
805 defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">;
807 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
808 defm : STOPregister<"stadd","LDADD">; // STADDx
809 defm : STOPregister<"stclr","LDCLR">; // STCLRx
810 defm : STOPregister<"steor","LDEOR">; // STEORx
811 defm : STOPregister<"stset","LDSET">; // STSETx
812 defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx
813 defm : STOPregister<"stsmin","LDSMIN">;// STSMINx
814 defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
815 defm : STOPregister<"stumin","LDUMIN">;// STUMINx
817 //===----------------------------------------------------------------------===//
818 // Logical instructions.
819 //===----------------------------------------------------------------------===//
822 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
823 defm AND : LogicalImm<0b00, "and", and, "bic">;
824 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
825 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
827 // FIXME: these aliases *are* canonical sometimes (when movz can't be
828 // used). Actually, it seems to be working right now, but putting logical_immXX
829 // here is a bit dodgy on the AsmParser side too.
830 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
831 logical_imm32:$imm), 0>;
832 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
833 logical_imm64:$imm), 0>;
837 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
838 defm BICS : LogicalRegS<0b11, 1, "bics",
839 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
840 defm AND : LogicalReg<0b00, 0, "and", and>;
841 defm BIC : LogicalReg<0b00, 1, "bic",
842 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
843 defm EON : LogicalReg<0b10, 1, "eon",
844 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
845 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
846 defm ORN : LogicalReg<0b01, 1, "orn",
847 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
848 defm ORR : LogicalReg<0b01, 0, "orr", or>;
850 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
851 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
853 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
854 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
856 def : InstAlias<"mvn $Wd, $Wm$sh",
857 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
858 def : InstAlias<"mvn $Xd, $Xm$sh",
859 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
861 def : InstAlias<"tst $src1, $src2",
862 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
863 def : InstAlias<"tst $src1, $src2",
864 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
866 def : InstAlias<"tst $src1, $src2",
867 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
868 def : InstAlias<"tst $src1, $src2",
869 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
871 def : InstAlias<"tst $src1, $src2$sh",
872 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
873 def : InstAlias<"tst $src1, $src2$sh",
874 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
877 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
878 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
881 //===----------------------------------------------------------------------===//
882 // One operand data processing instructions.
883 //===----------------------------------------------------------------------===//
885 defm CLS : OneOperandData<0b101, "cls">;
886 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
887 defm RBIT : OneOperandData<0b000, "rbit">;
889 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
890 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
892 def REV16Wr : OneWRegData<0b001, "rev16",
893 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
894 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
896 def : Pat<(cttz GPR32:$Rn),
897 (CLZWr (RBITWr GPR32:$Rn))>;
898 def : Pat<(cttz GPR64:$Rn),
899 (CLZXr (RBITXr GPR64:$Rn))>;
900 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
903 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
907 // Unlike the other one operand instructions, the instructions with the "rev"
908 // mnemonic do *not* just different in the size bit, but actually use different
909 // opcode bits for the different sizes.
910 def REVWr : OneWRegData<0b010, "rev", bswap>;
911 def REVXr : OneXRegData<0b011, "rev", bswap>;
912 def REV32Xr : OneXRegData<0b010, "rev32",
913 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
915 // The bswap commutes with the rotr so we want a pattern for both possible
917 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
918 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
920 //===----------------------------------------------------------------------===//
921 // Bitfield immediate extraction instruction.
922 //===----------------------------------------------------------------------===//
923 let hasSideEffects = 0 in
924 defm EXTR : ExtractImm<"extr">;
925 def : InstAlias<"ror $dst, $src, $shift",
926 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
927 def : InstAlias<"ror $dst, $src, $shift",
928 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
930 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
931 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
932 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
933 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
935 //===----------------------------------------------------------------------===//
936 // Other bitfield immediate instructions.
937 //===----------------------------------------------------------------------===//
938 let hasSideEffects = 0 in {
939 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
940 defm SBFM : BitfieldImm<0b00, "sbfm">;
941 defm UBFM : BitfieldImm<0b10, "ubfm">;
944 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
945 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
946 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
949 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
950 uint64_t enc = 31 - N->getZExtValue();
951 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
954 // min(7, 31 - shift_amt)
955 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
956 uint64_t enc = 31 - N->getZExtValue();
957 enc = enc > 7 ? 7 : enc;
958 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
961 // min(15, 31 - shift_amt)
962 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
963 uint64_t enc = 31 - N->getZExtValue();
964 enc = enc > 15 ? 15 : enc;
965 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
968 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
969 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
970 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
973 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
974 uint64_t enc = 63 - N->getZExtValue();
975 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
978 // min(7, 63 - shift_amt)
979 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
980 uint64_t enc = 63 - N->getZExtValue();
981 enc = enc > 7 ? 7 : enc;
982 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
985 // min(15, 63 - shift_amt)
986 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
987 uint64_t enc = 63 - N->getZExtValue();
988 enc = enc > 15 ? 15 : enc;
989 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
992 // min(31, 63 - shift_amt)
993 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
994 uint64_t enc = 63 - N->getZExtValue();
995 enc = enc > 31 ? 31 : enc;
996 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
999 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
1000 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
1001 (i64 (i32shift_b imm0_31:$imm)))>;
1002 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
1003 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
1004 (i64 (i64shift_b imm0_63:$imm)))>;
1006 let AddedComplexity = 10 in {
1007 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
1008 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1009 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
1010 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1013 def : InstAlias<"asr $dst, $src, $shift",
1014 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1015 def : InstAlias<"asr $dst, $src, $shift",
1016 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1017 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1018 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1019 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1020 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1021 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1023 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
1024 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1025 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
1026 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1028 def : InstAlias<"lsr $dst, $src, $shift",
1029 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1030 def : InstAlias<"lsr $dst, $src, $shift",
1031 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1032 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1033 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1034 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1035 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1036 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1038 //===----------------------------------------------------------------------===//
1039 // Conditional comparison instructions.
1040 //===----------------------------------------------------------------------===//
1041 defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>;
1042 defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>;
1044 //===----------------------------------------------------------------------===//
1045 // Conditional select instructions.
1046 //===----------------------------------------------------------------------===//
1047 defm CSEL : CondSelect<0, 0b00, "csel">;
1049 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
1050 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1051 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1052 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1054 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1055 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1056 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1057 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1058 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1059 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1060 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1061 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1062 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1063 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1064 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1065 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1067 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
1068 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
1069 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
1070 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
1071 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
1072 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
1073 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
1074 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
1076 // The inverse of the condition code from the alias instruction is what is used
1077 // in the aliased instruction. The parser all ready inverts the condition code
1078 // for these aliases.
1079 def : InstAlias<"cset $dst, $cc",
1080 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1081 def : InstAlias<"cset $dst, $cc",
1082 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1084 def : InstAlias<"csetm $dst, $cc",
1085 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1086 def : InstAlias<"csetm $dst, $cc",
1087 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1089 def : InstAlias<"cinc $dst, $src, $cc",
1090 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1091 def : InstAlias<"cinc $dst, $src, $cc",
1092 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1094 def : InstAlias<"cinv $dst, $src, $cc",
1095 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1096 def : InstAlias<"cinv $dst, $src, $cc",
1097 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1099 def : InstAlias<"cneg $dst, $src, $cc",
1100 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1101 def : InstAlias<"cneg $dst, $src, $cc",
1102 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1104 //===----------------------------------------------------------------------===//
1105 // PC-relative instructions.
1106 //===----------------------------------------------------------------------===//
1107 let isReMaterializable = 1 in {
1108 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1109 def ADR : ADRI<0, "adr", adrlabel, []>;
1110 } // hasSideEffects = 0
1112 def ADRP : ADRI<1, "adrp", adrplabel,
1113 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1114 } // isReMaterializable = 1
1116 // page address of a constant pool entry, block address
1117 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1118 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1120 //===----------------------------------------------------------------------===//
1121 // Unconditional branch (register) instructions.
1122 //===----------------------------------------------------------------------===//
1124 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1125 def RET : BranchReg<0b0010, "ret", []>;
1126 def DRPS : SpecialReturn<0b0101, "drps">;
1127 def ERET : SpecialReturn<0b0100, "eret">;
1128 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1130 // Default to the LR register.
1131 def : InstAlias<"ret", (RET LR)>;
1133 let isCall = 1, Defs = [LR], Uses = [SP] in {
1134 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1137 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1138 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1139 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1141 // Create a separate pseudo-instruction for codegen to use so that we don't
1142 // flag lr as used in every function. It'll be restored before the RET by the
1143 // epilogue if it's legitimately used.
1144 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1145 let isTerminator = 1;
1150 // This is a directive-like pseudo-instruction. The purpose is to insert an
1151 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1152 // (which in the usual case is a BLR).
1153 let hasSideEffects = 1 in
1154 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1155 let AsmString = ".tlsdesccall $sym";
1158 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
1159 // FIXME: can "hasSideEffects be dropped?
1160 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
1161 isCodeGenOnly = 1 in
1163 : Pseudo<(outs), (ins i64imm:$sym),
1164 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>;
1165 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
1166 (TLSDESC_CALLSEQ texternalsym:$sym)>;
1168 //===----------------------------------------------------------------------===//
1169 // Conditional branch (immediate) instruction.
1170 //===----------------------------------------------------------------------===//
1171 def Bcc : BranchCond;
1173 //===----------------------------------------------------------------------===//
1174 // Compare-and-branch instructions.
1175 //===----------------------------------------------------------------------===//
1176 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1177 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1179 //===----------------------------------------------------------------------===//
1180 // Test-bit-and-branch instructions.
1181 //===----------------------------------------------------------------------===//
1182 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1183 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1185 //===----------------------------------------------------------------------===//
1186 // Unconditional branch (immediate) instructions.
1187 //===----------------------------------------------------------------------===//
1188 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1189 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1190 } // isBranch, isTerminator, isBarrier
1192 let isCall = 1, Defs = [LR], Uses = [SP] in {
1193 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1195 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1197 //===----------------------------------------------------------------------===//
1198 // Exception generation instructions.
1199 //===----------------------------------------------------------------------===//
1200 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1201 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1202 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1203 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1204 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1205 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1206 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1207 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1209 // DCPSn defaults to an immediate operand of zero if unspecified.
1210 def : InstAlias<"dcps1", (DCPS1 0)>;
1211 def : InstAlias<"dcps2", (DCPS2 0)>;
1212 def : InstAlias<"dcps3", (DCPS3 0)>;
1214 //===----------------------------------------------------------------------===//
1215 // Load instructions.
1216 //===----------------------------------------------------------------------===//
1218 // Pair (indexed, offset)
1219 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1220 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1221 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1222 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1223 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1225 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1227 // Pair (pre-indexed)
1228 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1229 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1230 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1231 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1232 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1234 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1236 // Pair (post-indexed)
1237 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1238 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1239 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1240 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1241 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1243 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1246 // Pair (no allocate)
1247 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1248 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1249 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1250 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1251 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1254 // (register offset)
1258 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1259 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1260 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1261 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1264 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1265 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1266 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1267 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1268 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1270 // Load sign-extended half-word
1271 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1272 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1274 // Load sign-extended byte
1275 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1276 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1278 // Load sign-extended word
1279 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1282 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1284 // For regular load, we do not have any alignment requirement.
1285 // Thus, it is safe to directly map the vector loads with interesting
1286 // addressing modes.
1287 // FIXME: We could do the same for bitconvert to floating point vectors.
1288 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1289 ValueType ScalTy, ValueType VecTy,
1290 Instruction LOADW, Instruction LOADX,
1292 def : Pat<(VecTy (scalar_to_vector (ScalTy
1293 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1294 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1295 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1298 def : Pat<(VecTy (scalar_to_vector (ScalTy
1299 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1300 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1301 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1305 let AddedComplexity = 10 in {
1306 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1307 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1309 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1310 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1312 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1313 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1315 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1316 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1318 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1319 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1321 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1323 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1326 def : Pat <(v1i64 (scalar_to_vector (i64
1327 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1328 ro_Wextend64:$extend))))),
1329 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1331 def : Pat <(v1i64 (scalar_to_vector (i64
1332 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1333 ro_Xextend64:$extend))))),
1334 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1337 // Match all load 64 bits width whose type is compatible with FPR64
1338 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1339 Instruction LOADW, Instruction LOADX> {
1341 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1342 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1344 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1345 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1348 let AddedComplexity = 10 in {
1349 let Predicates = [IsLE] in {
1350 // We must do vector loads with LD1 in big-endian.
1351 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1352 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1353 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1354 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1355 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1358 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1359 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1361 // Match all load 128 bits width whose type is compatible with FPR128
1362 let Predicates = [IsLE] in {
1363 // We must do vector loads with LD1 in big-endian.
1364 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1365 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1366 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1367 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1368 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1369 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1370 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1372 } // AddedComplexity = 10
1375 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1376 Instruction INSTW, Instruction INSTX> {
1377 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1378 (SUBREG_TO_REG (i64 0),
1379 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1382 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1383 (SUBREG_TO_REG (i64 0),
1384 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1388 let AddedComplexity = 10 in {
1389 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1390 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1391 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1393 // zextloadi1 -> zextloadi8
1394 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1396 // extload -> zextload
1397 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1398 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1399 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1401 // extloadi1 -> zextloadi8
1402 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1407 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1408 Instruction INSTW, Instruction INSTX> {
1409 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1410 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1412 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1413 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1417 let AddedComplexity = 10 in {
1418 // extload -> zextload
1419 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1420 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1421 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1423 // zextloadi1 -> zextloadi8
1424 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1428 // (unsigned immediate)
1430 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1432 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1433 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1435 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1436 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1438 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1439 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1440 [(set (f16 FPR16:$Rt),
1441 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1442 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1443 [(set (f32 FPR32:$Rt),
1444 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1445 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1446 [(set (f64 FPR64:$Rt),
1447 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1448 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1449 [(set (f128 FPR128:$Rt),
1450 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1452 // For regular load, we do not have any alignment requirement.
1453 // Thus, it is safe to directly map the vector loads with interesting
1454 // addressing modes.
1455 // FIXME: We could do the same for bitconvert to floating point vectors.
1456 def : Pat <(v8i8 (scalar_to_vector (i32
1457 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1458 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1459 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1460 def : Pat <(v16i8 (scalar_to_vector (i32
1461 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1462 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1463 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1464 def : Pat <(v4i16 (scalar_to_vector (i32
1465 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1466 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1467 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1468 def : Pat <(v8i16 (scalar_to_vector (i32
1469 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1470 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1471 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1472 def : Pat <(v2i32 (scalar_to_vector (i32
1473 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1474 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1475 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1476 def : Pat <(v4i32 (scalar_to_vector (i32
1477 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1478 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1479 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1480 def : Pat <(v1i64 (scalar_to_vector (i64
1481 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1482 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1483 def : Pat <(v2i64 (scalar_to_vector (i64
1484 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1485 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1486 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1488 // Match all load 64 bits width whose type is compatible with FPR64
1489 let Predicates = [IsLE] in {
1490 // We must use LD1 to perform vector loads in big-endian.
1491 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1492 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1493 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1494 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1495 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1496 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1497 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1498 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1499 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1500 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1502 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1503 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1504 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1505 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1507 // Match all load 128 bits width whose type is compatible with FPR128
1508 let Predicates = [IsLE] in {
1509 // We must use LD1 to perform vector loads in big-endian.
1510 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1511 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1512 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1513 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1514 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1515 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1516 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1517 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1518 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1519 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1520 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1521 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1522 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1523 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1525 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1526 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1528 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1530 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1531 uimm12s2:$offset)))]>;
1532 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1534 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1535 uimm12s1:$offset)))]>;
1537 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1538 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1539 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1540 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1542 // zextloadi1 -> zextloadi8
1543 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1544 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1545 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1546 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1548 // extload -> zextload
1549 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1550 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1551 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1552 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1553 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1554 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1555 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1556 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1557 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1558 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1559 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1560 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1561 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1562 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1564 // load sign-extended half-word
1565 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1567 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1568 uimm12s2:$offset)))]>;
1569 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1571 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1572 uimm12s2:$offset)))]>;
1574 // load sign-extended byte
1575 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1577 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1578 uimm12s1:$offset)))]>;
1579 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1581 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1582 uimm12s1:$offset)))]>;
1584 // load sign-extended word
1585 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1587 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1588 uimm12s4:$offset)))]>;
1590 // load zero-extended word
1591 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1592 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1595 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1596 [(AArch64Prefetch imm:$Rt,
1597 (am_indexed64 GPR64sp:$Rn,
1598 uimm12s8:$offset))]>;
1600 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1604 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1605 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1606 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1607 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1608 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1610 // load sign-extended word
1611 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1614 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1615 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1618 // (unscaled immediate)
1619 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1621 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1622 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1624 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1625 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1627 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1628 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1630 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1631 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1632 [(set (f32 FPR32:$Rt),
1633 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1634 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1635 [(set (f64 FPR64:$Rt),
1636 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1637 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1638 [(set (f128 FPR128:$Rt),
1639 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1642 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1644 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1646 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1648 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1650 // Match all load 64 bits width whose type is compatible with FPR64
1651 let Predicates = [IsLE] in {
1652 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1653 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1654 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1655 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1656 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1657 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1658 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1659 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1660 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1661 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1663 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1664 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1665 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1666 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1668 // Match all load 128 bits width whose type is compatible with FPR128
1669 let Predicates = [IsLE] in {
1670 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1671 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1672 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1673 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1674 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1675 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1676 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1677 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1678 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1679 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1680 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1681 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1682 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1683 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1687 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1688 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1689 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1690 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1691 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1692 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1693 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1694 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1695 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1696 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1697 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1698 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1699 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1700 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1702 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1703 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1704 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1705 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1706 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1707 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1708 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1709 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1710 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1711 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1712 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1713 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1714 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1715 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1719 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1721 // Define new assembler match classes as we want to only match these when
1722 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1723 // associate a DiagnosticType either, as we want the diagnostic for the
1724 // canonical form (the scaled operand) to take precedence.
1725 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1726 let Name = "SImm9OffsetFB" # Width;
1727 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1728 let RenderMethod = "addImmOperands";
1731 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1732 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1733 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1734 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1735 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1737 def simm9_offset_fb8 : Operand<i64> {
1738 let ParserMatchClass = SImm9OffsetFB8Operand;
1740 def simm9_offset_fb16 : Operand<i64> {
1741 let ParserMatchClass = SImm9OffsetFB16Operand;
1743 def simm9_offset_fb32 : Operand<i64> {
1744 let ParserMatchClass = SImm9OffsetFB32Operand;
1746 def simm9_offset_fb64 : Operand<i64> {
1747 let ParserMatchClass = SImm9OffsetFB64Operand;
1749 def simm9_offset_fb128 : Operand<i64> {
1750 let ParserMatchClass = SImm9OffsetFB128Operand;
1753 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1754 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1755 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1756 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1757 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1758 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1759 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1760 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1761 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1762 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1763 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1764 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1765 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1766 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1769 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1770 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1771 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1772 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1774 // load sign-extended half-word
1776 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1778 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1780 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1782 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1784 // load sign-extended byte
1786 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1788 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1790 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1792 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1794 // load sign-extended word
1796 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1798 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1800 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1801 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1802 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1803 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1804 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1805 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1806 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1807 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1808 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1809 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1810 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1811 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1812 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1813 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1814 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1817 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1818 [(AArch64Prefetch imm:$Rt,
1819 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1822 // (unscaled immediate, unprivileged)
1823 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1824 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1826 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1827 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1829 // load sign-extended half-word
1830 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1831 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1833 // load sign-extended byte
1834 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1835 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1837 // load sign-extended word
1838 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1841 // (immediate pre-indexed)
1842 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1843 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1844 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1845 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1846 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1847 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1848 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1850 // load sign-extended half-word
1851 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1852 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1854 // load sign-extended byte
1855 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1856 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1858 // load zero-extended byte
1859 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1860 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1862 // load sign-extended word
1863 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1866 // (immediate post-indexed)
1867 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1868 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1869 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1870 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1871 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1872 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1873 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1875 // load sign-extended half-word
1876 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1877 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1879 // load sign-extended byte
1880 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1881 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1883 // load zero-extended byte
1884 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1885 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1887 // load sign-extended word
1888 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1890 //===----------------------------------------------------------------------===//
1891 // Store instructions.
1892 //===----------------------------------------------------------------------===//
1894 // Pair (indexed, offset)
1895 // FIXME: Use dedicated range-checked addressing mode operand here.
1896 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1897 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1898 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1899 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1900 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1902 // Pair (pre-indexed)
1903 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1904 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1905 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1906 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1907 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1909 // Pair (pre-indexed)
1910 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1911 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1912 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1913 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1914 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1916 // Pair (no allocate)
1917 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1918 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1919 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1920 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1921 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1924 // (Register offset)
1927 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1928 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1929 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1930 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1934 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1935 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1936 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1937 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1938 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1940 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1941 Instruction STRW, Instruction STRX> {
1943 def : Pat<(storeop GPR64:$Rt,
1944 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1945 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1946 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1948 def : Pat<(storeop GPR64:$Rt,
1949 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1950 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1951 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1954 let AddedComplexity = 10 in {
1956 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1957 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1958 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1961 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1962 Instruction STRW, Instruction STRX> {
1963 def : Pat<(store (VecTy FPR:$Rt),
1964 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1965 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1967 def : Pat<(store (VecTy FPR:$Rt),
1968 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1969 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1972 let AddedComplexity = 10 in {
1973 // Match all store 64 bits width whose type is compatible with FPR64
1974 let Predicates = [IsLE] in {
1975 // We must use ST1 to store vectors in big-endian.
1976 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1977 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1978 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1979 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1980 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1983 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1984 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1986 // Match all store 128 bits width whose type is compatible with FPR128
1987 let Predicates = [IsLE] in {
1988 // We must use ST1 to store vectors in big-endian.
1989 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1990 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1991 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1992 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1993 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1994 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1995 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
1997 } // AddedComplexity = 10
1999 // Match stores from lane 0 to the appropriate subreg's store.
2000 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
2001 ValueType VecTy, ValueType STy,
2002 SubRegIndex SubRegIdx,
2003 Instruction STRW, Instruction STRX> {
2005 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2006 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
2007 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2008 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
2010 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2011 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
2012 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2013 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2016 let AddedComplexity = 19 in {
2017 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2018 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
2019 defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
2020 defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
2021 defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
2022 defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
2023 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
2027 // (unsigned immediate)
2028 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
2030 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2031 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
2033 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2034 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
2036 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
2037 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
2038 [(store (f16 FPR16:$Rt),
2039 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
2040 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
2041 [(store (f32 FPR32:$Rt),
2042 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2043 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
2044 [(store (f64 FPR64:$Rt),
2045 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2046 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
2048 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
2049 [(truncstorei16 GPR32:$Rt,
2050 (am_indexed16 GPR64sp:$Rn,
2051 uimm12s2:$offset))]>;
2052 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
2053 [(truncstorei8 GPR32:$Rt,
2054 (am_indexed8 GPR64sp:$Rn,
2055 uimm12s1:$offset))]>;
2057 // Match all store 64 bits width whose type is compatible with FPR64
2058 let AddedComplexity = 10 in {
2059 let Predicates = [IsLE] in {
2060 // We must use ST1 to store vectors in big-endian.
2061 def : Pat<(store (v2f32 FPR64:$Rt),
2062 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2063 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2064 def : Pat<(store (v8i8 FPR64:$Rt),
2065 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2066 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2067 def : Pat<(store (v4i16 FPR64:$Rt),
2068 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2069 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2070 def : Pat<(store (v2i32 FPR64:$Rt),
2071 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2072 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2073 def : Pat<(store (v4f16 FPR64:$Rt),
2074 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2075 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2077 def : Pat<(store (v1f64 FPR64:$Rt),
2078 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2079 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2080 def : Pat<(store (v1i64 FPR64:$Rt),
2081 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2082 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2084 // Match all store 128 bits width whose type is compatible with FPR128
2085 let Predicates = [IsLE] in {
2086 // We must use ST1 to store vectors in big-endian.
2087 def : Pat<(store (v4f32 FPR128:$Rt),
2088 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2089 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2090 def : Pat<(store (v2f64 FPR128:$Rt),
2091 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2092 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2093 def : Pat<(store (v16i8 FPR128:$Rt),
2094 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2095 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2096 def : Pat<(store (v8i16 FPR128:$Rt),
2097 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2098 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2099 def : Pat<(store (v4i32 FPR128:$Rt),
2100 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2101 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2102 def : Pat<(store (v2i64 FPR128:$Rt),
2103 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2104 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2105 def : Pat<(store (v8f16 FPR128:$Rt),
2106 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2107 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2109 def : Pat<(store (f128 FPR128:$Rt),
2110 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2111 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2114 def : Pat<(truncstorei32 GPR64:$Rt,
2115 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
2116 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2117 def : Pat<(truncstorei16 GPR64:$Rt,
2118 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2119 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
2120 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
2121 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
2123 } // AddedComplexity = 10
2126 // (unscaled immediate)
2127 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2129 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2130 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2132 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2133 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2135 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2136 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2137 [(store (f16 FPR16:$Rt),
2138 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2139 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2140 [(store (f32 FPR32:$Rt),
2141 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2142 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2143 [(store (f64 FPR64:$Rt),
2144 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2145 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2146 [(store (f128 FPR128:$Rt),
2147 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2148 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2149 [(truncstorei16 GPR32:$Rt,
2150 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2151 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2152 [(truncstorei8 GPR32:$Rt,
2153 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2155 // Match all store 64 bits width whose type is compatible with FPR64
2156 let Predicates = [IsLE] in {
2157 // We must use ST1 to store vectors in big-endian.
2158 def : Pat<(store (v2f32 FPR64:$Rt),
2159 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2160 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2161 def : Pat<(store (v8i8 FPR64:$Rt),
2162 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2163 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2164 def : Pat<(store (v4i16 FPR64:$Rt),
2165 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2166 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2167 def : Pat<(store (v2i32 FPR64:$Rt),
2168 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2169 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2170 def : Pat<(store (v4f16 FPR64:$Rt),
2171 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2172 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2174 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2175 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2176 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2177 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2179 // Match all store 128 bits width whose type is compatible with FPR128
2180 let Predicates = [IsLE] in {
2181 // We must use ST1 to store vectors in big-endian.
2182 def : Pat<(store (v4f32 FPR128:$Rt),
2183 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2184 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2185 def : Pat<(store (v2f64 FPR128:$Rt),
2186 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2187 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2188 def : Pat<(store (v16i8 FPR128:$Rt),
2189 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2190 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2191 def : Pat<(store (v8i16 FPR128:$Rt),
2192 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2193 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2194 def : Pat<(store (v4i32 FPR128:$Rt),
2195 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2196 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2197 def : Pat<(store (v2i64 FPR128:$Rt),
2198 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2199 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2200 def : Pat<(store (v2f64 FPR128:$Rt),
2201 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2202 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2203 def : Pat<(store (v8f16 FPR128:$Rt),
2204 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2205 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2208 // unscaled i64 truncating stores
2209 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2210 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2211 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2212 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2213 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2214 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2217 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2218 def : InstAlias<"str $Rt, [$Rn, $offset]",
2219 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2220 def : InstAlias<"str $Rt, [$Rn, $offset]",
2221 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2222 def : InstAlias<"str $Rt, [$Rn, $offset]",
2223 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2224 def : InstAlias<"str $Rt, [$Rn, $offset]",
2225 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2226 def : InstAlias<"str $Rt, [$Rn, $offset]",
2227 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2228 def : InstAlias<"str $Rt, [$Rn, $offset]",
2229 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2230 def : InstAlias<"str $Rt, [$Rn, $offset]",
2231 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2233 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2234 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2235 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2236 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2239 // (unscaled immediate, unprivileged)
2240 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2241 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2243 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2244 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2247 // (immediate pre-indexed)
2248 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2249 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2250 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2251 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2252 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2253 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2254 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2256 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2257 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2260 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2261 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2263 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2264 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2266 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2267 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2270 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2271 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2272 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2273 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2274 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2275 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2276 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2277 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2278 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2279 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2280 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2281 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2282 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2283 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2285 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2286 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2287 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2288 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2289 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2290 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2291 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2292 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2293 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2294 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2295 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2296 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2297 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2298 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2301 // (immediate post-indexed)
2302 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2303 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2304 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2305 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2306 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2307 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2308 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2310 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2311 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2314 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2315 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2317 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2318 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2320 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2321 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2324 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2325 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2326 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2327 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2328 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2329 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2330 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2331 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2332 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2333 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2334 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2335 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2336 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2337 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2339 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2340 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2341 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2342 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2343 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2344 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2345 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2346 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2347 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2348 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2349 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2350 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2351 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2352 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2354 //===----------------------------------------------------------------------===//
2355 // Load/store exclusive instructions.
2356 //===----------------------------------------------------------------------===//
2358 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2359 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2360 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2361 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2363 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2364 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2365 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2366 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2368 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2369 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2370 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2371 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2373 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2374 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2375 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2376 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2378 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2379 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2380 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2381 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2383 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2384 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2385 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2386 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2388 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2389 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2391 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2392 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2394 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2395 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2397 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2398 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2400 let Predicates = [HasV8_1a] in {
2401 // v8.1a "Limited Order Region" extension load-acquire instructions
2402 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2403 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
2404 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2405 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
2407 // v8.1a "Limited Order Region" extension store-release instructions
2408 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
2409 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
2410 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2411 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
2414 //===----------------------------------------------------------------------===//
2415 // Scaled floating point to integer conversion instructions.
2416 //===----------------------------------------------------------------------===//
2418 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2419 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2420 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2421 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2422 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2423 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2424 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2425 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2426 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2427 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2428 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2429 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2430 let isCodeGenOnly = 1 in {
2431 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2432 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2433 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2434 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2437 //===----------------------------------------------------------------------===//
2438 // Scaled integer to floating point conversion instructions.
2439 //===----------------------------------------------------------------------===//
2441 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2442 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2444 //===----------------------------------------------------------------------===//
2445 // Unscaled integer to floating point conversion instruction.
2446 //===----------------------------------------------------------------------===//
2448 defm FMOV : UnscaledConversion<"fmov">;
2450 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
2451 let isReMaterializable = 1, isCodeGenOnly = 1 in {
2452 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
2453 PseudoInstExpansion<(FMOVWSr FPR32:$Rd, WZR)>,
2455 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
2456 PseudoInstExpansion<(FMOVXDr FPR64:$Rd, XZR)>,
2460 //===----------------------------------------------------------------------===//
2461 // Floating point conversion instruction.
2462 //===----------------------------------------------------------------------===//
2464 defm FCVT : FPConversion<"fcvt">;
2466 //===----------------------------------------------------------------------===//
2467 // Floating point single operand instructions.
2468 //===----------------------------------------------------------------------===//
2470 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2471 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2472 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2473 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2474 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2475 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2476 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2477 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2479 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2480 (FRINTNDr FPR64:$Rn)>;
2482 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2483 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2484 // <rdar://problem/13715968>
2485 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2486 let hasSideEffects = 1 in {
2487 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2490 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2492 let SchedRW = [WriteFDiv] in {
2493 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2496 //===----------------------------------------------------------------------===//
2497 // Floating point two operand instructions.
2498 //===----------------------------------------------------------------------===//
2500 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2501 let SchedRW = [WriteFDiv] in {
2502 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2504 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2505 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2506 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2507 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2508 let SchedRW = [WriteFMul] in {
2509 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2510 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2512 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2514 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2515 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2516 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2517 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2518 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2519 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2520 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2521 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2523 //===----------------------------------------------------------------------===//
2524 // Floating point three operand instructions.
2525 //===----------------------------------------------------------------------===//
2527 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2528 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2529 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2530 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2531 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2532 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2533 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2535 // The following def pats catch the case where the LHS of an FMA is negated.
2536 // The TriOpFrag above catches the case where the middle operand is negated.
2538 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2539 // the NEON variant.
2540 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2541 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2543 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2544 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2546 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2548 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2549 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2551 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2552 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2554 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2555 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2557 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2558 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2560 //===----------------------------------------------------------------------===//
2561 // Floating point comparison instructions.
2562 //===----------------------------------------------------------------------===//
2564 defm FCMPE : FPComparison<1, "fcmpe">;
2565 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2567 //===----------------------------------------------------------------------===//
2568 // Floating point conditional comparison instructions.
2569 //===----------------------------------------------------------------------===//
2571 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2572 defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>;
2574 //===----------------------------------------------------------------------===//
2575 // Floating point conditional select instruction.
2576 //===----------------------------------------------------------------------===//
2578 defm FCSEL : FPCondSelect<"fcsel">;
2580 // CSEL instructions providing f128 types need to be handled by a
2581 // pseudo-instruction since the eventual code will need to introduce basic
2582 // blocks and control flow.
2583 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2584 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2585 [(set (f128 FPR128:$Rd),
2586 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2587 (i32 imm:$cond), NZCV))]> {
2589 let usesCustomInserter = 1;
2593 //===----------------------------------------------------------------------===//
2594 // Floating point immediate move.
2595 //===----------------------------------------------------------------------===//
2597 let isReMaterializable = 1 in {
2598 defm FMOV : FPMoveImmediate<"fmov">;
2601 //===----------------------------------------------------------------------===//
2602 // Advanced SIMD two vector instructions.
2603 //===----------------------------------------------------------------------===//
2605 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2606 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2607 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2608 (ABSv8i8 V64:$src)>;
2609 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2610 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2611 (ABSv4i16 V64:$src)>;
2612 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2613 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2614 (ABSv2i32 V64:$src)>;
2615 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2616 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2617 (ABSv16i8 V128:$src)>;
2618 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2619 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2620 (ABSv8i16 V128:$src)>;
2621 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2622 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2623 (ABSv4i32 V128:$src)>;
2624 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2625 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2626 (ABSv2i64 V128:$src)>;
2628 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2629 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2630 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2631 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2632 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2633 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2634 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2635 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2636 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2638 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2639 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2640 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2641 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2642 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2643 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2644 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2645 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2646 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2647 (FCVTLv4i16 V64:$Rn)>;
2648 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2650 (FCVTLv8i16 V128:$Rn)>;
2651 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2652 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2654 (FCVTLv4i32 V128:$Rn)>;
2656 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2657 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2659 (FCVTLv8i16 V128:$Rn)>;
2661 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2662 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2663 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2664 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2665 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2666 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2667 (FCVTNv4i16 V128:$Rn)>;
2668 def : Pat<(concat_vectors V64:$Rd,
2669 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2670 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2671 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2672 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2673 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2674 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2675 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2676 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2677 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2678 int_aarch64_neon_fcvtxn>;
2679 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2680 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2681 let isCodeGenOnly = 1 in {
2682 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2683 int_aarch64_neon_fcvtzs>;
2684 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2685 int_aarch64_neon_fcvtzu>;
2687 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2688 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2689 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2690 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2691 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2692 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2693 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2694 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2695 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2696 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2697 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2698 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2699 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2700 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2701 // Aliases for MVN -> NOT.
2702 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2703 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2704 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2705 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2707 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2708 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2709 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2710 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2711 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2712 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2713 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2715 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2716 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2717 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2718 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2719 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2720 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2721 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2722 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2724 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2725 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2726 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2727 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2728 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2730 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2731 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2732 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2733 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2734 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2735 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2736 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2737 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2738 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2739 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2740 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2741 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2742 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2743 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2744 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2745 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2746 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2747 int_aarch64_neon_uaddlp>;
2748 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2749 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2750 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2751 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2752 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2753 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2755 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2756 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2757 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2758 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2759 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2760 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2762 // Patterns for vector long shift (by element width). These need to match all
2763 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2765 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2766 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2767 (SHLLv8i8 V64:$Rn)>;
2768 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2769 (SHLLv16i8 V128:$Rn)>;
2770 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2771 (SHLLv4i16 V64:$Rn)>;
2772 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2773 (SHLLv8i16 V128:$Rn)>;
2774 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2775 (SHLLv2i32 V64:$Rn)>;
2776 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2777 (SHLLv4i32 V128:$Rn)>;
2780 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2781 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2782 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2784 //===----------------------------------------------------------------------===//
2785 // Advanced SIMD three vector instructions.
2786 //===----------------------------------------------------------------------===//
2788 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2789 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2790 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2791 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2792 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2793 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2794 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2795 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2796 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2797 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2798 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2799 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2800 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2801 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2802 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2803 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2804 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2805 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2806 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2807 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2808 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2809 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2810 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2811 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2812 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2814 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2815 // instruction expects the addend first, while the fma intrinsic puts it last.
2816 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2817 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2818 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2819 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2821 // The following def pats catch the case where the LHS of an FMA is negated.
2822 // The TriOpFrag above catches the case where the middle operand is negated.
2823 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2824 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2826 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2827 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2829 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2830 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2832 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2833 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2834 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2835 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2836 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2837 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2838 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2839 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2840 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2841 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2842 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2843 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2844 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2845 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2846 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2847 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2848 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2849 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2850 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2851 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2852 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2853 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2854 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2855 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2856 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2857 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2858 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2859 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2860 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2861 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2862 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2863 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2864 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2865 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2866 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2867 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2868 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2869 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2870 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2871 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2872 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2873 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2874 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2875 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2876 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2877 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2878 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
2879 int_aarch64_neon_sqadd>;
2880 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
2881 int_aarch64_neon_sqsub>;
2883 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2884 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2885 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2886 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2887 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2888 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2889 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2890 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2891 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2892 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2893 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2895 def : Pat<(v8i8 (smin V64:$Rn, V64:$Rm)),
2896 (SMINv8i8 V64:$Rn, V64:$Rm)>;
2897 def : Pat<(v4i16 (smin V64:$Rn, V64:$Rm)),
2898 (SMINv4i16 V64:$Rn, V64:$Rm)>;
2899 def : Pat<(v2i32 (smin V64:$Rn, V64:$Rm)),
2900 (SMINv2i32 V64:$Rn, V64:$Rm)>;
2901 def : Pat<(v16i8 (smin V128:$Rn, V128:$Rm)),
2902 (SMINv16i8 V128:$Rn, V128:$Rm)>;
2903 def : Pat<(v8i16 (smin V128:$Rn, V128:$Rm)),
2904 (SMINv8i16 V128:$Rn, V128:$Rm)>;
2905 def : Pat<(v4i32 (smin V128:$Rn, V128:$Rm)),
2906 (SMINv4i32 V128:$Rn, V128:$Rm)>;
2907 def : Pat<(v8i8 (smax V64:$Rn, V64:$Rm)),
2908 (SMAXv8i8 V64:$Rn, V64:$Rm)>;
2909 def : Pat<(v4i16 (smax V64:$Rn, V64:$Rm)),
2910 (SMAXv4i16 V64:$Rn, V64:$Rm)>;
2911 def : Pat<(v2i32 (smax V64:$Rn, V64:$Rm)),
2912 (SMAXv2i32 V64:$Rn, V64:$Rm)>;
2913 def : Pat<(v16i8 (smax V128:$Rn, V128:$Rm)),
2914 (SMAXv16i8 V128:$Rn, V128:$Rm)>;
2915 def : Pat<(v8i16 (smax V128:$Rn, V128:$Rm)),
2916 (SMAXv8i16 V128:$Rn, V128:$Rm)>;
2917 def : Pat<(v4i32 (smax V128:$Rn, V128:$Rm)),
2918 (SMAXv4i32 V128:$Rn, V128:$Rm)>;
2919 def : Pat<(v8i8 (umin V64:$Rn, V64:$Rm)),
2920 (UMINv8i8 V64:$Rn, V64:$Rm)>;
2921 def : Pat<(v4i16 (umin V64:$Rn, V64:$Rm)),
2922 (UMINv4i16 V64:$Rn, V64:$Rm)>;
2923 def : Pat<(v2i32 (umin V64:$Rn, V64:$Rm)),
2924 (UMINv2i32 V64:$Rn, V64:$Rm)>;
2925 def : Pat<(v16i8 (umin V128:$Rn, V128:$Rm)),
2926 (UMINv16i8 V128:$Rn, V128:$Rm)>;
2927 def : Pat<(v8i16 (umin V128:$Rn, V128:$Rm)),
2928 (UMINv8i16 V128:$Rn, V128:$Rm)>;
2929 def : Pat<(v4i32 (umin V128:$Rn, V128:$Rm)),
2930 (UMINv4i32 V128:$Rn, V128:$Rm)>;
2931 def : Pat<(v8i8 (umax V64:$Rn, V64:$Rm)),
2932 (UMAXv8i8 V64:$Rn, V64:$Rm)>;
2933 def : Pat<(v4i16 (umax V64:$Rn, V64:$Rm)),
2934 (UMAXv4i16 V64:$Rn, V64:$Rm)>;
2935 def : Pat<(v2i32 (umax V64:$Rn, V64:$Rm)),
2936 (UMAXv2i32 V64:$Rn, V64:$Rm)>;
2937 def : Pat<(v16i8 (umax V128:$Rn, V128:$Rm)),
2938 (UMAXv16i8 V128:$Rn, V128:$Rm)>;
2939 def : Pat<(v8i16 (umax V128:$Rn, V128:$Rm)),
2940 (UMAXv8i16 V128:$Rn, V128:$Rm)>;
2941 def : Pat<(v4i32 (umax V128:$Rn, V128:$Rm)),
2942 (UMAXv4i32 V128:$Rn, V128:$Rm)>;
2944 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2945 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2946 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2947 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2948 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2949 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2950 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2951 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2953 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2954 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2955 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2956 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2957 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2958 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2959 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2960 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2962 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2963 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2964 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2965 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2966 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2967 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2968 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2969 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2971 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2972 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2973 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2974 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2975 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2976 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2977 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2978 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2980 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2981 "|cmls.8b\t$dst, $src1, $src2}",
2982 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2983 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2984 "|cmls.16b\t$dst, $src1, $src2}",
2985 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2986 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2987 "|cmls.4h\t$dst, $src1, $src2}",
2988 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2989 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2990 "|cmls.8h\t$dst, $src1, $src2}",
2991 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2992 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2993 "|cmls.2s\t$dst, $src1, $src2}",
2994 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2995 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2996 "|cmls.4s\t$dst, $src1, $src2}",
2997 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2998 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2999 "|cmls.2d\t$dst, $src1, $src2}",
3000 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3002 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
3003 "|cmlo.8b\t$dst, $src1, $src2}",
3004 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3005 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
3006 "|cmlo.16b\t$dst, $src1, $src2}",
3007 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3008 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
3009 "|cmlo.4h\t$dst, $src1, $src2}",
3010 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3011 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
3012 "|cmlo.8h\t$dst, $src1, $src2}",
3013 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3014 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
3015 "|cmlo.2s\t$dst, $src1, $src2}",
3016 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3017 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
3018 "|cmlo.4s\t$dst, $src1, $src2}",
3019 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3020 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
3021 "|cmlo.2d\t$dst, $src1, $src2}",
3022 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3024 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
3025 "|cmle.8b\t$dst, $src1, $src2}",
3026 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3027 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
3028 "|cmle.16b\t$dst, $src1, $src2}",
3029 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3030 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
3031 "|cmle.4h\t$dst, $src1, $src2}",
3032 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3033 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
3034 "|cmle.8h\t$dst, $src1, $src2}",
3035 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3036 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
3037 "|cmle.2s\t$dst, $src1, $src2}",
3038 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3039 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
3040 "|cmle.4s\t$dst, $src1, $src2}",
3041 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3042 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
3043 "|cmle.2d\t$dst, $src1, $src2}",
3044 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3046 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
3047 "|cmlt.8b\t$dst, $src1, $src2}",
3048 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3049 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
3050 "|cmlt.16b\t$dst, $src1, $src2}",
3051 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3052 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
3053 "|cmlt.4h\t$dst, $src1, $src2}",
3054 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3055 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
3056 "|cmlt.8h\t$dst, $src1, $src2}",
3057 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3058 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
3059 "|cmlt.2s\t$dst, $src1, $src2}",
3060 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3061 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
3062 "|cmlt.4s\t$dst, $src1, $src2}",
3063 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3064 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
3065 "|cmlt.2d\t$dst, $src1, $src2}",
3066 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3068 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
3069 "|fcmle.2s\t$dst, $src1, $src2}",
3070 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3071 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
3072 "|fcmle.4s\t$dst, $src1, $src2}",
3073 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3074 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
3075 "|fcmle.2d\t$dst, $src1, $src2}",
3076 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3078 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
3079 "|fcmlt.2s\t$dst, $src1, $src2}",
3080 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3081 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
3082 "|fcmlt.4s\t$dst, $src1, $src2}",
3083 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3084 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
3085 "|fcmlt.2d\t$dst, $src1, $src2}",
3086 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3088 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
3089 "|facle.2s\t$dst, $src1, $src2}",
3090 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3091 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
3092 "|facle.4s\t$dst, $src1, $src2}",
3093 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3094 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
3095 "|facle.2d\t$dst, $src1, $src2}",
3096 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3098 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
3099 "|faclt.2s\t$dst, $src1, $src2}",
3100 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3101 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
3102 "|faclt.4s\t$dst, $src1, $src2}",
3103 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3104 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
3105 "|faclt.2d\t$dst, $src1, $src2}",
3106 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3108 //===----------------------------------------------------------------------===//
3109 // Advanced SIMD three scalar instructions.
3110 //===----------------------------------------------------------------------===//
3112 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
3113 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
3114 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
3115 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
3116 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
3117 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
3118 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
3119 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
3120 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3121 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
3122 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
3123 int_aarch64_neon_facge>;
3124 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
3125 int_aarch64_neon_facgt>;
3126 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
3127 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
3128 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
3129 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
3130 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
3131 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
3132 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
3133 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
3134 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
3135 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
3136 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
3137 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
3138 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
3139 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
3140 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
3141 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
3142 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
3143 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
3144 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
3145 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
3146 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
3147 let Predicates = [HasV8_1a] in {
3148 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
3149 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
3150 def : Pat<(i32 (int_aarch64_neon_sqadd
3152 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3153 (i32 FPR32:$Rm))))),
3154 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3155 def : Pat<(i32 (int_aarch64_neon_sqsub
3157 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3158 (i32 FPR32:$Rm))))),
3159 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3162 def : InstAlias<"cmls $dst, $src1, $src2",
3163 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3164 def : InstAlias<"cmle $dst, $src1, $src2",
3165 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3166 def : InstAlias<"cmlo $dst, $src1, $src2",
3167 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3168 def : InstAlias<"cmlt $dst, $src1, $src2",
3169 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3170 def : InstAlias<"fcmle $dst, $src1, $src2",
3171 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3172 def : InstAlias<"fcmle $dst, $src1, $src2",
3173 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3174 def : InstAlias<"fcmlt $dst, $src1, $src2",
3175 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3176 def : InstAlias<"fcmlt $dst, $src1, $src2",
3177 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3178 def : InstAlias<"facle $dst, $src1, $src2",
3179 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3180 def : InstAlias<"facle $dst, $src1, $src2",
3181 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3182 def : InstAlias<"faclt $dst, $src1, $src2",
3183 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3184 def : InstAlias<"faclt $dst, $src1, $src2",
3185 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3187 //===----------------------------------------------------------------------===//
3188 // Advanced SIMD three scalar instructions (mixed operands).
3189 //===----------------------------------------------------------------------===//
3190 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3191 int_aarch64_neon_sqdmulls_scalar>;
3192 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
3193 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3195 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3196 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3197 (i32 FPR32:$Rm))))),
3198 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3199 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3200 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3201 (i32 FPR32:$Rm))))),
3202 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3204 //===----------------------------------------------------------------------===//
3205 // Advanced SIMD two scalar instructions.
3206 //===----------------------------------------------------------------------===//
3208 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
3209 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3210 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3211 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3212 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3213 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3214 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3215 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3216 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3217 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3218 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3219 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
3220 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
3221 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
3222 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
3223 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
3224 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
3225 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
3226 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
3227 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3228 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
3229 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
3230 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
3231 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
3232 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
3233 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3234 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3235 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3236 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3237 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3238 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3239 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3240 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3241 int_aarch64_neon_suqadd>;
3242 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3243 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3244 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3245 int_aarch64_neon_usqadd>;
3247 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3249 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3250 (FCVTASv1i64 FPR64:$Rn)>;
3251 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3252 (FCVTAUv1i64 FPR64:$Rn)>;
3253 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3254 (FCVTMSv1i64 FPR64:$Rn)>;
3255 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3256 (FCVTMUv1i64 FPR64:$Rn)>;
3257 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3258 (FCVTNSv1i64 FPR64:$Rn)>;
3259 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3260 (FCVTNUv1i64 FPR64:$Rn)>;
3261 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3262 (FCVTPSv1i64 FPR64:$Rn)>;
3263 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3264 (FCVTPUv1i64 FPR64:$Rn)>;
3266 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3267 (FRECPEv1i32 FPR32:$Rn)>;
3268 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3269 (FRECPEv1i64 FPR64:$Rn)>;
3270 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3271 (FRECPEv1i64 FPR64:$Rn)>;
3273 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3274 (FRECPXv1i32 FPR32:$Rn)>;
3275 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3276 (FRECPXv1i64 FPR64:$Rn)>;
3278 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3279 (FRSQRTEv1i32 FPR32:$Rn)>;
3280 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3281 (FRSQRTEv1i64 FPR64:$Rn)>;
3282 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3283 (FRSQRTEv1i64 FPR64:$Rn)>;
3285 // If an integer is about to be converted to a floating point value,
3286 // just load it on the floating point unit.
3287 // Here are the patterns for 8 and 16-bits to float.
3289 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3290 SDPatternOperator loadop, Instruction UCVTF,
3291 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3293 def : Pat<(DstTy (uint_to_fp (SrcTy
3294 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3295 ro.Wext:$extend))))),
3296 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3297 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3300 def : Pat<(DstTy (uint_to_fp (SrcTy
3301 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3302 ro.Wext:$extend))))),
3303 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3304 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3308 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3309 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3310 def : Pat <(f32 (uint_to_fp (i32
3311 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3312 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3313 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3314 def : Pat <(f32 (uint_to_fp (i32
3315 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3316 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3317 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3318 // 16-bits -> float.
3319 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3320 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3321 def : Pat <(f32 (uint_to_fp (i32
3322 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3323 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3324 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3325 def : Pat <(f32 (uint_to_fp (i32
3326 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3327 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3328 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3329 // 32-bits are handled in target specific dag combine:
3330 // performIntToFpCombine.
3331 // 64-bits integer to 32-bits floating point, not possible with
3332 // UCVTF on floating point registers (both source and destination
3333 // must have the same size).
3335 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3336 // 8-bits -> double.
3337 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3338 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3339 def : Pat <(f64 (uint_to_fp (i32
3340 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3341 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3342 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3343 def : Pat <(f64 (uint_to_fp (i32
3344 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3345 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3346 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3347 // 16-bits -> double.
3348 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3349 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3350 def : Pat <(f64 (uint_to_fp (i32
3351 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3352 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3353 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3354 def : Pat <(f64 (uint_to_fp (i32
3355 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3356 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3357 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3358 // 32-bits -> double.
3359 defm : UIntToFPROLoadPat<f64, i32, load,
3360 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3361 def : Pat <(f64 (uint_to_fp (i32
3362 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3363 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3364 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3365 def : Pat <(f64 (uint_to_fp (i32
3366 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3367 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3368 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3369 // 64-bits -> double are handled in target specific dag combine:
3370 // performIntToFpCombine.
3372 //===----------------------------------------------------------------------===//
3373 // Advanced SIMD three different-sized vector instructions.
3374 //===----------------------------------------------------------------------===//
3376 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3377 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3378 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3379 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3380 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3381 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3382 int_aarch64_neon_sabd>;
3383 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3384 int_aarch64_neon_sabd>;
3385 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3386 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3387 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3388 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3389 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3390 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3391 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3392 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3393 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3394 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3395 int_aarch64_neon_sqadd>;
3396 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3397 int_aarch64_neon_sqsub>;
3398 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3399 int_aarch64_neon_sqdmull>;
3400 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3401 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3402 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3403 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3404 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3405 int_aarch64_neon_uabd>;
3406 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3407 int_aarch64_neon_uabd>;
3408 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3409 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3410 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3411 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3412 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3413 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3414 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3415 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3416 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3417 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3418 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3419 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3420 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3422 // Additional patterns for SMULL and UMULL
3423 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3424 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3425 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3426 (INST8B V64:$Rn, V64:$Rm)>;
3427 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3428 (INST4H V64:$Rn, V64:$Rm)>;
3429 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3430 (INST2S V64:$Rn, V64:$Rm)>;
3433 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3434 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3435 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3436 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3438 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3439 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3440 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3441 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3442 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3443 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3444 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3445 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3446 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3449 defm : Neon_mulacc_widen_patterns<
3450 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3451 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3452 defm : Neon_mulacc_widen_patterns<
3453 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3454 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3455 defm : Neon_mulacc_widen_patterns<
3456 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3457 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3458 defm : Neon_mulacc_widen_patterns<
3459 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3460 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3462 // Patterns for 64-bit pmull
3463 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3464 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3465 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3466 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3467 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3469 // CodeGen patterns for addhn and subhn instructions, which can actually be
3470 // written in LLVM IR without too much difficulty.
3473 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3474 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3475 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3477 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3478 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3480 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3481 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3482 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3484 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3485 V128:$Rn, V128:$Rm)>;
3486 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3487 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3489 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3490 V128:$Rn, V128:$Rm)>;
3491 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3492 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3494 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3495 V128:$Rn, V128:$Rm)>;
3498 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3499 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3500 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3502 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3503 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3505 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3506 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3507 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3509 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3510 V128:$Rn, V128:$Rm)>;
3511 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3512 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3514 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3515 V128:$Rn, V128:$Rm)>;
3516 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3517 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3519 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3520 V128:$Rn, V128:$Rm)>;
3522 //----------------------------------------------------------------------------
3523 // AdvSIMD bitwise extract from vector instruction.
3524 //----------------------------------------------------------------------------
3526 defm EXT : SIMDBitwiseExtract<"ext">;
3528 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3529 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3530 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3531 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3532 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3533 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3534 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3535 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3536 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3537 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3538 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3539 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3540 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3541 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3542 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3543 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3544 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3545 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3546 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3547 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3549 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3551 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3552 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3553 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3554 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3555 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3556 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3557 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3558 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3559 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3560 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3561 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3562 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3563 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3564 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3567 //----------------------------------------------------------------------------
3568 // AdvSIMD zip vector
3569 //----------------------------------------------------------------------------
3571 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3572 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3573 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3574 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3575 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3576 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3578 //----------------------------------------------------------------------------
3579 // AdvSIMD TBL/TBX instructions
3580 //----------------------------------------------------------------------------
3582 defm TBL : SIMDTableLookup< 0, "tbl">;
3583 defm TBX : SIMDTableLookupTied<1, "tbx">;
3585 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3586 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3587 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3588 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3590 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3591 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3592 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3593 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3594 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3595 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3598 //----------------------------------------------------------------------------
3599 // AdvSIMD scalar CPY instruction
3600 //----------------------------------------------------------------------------
3602 defm CPY : SIMDScalarCPY<"cpy">;
3604 //----------------------------------------------------------------------------
3605 // AdvSIMD scalar pairwise instructions
3606 //----------------------------------------------------------------------------
3608 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3609 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3610 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3611 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3612 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3613 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3614 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
3615 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3616 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),
3617 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3618 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3619 (FADDPv2i32p V64:$Rn)>;
3620 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3621 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3622 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3623 (FADDPv2i64p V128:$Rn)>;
3624 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3625 (FMAXNMPv2i32p V64:$Rn)>;
3626 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3627 (FMAXNMPv2i64p V128:$Rn)>;
3628 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3629 (FMAXPv2i32p V64:$Rn)>;
3630 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3631 (FMAXPv2i64p V128:$Rn)>;
3632 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3633 (FMINNMPv2i32p V64:$Rn)>;
3634 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3635 (FMINNMPv2i64p V128:$Rn)>;
3636 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3637 (FMINPv2i32p V64:$Rn)>;
3638 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3639 (FMINPv2i64p V128:$Rn)>;
3641 //----------------------------------------------------------------------------
3642 // AdvSIMD INS/DUP instructions
3643 //----------------------------------------------------------------------------
3645 def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>;
3646 def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>;
3647 def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>;
3648 def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>;
3649 def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>;
3650 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;
3651 def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>;
3653 def DUPv2i64lane : SIMDDup64FromElement;
3654 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3655 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3656 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3657 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3658 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3659 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3661 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3662 (v2f32 (DUPv2i32lane
3663 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3665 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3666 (v4f32 (DUPv4i32lane
3667 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3669 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3670 (v2f64 (DUPv2i64lane
3671 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3673 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3674 (v4f16 (DUPv4i16lane
3675 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3677 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3678 (v8f16 (DUPv8i16lane
3679 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3682 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3683 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3684 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3685 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3687 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3688 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3689 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3690 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3691 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3692 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3694 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3695 // instruction even if the types don't match: we just have to remap the lane
3696 // carefully. N.b. this trick only applies to truncations.
3697 def VecIndex_x2 : SDNodeXForm<imm, [{
3698 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64);
3700 def VecIndex_x4 : SDNodeXForm<imm, [{
3701 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64);
3703 def VecIndex_x8 : SDNodeXForm<imm, [{
3704 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64);
3707 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3708 ValueType Src128VT, ValueType ScalVT,
3709 Instruction DUP, SDNodeXForm IdxXFORM> {
3710 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3712 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3714 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3716 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3719 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3720 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3721 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3723 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3724 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3725 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3727 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3728 SDNodeXForm IdxXFORM> {
3729 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3731 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3733 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3735 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3738 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3739 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3740 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3742 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3743 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3744 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3746 // SMOV and UMOV definitions, with some extra patterns for convenience
3750 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3751 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3752 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3753 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3754 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3755 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3756 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3757 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3758 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3759 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3760 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3761 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3763 // Extracting i8 or i16 elements will have the zero-extend transformed to
3764 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3765 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3766 // bits of the destination register.
3767 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3769 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3770 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3772 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3776 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3777 (SUBREG_TO_REG (i32 0),
3778 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3779 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3780 (SUBREG_TO_REG (i32 0),
3781 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3783 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3784 (SUBREG_TO_REG (i32 0),
3785 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3786 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3787 (SUBREG_TO_REG (i32 0),
3788 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3790 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3791 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3792 (i32 FPR32:$Rn), ssub))>;
3793 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3794 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3795 (i32 FPR32:$Rn), ssub))>;
3796 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3797 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3798 (i64 FPR64:$Rn), dsub))>;
3800 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3801 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3802 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3803 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3804 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3805 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3807 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3808 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3811 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3813 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3817 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3818 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3820 V128:$Rn, VectorIndexH:$imm,
3821 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3824 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3825 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3828 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3830 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3833 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3834 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3836 V128:$Rn, VectorIndexS:$imm,
3837 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3839 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3840 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3842 V128:$Rn, VectorIndexD:$imm,
3843 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3846 // Copy an element at a constant index in one vector into a constant indexed
3847 // element of another.
3848 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3849 // index type and INS extension
3850 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3851 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3852 VectorIndexB:$idx2)),
3854 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3856 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3857 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3858 VectorIndexH:$idx2)),
3860 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3862 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3863 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3864 VectorIndexS:$idx2)),
3866 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3868 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3869 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3870 VectorIndexD:$idx2)),
3872 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3875 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3876 ValueType VTScal, Instruction INS> {
3877 def : Pat<(VT128 (vector_insert V128:$src,
3878 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3880 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3882 def : Pat<(VT128 (vector_insert V128:$src,
3883 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3885 (INS V128:$src, imm:$Immd,
3886 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3888 def : Pat<(VT64 (vector_insert V64:$src,
3889 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3891 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3892 imm:$Immd, V128:$Rn, imm:$Immn),
3895 def : Pat<(VT64 (vector_insert V64:$src,
3896 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3899 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3900 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3904 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3905 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3906 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3909 // Floating point vector extractions are codegen'd as either a sequence of
3910 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
3911 // the lane number is anything other than zero.
3912 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3913 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3914 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3915 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3916 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3917 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3919 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3920 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
3921 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3922 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
3923 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3924 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
3926 // All concat_vectors operations are canonicalised to act on i64 vectors for
3927 // AArch64. In the general case we need an instruction, which had just as well be
3929 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3930 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3931 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3932 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3934 def : ConcatPat<v2i64, v1i64>;
3935 def : ConcatPat<v2f64, v1f64>;
3936 def : ConcatPat<v4i32, v2i32>;
3937 def : ConcatPat<v4f32, v2f32>;
3938 def : ConcatPat<v8i16, v4i16>;
3939 def : ConcatPat<v8f16, v4f16>;
3940 def : ConcatPat<v16i8, v8i8>;
3942 // If the high lanes are undef, though, we can just ignore them:
3943 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3944 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3945 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3947 def : ConcatUndefPat<v2i64, v1i64>;
3948 def : ConcatUndefPat<v2f64, v1f64>;
3949 def : ConcatUndefPat<v4i32, v2i32>;
3950 def : ConcatUndefPat<v4f32, v2f32>;
3951 def : ConcatUndefPat<v8i16, v4i16>;
3952 def : ConcatUndefPat<v16i8, v8i8>;
3954 //----------------------------------------------------------------------------
3955 // AdvSIMD across lanes instructions
3956 //----------------------------------------------------------------------------
3958 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3959 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3960 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3961 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3962 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3963 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3964 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3965 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3966 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3967 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3968 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3970 // Patterns for across-vector intrinsics, that have a node equivalent, that
3971 // returns a vector (with only the low lane defined) instead of a scalar.
3972 // In effect, opNode is the same as (scalar_to_vector (IntNode)).
3973 multiclass SIMDAcrossLanesIntrinsic<string baseOpc,
3974 SDPatternOperator opNode> {
3975 // If a lane instruction caught the vector_extract around opNode, we can
3976 // directly match the latter to the instruction.
3977 def : Pat<(v8i8 (opNode V64:$Rn)),
3978 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3979 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;
3980 def : Pat<(v16i8 (opNode V128:$Rn)),
3981 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3982 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;
3983 def : Pat<(v4i16 (opNode V64:$Rn)),
3984 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3985 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;
3986 def : Pat<(v8i16 (opNode V128:$Rn)),
3987 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3988 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;
3989 def : Pat<(v4i32 (opNode V128:$Rn)),
3990 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3991 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;
3994 // If none did, fallback to the explicit patterns, consuming the vector_extract.
3995 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
3996 (i32 0)), (i64 0))),
3997 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3998 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),
4000 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
4001 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4002 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),
4004 def : Pat<(i32 (vector_extract (insert_subvector undef,
4005 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))),
4006 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
4007 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),
4009 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
4010 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4011 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),
4013 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
4014 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4015 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),
4020 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,
4021 SDPatternOperator opNode>
4022 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4023 // If there is a sign extension after this intrinsic, consume it as smov already
4025 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4026 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)),
4028 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4029 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4031 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4032 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),
4034 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4035 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4037 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4038 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)),
4040 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4041 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4043 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4044 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),
4046 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4047 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4051 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
4052 SDPatternOperator opNode>
4053 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4054 // If there is a masking operation keeping only what has been actually
4055 // generated, consume it.
4056 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4057 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)),
4058 (i32 (EXTRACT_SUBREG
4059 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4060 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4062 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
4064 (i32 (EXTRACT_SUBREG
4065 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4066 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4068 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4069 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)),
4070 (i32 (EXTRACT_SUBREG
4071 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4072 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4074 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
4076 (i32 (EXTRACT_SUBREG
4077 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4078 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4082 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;
4083 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4084 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
4085 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4087 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;
4088 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4089 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
4090 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4092 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;
4093 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
4094 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
4096 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
4097 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
4098 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
4100 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;
4101 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
4102 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
4104 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
4105 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
4106 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
4108 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
4109 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4111 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4112 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4114 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4116 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4117 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4120 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4121 (i32 (EXTRACT_SUBREG
4122 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4123 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4125 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4126 (i32 (EXTRACT_SUBREG
4127 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4128 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4131 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4132 (i64 (EXTRACT_SUBREG
4133 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4134 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4138 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
4140 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4141 (i32 (EXTRACT_SUBREG
4142 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4143 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4145 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4146 (i32 (EXTRACT_SUBREG
4147 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4148 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4151 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4152 (i32 (EXTRACT_SUBREG
4153 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4154 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4156 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4157 (i32 (EXTRACT_SUBREG
4158 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4159 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4162 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4163 (i64 (EXTRACT_SUBREG
4164 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4165 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4169 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
4170 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
4172 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
4173 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
4174 (i64 (EXTRACT_SUBREG
4175 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4176 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
4178 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4179 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4180 (i64 (EXTRACT_SUBREG
4181 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4182 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4185 //------------------------------------------------------------------------------
4186 // AdvSIMD modified immediate instructions
4187 //------------------------------------------------------------------------------
4190 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4192 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4194 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4195 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4196 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4197 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4199 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4200 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4201 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4202 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4204 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4205 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4206 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4207 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4209 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4210 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4211 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4212 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4215 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
4217 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4218 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
4220 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4221 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
4223 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4227 // EDIT byte mask: scalar
4228 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4229 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4230 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4231 // The movi_edit node has the immediate value already encoded, so we use
4232 // a plain imm0_255 here.
4233 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4234 (MOVID imm0_255:$shift)>;
4236 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4237 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4238 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4239 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4241 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4242 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4243 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4244 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4246 // EDIT byte mask: 2d
4248 // The movi_edit node has the immediate value already encoded, so we use
4249 // a plain imm0_255 in the pattern
4250 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4251 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
4254 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4257 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4258 // Complexity is added to break a tie with a plain MOVI.
4259 let AddedComplexity = 1 in {
4260 def : Pat<(f32 fpimm0),
4261 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4263 def : Pat<(f64 fpimm0),
4264 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4268 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4269 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4270 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4271 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4273 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4274 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4275 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4276 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4278 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4279 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4281 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4282 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4284 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4285 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4286 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4287 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4289 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4290 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4291 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4292 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4294 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4295 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4296 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4297 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4298 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4299 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4300 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4301 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4303 // EDIT per word: 2s & 4s with MSL shifter
4304 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4305 [(set (v2i32 V64:$Rd),
4306 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4307 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4308 [(set (v4i32 V128:$Rd),
4309 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4311 // Per byte: 8b & 16b
4312 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4314 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4315 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4317 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4321 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4322 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4324 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4325 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4326 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4327 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4329 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4330 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4331 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4332 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4334 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4335 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4336 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4337 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4338 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4339 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4340 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4341 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4343 // EDIT per word: 2s & 4s with MSL shifter
4344 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4345 [(set (v2i32 V64:$Rd),
4346 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4347 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4348 [(set (v4i32 V128:$Rd),
4349 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4351 //----------------------------------------------------------------------------
4352 // AdvSIMD indexed element
4353 //----------------------------------------------------------------------------
4355 let hasSideEffects = 0 in {
4356 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
4357 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
4360 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4361 // instruction expects the addend first, while the intrinsic expects it last.
4363 // On the other hand, there are quite a few valid combinatorial options due to
4364 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4365 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4366 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4367 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4368 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4370 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4371 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4372 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4373 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4374 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4375 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4376 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4377 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4379 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4380 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4382 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4383 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4384 VectorIndexS:$idx))),
4385 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4386 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4387 (v2f32 (AArch64duplane32
4388 (v4f32 (insert_subvector undef,
4389 (v2f32 (fneg V64:$Rm)),
4391 VectorIndexS:$idx)))),
4392 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4393 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4394 VectorIndexS:$idx)>;
4395 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4396 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4397 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4398 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4400 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4402 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4403 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4404 VectorIndexS:$idx))),
4405 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4406 VectorIndexS:$idx)>;
4407 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4408 (v4f32 (AArch64duplane32
4409 (v4f32 (insert_subvector undef,
4410 (v2f32 (fneg V64:$Rm)),
4412 VectorIndexS:$idx)))),
4413 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4414 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4415 VectorIndexS:$idx)>;
4416 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4417 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4418 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4419 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4421 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4422 // (DUPLANE from 64-bit would be trivial).
4423 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4424 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4425 VectorIndexD:$idx))),
4427 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4428 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4429 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4430 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4431 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4433 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4434 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4435 (vector_extract (v4f32 (fneg V128:$Rm)),
4436 VectorIndexS:$idx))),
4437 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4438 V128:$Rm, VectorIndexS:$idx)>;
4439 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4440 (vector_extract (v2f32 (fneg V64:$Rm)),
4441 VectorIndexS:$idx))),
4442 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4443 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4445 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4446 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4447 (vector_extract (v2f64 (fneg V128:$Rm)),
4448 VectorIndexS:$idx))),
4449 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4450 V128:$Rm, VectorIndexS:$idx)>;
4453 defm : FMLSIndexedAfterNegPatterns<
4454 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4455 defm : FMLSIndexedAfterNegPatterns<
4456 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4458 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4459 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4461 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4462 (FMULv2i32_indexed V64:$Rn,
4463 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4465 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4466 (FMULv4i32_indexed V128:$Rn,
4467 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4469 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4470 (FMULv2i64_indexed V128:$Rn,
4471 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4474 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4475 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4476 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4477 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4478 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4479 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4480 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4481 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4482 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4483 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4484 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4485 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4486 int_aarch64_neon_smull>;
4487 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4488 int_aarch64_neon_sqadd>;
4489 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4490 int_aarch64_neon_sqsub>;
4491 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
4492 int_aarch64_neon_sqadd>;
4493 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
4494 int_aarch64_neon_sqsub>;
4495 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4496 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4497 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4498 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4499 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4500 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4501 int_aarch64_neon_umull>;
4503 // A scalar sqdmull with the second operand being a vector lane can be
4504 // handled directly with the indexed instruction encoding.
4505 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4506 (vector_extract (v4i32 V128:$Vm),
4507 VectorIndexS:$idx)),
4508 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4510 //----------------------------------------------------------------------------
4511 // AdvSIMD scalar shift instructions
4512 //----------------------------------------------------------------------------
4513 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4514 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4515 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4516 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4517 // Codegen patterns for the above. We don't put these directly on the
4518 // instructions because TableGen's type inference can't handle the truth.
4519 // Having the same base pattern for fp <--> int totally freaks it out.
4520 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4521 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4522 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4523 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4524 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4525 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4526 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4527 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4528 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4530 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4531 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4533 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4534 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4535 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4536 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4537 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4538 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4539 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4540 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4541 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4542 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4544 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4545 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4547 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4549 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4550 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4551 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4552 int_aarch64_neon_sqrshrn>;
4553 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4554 int_aarch64_neon_sqrshrun>;
4555 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4556 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4557 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4558 int_aarch64_neon_sqshrn>;
4559 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4560 int_aarch64_neon_sqshrun>;
4561 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4562 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4563 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4564 TriOpFrag<(add node:$LHS,
4565 (AArch64srshri node:$MHS, node:$RHS))>>;
4566 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4567 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4568 TriOpFrag<(add node:$LHS,
4569 (AArch64vashr node:$MHS, node:$RHS))>>;
4570 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4571 int_aarch64_neon_uqrshrn>;
4572 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4573 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4574 int_aarch64_neon_uqshrn>;
4575 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4576 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4577 TriOpFrag<(add node:$LHS,
4578 (AArch64urshri node:$MHS, node:$RHS))>>;
4579 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4580 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4581 TriOpFrag<(add node:$LHS,
4582 (AArch64vlshr node:$MHS, node:$RHS))>>;
4584 //----------------------------------------------------------------------------
4585 // AdvSIMD vector shift instructions
4586 //----------------------------------------------------------------------------
4587 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4588 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4589 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4590 int_aarch64_neon_vcvtfxs2fp>;
4591 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4592 int_aarch64_neon_rshrn>;
4593 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4594 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4595 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4596 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4597 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4598 (i32 vecshiftL64:$imm))),
4599 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4600 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4601 int_aarch64_neon_sqrshrn>;
4602 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4603 int_aarch64_neon_sqrshrun>;
4604 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4605 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4606 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4607 int_aarch64_neon_sqshrn>;
4608 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4609 int_aarch64_neon_sqshrun>;
4610 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4611 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4612 (i32 vecshiftR64:$imm))),
4613 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4614 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4615 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4616 TriOpFrag<(add node:$LHS,
4617 (AArch64srshri node:$MHS, node:$RHS))> >;
4618 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4619 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4621 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4622 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4623 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4624 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4625 int_aarch64_neon_vcvtfxu2fp>;
4626 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4627 int_aarch64_neon_uqrshrn>;
4628 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4629 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4630 int_aarch64_neon_uqshrn>;
4631 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4632 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4633 TriOpFrag<(add node:$LHS,
4634 (AArch64urshri node:$MHS, node:$RHS))> >;
4635 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4636 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4637 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4638 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4639 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4641 // SHRN patterns for when a logical right shift was used instead of arithmetic
4642 // (the immediate guarantees no sign bits actually end up in the result so it
4644 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4645 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4646 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4647 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4648 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4649 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4651 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4652 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4653 vecshiftR16Narrow:$imm)))),
4654 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4655 V128:$Rn, vecshiftR16Narrow:$imm)>;
4656 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4657 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4658 vecshiftR32Narrow:$imm)))),
4659 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4660 V128:$Rn, vecshiftR32Narrow:$imm)>;
4661 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4662 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4663 vecshiftR64Narrow:$imm)))),
4664 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4665 V128:$Rn, vecshiftR32Narrow:$imm)>;
4667 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4668 // Anyexts are implemented as zexts.
4669 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4670 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4671 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4672 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4673 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4674 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4675 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4676 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4677 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4678 // Also match an extend from the upper half of a 128 bit source register.
4679 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4680 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4681 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4682 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4683 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4684 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4685 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4686 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4687 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4688 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4689 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4690 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4691 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4692 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4693 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4694 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4695 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4696 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4698 // Vector shift sxtl aliases
4699 def : InstAlias<"sxtl.8h $dst, $src1",
4700 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4701 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4702 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4703 def : InstAlias<"sxtl.4s $dst, $src1",
4704 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4705 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4706 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4707 def : InstAlias<"sxtl.2d $dst, $src1",
4708 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4709 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4710 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4712 // Vector shift sxtl2 aliases
4713 def : InstAlias<"sxtl2.8h $dst, $src1",
4714 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4715 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4716 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4717 def : InstAlias<"sxtl2.4s $dst, $src1",
4718 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4719 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4720 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4721 def : InstAlias<"sxtl2.2d $dst, $src1",
4722 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4723 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4724 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4726 // Vector shift uxtl aliases
4727 def : InstAlias<"uxtl.8h $dst, $src1",
4728 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4729 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4730 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4731 def : InstAlias<"uxtl.4s $dst, $src1",
4732 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4733 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4734 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4735 def : InstAlias<"uxtl.2d $dst, $src1",
4736 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4737 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4738 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4740 // Vector shift uxtl2 aliases
4741 def : InstAlias<"uxtl2.8h $dst, $src1",
4742 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4743 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4744 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4745 def : InstAlias<"uxtl2.4s $dst, $src1",
4746 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4747 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4748 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4749 def : InstAlias<"uxtl2.2d $dst, $src1",
4750 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4751 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4752 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4754 // If an integer is about to be converted to a floating point value,
4755 // just load it on the floating point unit.
4756 // These patterns are more complex because floating point loads do not
4757 // support sign extension.
4758 // The sign extension has to be explicitly added and is only supported for
4759 // one step: byte-to-half, half-to-word, word-to-doubleword.
4760 // SCVTF GPR -> FPR is 9 cycles.
4761 // SCVTF FPR -> FPR is 4 cyclces.
4762 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4763 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4764 // and still being faster.
4765 // However, this is not good for code size.
4766 // 8-bits -> float. 2 sizes step-up.
4767 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4768 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4769 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4774 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4780 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4782 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4783 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4784 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4785 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4786 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4787 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4788 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4789 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4791 // 16-bits -> float. 1 size step-up.
4792 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4793 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4794 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4796 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4800 ssub)))>, Requires<[NotForCodeSize]>;
4802 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4803 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4804 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4805 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4806 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4807 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4808 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4809 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4811 // 32-bits to 32-bits are handled in target specific dag combine:
4812 // performIntToFpCombine.
4813 // 64-bits integer to 32-bits floating point, not possible with
4814 // SCVTF on floating point registers (both source and destination
4815 // must have the same size).
4817 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4818 // 8-bits -> double. 3 size step-up: give up.
4819 // 16-bits -> double. 2 size step.
4820 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4821 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4822 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4827 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4833 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4835 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4836 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4837 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4838 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4839 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4840 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4841 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4842 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4843 // 32-bits -> double. 1 size step-up.
4844 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4845 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4846 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4848 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4852 dsub)))>, Requires<[NotForCodeSize]>;
4854 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4855 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4856 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4857 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4858 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4859 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4860 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4861 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4863 // 64-bits -> double are handled in target specific dag combine:
4864 // performIntToFpCombine.
4867 //----------------------------------------------------------------------------
4868 // AdvSIMD Load-Store Structure
4869 //----------------------------------------------------------------------------
4870 defm LD1 : SIMDLd1Multiple<"ld1">;
4871 defm LD2 : SIMDLd2Multiple<"ld2">;
4872 defm LD3 : SIMDLd3Multiple<"ld3">;
4873 defm LD4 : SIMDLd4Multiple<"ld4">;
4875 defm ST1 : SIMDSt1Multiple<"st1">;
4876 defm ST2 : SIMDSt2Multiple<"st2">;
4877 defm ST3 : SIMDSt3Multiple<"st3">;
4878 defm ST4 : SIMDSt4Multiple<"st4">;
4880 class Ld1Pat<ValueType ty, Instruction INST>
4881 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4883 def : Ld1Pat<v16i8, LD1Onev16b>;
4884 def : Ld1Pat<v8i16, LD1Onev8h>;
4885 def : Ld1Pat<v4i32, LD1Onev4s>;
4886 def : Ld1Pat<v2i64, LD1Onev2d>;
4887 def : Ld1Pat<v8i8, LD1Onev8b>;
4888 def : Ld1Pat<v4i16, LD1Onev4h>;
4889 def : Ld1Pat<v2i32, LD1Onev2s>;
4890 def : Ld1Pat<v1i64, LD1Onev1d>;
4892 class St1Pat<ValueType ty, Instruction INST>
4893 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4894 (INST ty:$Vt, GPR64sp:$Rn)>;
4896 def : St1Pat<v16i8, ST1Onev16b>;
4897 def : St1Pat<v8i16, ST1Onev8h>;
4898 def : St1Pat<v4i32, ST1Onev4s>;
4899 def : St1Pat<v2i64, ST1Onev2d>;
4900 def : St1Pat<v8i8, ST1Onev8b>;
4901 def : St1Pat<v4i16, ST1Onev4h>;
4902 def : St1Pat<v2i32, ST1Onev2s>;
4903 def : St1Pat<v1i64, ST1Onev1d>;
4909 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4910 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4911 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4912 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4913 let mayLoad = 1, hasSideEffects = 0 in {
4914 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4915 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4916 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4917 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4918 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4919 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4920 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4921 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4922 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4923 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4924 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4925 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4926 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4927 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4928 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4929 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4932 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4933 (LD1Rv8b GPR64sp:$Rn)>;
4934 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4935 (LD1Rv16b GPR64sp:$Rn)>;
4936 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4937 (LD1Rv4h GPR64sp:$Rn)>;
4938 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4939 (LD1Rv8h GPR64sp:$Rn)>;
4940 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4941 (LD1Rv2s GPR64sp:$Rn)>;
4942 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4943 (LD1Rv4s GPR64sp:$Rn)>;
4944 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4945 (LD1Rv2d GPR64sp:$Rn)>;
4946 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4947 (LD1Rv1d GPR64sp:$Rn)>;
4948 // Grab the floating point version too
4949 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4950 (LD1Rv2s GPR64sp:$Rn)>;
4951 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4952 (LD1Rv4s GPR64sp:$Rn)>;
4953 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4954 (LD1Rv2d GPR64sp:$Rn)>;
4955 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4956 (LD1Rv1d GPR64sp:$Rn)>;
4957 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4958 (LD1Rv4h GPR64sp:$Rn)>;
4959 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4960 (LD1Rv8h GPR64sp:$Rn)>;
4962 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4963 ValueType VTy, ValueType STy, Instruction LD1>
4964 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4965 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4966 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4968 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4969 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4970 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4971 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4972 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4973 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4974 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4976 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4977 ValueType VTy, ValueType STy, Instruction LD1>
4978 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4979 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4981 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4982 VecIndex:$idx, GPR64sp:$Rn),
4985 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4986 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4987 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4988 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4989 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4992 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4993 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4994 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4995 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4998 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4999 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
5000 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
5001 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
5003 let AddedComplexity = 19 in
5004 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5005 ValueType VTy, ValueType STy, Instruction ST1>
5007 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5009 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
5011 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
5012 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
5013 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
5014 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
5015 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
5016 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
5017 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
5019 let AddedComplexity = 19 in
5020 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5021 ValueType VTy, ValueType STy, Instruction ST1>
5023 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5025 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5026 VecIndex:$idx, GPR64sp:$Rn)>;
5028 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
5029 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
5030 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
5031 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
5032 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
5034 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5035 ValueType VTy, ValueType STy, Instruction ST1,
5037 def : Pat<(scalar_store
5038 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5039 GPR64sp:$Rn, offset),
5040 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5041 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5043 def : Pat<(scalar_store
5044 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5045 GPR64sp:$Rn, GPR64:$Rm),
5046 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5047 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5050 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
5051 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
5053 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
5054 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
5055 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
5056 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
5057 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
5059 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5060 ValueType VTy, ValueType STy, Instruction ST1,
5062 def : Pat<(scalar_store
5063 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5064 GPR64sp:$Rn, offset),
5065 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5067 def : Pat<(scalar_store
5068 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5069 GPR64sp:$Rn, GPR64:$Rm),
5070 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5073 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
5075 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
5077 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
5078 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
5079 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
5080 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
5081 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
5083 let mayStore = 1, hasSideEffects = 0 in {
5084 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
5085 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
5086 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
5087 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
5088 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
5089 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
5090 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
5091 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
5092 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
5093 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
5094 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
5095 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
5098 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
5099 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
5100 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
5101 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
5103 //----------------------------------------------------------------------------
5104 // Crypto extensions
5105 //----------------------------------------------------------------------------
5107 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
5108 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
5109 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
5110 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
5112 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
5113 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
5114 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
5115 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
5116 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
5117 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
5118 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
5120 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
5121 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
5122 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
5124 //----------------------------------------------------------------------------
5126 //----------------------------------------------------------------------------
5127 // FIXME: Like for X86, these should go in their own separate .td file.
5129 // Any instruction that defines a 32-bit result leaves the high half of the
5130 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
5131 // be copying from a truncate. But any other 32-bit operation will zero-extend
5133 // FIXME: X86 also checks for CMOV here. Do we need something similar?
5134 def def32 : PatLeaf<(i32 GPR32:$src), [{
5135 return N->getOpcode() != ISD::TRUNCATE &&
5136 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
5137 N->getOpcode() != ISD::CopyFromReg;
5140 // In the case of a 32-bit def that is known to implicitly zero-extend,
5141 // we can use a SUBREG_TO_REG.
5142 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
5144 // For an anyext, we don't care what the high bits are, so we can perform an
5145 // INSERT_SUBREF into an IMPLICIT_DEF.
5146 def : Pat<(i64 (anyext GPR32:$src)),
5147 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
5149 // When we need to explicitly zero-extend, we use an unsigned bitfield move
5150 // instruction (UBFM) on the enclosing super-reg.
5151 def : Pat<(i64 (zext GPR32:$src)),
5152 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5154 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
5155 // containing super-reg.
5156 def : Pat<(i64 (sext GPR32:$src)),
5157 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5158 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
5159 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
5160 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
5161 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
5162 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
5163 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
5164 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
5166 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
5167 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5168 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
5169 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
5170 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5171 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
5173 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
5174 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5175 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
5176 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
5177 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5178 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
5180 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
5181 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5182 (i64 (i64shift_a imm0_63:$imm)),
5183 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
5185 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
5186 // AddedComplexity for the following patterns since we want to match sext + sra
5187 // patterns before we attempt to match a single sra node.
5188 let AddedComplexity = 20 in {
5189 // We support all sext + sra combinations which preserve at least one bit of the
5190 // original value which is to be sign extended. E.g. we support shifts up to
5192 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
5193 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
5194 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
5195 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
5197 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
5198 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
5199 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
5200 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
5202 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
5203 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5204 (i64 imm0_31:$imm), 31)>;
5205 } // AddedComplexity = 20
5207 // To truncate, we can simply extract from a subregister.
5208 def : Pat<(i32 (trunc GPR64sp:$src)),
5209 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5211 // __builtin_trap() uses the BRK instruction on AArch64.
5212 def : Pat<(trap), (BRK 1)>;
5214 // Conversions within AdvSIMD types in the same register size are free.
5215 // But because we need a consistent lane ordering, in big endian many
5216 // conversions require one or more REV instructions.
5218 // Consider a simple memory load followed by a bitconvert then a store.
5220 // v1 = BITCAST v2i32 v0 to v4i16
5223 // In big endian mode every memory access has an implicit byte swap. LDR and
5224 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5225 // is, they treat the vector as a sequence of elements to be byte-swapped.
5226 // The two pairs of instructions are fundamentally incompatible. We've decided
5227 // to use LD1/ST1 only to simplify compiler implementation.
5229 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5230 // the original code sequence:
5232 // v1 = REV v2i32 (implicit)
5233 // v2 = BITCAST v2i32 v1 to v4i16
5234 // v3 = REV v4i16 v2 (implicit)
5237 // But this is now broken - the value stored is different to the value loaded
5238 // due to lane reordering. To fix this, on every BITCAST we must perform two
5241 // v1 = REV v2i32 (implicit)
5243 // v3 = BITCAST v2i32 v2 to v4i16
5245 // v5 = REV v4i16 v4 (implicit)
5248 // This means an extra two instructions, but actually in most cases the two REV
5249 // instructions can be combined into one. For example:
5250 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5252 // There is also no 128-bit REV instruction. This must be synthesized with an
5255 // Most bitconverts require some sort of conversion. The only exceptions are:
5256 // a) Identity conversions - vNfX <-> vNiX
5257 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5260 // Natural vector casts (64 bit)
5261 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5262 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5263 def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5264 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5265 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5266 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5268 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5269 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5270 def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5271 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5272 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5274 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5275 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5276 def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5277 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5278 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5280 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5281 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5282 def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5283 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5284 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5285 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5286 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5288 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5289 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5290 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5291 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5292 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5294 // Natural vector casts (128 bit)
5295 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5296 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5297 def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5298 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5299 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5300 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5302 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5303 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5304 def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5305 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5306 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5308 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5309 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5310 def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5311 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5312 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5314 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5315 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5316 def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5317 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5318 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5319 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5320 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5322 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5323 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5324 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5325 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5326 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5328 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5329 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5330 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5331 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5332 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5334 let Predicates = [IsLE] in {
5335 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5336 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5337 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5338 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5339 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5341 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5342 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5343 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5344 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5345 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5346 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5347 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5348 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5349 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5350 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5351 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5352 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5354 let Predicates = [IsBE] in {
5355 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5356 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5357 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5358 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5359 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5360 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5361 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5362 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5363 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5364 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5366 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5367 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5368 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5369 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5370 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5371 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5372 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5373 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5374 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5375 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5377 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5378 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5379 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5380 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5381 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5382 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5383 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5384 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5385 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5387 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5388 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5389 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5390 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5391 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5392 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5393 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5394 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5395 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5396 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5398 let Predicates = [IsLE] in {
5399 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5400 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5401 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5402 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5403 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5405 let Predicates = [IsBE] in {
5406 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5407 (v1i64 (REV64v2i32 FPR64:$src))>;
5408 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5409 (v1i64 (REV64v4i16 FPR64:$src))>;
5410 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5411 (v1i64 (REV64v8i8 FPR64:$src))>;
5412 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5413 (v1i64 (REV64v4i16 FPR64:$src))>;
5414 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5415 (v1i64 (REV64v2i32 FPR64:$src))>;
5417 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5418 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5420 let Predicates = [IsLE] in {
5421 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5422 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5423 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5424 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5425 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5426 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5428 let Predicates = [IsBE] in {
5429 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5430 (v2i32 (REV64v2i32 FPR64:$src))>;
5431 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5432 (v2i32 (REV32v4i16 FPR64:$src))>;
5433 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5434 (v2i32 (REV32v8i8 FPR64:$src))>;
5435 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5436 (v2i32 (REV64v2i32 FPR64:$src))>;
5437 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5438 (v2i32 (REV64v2i32 FPR64:$src))>;
5439 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5440 (v2i32 (REV64v4i16 FPR64:$src))>;
5442 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5444 let Predicates = [IsLE] in {
5445 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5446 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5447 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5448 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5449 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5450 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5451 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5453 let Predicates = [IsBE] in {
5454 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5455 (v4i16 (REV64v4i16 FPR64:$src))>;
5456 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5457 (v4i16 (REV32v4i16 FPR64:$src))>;
5458 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5459 (v4i16 (REV16v8i8 FPR64:$src))>;
5460 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5461 (v4i16 (REV64v4i16 FPR64:$src))>;
5462 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5463 (v4i16 (REV32v4i16 FPR64:$src))>;
5464 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5465 (v4i16 (REV32v4i16 FPR64:$src))>;
5466 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5467 (v4i16 (REV64v4i16 FPR64:$src))>;
5470 let Predicates = [IsLE] in {
5471 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5472 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5473 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5474 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5475 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5476 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5477 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5479 let Predicates = [IsBE] in {
5480 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5481 (v4f16 (REV64v4i16 FPR64:$src))>;
5482 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5483 (v4f16 (REV64v4i16 FPR64:$src))>;
5484 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5485 (v4f16 (REV64v4i16 FPR64:$src))>;
5486 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5487 (v4f16 (REV16v8i8 FPR64:$src))>;
5488 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5489 (v4f16 (REV64v4i16 FPR64:$src))>;
5490 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5491 (v4f16 (REV64v4i16 FPR64:$src))>;
5492 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5493 (v4f16 (REV64v4i16 FPR64:$src))>;
5498 let Predicates = [IsLE] in {
5499 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5500 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5501 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5502 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5503 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5504 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5505 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5507 let Predicates = [IsBE] in {
5508 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5509 (v8i8 (REV64v8i8 FPR64:$src))>;
5510 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5511 (v8i8 (REV32v8i8 FPR64:$src))>;
5512 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5513 (v8i8 (REV16v8i8 FPR64:$src))>;
5514 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5515 (v8i8 (REV64v8i8 FPR64:$src))>;
5516 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5517 (v8i8 (REV32v8i8 FPR64:$src))>;
5518 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5519 (v8i8 (REV64v8i8 FPR64:$src))>;
5520 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5521 (v8i8 (REV16v8i8 FPR64:$src))>;
5524 let Predicates = [IsLE] in {
5525 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5526 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5527 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5528 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5529 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5531 let Predicates = [IsBE] in {
5532 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5533 (f64 (REV64v2i32 FPR64:$src))>;
5534 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5535 (f64 (REV64v4i16 FPR64:$src))>;
5536 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5537 (f64 (REV64v2i32 FPR64:$src))>;
5538 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5539 (f64 (REV64v8i8 FPR64:$src))>;
5540 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5541 (f64 (REV64v4i16 FPR64:$src))>;
5543 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5544 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5546 let Predicates = [IsLE] in {
5547 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5548 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5549 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5550 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5551 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5553 let Predicates = [IsBE] in {
5554 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5555 (v1f64 (REV64v2i32 FPR64:$src))>;
5556 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5557 (v1f64 (REV64v4i16 FPR64:$src))>;
5558 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5559 (v1f64 (REV64v8i8 FPR64:$src))>;
5560 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5561 (v1f64 (REV64v2i32 FPR64:$src))>;
5562 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5563 (v1f64 (REV64v4i16 FPR64:$src))>;
5565 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5566 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5568 let Predicates = [IsLE] in {
5569 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5570 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5571 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5572 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5573 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5574 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5576 let Predicates = [IsBE] in {
5577 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5578 (v2f32 (REV64v2i32 FPR64:$src))>;
5579 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5580 (v2f32 (REV32v4i16 FPR64:$src))>;
5581 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5582 (v2f32 (REV32v8i8 FPR64:$src))>;
5583 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5584 (v2f32 (REV64v2i32 FPR64:$src))>;
5585 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5586 (v2f32 (REV64v2i32 FPR64:$src))>;
5587 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5588 (v2f32 (REV64v4i16 FPR64:$src))>;
5590 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5592 let Predicates = [IsLE] in {
5593 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5594 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5595 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5596 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5597 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5598 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5599 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5601 let Predicates = [IsBE] in {
5602 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5603 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5604 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5605 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5606 (REV64v4i32 FPR128:$src), (i32 8)))>;
5607 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5608 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5609 (REV64v8i16 FPR128:$src), (i32 8)))>;
5610 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5611 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5612 (REV64v8i16 FPR128:$src), (i32 8)))>;
5613 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5614 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5615 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5616 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5617 (REV64v4i32 FPR128:$src), (i32 8)))>;
5618 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5619 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5620 (REV64v16i8 FPR128:$src), (i32 8)))>;
5623 let Predicates = [IsLE] in {
5624 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5625 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5626 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5627 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5628 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5629 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5631 let Predicates = [IsBE] in {
5632 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5633 (v2f64 (EXTv16i8 FPR128:$src,
5634 FPR128:$src, (i32 8)))>;
5635 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5636 (v2f64 (REV64v4i32 FPR128:$src))>;
5637 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5638 (v2f64 (REV64v8i16 FPR128:$src))>;
5639 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5640 (v2f64 (REV64v8i16 FPR128:$src))>;
5641 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5642 (v2f64 (REV64v16i8 FPR128:$src))>;
5643 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5644 (v2f64 (REV64v4i32 FPR128:$src))>;
5646 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5648 let Predicates = [IsLE] in {
5649 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5650 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5651 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5652 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5653 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5654 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5656 let Predicates = [IsBE] in {
5657 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5658 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5659 (REV64v4i32 FPR128:$src), (i32 8)))>;
5660 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5661 (v4f32 (REV32v8i16 FPR128:$src))>;
5662 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5663 (v4f32 (REV32v8i16 FPR128:$src))>;
5664 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5665 (v4f32 (REV32v16i8 FPR128:$src))>;
5666 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5667 (v4f32 (REV64v4i32 FPR128:$src))>;
5668 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5669 (v4f32 (REV64v4i32 FPR128:$src))>;
5671 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5673 let Predicates = [IsLE] in {
5674 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5675 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5676 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5677 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5678 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5679 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5681 let Predicates = [IsBE] in {
5682 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5683 (v2i64 (EXTv16i8 FPR128:$src,
5684 FPR128:$src, (i32 8)))>;
5685 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5686 (v2i64 (REV64v4i32 FPR128:$src))>;
5687 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5688 (v2i64 (REV64v8i16 FPR128:$src))>;
5689 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5690 (v2i64 (REV64v16i8 FPR128:$src))>;
5691 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5692 (v2i64 (REV64v4i32 FPR128:$src))>;
5693 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5694 (v2i64 (REV64v8i16 FPR128:$src))>;
5696 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5698 let Predicates = [IsLE] in {
5699 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5700 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5701 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5702 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5703 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5704 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5706 let Predicates = [IsBE] in {
5707 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5708 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5709 (REV64v4i32 FPR128:$src),
5711 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5712 (v4i32 (REV64v4i32 FPR128:$src))>;
5713 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5714 (v4i32 (REV32v8i16 FPR128:$src))>;
5715 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5716 (v4i32 (REV32v16i8 FPR128:$src))>;
5717 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5718 (v4i32 (REV64v4i32 FPR128:$src))>;
5719 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5720 (v4i32 (REV32v8i16 FPR128:$src))>;
5722 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5724 let Predicates = [IsLE] in {
5725 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5726 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5727 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5728 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5729 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5730 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5731 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5733 let Predicates = [IsBE] in {
5734 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5735 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5736 (REV64v8i16 FPR128:$src),
5738 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5739 (v8i16 (REV64v8i16 FPR128:$src))>;
5740 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5741 (v8i16 (REV32v8i16 FPR128:$src))>;
5742 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5743 (v8i16 (REV16v16i8 FPR128:$src))>;
5744 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5745 (v8i16 (REV64v8i16 FPR128:$src))>;
5746 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5747 (v8i16 (REV32v8i16 FPR128:$src))>;
5748 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5749 (v8i16 (REV32v8i16 FPR128:$src))>;
5752 let Predicates = [IsLE] in {
5753 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5754 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5755 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5756 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5757 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5758 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5759 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5761 let Predicates = [IsBE] in {
5762 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5763 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5764 (REV64v8i16 FPR128:$src),
5766 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5767 (v8f16 (REV64v8i16 FPR128:$src))>;
5768 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5769 (v8f16 (REV32v8i16 FPR128:$src))>;
5770 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5771 (v8f16 (REV64v8i16 FPR128:$src))>;
5772 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5773 (v8f16 (REV16v16i8 FPR128:$src))>;
5774 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5775 (v8f16 (REV64v8i16 FPR128:$src))>;
5776 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5777 (v8f16 (REV32v8i16 FPR128:$src))>;
5780 let Predicates = [IsLE] in {
5781 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5782 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5783 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5784 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5785 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5786 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5787 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5789 let Predicates = [IsBE] in {
5790 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5791 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5792 (REV64v16i8 FPR128:$src),
5794 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5795 (v16i8 (REV64v16i8 FPR128:$src))>;
5796 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5797 (v16i8 (REV32v16i8 FPR128:$src))>;
5798 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5799 (v16i8 (REV16v16i8 FPR128:$src))>;
5800 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5801 (v16i8 (REV64v16i8 FPR128:$src))>;
5802 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5803 (v16i8 (REV32v16i8 FPR128:$src))>;
5804 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5805 (v16i8 (REV16v16i8 FPR128:$src))>;
5808 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5809 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5810 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5811 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5812 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5813 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5814 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5815 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5817 // A 64-bit subvector insert to the first 128-bit vector position
5818 // is a subregister copy that needs no instruction.
5819 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5820 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5821 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5822 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5823 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5824 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5825 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5826 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5827 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5828 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5829 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5830 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5831 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5832 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5834 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5836 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5837 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5838 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5839 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5840 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5841 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5842 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5843 // so we match on v4f32 here, not v2f32. This will also catch adding
5844 // the low two lanes of a true v4f32 vector.
5845 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5846 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5847 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5849 // Scalar 64-bit shifts in FPR64 registers.
5850 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5851 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5852 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5853 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5854 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5855 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5856 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5857 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5859 // Tail call return handling. These are all compiler pseudo-instructions,
5860 // so no encoding information or anything like that.
5861 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5862 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5863 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5866 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5867 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5868 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5869 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5870 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5871 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5873 include "AArch64InstrAtomics.td"