1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
18 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
19 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
20 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
21 def HasNEON : Predicate<"Subtarget->hasNEON()">,
22 AssemblerPredicate<"FeatureNEON", "neon">;
23 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
24 AssemblerPredicate<"FeatureCrypto", "crypto">;
25 def HasCRC : Predicate<"Subtarget->hasCRC()">,
26 AssemblerPredicate<"FeatureCRC", "crc">;
27 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
28 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
29 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
31 //===----------------------------------------------------------------------===//
32 // AArch64-specific DAG Nodes.
35 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
36 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
39 SDTCisInt<0>, SDTCisVT<1, i32>]>;
41 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
42 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
48 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
49 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
56 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
59 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
60 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
61 SDTCisVT<2, OtherVT>]>;
64 def SDT_AArch64CSel : SDTypeProfile<1, 4,
69 def SDT_AArch64CCMP : SDTypeProfile<1, 5,
76 def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
83 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
86 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
87 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
88 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
91 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
92 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
93 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
94 SDTCisInt<2>, SDTCisInt<3>]>;
95 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
96 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
97 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
98 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
100 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
101 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
102 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
103 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
105 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
108 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
109 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
111 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
113 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
116 // Generates the general dynamic sequences, i.e.
117 // adrp x0, :tlsdesc:var
118 // ldr x1, [x0, #:tlsdesc_lo12:var]
119 // add x0, x0, #:tlsdesc_lo12:var
123 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
124 // number of operands (the variable)
125 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
128 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
129 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
130 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
131 SDTCisSameAs<1, 4>]>;
135 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
136 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
137 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
138 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
139 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
140 [SDNPHasChain, SDNPOutGlue]>;
141 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
142 SDCallSeqEnd<[ SDTCisVT<0, i32>,
144 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
145 def AArch64call : SDNode<"AArch64ISD::CALL",
146 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
147 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
149 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
151 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
153 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
155 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
157 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
161 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
162 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
163 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
164 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
165 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
166 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
167 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
168 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
169 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
171 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
172 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
174 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
175 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
177 def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>;
178 def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>;
179 def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>;
181 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
183 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
185 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
186 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
187 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
188 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
189 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
191 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
192 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
193 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
194 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
195 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
196 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
198 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
199 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
200 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
201 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
202 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
203 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
204 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
206 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
207 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
208 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
209 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
211 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
212 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
213 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
214 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
215 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
216 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
217 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
218 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
220 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
221 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
222 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
224 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
225 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
226 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
227 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
228 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
230 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
231 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
232 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
234 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
235 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
236 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
237 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
238 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
239 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
240 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
242 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
243 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
244 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
245 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
246 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
248 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
249 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
251 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
253 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
254 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
256 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
257 [SDNPHasChain, SDNPSideEffect]>;
259 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
260 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
262 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
263 SDT_AArch64TLSDescCallSeq,
264 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
268 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
269 SDT_AArch64WrapperLarge>;
271 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
273 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
274 SDTCisSameAs<1, 2>]>;
275 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
276 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
278 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
279 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
280 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
281 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
282 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
283 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
285 //===----------------------------------------------------------------------===//
287 //===----------------------------------------------------------------------===//
289 // AArch64 Instruction Predicate Definitions.
291 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
292 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
293 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
294 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
295 def ForCodeSize : Predicate<"ForCodeSize">;
296 def NotForCodeSize : Predicate<"!ForCodeSize">;
298 include "AArch64InstrFormats.td"
300 //===----------------------------------------------------------------------===//
302 //===----------------------------------------------------------------------===//
303 // Miscellaneous instructions.
304 //===----------------------------------------------------------------------===//
306 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
307 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
308 [(AArch64callseq_start timm:$amt)]>;
309 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
310 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
311 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
313 let isReMaterializable = 1, isCodeGenOnly = 1 in {
314 // FIXME: The following pseudo instructions are only needed because remat
315 // cannot handle multiple instructions. When that changes, they can be
316 // removed, along with the AArch64Wrapper node.
318 let AddedComplexity = 10 in
319 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
320 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
323 // The MOVaddr instruction should match only when the add is not folded
324 // into a load or store address.
326 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
327 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
328 tglobaladdr:$low))]>,
329 Sched<[WriteAdrAdr]>;
331 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
332 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
334 Sched<[WriteAdrAdr]>;
336 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
337 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
339 Sched<[WriteAdrAdr]>;
341 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
342 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
343 tblockaddress:$low))]>,
344 Sched<[WriteAdrAdr]>;
346 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
347 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
348 tglobaltlsaddr:$low))]>,
349 Sched<[WriteAdrAdr]>;
351 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
352 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
353 texternalsym:$low))]>,
354 Sched<[WriteAdrAdr]>;
356 } // isReMaterializable, isCodeGenOnly
358 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
359 (LOADgot tglobaltlsaddr:$addr)>;
361 def : Pat<(AArch64LOADgot texternalsym:$addr),
362 (LOADgot texternalsym:$addr)>;
364 def : Pat<(AArch64LOADgot tconstpool:$addr),
365 (LOADgot tconstpool:$addr)>;
367 //===----------------------------------------------------------------------===//
368 // System instructions.
369 //===----------------------------------------------------------------------===//
371 def HINT : HintI<"hint">;
372 def : InstAlias<"nop", (HINT 0b000)>;
373 def : InstAlias<"yield",(HINT 0b001)>;
374 def : InstAlias<"wfe", (HINT 0b010)>;
375 def : InstAlias<"wfi", (HINT 0b011)>;
376 def : InstAlias<"sev", (HINT 0b100)>;
377 def : InstAlias<"sevl", (HINT 0b101)>;
379 // As far as LLVM is concerned this writes to the system's exclusive monitors.
380 let mayLoad = 1, mayStore = 1 in
381 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
383 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
384 // model patterns with sufficiently fine granularity.
385 let mayLoad = ?, mayStore = ? in {
386 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
387 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
389 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
390 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
392 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
393 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
396 def : InstAlias<"clrex", (CLREX 0xf)>;
397 def : InstAlias<"isb", (ISB 0xf)>;
401 def MSRpstate: MSRpstateI;
403 // The thread pointer (on Linux, at least, where this has been implemented) is
405 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
407 // Generic system instructions
408 def SYSxt : SystemXtI<0, "sys">;
409 def SYSLxt : SystemLXtI<1, "sysl">;
411 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
412 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
413 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
415 //===----------------------------------------------------------------------===//
416 // Move immediate instructions.
417 //===----------------------------------------------------------------------===//
419 defm MOVK : InsertImmediate<0b11, "movk">;
420 defm MOVN : MoveImmediate<0b00, "movn">;
422 let PostEncoderMethod = "fixMOVZ" in
423 defm MOVZ : MoveImmediate<0b10, "movz">;
425 // First group of aliases covers an implicit "lsl #0".
426 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
427 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
428 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
429 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
430 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
431 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
433 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
434 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
435 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
436 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
437 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
439 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
440 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
441 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
442 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
444 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
445 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
446 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
447 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
449 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
450 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
452 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
453 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
455 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
456 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
458 // Final group of aliases covers true "mov $Rd, $imm" cases.
459 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
460 int width, int shift> {
461 def _asmoperand : AsmOperandClass {
462 let Name = basename # width # "_lsl" # shift # "MovAlias";
463 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
465 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
468 def _movimm : Operand<i32> {
469 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
472 def : InstAlias<"mov $Rd, $imm",
473 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
476 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
477 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
479 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
480 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
481 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
482 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
484 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
485 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
487 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
488 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
489 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
490 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
492 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
493 isAsCheapAsAMove = 1 in {
494 // FIXME: The following pseudo instructions are only needed because remat
495 // cannot handle multiple instructions. When that changes, we can select
496 // directly to the real instructions and get rid of these pseudos.
499 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
500 [(set GPR32:$dst, imm:$src)]>,
503 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
504 [(set GPR64:$dst, imm:$src)]>,
506 } // isReMaterializable, isCodeGenOnly
508 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
509 // eventual expansion code fewer bits to worry about getting right. Marshalling
510 // the types is a little tricky though:
511 def i64imm_32bit : ImmLeaf<i64, [{
512 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
515 def trunc_imm : SDNodeXForm<imm, [{
516 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32);
519 def : Pat<(i64 i64imm_32bit:$src),
520 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
522 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
523 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
524 return CurDAG->getTargetConstant(
525 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
528 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
529 return CurDAG->getTargetConstant(
530 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
534 def : Pat<(f32 fpimm:$in),
535 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
536 def : Pat<(f64 fpimm:$in),
537 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
540 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
542 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
543 tglobaladdr:$g1, tglobaladdr:$g0),
544 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
545 tglobaladdr:$g2, 32),
546 tglobaladdr:$g1, 16),
547 tglobaladdr:$g0, 0)>;
549 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
550 tblockaddress:$g1, tblockaddress:$g0),
551 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
552 tblockaddress:$g2, 32),
553 tblockaddress:$g1, 16),
554 tblockaddress:$g0, 0)>;
556 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
557 tconstpool:$g1, tconstpool:$g0),
558 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
563 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
564 tjumptable:$g1, tjumptable:$g0),
565 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
571 //===----------------------------------------------------------------------===//
572 // Arithmetic instructions.
573 //===----------------------------------------------------------------------===//
575 // Add/subtract with carry.
576 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
577 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
579 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
580 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
581 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
582 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
585 defm ADD : AddSub<0, "add", "sub", add>;
586 defm SUB : AddSub<1, "sub", "add">;
588 def : InstAlias<"mov $dst, $src",
589 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
590 def : InstAlias<"mov $dst, $src",
591 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
592 def : InstAlias<"mov $dst, $src",
593 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
594 def : InstAlias<"mov $dst, $src",
595 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
597 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;
598 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">;
600 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
601 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
602 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
603 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
604 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
605 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
606 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
607 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
608 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
609 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
610 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
611 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
612 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
613 let AddedComplexity = 1 in {
614 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
615 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
616 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
617 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
620 // Because of the immediate format for add/sub-imm instructions, the
621 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
622 // These patterns capture that transformation.
623 let AddedComplexity = 1 in {
624 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
625 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
626 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
627 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
628 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
629 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
630 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
631 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
634 // Because of the immediate format for add/sub-imm instructions, the
635 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
636 // These patterns capture that transformation.
637 let AddedComplexity = 1 in {
638 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
639 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
640 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
641 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
642 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
643 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
644 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
645 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
648 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
649 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
650 def : InstAlias<"neg $dst, $src$shift",
651 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
652 def : InstAlias<"neg $dst, $src$shift",
653 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
655 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
656 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
657 def : InstAlias<"negs $dst, $src$shift",
658 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
659 def : InstAlias<"negs $dst, $src$shift",
660 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
663 // Unsigned/Signed divide
664 defm UDIV : Div<0, "udiv", udiv>;
665 defm SDIV : Div<1, "sdiv", sdiv>;
666 let isCodeGenOnly = 1 in {
667 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
668 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
672 defm ASRV : Shift<0b10, "asr", sra>;
673 defm LSLV : Shift<0b00, "lsl", shl>;
674 defm LSRV : Shift<0b01, "lsr", srl>;
675 defm RORV : Shift<0b11, "ror", rotr>;
677 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
678 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
679 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
680 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
681 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
682 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
683 def : ShiftAlias<"rorv", RORVWr, GPR32>;
684 def : ShiftAlias<"rorv", RORVXr, GPR64>;
687 let AddedComplexity = 7 in {
688 defm MADD : MulAccum<0, "madd", add>;
689 defm MSUB : MulAccum<1, "msub", sub>;
691 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
692 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
693 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
694 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
696 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
697 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
698 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
699 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
700 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
701 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
702 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
703 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
704 } // AddedComplexity = 7
706 let AddedComplexity = 5 in {
707 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
708 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
709 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
710 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
712 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
713 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
714 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
715 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
717 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
718 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
719 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
720 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
721 } // AddedComplexity = 5
723 def : MulAccumWAlias<"mul", MADDWrrr>;
724 def : MulAccumXAlias<"mul", MADDXrrr>;
725 def : MulAccumWAlias<"mneg", MSUBWrrr>;
726 def : MulAccumXAlias<"mneg", MSUBXrrr>;
727 def : WideMulAccumAlias<"smull", SMADDLrrr>;
728 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
729 def : WideMulAccumAlias<"umull", UMADDLrrr>;
730 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
733 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
734 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
737 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
738 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
739 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
740 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
742 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
743 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
744 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
745 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
748 defm CAS : CompareAndSwap<0, 0, "">;
749 defm CASA : CompareAndSwap<1, 0, "a">;
750 defm CASL : CompareAndSwap<0, 1, "l">;
751 defm CASAL : CompareAndSwap<1, 1, "al">;
754 defm CASP : CompareAndSwapPair<0, 0, "">;
755 defm CASPA : CompareAndSwapPair<1, 0, "a">;
756 defm CASPL : CompareAndSwapPair<0, 1, "l">;
757 defm CASPAL : CompareAndSwapPair<1, 1, "al">;
760 defm SWP : Swap<0, 0, "">;
761 defm SWPA : Swap<1, 0, "a">;
762 defm SWPL : Swap<0, 1, "l">;
763 defm SWPAL : Swap<1, 1, "al">;
765 // v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)
766 defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
767 defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
768 defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;
769 defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;
771 defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">;
772 defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">;
773 defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">;
774 defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">;
776 defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">;
777 defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">;
778 defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">;
779 defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">;
781 defm LDSET : LDOPregister<0b011, "set", 0, 0, "">;
782 defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">;
783 defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">;
784 defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">;
786 defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">;
787 defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">;
788 defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;
789 defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;
791 defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;
792 defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;
793 defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;
794 defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;
796 defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">;
797 defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">;
798 defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">;
799 defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">;
801 defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">;
802 defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">;
803 defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">;
804 defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">;
806 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
807 defm : STOPregister<"stadd","LDADD">; // STADDx
808 defm : STOPregister<"stclr","LDCLR">; // STCLRx
809 defm : STOPregister<"steor","LDEOR">; // STEORx
810 defm : STOPregister<"stset","LDSET">; // STSETx
811 defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx
812 defm : STOPregister<"stsmin","LDSMIN">;// STSMINx
813 defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
814 defm : STOPregister<"stumin","LDUMIN">;// STUMINx
816 //===----------------------------------------------------------------------===//
817 // Logical instructions.
818 //===----------------------------------------------------------------------===//
821 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
822 defm AND : LogicalImm<0b00, "and", and, "bic">;
823 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
824 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
826 // FIXME: these aliases *are* canonical sometimes (when movz can't be
827 // used). Actually, it seems to be working right now, but putting logical_immXX
828 // here is a bit dodgy on the AsmParser side too.
829 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
830 logical_imm32:$imm), 0>;
831 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
832 logical_imm64:$imm), 0>;
836 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
837 defm BICS : LogicalRegS<0b11, 1, "bics",
838 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
839 defm AND : LogicalReg<0b00, 0, "and", and>;
840 defm BIC : LogicalReg<0b00, 1, "bic",
841 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
842 defm EON : LogicalReg<0b10, 1, "eon",
843 BinOpFrag<(not (xor node:$LHS, node:$RHS))>>;
844 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
845 defm ORN : LogicalReg<0b01, 1, "orn",
846 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
847 defm ORR : LogicalReg<0b01, 0, "orr", or>;
849 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
850 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
852 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
853 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
855 def : InstAlias<"mvn $Wd, $Wm$sh",
856 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
857 def : InstAlias<"mvn $Xd, $Xm$sh",
858 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
860 def : InstAlias<"tst $src1, $src2",
861 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
862 def : InstAlias<"tst $src1, $src2",
863 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
865 def : InstAlias<"tst $src1, $src2",
866 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
867 def : InstAlias<"tst $src1, $src2",
868 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
870 def : InstAlias<"tst $src1, $src2$sh",
871 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
872 def : InstAlias<"tst $src1, $src2$sh",
873 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
876 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
877 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
880 //===----------------------------------------------------------------------===//
881 // One operand data processing instructions.
882 //===----------------------------------------------------------------------===//
884 defm CLS : OneOperandData<0b101, "cls">;
885 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
886 defm RBIT : OneOperandData<0b000, "rbit">;
888 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
889 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
891 def REV16Wr : OneWRegData<0b001, "rev16",
892 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
893 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
895 def : Pat<(cttz GPR32:$Rn),
896 (CLZWr (RBITWr GPR32:$Rn))>;
897 def : Pat<(cttz GPR64:$Rn),
898 (CLZXr (RBITXr GPR64:$Rn))>;
899 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
902 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
906 // Unlike the other one operand instructions, the instructions with the "rev"
907 // mnemonic do *not* just different in the size bit, but actually use different
908 // opcode bits for the different sizes.
909 def REVWr : OneWRegData<0b010, "rev", bswap>;
910 def REVXr : OneXRegData<0b011, "rev", bswap>;
911 def REV32Xr : OneXRegData<0b010, "rev32",
912 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
914 def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
916 // The bswap commutes with the rotr so we want a pattern for both possible
918 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
919 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
921 //===----------------------------------------------------------------------===//
922 // Bitfield immediate extraction instruction.
923 //===----------------------------------------------------------------------===//
924 let hasSideEffects = 0 in
925 defm EXTR : ExtractImm<"extr">;
926 def : InstAlias<"ror $dst, $src, $shift",
927 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
928 def : InstAlias<"ror $dst, $src, $shift",
929 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
931 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
932 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
933 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
934 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
936 //===----------------------------------------------------------------------===//
937 // Other bitfield immediate instructions.
938 //===----------------------------------------------------------------------===//
939 let hasSideEffects = 0 in {
940 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
941 defm SBFM : BitfieldImm<0b00, "sbfm">;
942 defm UBFM : BitfieldImm<0b10, "ubfm">;
945 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
946 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
947 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
950 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
951 uint64_t enc = 31 - N->getZExtValue();
952 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
955 // min(7, 31 - shift_amt)
956 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
957 uint64_t enc = 31 - N->getZExtValue();
958 enc = enc > 7 ? 7 : enc;
959 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
962 // min(15, 31 - shift_amt)
963 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
964 uint64_t enc = 31 - N->getZExtValue();
965 enc = enc > 15 ? 15 : enc;
966 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
969 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
970 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
971 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
974 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
975 uint64_t enc = 63 - N->getZExtValue();
976 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
979 // min(7, 63 - shift_amt)
980 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
981 uint64_t enc = 63 - N->getZExtValue();
982 enc = enc > 7 ? 7 : enc;
983 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
986 // min(15, 63 - shift_amt)
987 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
988 uint64_t enc = 63 - N->getZExtValue();
989 enc = enc > 15 ? 15 : enc;
990 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
993 // min(31, 63 - shift_amt)
994 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
995 uint64_t enc = 63 - N->getZExtValue();
996 enc = enc > 31 ? 31 : enc;
997 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1000 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
1001 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
1002 (i64 (i32shift_b imm0_31:$imm)))>;
1003 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
1004 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
1005 (i64 (i64shift_b imm0_63:$imm)))>;
1007 let AddedComplexity = 10 in {
1008 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
1009 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1010 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
1011 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1014 def : InstAlias<"asr $dst, $src, $shift",
1015 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1016 def : InstAlias<"asr $dst, $src, $shift",
1017 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1018 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1019 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1020 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1021 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1022 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1024 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
1025 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1026 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
1027 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1029 def : InstAlias<"lsr $dst, $src, $shift",
1030 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1031 def : InstAlias<"lsr $dst, $src, $shift",
1032 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1033 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1034 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1035 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1036 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1037 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1039 //===----------------------------------------------------------------------===//
1040 // Conditional comparison instructions.
1041 //===----------------------------------------------------------------------===//
1042 defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>;
1043 defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>;
1045 //===----------------------------------------------------------------------===//
1046 // Conditional select instructions.
1047 //===----------------------------------------------------------------------===//
1048 defm CSEL : CondSelect<0, 0b00, "csel">;
1050 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
1051 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1052 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1053 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1055 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1056 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1057 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1058 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1059 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1060 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1061 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1062 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1063 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1064 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1065 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1066 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1068 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
1069 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
1070 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
1071 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
1072 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
1073 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
1074 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
1075 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
1077 // The inverse of the condition code from the alias instruction is what is used
1078 // in the aliased instruction. The parser all ready inverts the condition code
1079 // for these aliases.
1080 def : InstAlias<"cset $dst, $cc",
1081 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1082 def : InstAlias<"cset $dst, $cc",
1083 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1085 def : InstAlias<"csetm $dst, $cc",
1086 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1087 def : InstAlias<"csetm $dst, $cc",
1088 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1090 def : InstAlias<"cinc $dst, $src, $cc",
1091 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1092 def : InstAlias<"cinc $dst, $src, $cc",
1093 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1095 def : InstAlias<"cinv $dst, $src, $cc",
1096 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1097 def : InstAlias<"cinv $dst, $src, $cc",
1098 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1100 def : InstAlias<"cneg $dst, $src, $cc",
1101 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1102 def : InstAlias<"cneg $dst, $src, $cc",
1103 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1105 //===----------------------------------------------------------------------===//
1106 // PC-relative instructions.
1107 //===----------------------------------------------------------------------===//
1108 let isReMaterializable = 1 in {
1109 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1110 def ADR : ADRI<0, "adr", adrlabel, []>;
1111 } // hasSideEffects = 0
1113 def ADRP : ADRI<1, "adrp", adrplabel,
1114 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1115 } // isReMaterializable = 1
1117 // page address of a constant pool entry, block address
1118 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1119 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1121 //===----------------------------------------------------------------------===//
1122 // Unconditional branch (register) instructions.
1123 //===----------------------------------------------------------------------===//
1125 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1126 def RET : BranchReg<0b0010, "ret", []>;
1127 def DRPS : SpecialReturn<0b0101, "drps">;
1128 def ERET : SpecialReturn<0b0100, "eret">;
1129 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1131 // Default to the LR register.
1132 def : InstAlias<"ret", (RET LR)>;
1134 let isCall = 1, Defs = [LR], Uses = [SP] in {
1135 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1138 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1139 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1140 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1142 // Create a separate pseudo-instruction for codegen to use so that we don't
1143 // flag lr as used in every function. It'll be restored before the RET by the
1144 // epilogue if it's legitimately used.
1145 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1146 let isTerminator = 1;
1151 // This is a directive-like pseudo-instruction. The purpose is to insert an
1152 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1153 // (which in the usual case is a BLR).
1154 let hasSideEffects = 1 in
1155 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1156 let AsmString = ".tlsdesccall $sym";
1159 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
1160 // FIXME: can "hasSideEffects be dropped?
1161 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
1162 isCodeGenOnly = 1 in
1164 : Pseudo<(outs), (ins i64imm:$sym),
1165 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>;
1166 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
1167 (TLSDESC_CALLSEQ texternalsym:$sym)>;
1169 //===----------------------------------------------------------------------===//
1170 // Conditional branch (immediate) instruction.
1171 //===----------------------------------------------------------------------===//
1172 def Bcc : BranchCond;
1174 //===----------------------------------------------------------------------===//
1175 // Compare-and-branch instructions.
1176 //===----------------------------------------------------------------------===//
1177 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1178 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1180 //===----------------------------------------------------------------------===//
1181 // Test-bit-and-branch instructions.
1182 //===----------------------------------------------------------------------===//
1183 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1184 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1186 //===----------------------------------------------------------------------===//
1187 // Unconditional branch (immediate) instructions.
1188 //===----------------------------------------------------------------------===//
1189 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1190 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1191 } // isBranch, isTerminator, isBarrier
1193 let isCall = 1, Defs = [LR], Uses = [SP] in {
1194 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1196 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1198 //===----------------------------------------------------------------------===//
1199 // Exception generation instructions.
1200 //===----------------------------------------------------------------------===//
1201 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1202 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1203 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1204 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1205 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1206 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1207 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1208 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1210 // DCPSn defaults to an immediate operand of zero if unspecified.
1211 def : InstAlias<"dcps1", (DCPS1 0)>;
1212 def : InstAlias<"dcps2", (DCPS2 0)>;
1213 def : InstAlias<"dcps3", (DCPS3 0)>;
1215 //===----------------------------------------------------------------------===//
1216 // Load instructions.
1217 //===----------------------------------------------------------------------===//
1219 // Pair (indexed, offset)
1220 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1221 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1222 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1223 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1224 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1226 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1228 // Pair (pre-indexed)
1229 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1230 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1231 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1232 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1233 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1235 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1237 // Pair (post-indexed)
1238 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1239 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1240 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1241 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1242 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1244 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1247 // Pair (no allocate)
1248 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1249 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1250 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1251 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1252 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1255 // (register offset)
1259 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1260 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1261 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1262 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1265 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1266 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1267 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1268 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1269 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1271 // Load sign-extended half-word
1272 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1273 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1275 // Load sign-extended byte
1276 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1277 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1279 // Load sign-extended word
1280 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1283 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1285 // For regular load, we do not have any alignment requirement.
1286 // Thus, it is safe to directly map the vector loads with interesting
1287 // addressing modes.
1288 // FIXME: We could do the same for bitconvert to floating point vectors.
1289 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1290 ValueType ScalTy, ValueType VecTy,
1291 Instruction LOADW, Instruction LOADX,
1293 def : Pat<(VecTy (scalar_to_vector (ScalTy
1294 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1295 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1296 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1299 def : Pat<(VecTy (scalar_to_vector (ScalTy
1300 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1301 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1302 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1306 let AddedComplexity = 10 in {
1307 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1308 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1310 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1311 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1313 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1314 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1316 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1317 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1319 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1320 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1322 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1324 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1327 def : Pat <(v1i64 (scalar_to_vector (i64
1328 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1329 ro_Wextend64:$extend))))),
1330 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1332 def : Pat <(v1i64 (scalar_to_vector (i64
1333 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1334 ro_Xextend64:$extend))))),
1335 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1338 // Match all load 64 bits width whose type is compatible with FPR64
1339 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1340 Instruction LOADW, Instruction LOADX> {
1342 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1343 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1345 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1346 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1349 let AddedComplexity = 10 in {
1350 let Predicates = [IsLE] in {
1351 // We must do vector loads with LD1 in big-endian.
1352 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1353 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1354 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1355 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1356 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1359 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1360 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1362 // Match all load 128 bits width whose type is compatible with FPR128
1363 let Predicates = [IsLE] in {
1364 // We must do vector loads with LD1 in big-endian.
1365 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1366 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1367 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1368 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1369 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1370 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1371 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1373 } // AddedComplexity = 10
1376 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1377 Instruction INSTW, Instruction INSTX> {
1378 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1379 (SUBREG_TO_REG (i64 0),
1380 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1383 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1384 (SUBREG_TO_REG (i64 0),
1385 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1389 let AddedComplexity = 10 in {
1390 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1391 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1392 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1394 // zextloadi1 -> zextloadi8
1395 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1397 // extload -> zextload
1398 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1399 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1400 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1402 // extloadi1 -> zextloadi8
1403 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1408 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1409 Instruction INSTW, Instruction INSTX> {
1410 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1411 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1413 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1414 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1418 let AddedComplexity = 10 in {
1419 // extload -> zextload
1420 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1421 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1422 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1424 // zextloadi1 -> zextloadi8
1425 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1429 // (unsigned immediate)
1431 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1433 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1434 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1436 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1437 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1439 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1440 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1441 [(set (f16 FPR16:$Rt),
1442 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1443 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1444 [(set (f32 FPR32:$Rt),
1445 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1446 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1447 [(set (f64 FPR64:$Rt),
1448 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1449 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1450 [(set (f128 FPR128:$Rt),
1451 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1453 // For regular load, we do not have any alignment requirement.
1454 // Thus, it is safe to directly map the vector loads with interesting
1455 // addressing modes.
1456 // FIXME: We could do the same for bitconvert to floating point vectors.
1457 def : Pat <(v8i8 (scalar_to_vector (i32
1458 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1459 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1460 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1461 def : Pat <(v16i8 (scalar_to_vector (i32
1462 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1463 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1464 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1465 def : Pat <(v4i16 (scalar_to_vector (i32
1466 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1467 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1468 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1469 def : Pat <(v8i16 (scalar_to_vector (i32
1470 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1471 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1472 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1473 def : Pat <(v2i32 (scalar_to_vector (i32
1474 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1475 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1476 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1477 def : Pat <(v4i32 (scalar_to_vector (i32
1478 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1479 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1480 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1481 def : Pat <(v1i64 (scalar_to_vector (i64
1482 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1483 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1484 def : Pat <(v2i64 (scalar_to_vector (i64
1485 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1486 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1487 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1489 // Match all load 64 bits width whose type is compatible with FPR64
1490 let Predicates = [IsLE] in {
1491 // We must use LD1 to perform vector loads in big-endian.
1492 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1493 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1494 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1495 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1496 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1497 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1498 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1499 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1500 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1501 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1503 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1504 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1505 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1506 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1508 // Match all load 128 bits width whose type is compatible with FPR128
1509 let Predicates = [IsLE] in {
1510 // We must use LD1 to perform vector loads in big-endian.
1511 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1512 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1513 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1514 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1515 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1516 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1517 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1518 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1519 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1520 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1521 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1522 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1523 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1524 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1526 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1527 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1529 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1531 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1532 uimm12s2:$offset)))]>;
1533 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1535 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1536 uimm12s1:$offset)))]>;
1538 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1539 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1540 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1541 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1543 // zextloadi1 -> zextloadi8
1544 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1545 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1546 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1547 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1549 // extload -> zextload
1550 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1551 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1552 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1553 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1554 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1555 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1556 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1557 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1558 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1559 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1560 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1561 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1562 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1563 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1565 // load sign-extended half-word
1566 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1568 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1569 uimm12s2:$offset)))]>;
1570 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1572 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1573 uimm12s2:$offset)))]>;
1575 // load sign-extended byte
1576 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1578 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1579 uimm12s1:$offset)))]>;
1580 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1582 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1583 uimm12s1:$offset)))]>;
1585 // load sign-extended word
1586 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1588 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1589 uimm12s4:$offset)))]>;
1591 // load zero-extended word
1592 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1593 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1596 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1597 [(AArch64Prefetch imm:$Rt,
1598 (am_indexed64 GPR64sp:$Rn,
1599 uimm12s8:$offset))]>;
1601 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1605 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1606 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1607 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1608 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1609 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1611 // load sign-extended word
1612 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1615 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1616 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1619 // (unscaled immediate)
1620 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1622 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1623 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1625 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1626 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1628 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1629 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1631 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1632 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1633 [(set (f32 FPR32:$Rt),
1634 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1635 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1636 [(set (f64 FPR64:$Rt),
1637 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1638 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1639 [(set (f128 FPR128:$Rt),
1640 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1643 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1645 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1647 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1649 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1651 // Match all load 64 bits width whose type is compatible with FPR64
1652 let Predicates = [IsLE] in {
1653 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1654 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1655 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1656 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1657 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1658 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1659 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1660 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1661 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1662 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1664 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1665 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1666 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1667 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1669 // Match all load 128 bits width whose type is compatible with FPR128
1670 let Predicates = [IsLE] in {
1671 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1672 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1673 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1674 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1675 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1676 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1677 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1678 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1679 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1680 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1681 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1682 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1683 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1684 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1688 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1689 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1690 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1691 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1692 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1693 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1694 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1695 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1696 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1697 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1698 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1699 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1700 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1701 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1703 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1704 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1705 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1706 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1707 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1708 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1709 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1710 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1711 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1712 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1713 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1714 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1715 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1716 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1720 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1722 // Define new assembler match classes as we want to only match these when
1723 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1724 // associate a DiagnosticType either, as we want the diagnostic for the
1725 // canonical form (the scaled operand) to take precedence.
1726 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1727 let Name = "SImm9OffsetFB" # Width;
1728 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1729 let RenderMethod = "addImmOperands";
1732 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1733 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1734 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1735 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1736 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1738 def simm9_offset_fb8 : Operand<i64> {
1739 let ParserMatchClass = SImm9OffsetFB8Operand;
1741 def simm9_offset_fb16 : Operand<i64> {
1742 let ParserMatchClass = SImm9OffsetFB16Operand;
1744 def simm9_offset_fb32 : Operand<i64> {
1745 let ParserMatchClass = SImm9OffsetFB32Operand;
1747 def simm9_offset_fb64 : Operand<i64> {
1748 let ParserMatchClass = SImm9OffsetFB64Operand;
1750 def simm9_offset_fb128 : Operand<i64> {
1751 let ParserMatchClass = SImm9OffsetFB128Operand;
1754 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1755 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1756 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1757 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1758 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1759 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1760 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1761 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1762 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1763 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1764 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1765 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1766 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1767 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1770 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1771 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1772 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1773 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1775 // load sign-extended half-word
1777 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1779 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1781 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1783 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1785 // load sign-extended byte
1787 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1789 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1791 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1793 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1795 // load sign-extended word
1797 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1799 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1801 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1802 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1803 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1804 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1805 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1806 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1807 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1808 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1809 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1810 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1811 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1812 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1813 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1814 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1815 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1818 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1819 [(AArch64Prefetch imm:$Rt,
1820 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1823 // (unscaled immediate, unprivileged)
1824 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1825 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1827 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1828 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1830 // load sign-extended half-word
1831 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1832 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1834 // load sign-extended byte
1835 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1836 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1838 // load sign-extended word
1839 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1842 // (immediate pre-indexed)
1843 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1844 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1845 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1846 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1847 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1848 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1849 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1851 // load sign-extended half-word
1852 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1853 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1855 // load sign-extended byte
1856 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1857 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1859 // load zero-extended byte
1860 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1861 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1863 // load sign-extended word
1864 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1867 // (immediate post-indexed)
1868 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1869 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1870 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1871 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1872 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1873 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1874 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1876 // load sign-extended half-word
1877 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1878 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1880 // load sign-extended byte
1881 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1882 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1884 // load zero-extended byte
1885 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1886 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1888 // load sign-extended word
1889 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1891 //===----------------------------------------------------------------------===//
1892 // Store instructions.
1893 //===----------------------------------------------------------------------===//
1895 // Pair (indexed, offset)
1896 // FIXME: Use dedicated range-checked addressing mode operand here.
1897 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1898 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1899 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1900 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1901 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1903 // Pair (pre-indexed)
1904 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1905 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1906 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1907 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1908 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1910 // Pair (pre-indexed)
1911 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1912 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1913 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1914 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1915 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1917 // Pair (no allocate)
1918 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1919 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1920 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1921 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1922 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1925 // (Register offset)
1928 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1929 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1930 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1931 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1935 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1936 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1937 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1938 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1939 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1941 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1942 Instruction STRW, Instruction STRX> {
1944 def : Pat<(storeop GPR64:$Rt,
1945 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1946 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1947 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1949 def : Pat<(storeop GPR64:$Rt,
1950 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1951 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1952 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1955 let AddedComplexity = 10 in {
1957 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1958 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1959 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1962 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1963 Instruction STRW, Instruction STRX> {
1964 def : Pat<(store (VecTy FPR:$Rt),
1965 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1966 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1968 def : Pat<(store (VecTy FPR:$Rt),
1969 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1970 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1973 let AddedComplexity = 10 in {
1974 // Match all store 64 bits width whose type is compatible with FPR64
1975 let Predicates = [IsLE] in {
1976 // We must use ST1 to store vectors in big-endian.
1977 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1978 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1979 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1980 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1981 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1984 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1985 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1987 // Match all store 128 bits width whose type is compatible with FPR128
1988 let Predicates = [IsLE] in {
1989 // We must use ST1 to store vectors in big-endian.
1990 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1991 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1992 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1993 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1994 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1995 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1996 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
1998 } // AddedComplexity = 10
2000 // Match stores from lane 0 to the appropriate subreg's store.
2001 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
2002 ValueType VecTy, ValueType STy,
2003 SubRegIndex SubRegIdx,
2004 Instruction STRW, Instruction STRX> {
2006 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2007 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
2008 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2009 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
2011 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2012 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
2013 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2014 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2017 let AddedComplexity = 19 in {
2018 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2019 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
2020 defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
2021 defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
2022 defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
2023 defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
2024 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
2028 // (unsigned immediate)
2029 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
2031 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2032 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
2034 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2035 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
2037 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
2038 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
2039 [(store (f16 FPR16:$Rt),
2040 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
2041 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
2042 [(store (f32 FPR32:$Rt),
2043 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2044 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
2045 [(store (f64 FPR64:$Rt),
2046 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2047 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
2049 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
2050 [(truncstorei16 GPR32:$Rt,
2051 (am_indexed16 GPR64sp:$Rn,
2052 uimm12s2:$offset))]>;
2053 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
2054 [(truncstorei8 GPR32:$Rt,
2055 (am_indexed8 GPR64sp:$Rn,
2056 uimm12s1:$offset))]>;
2058 // Match all store 64 bits width whose type is compatible with FPR64
2059 let AddedComplexity = 10 in {
2060 let Predicates = [IsLE] in {
2061 // We must use ST1 to store vectors in big-endian.
2062 def : Pat<(store (v2f32 FPR64:$Rt),
2063 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2064 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2065 def : Pat<(store (v8i8 FPR64:$Rt),
2066 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2067 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2068 def : Pat<(store (v4i16 FPR64:$Rt),
2069 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2070 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2071 def : Pat<(store (v2i32 FPR64:$Rt),
2072 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2073 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2074 def : Pat<(store (v4f16 FPR64:$Rt),
2075 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2076 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2078 def : Pat<(store (v1f64 FPR64:$Rt),
2079 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2080 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2081 def : Pat<(store (v1i64 FPR64:$Rt),
2082 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2083 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2085 // Match all store 128 bits width whose type is compatible with FPR128
2086 let Predicates = [IsLE] in {
2087 // We must use ST1 to store vectors in big-endian.
2088 def : Pat<(store (v4f32 FPR128:$Rt),
2089 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2090 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2091 def : Pat<(store (v2f64 FPR128:$Rt),
2092 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2093 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2094 def : Pat<(store (v16i8 FPR128:$Rt),
2095 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2096 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2097 def : Pat<(store (v8i16 FPR128:$Rt),
2098 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2099 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2100 def : Pat<(store (v4i32 FPR128:$Rt),
2101 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2102 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2103 def : Pat<(store (v2i64 FPR128:$Rt),
2104 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2105 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2106 def : Pat<(store (v8f16 FPR128:$Rt),
2107 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2108 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2110 def : Pat<(store (f128 FPR128:$Rt),
2111 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2112 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2115 def : Pat<(truncstorei32 GPR64:$Rt,
2116 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
2117 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2118 def : Pat<(truncstorei16 GPR64:$Rt,
2119 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2120 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
2121 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
2122 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
2124 } // AddedComplexity = 10
2127 // (unscaled immediate)
2128 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2130 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2131 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2133 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2134 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2136 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2137 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2138 [(store (f16 FPR16:$Rt),
2139 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2140 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2141 [(store (f32 FPR32:$Rt),
2142 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2143 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2144 [(store (f64 FPR64:$Rt),
2145 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2146 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2147 [(store (f128 FPR128:$Rt),
2148 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2149 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2150 [(truncstorei16 GPR32:$Rt,
2151 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2152 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2153 [(truncstorei8 GPR32:$Rt,
2154 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2156 // Match all store 64 bits width whose type is compatible with FPR64
2157 let Predicates = [IsLE] in {
2158 // We must use ST1 to store vectors in big-endian.
2159 def : Pat<(store (v2f32 FPR64:$Rt),
2160 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2161 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2162 def : Pat<(store (v8i8 FPR64:$Rt),
2163 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2164 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2165 def : Pat<(store (v4i16 FPR64:$Rt),
2166 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2167 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2168 def : Pat<(store (v2i32 FPR64:$Rt),
2169 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2170 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2171 def : Pat<(store (v4f16 FPR64:$Rt),
2172 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2173 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2175 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2176 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2177 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2178 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2180 // Match all store 128 bits width whose type is compatible with FPR128
2181 let Predicates = [IsLE] in {
2182 // We must use ST1 to store vectors in big-endian.
2183 def : Pat<(store (v4f32 FPR128:$Rt),
2184 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2185 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2186 def : Pat<(store (v2f64 FPR128:$Rt),
2187 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2188 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2189 def : Pat<(store (v16i8 FPR128:$Rt),
2190 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2191 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2192 def : Pat<(store (v8i16 FPR128:$Rt),
2193 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2194 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2195 def : Pat<(store (v4i32 FPR128:$Rt),
2196 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2197 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2198 def : Pat<(store (v2i64 FPR128:$Rt),
2199 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2200 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2201 def : Pat<(store (v2f64 FPR128:$Rt),
2202 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2203 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2204 def : Pat<(store (v8f16 FPR128:$Rt),
2205 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2206 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2209 // unscaled i64 truncating stores
2210 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2211 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2212 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2213 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2214 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2215 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2218 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2219 def : InstAlias<"str $Rt, [$Rn, $offset]",
2220 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2221 def : InstAlias<"str $Rt, [$Rn, $offset]",
2222 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2223 def : InstAlias<"str $Rt, [$Rn, $offset]",
2224 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2225 def : InstAlias<"str $Rt, [$Rn, $offset]",
2226 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2227 def : InstAlias<"str $Rt, [$Rn, $offset]",
2228 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2229 def : InstAlias<"str $Rt, [$Rn, $offset]",
2230 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2231 def : InstAlias<"str $Rt, [$Rn, $offset]",
2232 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2234 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2235 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2236 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2237 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2240 // (unscaled immediate, unprivileged)
2241 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2242 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2244 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2245 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2248 // (immediate pre-indexed)
2249 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2250 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2251 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2252 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2253 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2254 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2255 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2257 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2258 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2261 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2262 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2264 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2265 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2267 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2268 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2271 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2272 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2273 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2274 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2275 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2276 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2277 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2278 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2279 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2280 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2281 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2282 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2283 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2284 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2286 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2287 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2288 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2289 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2290 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2291 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2292 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2293 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2294 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2295 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2296 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2297 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2298 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2299 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2302 // (immediate post-indexed)
2303 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2304 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2305 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2306 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2307 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2308 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2309 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2311 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2312 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2315 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2316 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2318 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2319 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2321 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2322 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2325 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2326 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2327 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2328 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2329 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2330 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2331 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2332 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2333 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2334 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2335 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2336 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2337 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2338 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2340 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2341 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2342 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2343 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2344 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2345 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2346 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2347 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2348 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2349 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2350 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2351 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2352 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2353 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2355 //===----------------------------------------------------------------------===//
2356 // Load/store exclusive instructions.
2357 //===----------------------------------------------------------------------===//
2359 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2360 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2361 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2362 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2364 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2365 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2366 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2367 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2369 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2370 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2371 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2372 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2374 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2375 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2376 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2377 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2379 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2380 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2381 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2382 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2384 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2385 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2386 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2387 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2389 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2390 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2392 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2393 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2395 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2396 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2398 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2399 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2401 let Predicates = [HasV8_1a] in {
2402 // v8.1a "Limited Order Region" extension load-acquire instructions
2403 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2404 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
2405 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2406 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
2408 // v8.1a "Limited Order Region" extension store-release instructions
2409 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
2410 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
2411 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2412 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
2415 //===----------------------------------------------------------------------===//
2416 // Scaled floating point to integer conversion instructions.
2417 //===----------------------------------------------------------------------===//
2419 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2420 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2421 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2422 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2423 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2424 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2425 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2426 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2427 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2428 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2429 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2430 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2431 let isCodeGenOnly = 1 in {
2432 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2433 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2434 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2435 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2438 //===----------------------------------------------------------------------===//
2439 // Scaled integer to floating point conversion instructions.
2440 //===----------------------------------------------------------------------===//
2442 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2443 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2445 //===----------------------------------------------------------------------===//
2446 // Unscaled integer to floating point conversion instruction.
2447 //===----------------------------------------------------------------------===//
2449 defm FMOV : UnscaledConversion<"fmov">;
2451 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
2452 let isReMaterializable = 1, isCodeGenOnly = 1 in {
2453 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
2454 PseudoInstExpansion<(FMOVWSr FPR32:$Rd, WZR)>,
2456 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
2457 PseudoInstExpansion<(FMOVXDr FPR64:$Rd, XZR)>,
2461 //===----------------------------------------------------------------------===//
2462 // Floating point conversion instruction.
2463 //===----------------------------------------------------------------------===//
2465 defm FCVT : FPConversion<"fcvt">;
2467 //===----------------------------------------------------------------------===//
2468 // Floating point single operand instructions.
2469 //===----------------------------------------------------------------------===//
2471 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2472 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2473 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2474 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2475 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2476 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2477 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2478 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2480 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2481 (FRINTNDr FPR64:$Rn)>;
2483 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2484 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2485 // <rdar://problem/13715968>
2486 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2487 let hasSideEffects = 1 in {
2488 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2491 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2493 let SchedRW = [WriteFDiv] in {
2494 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2497 //===----------------------------------------------------------------------===//
2498 // Floating point two operand instructions.
2499 //===----------------------------------------------------------------------===//
2501 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2502 let SchedRW = [WriteFDiv] in {
2503 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2505 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>;
2506 defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>;
2507 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>;
2508 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;
2509 let SchedRW = [WriteFMul] in {
2510 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2511 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2513 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2515 def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2516 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2517 def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2518 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2519 def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2520 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2521 def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2522 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2524 //===----------------------------------------------------------------------===//
2525 // Floating point three operand instructions.
2526 //===----------------------------------------------------------------------===//
2528 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2529 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2530 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2531 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2532 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2533 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2534 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2536 // The following def pats catch the case where the LHS of an FMA is negated.
2537 // The TriOpFrag above catches the case where the middle operand is negated.
2539 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2540 // the NEON variant.
2541 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2542 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2544 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2545 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2547 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2549 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2550 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2552 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2553 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2555 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2556 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2558 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2559 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2561 //===----------------------------------------------------------------------===//
2562 // Floating point comparison instructions.
2563 //===----------------------------------------------------------------------===//
2565 defm FCMPE : FPComparison<1, "fcmpe">;
2566 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2568 //===----------------------------------------------------------------------===//
2569 // Floating point conditional comparison instructions.
2570 //===----------------------------------------------------------------------===//
2572 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2573 defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>;
2575 //===----------------------------------------------------------------------===//
2576 // Floating point conditional select instruction.
2577 //===----------------------------------------------------------------------===//
2579 defm FCSEL : FPCondSelect<"fcsel">;
2581 // CSEL instructions providing f128 types need to be handled by a
2582 // pseudo-instruction since the eventual code will need to introduce basic
2583 // blocks and control flow.
2584 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2585 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2586 [(set (f128 FPR128:$Rd),
2587 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2588 (i32 imm:$cond), NZCV))]> {
2590 let usesCustomInserter = 1;
2594 //===----------------------------------------------------------------------===//
2595 // Floating point immediate move.
2596 //===----------------------------------------------------------------------===//
2598 let isReMaterializable = 1 in {
2599 defm FMOV : FPMoveImmediate<"fmov">;
2602 //===----------------------------------------------------------------------===//
2603 // Advanced SIMD two vector instructions.
2604 //===----------------------------------------------------------------------===//
2606 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2607 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2608 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2609 (ABSv8i8 V64:$src)>;
2610 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2611 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2612 (ABSv4i16 V64:$src)>;
2613 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2614 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2615 (ABSv2i32 V64:$src)>;
2616 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2617 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2618 (ABSv16i8 V128:$src)>;
2619 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2620 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2621 (ABSv8i16 V128:$src)>;
2622 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2623 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2624 (ABSv4i32 V128:$src)>;
2625 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2626 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2627 (ABSv2i64 V128:$src)>;
2629 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2630 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2631 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2632 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2633 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2634 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2635 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2636 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2637 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2639 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2640 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2641 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2642 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2643 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2644 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2645 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2646 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2647 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2648 (FCVTLv4i16 V64:$Rn)>;
2649 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2651 (FCVTLv8i16 V128:$Rn)>;
2652 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2653 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2655 (FCVTLv4i32 V128:$Rn)>;
2657 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2658 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2660 (FCVTLv8i16 V128:$Rn)>;
2662 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2663 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2664 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2665 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2666 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2667 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2668 (FCVTNv4i16 V128:$Rn)>;
2669 def : Pat<(concat_vectors V64:$Rd,
2670 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2671 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2672 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2673 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2674 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2675 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2676 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2677 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2678 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2679 int_aarch64_neon_fcvtxn>;
2680 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2681 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2682 let isCodeGenOnly = 1 in {
2683 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2684 int_aarch64_neon_fcvtzs>;
2685 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2686 int_aarch64_neon_fcvtzu>;
2688 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2689 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2690 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2691 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2692 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2693 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2694 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2695 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2696 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2697 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2698 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2699 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2700 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2701 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2702 // Aliases for MVN -> NOT.
2703 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2704 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2705 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2706 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2708 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2709 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2710 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2711 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2712 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2713 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2714 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2716 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2717 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2718 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2719 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2720 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2721 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2722 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2723 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2725 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2726 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2727 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2728 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2729 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2731 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2732 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2733 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2734 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2735 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2736 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2737 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2738 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2739 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2740 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2741 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2742 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2743 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2744 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2745 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2746 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2747 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2748 int_aarch64_neon_uaddlp>;
2749 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2750 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2751 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2752 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2753 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2754 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2756 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2757 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2758 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2759 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2760 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2761 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2763 // Patterns for vector long shift (by element width). These need to match all
2764 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2766 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2767 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2768 (SHLLv8i8 V64:$Rn)>;
2769 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2770 (SHLLv16i8 V128:$Rn)>;
2771 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2772 (SHLLv4i16 V64:$Rn)>;
2773 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2774 (SHLLv8i16 V128:$Rn)>;
2775 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2776 (SHLLv2i32 V64:$Rn)>;
2777 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2778 (SHLLv4i32 V128:$Rn)>;
2781 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2782 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2783 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2785 //===----------------------------------------------------------------------===//
2786 // Advanced SIMD three vector instructions.
2787 //===----------------------------------------------------------------------===//
2789 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2790 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2791 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2792 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2793 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2794 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2795 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2796 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2797 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2798 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2799 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2800 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2801 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2802 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2803 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2804 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2805 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2806 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2807 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", fmaxnum>;
2808 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2809 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", fmaxnan>;
2810 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2811 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", fminnum>;
2812 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2813 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", fminnan>;
2815 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2816 // instruction expects the addend first, while the fma intrinsic puts it last.
2817 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2818 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2819 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2820 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2822 // The following def pats catch the case where the LHS of an FMA is negated.
2823 // The TriOpFrag above catches the case where the middle operand is negated.
2824 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2825 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2827 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2828 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2830 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2831 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2833 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2834 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2835 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2836 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2837 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2838 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2839 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2840 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2841 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2842 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2843 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2844 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2845 TriOpFrag<(add node:$LHS, (sabsdiff node:$MHS, node:$RHS))> >;
2846 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", sabsdiff>;
2847 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2848 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2849 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2850 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", smax>;
2851 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2852 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>;
2853 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2854 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2855 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2856 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2857 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2858 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2859 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2860 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2861 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2862 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2863 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2864 TriOpFrag<(add node:$LHS, (uabsdiff node:$MHS, node:$RHS))> >;
2865 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", uabsdiff>;
2866 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2867 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2868 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2869 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", umax>;
2870 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2871 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", umin>;
2872 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2873 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2874 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2875 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2876 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2877 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2878 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2879 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
2880 int_aarch64_neon_sqadd>;
2881 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
2882 int_aarch64_neon_sqsub>;
2884 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2885 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2886 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2887 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2888 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2889 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2890 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2891 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2892 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2893 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2894 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2897 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2898 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2899 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2900 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2901 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2902 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2903 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2904 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2906 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2907 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2908 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2909 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2910 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2911 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2912 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2913 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2915 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2916 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2917 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2918 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2919 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2920 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2921 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2922 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2924 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2925 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2926 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2927 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2928 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2929 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2930 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2931 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2933 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2934 "|cmls.8b\t$dst, $src1, $src2}",
2935 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2936 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2937 "|cmls.16b\t$dst, $src1, $src2}",
2938 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2939 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2940 "|cmls.4h\t$dst, $src1, $src2}",
2941 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2942 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2943 "|cmls.8h\t$dst, $src1, $src2}",
2944 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2945 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2946 "|cmls.2s\t$dst, $src1, $src2}",
2947 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2948 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2949 "|cmls.4s\t$dst, $src1, $src2}",
2950 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2951 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2952 "|cmls.2d\t$dst, $src1, $src2}",
2953 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2955 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2956 "|cmlo.8b\t$dst, $src1, $src2}",
2957 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2958 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2959 "|cmlo.16b\t$dst, $src1, $src2}",
2960 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2961 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2962 "|cmlo.4h\t$dst, $src1, $src2}",
2963 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2964 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2965 "|cmlo.8h\t$dst, $src1, $src2}",
2966 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2967 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2968 "|cmlo.2s\t$dst, $src1, $src2}",
2969 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2970 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2971 "|cmlo.4s\t$dst, $src1, $src2}",
2972 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2973 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2974 "|cmlo.2d\t$dst, $src1, $src2}",
2975 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2977 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2978 "|cmle.8b\t$dst, $src1, $src2}",
2979 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2980 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2981 "|cmle.16b\t$dst, $src1, $src2}",
2982 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2983 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2984 "|cmle.4h\t$dst, $src1, $src2}",
2985 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2986 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2987 "|cmle.8h\t$dst, $src1, $src2}",
2988 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2989 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2990 "|cmle.2s\t$dst, $src1, $src2}",
2991 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2992 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2993 "|cmle.4s\t$dst, $src1, $src2}",
2994 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2995 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2996 "|cmle.2d\t$dst, $src1, $src2}",
2997 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2999 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
3000 "|cmlt.8b\t$dst, $src1, $src2}",
3001 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3002 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
3003 "|cmlt.16b\t$dst, $src1, $src2}",
3004 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3005 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
3006 "|cmlt.4h\t$dst, $src1, $src2}",
3007 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3008 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
3009 "|cmlt.8h\t$dst, $src1, $src2}",
3010 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3011 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
3012 "|cmlt.2s\t$dst, $src1, $src2}",
3013 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3014 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
3015 "|cmlt.4s\t$dst, $src1, $src2}",
3016 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3017 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
3018 "|cmlt.2d\t$dst, $src1, $src2}",
3019 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3021 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
3022 "|fcmle.2s\t$dst, $src1, $src2}",
3023 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3024 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
3025 "|fcmle.4s\t$dst, $src1, $src2}",
3026 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3027 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
3028 "|fcmle.2d\t$dst, $src1, $src2}",
3029 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3031 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
3032 "|fcmlt.2s\t$dst, $src1, $src2}",
3033 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3034 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
3035 "|fcmlt.4s\t$dst, $src1, $src2}",
3036 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3037 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
3038 "|fcmlt.2d\t$dst, $src1, $src2}",
3039 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3041 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
3042 "|facle.2s\t$dst, $src1, $src2}",
3043 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3044 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
3045 "|facle.4s\t$dst, $src1, $src2}",
3046 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3047 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
3048 "|facle.2d\t$dst, $src1, $src2}",
3049 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3051 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
3052 "|faclt.2s\t$dst, $src1, $src2}",
3053 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3054 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
3055 "|faclt.4s\t$dst, $src1, $src2}",
3056 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3057 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
3058 "|faclt.2d\t$dst, $src1, $src2}",
3059 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3061 //===----------------------------------------------------------------------===//
3062 // Advanced SIMD three scalar instructions.
3063 //===----------------------------------------------------------------------===//
3065 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
3066 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
3067 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
3068 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
3069 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
3070 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
3071 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
3072 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
3073 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3074 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
3075 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
3076 int_aarch64_neon_facge>;
3077 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
3078 int_aarch64_neon_facgt>;
3079 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
3080 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
3081 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
3082 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
3083 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
3084 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
3085 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
3086 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
3087 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
3088 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
3089 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
3090 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
3091 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
3092 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
3093 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
3094 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
3095 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
3096 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
3097 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
3098 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
3099 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
3100 let Predicates = [HasV8_1a] in {
3101 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
3102 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
3103 def : Pat<(i32 (int_aarch64_neon_sqadd
3105 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3106 (i32 FPR32:$Rm))))),
3107 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3108 def : Pat<(i32 (int_aarch64_neon_sqsub
3110 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3111 (i32 FPR32:$Rm))))),
3112 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3115 def : InstAlias<"cmls $dst, $src1, $src2",
3116 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3117 def : InstAlias<"cmle $dst, $src1, $src2",
3118 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3119 def : InstAlias<"cmlo $dst, $src1, $src2",
3120 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3121 def : InstAlias<"cmlt $dst, $src1, $src2",
3122 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3123 def : InstAlias<"fcmle $dst, $src1, $src2",
3124 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3125 def : InstAlias<"fcmle $dst, $src1, $src2",
3126 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3127 def : InstAlias<"fcmlt $dst, $src1, $src2",
3128 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3129 def : InstAlias<"fcmlt $dst, $src1, $src2",
3130 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3131 def : InstAlias<"facle $dst, $src1, $src2",
3132 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3133 def : InstAlias<"facle $dst, $src1, $src2",
3134 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3135 def : InstAlias<"faclt $dst, $src1, $src2",
3136 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3137 def : InstAlias<"faclt $dst, $src1, $src2",
3138 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3140 //===----------------------------------------------------------------------===//
3141 // Advanced SIMD three scalar instructions (mixed operands).
3142 //===----------------------------------------------------------------------===//
3143 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3144 int_aarch64_neon_sqdmulls_scalar>;
3145 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
3146 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3148 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3149 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3150 (i32 FPR32:$Rm))))),
3151 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3152 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3153 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3154 (i32 FPR32:$Rm))))),
3155 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3157 //===----------------------------------------------------------------------===//
3158 // Advanced SIMD two scalar instructions.
3159 //===----------------------------------------------------------------------===//
3161 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
3162 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3163 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3164 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3165 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3166 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3167 defm FCMEQ : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3168 defm FCMGE : SIMDFPCmpTwoScalar<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3169 defm FCMGT : SIMDFPCmpTwoScalar<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3170 defm FCMLE : SIMDFPCmpTwoScalar<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3171 defm FCMLT : SIMDFPCmpTwoScalar<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3172 defm FCVTAS : SIMDFPTwoScalar< 0, 0, 0b11100, "fcvtas">;
3173 defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau">;
3174 defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms">;
3175 defm FCVTMU : SIMDFPTwoScalar< 1, 0, 0b11011, "fcvtmu">;
3176 defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns">;
3177 defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu">;
3178 defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps">;
3179 defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu">;
3180 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3181 defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">;
3182 defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">;
3183 defm FRECPE : SIMDFPTwoScalar< 0, 1, 0b11101, "frecpe">;
3184 defm FRECPX : SIMDFPTwoScalar< 0, 1, 0b11111, "frecpx">;
3185 defm FRSQRTE : SIMDFPTwoScalar< 1, 1, 0b11101, "frsqrte">;
3186 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3187 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3188 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3189 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3190 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3191 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3192 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3193 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3194 int_aarch64_neon_suqadd>;
3195 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3196 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3197 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3198 int_aarch64_neon_usqadd>;
3200 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3202 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3203 (FCVTASv1i64 FPR64:$Rn)>;
3204 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3205 (FCVTAUv1i64 FPR64:$Rn)>;
3206 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3207 (FCVTMSv1i64 FPR64:$Rn)>;
3208 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3209 (FCVTMUv1i64 FPR64:$Rn)>;
3210 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3211 (FCVTNSv1i64 FPR64:$Rn)>;
3212 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3213 (FCVTNUv1i64 FPR64:$Rn)>;
3214 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3215 (FCVTPSv1i64 FPR64:$Rn)>;
3216 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3217 (FCVTPUv1i64 FPR64:$Rn)>;
3219 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3220 (FRECPEv1i32 FPR32:$Rn)>;
3221 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3222 (FRECPEv1i64 FPR64:$Rn)>;
3223 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3224 (FRECPEv1i64 FPR64:$Rn)>;
3226 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3227 (FRECPXv1i32 FPR32:$Rn)>;
3228 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3229 (FRECPXv1i64 FPR64:$Rn)>;
3231 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3232 (FRSQRTEv1i32 FPR32:$Rn)>;
3233 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3234 (FRSQRTEv1i64 FPR64:$Rn)>;
3235 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3236 (FRSQRTEv1i64 FPR64:$Rn)>;
3238 // If an integer is about to be converted to a floating point value,
3239 // just load it on the floating point unit.
3240 // Here are the patterns for 8 and 16-bits to float.
3242 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3243 SDPatternOperator loadop, Instruction UCVTF,
3244 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3246 def : Pat<(DstTy (uint_to_fp (SrcTy
3247 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3248 ro.Wext:$extend))))),
3249 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3250 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3253 def : Pat<(DstTy (uint_to_fp (SrcTy
3254 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3255 ro.Wext:$extend))))),
3256 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3257 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3261 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3262 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3263 def : Pat <(f32 (uint_to_fp (i32
3264 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3265 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3266 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3267 def : Pat <(f32 (uint_to_fp (i32
3268 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3269 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3270 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3271 // 16-bits -> float.
3272 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3273 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3274 def : Pat <(f32 (uint_to_fp (i32
3275 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3276 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3277 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3278 def : Pat <(f32 (uint_to_fp (i32
3279 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3280 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3281 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3282 // 32-bits are handled in target specific dag combine:
3283 // performIntToFpCombine.
3284 // 64-bits integer to 32-bits floating point, not possible with
3285 // UCVTF on floating point registers (both source and destination
3286 // must have the same size).
3288 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3289 // 8-bits -> double.
3290 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3291 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3292 def : Pat <(f64 (uint_to_fp (i32
3293 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3294 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3295 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3296 def : Pat <(f64 (uint_to_fp (i32
3297 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3298 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3299 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3300 // 16-bits -> double.
3301 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3302 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3303 def : Pat <(f64 (uint_to_fp (i32
3304 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3305 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3306 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3307 def : Pat <(f64 (uint_to_fp (i32
3308 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3309 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3310 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3311 // 32-bits -> double.
3312 defm : UIntToFPROLoadPat<f64, i32, load,
3313 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3314 def : Pat <(f64 (uint_to_fp (i32
3315 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3316 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3317 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3318 def : Pat <(f64 (uint_to_fp (i32
3319 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3320 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3321 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3322 // 64-bits -> double are handled in target specific dag combine:
3323 // performIntToFpCombine.
3325 //===----------------------------------------------------------------------===//
3326 // Advanced SIMD three different-sized vector instructions.
3327 //===----------------------------------------------------------------------===//
3329 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3330 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3331 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3332 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3333 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3334 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3336 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3338 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3339 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3340 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3341 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3342 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3343 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3344 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3345 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3346 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3347 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3348 int_aarch64_neon_sqadd>;
3349 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3350 int_aarch64_neon_sqsub>;
3351 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3352 int_aarch64_neon_sqdmull>;
3353 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3354 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3355 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3356 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3357 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3359 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3361 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3362 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3363 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3364 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3365 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3366 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3367 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3368 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3369 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3370 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3371 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3372 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3373 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3375 // Additional patterns for SMULL and UMULL
3376 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3377 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3378 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3379 (INST8B V64:$Rn, V64:$Rm)>;
3380 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3381 (INST4H V64:$Rn, V64:$Rm)>;
3382 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3383 (INST2S V64:$Rn, V64:$Rm)>;
3386 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3387 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3388 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3389 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3391 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3392 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3393 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3394 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3395 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3396 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3397 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3398 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3399 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3402 defm : Neon_mulacc_widen_patterns<
3403 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3404 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3405 defm : Neon_mulacc_widen_patterns<
3406 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3407 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3408 defm : Neon_mulacc_widen_patterns<
3409 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3410 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3411 defm : Neon_mulacc_widen_patterns<
3412 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3413 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3415 // Patterns for 64-bit pmull
3416 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3417 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3418 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3419 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3420 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3422 // CodeGen patterns for addhn and subhn instructions, which can actually be
3423 // written in LLVM IR without too much difficulty.
3426 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3427 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3428 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3430 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3431 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3433 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3434 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3435 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3437 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3438 V128:$Rn, V128:$Rm)>;
3439 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3440 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3442 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3443 V128:$Rn, V128:$Rm)>;
3444 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3445 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3447 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3448 V128:$Rn, V128:$Rm)>;
3451 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3452 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3453 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3455 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3456 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3458 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3459 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3460 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3462 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3463 V128:$Rn, V128:$Rm)>;
3464 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3465 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3467 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3468 V128:$Rn, V128:$Rm)>;
3469 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3470 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3472 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3473 V128:$Rn, V128:$Rm)>;
3475 //----------------------------------------------------------------------------
3476 // AdvSIMD bitwise extract from vector instruction.
3477 //----------------------------------------------------------------------------
3479 defm EXT : SIMDBitwiseExtract<"ext">;
3481 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3482 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3483 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3484 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3485 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3486 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3487 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3488 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3489 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3490 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3491 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3492 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3493 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3494 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3495 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3496 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3497 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3498 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3499 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3500 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3502 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3504 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3505 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3506 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3507 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3508 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3509 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3510 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3511 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3512 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3513 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3514 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3515 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3516 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3517 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3520 //----------------------------------------------------------------------------
3521 // AdvSIMD zip vector
3522 //----------------------------------------------------------------------------
3524 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3525 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3526 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3527 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3528 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3529 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3531 //----------------------------------------------------------------------------
3532 // AdvSIMD TBL/TBX instructions
3533 //----------------------------------------------------------------------------
3535 defm TBL : SIMDTableLookup< 0, "tbl">;
3536 defm TBX : SIMDTableLookupTied<1, "tbx">;
3538 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3539 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3540 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3541 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3543 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3544 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3545 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3546 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3547 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3548 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3551 //----------------------------------------------------------------------------
3552 // AdvSIMD scalar CPY instruction
3553 //----------------------------------------------------------------------------
3555 defm CPY : SIMDScalarCPY<"cpy">;
3557 //----------------------------------------------------------------------------
3558 // AdvSIMD scalar pairwise instructions
3559 //----------------------------------------------------------------------------
3561 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3562 defm FADDP : SIMDFPPairwiseScalar<1, 0, 0b01101, "faddp">;
3563 defm FMAXNMP : SIMDFPPairwiseScalar<1, 0, 0b01100, "fmaxnmp">;
3564 defm FMAXP : SIMDFPPairwiseScalar<1, 0, 0b01111, "fmaxp">;
3565 defm FMINNMP : SIMDFPPairwiseScalar<1, 1, 0b01100, "fminnmp">;
3566 defm FMINP : SIMDFPPairwiseScalar<1, 1, 0b01111, "fminp">;
3567 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
3568 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3569 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),
3570 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3571 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3572 (FADDPv2i32p V64:$Rn)>;
3573 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3574 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3575 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3576 (FADDPv2i64p V128:$Rn)>;
3577 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3578 (FMAXNMPv2i32p V64:$Rn)>;
3579 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3580 (FMAXNMPv2i64p V128:$Rn)>;
3581 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3582 (FMAXPv2i32p V64:$Rn)>;
3583 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3584 (FMAXPv2i64p V128:$Rn)>;
3585 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3586 (FMINNMPv2i32p V64:$Rn)>;
3587 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3588 (FMINNMPv2i64p V128:$Rn)>;
3589 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3590 (FMINPv2i32p V64:$Rn)>;
3591 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3592 (FMINPv2i64p V128:$Rn)>;
3594 //----------------------------------------------------------------------------
3595 // AdvSIMD INS/DUP instructions
3596 //----------------------------------------------------------------------------
3598 def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>;
3599 def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>;
3600 def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>;
3601 def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>;
3602 def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>;
3603 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;
3604 def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>;
3606 def DUPv2i64lane : SIMDDup64FromElement;
3607 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3608 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3609 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3610 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3611 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3612 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3614 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3615 (v2f32 (DUPv2i32lane
3616 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3618 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3619 (v4f32 (DUPv4i32lane
3620 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3622 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3623 (v2f64 (DUPv2i64lane
3624 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3626 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3627 (v4f16 (DUPv4i16lane
3628 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3630 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3631 (v8f16 (DUPv8i16lane
3632 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3635 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3636 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3637 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3638 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3640 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3641 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3642 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3643 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3644 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3645 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3647 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3648 // instruction even if the types don't match: we just have to remap the lane
3649 // carefully. N.b. this trick only applies to truncations.
3650 def VecIndex_x2 : SDNodeXForm<imm, [{
3651 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64);
3653 def VecIndex_x4 : SDNodeXForm<imm, [{
3654 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64);
3656 def VecIndex_x8 : SDNodeXForm<imm, [{
3657 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64);
3660 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3661 ValueType Src128VT, ValueType ScalVT,
3662 Instruction DUP, SDNodeXForm IdxXFORM> {
3663 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3665 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3667 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3669 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3672 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3673 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3674 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3676 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3677 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3678 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3680 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3681 SDNodeXForm IdxXFORM> {
3682 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3684 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3686 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3688 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3691 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3692 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3693 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3695 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3696 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3697 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3699 // SMOV and UMOV definitions, with some extra patterns for convenience
3703 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3704 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3705 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3706 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3707 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3708 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3709 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3710 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3711 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3712 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3713 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3714 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3716 // Extracting i8 or i16 elements will have the zero-extend transformed to
3717 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3718 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3719 // bits of the destination register.
3720 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3722 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3723 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3725 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3729 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3730 (SUBREG_TO_REG (i32 0),
3731 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3732 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3733 (SUBREG_TO_REG (i32 0),
3734 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3736 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3737 (SUBREG_TO_REG (i32 0),
3738 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3739 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3740 (SUBREG_TO_REG (i32 0),
3741 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3743 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3744 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3745 (i32 FPR32:$Rn), ssub))>;
3746 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3747 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3748 (i32 FPR32:$Rn), ssub))>;
3749 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3750 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3751 (i64 FPR64:$Rn), dsub))>;
3753 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3754 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3755 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3756 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3757 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3758 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3760 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3761 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3764 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3766 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3770 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3771 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3773 V128:$Rn, VectorIndexH:$imm,
3774 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3777 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3778 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3781 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3783 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3786 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3787 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3789 V128:$Rn, VectorIndexS:$imm,
3790 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3792 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3793 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3795 V128:$Rn, VectorIndexD:$imm,
3796 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3799 // Copy an element at a constant index in one vector into a constant indexed
3800 // element of another.
3801 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3802 // index type and INS extension
3803 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3804 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3805 VectorIndexB:$idx2)),
3807 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3809 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3810 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3811 VectorIndexH:$idx2)),
3813 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3815 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3816 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3817 VectorIndexS:$idx2)),
3819 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3821 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3822 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3823 VectorIndexD:$idx2)),
3825 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3828 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3829 ValueType VTScal, Instruction INS> {
3830 def : Pat<(VT128 (vector_insert V128:$src,
3831 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3833 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3835 def : Pat<(VT128 (vector_insert V128:$src,
3836 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3838 (INS V128:$src, imm:$Immd,
3839 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3841 def : Pat<(VT64 (vector_insert V64:$src,
3842 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3844 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3845 imm:$Immd, V128:$Rn, imm:$Immn),
3848 def : Pat<(VT64 (vector_insert V64:$src,
3849 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3852 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3853 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3857 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3858 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3859 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3862 // Floating point vector extractions are codegen'd as either a sequence of
3863 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
3864 // the lane number is anything other than zero.
3865 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3866 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3867 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3868 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3869 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3870 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3872 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3873 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
3874 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3875 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
3876 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3877 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
3879 // All concat_vectors operations are canonicalised to act on i64 vectors for
3880 // AArch64. In the general case we need an instruction, which had just as well be
3882 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3883 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3884 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3885 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3887 def : ConcatPat<v2i64, v1i64>;
3888 def : ConcatPat<v2f64, v1f64>;
3889 def : ConcatPat<v4i32, v2i32>;
3890 def : ConcatPat<v4f32, v2f32>;
3891 def : ConcatPat<v8i16, v4i16>;
3892 def : ConcatPat<v8f16, v4f16>;
3893 def : ConcatPat<v16i8, v8i8>;
3895 // If the high lanes are undef, though, we can just ignore them:
3896 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3897 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3898 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3900 def : ConcatUndefPat<v2i64, v1i64>;
3901 def : ConcatUndefPat<v2f64, v1f64>;
3902 def : ConcatUndefPat<v4i32, v2i32>;
3903 def : ConcatUndefPat<v4f32, v2f32>;
3904 def : ConcatUndefPat<v8i16, v4i16>;
3905 def : ConcatUndefPat<v16i8, v8i8>;
3907 //----------------------------------------------------------------------------
3908 // AdvSIMD across lanes instructions
3909 //----------------------------------------------------------------------------
3911 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3912 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3913 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3914 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3915 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3916 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3917 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3918 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3919 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3920 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3921 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3923 // Patterns for across-vector intrinsics, that have a node equivalent, that
3924 // returns a vector (with only the low lane defined) instead of a scalar.
3925 // In effect, opNode is the same as (scalar_to_vector (IntNode)).
3926 multiclass SIMDAcrossLanesIntrinsic<string baseOpc,
3927 SDPatternOperator opNode> {
3928 // If a lane instruction caught the vector_extract around opNode, we can
3929 // directly match the latter to the instruction.
3930 def : Pat<(v8i8 (opNode V64:$Rn)),
3931 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3932 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;
3933 def : Pat<(v16i8 (opNode V128:$Rn)),
3934 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3935 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;
3936 def : Pat<(v4i16 (opNode V64:$Rn)),
3937 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3938 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;
3939 def : Pat<(v8i16 (opNode V128:$Rn)),
3940 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3941 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;
3942 def : Pat<(v4i32 (opNode V128:$Rn)),
3943 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3944 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;
3947 // If none did, fallback to the explicit patterns, consuming the vector_extract.
3948 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
3949 (i32 0)), (i64 0))),
3950 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3951 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),
3953 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
3954 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3955 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),
3957 def : Pat<(i32 (vector_extract (insert_subvector undef,
3958 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))),
3959 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3960 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),
3962 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
3963 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3964 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),
3966 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
3967 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3968 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),
3973 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,
3974 SDPatternOperator opNode>
3975 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
3976 // If there is a sign extension after this intrinsic, consume it as smov already
3978 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
3979 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)),
3981 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3982 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3984 def : Pat<(i32 (sext_inreg (i32 (vector_extract
3985 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),
3987 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3988 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3990 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
3991 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)),
3993 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3994 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3996 def : Pat<(i32 (sext_inreg (i32 (vector_extract
3997 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),
3999 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4000 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4004 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
4005 SDPatternOperator opNode>
4006 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4007 // If there is a masking operation keeping only what has been actually
4008 // generated, consume it.
4009 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4010 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)),
4011 (i32 (EXTRACT_SUBREG
4012 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4013 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4015 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
4017 (i32 (EXTRACT_SUBREG
4018 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4019 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4021 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4022 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)),
4023 (i32 (EXTRACT_SUBREG
4024 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4025 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4027 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
4029 (i32 (EXTRACT_SUBREG
4030 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4031 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4035 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;
4036 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4037 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
4038 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4040 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;
4041 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4042 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
4043 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4045 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;
4046 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
4047 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
4049 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
4050 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
4051 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
4053 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;
4054 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
4055 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
4057 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
4058 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
4059 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
4061 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
4062 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4064 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4065 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4067 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4069 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4070 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4073 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4074 (i32 (EXTRACT_SUBREG
4075 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4076 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4078 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4079 (i32 (EXTRACT_SUBREG
4080 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4081 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4084 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4085 (i64 (EXTRACT_SUBREG
4086 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4087 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4091 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
4093 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4094 (i32 (EXTRACT_SUBREG
4095 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4096 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4098 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4099 (i32 (EXTRACT_SUBREG
4100 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4101 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4104 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4105 (i32 (EXTRACT_SUBREG
4106 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4107 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4109 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4110 (i32 (EXTRACT_SUBREG
4111 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4112 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4115 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4116 (i64 (EXTRACT_SUBREG
4117 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4118 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4122 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
4123 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
4125 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
4126 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
4127 (i64 (EXTRACT_SUBREG
4128 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4129 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
4131 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4132 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4133 (i64 (EXTRACT_SUBREG
4134 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4135 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4138 //------------------------------------------------------------------------------
4139 // AdvSIMD modified immediate instructions
4140 //------------------------------------------------------------------------------
4143 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4145 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4147 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4148 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4149 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4150 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4152 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4153 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4154 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4155 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4157 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4158 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4159 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4160 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4162 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4163 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4164 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4165 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4168 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
4170 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4171 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
4173 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4174 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
4176 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4180 // EDIT byte mask: scalar
4181 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4182 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4183 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4184 // The movi_edit node has the immediate value already encoded, so we use
4185 // a plain imm0_255 here.
4186 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4187 (MOVID imm0_255:$shift)>;
4189 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4190 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4191 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4192 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4194 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4195 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4196 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4197 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4199 // EDIT byte mask: 2d
4201 // The movi_edit node has the immediate value already encoded, so we use
4202 // a plain imm0_255 in the pattern
4203 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4204 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
4207 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4210 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4211 // Complexity is added to break a tie with a plain MOVI.
4212 let AddedComplexity = 1 in {
4213 def : Pat<(f32 fpimm0),
4214 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4216 def : Pat<(f64 fpimm0),
4217 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4221 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4222 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4223 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4224 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4226 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4227 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4228 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4229 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4231 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4232 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4234 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4235 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4237 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4238 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4239 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4240 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4242 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4243 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4244 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4245 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4247 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4248 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4249 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4250 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4251 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4252 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4253 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4254 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4256 // EDIT per word: 2s & 4s with MSL shifter
4257 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4258 [(set (v2i32 V64:$Rd),
4259 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4260 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4261 [(set (v4i32 V128:$Rd),
4262 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4264 // Per byte: 8b & 16b
4265 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4267 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4268 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4270 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4274 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4275 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4277 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4278 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4279 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4280 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4282 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4283 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4284 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4285 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4287 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4288 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4289 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4290 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4291 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4292 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4293 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4294 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4296 // EDIT per word: 2s & 4s with MSL shifter
4297 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4298 [(set (v2i32 V64:$Rd),
4299 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4300 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4301 [(set (v4i32 V128:$Rd),
4302 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4304 //----------------------------------------------------------------------------
4305 // AdvSIMD indexed element
4306 //----------------------------------------------------------------------------
4308 let hasSideEffects = 0 in {
4309 defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">;
4310 defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">;
4313 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4314 // instruction expects the addend first, while the intrinsic expects it last.
4316 // On the other hand, there are quite a few valid combinatorial options due to
4317 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4318 defm : SIMDFPIndexedTiedPatterns<"FMLA",
4319 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4320 defm : SIMDFPIndexedTiedPatterns<"FMLA",
4321 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4323 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4324 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4325 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4326 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4327 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4328 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4329 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4330 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4332 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4333 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4335 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4336 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4337 VectorIndexS:$idx))),
4338 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4339 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4340 (v2f32 (AArch64duplane32
4341 (v4f32 (insert_subvector undef,
4342 (v2f32 (fneg V64:$Rm)),
4344 VectorIndexS:$idx)))),
4345 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4346 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4347 VectorIndexS:$idx)>;
4348 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4349 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4350 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4351 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4353 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4355 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4356 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4357 VectorIndexS:$idx))),
4358 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4359 VectorIndexS:$idx)>;
4360 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4361 (v4f32 (AArch64duplane32
4362 (v4f32 (insert_subvector undef,
4363 (v2f32 (fneg V64:$Rm)),
4365 VectorIndexS:$idx)))),
4366 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4367 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4368 VectorIndexS:$idx)>;
4369 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4370 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4371 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4372 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4374 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4375 // (DUPLANE from 64-bit would be trivial).
4376 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4377 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4378 VectorIndexD:$idx))),
4380 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4381 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4382 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4383 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4384 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4386 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4387 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4388 (vector_extract (v4f32 (fneg V128:$Rm)),
4389 VectorIndexS:$idx))),
4390 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4391 V128:$Rm, VectorIndexS:$idx)>;
4392 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4393 (vector_extract (v4f32 (insert_subvector undef,
4394 (v2f32 (fneg V64:$Rm)),
4396 VectorIndexS:$idx))),
4397 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4398 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4400 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4401 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4402 (vector_extract (v2f64 (fneg V128:$Rm)),
4403 VectorIndexS:$idx))),
4404 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4405 V128:$Rm, VectorIndexS:$idx)>;
4408 defm : FMLSIndexedAfterNegPatterns<
4409 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4410 defm : FMLSIndexedAfterNegPatterns<
4411 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4413 defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4414 defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", fmul>;
4416 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4417 (FMULv2i32_indexed V64:$Rn,
4418 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4420 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4421 (FMULv4i32_indexed V128:$Rn,
4422 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4424 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4425 (FMULv2i64_indexed V128:$Rn,
4426 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4429 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4430 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4431 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4432 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4433 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4434 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4435 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4436 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4437 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4438 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4439 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4440 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4441 int_aarch64_neon_smull>;
4442 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4443 int_aarch64_neon_sqadd>;
4444 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4445 int_aarch64_neon_sqsub>;
4446 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
4447 int_aarch64_neon_sqadd>;
4448 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
4449 int_aarch64_neon_sqsub>;
4450 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4451 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4452 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4453 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4454 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4455 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4456 int_aarch64_neon_umull>;
4458 // A scalar sqdmull with the second operand being a vector lane can be
4459 // handled directly with the indexed instruction encoding.
4460 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4461 (vector_extract (v4i32 V128:$Vm),
4462 VectorIndexS:$idx)),
4463 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4465 //----------------------------------------------------------------------------
4466 // AdvSIMD scalar shift instructions
4467 //----------------------------------------------------------------------------
4468 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4469 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4470 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4471 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4472 // Codegen patterns for the above. We don't put these directly on the
4473 // instructions because TableGen's type inference can't handle the truth.
4474 // Having the same base pattern for fp <--> int totally freaks it out.
4475 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4476 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4477 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4478 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4479 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4480 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4481 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4482 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4483 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4485 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4486 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4488 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4489 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4490 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4491 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4492 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4493 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4494 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4495 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4496 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4497 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4499 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4500 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4502 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4504 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4505 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4506 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4507 int_aarch64_neon_sqrshrn>;
4508 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4509 int_aarch64_neon_sqrshrun>;
4510 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4511 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4512 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4513 int_aarch64_neon_sqshrn>;
4514 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4515 int_aarch64_neon_sqshrun>;
4516 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4517 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4518 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4519 TriOpFrag<(add node:$LHS,
4520 (AArch64srshri node:$MHS, node:$RHS))>>;
4521 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4522 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4523 TriOpFrag<(add node:$LHS,
4524 (AArch64vashr node:$MHS, node:$RHS))>>;
4525 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4526 int_aarch64_neon_uqrshrn>;
4527 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4528 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4529 int_aarch64_neon_uqshrn>;
4530 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4531 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4532 TriOpFrag<(add node:$LHS,
4533 (AArch64urshri node:$MHS, node:$RHS))>>;
4534 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4535 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4536 TriOpFrag<(add node:$LHS,
4537 (AArch64vlshr node:$MHS, node:$RHS))>>;
4539 //----------------------------------------------------------------------------
4540 // AdvSIMD vector shift instructions
4541 //----------------------------------------------------------------------------
4542 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4543 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4544 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4545 int_aarch64_neon_vcvtfxs2fp>;
4546 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4547 int_aarch64_neon_rshrn>;
4548 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4549 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4550 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4551 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4552 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4553 (i32 vecshiftL64:$imm))),
4554 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4555 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4556 int_aarch64_neon_sqrshrn>;
4557 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4558 int_aarch64_neon_sqrshrun>;
4559 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4560 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4561 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4562 int_aarch64_neon_sqshrn>;
4563 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4564 int_aarch64_neon_sqshrun>;
4565 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4566 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4567 (i32 vecshiftR64:$imm))),
4568 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4569 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4570 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4571 TriOpFrag<(add node:$LHS,
4572 (AArch64srshri node:$MHS, node:$RHS))> >;
4573 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4574 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4576 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4577 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4578 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4579 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4580 int_aarch64_neon_vcvtfxu2fp>;
4581 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4582 int_aarch64_neon_uqrshrn>;
4583 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4584 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4585 int_aarch64_neon_uqshrn>;
4586 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4587 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4588 TriOpFrag<(add node:$LHS,
4589 (AArch64urshri node:$MHS, node:$RHS))> >;
4590 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4591 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4592 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4593 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4594 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4596 // SHRN patterns for when a logical right shift was used instead of arithmetic
4597 // (the immediate guarantees no sign bits actually end up in the result so it
4599 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4600 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4601 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4602 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4603 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4604 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4606 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4607 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4608 vecshiftR16Narrow:$imm)))),
4609 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4610 V128:$Rn, vecshiftR16Narrow:$imm)>;
4611 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4612 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4613 vecshiftR32Narrow:$imm)))),
4614 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4615 V128:$Rn, vecshiftR32Narrow:$imm)>;
4616 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4617 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4618 vecshiftR64Narrow:$imm)))),
4619 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4620 V128:$Rn, vecshiftR32Narrow:$imm)>;
4622 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4623 // Anyexts are implemented as zexts.
4624 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4625 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4626 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4627 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4628 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4629 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4630 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4631 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4632 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4633 // Also match an extend from the upper half of a 128 bit source register.
4634 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4635 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4636 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4637 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4638 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4639 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4640 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4641 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4642 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4643 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4644 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4645 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4646 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4647 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4648 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4649 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4650 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4651 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4653 // Vector shift sxtl aliases
4654 def : InstAlias<"sxtl.8h $dst, $src1",
4655 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4656 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4657 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4658 def : InstAlias<"sxtl.4s $dst, $src1",
4659 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4660 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4661 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4662 def : InstAlias<"sxtl.2d $dst, $src1",
4663 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4664 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4665 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4667 // Vector shift sxtl2 aliases
4668 def : InstAlias<"sxtl2.8h $dst, $src1",
4669 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4670 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4671 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4672 def : InstAlias<"sxtl2.4s $dst, $src1",
4673 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4674 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4675 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4676 def : InstAlias<"sxtl2.2d $dst, $src1",
4677 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4678 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4679 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4681 // Vector shift uxtl aliases
4682 def : InstAlias<"uxtl.8h $dst, $src1",
4683 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4684 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4685 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4686 def : InstAlias<"uxtl.4s $dst, $src1",
4687 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4688 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4689 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4690 def : InstAlias<"uxtl.2d $dst, $src1",
4691 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4692 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4693 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4695 // Vector shift uxtl2 aliases
4696 def : InstAlias<"uxtl2.8h $dst, $src1",
4697 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4698 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4699 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4700 def : InstAlias<"uxtl2.4s $dst, $src1",
4701 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4702 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4703 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4704 def : InstAlias<"uxtl2.2d $dst, $src1",
4705 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4706 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4707 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4709 // If an integer is about to be converted to a floating point value,
4710 // just load it on the floating point unit.
4711 // These patterns are more complex because floating point loads do not
4712 // support sign extension.
4713 // The sign extension has to be explicitly added and is only supported for
4714 // one step: byte-to-half, half-to-word, word-to-doubleword.
4715 // SCVTF GPR -> FPR is 9 cycles.
4716 // SCVTF FPR -> FPR is 4 cyclces.
4717 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4718 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4719 // and still being faster.
4720 // However, this is not good for code size.
4721 // 8-bits -> float. 2 sizes step-up.
4722 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4723 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4724 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4729 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4735 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4737 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4738 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4739 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4740 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4741 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4742 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4743 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4744 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4746 // 16-bits -> float. 1 size step-up.
4747 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4748 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4749 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4751 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4755 ssub)))>, Requires<[NotForCodeSize]>;
4757 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4758 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4759 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4760 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4761 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4762 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4763 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4764 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4766 // 32-bits to 32-bits are handled in target specific dag combine:
4767 // performIntToFpCombine.
4768 // 64-bits integer to 32-bits floating point, not possible with
4769 // SCVTF on floating point registers (both source and destination
4770 // must have the same size).
4772 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4773 // 8-bits -> double. 3 size step-up: give up.
4774 // 16-bits -> double. 2 size step.
4775 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4776 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4777 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4782 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4788 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4790 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4791 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4792 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4793 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4794 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4795 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4796 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4797 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4798 // 32-bits -> double. 1 size step-up.
4799 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4800 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4801 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4803 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4807 dsub)))>, Requires<[NotForCodeSize]>;
4809 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4810 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4811 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4812 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4813 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4814 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4815 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4816 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4818 // 64-bits -> double are handled in target specific dag combine:
4819 // performIntToFpCombine.
4822 //----------------------------------------------------------------------------
4823 // AdvSIMD Load-Store Structure
4824 //----------------------------------------------------------------------------
4825 defm LD1 : SIMDLd1Multiple<"ld1">;
4826 defm LD2 : SIMDLd2Multiple<"ld2">;
4827 defm LD3 : SIMDLd3Multiple<"ld3">;
4828 defm LD4 : SIMDLd4Multiple<"ld4">;
4830 defm ST1 : SIMDSt1Multiple<"st1">;
4831 defm ST2 : SIMDSt2Multiple<"st2">;
4832 defm ST3 : SIMDSt3Multiple<"st3">;
4833 defm ST4 : SIMDSt4Multiple<"st4">;
4835 class Ld1Pat<ValueType ty, Instruction INST>
4836 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4838 def : Ld1Pat<v16i8, LD1Onev16b>;
4839 def : Ld1Pat<v8i16, LD1Onev8h>;
4840 def : Ld1Pat<v4i32, LD1Onev4s>;
4841 def : Ld1Pat<v2i64, LD1Onev2d>;
4842 def : Ld1Pat<v8i8, LD1Onev8b>;
4843 def : Ld1Pat<v4i16, LD1Onev4h>;
4844 def : Ld1Pat<v2i32, LD1Onev2s>;
4845 def : Ld1Pat<v1i64, LD1Onev1d>;
4847 class St1Pat<ValueType ty, Instruction INST>
4848 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4849 (INST ty:$Vt, GPR64sp:$Rn)>;
4851 def : St1Pat<v16i8, ST1Onev16b>;
4852 def : St1Pat<v8i16, ST1Onev8h>;
4853 def : St1Pat<v4i32, ST1Onev4s>;
4854 def : St1Pat<v2i64, ST1Onev2d>;
4855 def : St1Pat<v8i8, ST1Onev8b>;
4856 def : St1Pat<v4i16, ST1Onev4h>;
4857 def : St1Pat<v2i32, ST1Onev2s>;
4858 def : St1Pat<v1i64, ST1Onev1d>;
4864 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4865 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4866 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4867 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4868 let mayLoad = 1, hasSideEffects = 0 in {
4869 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4870 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4871 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4872 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4873 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4874 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4875 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4876 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4877 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4878 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4879 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4880 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4881 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4882 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4883 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4884 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4887 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4888 (LD1Rv8b GPR64sp:$Rn)>;
4889 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4890 (LD1Rv16b GPR64sp:$Rn)>;
4891 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4892 (LD1Rv4h GPR64sp:$Rn)>;
4893 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4894 (LD1Rv8h GPR64sp:$Rn)>;
4895 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4896 (LD1Rv2s GPR64sp:$Rn)>;
4897 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4898 (LD1Rv4s GPR64sp:$Rn)>;
4899 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4900 (LD1Rv2d GPR64sp:$Rn)>;
4901 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4902 (LD1Rv1d GPR64sp:$Rn)>;
4903 // Grab the floating point version too
4904 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4905 (LD1Rv2s GPR64sp:$Rn)>;
4906 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4907 (LD1Rv4s GPR64sp:$Rn)>;
4908 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4909 (LD1Rv2d GPR64sp:$Rn)>;
4910 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4911 (LD1Rv1d GPR64sp:$Rn)>;
4912 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4913 (LD1Rv4h GPR64sp:$Rn)>;
4914 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4915 (LD1Rv8h GPR64sp:$Rn)>;
4917 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4918 ValueType VTy, ValueType STy, Instruction LD1>
4919 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4920 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4921 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4923 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4924 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4925 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4926 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4927 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4928 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4929 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4931 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4932 ValueType VTy, ValueType STy, Instruction LD1>
4933 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4934 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4936 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4937 VecIndex:$idx, GPR64sp:$Rn),
4940 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4941 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4942 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4943 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4944 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4947 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4948 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4949 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4950 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4953 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4954 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4955 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4956 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4958 let AddedComplexity = 19 in
4959 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4960 ValueType VTy, ValueType STy, Instruction ST1>
4962 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4964 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4966 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4967 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4968 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4969 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4970 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4971 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4972 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
4974 let AddedComplexity = 19 in
4975 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4976 ValueType VTy, ValueType STy, Instruction ST1>
4978 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4980 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4981 VecIndex:$idx, GPR64sp:$Rn)>;
4983 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4984 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4985 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4986 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4987 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
4989 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4990 ValueType VTy, ValueType STy, Instruction ST1,
4992 def : Pat<(scalar_store
4993 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4994 GPR64sp:$Rn, offset),
4995 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4996 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4998 def : Pat<(scalar_store
4999 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5000 GPR64sp:$Rn, GPR64:$Rm),
5001 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5002 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5005 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
5006 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
5008 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
5009 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
5010 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
5011 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
5012 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
5014 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5015 ValueType VTy, ValueType STy, Instruction ST1,
5017 def : Pat<(scalar_store
5018 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5019 GPR64sp:$Rn, offset),
5020 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5022 def : Pat<(scalar_store
5023 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5024 GPR64sp:$Rn, GPR64:$Rm),
5025 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5028 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
5030 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
5032 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
5033 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
5034 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
5035 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
5036 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
5038 let mayStore = 1, hasSideEffects = 0 in {
5039 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
5040 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
5041 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
5042 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
5043 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
5044 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
5045 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
5046 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
5047 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
5048 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
5049 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
5050 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
5053 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
5054 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
5055 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
5056 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
5058 //----------------------------------------------------------------------------
5059 // Crypto extensions
5060 //----------------------------------------------------------------------------
5062 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
5063 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
5064 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
5065 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
5067 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
5068 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
5069 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
5070 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
5071 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
5072 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
5073 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
5075 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
5076 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
5077 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
5079 //----------------------------------------------------------------------------
5081 //----------------------------------------------------------------------------
5082 // FIXME: Like for X86, these should go in their own separate .td file.
5084 // Any instruction that defines a 32-bit result leaves the high half of the
5085 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
5086 // be copying from a truncate. But any other 32-bit operation will zero-extend
5088 // FIXME: X86 also checks for CMOV here. Do we need something similar?
5089 def def32 : PatLeaf<(i32 GPR32:$src), [{
5090 return N->getOpcode() != ISD::TRUNCATE &&
5091 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
5092 N->getOpcode() != ISD::CopyFromReg;
5095 // In the case of a 32-bit def that is known to implicitly zero-extend,
5096 // we can use a SUBREG_TO_REG.
5097 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
5099 // For an anyext, we don't care what the high bits are, so we can perform an
5100 // INSERT_SUBREF into an IMPLICIT_DEF.
5101 def : Pat<(i64 (anyext GPR32:$src)),
5102 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
5104 // When we need to explicitly zero-extend, we use a 32-bit MOV instruction and
5105 // then assert the extension has happened.
5106 def : Pat<(i64 (zext GPR32:$src)),
5107 (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>;
5109 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
5110 // containing super-reg.
5111 def : Pat<(i64 (sext GPR32:$src)),
5112 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5113 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
5114 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
5115 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
5116 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
5117 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
5118 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
5119 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
5121 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
5122 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5123 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
5124 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
5125 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5126 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
5128 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
5129 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5130 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
5131 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
5132 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5133 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
5135 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
5136 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5137 (i64 (i64shift_a imm0_63:$imm)),
5138 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
5140 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
5141 // AddedComplexity for the following patterns since we want to match sext + sra
5142 // patterns before we attempt to match a single sra node.
5143 let AddedComplexity = 20 in {
5144 // We support all sext + sra combinations which preserve at least one bit of the
5145 // original value which is to be sign extended. E.g. we support shifts up to
5147 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
5148 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
5149 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
5150 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
5152 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
5153 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
5154 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
5155 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
5157 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
5158 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5159 (i64 imm0_31:$imm), 31)>;
5160 } // AddedComplexity = 20
5162 // To truncate, we can simply extract from a subregister.
5163 def : Pat<(i32 (trunc GPR64sp:$src)),
5164 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5166 // __builtin_trap() uses the BRK instruction on AArch64.
5167 def : Pat<(trap), (BRK 1)>;
5169 // Conversions within AdvSIMD types in the same register size are free.
5170 // But because we need a consistent lane ordering, in big endian many
5171 // conversions require one or more REV instructions.
5173 // Consider a simple memory load followed by a bitconvert then a store.
5175 // v1 = BITCAST v2i32 v0 to v4i16
5178 // In big endian mode every memory access has an implicit byte swap. LDR and
5179 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5180 // is, they treat the vector as a sequence of elements to be byte-swapped.
5181 // The two pairs of instructions are fundamentally incompatible. We've decided
5182 // to use LD1/ST1 only to simplify compiler implementation.
5184 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5185 // the original code sequence:
5187 // v1 = REV v2i32 (implicit)
5188 // v2 = BITCAST v2i32 v1 to v4i16
5189 // v3 = REV v4i16 v2 (implicit)
5192 // But this is now broken - the value stored is different to the value loaded
5193 // due to lane reordering. To fix this, on every BITCAST we must perform two
5196 // v1 = REV v2i32 (implicit)
5198 // v3 = BITCAST v2i32 v2 to v4i16
5200 // v5 = REV v4i16 v4 (implicit)
5203 // This means an extra two instructions, but actually in most cases the two REV
5204 // instructions can be combined into one. For example:
5205 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5207 // There is also no 128-bit REV instruction. This must be synthesized with an
5210 // Most bitconverts require some sort of conversion. The only exceptions are:
5211 // a) Identity conversions - vNfX <-> vNiX
5212 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5215 // Natural vector casts (64 bit)
5216 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5217 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5218 def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5219 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5220 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5221 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5223 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5224 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5225 def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5226 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5227 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5229 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5230 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5231 def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5232 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5233 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5235 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5236 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5237 def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5238 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5239 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5240 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5241 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5243 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5244 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5245 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5246 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5247 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5249 // Natural vector casts (128 bit)
5250 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5251 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5252 def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5253 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5254 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5255 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5256 def : Pat<(v2f64 (AArch64NvCast (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5258 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5259 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5260 def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5261 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5262 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5263 def : Pat<(v4f32 (AArch64NvCast (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5264 def : Pat<(v2f64 (AArch64NvCast (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5266 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5267 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5268 def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5269 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5270 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5271 def : Pat<(v4f32 (AArch64NvCast (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5272 def : Pat<(v2f64 (AArch64NvCast (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5274 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5275 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5276 def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5277 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5278 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5279 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5280 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5282 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5283 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5284 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5285 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5286 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5287 def : Pat<(v8f16 (AArch64NvCast (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5288 def : Pat<(v2f64 (AArch64NvCast (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5290 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5291 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5292 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5293 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5294 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5295 def : Pat<(v8f16 (AArch64NvCast (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5296 def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5298 let Predicates = [IsLE] in {
5299 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5300 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5301 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5302 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5303 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5305 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5306 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5307 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5308 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5309 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5310 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5311 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5312 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5313 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5314 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5315 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5316 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5318 let Predicates = [IsBE] in {
5319 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5320 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5321 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5322 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5323 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5324 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5325 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5326 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5327 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5328 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5330 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5331 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5332 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5333 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5334 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5335 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5336 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5337 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5338 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5339 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5341 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5342 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5343 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5344 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5345 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5346 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5347 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5348 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5349 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5351 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5352 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5353 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5354 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5355 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5356 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5357 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5358 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5359 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5360 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5362 let Predicates = [IsLE] in {
5363 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5364 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5365 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5366 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5367 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5369 let Predicates = [IsBE] in {
5370 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5371 (v1i64 (REV64v2i32 FPR64:$src))>;
5372 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5373 (v1i64 (REV64v4i16 FPR64:$src))>;
5374 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5375 (v1i64 (REV64v8i8 FPR64:$src))>;
5376 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5377 (v1i64 (REV64v4i16 FPR64:$src))>;
5378 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5379 (v1i64 (REV64v2i32 FPR64:$src))>;
5381 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5382 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5384 let Predicates = [IsLE] in {
5385 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5386 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5387 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5388 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5389 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5390 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5392 let Predicates = [IsBE] in {
5393 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5394 (v2i32 (REV64v2i32 FPR64:$src))>;
5395 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5396 (v2i32 (REV32v4i16 FPR64:$src))>;
5397 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5398 (v2i32 (REV32v8i8 FPR64:$src))>;
5399 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5400 (v2i32 (REV64v2i32 FPR64:$src))>;
5401 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5402 (v2i32 (REV64v2i32 FPR64:$src))>;
5403 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5404 (v2i32 (REV64v4i16 FPR64:$src))>;
5406 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5408 let Predicates = [IsLE] in {
5409 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5410 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5411 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5412 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5413 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5414 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5415 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5417 let Predicates = [IsBE] in {
5418 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5419 (v4i16 (REV64v4i16 FPR64:$src))>;
5420 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5421 (v4i16 (REV32v4i16 FPR64:$src))>;
5422 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5423 (v4i16 (REV16v8i8 FPR64:$src))>;
5424 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5425 (v4i16 (REV64v4i16 FPR64:$src))>;
5426 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5427 (v4i16 (REV32v4i16 FPR64:$src))>;
5428 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5429 (v4i16 (REV32v4i16 FPR64:$src))>;
5430 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5431 (v4i16 (REV64v4i16 FPR64:$src))>;
5434 let Predicates = [IsLE] in {
5435 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5436 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5437 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5438 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5439 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5440 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5441 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5443 let Predicates = [IsBE] in {
5444 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5445 (v4f16 (REV64v4i16 FPR64:$src))>;
5446 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5447 (v4f16 (REV64v4i16 FPR64:$src))>;
5448 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5449 (v4f16 (REV64v4i16 FPR64:$src))>;
5450 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5451 (v4f16 (REV16v8i8 FPR64:$src))>;
5452 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5453 (v4f16 (REV64v4i16 FPR64:$src))>;
5454 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5455 (v4f16 (REV64v4i16 FPR64:$src))>;
5456 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5457 (v4f16 (REV64v4i16 FPR64:$src))>;
5462 let Predicates = [IsLE] in {
5463 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5464 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5465 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5466 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5467 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5468 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5469 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5471 let Predicates = [IsBE] in {
5472 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5473 (v8i8 (REV64v8i8 FPR64:$src))>;
5474 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5475 (v8i8 (REV32v8i8 FPR64:$src))>;
5476 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5477 (v8i8 (REV16v8i8 FPR64:$src))>;
5478 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5479 (v8i8 (REV64v8i8 FPR64:$src))>;
5480 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5481 (v8i8 (REV32v8i8 FPR64:$src))>;
5482 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5483 (v8i8 (REV64v8i8 FPR64:$src))>;
5484 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5485 (v8i8 (REV16v8i8 FPR64:$src))>;
5488 let Predicates = [IsLE] in {
5489 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5490 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5491 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5492 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5493 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5495 let Predicates = [IsBE] in {
5496 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5497 (f64 (REV64v2i32 FPR64:$src))>;
5498 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5499 (f64 (REV64v4i16 FPR64:$src))>;
5500 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5501 (f64 (REV64v2i32 FPR64:$src))>;
5502 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5503 (f64 (REV64v8i8 FPR64:$src))>;
5504 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5505 (f64 (REV64v4i16 FPR64:$src))>;
5507 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5508 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5510 let Predicates = [IsLE] in {
5511 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5512 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5513 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5514 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5515 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5517 let Predicates = [IsBE] in {
5518 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5519 (v1f64 (REV64v2i32 FPR64:$src))>;
5520 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5521 (v1f64 (REV64v4i16 FPR64:$src))>;
5522 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5523 (v1f64 (REV64v8i8 FPR64:$src))>;
5524 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5525 (v1f64 (REV64v2i32 FPR64:$src))>;
5526 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5527 (v1f64 (REV64v4i16 FPR64:$src))>;
5529 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5530 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5532 let Predicates = [IsLE] in {
5533 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5534 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5535 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5536 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5537 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5538 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5540 let Predicates = [IsBE] in {
5541 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5542 (v2f32 (REV64v2i32 FPR64:$src))>;
5543 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5544 (v2f32 (REV32v4i16 FPR64:$src))>;
5545 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5546 (v2f32 (REV32v8i8 FPR64:$src))>;
5547 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5548 (v2f32 (REV64v2i32 FPR64:$src))>;
5549 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5550 (v2f32 (REV64v2i32 FPR64:$src))>;
5551 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5552 (v2f32 (REV64v4i16 FPR64:$src))>;
5554 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5556 let Predicates = [IsLE] in {
5557 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5558 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5559 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5560 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5561 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5562 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5563 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5565 let Predicates = [IsBE] in {
5566 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5567 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5568 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5569 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5570 (REV64v4i32 FPR128:$src), (i32 8)))>;
5571 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5572 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5573 (REV64v8i16 FPR128:$src), (i32 8)))>;
5574 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5575 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5576 (REV64v8i16 FPR128:$src), (i32 8)))>;
5577 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5578 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5579 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5580 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5581 (REV64v4i32 FPR128:$src), (i32 8)))>;
5582 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5583 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5584 (REV64v16i8 FPR128:$src), (i32 8)))>;
5587 let Predicates = [IsLE] in {
5588 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5589 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5590 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5591 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5592 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5593 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5595 let Predicates = [IsBE] in {
5596 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5597 (v2f64 (EXTv16i8 FPR128:$src,
5598 FPR128:$src, (i32 8)))>;
5599 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5600 (v2f64 (REV64v4i32 FPR128:$src))>;
5601 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5602 (v2f64 (REV64v8i16 FPR128:$src))>;
5603 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5604 (v2f64 (REV64v8i16 FPR128:$src))>;
5605 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5606 (v2f64 (REV64v16i8 FPR128:$src))>;
5607 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5608 (v2f64 (REV64v4i32 FPR128:$src))>;
5610 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5612 let Predicates = [IsLE] in {
5613 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5614 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5615 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5616 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5617 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5618 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5620 let Predicates = [IsBE] in {
5621 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5622 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5623 (REV64v4i32 FPR128:$src), (i32 8)))>;
5624 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5625 (v4f32 (REV32v8i16 FPR128:$src))>;
5626 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5627 (v4f32 (REV32v8i16 FPR128:$src))>;
5628 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5629 (v4f32 (REV32v16i8 FPR128:$src))>;
5630 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5631 (v4f32 (REV64v4i32 FPR128:$src))>;
5632 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5633 (v4f32 (REV64v4i32 FPR128:$src))>;
5635 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5637 let Predicates = [IsLE] in {
5638 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5639 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5640 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5641 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5642 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5643 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5645 let Predicates = [IsBE] in {
5646 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5647 (v2i64 (EXTv16i8 FPR128:$src,
5648 FPR128:$src, (i32 8)))>;
5649 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5650 (v2i64 (REV64v4i32 FPR128:$src))>;
5651 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5652 (v2i64 (REV64v8i16 FPR128:$src))>;
5653 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5654 (v2i64 (REV64v16i8 FPR128:$src))>;
5655 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5656 (v2i64 (REV64v4i32 FPR128:$src))>;
5657 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5658 (v2i64 (REV64v8i16 FPR128:$src))>;
5660 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5662 let Predicates = [IsLE] in {
5663 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5664 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5665 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5666 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5667 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5668 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5670 let Predicates = [IsBE] in {
5671 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5672 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5673 (REV64v4i32 FPR128:$src),
5675 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5676 (v4i32 (REV64v4i32 FPR128:$src))>;
5677 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5678 (v4i32 (REV32v8i16 FPR128:$src))>;
5679 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5680 (v4i32 (REV32v16i8 FPR128:$src))>;
5681 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5682 (v4i32 (REV64v4i32 FPR128:$src))>;
5683 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5684 (v4i32 (REV32v8i16 FPR128:$src))>;
5686 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5688 let Predicates = [IsLE] in {
5689 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5690 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5691 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5692 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5693 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5694 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5695 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5697 let Predicates = [IsBE] in {
5698 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5699 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5700 (REV64v8i16 FPR128:$src),
5702 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5703 (v8i16 (REV64v8i16 FPR128:$src))>;
5704 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5705 (v8i16 (REV32v8i16 FPR128:$src))>;
5706 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5707 (v8i16 (REV16v16i8 FPR128:$src))>;
5708 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5709 (v8i16 (REV64v8i16 FPR128:$src))>;
5710 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5711 (v8i16 (REV32v8i16 FPR128:$src))>;
5712 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5713 (v8i16 (REV32v8i16 FPR128:$src))>;
5716 let Predicates = [IsLE] in {
5717 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5718 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5719 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5720 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5721 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5722 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5723 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5725 let Predicates = [IsBE] in {
5726 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5727 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5728 (REV64v8i16 FPR128:$src),
5730 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5731 (v8f16 (REV64v8i16 FPR128:$src))>;
5732 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5733 (v8f16 (REV32v8i16 FPR128:$src))>;
5734 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5735 (v8f16 (REV64v8i16 FPR128:$src))>;
5736 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5737 (v8f16 (REV16v16i8 FPR128:$src))>;
5738 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5739 (v8f16 (REV64v8i16 FPR128:$src))>;
5740 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5741 (v8f16 (REV32v8i16 FPR128:$src))>;
5744 let Predicates = [IsLE] in {
5745 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5746 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5747 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5748 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5749 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5750 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5751 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5753 let Predicates = [IsBE] in {
5754 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5755 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5756 (REV64v16i8 FPR128:$src),
5758 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5759 (v16i8 (REV64v16i8 FPR128:$src))>;
5760 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5761 (v16i8 (REV32v16i8 FPR128:$src))>;
5762 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5763 (v16i8 (REV16v16i8 FPR128:$src))>;
5764 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5765 (v16i8 (REV64v16i8 FPR128:$src))>;
5766 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5767 (v16i8 (REV32v16i8 FPR128:$src))>;
5768 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5769 (v16i8 (REV16v16i8 FPR128:$src))>;
5772 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5773 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5774 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5775 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5776 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5777 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5778 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5779 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5781 // A 64-bit subvector insert to the first 128-bit vector position
5782 // is a subregister copy that needs no instruction.
5783 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5784 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5785 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5786 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5787 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5788 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5789 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5790 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5791 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5792 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5793 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5794 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5795 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5796 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5798 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5800 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5801 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5802 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5803 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5804 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5805 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5806 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5807 // so we match on v4f32 here, not v2f32. This will also catch adding
5808 // the low two lanes of a true v4f32 vector.
5809 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5810 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5811 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5813 // Scalar 64-bit shifts in FPR64 registers.
5814 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5815 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5816 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5817 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5818 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5819 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5820 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5821 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5823 // Tail call return handling. These are all compiler pseudo-instructions,
5824 // so no encoding information or anything like that.
5825 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5826 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5827 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5830 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5831 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5832 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5833 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5834 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5835 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5837 include "AArch64InstrAtomics.td"