1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
27 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
29 //===----------------------------------------------------------------------===//
30 // AArch64-specific DAG Nodes.
33 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
34 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
39 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
40 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
46 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
47 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
54 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
55 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
57 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
58 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
59 SDTCisVT<2, OtherVT>]>;
62 def SDT_AArch64CSel : SDTypeProfile<1, 4,
67 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
70 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
71 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
72 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
75 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
76 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
77 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
78 SDTCisInt<2>, SDTCisInt<3>]>;
79 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
80 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
82 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
84 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
85 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
86 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
87 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
89 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
92 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
93 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
95 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
97 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
100 // Generates the general dynamic sequences, i.e.
101 // adrp x0, :tlsdesc:var
102 // ldr x1, [x0, #:tlsdesc_lo12:var]
103 // add x0, x0, #:tlsdesc_lo12:var
107 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
108 // number of operands (the variable)
109 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
112 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
113 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
114 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
115 SDTCisSameAs<1, 4>]>;
119 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
120 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
121 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
122 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
123 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
124 [SDNPHasChain, SDNPOutGlue]>;
125 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
126 SDCallSeqEnd<[ SDTCisVT<0, i32>,
128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
129 def AArch64call : SDNode<"AArch64ISD::CALL",
130 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
131 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
133 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
135 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
137 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
139 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
141 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
145 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
146 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
147 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
148 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
149 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
151 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
152 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
153 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
155 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
156 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
158 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
159 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
161 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
163 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
165 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
166 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
168 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
169 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
170 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
171 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
172 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
174 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
175 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
176 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
177 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
178 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
179 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
181 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
182 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
183 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
184 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
185 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
186 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
187 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
189 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
190 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
191 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
192 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
194 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
195 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
196 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
197 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
198 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
199 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
200 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
201 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
203 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
204 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
205 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
207 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
208 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
209 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
210 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
211 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
213 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
214 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
215 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
217 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
218 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
219 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
220 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
221 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
222 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
223 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
225 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
226 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
227 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
228 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
229 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
231 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
232 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
234 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
236 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
237 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
239 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
240 [SDNPHasChain, SDNPSideEffect]>;
242 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
243 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
245 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
246 SDT_AArch64TLSDescCallSeq,
247 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
251 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
252 SDT_AArch64WrapperLarge>;
254 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
256 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
257 SDTCisSameAs<1, 2>]>;
258 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
259 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
261 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
262 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
263 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
264 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
265 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
266 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
268 //===----------------------------------------------------------------------===//
270 //===----------------------------------------------------------------------===//
272 // AArch64 Instruction Predicate Definitions.
274 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
275 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
276 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
277 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
278 def ForCodeSize : Predicate<"ForCodeSize">;
279 def NotForCodeSize : Predicate<"!ForCodeSize">;
281 include "AArch64InstrFormats.td"
283 //===----------------------------------------------------------------------===//
285 //===----------------------------------------------------------------------===//
286 // Miscellaneous instructions.
287 //===----------------------------------------------------------------------===//
289 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
290 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
291 [(AArch64callseq_start timm:$amt)]>;
292 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
293 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
294 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
296 let isReMaterializable = 1, isCodeGenOnly = 1 in {
297 // FIXME: The following pseudo instructions are only needed because remat
298 // cannot handle multiple instructions. When that changes, they can be
299 // removed, along with the AArch64Wrapper node.
301 let AddedComplexity = 10 in
302 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
303 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
306 // The MOVaddr instruction should match only when the add is not folded
307 // into a load or store address.
309 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
310 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
311 tglobaladdr:$low))]>,
312 Sched<[WriteAdrAdr]>;
314 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
315 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
317 Sched<[WriteAdrAdr]>;
319 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
320 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
322 Sched<[WriteAdrAdr]>;
324 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
325 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
326 tblockaddress:$low))]>,
327 Sched<[WriteAdrAdr]>;
329 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
330 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
331 tglobaltlsaddr:$low))]>,
332 Sched<[WriteAdrAdr]>;
334 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
335 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
336 texternalsym:$low))]>,
337 Sched<[WriteAdrAdr]>;
339 } // isReMaterializable, isCodeGenOnly
341 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
342 (LOADgot tglobaltlsaddr:$addr)>;
344 def : Pat<(AArch64LOADgot texternalsym:$addr),
345 (LOADgot texternalsym:$addr)>;
347 def : Pat<(AArch64LOADgot tconstpool:$addr),
348 (LOADgot tconstpool:$addr)>;
350 //===----------------------------------------------------------------------===//
351 // System instructions.
352 //===----------------------------------------------------------------------===//
354 def HINT : HintI<"hint">;
355 def : InstAlias<"nop", (HINT 0b000)>;
356 def : InstAlias<"yield",(HINT 0b001)>;
357 def : InstAlias<"wfe", (HINT 0b010)>;
358 def : InstAlias<"wfi", (HINT 0b011)>;
359 def : InstAlias<"sev", (HINT 0b100)>;
360 def : InstAlias<"sevl", (HINT 0b101)>;
362 // As far as LLVM is concerned this writes to the system's exclusive monitors.
363 let mayLoad = 1, mayStore = 1 in
364 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
366 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
367 // model patterns with sufficiently fine granularity.
368 let mayLoad = ?, mayStore = ? in {
369 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
370 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
372 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
373 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
375 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
376 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
379 def : InstAlias<"clrex", (CLREX 0xf)>;
380 def : InstAlias<"isb", (ISB 0xf)>;
384 def MSRpstate: MSRpstateI;
386 // The thread pointer (on Linux, at least, where this has been implemented) is
388 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
390 // Generic system instructions
391 def SYSxt : SystemXtI<0, "sys">;
392 def SYSLxt : SystemLXtI<1, "sysl">;
394 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
395 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
396 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
398 //===----------------------------------------------------------------------===//
399 // Move immediate instructions.
400 //===----------------------------------------------------------------------===//
402 defm MOVK : InsertImmediate<0b11, "movk">;
403 defm MOVN : MoveImmediate<0b00, "movn">;
405 let PostEncoderMethod = "fixMOVZ" in
406 defm MOVZ : MoveImmediate<0b10, "movz">;
408 // First group of aliases covers an implicit "lsl #0".
409 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
410 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
411 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
412 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
413 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
414 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
416 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
417 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
418 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
419 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
420 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
422 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
423 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
424 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
425 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
427 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
428 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
429 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
430 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
432 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
433 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
435 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
436 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
438 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
439 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
441 // Final group of aliases covers true "mov $Rd, $imm" cases.
442 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
443 int width, int shift> {
444 def _asmoperand : AsmOperandClass {
445 let Name = basename # width # "_lsl" # shift # "MovAlias";
446 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
448 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
451 def _movimm : Operand<i32> {
452 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
455 def : InstAlias<"mov $Rd, $imm",
456 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
459 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
460 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
462 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
463 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
464 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
465 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
467 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
468 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
470 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
471 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
472 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
473 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
475 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
476 isAsCheapAsAMove = 1 in {
477 // FIXME: The following pseudo instructions are only needed because remat
478 // cannot handle multiple instructions. When that changes, we can select
479 // directly to the real instructions and get rid of these pseudos.
482 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
483 [(set GPR32:$dst, imm:$src)]>,
486 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
487 [(set GPR64:$dst, imm:$src)]>,
489 } // isReMaterializable, isCodeGenOnly
491 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
492 // eventual expansion code fewer bits to worry about getting right. Marshalling
493 // the types is a little tricky though:
494 def i64imm_32bit : ImmLeaf<i64, [{
495 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
498 def trunc_imm : SDNodeXForm<imm, [{
499 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
502 def : Pat<(i64 i64imm_32bit:$src),
503 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
505 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
506 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
507 return CurDAG->getTargetConstant(
508 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
511 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
512 return CurDAG->getTargetConstant(
513 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
517 def : Pat<(f32 fpimm:$in),
518 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
519 def : Pat<(f64 fpimm:$in),
520 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
523 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
525 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
526 tglobaladdr:$g1, tglobaladdr:$g0),
527 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
528 tglobaladdr:$g2, 32),
529 tglobaladdr:$g1, 16),
530 tglobaladdr:$g0, 0)>;
532 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
533 tblockaddress:$g1, tblockaddress:$g0),
534 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
535 tblockaddress:$g2, 32),
536 tblockaddress:$g1, 16),
537 tblockaddress:$g0, 0)>;
539 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
540 tconstpool:$g1, tconstpool:$g0),
541 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
546 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
547 tjumptable:$g1, tjumptable:$g0),
548 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
554 //===----------------------------------------------------------------------===//
555 // Arithmetic instructions.
556 //===----------------------------------------------------------------------===//
558 // Add/subtract with carry.
559 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
560 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
562 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
563 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
564 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
565 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
568 defm ADD : AddSub<0, "add", add>;
569 defm SUB : AddSub<1, "sub">;
571 def : InstAlias<"mov $dst, $src",
572 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
573 def : InstAlias<"mov $dst, $src",
574 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
575 def : InstAlias<"mov $dst, $src",
576 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
577 def : InstAlias<"mov $dst, $src",
578 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
580 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
581 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
583 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
584 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
585 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
586 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
587 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
588 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
589 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
590 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
591 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
592 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
593 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
594 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
595 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
596 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
597 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
598 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
599 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
601 // Because of the immediate format for add/sub-imm instructions, the
602 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
603 // These patterns capture that transformation.
604 let AddedComplexity = 1 in {
605 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
606 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
607 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
608 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
609 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
610 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
611 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
612 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
615 // Because of the immediate format for add/sub-imm instructions, the
616 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
617 // These patterns capture that transformation.
618 let AddedComplexity = 1 in {
619 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
620 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
621 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
622 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
623 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
624 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
625 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
626 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
629 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
630 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
631 def : InstAlias<"neg $dst, $src$shift",
632 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
633 def : InstAlias<"neg $dst, $src$shift",
634 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
636 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
637 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
638 def : InstAlias<"negs $dst, $src$shift",
639 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
640 def : InstAlias<"negs $dst, $src$shift",
641 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
644 // Unsigned/Signed divide
645 defm UDIV : Div<0, "udiv", udiv>;
646 defm SDIV : Div<1, "sdiv", sdiv>;
647 let isCodeGenOnly = 1 in {
648 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
649 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
653 defm ASRV : Shift<0b10, "asr", sra>;
654 defm LSLV : Shift<0b00, "lsl", shl>;
655 defm LSRV : Shift<0b01, "lsr", srl>;
656 defm RORV : Shift<0b11, "ror", rotr>;
658 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
659 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
660 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
661 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
662 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
663 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
664 def : ShiftAlias<"rorv", RORVWr, GPR32>;
665 def : ShiftAlias<"rorv", RORVXr, GPR64>;
668 let AddedComplexity = 7 in {
669 defm MADD : MulAccum<0, "madd", add>;
670 defm MSUB : MulAccum<1, "msub", sub>;
672 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
673 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
674 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
675 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
677 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
678 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
679 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
680 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
681 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
682 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
683 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
684 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
685 } // AddedComplexity = 7
687 let AddedComplexity = 5 in {
688 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
689 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
690 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
691 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
693 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
694 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
695 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
696 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
698 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
699 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
700 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
701 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
702 } // AddedComplexity = 5
704 def : MulAccumWAlias<"mul", MADDWrrr>;
705 def : MulAccumXAlias<"mul", MADDXrrr>;
706 def : MulAccumWAlias<"mneg", MSUBWrrr>;
707 def : MulAccumXAlias<"mneg", MSUBXrrr>;
708 def : WideMulAccumAlias<"smull", SMADDLrrr>;
709 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
710 def : WideMulAccumAlias<"umull", UMADDLrrr>;
711 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
714 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
715 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
718 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
719 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
720 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
721 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
723 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
724 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
725 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
726 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
729 //===----------------------------------------------------------------------===//
730 // Logical instructions.
731 //===----------------------------------------------------------------------===//
734 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
735 defm AND : LogicalImm<0b00, "and", and, "bic">;
736 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
737 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
739 // FIXME: these aliases *are* canonical sometimes (when movz can't be
740 // used). Actually, it seems to be working right now, but putting logical_immXX
741 // here is a bit dodgy on the AsmParser side too.
742 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
743 logical_imm32:$imm), 0>;
744 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
745 logical_imm64:$imm), 0>;
749 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
750 defm BICS : LogicalRegS<0b11, 1, "bics",
751 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
752 defm AND : LogicalReg<0b00, 0, "and", and>;
753 defm BIC : LogicalReg<0b00, 1, "bic",
754 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
755 defm EON : LogicalReg<0b10, 1, "eon",
756 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
757 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
758 defm ORN : LogicalReg<0b01, 1, "orn",
759 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
760 defm ORR : LogicalReg<0b01, 0, "orr", or>;
762 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
763 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
765 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
766 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
768 def : InstAlias<"mvn $Wd, $Wm$sh",
769 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
770 def : InstAlias<"mvn $Xd, $Xm$sh",
771 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
773 def : InstAlias<"tst $src1, $src2",
774 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
775 def : InstAlias<"tst $src1, $src2",
776 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
778 def : InstAlias<"tst $src1, $src2",
779 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
780 def : InstAlias<"tst $src1, $src2",
781 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
783 def : InstAlias<"tst $src1, $src2$sh",
784 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
785 def : InstAlias<"tst $src1, $src2$sh",
786 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
789 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
790 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
793 //===----------------------------------------------------------------------===//
794 // One operand data processing instructions.
795 //===----------------------------------------------------------------------===//
797 defm CLS : OneOperandData<0b101, "cls">;
798 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
799 defm RBIT : OneOperandData<0b000, "rbit">;
801 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
802 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
804 def REV16Wr : OneWRegData<0b001, "rev16",
805 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
806 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
808 def : Pat<(cttz GPR32:$Rn),
809 (CLZWr (RBITWr GPR32:$Rn))>;
810 def : Pat<(cttz GPR64:$Rn),
811 (CLZXr (RBITXr GPR64:$Rn))>;
812 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
815 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
819 // Unlike the other one operand instructions, the instructions with the "rev"
820 // mnemonic do *not* just different in the size bit, but actually use different
821 // opcode bits for the different sizes.
822 def REVWr : OneWRegData<0b010, "rev", bswap>;
823 def REVXr : OneXRegData<0b011, "rev", bswap>;
824 def REV32Xr : OneXRegData<0b010, "rev32",
825 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
827 // The bswap commutes with the rotr so we want a pattern for both possible
829 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
830 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
832 //===----------------------------------------------------------------------===//
833 // Bitfield immediate extraction instruction.
834 //===----------------------------------------------------------------------===//
835 let hasSideEffects = 0 in
836 defm EXTR : ExtractImm<"extr">;
837 def : InstAlias<"ror $dst, $src, $shift",
838 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
839 def : InstAlias<"ror $dst, $src, $shift",
840 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
842 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
843 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
844 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
845 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
847 //===----------------------------------------------------------------------===//
848 // Other bitfield immediate instructions.
849 //===----------------------------------------------------------------------===//
850 let hasSideEffects = 0 in {
851 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
852 defm SBFM : BitfieldImm<0b00, "sbfm">;
853 defm UBFM : BitfieldImm<0b10, "ubfm">;
856 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
857 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
858 return CurDAG->getTargetConstant(enc, MVT::i64);
861 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
862 uint64_t enc = 31 - N->getZExtValue();
863 return CurDAG->getTargetConstant(enc, MVT::i64);
866 // min(7, 31 - shift_amt)
867 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
868 uint64_t enc = 31 - N->getZExtValue();
869 enc = enc > 7 ? 7 : enc;
870 return CurDAG->getTargetConstant(enc, MVT::i64);
873 // min(15, 31 - shift_amt)
874 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
875 uint64_t enc = 31 - N->getZExtValue();
876 enc = enc > 15 ? 15 : enc;
877 return CurDAG->getTargetConstant(enc, MVT::i64);
880 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
881 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
882 return CurDAG->getTargetConstant(enc, MVT::i64);
885 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
886 uint64_t enc = 63 - N->getZExtValue();
887 return CurDAG->getTargetConstant(enc, MVT::i64);
890 // min(7, 63 - shift_amt)
891 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
892 uint64_t enc = 63 - N->getZExtValue();
893 enc = enc > 7 ? 7 : enc;
894 return CurDAG->getTargetConstant(enc, MVT::i64);
897 // min(15, 63 - shift_amt)
898 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
899 uint64_t enc = 63 - N->getZExtValue();
900 enc = enc > 15 ? 15 : enc;
901 return CurDAG->getTargetConstant(enc, MVT::i64);
904 // min(31, 63 - shift_amt)
905 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
906 uint64_t enc = 63 - N->getZExtValue();
907 enc = enc > 31 ? 31 : enc;
908 return CurDAG->getTargetConstant(enc, MVT::i64);
911 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
912 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
913 (i64 (i32shift_b imm0_31:$imm)))>;
914 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
915 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
916 (i64 (i64shift_b imm0_63:$imm)))>;
918 let AddedComplexity = 10 in {
919 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
920 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
921 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
922 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
925 def : InstAlias<"asr $dst, $src, $shift",
926 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
927 def : InstAlias<"asr $dst, $src, $shift",
928 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
929 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
930 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
931 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
932 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
933 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
935 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
936 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
937 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
938 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
940 def : InstAlias<"lsr $dst, $src, $shift",
941 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
942 def : InstAlias<"lsr $dst, $src, $shift",
943 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
944 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
945 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
946 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
947 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
948 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
950 //===----------------------------------------------------------------------===//
951 // Conditionally set flags instructions.
952 //===----------------------------------------------------------------------===//
953 defm CCMN : CondSetFlagsImm<0, "ccmn">;
954 defm CCMP : CondSetFlagsImm<1, "ccmp">;
956 defm CCMN : CondSetFlagsReg<0, "ccmn">;
957 defm CCMP : CondSetFlagsReg<1, "ccmp">;
959 //===----------------------------------------------------------------------===//
960 // Conditional select instructions.
961 //===----------------------------------------------------------------------===//
962 defm CSEL : CondSelect<0, 0b00, "csel">;
964 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
965 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
966 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
967 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
969 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
970 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
971 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
972 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
973 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
974 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
975 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
976 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
977 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
978 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
979 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
980 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
982 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
983 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
984 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
985 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
986 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
987 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
988 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
989 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
991 // The inverse of the condition code from the alias instruction is what is used
992 // in the aliased instruction. The parser all ready inverts the condition code
993 // for these aliases.
994 def : InstAlias<"cset $dst, $cc",
995 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
996 def : InstAlias<"cset $dst, $cc",
997 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
999 def : InstAlias<"csetm $dst, $cc",
1000 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1001 def : InstAlias<"csetm $dst, $cc",
1002 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1004 def : InstAlias<"cinc $dst, $src, $cc",
1005 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1006 def : InstAlias<"cinc $dst, $src, $cc",
1007 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1009 def : InstAlias<"cinv $dst, $src, $cc",
1010 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1011 def : InstAlias<"cinv $dst, $src, $cc",
1012 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1014 def : InstAlias<"cneg $dst, $src, $cc",
1015 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1016 def : InstAlias<"cneg $dst, $src, $cc",
1017 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1019 //===----------------------------------------------------------------------===//
1020 // PC-relative instructions.
1021 //===----------------------------------------------------------------------===//
1022 let isReMaterializable = 1 in {
1023 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1024 def ADR : ADRI<0, "adr", adrlabel, []>;
1025 } // hasSideEffects = 0
1027 def ADRP : ADRI<1, "adrp", adrplabel,
1028 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1029 } // isReMaterializable = 1
1031 // page address of a constant pool entry, block address
1032 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1033 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1035 //===----------------------------------------------------------------------===//
1036 // Unconditional branch (register) instructions.
1037 //===----------------------------------------------------------------------===//
1039 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1040 def RET : BranchReg<0b0010, "ret", []>;
1041 def DRPS : SpecialReturn<0b0101, "drps">;
1042 def ERET : SpecialReturn<0b0100, "eret">;
1043 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1045 // Default to the LR register.
1046 def : InstAlias<"ret", (RET LR)>;
1048 let isCall = 1, Defs = [LR], Uses = [SP] in {
1049 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1052 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1053 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1054 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1056 // Create a separate pseudo-instruction for codegen to use so that we don't
1057 // flag lr as used in every function. It'll be restored before the RET by the
1058 // epilogue if it's legitimately used.
1059 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1060 let isTerminator = 1;
1065 // This is a directive-like pseudo-instruction. The purpose is to insert an
1066 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1067 // (which in the usual case is a BLR).
1068 let hasSideEffects = 1 in
1069 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1070 let AsmString = ".tlsdesccall $sym";
1073 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
1074 // FIXME: can "hasSideEffects be dropped?
1075 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
1076 isCodeGenOnly = 1 in
1078 : Pseudo<(outs), (ins i64imm:$sym),
1079 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>;
1080 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
1081 (TLSDESC_CALLSEQ texternalsym:$sym)>;
1083 //===----------------------------------------------------------------------===//
1084 // Conditional branch (immediate) instruction.
1085 //===----------------------------------------------------------------------===//
1086 def Bcc : BranchCond;
1088 //===----------------------------------------------------------------------===//
1089 // Compare-and-branch instructions.
1090 //===----------------------------------------------------------------------===//
1091 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1092 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1094 //===----------------------------------------------------------------------===//
1095 // Test-bit-and-branch instructions.
1096 //===----------------------------------------------------------------------===//
1097 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1098 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1100 //===----------------------------------------------------------------------===//
1101 // Unconditional branch (immediate) instructions.
1102 //===----------------------------------------------------------------------===//
1103 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1104 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1105 } // isBranch, isTerminator, isBarrier
1107 let isCall = 1, Defs = [LR], Uses = [SP] in {
1108 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1110 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1112 //===----------------------------------------------------------------------===//
1113 // Exception generation instructions.
1114 //===----------------------------------------------------------------------===//
1115 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1116 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1117 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1118 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1119 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1120 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1121 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1122 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1124 // DCPSn defaults to an immediate operand of zero if unspecified.
1125 def : InstAlias<"dcps1", (DCPS1 0)>;
1126 def : InstAlias<"dcps2", (DCPS2 0)>;
1127 def : InstAlias<"dcps3", (DCPS3 0)>;
1129 //===----------------------------------------------------------------------===//
1130 // Load instructions.
1131 //===----------------------------------------------------------------------===//
1133 // Pair (indexed, offset)
1134 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1135 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1136 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1137 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1138 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1140 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1142 // Pair (pre-indexed)
1143 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1144 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1145 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1146 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1147 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1149 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1151 // Pair (post-indexed)
1152 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1153 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1154 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1155 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1156 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1158 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1161 // Pair (no allocate)
1162 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1163 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1164 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1165 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1166 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1169 // (register offset)
1173 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1174 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1175 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1176 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1179 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1180 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1181 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1182 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1183 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1185 // Load sign-extended half-word
1186 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1187 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1189 // Load sign-extended byte
1190 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1191 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1193 // Load sign-extended word
1194 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1197 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1199 // For regular load, we do not have any alignment requirement.
1200 // Thus, it is safe to directly map the vector loads with interesting
1201 // addressing modes.
1202 // FIXME: We could do the same for bitconvert to floating point vectors.
1203 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1204 ValueType ScalTy, ValueType VecTy,
1205 Instruction LOADW, Instruction LOADX,
1207 def : Pat<(VecTy (scalar_to_vector (ScalTy
1208 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1209 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1210 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1213 def : Pat<(VecTy (scalar_to_vector (ScalTy
1214 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1215 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1216 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1220 let AddedComplexity = 10 in {
1221 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1222 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1224 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1225 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1227 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1228 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1230 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1231 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1233 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1234 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1236 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1238 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1241 def : Pat <(v1i64 (scalar_to_vector (i64
1242 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1243 ro_Wextend64:$extend))))),
1244 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1246 def : Pat <(v1i64 (scalar_to_vector (i64
1247 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1248 ro_Xextend64:$extend))))),
1249 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1252 // Match all load 64 bits width whose type is compatible with FPR64
1253 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1254 Instruction LOADW, Instruction LOADX> {
1256 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1257 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1259 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1260 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1263 let AddedComplexity = 10 in {
1264 let Predicates = [IsLE] in {
1265 // We must do vector loads with LD1 in big-endian.
1266 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1267 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1268 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1269 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1270 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1273 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1274 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1276 // Match all load 128 bits width whose type is compatible with FPR128
1277 let Predicates = [IsLE] in {
1278 // We must do vector loads with LD1 in big-endian.
1279 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1280 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1281 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1282 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1283 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1284 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1285 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1287 } // AddedComplexity = 10
1290 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1291 Instruction INSTW, Instruction INSTX> {
1292 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1293 (SUBREG_TO_REG (i64 0),
1294 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1297 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1298 (SUBREG_TO_REG (i64 0),
1299 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1303 let AddedComplexity = 10 in {
1304 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1305 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1306 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1308 // zextloadi1 -> zextloadi8
1309 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1311 // extload -> zextload
1312 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1313 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1314 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1316 // extloadi1 -> zextloadi8
1317 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1322 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1323 Instruction INSTW, Instruction INSTX> {
1324 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1325 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1327 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1328 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1332 let AddedComplexity = 10 in {
1333 // extload -> zextload
1334 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1335 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1336 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1338 // zextloadi1 -> zextloadi8
1339 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1343 // (unsigned immediate)
1345 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1347 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1348 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1350 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1351 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1353 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1354 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1355 [(set (f16 FPR16:$Rt),
1356 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1357 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1358 [(set (f32 FPR32:$Rt),
1359 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1360 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1361 [(set (f64 FPR64:$Rt),
1362 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1363 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1364 [(set (f128 FPR128:$Rt),
1365 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1367 // For regular load, we do not have any alignment requirement.
1368 // Thus, it is safe to directly map the vector loads with interesting
1369 // addressing modes.
1370 // FIXME: We could do the same for bitconvert to floating point vectors.
1371 def : Pat <(v8i8 (scalar_to_vector (i32
1372 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1373 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1374 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1375 def : Pat <(v16i8 (scalar_to_vector (i32
1376 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1377 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1378 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1379 def : Pat <(v4i16 (scalar_to_vector (i32
1380 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1381 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1382 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1383 def : Pat <(v8i16 (scalar_to_vector (i32
1384 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1385 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1386 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1387 def : Pat <(v2i32 (scalar_to_vector (i32
1388 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1389 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1390 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1391 def : Pat <(v4i32 (scalar_to_vector (i32
1392 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1393 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1394 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1395 def : Pat <(v1i64 (scalar_to_vector (i64
1396 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1397 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1398 def : Pat <(v2i64 (scalar_to_vector (i64
1399 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1400 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1401 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1403 // Match all load 64 bits width whose type is compatible with FPR64
1404 let Predicates = [IsLE] in {
1405 // We must use LD1 to perform vector loads in big-endian.
1406 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1407 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1408 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1409 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1410 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1411 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1412 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1413 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1414 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1415 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1417 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1418 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1419 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1420 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1422 // Match all load 128 bits width whose type is compatible with FPR128
1423 let Predicates = [IsLE] in {
1424 // We must use LD1 to perform vector loads in big-endian.
1425 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1426 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1427 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1428 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1429 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1430 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1431 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1432 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1433 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1434 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1435 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1436 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1437 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1438 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1440 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1441 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1443 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1445 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1446 uimm12s2:$offset)))]>;
1447 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1449 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1450 uimm12s1:$offset)))]>;
1452 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1453 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1454 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1455 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1457 // zextloadi1 -> zextloadi8
1458 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1459 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1460 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1461 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1463 // extload -> zextload
1464 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1465 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1466 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1467 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1468 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1469 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1470 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1471 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1472 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1473 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1474 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1475 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1476 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1477 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1479 // load sign-extended half-word
1480 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1482 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1483 uimm12s2:$offset)))]>;
1484 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1486 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1487 uimm12s2:$offset)))]>;
1489 // load sign-extended byte
1490 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1492 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1493 uimm12s1:$offset)))]>;
1494 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1496 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1497 uimm12s1:$offset)))]>;
1499 // load sign-extended word
1500 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1502 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1503 uimm12s4:$offset)))]>;
1505 // load zero-extended word
1506 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1507 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1510 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1511 [(AArch64Prefetch imm:$Rt,
1512 (am_indexed64 GPR64sp:$Rn,
1513 uimm12s8:$offset))]>;
1515 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1519 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1520 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1521 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1522 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1523 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1525 // load sign-extended word
1526 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1529 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1530 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1533 // (unscaled immediate)
1534 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1536 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1537 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1539 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1540 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1542 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1543 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1545 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1546 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1547 [(set (f32 FPR32:$Rt),
1548 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1549 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1550 [(set (f64 FPR64:$Rt),
1551 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1552 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1553 [(set (f128 FPR128:$Rt),
1554 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1557 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1559 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1561 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1563 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1565 // Match all load 64 bits width whose type is compatible with FPR64
1566 let Predicates = [IsLE] in {
1567 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1568 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1569 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1570 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1571 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1572 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1573 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1574 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1575 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1576 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1578 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1579 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1580 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1581 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1583 // Match all load 128 bits width whose type is compatible with FPR128
1584 let Predicates = [IsLE] in {
1585 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1586 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1587 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1588 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1589 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1590 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1591 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1592 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1593 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1594 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1595 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1596 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1597 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1598 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1602 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1603 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1604 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1605 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1606 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1607 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1608 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1609 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1610 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1611 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1612 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1613 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1614 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1615 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1617 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1618 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1619 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1620 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1621 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1622 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1623 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1624 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1625 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1626 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1627 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1628 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1629 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1630 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1634 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1636 // Define new assembler match classes as we want to only match these when
1637 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1638 // associate a DiagnosticType either, as we want the diagnostic for the
1639 // canonical form (the scaled operand) to take precedence.
1640 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1641 let Name = "SImm9OffsetFB" # Width;
1642 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1643 let RenderMethod = "addImmOperands";
1646 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1647 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1648 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1649 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1650 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1652 def simm9_offset_fb8 : Operand<i64> {
1653 let ParserMatchClass = SImm9OffsetFB8Operand;
1655 def simm9_offset_fb16 : Operand<i64> {
1656 let ParserMatchClass = SImm9OffsetFB16Operand;
1658 def simm9_offset_fb32 : Operand<i64> {
1659 let ParserMatchClass = SImm9OffsetFB32Operand;
1661 def simm9_offset_fb64 : Operand<i64> {
1662 let ParserMatchClass = SImm9OffsetFB64Operand;
1664 def simm9_offset_fb128 : Operand<i64> {
1665 let ParserMatchClass = SImm9OffsetFB128Operand;
1668 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1669 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1670 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1671 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1672 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1673 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1674 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1675 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1676 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1677 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1678 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1679 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1680 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1681 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1684 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1685 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1686 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1687 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1689 // load sign-extended half-word
1691 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1693 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1695 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1697 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1699 // load sign-extended byte
1701 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1703 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1705 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1707 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1709 // load sign-extended word
1711 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1713 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1715 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1716 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1717 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1718 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1719 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1720 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1721 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1722 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1723 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1724 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1725 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1726 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1727 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1728 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1729 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1732 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1733 [(AArch64Prefetch imm:$Rt,
1734 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1737 // (unscaled immediate, unprivileged)
1738 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1739 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1741 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1742 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1744 // load sign-extended half-word
1745 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1746 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1748 // load sign-extended byte
1749 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1750 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1752 // load sign-extended word
1753 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1756 // (immediate pre-indexed)
1757 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1758 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1759 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1760 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1761 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1762 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1763 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1765 // load sign-extended half-word
1766 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1767 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1769 // load sign-extended byte
1770 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1771 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1773 // load zero-extended byte
1774 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1775 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1777 // load sign-extended word
1778 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1781 // (immediate post-indexed)
1782 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1783 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1784 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1785 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1786 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1787 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1788 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1790 // load sign-extended half-word
1791 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1792 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1794 // load sign-extended byte
1795 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1796 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1798 // load zero-extended byte
1799 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1800 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1802 // load sign-extended word
1803 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1805 //===----------------------------------------------------------------------===//
1806 // Store instructions.
1807 //===----------------------------------------------------------------------===//
1809 // Pair (indexed, offset)
1810 // FIXME: Use dedicated range-checked addressing mode operand here.
1811 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1812 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1813 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1814 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1815 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1817 // Pair (pre-indexed)
1818 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1819 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1820 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1821 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1822 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1824 // Pair (pre-indexed)
1825 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1826 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1827 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1828 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1829 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1831 // Pair (no allocate)
1832 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1833 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1834 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1835 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1836 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1839 // (Register offset)
1842 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1843 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1844 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1845 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1849 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1850 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1851 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1852 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1853 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1855 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1856 Instruction STRW, Instruction STRX> {
1858 def : Pat<(storeop GPR64:$Rt,
1859 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1860 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1861 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1863 def : Pat<(storeop GPR64:$Rt,
1864 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1865 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1866 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1869 let AddedComplexity = 10 in {
1871 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1872 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1873 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1876 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1877 Instruction STRW, Instruction STRX> {
1878 def : Pat<(store (VecTy FPR:$Rt),
1879 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1880 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1882 def : Pat<(store (VecTy FPR:$Rt),
1883 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1884 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1887 let AddedComplexity = 10 in {
1888 // Match all store 64 bits width whose type is compatible with FPR64
1889 let Predicates = [IsLE] in {
1890 // We must use ST1 to store vectors in big-endian.
1891 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1892 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1893 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1894 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1895 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1898 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1899 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1901 // Match all store 128 bits width whose type is compatible with FPR128
1902 let Predicates = [IsLE] in {
1903 // We must use ST1 to store vectors in big-endian.
1904 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1905 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1906 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1907 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1908 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1909 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1910 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
1912 } // AddedComplexity = 10
1914 // Match stores from lane 0 to the appropriate subreg's store.
1915 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
1916 ValueType VecTy, ValueType STy,
1917 SubRegIndex SubRegIdx,
1918 Instruction STRW, Instruction STRX> {
1920 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
1921 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1922 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
1923 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1925 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
1926 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1927 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
1928 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1931 let AddedComplexity = 19 in {
1932 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
1933 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
1934 defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
1935 defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
1936 defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
1937 defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
1938 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
1942 // (unsigned immediate)
1943 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1945 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1946 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1948 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1949 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1951 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
1952 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1953 [(store (f16 FPR16:$Rt),
1954 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
1955 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1956 [(store (f32 FPR32:$Rt),
1957 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1958 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1959 [(store (f64 FPR64:$Rt),
1960 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1961 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1963 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1964 [(truncstorei16 GPR32:$Rt,
1965 (am_indexed16 GPR64sp:$Rn,
1966 uimm12s2:$offset))]>;
1967 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
1968 [(truncstorei8 GPR32:$Rt,
1969 (am_indexed8 GPR64sp:$Rn,
1970 uimm12s1:$offset))]>;
1972 // Match all store 64 bits width whose type is compatible with FPR64
1973 let AddedComplexity = 10 in {
1974 let Predicates = [IsLE] in {
1975 // We must use ST1 to store vectors in big-endian.
1976 def : Pat<(store (v2f32 FPR64:$Rt),
1977 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1978 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1979 def : Pat<(store (v8i8 FPR64:$Rt),
1980 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1981 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1982 def : Pat<(store (v4i16 FPR64:$Rt),
1983 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1984 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1985 def : Pat<(store (v2i32 FPR64:$Rt),
1986 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1987 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1988 def : Pat<(store (v4f16 FPR64:$Rt),
1989 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1990 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1992 def : Pat<(store (v1f64 FPR64:$Rt),
1993 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1994 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1995 def : Pat<(store (v1i64 FPR64:$Rt),
1996 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1997 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1999 // Match all store 128 bits width whose type is compatible with FPR128
2000 let Predicates = [IsLE] in {
2001 // We must use ST1 to store vectors in big-endian.
2002 def : Pat<(store (v4f32 FPR128:$Rt),
2003 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2004 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2005 def : Pat<(store (v2f64 FPR128:$Rt),
2006 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2007 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2008 def : Pat<(store (v16i8 FPR128:$Rt),
2009 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2010 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2011 def : Pat<(store (v8i16 FPR128:$Rt),
2012 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2013 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2014 def : Pat<(store (v4i32 FPR128:$Rt),
2015 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2016 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2017 def : Pat<(store (v2i64 FPR128:$Rt),
2018 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2019 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2020 def : Pat<(store (v8f16 FPR128:$Rt),
2021 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2022 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2024 def : Pat<(store (f128 FPR128:$Rt),
2025 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2026 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2029 def : Pat<(truncstorei32 GPR64:$Rt,
2030 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
2031 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2032 def : Pat<(truncstorei16 GPR64:$Rt,
2033 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2034 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
2035 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
2036 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
2038 } // AddedComplexity = 10
2041 // (unscaled immediate)
2042 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2044 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2045 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2047 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2048 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2050 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2051 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2052 [(store (f16 FPR16:$Rt),
2053 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2054 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2055 [(store (f32 FPR32:$Rt),
2056 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2057 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2058 [(store (f64 FPR64:$Rt),
2059 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2060 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2061 [(store (f128 FPR128:$Rt),
2062 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2063 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2064 [(truncstorei16 GPR32:$Rt,
2065 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2066 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2067 [(truncstorei8 GPR32:$Rt,
2068 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2070 // Match all store 64 bits width whose type is compatible with FPR64
2071 let Predicates = [IsLE] in {
2072 // We must use ST1 to store vectors in big-endian.
2073 def : Pat<(store (v2f32 FPR64:$Rt),
2074 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2075 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2076 def : Pat<(store (v8i8 FPR64:$Rt),
2077 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2078 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2079 def : Pat<(store (v4i16 FPR64:$Rt),
2080 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2081 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2082 def : Pat<(store (v2i32 FPR64:$Rt),
2083 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2084 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2085 def : Pat<(store (v4f16 FPR64:$Rt),
2086 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2087 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2089 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2090 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2091 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2092 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2094 // Match all store 128 bits width whose type is compatible with FPR128
2095 let Predicates = [IsLE] in {
2096 // We must use ST1 to store vectors in big-endian.
2097 def : Pat<(store (v4f32 FPR128:$Rt),
2098 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2099 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2100 def : Pat<(store (v2f64 FPR128:$Rt),
2101 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2102 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2103 def : Pat<(store (v16i8 FPR128:$Rt),
2104 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2105 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2106 def : Pat<(store (v8i16 FPR128:$Rt),
2107 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2108 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2109 def : Pat<(store (v4i32 FPR128:$Rt),
2110 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2111 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2112 def : Pat<(store (v2i64 FPR128:$Rt),
2113 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2114 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2115 def : Pat<(store (v2f64 FPR128:$Rt),
2116 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2117 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2118 def : Pat<(store (v8f16 FPR128:$Rt),
2119 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2120 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2123 // unscaled i64 truncating stores
2124 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2125 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2126 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2127 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2128 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2129 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2132 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2133 def : InstAlias<"str $Rt, [$Rn, $offset]",
2134 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2135 def : InstAlias<"str $Rt, [$Rn, $offset]",
2136 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2137 def : InstAlias<"str $Rt, [$Rn, $offset]",
2138 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2139 def : InstAlias<"str $Rt, [$Rn, $offset]",
2140 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2141 def : InstAlias<"str $Rt, [$Rn, $offset]",
2142 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2143 def : InstAlias<"str $Rt, [$Rn, $offset]",
2144 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2145 def : InstAlias<"str $Rt, [$Rn, $offset]",
2146 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2148 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2149 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2150 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2151 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2154 // (unscaled immediate, unprivileged)
2155 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2156 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2158 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2159 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2162 // (immediate pre-indexed)
2163 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2164 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2165 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2166 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2167 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2168 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2169 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2171 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2172 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2175 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2176 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2178 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2179 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2181 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2182 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2185 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2186 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2187 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2188 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2189 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2190 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2191 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2192 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2193 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2194 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2195 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2196 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2197 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2198 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2200 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2201 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2202 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2203 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2204 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2205 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2206 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2207 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2208 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2209 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2210 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2211 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2212 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2213 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2216 // (immediate post-indexed)
2217 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2218 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2219 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2220 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2221 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2222 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2223 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2225 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2226 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2229 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2230 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2232 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2233 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2235 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2236 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2239 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2240 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2241 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2242 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2243 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2244 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2245 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2246 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2247 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2248 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2249 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2250 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2251 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2252 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2254 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2255 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2256 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2257 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2258 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2259 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2260 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2261 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2262 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2263 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2264 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2265 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2266 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2267 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2269 //===----------------------------------------------------------------------===//
2270 // Load/store exclusive instructions.
2271 //===----------------------------------------------------------------------===//
2273 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2274 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2275 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2276 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2278 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2279 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2280 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2281 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2283 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2284 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2285 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2286 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2288 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2289 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2290 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2291 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2293 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2294 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2295 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2296 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2298 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2299 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2300 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2301 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2303 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2304 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2306 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2307 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2309 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2310 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2312 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2313 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2315 //===----------------------------------------------------------------------===//
2316 // Scaled floating point to integer conversion instructions.
2317 //===----------------------------------------------------------------------===//
2319 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2320 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2321 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2322 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2323 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2324 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2325 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2326 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2327 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2328 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2329 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2330 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2331 let isCodeGenOnly = 1 in {
2332 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2333 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2334 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2335 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2338 //===----------------------------------------------------------------------===//
2339 // Scaled integer to floating point conversion instructions.
2340 //===----------------------------------------------------------------------===//
2342 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2343 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2345 //===----------------------------------------------------------------------===//
2346 // Unscaled integer to floating point conversion instruction.
2347 //===----------------------------------------------------------------------===//
2349 defm FMOV : UnscaledConversion<"fmov">;
2351 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
2352 let isReMaterializable = 1, isCodeGenOnly = 1 in {
2353 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
2354 PseudoInstExpansion<(FMOVWSr FPR32:$Rd, WZR)>,
2356 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
2357 PseudoInstExpansion<(FMOVXDr FPR64:$Rd, XZR)>,
2361 //===----------------------------------------------------------------------===//
2362 // Floating point conversion instruction.
2363 //===----------------------------------------------------------------------===//
2365 defm FCVT : FPConversion<"fcvt">;
2367 //===----------------------------------------------------------------------===//
2368 // Floating point single operand instructions.
2369 //===----------------------------------------------------------------------===//
2371 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2372 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2373 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2374 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2375 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2376 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2377 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2378 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2380 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2381 (FRINTNDr FPR64:$Rn)>;
2383 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2384 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2385 // <rdar://problem/13715968>
2386 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2387 let hasSideEffects = 1 in {
2388 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2391 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2393 let SchedRW = [WriteFDiv] in {
2394 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2397 //===----------------------------------------------------------------------===//
2398 // Floating point two operand instructions.
2399 //===----------------------------------------------------------------------===//
2401 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2402 let SchedRW = [WriteFDiv] in {
2403 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2405 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2406 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2407 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2408 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2409 let SchedRW = [WriteFMul] in {
2410 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2411 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2413 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2415 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2416 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2417 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2418 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2419 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2420 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2421 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2422 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2424 //===----------------------------------------------------------------------===//
2425 // Floating point three operand instructions.
2426 //===----------------------------------------------------------------------===//
2428 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2429 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2430 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2431 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2432 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2433 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2434 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2436 // The following def pats catch the case where the LHS of an FMA is negated.
2437 // The TriOpFrag above catches the case where the middle operand is negated.
2439 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2440 // the NEON variant.
2441 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2442 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2444 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2445 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2447 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2449 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2450 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2452 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2453 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2455 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2456 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2458 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2459 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2461 //===----------------------------------------------------------------------===//
2462 // Floating point comparison instructions.
2463 //===----------------------------------------------------------------------===//
2465 defm FCMPE : FPComparison<1, "fcmpe">;
2466 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2468 //===----------------------------------------------------------------------===//
2469 // Floating point conditional comparison instructions.
2470 //===----------------------------------------------------------------------===//
2472 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2473 defm FCCMP : FPCondComparison<0, "fccmp">;
2475 //===----------------------------------------------------------------------===//
2476 // Floating point conditional select instruction.
2477 //===----------------------------------------------------------------------===//
2479 defm FCSEL : FPCondSelect<"fcsel">;
2481 // CSEL instructions providing f128 types need to be handled by a
2482 // pseudo-instruction since the eventual code will need to introduce basic
2483 // blocks and control flow.
2484 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2485 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2486 [(set (f128 FPR128:$Rd),
2487 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2488 (i32 imm:$cond), NZCV))]> {
2490 let usesCustomInserter = 1;
2494 //===----------------------------------------------------------------------===//
2495 // Floating point immediate move.
2496 //===----------------------------------------------------------------------===//
2498 let isReMaterializable = 1 in {
2499 defm FMOV : FPMoveImmediate<"fmov">;
2502 //===----------------------------------------------------------------------===//
2503 // Advanced SIMD two vector instructions.
2504 //===----------------------------------------------------------------------===//
2506 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2507 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2508 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2509 (ABSv8i8 V64:$src)>;
2510 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2511 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2512 (ABSv4i16 V64:$src)>;
2513 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2514 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2515 (ABSv2i32 V64:$src)>;
2516 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2517 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2518 (ABSv16i8 V128:$src)>;
2519 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2520 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2521 (ABSv8i16 V128:$src)>;
2522 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2523 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2524 (ABSv4i32 V128:$src)>;
2525 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2526 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2527 (ABSv2i64 V128:$src)>;
2529 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2530 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2531 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2532 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2533 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2534 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2535 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2536 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2537 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2539 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2540 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2541 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2542 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2543 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2544 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2545 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2546 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2547 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2548 (FCVTLv4i16 V64:$Rn)>;
2549 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2551 (FCVTLv8i16 V128:$Rn)>;
2552 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2553 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2555 (FCVTLv4i32 V128:$Rn)>;
2557 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2558 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2560 (FCVTLv8i16 V128:$Rn)>;
2562 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2563 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2564 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2565 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2566 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2567 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2568 (FCVTNv4i16 V128:$Rn)>;
2569 def : Pat<(concat_vectors V64:$Rd,
2570 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2571 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2572 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2573 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2574 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2575 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2576 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2577 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2578 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2579 int_aarch64_neon_fcvtxn>;
2580 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2581 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2582 let isCodeGenOnly = 1 in {
2583 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2584 int_aarch64_neon_fcvtzs>;
2585 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2586 int_aarch64_neon_fcvtzu>;
2588 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2589 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2590 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2591 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2592 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2593 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2594 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2595 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2596 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2597 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2598 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2599 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2600 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2601 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2602 // Aliases for MVN -> NOT.
2603 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2604 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2605 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2606 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2608 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2609 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2610 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2611 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2612 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2613 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2614 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2616 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2617 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2618 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2619 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2620 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2621 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2622 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2623 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2625 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2626 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2627 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2628 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2629 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2631 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2632 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2633 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2634 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2635 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2636 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2637 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2638 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2639 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2640 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2641 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2642 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2643 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2644 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2645 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2646 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2647 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2648 int_aarch64_neon_uaddlp>;
2649 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2650 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2651 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2652 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2653 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2654 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2656 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2657 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2658 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2659 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2660 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2661 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2663 // Patterns for vector long shift (by element width). These need to match all
2664 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2666 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2667 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2668 (SHLLv8i8 V64:$Rn)>;
2669 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2670 (SHLLv16i8 V128:$Rn)>;
2671 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2672 (SHLLv4i16 V64:$Rn)>;
2673 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2674 (SHLLv8i16 V128:$Rn)>;
2675 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2676 (SHLLv2i32 V64:$Rn)>;
2677 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2678 (SHLLv4i32 V128:$Rn)>;
2681 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2682 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2683 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2685 //===----------------------------------------------------------------------===//
2686 // Advanced SIMD three vector instructions.
2687 //===----------------------------------------------------------------------===//
2689 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2690 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2691 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2692 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2693 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2694 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2695 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2696 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2697 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2698 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2699 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2700 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2701 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2702 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2703 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2704 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2705 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2706 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2707 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2708 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2709 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2710 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2711 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2712 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2713 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2715 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2716 // instruction expects the addend first, while the fma intrinsic puts it last.
2717 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2718 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2719 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2720 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2722 // The following def pats catch the case where the LHS of an FMA is negated.
2723 // The TriOpFrag above catches the case where the middle operand is negated.
2724 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2725 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2727 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2728 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2730 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2731 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2733 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2734 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2735 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2736 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2737 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2738 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2739 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2740 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2741 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2742 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2743 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2744 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2745 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2746 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2747 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2748 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2749 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2750 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2751 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2752 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2753 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2754 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2755 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2756 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2757 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2758 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2759 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2760 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2761 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2762 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2763 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2764 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2765 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2766 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2767 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2768 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2769 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2770 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2771 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2772 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2773 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2774 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2775 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2776 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2777 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2778 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2780 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2781 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2782 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2783 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2784 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2785 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2786 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2787 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2788 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2789 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2790 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2792 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2793 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2794 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2795 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2796 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2797 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2798 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2799 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2801 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2802 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2803 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2804 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2805 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2806 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2807 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2808 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2810 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2811 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2812 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2813 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2814 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2815 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2816 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2817 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2819 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2820 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2821 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2822 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2823 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2824 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2825 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2826 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2828 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2829 "|cmls.8b\t$dst, $src1, $src2}",
2830 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2831 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2832 "|cmls.16b\t$dst, $src1, $src2}",
2833 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2834 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2835 "|cmls.4h\t$dst, $src1, $src2}",
2836 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2837 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2838 "|cmls.8h\t$dst, $src1, $src2}",
2839 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2840 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2841 "|cmls.2s\t$dst, $src1, $src2}",
2842 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2843 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2844 "|cmls.4s\t$dst, $src1, $src2}",
2845 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2846 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2847 "|cmls.2d\t$dst, $src1, $src2}",
2848 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2850 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2851 "|cmlo.8b\t$dst, $src1, $src2}",
2852 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2853 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2854 "|cmlo.16b\t$dst, $src1, $src2}",
2855 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2856 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2857 "|cmlo.4h\t$dst, $src1, $src2}",
2858 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2859 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2860 "|cmlo.8h\t$dst, $src1, $src2}",
2861 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2862 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2863 "|cmlo.2s\t$dst, $src1, $src2}",
2864 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2865 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2866 "|cmlo.4s\t$dst, $src1, $src2}",
2867 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2868 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2869 "|cmlo.2d\t$dst, $src1, $src2}",
2870 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2872 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2873 "|cmle.8b\t$dst, $src1, $src2}",
2874 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2875 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2876 "|cmle.16b\t$dst, $src1, $src2}",
2877 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2878 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2879 "|cmle.4h\t$dst, $src1, $src2}",
2880 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2881 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2882 "|cmle.8h\t$dst, $src1, $src2}",
2883 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2884 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2885 "|cmle.2s\t$dst, $src1, $src2}",
2886 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2887 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2888 "|cmle.4s\t$dst, $src1, $src2}",
2889 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2890 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2891 "|cmle.2d\t$dst, $src1, $src2}",
2892 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2894 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2895 "|cmlt.8b\t$dst, $src1, $src2}",
2896 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2897 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2898 "|cmlt.16b\t$dst, $src1, $src2}",
2899 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2900 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2901 "|cmlt.4h\t$dst, $src1, $src2}",
2902 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2903 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2904 "|cmlt.8h\t$dst, $src1, $src2}",
2905 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2906 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2907 "|cmlt.2s\t$dst, $src1, $src2}",
2908 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2909 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2910 "|cmlt.4s\t$dst, $src1, $src2}",
2911 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2912 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2913 "|cmlt.2d\t$dst, $src1, $src2}",
2914 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2916 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2917 "|fcmle.2s\t$dst, $src1, $src2}",
2918 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2919 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2920 "|fcmle.4s\t$dst, $src1, $src2}",
2921 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2922 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2923 "|fcmle.2d\t$dst, $src1, $src2}",
2924 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2926 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2927 "|fcmlt.2s\t$dst, $src1, $src2}",
2928 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2929 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2930 "|fcmlt.4s\t$dst, $src1, $src2}",
2931 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2932 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2933 "|fcmlt.2d\t$dst, $src1, $src2}",
2934 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2936 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2937 "|facle.2s\t$dst, $src1, $src2}",
2938 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2939 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2940 "|facle.4s\t$dst, $src1, $src2}",
2941 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2942 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2943 "|facle.2d\t$dst, $src1, $src2}",
2944 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2946 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2947 "|faclt.2s\t$dst, $src1, $src2}",
2948 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2949 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2950 "|faclt.4s\t$dst, $src1, $src2}",
2951 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2952 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2953 "|faclt.2d\t$dst, $src1, $src2}",
2954 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2956 //===----------------------------------------------------------------------===//
2957 // Advanced SIMD three scalar instructions.
2958 //===----------------------------------------------------------------------===//
2960 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2961 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
2962 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
2963 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
2964 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
2965 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
2966 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
2967 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
2968 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2969 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2970 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2971 int_aarch64_neon_facge>;
2972 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2973 int_aarch64_neon_facgt>;
2974 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2975 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2976 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2977 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
2978 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
2979 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
2980 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
2981 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
2982 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
2983 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
2984 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
2985 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
2986 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
2987 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
2988 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2989 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
2990 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
2991 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
2992 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
2993 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
2994 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
2996 def : InstAlias<"cmls $dst, $src1, $src2",
2997 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2998 def : InstAlias<"cmle $dst, $src1, $src2",
2999 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3000 def : InstAlias<"cmlo $dst, $src1, $src2",
3001 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3002 def : InstAlias<"cmlt $dst, $src1, $src2",
3003 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3004 def : InstAlias<"fcmle $dst, $src1, $src2",
3005 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3006 def : InstAlias<"fcmle $dst, $src1, $src2",
3007 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3008 def : InstAlias<"fcmlt $dst, $src1, $src2",
3009 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3010 def : InstAlias<"fcmlt $dst, $src1, $src2",
3011 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3012 def : InstAlias<"facle $dst, $src1, $src2",
3013 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3014 def : InstAlias<"facle $dst, $src1, $src2",
3015 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3016 def : InstAlias<"faclt $dst, $src1, $src2",
3017 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3018 def : InstAlias<"faclt $dst, $src1, $src2",
3019 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3021 //===----------------------------------------------------------------------===//
3022 // Advanced SIMD three scalar instructions (mixed operands).
3023 //===----------------------------------------------------------------------===//
3024 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3025 int_aarch64_neon_sqdmulls_scalar>;
3026 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
3027 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3029 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3030 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3031 (i32 FPR32:$Rm))))),
3032 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3033 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3034 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3035 (i32 FPR32:$Rm))))),
3036 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3038 //===----------------------------------------------------------------------===//
3039 // Advanced SIMD two scalar instructions.
3040 //===----------------------------------------------------------------------===//
3042 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
3043 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3044 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3045 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3046 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3047 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3048 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3049 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3050 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3051 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3052 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3053 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
3054 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
3055 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
3056 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
3057 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
3058 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
3059 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
3060 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
3061 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3062 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
3063 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
3064 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
3065 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
3066 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
3067 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3068 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3069 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3070 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3071 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3072 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3073 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3074 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3075 int_aarch64_neon_suqadd>;
3076 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3077 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3078 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3079 int_aarch64_neon_usqadd>;
3081 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3083 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3084 (FCVTASv1i64 FPR64:$Rn)>;
3085 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3086 (FCVTAUv1i64 FPR64:$Rn)>;
3087 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3088 (FCVTMSv1i64 FPR64:$Rn)>;
3089 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3090 (FCVTMUv1i64 FPR64:$Rn)>;
3091 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3092 (FCVTNSv1i64 FPR64:$Rn)>;
3093 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3094 (FCVTNUv1i64 FPR64:$Rn)>;
3095 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3096 (FCVTPSv1i64 FPR64:$Rn)>;
3097 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3098 (FCVTPUv1i64 FPR64:$Rn)>;
3100 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3101 (FRECPEv1i32 FPR32:$Rn)>;
3102 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3103 (FRECPEv1i64 FPR64:$Rn)>;
3104 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3105 (FRECPEv1i64 FPR64:$Rn)>;
3107 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3108 (FRECPXv1i32 FPR32:$Rn)>;
3109 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3110 (FRECPXv1i64 FPR64:$Rn)>;
3112 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3113 (FRSQRTEv1i32 FPR32:$Rn)>;
3114 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3115 (FRSQRTEv1i64 FPR64:$Rn)>;
3116 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3117 (FRSQRTEv1i64 FPR64:$Rn)>;
3119 // If an integer is about to be converted to a floating point value,
3120 // just load it on the floating point unit.
3121 // Here are the patterns for 8 and 16-bits to float.
3123 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3124 SDPatternOperator loadop, Instruction UCVTF,
3125 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3127 def : Pat<(DstTy (uint_to_fp (SrcTy
3128 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3129 ro.Wext:$extend))))),
3130 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3131 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3134 def : Pat<(DstTy (uint_to_fp (SrcTy
3135 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3136 ro.Wext:$extend))))),
3137 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3138 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3142 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3143 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3144 def : Pat <(f32 (uint_to_fp (i32
3145 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3146 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3147 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3148 def : Pat <(f32 (uint_to_fp (i32
3149 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3150 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3151 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3152 // 16-bits -> float.
3153 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3154 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3155 def : Pat <(f32 (uint_to_fp (i32
3156 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3157 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3158 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3159 def : Pat <(f32 (uint_to_fp (i32
3160 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3161 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3162 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3163 // 32-bits are handled in target specific dag combine:
3164 // performIntToFpCombine.
3165 // 64-bits integer to 32-bits floating point, not possible with
3166 // UCVTF on floating point registers (both source and destination
3167 // must have the same size).
3169 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3170 // 8-bits -> double.
3171 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3172 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3173 def : Pat <(f64 (uint_to_fp (i32
3174 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3175 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3176 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3177 def : Pat <(f64 (uint_to_fp (i32
3178 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3179 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3180 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3181 // 16-bits -> double.
3182 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3183 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3184 def : Pat <(f64 (uint_to_fp (i32
3185 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3186 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3187 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3188 def : Pat <(f64 (uint_to_fp (i32
3189 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3190 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3191 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3192 // 32-bits -> double.
3193 defm : UIntToFPROLoadPat<f64, i32, load,
3194 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3195 def : Pat <(f64 (uint_to_fp (i32
3196 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3197 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3198 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3199 def : Pat <(f64 (uint_to_fp (i32
3200 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3201 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3202 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3203 // 64-bits -> double are handled in target specific dag combine:
3204 // performIntToFpCombine.
3206 //===----------------------------------------------------------------------===//
3207 // Advanced SIMD three different-sized vector instructions.
3208 //===----------------------------------------------------------------------===//
3210 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3211 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3212 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3213 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3214 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3215 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3216 int_aarch64_neon_sabd>;
3217 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3218 int_aarch64_neon_sabd>;
3219 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3220 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3221 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3222 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3223 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3224 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3225 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3226 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3227 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3228 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3229 int_aarch64_neon_sqadd>;
3230 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3231 int_aarch64_neon_sqsub>;
3232 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3233 int_aarch64_neon_sqdmull>;
3234 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3235 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3236 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3237 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3238 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3239 int_aarch64_neon_uabd>;
3240 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3241 int_aarch64_neon_uabd>;
3242 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3243 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3244 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3245 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3246 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3247 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3248 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3249 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3250 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3251 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3252 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3253 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3254 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3256 // Additional patterns for SMULL and UMULL
3257 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3258 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3259 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3260 (INST8B V64:$Rn, V64:$Rm)>;
3261 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3262 (INST4H V64:$Rn, V64:$Rm)>;
3263 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3264 (INST2S V64:$Rn, V64:$Rm)>;
3267 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3268 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3269 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3270 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3272 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3273 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3274 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3275 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3276 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3277 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3278 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3279 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3280 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3283 defm : Neon_mulacc_widen_patterns<
3284 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3285 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3286 defm : Neon_mulacc_widen_patterns<
3287 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3288 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3289 defm : Neon_mulacc_widen_patterns<
3290 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3291 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3292 defm : Neon_mulacc_widen_patterns<
3293 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3294 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3296 // Patterns for 64-bit pmull
3297 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3298 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3299 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3300 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3301 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3303 // CodeGen patterns for addhn and subhn instructions, which can actually be
3304 // written in LLVM IR without too much difficulty.
3307 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3308 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3309 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3311 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3312 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3314 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3315 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3316 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3318 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3319 V128:$Rn, V128:$Rm)>;
3320 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3321 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3323 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3324 V128:$Rn, V128:$Rm)>;
3325 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3326 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3328 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3329 V128:$Rn, V128:$Rm)>;
3332 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3333 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3334 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3336 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3337 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3339 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3340 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3341 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3343 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3344 V128:$Rn, V128:$Rm)>;
3345 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3346 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3348 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3349 V128:$Rn, V128:$Rm)>;
3350 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3351 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3353 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3354 V128:$Rn, V128:$Rm)>;
3356 //----------------------------------------------------------------------------
3357 // AdvSIMD bitwise extract from vector instruction.
3358 //----------------------------------------------------------------------------
3360 defm EXT : SIMDBitwiseExtract<"ext">;
3362 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3363 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3364 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3365 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3366 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3367 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3368 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3369 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3370 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3371 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3372 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3373 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3374 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3375 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3376 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3377 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3378 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3379 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3380 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3381 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3383 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3385 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3386 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3387 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3388 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3389 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3390 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3391 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3392 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3393 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3394 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3395 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3396 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3397 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3398 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3401 //----------------------------------------------------------------------------
3402 // AdvSIMD zip vector
3403 //----------------------------------------------------------------------------
3405 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3406 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3407 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3408 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3409 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3410 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3412 //----------------------------------------------------------------------------
3413 // AdvSIMD TBL/TBX instructions
3414 //----------------------------------------------------------------------------
3416 defm TBL : SIMDTableLookup< 0, "tbl">;
3417 defm TBX : SIMDTableLookupTied<1, "tbx">;
3419 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3420 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3421 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3422 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3424 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3425 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3426 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3427 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3428 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3429 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3432 //----------------------------------------------------------------------------
3433 // AdvSIMD scalar CPY instruction
3434 //----------------------------------------------------------------------------
3436 defm CPY : SIMDScalarCPY<"cpy">;
3438 //----------------------------------------------------------------------------
3439 // AdvSIMD scalar pairwise instructions
3440 //----------------------------------------------------------------------------
3442 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3443 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3444 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3445 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3446 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3447 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3448 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
3449 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3450 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),
3451 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3452 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3453 (FADDPv2i32p V64:$Rn)>;
3454 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3455 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3456 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3457 (FADDPv2i64p V128:$Rn)>;
3458 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3459 (FMAXNMPv2i32p V64:$Rn)>;
3460 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3461 (FMAXNMPv2i64p V128:$Rn)>;
3462 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3463 (FMAXPv2i32p V64:$Rn)>;
3464 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3465 (FMAXPv2i64p V128:$Rn)>;
3466 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3467 (FMINNMPv2i32p V64:$Rn)>;
3468 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3469 (FMINNMPv2i64p V128:$Rn)>;
3470 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3471 (FMINPv2i32p V64:$Rn)>;
3472 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3473 (FMINPv2i64p V128:$Rn)>;
3475 //----------------------------------------------------------------------------
3476 // AdvSIMD INS/DUP instructions
3477 //----------------------------------------------------------------------------
3479 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3480 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3481 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3482 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3483 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3484 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3485 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3487 def DUPv2i64lane : SIMDDup64FromElement;
3488 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3489 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3490 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3491 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3492 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3493 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3495 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3496 (v2f32 (DUPv2i32lane
3497 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3499 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3500 (v4f32 (DUPv4i32lane
3501 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3503 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3504 (v2f64 (DUPv2i64lane
3505 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3507 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3508 (v4f16 (DUPv4i16lane
3509 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3511 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3512 (v8f16 (DUPv8i16lane
3513 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3516 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3517 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3518 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3519 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3521 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3522 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3523 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3524 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3525 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3526 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3528 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3529 // instruction even if the types don't match: we just have to remap the lane
3530 // carefully. N.b. this trick only applies to truncations.
3531 def VecIndex_x2 : SDNodeXForm<imm, [{
3532 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3534 def VecIndex_x4 : SDNodeXForm<imm, [{
3535 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3537 def VecIndex_x8 : SDNodeXForm<imm, [{
3538 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3541 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3542 ValueType Src128VT, ValueType ScalVT,
3543 Instruction DUP, SDNodeXForm IdxXFORM> {
3544 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3546 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3548 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3550 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3553 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3554 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3555 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3557 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3558 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3559 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3561 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3562 SDNodeXForm IdxXFORM> {
3563 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3565 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3567 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3569 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3572 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3573 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3574 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3576 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3577 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3578 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3580 // SMOV and UMOV definitions, with some extra patterns for convenience
3584 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3585 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3586 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3587 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3588 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3589 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3590 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3591 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3592 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3593 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3594 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3595 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3597 // Extracting i8 or i16 elements will have the zero-extend transformed to
3598 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3599 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3600 // bits of the destination register.
3601 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3603 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3604 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3606 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3610 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3611 (SUBREG_TO_REG (i32 0),
3612 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3613 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3614 (SUBREG_TO_REG (i32 0),
3615 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3617 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3618 (SUBREG_TO_REG (i32 0),
3619 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3620 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3621 (SUBREG_TO_REG (i32 0),
3622 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3624 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3625 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3626 (i32 FPR32:$Rn), ssub))>;
3627 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3628 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3629 (i32 FPR32:$Rn), ssub))>;
3630 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3631 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3632 (i64 FPR64:$Rn), dsub))>;
3634 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3635 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3636 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3637 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3638 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3639 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3641 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3642 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3645 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3647 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3651 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3652 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3654 V128:$Rn, VectorIndexH:$imm,
3655 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3658 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3659 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3662 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3664 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3667 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3668 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3670 V128:$Rn, VectorIndexS:$imm,
3671 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3673 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3674 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3676 V128:$Rn, VectorIndexD:$imm,
3677 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3680 // Copy an element at a constant index in one vector into a constant indexed
3681 // element of another.
3682 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3683 // index type and INS extension
3684 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3685 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3686 VectorIndexB:$idx2)),
3688 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3690 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3691 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3692 VectorIndexH:$idx2)),
3694 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3696 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3697 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3698 VectorIndexS:$idx2)),
3700 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3702 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3703 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3704 VectorIndexD:$idx2)),
3706 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3709 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3710 ValueType VTScal, Instruction INS> {
3711 def : Pat<(VT128 (vector_insert V128:$src,
3712 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3714 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3716 def : Pat<(VT128 (vector_insert V128:$src,
3717 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3719 (INS V128:$src, imm:$Immd,
3720 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3722 def : Pat<(VT64 (vector_insert V64:$src,
3723 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3725 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3726 imm:$Immd, V128:$Rn, imm:$Immn),
3729 def : Pat<(VT64 (vector_insert V64:$src,
3730 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3733 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3734 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3738 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3739 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3740 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3743 // Floating point vector extractions are codegen'd as either a sequence of
3744 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
3745 // the lane number is anything other than zero.
3746 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3747 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3748 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3749 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3750 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3751 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3753 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3754 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
3755 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3756 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
3757 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3758 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
3760 // All concat_vectors operations are canonicalised to act on i64 vectors for
3761 // AArch64. In the general case we need an instruction, which had just as well be
3763 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3764 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3765 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3766 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3768 def : ConcatPat<v2i64, v1i64>;
3769 def : ConcatPat<v2f64, v1f64>;
3770 def : ConcatPat<v4i32, v2i32>;
3771 def : ConcatPat<v4f32, v2f32>;
3772 def : ConcatPat<v8i16, v4i16>;
3773 def : ConcatPat<v8f16, v4f16>;
3774 def : ConcatPat<v16i8, v8i8>;
3776 // If the high lanes are undef, though, we can just ignore them:
3777 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3778 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3779 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3781 def : ConcatUndefPat<v2i64, v1i64>;
3782 def : ConcatUndefPat<v2f64, v1f64>;
3783 def : ConcatUndefPat<v4i32, v2i32>;
3784 def : ConcatUndefPat<v4f32, v2f32>;
3785 def : ConcatUndefPat<v8i16, v4i16>;
3786 def : ConcatUndefPat<v16i8, v8i8>;
3788 //----------------------------------------------------------------------------
3789 // AdvSIMD across lanes instructions
3790 //----------------------------------------------------------------------------
3792 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3793 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3794 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3795 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3796 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3797 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3798 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3799 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3800 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3801 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3802 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3804 // Patterns for across-vector intrinsics, that have a node equivalent, that
3805 // returns a vector (with only the low lane defined) instead of a scalar.
3806 // In effect, opNode is the same as (scalar_to_vector (IntNode)).
3807 multiclass SIMDAcrossLanesIntrinsic<string baseOpc,
3808 SDPatternOperator opNode> {
3809 // If a lane instruction caught the vector_extract around opNode, we can
3810 // directly match the latter to the instruction.
3811 def : Pat<(v8i8 (opNode V64:$Rn)),
3812 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3813 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;
3814 def : Pat<(v16i8 (opNode V128:$Rn)),
3815 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3816 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;
3817 def : Pat<(v4i16 (opNode V64:$Rn)),
3818 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3819 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;
3820 def : Pat<(v8i16 (opNode V128:$Rn)),
3821 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3822 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;
3823 def : Pat<(v4i32 (opNode V128:$Rn)),
3824 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3825 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;
3828 // If none did, fallback to the explicit patterns, consuming the vector_extract.
3829 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
3830 (i32 0)), (i64 0))),
3831 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3832 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),
3834 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
3835 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3836 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),
3838 def : Pat<(i32 (vector_extract (insert_subvector undef,
3839 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))),
3840 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3841 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),
3843 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
3844 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3845 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),
3847 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
3848 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3849 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),
3854 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,
3855 SDPatternOperator opNode>
3856 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
3857 // If there is a sign extension after this intrinsic, consume it as smov already
3859 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
3860 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)),
3862 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3863 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3865 def : Pat<(i32 (sext_inreg (i32 (vector_extract
3866 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),
3868 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3869 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3871 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
3872 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)),
3874 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3875 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3877 def : Pat<(i32 (sext_inreg (i32 (vector_extract
3878 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),
3880 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3881 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3885 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
3886 SDPatternOperator opNode>
3887 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
3888 // If there is a masking operation keeping only what has been actually
3889 // generated, consume it.
3890 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
3891 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)),
3892 (i32 (EXTRACT_SUBREG
3893 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3894 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3896 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
3898 (i32 (EXTRACT_SUBREG
3899 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3900 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3902 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
3903 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)),
3904 (i32 (EXTRACT_SUBREG
3905 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3906 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3908 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
3910 (i32 (EXTRACT_SUBREG
3911 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3912 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3916 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;
3917 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3918 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
3919 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
3921 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;
3922 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3923 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
3924 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
3926 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;
3927 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
3928 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
3930 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
3931 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
3932 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
3934 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;
3935 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
3936 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
3938 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
3939 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
3940 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
3942 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3943 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3945 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3946 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3948 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3950 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3951 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3954 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3955 (i32 (EXTRACT_SUBREG
3956 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3957 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3959 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3960 (i32 (EXTRACT_SUBREG
3961 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3962 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3965 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3966 (i64 (EXTRACT_SUBREG
3967 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3968 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3972 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3974 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3975 (i32 (EXTRACT_SUBREG
3976 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3977 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3979 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3980 (i32 (EXTRACT_SUBREG
3981 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3982 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3985 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3986 (i32 (EXTRACT_SUBREG
3987 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3988 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3990 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3991 (i32 (EXTRACT_SUBREG
3992 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3993 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3996 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3997 (i64 (EXTRACT_SUBREG
3998 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3999 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4003 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
4004 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
4006 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
4007 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
4008 (i64 (EXTRACT_SUBREG
4009 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4010 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
4012 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4013 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4014 (i64 (EXTRACT_SUBREG
4015 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4016 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4019 //------------------------------------------------------------------------------
4020 // AdvSIMD modified immediate instructions
4021 //------------------------------------------------------------------------------
4024 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4026 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4028 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4029 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4030 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4031 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4033 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4034 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4035 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4036 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4038 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4039 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4040 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4041 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4043 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4044 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4045 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4046 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4049 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
4051 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4052 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
4054 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4055 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
4057 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4061 // EDIT byte mask: scalar
4062 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4063 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4064 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4065 // The movi_edit node has the immediate value already encoded, so we use
4066 // a plain imm0_255 here.
4067 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4068 (MOVID imm0_255:$shift)>;
4070 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4071 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4072 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4073 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4075 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4076 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4077 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4078 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4080 // EDIT byte mask: 2d
4082 // The movi_edit node has the immediate value already encoded, so we use
4083 // a plain imm0_255 in the pattern
4084 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4085 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
4088 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4091 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4092 // Complexity is added to break a tie with a plain MOVI.
4093 let AddedComplexity = 1 in {
4094 def : Pat<(f32 fpimm0),
4095 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4097 def : Pat<(f64 fpimm0),
4098 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4102 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4103 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4104 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4105 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4107 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4108 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4109 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4110 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4112 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4113 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4115 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4116 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4118 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4119 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4120 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4121 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4123 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4124 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4125 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4126 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4128 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4129 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4130 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4131 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4132 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4133 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4134 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4135 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4137 // EDIT per word: 2s & 4s with MSL shifter
4138 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4139 [(set (v2i32 V64:$Rd),
4140 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4141 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4142 [(set (v4i32 V128:$Rd),
4143 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4145 // Per byte: 8b & 16b
4146 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4148 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4149 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4151 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4155 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4156 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4158 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4159 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4160 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4161 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4163 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4164 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4165 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4166 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4168 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4169 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4170 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4171 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4172 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4173 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4174 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4175 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4177 // EDIT per word: 2s & 4s with MSL shifter
4178 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4179 [(set (v2i32 V64:$Rd),
4180 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4181 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4182 [(set (v4i32 V128:$Rd),
4183 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4185 //----------------------------------------------------------------------------
4186 // AdvSIMD indexed element
4187 //----------------------------------------------------------------------------
4189 let hasSideEffects = 0 in {
4190 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
4191 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
4194 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4195 // instruction expects the addend first, while the intrinsic expects it last.
4197 // On the other hand, there are quite a few valid combinatorial options due to
4198 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4199 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4200 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4201 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4202 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4204 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4205 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4206 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4207 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4208 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4209 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4210 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4211 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4213 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4214 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4216 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4217 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4218 VectorIndexS:$idx))),
4219 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4220 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4221 (v2f32 (AArch64duplane32
4222 (v4f32 (insert_subvector undef,
4223 (v2f32 (fneg V64:$Rm)),
4225 VectorIndexS:$idx)))),
4226 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4227 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4228 VectorIndexS:$idx)>;
4229 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4230 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4231 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4232 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4234 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4236 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4237 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4238 VectorIndexS:$idx))),
4239 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4240 VectorIndexS:$idx)>;
4241 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4242 (v4f32 (AArch64duplane32
4243 (v4f32 (insert_subvector undef,
4244 (v2f32 (fneg V64:$Rm)),
4246 VectorIndexS:$idx)))),
4247 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4248 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4249 VectorIndexS:$idx)>;
4250 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4251 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4252 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4253 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4255 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4256 // (DUPLANE from 64-bit would be trivial).
4257 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4258 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4259 VectorIndexD:$idx))),
4261 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4262 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4263 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4264 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4265 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4267 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4268 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4269 (vector_extract (v4f32 (fneg V128:$Rm)),
4270 VectorIndexS:$idx))),
4271 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4272 V128:$Rm, VectorIndexS:$idx)>;
4273 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4274 (vector_extract (v2f32 (fneg V64:$Rm)),
4275 VectorIndexS:$idx))),
4276 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4277 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4279 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4280 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4281 (vector_extract (v2f64 (fneg V128:$Rm)),
4282 VectorIndexS:$idx))),
4283 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4284 V128:$Rm, VectorIndexS:$idx)>;
4287 defm : FMLSIndexedAfterNegPatterns<
4288 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4289 defm : FMLSIndexedAfterNegPatterns<
4290 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4292 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4293 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4295 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4296 (FMULv2i32_indexed V64:$Rn,
4297 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4299 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4300 (FMULv4i32_indexed V128:$Rn,
4301 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4303 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4304 (FMULv2i64_indexed V128:$Rn,
4305 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4308 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4309 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4310 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4311 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4312 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4313 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4314 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4315 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4316 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4317 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4318 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4319 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4320 int_aarch64_neon_smull>;
4321 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4322 int_aarch64_neon_sqadd>;
4323 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4324 int_aarch64_neon_sqsub>;
4325 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4326 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4327 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4328 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4329 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4330 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4331 int_aarch64_neon_umull>;
4333 // A scalar sqdmull with the second operand being a vector lane can be
4334 // handled directly with the indexed instruction encoding.
4335 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4336 (vector_extract (v4i32 V128:$Vm),
4337 VectorIndexS:$idx)),
4338 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4340 //----------------------------------------------------------------------------
4341 // AdvSIMD scalar shift instructions
4342 //----------------------------------------------------------------------------
4343 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4344 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4345 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4346 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4347 // Codegen patterns for the above. We don't put these directly on the
4348 // instructions because TableGen's type inference can't handle the truth.
4349 // Having the same base pattern for fp <--> int totally freaks it out.
4350 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4351 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4352 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4353 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4354 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4355 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4356 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4357 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4358 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4360 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4361 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4363 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4364 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4365 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4366 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4367 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4368 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4369 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4370 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4371 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4372 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4374 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4375 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4377 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4379 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4380 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4381 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4382 int_aarch64_neon_sqrshrn>;
4383 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4384 int_aarch64_neon_sqrshrun>;
4385 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4386 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4387 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4388 int_aarch64_neon_sqshrn>;
4389 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4390 int_aarch64_neon_sqshrun>;
4391 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4392 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4393 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4394 TriOpFrag<(add node:$LHS,
4395 (AArch64srshri node:$MHS, node:$RHS))>>;
4396 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4397 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4398 TriOpFrag<(add node:$LHS,
4399 (AArch64vashr node:$MHS, node:$RHS))>>;
4400 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4401 int_aarch64_neon_uqrshrn>;
4402 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4403 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4404 int_aarch64_neon_uqshrn>;
4405 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4406 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4407 TriOpFrag<(add node:$LHS,
4408 (AArch64urshri node:$MHS, node:$RHS))>>;
4409 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4410 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4411 TriOpFrag<(add node:$LHS,
4412 (AArch64vlshr node:$MHS, node:$RHS))>>;
4414 //----------------------------------------------------------------------------
4415 // AdvSIMD vector shift instructions
4416 //----------------------------------------------------------------------------
4417 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4418 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4419 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4420 int_aarch64_neon_vcvtfxs2fp>;
4421 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4422 int_aarch64_neon_rshrn>;
4423 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4424 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4425 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4426 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4427 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4428 (i32 vecshiftL64:$imm))),
4429 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4430 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4431 int_aarch64_neon_sqrshrn>;
4432 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4433 int_aarch64_neon_sqrshrun>;
4434 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4435 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4436 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4437 int_aarch64_neon_sqshrn>;
4438 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4439 int_aarch64_neon_sqshrun>;
4440 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4441 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4442 (i32 vecshiftR64:$imm))),
4443 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4444 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4445 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4446 TriOpFrag<(add node:$LHS,
4447 (AArch64srshri node:$MHS, node:$RHS))> >;
4448 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4449 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4451 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4452 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4453 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4454 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4455 int_aarch64_neon_vcvtfxu2fp>;
4456 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4457 int_aarch64_neon_uqrshrn>;
4458 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4459 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4460 int_aarch64_neon_uqshrn>;
4461 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4462 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4463 TriOpFrag<(add node:$LHS,
4464 (AArch64urshri node:$MHS, node:$RHS))> >;
4465 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4466 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4467 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4468 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4469 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4471 // SHRN patterns for when a logical right shift was used instead of arithmetic
4472 // (the immediate guarantees no sign bits actually end up in the result so it
4474 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4475 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4476 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4477 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4478 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4479 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4481 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4482 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4483 vecshiftR16Narrow:$imm)))),
4484 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4485 V128:$Rn, vecshiftR16Narrow:$imm)>;
4486 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4487 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4488 vecshiftR32Narrow:$imm)))),
4489 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4490 V128:$Rn, vecshiftR32Narrow:$imm)>;
4491 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4492 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4493 vecshiftR64Narrow:$imm)))),
4494 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4495 V128:$Rn, vecshiftR32Narrow:$imm)>;
4497 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4498 // Anyexts are implemented as zexts.
4499 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4500 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4501 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4502 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4503 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4504 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4505 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4506 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4507 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4508 // Also match an extend from the upper half of a 128 bit source register.
4509 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4510 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4511 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4512 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4513 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4514 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4515 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4516 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4517 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4518 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4519 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4520 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4521 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4522 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4523 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4524 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4525 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4526 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4528 // Vector shift sxtl aliases
4529 def : InstAlias<"sxtl.8h $dst, $src1",
4530 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4531 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4532 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4533 def : InstAlias<"sxtl.4s $dst, $src1",
4534 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4535 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4536 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4537 def : InstAlias<"sxtl.2d $dst, $src1",
4538 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4539 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4540 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4542 // Vector shift sxtl2 aliases
4543 def : InstAlias<"sxtl2.8h $dst, $src1",
4544 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4545 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4546 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4547 def : InstAlias<"sxtl2.4s $dst, $src1",
4548 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4549 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4550 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4551 def : InstAlias<"sxtl2.2d $dst, $src1",
4552 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4553 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4554 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4556 // Vector shift uxtl aliases
4557 def : InstAlias<"uxtl.8h $dst, $src1",
4558 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4559 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4560 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4561 def : InstAlias<"uxtl.4s $dst, $src1",
4562 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4563 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4564 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4565 def : InstAlias<"uxtl.2d $dst, $src1",
4566 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4567 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4568 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4570 // Vector shift uxtl2 aliases
4571 def : InstAlias<"uxtl2.8h $dst, $src1",
4572 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4573 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4574 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4575 def : InstAlias<"uxtl2.4s $dst, $src1",
4576 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4577 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4578 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4579 def : InstAlias<"uxtl2.2d $dst, $src1",
4580 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4581 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4582 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4584 // If an integer is about to be converted to a floating point value,
4585 // just load it on the floating point unit.
4586 // These patterns are more complex because floating point loads do not
4587 // support sign extension.
4588 // The sign extension has to be explicitly added and is only supported for
4589 // one step: byte-to-half, half-to-word, word-to-doubleword.
4590 // SCVTF GPR -> FPR is 9 cycles.
4591 // SCVTF FPR -> FPR is 4 cyclces.
4592 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4593 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4594 // and still being faster.
4595 // However, this is not good for code size.
4596 // 8-bits -> float. 2 sizes step-up.
4597 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4598 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4599 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4604 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4610 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4612 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4613 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4614 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4615 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4616 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4617 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4618 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4619 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4621 // 16-bits -> float. 1 size step-up.
4622 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4623 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4624 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4626 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4630 ssub)))>, Requires<[NotForCodeSize]>;
4632 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4633 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4634 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4635 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4636 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4637 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4638 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4639 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4641 // 32-bits to 32-bits are handled in target specific dag combine:
4642 // performIntToFpCombine.
4643 // 64-bits integer to 32-bits floating point, not possible with
4644 // SCVTF on floating point registers (both source and destination
4645 // must have the same size).
4647 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4648 // 8-bits -> double. 3 size step-up: give up.
4649 // 16-bits -> double. 2 size step.
4650 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4651 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4652 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4657 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4663 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4665 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4666 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4667 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4668 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4669 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4670 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4671 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4672 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4673 // 32-bits -> double. 1 size step-up.
4674 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4675 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4676 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4678 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4682 dsub)))>, Requires<[NotForCodeSize]>;
4684 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4685 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4686 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4687 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4688 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4689 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4690 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4691 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4693 // 64-bits -> double are handled in target specific dag combine:
4694 // performIntToFpCombine.
4697 //----------------------------------------------------------------------------
4698 // AdvSIMD Load-Store Structure
4699 //----------------------------------------------------------------------------
4700 defm LD1 : SIMDLd1Multiple<"ld1">;
4701 defm LD2 : SIMDLd2Multiple<"ld2">;
4702 defm LD3 : SIMDLd3Multiple<"ld3">;
4703 defm LD4 : SIMDLd4Multiple<"ld4">;
4705 defm ST1 : SIMDSt1Multiple<"st1">;
4706 defm ST2 : SIMDSt2Multiple<"st2">;
4707 defm ST3 : SIMDSt3Multiple<"st3">;
4708 defm ST4 : SIMDSt4Multiple<"st4">;
4710 class Ld1Pat<ValueType ty, Instruction INST>
4711 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4713 def : Ld1Pat<v16i8, LD1Onev16b>;
4714 def : Ld1Pat<v8i16, LD1Onev8h>;
4715 def : Ld1Pat<v4i32, LD1Onev4s>;
4716 def : Ld1Pat<v2i64, LD1Onev2d>;
4717 def : Ld1Pat<v8i8, LD1Onev8b>;
4718 def : Ld1Pat<v4i16, LD1Onev4h>;
4719 def : Ld1Pat<v2i32, LD1Onev2s>;
4720 def : Ld1Pat<v1i64, LD1Onev1d>;
4722 class St1Pat<ValueType ty, Instruction INST>
4723 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4724 (INST ty:$Vt, GPR64sp:$Rn)>;
4726 def : St1Pat<v16i8, ST1Onev16b>;
4727 def : St1Pat<v8i16, ST1Onev8h>;
4728 def : St1Pat<v4i32, ST1Onev4s>;
4729 def : St1Pat<v2i64, ST1Onev2d>;
4730 def : St1Pat<v8i8, ST1Onev8b>;
4731 def : St1Pat<v4i16, ST1Onev4h>;
4732 def : St1Pat<v2i32, ST1Onev2s>;
4733 def : St1Pat<v1i64, ST1Onev1d>;
4739 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4740 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4741 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4742 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4743 let mayLoad = 1, hasSideEffects = 0 in {
4744 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4745 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4746 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4747 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4748 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4749 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4750 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4751 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4752 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4753 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4754 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4755 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4756 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4757 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4758 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4759 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4762 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4763 (LD1Rv8b GPR64sp:$Rn)>;
4764 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4765 (LD1Rv16b GPR64sp:$Rn)>;
4766 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4767 (LD1Rv4h GPR64sp:$Rn)>;
4768 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4769 (LD1Rv8h GPR64sp:$Rn)>;
4770 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4771 (LD1Rv2s GPR64sp:$Rn)>;
4772 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4773 (LD1Rv4s GPR64sp:$Rn)>;
4774 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4775 (LD1Rv2d GPR64sp:$Rn)>;
4776 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4777 (LD1Rv1d GPR64sp:$Rn)>;
4778 // Grab the floating point version too
4779 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4780 (LD1Rv2s GPR64sp:$Rn)>;
4781 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4782 (LD1Rv4s GPR64sp:$Rn)>;
4783 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4784 (LD1Rv2d GPR64sp:$Rn)>;
4785 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4786 (LD1Rv1d GPR64sp:$Rn)>;
4787 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4788 (LD1Rv4h GPR64sp:$Rn)>;
4789 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4790 (LD1Rv8h GPR64sp:$Rn)>;
4792 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4793 ValueType VTy, ValueType STy, Instruction LD1>
4794 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4795 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4796 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4798 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4799 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4800 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4801 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4802 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4803 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4804 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4806 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4807 ValueType VTy, ValueType STy, Instruction LD1>
4808 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4809 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4811 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4812 VecIndex:$idx, GPR64sp:$Rn),
4815 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4816 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4817 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4818 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4819 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4822 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4823 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4824 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4825 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4828 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4829 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4830 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4831 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4833 let AddedComplexity = 19 in
4834 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4835 ValueType VTy, ValueType STy, Instruction ST1>
4837 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4839 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4841 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4842 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4843 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4844 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4845 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4846 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4847 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
4849 let AddedComplexity = 19 in
4850 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4851 ValueType VTy, ValueType STy, Instruction ST1>
4853 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4855 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4856 VecIndex:$idx, GPR64sp:$Rn)>;
4858 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4859 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4860 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4861 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4862 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
4864 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4865 ValueType VTy, ValueType STy, Instruction ST1,
4867 def : Pat<(scalar_store
4868 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4869 GPR64sp:$Rn, offset),
4870 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4871 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4873 def : Pat<(scalar_store
4874 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4875 GPR64sp:$Rn, GPR64:$Rm),
4876 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4877 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4880 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4881 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4883 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4884 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4885 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4886 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4887 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
4889 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4890 ValueType VTy, ValueType STy, Instruction ST1,
4892 def : Pat<(scalar_store
4893 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4894 GPR64sp:$Rn, offset),
4895 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4897 def : Pat<(scalar_store
4898 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4899 GPR64sp:$Rn, GPR64:$Rm),
4900 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4903 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4905 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4907 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4908 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4909 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4910 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4911 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
4913 let mayStore = 1, hasSideEffects = 0 in {
4914 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4915 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4916 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4917 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4918 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4919 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4920 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4921 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4922 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4923 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4924 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4925 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4928 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4929 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4930 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4931 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4933 //----------------------------------------------------------------------------
4934 // Crypto extensions
4935 //----------------------------------------------------------------------------
4937 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
4938 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
4939 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
4940 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
4942 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
4943 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
4944 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
4945 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
4946 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
4947 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
4948 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
4950 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
4951 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
4952 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
4954 //----------------------------------------------------------------------------
4956 //----------------------------------------------------------------------------
4957 // FIXME: Like for X86, these should go in their own separate .td file.
4959 // Any instruction that defines a 32-bit result leaves the high half of the
4960 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4961 // be copying from a truncate. But any other 32-bit operation will zero-extend
4963 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4964 def def32 : PatLeaf<(i32 GPR32:$src), [{
4965 return N->getOpcode() != ISD::TRUNCATE &&
4966 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4967 N->getOpcode() != ISD::CopyFromReg;
4970 // In the case of a 32-bit def that is known to implicitly zero-extend,
4971 // we can use a SUBREG_TO_REG.
4972 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4974 // For an anyext, we don't care what the high bits are, so we can perform an
4975 // INSERT_SUBREF into an IMPLICIT_DEF.
4976 def : Pat<(i64 (anyext GPR32:$src)),
4977 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4979 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4980 // instruction (UBFM) on the enclosing super-reg.
4981 def : Pat<(i64 (zext GPR32:$src)),
4982 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4984 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4985 // containing super-reg.
4986 def : Pat<(i64 (sext GPR32:$src)),
4987 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4988 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4989 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4990 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4991 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4992 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4993 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4994 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4996 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4997 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4998 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4999 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
5000 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5001 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
5003 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
5004 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5005 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
5006 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
5007 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5008 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
5010 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
5011 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5012 (i64 (i64shift_a imm0_63:$imm)),
5013 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
5015 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
5016 // AddedComplexity for the following patterns since we want to match sext + sra
5017 // patterns before we attempt to match a single sra node.
5018 let AddedComplexity = 20 in {
5019 // We support all sext + sra combinations which preserve at least one bit of the
5020 // original value which is to be sign extended. E.g. we support shifts up to
5022 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
5023 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
5024 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
5025 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
5027 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
5028 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
5029 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
5030 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
5032 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
5033 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5034 (i64 imm0_31:$imm), 31)>;
5035 } // AddedComplexity = 20
5037 // To truncate, we can simply extract from a subregister.
5038 def : Pat<(i32 (trunc GPR64sp:$src)),
5039 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5041 // __builtin_trap() uses the BRK instruction on AArch64.
5042 def : Pat<(trap), (BRK 1)>;
5044 // Conversions within AdvSIMD types in the same register size are free.
5045 // But because we need a consistent lane ordering, in big endian many
5046 // conversions require one or more REV instructions.
5048 // Consider a simple memory load followed by a bitconvert then a store.
5050 // v1 = BITCAST v2i32 v0 to v4i16
5053 // In big endian mode every memory access has an implicit byte swap. LDR and
5054 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5055 // is, they treat the vector as a sequence of elements to be byte-swapped.
5056 // The two pairs of instructions are fundamentally incompatible. We've decided
5057 // to use LD1/ST1 only to simplify compiler implementation.
5059 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5060 // the original code sequence:
5062 // v1 = REV v2i32 (implicit)
5063 // v2 = BITCAST v2i32 v1 to v4i16
5064 // v3 = REV v4i16 v2 (implicit)
5067 // But this is now broken - the value stored is different to the value loaded
5068 // due to lane reordering. To fix this, on every BITCAST we must perform two
5071 // v1 = REV v2i32 (implicit)
5073 // v3 = BITCAST v2i32 v2 to v4i16
5075 // v5 = REV v4i16 v4 (implicit)
5078 // This means an extra two instructions, but actually in most cases the two REV
5079 // instructions can be combined into one. For example:
5080 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5082 // There is also no 128-bit REV instruction. This must be synthesized with an
5085 // Most bitconverts require some sort of conversion. The only exceptions are:
5086 // a) Identity conversions - vNfX <-> vNiX
5087 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5090 // Natural vector casts (64 bit)
5091 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5092 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5093 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5094 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5095 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5097 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5098 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5099 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5100 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5102 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5103 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5104 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5105 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5107 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5108 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5109 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5110 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5111 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5112 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5114 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5115 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5116 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5117 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5118 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5120 // Natural vector casts (128 bit)
5121 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5122 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5123 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5124 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5125 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5127 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5128 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5129 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5130 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5132 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5133 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5134 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5135 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5137 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5138 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5139 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5140 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5141 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5142 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5144 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5145 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5146 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5147 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5148 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5150 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5151 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5152 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5153 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5154 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5156 let Predicates = [IsLE] in {
5157 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5158 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5159 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5160 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5161 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5163 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5164 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5165 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5166 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5167 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5168 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5169 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5170 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5171 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5172 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5173 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5174 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5176 let Predicates = [IsBE] in {
5177 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5178 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5179 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5180 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5181 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5182 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5183 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5184 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5185 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5186 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5188 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5189 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5190 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5191 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5192 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5193 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5194 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5195 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5196 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5197 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5199 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5200 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5201 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5202 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5203 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5204 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5205 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5206 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5207 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5209 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5210 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5211 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5212 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5213 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5214 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5215 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5216 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5217 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5218 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5220 let Predicates = [IsLE] in {
5221 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5222 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5223 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5224 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5225 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5227 let Predicates = [IsBE] in {
5228 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5229 (v1i64 (REV64v2i32 FPR64:$src))>;
5230 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5231 (v1i64 (REV64v4i16 FPR64:$src))>;
5232 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5233 (v1i64 (REV64v8i8 FPR64:$src))>;
5234 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5235 (v1i64 (REV64v4i16 FPR64:$src))>;
5236 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5237 (v1i64 (REV64v2i32 FPR64:$src))>;
5239 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5240 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5242 let Predicates = [IsLE] in {
5243 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5244 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5245 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5246 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5247 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5248 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5250 let Predicates = [IsBE] in {
5251 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5252 (v2i32 (REV64v2i32 FPR64:$src))>;
5253 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5254 (v2i32 (REV32v4i16 FPR64:$src))>;
5255 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5256 (v2i32 (REV32v8i8 FPR64:$src))>;
5257 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5258 (v2i32 (REV64v2i32 FPR64:$src))>;
5259 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5260 (v2i32 (REV64v2i32 FPR64:$src))>;
5261 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5262 (v2i32 (REV64v4i16 FPR64:$src))>;
5264 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5266 let Predicates = [IsLE] in {
5267 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5268 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5269 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5270 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5271 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5272 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5273 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5275 let Predicates = [IsBE] in {
5276 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5277 (v4i16 (REV64v4i16 FPR64:$src))>;
5278 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5279 (v4i16 (REV32v4i16 FPR64:$src))>;
5280 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5281 (v4i16 (REV16v8i8 FPR64:$src))>;
5282 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5283 (v4i16 (REV64v4i16 FPR64:$src))>;
5284 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5285 (v4i16 (REV32v4i16 FPR64:$src))>;
5286 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5287 (v4i16 (REV32v4i16 FPR64:$src))>;
5288 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5289 (v4i16 (REV64v4i16 FPR64:$src))>;
5292 let Predicates = [IsLE] in {
5293 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5294 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5295 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5296 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5297 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5298 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5299 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5301 let Predicates = [IsBE] in {
5302 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5303 (v4f16 (REV64v4i16 FPR64:$src))>;
5304 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5305 (v4f16 (REV64v4i16 FPR64:$src))>;
5306 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5307 (v4f16 (REV64v4i16 FPR64:$src))>;
5308 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5309 (v4f16 (REV16v8i8 FPR64:$src))>;
5310 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5311 (v4f16 (REV64v4i16 FPR64:$src))>;
5312 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5313 (v4f16 (REV64v4i16 FPR64:$src))>;
5314 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5315 (v4f16 (REV64v4i16 FPR64:$src))>;
5320 let Predicates = [IsLE] in {
5321 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5322 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5323 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5324 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5325 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5326 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5327 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5329 let Predicates = [IsBE] in {
5330 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5331 (v8i8 (REV64v8i8 FPR64:$src))>;
5332 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5333 (v8i8 (REV32v8i8 FPR64:$src))>;
5334 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5335 (v8i8 (REV16v8i8 FPR64:$src))>;
5336 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5337 (v8i8 (REV64v8i8 FPR64:$src))>;
5338 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5339 (v8i8 (REV32v8i8 FPR64:$src))>;
5340 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5341 (v8i8 (REV64v8i8 FPR64:$src))>;
5342 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5343 (v8i8 (REV16v8i8 FPR64:$src))>;
5346 let Predicates = [IsLE] in {
5347 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5348 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5349 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5350 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5351 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5353 let Predicates = [IsBE] in {
5354 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5355 (f64 (REV64v2i32 FPR64:$src))>;
5356 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5357 (f64 (REV64v4i16 FPR64:$src))>;
5358 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5359 (f64 (REV64v2i32 FPR64:$src))>;
5360 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5361 (f64 (REV64v8i8 FPR64:$src))>;
5362 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5363 (f64 (REV64v4i16 FPR64:$src))>;
5365 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5366 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5368 let Predicates = [IsLE] in {
5369 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5370 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5371 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5372 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5373 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5375 let Predicates = [IsBE] in {
5376 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5377 (v1f64 (REV64v2i32 FPR64:$src))>;
5378 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5379 (v1f64 (REV64v4i16 FPR64:$src))>;
5380 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5381 (v1f64 (REV64v8i8 FPR64:$src))>;
5382 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5383 (v1f64 (REV64v2i32 FPR64:$src))>;
5384 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5385 (v1f64 (REV64v4i16 FPR64:$src))>;
5387 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5388 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5390 let Predicates = [IsLE] in {
5391 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5392 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5393 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5394 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5395 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5396 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5398 let Predicates = [IsBE] in {
5399 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5400 (v2f32 (REV64v2i32 FPR64:$src))>;
5401 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5402 (v2f32 (REV32v4i16 FPR64:$src))>;
5403 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5404 (v2f32 (REV32v8i8 FPR64:$src))>;
5405 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5406 (v2f32 (REV64v2i32 FPR64:$src))>;
5407 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5408 (v2f32 (REV64v2i32 FPR64:$src))>;
5409 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5410 (v2f32 (REV64v4i16 FPR64:$src))>;
5412 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5414 let Predicates = [IsLE] in {
5415 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5416 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5417 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5418 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5419 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5420 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5421 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5423 let Predicates = [IsBE] in {
5424 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5425 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5426 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5427 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5428 (REV64v4i32 FPR128:$src), (i32 8)))>;
5429 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5430 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5431 (REV64v8i16 FPR128:$src), (i32 8)))>;
5432 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5433 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5434 (REV64v8i16 FPR128:$src), (i32 8)))>;
5435 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5436 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5437 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5438 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5439 (REV64v4i32 FPR128:$src), (i32 8)))>;
5440 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5441 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5442 (REV64v16i8 FPR128:$src), (i32 8)))>;
5445 let Predicates = [IsLE] in {
5446 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5447 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5448 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5449 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5450 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5451 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5453 let Predicates = [IsBE] in {
5454 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5455 (v2f64 (EXTv16i8 FPR128:$src,
5456 FPR128:$src, (i32 8)))>;
5457 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5458 (v2f64 (REV64v4i32 FPR128:$src))>;
5459 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5460 (v2f64 (REV64v8i16 FPR128:$src))>;
5461 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5462 (v2f64 (REV64v8i16 FPR128:$src))>;
5463 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5464 (v2f64 (REV64v16i8 FPR128:$src))>;
5465 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5466 (v2f64 (REV64v4i32 FPR128:$src))>;
5468 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5470 let Predicates = [IsLE] in {
5471 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5472 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5473 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5474 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5475 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5476 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5478 let Predicates = [IsBE] in {
5479 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5480 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5481 (REV64v4i32 FPR128:$src), (i32 8)))>;
5482 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5483 (v4f32 (REV32v8i16 FPR128:$src))>;
5484 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5485 (v4f32 (REV32v8i16 FPR128:$src))>;
5486 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5487 (v4f32 (REV32v16i8 FPR128:$src))>;
5488 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5489 (v4f32 (REV64v4i32 FPR128:$src))>;
5490 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5491 (v4f32 (REV64v4i32 FPR128:$src))>;
5493 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5495 let Predicates = [IsLE] in {
5496 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5497 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5498 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5499 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5500 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5501 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5503 let Predicates = [IsBE] in {
5504 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5505 (v2i64 (EXTv16i8 FPR128:$src,
5506 FPR128:$src, (i32 8)))>;
5507 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5508 (v2i64 (REV64v4i32 FPR128:$src))>;
5509 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5510 (v2i64 (REV64v8i16 FPR128:$src))>;
5511 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5512 (v2i64 (REV64v16i8 FPR128:$src))>;
5513 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5514 (v2i64 (REV64v4i32 FPR128:$src))>;
5515 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5516 (v2i64 (REV64v8i16 FPR128:$src))>;
5518 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5520 let Predicates = [IsLE] in {
5521 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5522 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5523 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5524 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5525 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5526 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5528 let Predicates = [IsBE] in {
5529 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5530 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5531 (REV64v4i32 FPR128:$src),
5533 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5534 (v4i32 (REV64v4i32 FPR128:$src))>;
5535 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5536 (v4i32 (REV32v8i16 FPR128:$src))>;
5537 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5538 (v4i32 (REV32v16i8 FPR128:$src))>;
5539 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5540 (v4i32 (REV64v4i32 FPR128:$src))>;
5541 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5542 (v4i32 (REV32v8i16 FPR128:$src))>;
5544 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5546 let Predicates = [IsLE] in {
5547 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5548 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5549 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5550 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5551 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5552 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5553 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5555 let Predicates = [IsBE] in {
5556 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5557 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5558 (REV64v8i16 FPR128:$src),
5560 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5561 (v8i16 (REV64v8i16 FPR128:$src))>;
5562 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5563 (v8i16 (REV32v8i16 FPR128:$src))>;
5564 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5565 (v8i16 (REV16v16i8 FPR128:$src))>;
5566 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5567 (v8i16 (REV64v8i16 FPR128:$src))>;
5568 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5569 (v8i16 (REV32v8i16 FPR128:$src))>;
5570 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5571 (v8i16 (REV32v8i16 FPR128:$src))>;
5574 let Predicates = [IsLE] in {
5575 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5576 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5577 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5578 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5579 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5580 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5581 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5583 let Predicates = [IsBE] in {
5584 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5585 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5586 (REV64v8i16 FPR128:$src),
5588 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5589 (v8f16 (REV64v8i16 FPR128:$src))>;
5590 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5591 (v8f16 (REV32v8i16 FPR128:$src))>;
5592 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5593 (v8f16 (REV64v8i16 FPR128:$src))>;
5594 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5595 (v8f16 (REV16v16i8 FPR128:$src))>;
5596 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5597 (v8f16 (REV64v8i16 FPR128:$src))>;
5598 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5599 (v8f16 (REV32v8i16 FPR128:$src))>;
5602 let Predicates = [IsLE] in {
5603 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5604 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5605 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5606 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5607 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5608 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5609 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5611 let Predicates = [IsBE] in {
5612 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5613 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5614 (REV64v16i8 FPR128:$src),
5616 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5617 (v16i8 (REV64v16i8 FPR128:$src))>;
5618 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5619 (v16i8 (REV32v16i8 FPR128:$src))>;
5620 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5621 (v16i8 (REV16v16i8 FPR128:$src))>;
5622 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5623 (v16i8 (REV64v16i8 FPR128:$src))>;
5624 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5625 (v16i8 (REV32v16i8 FPR128:$src))>;
5626 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5627 (v16i8 (REV16v16i8 FPR128:$src))>;
5630 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5631 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5632 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5633 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5634 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5635 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5636 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5637 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5639 // A 64-bit subvector insert to the first 128-bit vector position
5640 // is a subregister copy that needs no instruction.
5641 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5642 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5643 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5644 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5645 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5646 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5647 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5648 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5649 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5650 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5651 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5652 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5653 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5654 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5656 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5658 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5659 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5660 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5661 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5662 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5663 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5664 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5665 // so we match on v4f32 here, not v2f32. This will also catch adding
5666 // the low two lanes of a true v4f32 vector.
5667 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5668 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5669 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5671 // Scalar 64-bit shifts in FPR64 registers.
5672 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5673 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5674 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5675 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5676 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5677 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5678 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5679 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5681 // Tail call return handling. These are all compiler pseudo-instructions,
5682 // so no encoding information or anything like that.
5683 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5684 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5685 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5688 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5689 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5690 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5691 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5692 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5693 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5695 include "AArch64InstrAtomics.td"