1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
18 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
19 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
20 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
21 def HasNEON : Predicate<"Subtarget->hasNEON()">,
22 AssemblerPredicate<"FeatureNEON", "neon">;
23 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
24 AssemblerPredicate<"FeatureCrypto", "crypto">;
25 def HasCRC : Predicate<"Subtarget->hasCRC()">,
26 AssemblerPredicate<"FeatureCRC", "crc">;
27 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
28 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
29 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
31 //===----------------------------------------------------------------------===//
32 // AArch64-specific DAG Nodes.
35 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
36 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
39 SDTCisInt<0>, SDTCisVT<1, i32>]>;
41 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
42 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
48 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
49 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
56 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
59 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
60 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
61 SDTCisVT<2, OtherVT>]>;
64 def SDT_AArch64CSel : SDTypeProfile<1, 4,
69 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
72 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
73 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
74 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
77 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
78 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
79 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
80 SDTCisInt<2>, SDTCisInt<3>]>;
81 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
82 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
83 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
84 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
86 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
87 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
88 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
89 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
91 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
94 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
95 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
97 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
99 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
102 // Generates the general dynamic sequences, i.e.
103 // adrp x0, :tlsdesc:var
104 // ldr x1, [x0, #:tlsdesc_lo12:var]
105 // add x0, x0, #:tlsdesc_lo12:var
109 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
110 // number of operands (the variable)
111 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
114 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
115 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
116 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
117 SDTCisSameAs<1, 4>]>;
121 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
122 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
123 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
124 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
125 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
128 SDCallSeqEnd<[ SDTCisVT<0, i32>,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
131 def AArch64call : SDNode<"AArch64ISD::CALL",
132 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
135 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
137 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
139 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
141 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
143 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
147 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
148 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
149 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
150 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
151 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
153 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
154 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
155 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
157 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
158 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
160 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
161 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
163 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
165 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
167 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
168 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
170 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
171 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
172 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
173 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
174 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
176 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
177 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
178 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
179 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
180 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
181 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
183 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
184 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
185 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
186 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
187 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
188 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
189 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
191 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
192 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
193 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
194 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
196 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
197 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
198 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
199 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
200 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
201 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
202 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
203 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
205 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
206 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
207 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
209 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
210 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
211 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
212 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
213 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
215 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
216 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
217 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
219 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
220 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
221 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
222 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
223 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
224 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
225 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
227 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
228 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
229 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
230 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
231 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
233 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
234 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
236 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
238 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
239 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
241 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
242 [SDNPHasChain, SDNPSideEffect]>;
244 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
245 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
247 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
248 SDT_AArch64TLSDescCallSeq,
249 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
253 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
254 SDT_AArch64WrapperLarge>;
256 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
258 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
259 SDTCisSameAs<1, 2>]>;
260 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
261 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
263 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
264 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
265 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
266 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
267 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
268 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
270 //===----------------------------------------------------------------------===//
272 //===----------------------------------------------------------------------===//
274 // AArch64 Instruction Predicate Definitions.
276 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
277 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
278 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
279 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
280 def ForCodeSize : Predicate<"ForCodeSize">;
281 def NotForCodeSize : Predicate<"!ForCodeSize">;
283 include "AArch64InstrFormats.td"
285 //===----------------------------------------------------------------------===//
287 //===----------------------------------------------------------------------===//
288 // Miscellaneous instructions.
289 //===----------------------------------------------------------------------===//
291 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
292 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
293 [(AArch64callseq_start timm:$amt)]>;
294 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
295 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
296 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
298 let isReMaterializable = 1, isCodeGenOnly = 1 in {
299 // FIXME: The following pseudo instructions are only needed because remat
300 // cannot handle multiple instructions. When that changes, they can be
301 // removed, along with the AArch64Wrapper node.
303 let AddedComplexity = 10 in
304 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
305 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
308 // The MOVaddr instruction should match only when the add is not folded
309 // into a load or store address.
311 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
312 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
313 tglobaladdr:$low))]>,
314 Sched<[WriteAdrAdr]>;
316 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
317 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
319 Sched<[WriteAdrAdr]>;
321 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
322 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
324 Sched<[WriteAdrAdr]>;
326 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
327 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
328 tblockaddress:$low))]>,
329 Sched<[WriteAdrAdr]>;
331 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
332 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
333 tglobaltlsaddr:$low))]>,
334 Sched<[WriteAdrAdr]>;
336 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
337 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
338 texternalsym:$low))]>,
339 Sched<[WriteAdrAdr]>;
341 } // isReMaterializable, isCodeGenOnly
343 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
344 (LOADgot tglobaltlsaddr:$addr)>;
346 def : Pat<(AArch64LOADgot texternalsym:$addr),
347 (LOADgot texternalsym:$addr)>;
349 def : Pat<(AArch64LOADgot tconstpool:$addr),
350 (LOADgot tconstpool:$addr)>;
352 //===----------------------------------------------------------------------===//
353 // System instructions.
354 //===----------------------------------------------------------------------===//
356 def HINT : HintI<"hint">;
357 def : InstAlias<"nop", (HINT 0b000)>;
358 def : InstAlias<"yield",(HINT 0b001)>;
359 def : InstAlias<"wfe", (HINT 0b010)>;
360 def : InstAlias<"wfi", (HINT 0b011)>;
361 def : InstAlias<"sev", (HINT 0b100)>;
362 def : InstAlias<"sevl", (HINT 0b101)>;
364 // As far as LLVM is concerned this writes to the system's exclusive monitors.
365 let mayLoad = 1, mayStore = 1 in
366 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
368 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
369 // model patterns with sufficiently fine granularity.
370 let mayLoad = ?, mayStore = ? in {
371 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
372 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
374 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
375 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
377 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
378 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
381 def : InstAlias<"clrex", (CLREX 0xf)>;
382 def : InstAlias<"isb", (ISB 0xf)>;
386 def MSRpstate: MSRpstateI;
388 // The thread pointer (on Linux, at least, where this has been implemented) is
390 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
392 // Generic system instructions
393 def SYSxt : SystemXtI<0, "sys">;
394 def SYSLxt : SystemLXtI<1, "sysl">;
396 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
397 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
398 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
400 //===----------------------------------------------------------------------===//
401 // Move immediate instructions.
402 //===----------------------------------------------------------------------===//
404 defm MOVK : InsertImmediate<0b11, "movk">;
405 defm MOVN : MoveImmediate<0b00, "movn">;
407 let PostEncoderMethod = "fixMOVZ" in
408 defm MOVZ : MoveImmediate<0b10, "movz">;
410 // First group of aliases covers an implicit "lsl #0".
411 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
412 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
413 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
414 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
415 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
416 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
418 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
419 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
420 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
421 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
422 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
424 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
425 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
426 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
427 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
429 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
430 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
431 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
432 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
434 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
435 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
437 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
438 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
440 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
441 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
443 // Final group of aliases covers true "mov $Rd, $imm" cases.
444 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
445 int width, int shift> {
446 def _asmoperand : AsmOperandClass {
447 let Name = basename # width # "_lsl" # shift # "MovAlias";
448 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
450 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
453 def _movimm : Operand<i32> {
454 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
457 def : InstAlias<"mov $Rd, $imm",
458 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
461 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
462 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
464 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
465 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
466 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
467 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
469 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
470 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
472 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
473 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
474 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
475 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
477 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
478 isAsCheapAsAMove = 1 in {
479 // FIXME: The following pseudo instructions are only needed because remat
480 // cannot handle multiple instructions. When that changes, we can select
481 // directly to the real instructions and get rid of these pseudos.
484 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
485 [(set GPR32:$dst, imm:$src)]>,
488 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
489 [(set GPR64:$dst, imm:$src)]>,
491 } // isReMaterializable, isCodeGenOnly
493 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
494 // eventual expansion code fewer bits to worry about getting right. Marshalling
495 // the types is a little tricky though:
496 def i64imm_32bit : ImmLeaf<i64, [{
497 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
500 def trunc_imm : SDNodeXForm<imm, [{
501 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
504 def : Pat<(i64 i64imm_32bit:$src),
505 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
507 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
508 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
509 return CurDAG->getTargetConstant(
510 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
513 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
514 return CurDAG->getTargetConstant(
515 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
519 def : Pat<(f32 fpimm:$in),
520 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
521 def : Pat<(f64 fpimm:$in),
522 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
525 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
527 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
528 tglobaladdr:$g1, tglobaladdr:$g0),
529 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
530 tglobaladdr:$g2, 32),
531 tglobaladdr:$g1, 16),
532 tglobaladdr:$g0, 0)>;
534 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
535 tblockaddress:$g1, tblockaddress:$g0),
536 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
537 tblockaddress:$g2, 32),
538 tblockaddress:$g1, 16),
539 tblockaddress:$g0, 0)>;
541 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
542 tconstpool:$g1, tconstpool:$g0),
543 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
548 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
549 tjumptable:$g1, tjumptable:$g0),
550 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
556 //===----------------------------------------------------------------------===//
557 // Arithmetic instructions.
558 //===----------------------------------------------------------------------===//
560 // Add/subtract with carry.
561 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
562 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
564 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
565 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
566 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
567 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
570 defm ADD : AddSub<0, "add", add>;
571 defm SUB : AddSub<1, "sub">;
573 def : InstAlias<"mov $dst, $src",
574 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
575 def : InstAlias<"mov $dst, $src",
576 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
577 def : InstAlias<"mov $dst, $src",
578 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
579 def : InstAlias<"mov $dst, $src",
580 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
582 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
583 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
585 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
586 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
587 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
588 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
589 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
590 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
591 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
592 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
593 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
594 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
595 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
596 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
597 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
598 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
599 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
600 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
601 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
603 // Because of the immediate format for add/sub-imm instructions, the
604 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
605 // These patterns capture that transformation.
606 let AddedComplexity = 1 in {
607 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
608 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
609 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
610 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
611 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
612 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
613 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
614 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
617 // Because of the immediate format for add/sub-imm instructions, the
618 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
619 // These patterns capture that transformation.
620 let AddedComplexity = 1 in {
621 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
622 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
623 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
624 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
625 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
626 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
627 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
628 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
631 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
632 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
633 def : InstAlias<"neg $dst, $src$shift",
634 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
635 def : InstAlias<"neg $dst, $src$shift",
636 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
638 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
639 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
640 def : InstAlias<"negs $dst, $src$shift",
641 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
642 def : InstAlias<"negs $dst, $src$shift",
643 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
646 // Unsigned/Signed divide
647 defm UDIV : Div<0, "udiv", udiv>;
648 defm SDIV : Div<1, "sdiv", sdiv>;
649 let isCodeGenOnly = 1 in {
650 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
651 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
655 defm ASRV : Shift<0b10, "asr", sra>;
656 defm LSLV : Shift<0b00, "lsl", shl>;
657 defm LSRV : Shift<0b01, "lsr", srl>;
658 defm RORV : Shift<0b11, "ror", rotr>;
660 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
661 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
662 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
663 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
664 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
665 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
666 def : ShiftAlias<"rorv", RORVWr, GPR32>;
667 def : ShiftAlias<"rorv", RORVXr, GPR64>;
670 let AddedComplexity = 7 in {
671 defm MADD : MulAccum<0, "madd", add>;
672 defm MSUB : MulAccum<1, "msub", sub>;
674 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
675 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
676 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
677 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
679 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
680 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
681 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
682 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
683 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
684 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
685 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
686 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
687 } // AddedComplexity = 7
689 let AddedComplexity = 5 in {
690 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
691 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
692 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
693 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
695 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
696 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
697 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
698 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
700 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
701 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
702 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
703 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
704 } // AddedComplexity = 5
706 def : MulAccumWAlias<"mul", MADDWrrr>;
707 def : MulAccumXAlias<"mul", MADDXrrr>;
708 def : MulAccumWAlias<"mneg", MSUBWrrr>;
709 def : MulAccumXAlias<"mneg", MSUBXrrr>;
710 def : WideMulAccumAlias<"smull", SMADDLrrr>;
711 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
712 def : WideMulAccumAlias<"umull", UMADDLrrr>;
713 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
716 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
717 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
720 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
721 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
722 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
723 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
725 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
726 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
727 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
728 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
731 //===----------------------------------------------------------------------===//
732 // Logical instructions.
733 //===----------------------------------------------------------------------===//
736 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
737 defm AND : LogicalImm<0b00, "and", and, "bic">;
738 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
739 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
741 // FIXME: these aliases *are* canonical sometimes (when movz can't be
742 // used). Actually, it seems to be working right now, but putting logical_immXX
743 // here is a bit dodgy on the AsmParser side too.
744 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
745 logical_imm32:$imm), 0>;
746 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
747 logical_imm64:$imm), 0>;
751 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
752 defm BICS : LogicalRegS<0b11, 1, "bics",
753 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
754 defm AND : LogicalReg<0b00, 0, "and", and>;
755 defm BIC : LogicalReg<0b00, 1, "bic",
756 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
757 defm EON : LogicalReg<0b10, 1, "eon",
758 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
759 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
760 defm ORN : LogicalReg<0b01, 1, "orn",
761 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
762 defm ORR : LogicalReg<0b01, 0, "orr", or>;
764 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
765 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
767 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
768 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
770 def : InstAlias<"mvn $Wd, $Wm$sh",
771 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
772 def : InstAlias<"mvn $Xd, $Xm$sh",
773 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
775 def : InstAlias<"tst $src1, $src2",
776 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
777 def : InstAlias<"tst $src1, $src2",
778 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
780 def : InstAlias<"tst $src1, $src2",
781 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
782 def : InstAlias<"tst $src1, $src2",
783 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
785 def : InstAlias<"tst $src1, $src2$sh",
786 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
787 def : InstAlias<"tst $src1, $src2$sh",
788 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
791 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
792 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
795 //===----------------------------------------------------------------------===//
796 // One operand data processing instructions.
797 //===----------------------------------------------------------------------===//
799 defm CLS : OneOperandData<0b101, "cls">;
800 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
801 defm RBIT : OneOperandData<0b000, "rbit">;
803 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
804 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
806 def REV16Wr : OneWRegData<0b001, "rev16",
807 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
808 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
810 def : Pat<(cttz GPR32:$Rn),
811 (CLZWr (RBITWr GPR32:$Rn))>;
812 def : Pat<(cttz GPR64:$Rn),
813 (CLZXr (RBITXr GPR64:$Rn))>;
814 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
817 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
821 // Unlike the other one operand instructions, the instructions with the "rev"
822 // mnemonic do *not* just different in the size bit, but actually use different
823 // opcode bits for the different sizes.
824 def REVWr : OneWRegData<0b010, "rev", bswap>;
825 def REVXr : OneXRegData<0b011, "rev", bswap>;
826 def REV32Xr : OneXRegData<0b010, "rev32",
827 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
829 // The bswap commutes with the rotr so we want a pattern for both possible
831 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
832 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
834 //===----------------------------------------------------------------------===//
835 // Bitfield immediate extraction instruction.
836 //===----------------------------------------------------------------------===//
837 let hasSideEffects = 0 in
838 defm EXTR : ExtractImm<"extr">;
839 def : InstAlias<"ror $dst, $src, $shift",
840 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
841 def : InstAlias<"ror $dst, $src, $shift",
842 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
844 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
845 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
846 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
847 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
849 //===----------------------------------------------------------------------===//
850 // Other bitfield immediate instructions.
851 //===----------------------------------------------------------------------===//
852 let hasSideEffects = 0 in {
853 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
854 defm SBFM : BitfieldImm<0b00, "sbfm">;
855 defm UBFM : BitfieldImm<0b10, "ubfm">;
858 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
859 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
860 return CurDAG->getTargetConstant(enc, MVT::i64);
863 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
864 uint64_t enc = 31 - N->getZExtValue();
865 return CurDAG->getTargetConstant(enc, MVT::i64);
868 // min(7, 31 - shift_amt)
869 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
870 uint64_t enc = 31 - N->getZExtValue();
871 enc = enc > 7 ? 7 : enc;
872 return CurDAG->getTargetConstant(enc, MVT::i64);
875 // min(15, 31 - shift_amt)
876 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
877 uint64_t enc = 31 - N->getZExtValue();
878 enc = enc > 15 ? 15 : enc;
879 return CurDAG->getTargetConstant(enc, MVT::i64);
882 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
883 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
884 return CurDAG->getTargetConstant(enc, MVT::i64);
887 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
888 uint64_t enc = 63 - N->getZExtValue();
889 return CurDAG->getTargetConstant(enc, MVT::i64);
892 // min(7, 63 - shift_amt)
893 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
894 uint64_t enc = 63 - N->getZExtValue();
895 enc = enc > 7 ? 7 : enc;
896 return CurDAG->getTargetConstant(enc, MVT::i64);
899 // min(15, 63 - shift_amt)
900 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
901 uint64_t enc = 63 - N->getZExtValue();
902 enc = enc > 15 ? 15 : enc;
903 return CurDAG->getTargetConstant(enc, MVT::i64);
906 // min(31, 63 - shift_amt)
907 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
908 uint64_t enc = 63 - N->getZExtValue();
909 enc = enc > 31 ? 31 : enc;
910 return CurDAG->getTargetConstant(enc, MVT::i64);
913 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
914 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
915 (i64 (i32shift_b imm0_31:$imm)))>;
916 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
917 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
918 (i64 (i64shift_b imm0_63:$imm)))>;
920 let AddedComplexity = 10 in {
921 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
922 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
923 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
924 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
927 def : InstAlias<"asr $dst, $src, $shift",
928 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
929 def : InstAlias<"asr $dst, $src, $shift",
930 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
931 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
932 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
933 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
934 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
935 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
937 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
938 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
939 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
940 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
942 def : InstAlias<"lsr $dst, $src, $shift",
943 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
944 def : InstAlias<"lsr $dst, $src, $shift",
945 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
946 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
947 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
948 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
949 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
950 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
952 //===----------------------------------------------------------------------===//
953 // Conditionally set flags instructions.
954 //===----------------------------------------------------------------------===//
955 defm CCMN : CondSetFlagsImm<0, "ccmn">;
956 defm CCMP : CondSetFlagsImm<1, "ccmp">;
958 defm CCMN : CondSetFlagsReg<0, "ccmn">;
959 defm CCMP : CondSetFlagsReg<1, "ccmp">;
961 //===----------------------------------------------------------------------===//
962 // Conditional select instructions.
963 //===----------------------------------------------------------------------===//
964 defm CSEL : CondSelect<0, 0b00, "csel">;
966 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
967 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
968 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
969 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
971 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
972 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
973 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
974 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
975 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
976 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
977 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
978 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
979 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
980 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
981 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
982 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
984 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
985 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
986 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
987 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
988 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
989 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
990 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
991 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
993 // The inverse of the condition code from the alias instruction is what is used
994 // in the aliased instruction. The parser all ready inverts the condition code
995 // for these aliases.
996 def : InstAlias<"cset $dst, $cc",
997 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
998 def : InstAlias<"cset $dst, $cc",
999 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1001 def : InstAlias<"csetm $dst, $cc",
1002 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1003 def : InstAlias<"csetm $dst, $cc",
1004 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1006 def : InstAlias<"cinc $dst, $src, $cc",
1007 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1008 def : InstAlias<"cinc $dst, $src, $cc",
1009 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1011 def : InstAlias<"cinv $dst, $src, $cc",
1012 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1013 def : InstAlias<"cinv $dst, $src, $cc",
1014 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1016 def : InstAlias<"cneg $dst, $src, $cc",
1017 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1018 def : InstAlias<"cneg $dst, $src, $cc",
1019 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1021 //===----------------------------------------------------------------------===//
1022 // PC-relative instructions.
1023 //===----------------------------------------------------------------------===//
1024 let isReMaterializable = 1 in {
1025 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1026 def ADR : ADRI<0, "adr", adrlabel, []>;
1027 } // hasSideEffects = 0
1029 def ADRP : ADRI<1, "adrp", adrplabel,
1030 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1031 } // isReMaterializable = 1
1033 // page address of a constant pool entry, block address
1034 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1035 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1037 //===----------------------------------------------------------------------===//
1038 // Unconditional branch (register) instructions.
1039 //===----------------------------------------------------------------------===//
1041 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1042 def RET : BranchReg<0b0010, "ret", []>;
1043 def DRPS : SpecialReturn<0b0101, "drps">;
1044 def ERET : SpecialReturn<0b0100, "eret">;
1045 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1047 // Default to the LR register.
1048 def : InstAlias<"ret", (RET LR)>;
1050 let isCall = 1, Defs = [LR], Uses = [SP] in {
1051 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1054 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1055 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1056 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1058 // Create a separate pseudo-instruction for codegen to use so that we don't
1059 // flag lr as used in every function. It'll be restored before the RET by the
1060 // epilogue if it's legitimately used.
1061 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1062 let isTerminator = 1;
1067 // This is a directive-like pseudo-instruction. The purpose is to insert an
1068 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1069 // (which in the usual case is a BLR).
1070 let hasSideEffects = 1 in
1071 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1072 let AsmString = ".tlsdesccall $sym";
1075 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
1076 // FIXME: can "hasSideEffects be dropped?
1077 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
1078 isCodeGenOnly = 1 in
1080 : Pseudo<(outs), (ins i64imm:$sym),
1081 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>;
1082 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
1083 (TLSDESC_CALLSEQ texternalsym:$sym)>;
1085 //===----------------------------------------------------------------------===//
1086 // Conditional branch (immediate) instruction.
1087 //===----------------------------------------------------------------------===//
1088 def Bcc : BranchCond;
1090 //===----------------------------------------------------------------------===//
1091 // Compare-and-branch instructions.
1092 //===----------------------------------------------------------------------===//
1093 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1094 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1096 //===----------------------------------------------------------------------===//
1097 // Test-bit-and-branch instructions.
1098 //===----------------------------------------------------------------------===//
1099 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1100 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1102 //===----------------------------------------------------------------------===//
1103 // Unconditional branch (immediate) instructions.
1104 //===----------------------------------------------------------------------===//
1105 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1106 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1107 } // isBranch, isTerminator, isBarrier
1109 let isCall = 1, Defs = [LR], Uses = [SP] in {
1110 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1112 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1114 //===----------------------------------------------------------------------===//
1115 // Exception generation instructions.
1116 //===----------------------------------------------------------------------===//
1117 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1118 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1119 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1120 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1121 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1122 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1123 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1124 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1126 // DCPSn defaults to an immediate operand of zero if unspecified.
1127 def : InstAlias<"dcps1", (DCPS1 0)>;
1128 def : InstAlias<"dcps2", (DCPS2 0)>;
1129 def : InstAlias<"dcps3", (DCPS3 0)>;
1131 //===----------------------------------------------------------------------===//
1132 // Load instructions.
1133 //===----------------------------------------------------------------------===//
1135 // Pair (indexed, offset)
1136 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1137 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1138 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1139 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1140 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1142 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1144 // Pair (pre-indexed)
1145 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1146 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1147 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1148 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1149 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1151 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1153 // Pair (post-indexed)
1154 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1155 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1156 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1157 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1158 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1160 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1163 // Pair (no allocate)
1164 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1165 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1166 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1167 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1168 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1171 // (register offset)
1175 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1176 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1177 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1178 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1181 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1182 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1183 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1184 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1185 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1187 // Load sign-extended half-word
1188 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1189 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1191 // Load sign-extended byte
1192 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1193 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1195 // Load sign-extended word
1196 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1199 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1201 // For regular load, we do not have any alignment requirement.
1202 // Thus, it is safe to directly map the vector loads with interesting
1203 // addressing modes.
1204 // FIXME: We could do the same for bitconvert to floating point vectors.
1205 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1206 ValueType ScalTy, ValueType VecTy,
1207 Instruction LOADW, Instruction LOADX,
1209 def : Pat<(VecTy (scalar_to_vector (ScalTy
1210 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1211 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1212 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1215 def : Pat<(VecTy (scalar_to_vector (ScalTy
1216 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1217 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1218 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1222 let AddedComplexity = 10 in {
1223 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1224 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1226 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1227 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1229 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1230 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1232 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1233 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1235 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1236 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1238 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1240 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1243 def : Pat <(v1i64 (scalar_to_vector (i64
1244 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1245 ro_Wextend64:$extend))))),
1246 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1248 def : Pat <(v1i64 (scalar_to_vector (i64
1249 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1250 ro_Xextend64:$extend))))),
1251 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1254 // Match all load 64 bits width whose type is compatible with FPR64
1255 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1256 Instruction LOADW, Instruction LOADX> {
1258 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1259 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1261 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1262 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1265 let AddedComplexity = 10 in {
1266 let Predicates = [IsLE] in {
1267 // We must do vector loads with LD1 in big-endian.
1268 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1269 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1270 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1271 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1272 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1275 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1276 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1278 // Match all load 128 bits width whose type is compatible with FPR128
1279 let Predicates = [IsLE] in {
1280 // We must do vector loads with LD1 in big-endian.
1281 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1282 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1283 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1284 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1285 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1286 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1287 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1289 } // AddedComplexity = 10
1292 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1293 Instruction INSTW, Instruction INSTX> {
1294 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1295 (SUBREG_TO_REG (i64 0),
1296 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1299 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1300 (SUBREG_TO_REG (i64 0),
1301 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1305 let AddedComplexity = 10 in {
1306 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1307 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1308 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1310 // zextloadi1 -> zextloadi8
1311 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1313 // extload -> zextload
1314 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1315 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1316 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1318 // extloadi1 -> zextloadi8
1319 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1324 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1325 Instruction INSTW, Instruction INSTX> {
1326 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1327 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1329 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1330 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1334 let AddedComplexity = 10 in {
1335 // extload -> zextload
1336 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1337 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1338 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1340 // zextloadi1 -> zextloadi8
1341 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1345 // (unsigned immediate)
1347 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1349 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1350 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1352 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1353 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1355 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1356 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1357 [(set (f16 FPR16:$Rt),
1358 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1359 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1360 [(set (f32 FPR32:$Rt),
1361 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1362 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1363 [(set (f64 FPR64:$Rt),
1364 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1365 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1366 [(set (f128 FPR128:$Rt),
1367 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1369 // For regular load, we do not have any alignment requirement.
1370 // Thus, it is safe to directly map the vector loads with interesting
1371 // addressing modes.
1372 // FIXME: We could do the same for bitconvert to floating point vectors.
1373 def : Pat <(v8i8 (scalar_to_vector (i32
1374 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1375 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1376 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1377 def : Pat <(v16i8 (scalar_to_vector (i32
1378 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1379 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1380 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1381 def : Pat <(v4i16 (scalar_to_vector (i32
1382 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1383 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1384 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1385 def : Pat <(v8i16 (scalar_to_vector (i32
1386 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1387 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1388 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1389 def : Pat <(v2i32 (scalar_to_vector (i32
1390 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1391 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1392 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1393 def : Pat <(v4i32 (scalar_to_vector (i32
1394 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1395 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1396 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1397 def : Pat <(v1i64 (scalar_to_vector (i64
1398 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1399 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1400 def : Pat <(v2i64 (scalar_to_vector (i64
1401 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1402 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1403 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1405 // Match all load 64 bits width whose type is compatible with FPR64
1406 let Predicates = [IsLE] in {
1407 // We must use LD1 to perform vector loads in big-endian.
1408 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1409 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1410 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1411 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1412 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1413 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1414 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1415 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1416 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1417 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1419 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1420 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1421 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1422 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1424 // Match all load 128 bits width whose type is compatible with FPR128
1425 let Predicates = [IsLE] in {
1426 // We must use LD1 to perform vector loads in big-endian.
1427 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1428 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1429 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1430 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1431 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1432 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1433 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1434 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1435 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1436 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1437 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1438 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1439 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1440 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1442 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1443 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1445 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1447 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1448 uimm12s2:$offset)))]>;
1449 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1451 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1452 uimm12s1:$offset)))]>;
1454 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1455 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1456 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1457 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1459 // zextloadi1 -> zextloadi8
1460 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1461 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1462 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1463 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1465 // extload -> zextload
1466 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1467 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1468 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1469 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1470 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1471 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1472 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1473 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1474 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1475 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1476 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1477 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1478 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1479 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1481 // load sign-extended half-word
1482 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1484 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1485 uimm12s2:$offset)))]>;
1486 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1488 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1489 uimm12s2:$offset)))]>;
1491 // load sign-extended byte
1492 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1494 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1495 uimm12s1:$offset)))]>;
1496 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1498 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1499 uimm12s1:$offset)))]>;
1501 // load sign-extended word
1502 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1504 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1505 uimm12s4:$offset)))]>;
1507 // load zero-extended word
1508 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1509 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1512 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1513 [(AArch64Prefetch imm:$Rt,
1514 (am_indexed64 GPR64sp:$Rn,
1515 uimm12s8:$offset))]>;
1517 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1521 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1522 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1523 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1524 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1525 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1527 // load sign-extended word
1528 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1531 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1532 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1535 // (unscaled immediate)
1536 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1538 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1539 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1541 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1542 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1544 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1545 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1547 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1548 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1549 [(set (f32 FPR32:$Rt),
1550 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1551 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1552 [(set (f64 FPR64:$Rt),
1553 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1554 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1555 [(set (f128 FPR128:$Rt),
1556 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1559 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1561 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1563 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1565 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1567 // Match all load 64 bits width whose type is compatible with FPR64
1568 let Predicates = [IsLE] in {
1569 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1570 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1571 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1572 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1573 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1574 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1575 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1576 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1577 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1578 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1580 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1581 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1582 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1583 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1585 // Match all load 128 bits width whose type is compatible with FPR128
1586 let Predicates = [IsLE] in {
1587 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1588 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1589 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1590 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1591 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1592 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1593 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1594 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1595 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1596 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1597 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1598 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1599 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1600 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1604 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1605 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1606 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1607 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1608 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1609 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1610 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1611 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1612 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1613 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1614 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1615 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1616 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1617 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1619 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1620 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1621 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1622 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1623 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1624 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1625 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1626 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1627 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1628 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1629 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1630 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1631 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1632 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1636 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1638 // Define new assembler match classes as we want to only match these when
1639 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1640 // associate a DiagnosticType either, as we want the diagnostic for the
1641 // canonical form (the scaled operand) to take precedence.
1642 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1643 let Name = "SImm9OffsetFB" # Width;
1644 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1645 let RenderMethod = "addImmOperands";
1648 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1649 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1650 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1651 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1652 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1654 def simm9_offset_fb8 : Operand<i64> {
1655 let ParserMatchClass = SImm9OffsetFB8Operand;
1657 def simm9_offset_fb16 : Operand<i64> {
1658 let ParserMatchClass = SImm9OffsetFB16Operand;
1660 def simm9_offset_fb32 : Operand<i64> {
1661 let ParserMatchClass = SImm9OffsetFB32Operand;
1663 def simm9_offset_fb64 : Operand<i64> {
1664 let ParserMatchClass = SImm9OffsetFB64Operand;
1666 def simm9_offset_fb128 : Operand<i64> {
1667 let ParserMatchClass = SImm9OffsetFB128Operand;
1670 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1671 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1672 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1673 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1674 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1675 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1676 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1677 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1678 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1679 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1680 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1681 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1682 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1683 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1686 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1687 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1688 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1689 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1691 // load sign-extended half-word
1693 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1695 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1697 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1699 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1701 // load sign-extended byte
1703 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1705 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1707 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1709 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1711 // load sign-extended word
1713 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1715 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1717 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1718 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1719 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1720 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1721 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1722 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1723 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1724 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1725 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1726 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1727 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1728 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1729 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1730 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1731 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1734 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1735 [(AArch64Prefetch imm:$Rt,
1736 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1739 // (unscaled immediate, unprivileged)
1740 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1741 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1743 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1744 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1746 // load sign-extended half-word
1747 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1748 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1750 // load sign-extended byte
1751 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1752 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1754 // load sign-extended word
1755 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1758 // (immediate pre-indexed)
1759 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1760 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1761 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1762 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1763 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1764 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1765 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1767 // load sign-extended half-word
1768 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1769 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1771 // load sign-extended byte
1772 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1773 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1775 // load zero-extended byte
1776 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1777 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1779 // load sign-extended word
1780 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1783 // (immediate post-indexed)
1784 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1785 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1786 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1787 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1788 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1789 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1790 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1792 // load sign-extended half-word
1793 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1794 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1796 // load sign-extended byte
1797 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1798 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1800 // load zero-extended byte
1801 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1802 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1804 // load sign-extended word
1805 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1807 //===----------------------------------------------------------------------===//
1808 // Store instructions.
1809 //===----------------------------------------------------------------------===//
1811 // Pair (indexed, offset)
1812 // FIXME: Use dedicated range-checked addressing mode operand here.
1813 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1814 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1815 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1816 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1817 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1819 // Pair (pre-indexed)
1820 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1821 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1822 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1823 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1824 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1826 // Pair (pre-indexed)
1827 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1828 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1829 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1830 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1831 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1833 // Pair (no allocate)
1834 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1835 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1836 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1837 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1838 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1841 // (Register offset)
1844 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1845 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1846 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1847 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1851 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1852 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1853 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1854 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1855 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1857 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1858 Instruction STRW, Instruction STRX> {
1860 def : Pat<(storeop GPR64:$Rt,
1861 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1862 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1863 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1865 def : Pat<(storeop GPR64:$Rt,
1866 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1867 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1868 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1871 let AddedComplexity = 10 in {
1873 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1874 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1875 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1878 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1879 Instruction STRW, Instruction STRX> {
1880 def : Pat<(store (VecTy FPR:$Rt),
1881 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1882 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1884 def : Pat<(store (VecTy FPR:$Rt),
1885 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1886 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1889 let AddedComplexity = 10 in {
1890 // Match all store 64 bits width whose type is compatible with FPR64
1891 let Predicates = [IsLE] in {
1892 // We must use ST1 to store vectors in big-endian.
1893 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1894 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1895 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1896 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1897 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1900 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1901 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1903 // Match all store 128 bits width whose type is compatible with FPR128
1904 let Predicates = [IsLE] in {
1905 // We must use ST1 to store vectors in big-endian.
1906 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1907 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1908 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1909 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1910 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1911 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1912 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
1914 } // AddedComplexity = 10
1916 // Match stores from lane 0 to the appropriate subreg's store.
1917 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
1918 ValueType VecTy, ValueType STy,
1919 SubRegIndex SubRegIdx,
1920 Instruction STRW, Instruction STRX> {
1922 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
1923 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1924 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
1925 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1927 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
1928 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1929 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
1930 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1933 let AddedComplexity = 19 in {
1934 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
1935 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
1936 defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
1937 defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
1938 defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
1939 defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
1940 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
1944 // (unsigned immediate)
1945 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1947 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1948 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1950 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1951 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1953 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
1954 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1955 [(store (f16 FPR16:$Rt),
1956 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
1957 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1958 [(store (f32 FPR32:$Rt),
1959 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1960 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1961 [(store (f64 FPR64:$Rt),
1962 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1963 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1965 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1966 [(truncstorei16 GPR32:$Rt,
1967 (am_indexed16 GPR64sp:$Rn,
1968 uimm12s2:$offset))]>;
1969 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
1970 [(truncstorei8 GPR32:$Rt,
1971 (am_indexed8 GPR64sp:$Rn,
1972 uimm12s1:$offset))]>;
1974 // Match all store 64 bits width whose type is compatible with FPR64
1975 let AddedComplexity = 10 in {
1976 let Predicates = [IsLE] in {
1977 // We must use ST1 to store vectors in big-endian.
1978 def : Pat<(store (v2f32 FPR64:$Rt),
1979 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1980 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1981 def : Pat<(store (v8i8 FPR64:$Rt),
1982 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1983 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1984 def : Pat<(store (v4i16 FPR64:$Rt),
1985 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1986 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1987 def : Pat<(store (v2i32 FPR64:$Rt),
1988 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1989 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1990 def : Pat<(store (v4f16 FPR64:$Rt),
1991 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1992 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1994 def : Pat<(store (v1f64 FPR64:$Rt),
1995 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1996 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1997 def : Pat<(store (v1i64 FPR64:$Rt),
1998 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1999 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2001 // Match all store 128 bits width whose type is compatible with FPR128
2002 let Predicates = [IsLE] in {
2003 // We must use ST1 to store vectors in big-endian.
2004 def : Pat<(store (v4f32 FPR128:$Rt),
2005 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2006 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2007 def : Pat<(store (v2f64 FPR128:$Rt),
2008 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2009 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2010 def : Pat<(store (v16i8 FPR128:$Rt),
2011 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2012 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2013 def : Pat<(store (v8i16 FPR128:$Rt),
2014 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2015 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2016 def : Pat<(store (v4i32 FPR128:$Rt),
2017 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2018 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2019 def : Pat<(store (v2i64 FPR128:$Rt),
2020 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2021 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2022 def : Pat<(store (v8f16 FPR128:$Rt),
2023 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2024 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2026 def : Pat<(store (f128 FPR128:$Rt),
2027 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2028 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2031 def : Pat<(truncstorei32 GPR64:$Rt,
2032 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
2033 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2034 def : Pat<(truncstorei16 GPR64:$Rt,
2035 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2036 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
2037 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
2038 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
2040 } // AddedComplexity = 10
2043 // (unscaled immediate)
2044 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2046 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2047 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2049 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2050 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2052 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2053 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2054 [(store (f16 FPR16:$Rt),
2055 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2056 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2057 [(store (f32 FPR32:$Rt),
2058 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2059 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2060 [(store (f64 FPR64:$Rt),
2061 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2062 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2063 [(store (f128 FPR128:$Rt),
2064 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2065 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2066 [(truncstorei16 GPR32:$Rt,
2067 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2068 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2069 [(truncstorei8 GPR32:$Rt,
2070 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2072 // Match all store 64 bits width whose type is compatible with FPR64
2073 let Predicates = [IsLE] in {
2074 // We must use ST1 to store vectors in big-endian.
2075 def : Pat<(store (v2f32 FPR64:$Rt),
2076 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2077 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2078 def : Pat<(store (v8i8 FPR64:$Rt),
2079 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2080 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2081 def : Pat<(store (v4i16 FPR64:$Rt),
2082 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2083 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2084 def : Pat<(store (v2i32 FPR64:$Rt),
2085 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2086 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2087 def : Pat<(store (v4f16 FPR64:$Rt),
2088 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2089 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2091 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2092 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2093 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2094 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2096 // Match all store 128 bits width whose type is compatible with FPR128
2097 let Predicates = [IsLE] in {
2098 // We must use ST1 to store vectors in big-endian.
2099 def : Pat<(store (v4f32 FPR128:$Rt),
2100 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2101 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2102 def : Pat<(store (v2f64 FPR128:$Rt),
2103 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2104 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2105 def : Pat<(store (v16i8 FPR128:$Rt),
2106 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2107 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2108 def : Pat<(store (v8i16 FPR128:$Rt),
2109 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2110 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2111 def : Pat<(store (v4i32 FPR128:$Rt),
2112 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2113 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2114 def : Pat<(store (v2i64 FPR128:$Rt),
2115 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2116 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2117 def : Pat<(store (v2f64 FPR128:$Rt),
2118 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2119 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2120 def : Pat<(store (v8f16 FPR128:$Rt),
2121 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2122 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2125 // unscaled i64 truncating stores
2126 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2127 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2128 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2129 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2130 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2131 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2134 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2135 def : InstAlias<"str $Rt, [$Rn, $offset]",
2136 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2137 def : InstAlias<"str $Rt, [$Rn, $offset]",
2138 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2139 def : InstAlias<"str $Rt, [$Rn, $offset]",
2140 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2141 def : InstAlias<"str $Rt, [$Rn, $offset]",
2142 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2143 def : InstAlias<"str $Rt, [$Rn, $offset]",
2144 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2145 def : InstAlias<"str $Rt, [$Rn, $offset]",
2146 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2147 def : InstAlias<"str $Rt, [$Rn, $offset]",
2148 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2150 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2151 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2152 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2153 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2156 // (unscaled immediate, unprivileged)
2157 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2158 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2160 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2161 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2164 // (immediate pre-indexed)
2165 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2166 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2167 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2168 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2169 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2170 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2171 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2173 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2174 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2177 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2178 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2180 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2181 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2183 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2184 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2187 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2188 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2189 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2190 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2191 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2192 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2193 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2194 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2195 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2196 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2197 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2198 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2199 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2200 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2202 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2203 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2204 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2205 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2206 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2207 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2208 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2209 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2210 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2211 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2212 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2213 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2214 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2215 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2218 // (immediate post-indexed)
2219 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2220 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2221 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2222 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2223 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2224 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2225 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2227 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2228 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2231 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2232 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2234 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2235 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2237 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2238 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2241 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2242 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2243 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2244 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2245 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2246 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2247 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2248 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2249 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2250 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2251 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2252 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2253 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2254 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2256 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2257 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2258 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2259 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2260 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2261 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2262 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2263 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2264 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2265 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2266 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2267 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2268 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2269 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2271 //===----------------------------------------------------------------------===//
2272 // Load/store exclusive instructions.
2273 //===----------------------------------------------------------------------===//
2275 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2276 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2277 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2278 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2280 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2281 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2282 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2283 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2285 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2286 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2287 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2288 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2290 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2291 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2292 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2293 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2295 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2296 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2297 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2298 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2300 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2301 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2302 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2303 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2305 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2306 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2308 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2309 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2311 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2312 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2314 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2315 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2317 //===----------------------------------------------------------------------===//
2318 // Scaled floating point to integer conversion instructions.
2319 //===----------------------------------------------------------------------===//
2321 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2322 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2323 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2324 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2325 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2326 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2327 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2328 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2329 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2330 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2331 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2332 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2333 let isCodeGenOnly = 1 in {
2334 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2335 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2336 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2337 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2340 //===----------------------------------------------------------------------===//
2341 // Scaled integer to floating point conversion instructions.
2342 //===----------------------------------------------------------------------===//
2344 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2345 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2347 //===----------------------------------------------------------------------===//
2348 // Unscaled integer to floating point conversion instruction.
2349 //===----------------------------------------------------------------------===//
2351 defm FMOV : UnscaledConversion<"fmov">;
2353 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
2354 let isReMaterializable = 1, isCodeGenOnly = 1 in {
2355 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
2356 PseudoInstExpansion<(FMOVWSr FPR32:$Rd, WZR)>,
2358 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
2359 PseudoInstExpansion<(FMOVXDr FPR64:$Rd, XZR)>,
2363 //===----------------------------------------------------------------------===//
2364 // Floating point conversion instruction.
2365 //===----------------------------------------------------------------------===//
2367 defm FCVT : FPConversion<"fcvt">;
2369 //===----------------------------------------------------------------------===//
2370 // Floating point single operand instructions.
2371 //===----------------------------------------------------------------------===//
2373 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2374 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2375 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2376 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2377 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2378 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2379 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2380 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2382 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2383 (FRINTNDr FPR64:$Rn)>;
2385 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2386 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2387 // <rdar://problem/13715968>
2388 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2389 let hasSideEffects = 1 in {
2390 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2393 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2395 let SchedRW = [WriteFDiv] in {
2396 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2399 //===----------------------------------------------------------------------===//
2400 // Floating point two operand instructions.
2401 //===----------------------------------------------------------------------===//
2403 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2404 let SchedRW = [WriteFDiv] in {
2405 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2407 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2408 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2409 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2410 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2411 let SchedRW = [WriteFMul] in {
2412 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2413 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2415 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2417 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2418 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2419 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2420 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2421 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2422 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2423 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2424 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2426 //===----------------------------------------------------------------------===//
2427 // Floating point three operand instructions.
2428 //===----------------------------------------------------------------------===//
2430 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2431 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2432 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2433 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2434 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2435 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2436 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2438 // The following def pats catch the case where the LHS of an FMA is negated.
2439 // The TriOpFrag above catches the case where the middle operand is negated.
2441 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2442 // the NEON variant.
2443 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2444 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2446 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2447 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2449 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2451 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2452 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2454 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2455 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2457 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2458 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2460 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2461 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2463 //===----------------------------------------------------------------------===//
2464 // Floating point comparison instructions.
2465 //===----------------------------------------------------------------------===//
2467 defm FCMPE : FPComparison<1, "fcmpe">;
2468 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2470 //===----------------------------------------------------------------------===//
2471 // Floating point conditional comparison instructions.
2472 //===----------------------------------------------------------------------===//
2474 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2475 defm FCCMP : FPCondComparison<0, "fccmp">;
2477 //===----------------------------------------------------------------------===//
2478 // Floating point conditional select instruction.
2479 //===----------------------------------------------------------------------===//
2481 defm FCSEL : FPCondSelect<"fcsel">;
2483 // CSEL instructions providing f128 types need to be handled by a
2484 // pseudo-instruction since the eventual code will need to introduce basic
2485 // blocks and control flow.
2486 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2487 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2488 [(set (f128 FPR128:$Rd),
2489 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2490 (i32 imm:$cond), NZCV))]> {
2492 let usesCustomInserter = 1;
2496 //===----------------------------------------------------------------------===//
2497 // Floating point immediate move.
2498 //===----------------------------------------------------------------------===//
2500 let isReMaterializable = 1 in {
2501 defm FMOV : FPMoveImmediate<"fmov">;
2504 //===----------------------------------------------------------------------===//
2505 // Advanced SIMD two vector instructions.
2506 //===----------------------------------------------------------------------===//
2508 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2509 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2510 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2511 (ABSv8i8 V64:$src)>;
2512 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2513 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2514 (ABSv4i16 V64:$src)>;
2515 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2516 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2517 (ABSv2i32 V64:$src)>;
2518 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2519 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2520 (ABSv16i8 V128:$src)>;
2521 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2522 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2523 (ABSv8i16 V128:$src)>;
2524 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2525 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2526 (ABSv4i32 V128:$src)>;
2527 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2528 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2529 (ABSv2i64 V128:$src)>;
2531 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2532 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2533 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2534 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2535 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2536 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2537 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2538 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2539 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2541 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2542 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2543 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2544 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2545 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2546 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2547 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2548 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2549 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2550 (FCVTLv4i16 V64:$Rn)>;
2551 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2553 (FCVTLv8i16 V128:$Rn)>;
2554 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2555 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2557 (FCVTLv4i32 V128:$Rn)>;
2559 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2560 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2562 (FCVTLv8i16 V128:$Rn)>;
2564 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2565 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2566 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2567 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2568 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2569 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2570 (FCVTNv4i16 V128:$Rn)>;
2571 def : Pat<(concat_vectors V64:$Rd,
2572 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2573 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2574 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2575 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2576 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2577 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2578 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2579 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2580 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2581 int_aarch64_neon_fcvtxn>;
2582 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2583 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2584 let isCodeGenOnly = 1 in {
2585 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2586 int_aarch64_neon_fcvtzs>;
2587 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2588 int_aarch64_neon_fcvtzu>;
2590 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2591 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2592 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2593 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2594 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2595 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2596 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2597 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2598 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2599 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2600 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2601 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2602 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2603 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2604 // Aliases for MVN -> NOT.
2605 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2606 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2607 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2608 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2610 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2611 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2612 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2613 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2614 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2615 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2616 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2618 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2619 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2620 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2621 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2622 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2623 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2624 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2625 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2627 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2628 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2629 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2630 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2631 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2633 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2634 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2635 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2636 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2637 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2638 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2639 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2640 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2641 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2642 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2643 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2644 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2645 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2646 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2647 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2648 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2649 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2650 int_aarch64_neon_uaddlp>;
2651 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2652 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2653 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2654 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2655 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2656 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2658 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2659 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2660 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2661 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2662 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2663 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2665 // Patterns for vector long shift (by element width). These need to match all
2666 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2668 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2669 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2670 (SHLLv8i8 V64:$Rn)>;
2671 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2672 (SHLLv16i8 V128:$Rn)>;
2673 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2674 (SHLLv4i16 V64:$Rn)>;
2675 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2676 (SHLLv8i16 V128:$Rn)>;
2677 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2678 (SHLLv2i32 V64:$Rn)>;
2679 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2680 (SHLLv4i32 V128:$Rn)>;
2683 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2684 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2685 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2687 //===----------------------------------------------------------------------===//
2688 // Advanced SIMD three vector instructions.
2689 //===----------------------------------------------------------------------===//
2691 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2692 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2693 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2694 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2695 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2696 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2697 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2698 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2699 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2700 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2701 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2702 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2703 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2704 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2705 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2706 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2707 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2708 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2709 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2710 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2711 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2712 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2713 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2714 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2715 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2717 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2718 // instruction expects the addend first, while the fma intrinsic puts it last.
2719 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2720 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2721 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2722 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2724 // The following def pats catch the case where the LHS of an FMA is negated.
2725 // The TriOpFrag above catches the case where the middle operand is negated.
2726 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2727 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2729 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2730 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2732 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2733 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2735 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2736 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2737 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2738 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2739 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2740 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2741 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2742 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2743 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2744 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2745 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2746 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2747 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2748 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2749 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2750 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2751 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2752 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2753 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2754 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2755 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2756 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2757 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2758 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2759 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2760 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2761 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2762 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2763 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2764 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2765 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2766 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2767 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2768 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2769 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2770 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2771 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2772 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2773 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2774 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2775 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2776 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2777 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2778 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2779 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2780 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2781 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
2782 int_aarch64_neon_sqadd>;
2783 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
2784 int_aarch64_neon_sqsub>;
2786 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2787 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2788 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2789 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2790 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2791 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2792 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2793 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2794 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2795 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2796 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2798 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2799 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2800 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2801 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2802 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2803 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2804 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2805 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2807 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2808 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2809 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2810 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2811 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2812 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2813 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2814 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2816 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2817 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2818 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2819 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2820 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2821 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2822 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2823 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2825 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2826 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2827 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2828 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2829 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2830 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2831 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2832 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2834 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2835 "|cmls.8b\t$dst, $src1, $src2}",
2836 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2837 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2838 "|cmls.16b\t$dst, $src1, $src2}",
2839 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2840 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2841 "|cmls.4h\t$dst, $src1, $src2}",
2842 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2843 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2844 "|cmls.8h\t$dst, $src1, $src2}",
2845 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2846 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2847 "|cmls.2s\t$dst, $src1, $src2}",
2848 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2849 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2850 "|cmls.4s\t$dst, $src1, $src2}",
2851 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2852 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2853 "|cmls.2d\t$dst, $src1, $src2}",
2854 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2856 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2857 "|cmlo.8b\t$dst, $src1, $src2}",
2858 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2859 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2860 "|cmlo.16b\t$dst, $src1, $src2}",
2861 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2862 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2863 "|cmlo.4h\t$dst, $src1, $src2}",
2864 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2865 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2866 "|cmlo.8h\t$dst, $src1, $src2}",
2867 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2868 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2869 "|cmlo.2s\t$dst, $src1, $src2}",
2870 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2871 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2872 "|cmlo.4s\t$dst, $src1, $src2}",
2873 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2874 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2875 "|cmlo.2d\t$dst, $src1, $src2}",
2876 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2878 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2879 "|cmle.8b\t$dst, $src1, $src2}",
2880 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2881 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2882 "|cmle.16b\t$dst, $src1, $src2}",
2883 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2884 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2885 "|cmle.4h\t$dst, $src1, $src2}",
2886 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2887 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2888 "|cmle.8h\t$dst, $src1, $src2}",
2889 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2890 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2891 "|cmle.2s\t$dst, $src1, $src2}",
2892 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2893 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2894 "|cmle.4s\t$dst, $src1, $src2}",
2895 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2896 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2897 "|cmle.2d\t$dst, $src1, $src2}",
2898 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2900 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2901 "|cmlt.8b\t$dst, $src1, $src2}",
2902 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2903 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2904 "|cmlt.16b\t$dst, $src1, $src2}",
2905 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2906 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2907 "|cmlt.4h\t$dst, $src1, $src2}",
2908 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2909 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2910 "|cmlt.8h\t$dst, $src1, $src2}",
2911 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2912 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2913 "|cmlt.2s\t$dst, $src1, $src2}",
2914 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2915 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2916 "|cmlt.4s\t$dst, $src1, $src2}",
2917 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2918 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2919 "|cmlt.2d\t$dst, $src1, $src2}",
2920 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2922 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2923 "|fcmle.2s\t$dst, $src1, $src2}",
2924 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2925 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2926 "|fcmle.4s\t$dst, $src1, $src2}",
2927 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2928 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2929 "|fcmle.2d\t$dst, $src1, $src2}",
2930 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2932 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2933 "|fcmlt.2s\t$dst, $src1, $src2}",
2934 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2935 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2936 "|fcmlt.4s\t$dst, $src1, $src2}",
2937 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2938 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2939 "|fcmlt.2d\t$dst, $src1, $src2}",
2940 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2942 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2943 "|facle.2s\t$dst, $src1, $src2}",
2944 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2945 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2946 "|facle.4s\t$dst, $src1, $src2}",
2947 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2948 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2949 "|facle.2d\t$dst, $src1, $src2}",
2950 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2952 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2953 "|faclt.2s\t$dst, $src1, $src2}",
2954 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2955 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2956 "|faclt.4s\t$dst, $src1, $src2}",
2957 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2958 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2959 "|faclt.2d\t$dst, $src1, $src2}",
2960 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2962 //===----------------------------------------------------------------------===//
2963 // Advanced SIMD three scalar instructions.
2964 //===----------------------------------------------------------------------===//
2966 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2967 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
2968 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
2969 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
2970 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
2971 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
2972 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
2973 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
2974 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2975 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2976 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2977 int_aarch64_neon_facge>;
2978 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2979 int_aarch64_neon_facgt>;
2980 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2981 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2982 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2983 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
2984 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
2985 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
2986 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
2987 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
2988 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
2989 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
2990 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
2991 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
2992 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
2993 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
2994 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2995 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
2996 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
2997 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
2998 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
2999 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
3000 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
3001 let Predicates = [HasV8_1a] in {
3002 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
3003 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
3004 def : Pat<(i32 (int_aarch64_neon_sqadd
3006 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3007 (i32 FPR32:$Rm))))),
3008 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3009 def : Pat<(i32 (int_aarch64_neon_sqsub
3011 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3012 (i32 FPR32:$Rm))))),
3013 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3016 def : InstAlias<"cmls $dst, $src1, $src2",
3017 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3018 def : InstAlias<"cmle $dst, $src1, $src2",
3019 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3020 def : InstAlias<"cmlo $dst, $src1, $src2",
3021 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3022 def : InstAlias<"cmlt $dst, $src1, $src2",
3023 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3024 def : InstAlias<"fcmle $dst, $src1, $src2",
3025 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3026 def : InstAlias<"fcmle $dst, $src1, $src2",
3027 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3028 def : InstAlias<"fcmlt $dst, $src1, $src2",
3029 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3030 def : InstAlias<"fcmlt $dst, $src1, $src2",
3031 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3032 def : InstAlias<"facle $dst, $src1, $src2",
3033 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3034 def : InstAlias<"facle $dst, $src1, $src2",
3035 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3036 def : InstAlias<"faclt $dst, $src1, $src2",
3037 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3038 def : InstAlias<"faclt $dst, $src1, $src2",
3039 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3041 //===----------------------------------------------------------------------===//
3042 // Advanced SIMD three scalar instructions (mixed operands).
3043 //===----------------------------------------------------------------------===//
3044 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3045 int_aarch64_neon_sqdmulls_scalar>;
3046 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
3047 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3049 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3050 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3051 (i32 FPR32:$Rm))))),
3052 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3053 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3054 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3055 (i32 FPR32:$Rm))))),
3056 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3058 //===----------------------------------------------------------------------===//
3059 // Advanced SIMD two scalar instructions.
3060 //===----------------------------------------------------------------------===//
3062 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
3063 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3064 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3065 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3066 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3067 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3068 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3069 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3070 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3071 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3072 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3073 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
3074 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
3075 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
3076 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
3077 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
3078 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
3079 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
3080 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
3081 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3082 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
3083 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
3084 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
3085 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
3086 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
3087 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3088 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3089 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3090 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3091 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3092 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3093 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3094 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3095 int_aarch64_neon_suqadd>;
3096 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3097 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3098 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3099 int_aarch64_neon_usqadd>;
3101 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3103 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3104 (FCVTASv1i64 FPR64:$Rn)>;
3105 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3106 (FCVTAUv1i64 FPR64:$Rn)>;
3107 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3108 (FCVTMSv1i64 FPR64:$Rn)>;
3109 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3110 (FCVTMUv1i64 FPR64:$Rn)>;
3111 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3112 (FCVTNSv1i64 FPR64:$Rn)>;
3113 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3114 (FCVTNUv1i64 FPR64:$Rn)>;
3115 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3116 (FCVTPSv1i64 FPR64:$Rn)>;
3117 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3118 (FCVTPUv1i64 FPR64:$Rn)>;
3120 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3121 (FRECPEv1i32 FPR32:$Rn)>;
3122 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3123 (FRECPEv1i64 FPR64:$Rn)>;
3124 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3125 (FRECPEv1i64 FPR64:$Rn)>;
3127 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3128 (FRECPXv1i32 FPR32:$Rn)>;
3129 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3130 (FRECPXv1i64 FPR64:$Rn)>;
3132 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3133 (FRSQRTEv1i32 FPR32:$Rn)>;
3134 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3135 (FRSQRTEv1i64 FPR64:$Rn)>;
3136 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3137 (FRSQRTEv1i64 FPR64:$Rn)>;
3139 // If an integer is about to be converted to a floating point value,
3140 // just load it on the floating point unit.
3141 // Here are the patterns for 8 and 16-bits to float.
3143 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3144 SDPatternOperator loadop, Instruction UCVTF,
3145 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3147 def : Pat<(DstTy (uint_to_fp (SrcTy
3148 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3149 ro.Wext:$extend))))),
3150 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3151 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3154 def : Pat<(DstTy (uint_to_fp (SrcTy
3155 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3156 ro.Wext:$extend))))),
3157 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3158 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3162 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3163 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3164 def : Pat <(f32 (uint_to_fp (i32
3165 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3166 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3167 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3168 def : Pat <(f32 (uint_to_fp (i32
3169 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3170 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3171 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3172 // 16-bits -> float.
3173 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3174 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3175 def : Pat <(f32 (uint_to_fp (i32
3176 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3177 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3178 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3179 def : Pat <(f32 (uint_to_fp (i32
3180 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3181 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3182 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3183 // 32-bits are handled in target specific dag combine:
3184 // performIntToFpCombine.
3185 // 64-bits integer to 32-bits floating point, not possible with
3186 // UCVTF on floating point registers (both source and destination
3187 // must have the same size).
3189 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3190 // 8-bits -> double.
3191 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3192 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3193 def : Pat <(f64 (uint_to_fp (i32
3194 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3195 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3196 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3197 def : Pat <(f64 (uint_to_fp (i32
3198 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3199 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3200 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3201 // 16-bits -> double.
3202 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3203 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3204 def : Pat <(f64 (uint_to_fp (i32
3205 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3206 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3207 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3208 def : Pat <(f64 (uint_to_fp (i32
3209 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3210 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3211 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3212 // 32-bits -> double.
3213 defm : UIntToFPROLoadPat<f64, i32, load,
3214 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3215 def : Pat <(f64 (uint_to_fp (i32
3216 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3217 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3218 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3219 def : Pat <(f64 (uint_to_fp (i32
3220 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3221 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3222 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3223 // 64-bits -> double are handled in target specific dag combine:
3224 // performIntToFpCombine.
3226 //===----------------------------------------------------------------------===//
3227 // Advanced SIMD three different-sized vector instructions.
3228 //===----------------------------------------------------------------------===//
3230 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3231 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3232 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3233 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3234 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3235 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3236 int_aarch64_neon_sabd>;
3237 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3238 int_aarch64_neon_sabd>;
3239 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3240 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3241 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3242 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3243 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3244 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3245 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3246 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3247 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3248 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3249 int_aarch64_neon_sqadd>;
3250 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3251 int_aarch64_neon_sqsub>;
3252 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3253 int_aarch64_neon_sqdmull>;
3254 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3255 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3256 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3257 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3258 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3259 int_aarch64_neon_uabd>;
3260 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3261 int_aarch64_neon_uabd>;
3262 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3263 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3264 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3265 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3266 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3267 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3268 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3269 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3270 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3271 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3272 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3273 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3274 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3276 // Additional patterns for SMULL and UMULL
3277 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3278 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3279 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3280 (INST8B V64:$Rn, V64:$Rm)>;
3281 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3282 (INST4H V64:$Rn, V64:$Rm)>;
3283 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3284 (INST2S V64:$Rn, V64:$Rm)>;
3287 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3288 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3289 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3290 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3292 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3293 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3294 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3295 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3296 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3297 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3298 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3299 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3300 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3303 defm : Neon_mulacc_widen_patterns<
3304 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3305 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3306 defm : Neon_mulacc_widen_patterns<
3307 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3308 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3309 defm : Neon_mulacc_widen_patterns<
3310 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3311 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3312 defm : Neon_mulacc_widen_patterns<
3313 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3314 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3316 // Patterns for 64-bit pmull
3317 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3318 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3319 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3320 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3321 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3323 // CodeGen patterns for addhn and subhn instructions, which can actually be
3324 // written in LLVM IR without too much difficulty.
3327 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3328 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3329 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3331 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3332 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3334 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3335 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3336 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3338 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3339 V128:$Rn, V128:$Rm)>;
3340 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3341 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3343 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3344 V128:$Rn, V128:$Rm)>;
3345 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3346 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3348 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3349 V128:$Rn, V128:$Rm)>;
3352 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3353 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3354 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3356 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3357 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3359 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3360 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3361 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3363 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3364 V128:$Rn, V128:$Rm)>;
3365 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3366 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3368 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3369 V128:$Rn, V128:$Rm)>;
3370 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3371 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3373 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3374 V128:$Rn, V128:$Rm)>;
3376 //----------------------------------------------------------------------------
3377 // AdvSIMD bitwise extract from vector instruction.
3378 //----------------------------------------------------------------------------
3380 defm EXT : SIMDBitwiseExtract<"ext">;
3382 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3383 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3384 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3385 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3386 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3387 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3388 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3389 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3390 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3391 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3392 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3393 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3394 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3395 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3396 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3397 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3398 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3399 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3400 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3401 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3403 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3405 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3406 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3407 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3408 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3409 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3410 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3411 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3412 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3413 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3414 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3415 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3416 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3417 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3418 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3421 //----------------------------------------------------------------------------
3422 // AdvSIMD zip vector
3423 //----------------------------------------------------------------------------
3425 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3426 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3427 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3428 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3429 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3430 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3432 //----------------------------------------------------------------------------
3433 // AdvSIMD TBL/TBX instructions
3434 //----------------------------------------------------------------------------
3436 defm TBL : SIMDTableLookup< 0, "tbl">;
3437 defm TBX : SIMDTableLookupTied<1, "tbx">;
3439 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3440 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3441 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3442 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3444 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3445 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3446 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3447 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3448 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3449 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3452 //----------------------------------------------------------------------------
3453 // AdvSIMD scalar CPY instruction
3454 //----------------------------------------------------------------------------
3456 defm CPY : SIMDScalarCPY<"cpy">;
3458 //----------------------------------------------------------------------------
3459 // AdvSIMD scalar pairwise instructions
3460 //----------------------------------------------------------------------------
3462 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3463 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3464 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3465 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3466 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3467 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3468 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
3469 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3470 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),
3471 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3472 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3473 (FADDPv2i32p V64:$Rn)>;
3474 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3475 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3476 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3477 (FADDPv2i64p V128:$Rn)>;
3478 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3479 (FMAXNMPv2i32p V64:$Rn)>;
3480 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3481 (FMAXNMPv2i64p V128:$Rn)>;
3482 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3483 (FMAXPv2i32p V64:$Rn)>;
3484 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3485 (FMAXPv2i64p V128:$Rn)>;
3486 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3487 (FMINNMPv2i32p V64:$Rn)>;
3488 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3489 (FMINNMPv2i64p V128:$Rn)>;
3490 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3491 (FMINPv2i32p V64:$Rn)>;
3492 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3493 (FMINPv2i64p V128:$Rn)>;
3495 //----------------------------------------------------------------------------
3496 // AdvSIMD INS/DUP instructions
3497 //----------------------------------------------------------------------------
3499 def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>;
3500 def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>;
3501 def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>;
3502 def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>;
3503 def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>;
3504 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;
3505 def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>;
3507 def DUPv2i64lane : SIMDDup64FromElement;
3508 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3509 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3510 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3511 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3512 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3513 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3515 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3516 (v2f32 (DUPv2i32lane
3517 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3519 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3520 (v4f32 (DUPv4i32lane
3521 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3523 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3524 (v2f64 (DUPv2i64lane
3525 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3527 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3528 (v4f16 (DUPv4i16lane
3529 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3531 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3532 (v8f16 (DUPv8i16lane
3533 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3536 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3537 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3538 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3539 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3541 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3542 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3543 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3544 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3545 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3546 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3548 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3549 // instruction even if the types don't match: we just have to remap the lane
3550 // carefully. N.b. this trick only applies to truncations.
3551 def VecIndex_x2 : SDNodeXForm<imm, [{
3552 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3554 def VecIndex_x4 : SDNodeXForm<imm, [{
3555 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3557 def VecIndex_x8 : SDNodeXForm<imm, [{
3558 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3561 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3562 ValueType Src128VT, ValueType ScalVT,
3563 Instruction DUP, SDNodeXForm IdxXFORM> {
3564 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3566 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3568 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3570 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3573 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3574 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3575 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3577 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3578 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3579 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3581 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3582 SDNodeXForm IdxXFORM> {
3583 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3585 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3587 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3589 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3592 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3593 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3594 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3596 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3597 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3598 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3600 // SMOV and UMOV definitions, with some extra patterns for convenience
3604 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3605 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3606 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3607 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3608 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3609 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3610 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3611 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3612 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3613 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3614 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3615 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3617 // Extracting i8 or i16 elements will have the zero-extend transformed to
3618 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3619 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3620 // bits of the destination register.
3621 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3623 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3624 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3626 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3630 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3631 (SUBREG_TO_REG (i32 0),
3632 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3633 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3634 (SUBREG_TO_REG (i32 0),
3635 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3637 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3638 (SUBREG_TO_REG (i32 0),
3639 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3640 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3641 (SUBREG_TO_REG (i32 0),
3642 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3644 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3645 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3646 (i32 FPR32:$Rn), ssub))>;
3647 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3648 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3649 (i32 FPR32:$Rn), ssub))>;
3650 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3651 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3652 (i64 FPR64:$Rn), dsub))>;
3654 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3655 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3656 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3657 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3658 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3659 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3661 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3662 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3665 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3667 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3671 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3672 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3674 V128:$Rn, VectorIndexH:$imm,
3675 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3678 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3679 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3682 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3684 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3687 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3688 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3690 V128:$Rn, VectorIndexS:$imm,
3691 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3693 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3694 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3696 V128:$Rn, VectorIndexD:$imm,
3697 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3700 // Copy an element at a constant index in one vector into a constant indexed
3701 // element of another.
3702 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3703 // index type and INS extension
3704 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3705 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3706 VectorIndexB:$idx2)),
3708 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3710 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3711 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3712 VectorIndexH:$idx2)),
3714 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3716 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3717 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3718 VectorIndexS:$idx2)),
3720 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3722 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3723 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3724 VectorIndexD:$idx2)),
3726 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3729 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3730 ValueType VTScal, Instruction INS> {
3731 def : Pat<(VT128 (vector_insert V128:$src,
3732 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3734 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3736 def : Pat<(VT128 (vector_insert V128:$src,
3737 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3739 (INS V128:$src, imm:$Immd,
3740 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3742 def : Pat<(VT64 (vector_insert V64:$src,
3743 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3745 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3746 imm:$Immd, V128:$Rn, imm:$Immn),
3749 def : Pat<(VT64 (vector_insert V64:$src,
3750 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3753 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3754 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3758 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3759 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3760 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3763 // Floating point vector extractions are codegen'd as either a sequence of
3764 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
3765 // the lane number is anything other than zero.
3766 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3767 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3768 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3769 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3770 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3771 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3773 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3774 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
3775 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3776 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
3777 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3778 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
3780 // All concat_vectors operations are canonicalised to act on i64 vectors for
3781 // AArch64. In the general case we need an instruction, which had just as well be
3783 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3784 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3785 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3786 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3788 def : ConcatPat<v2i64, v1i64>;
3789 def : ConcatPat<v2f64, v1f64>;
3790 def : ConcatPat<v4i32, v2i32>;
3791 def : ConcatPat<v4f32, v2f32>;
3792 def : ConcatPat<v8i16, v4i16>;
3793 def : ConcatPat<v8f16, v4f16>;
3794 def : ConcatPat<v16i8, v8i8>;
3796 // If the high lanes are undef, though, we can just ignore them:
3797 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3798 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3799 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3801 def : ConcatUndefPat<v2i64, v1i64>;
3802 def : ConcatUndefPat<v2f64, v1f64>;
3803 def : ConcatUndefPat<v4i32, v2i32>;
3804 def : ConcatUndefPat<v4f32, v2f32>;
3805 def : ConcatUndefPat<v8i16, v4i16>;
3806 def : ConcatUndefPat<v16i8, v8i8>;
3808 //----------------------------------------------------------------------------
3809 // AdvSIMD across lanes instructions
3810 //----------------------------------------------------------------------------
3812 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3813 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3814 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3815 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3816 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3817 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3818 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3819 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3820 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3821 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3822 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3824 // Patterns for across-vector intrinsics, that have a node equivalent, that
3825 // returns a vector (with only the low lane defined) instead of a scalar.
3826 // In effect, opNode is the same as (scalar_to_vector (IntNode)).
3827 multiclass SIMDAcrossLanesIntrinsic<string baseOpc,
3828 SDPatternOperator opNode> {
3829 // If a lane instruction caught the vector_extract around opNode, we can
3830 // directly match the latter to the instruction.
3831 def : Pat<(v8i8 (opNode V64:$Rn)),
3832 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3833 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;
3834 def : Pat<(v16i8 (opNode V128:$Rn)),
3835 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3836 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;
3837 def : Pat<(v4i16 (opNode V64:$Rn)),
3838 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3839 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;
3840 def : Pat<(v8i16 (opNode V128:$Rn)),
3841 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3842 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;
3843 def : Pat<(v4i32 (opNode V128:$Rn)),
3844 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3845 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;
3848 // If none did, fallback to the explicit patterns, consuming the vector_extract.
3849 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
3850 (i32 0)), (i64 0))),
3851 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3852 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),
3854 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
3855 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3856 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),
3858 def : Pat<(i32 (vector_extract (insert_subvector undef,
3859 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))),
3860 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3861 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),
3863 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
3864 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3865 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),
3867 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
3868 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3869 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),
3874 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,
3875 SDPatternOperator opNode>
3876 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
3877 // If there is a sign extension after this intrinsic, consume it as smov already
3879 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
3880 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)),
3882 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3883 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3885 def : Pat<(i32 (sext_inreg (i32 (vector_extract
3886 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),
3888 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3889 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3891 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
3892 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)),
3894 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3895 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3897 def : Pat<(i32 (sext_inreg (i32 (vector_extract
3898 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),
3900 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3901 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3905 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
3906 SDPatternOperator opNode>
3907 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
3908 // If there is a masking operation keeping only what has been actually
3909 // generated, consume it.
3910 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
3911 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)),
3912 (i32 (EXTRACT_SUBREG
3913 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3914 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3916 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
3918 (i32 (EXTRACT_SUBREG
3919 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3920 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3922 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
3923 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)),
3924 (i32 (EXTRACT_SUBREG
3925 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3926 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3928 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
3930 (i32 (EXTRACT_SUBREG
3931 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3932 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3936 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;
3937 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3938 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
3939 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
3941 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;
3942 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3943 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
3944 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
3946 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;
3947 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
3948 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
3950 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
3951 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
3952 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
3954 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;
3955 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
3956 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
3958 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
3959 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
3960 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
3962 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3963 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3965 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3966 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3968 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3970 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3971 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3974 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3975 (i32 (EXTRACT_SUBREG
3976 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3977 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3979 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3980 (i32 (EXTRACT_SUBREG
3981 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3982 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3985 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3986 (i64 (EXTRACT_SUBREG
3987 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3988 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3992 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3994 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3995 (i32 (EXTRACT_SUBREG
3996 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3997 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3999 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4000 (i32 (EXTRACT_SUBREG
4001 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4002 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4005 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4006 (i32 (EXTRACT_SUBREG
4007 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4008 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4010 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4011 (i32 (EXTRACT_SUBREG
4012 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4013 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4016 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4017 (i64 (EXTRACT_SUBREG
4018 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4019 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4023 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
4024 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
4026 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
4027 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
4028 (i64 (EXTRACT_SUBREG
4029 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4030 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
4032 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4033 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4034 (i64 (EXTRACT_SUBREG
4035 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4036 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4039 //------------------------------------------------------------------------------
4040 // AdvSIMD modified immediate instructions
4041 //------------------------------------------------------------------------------
4044 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4046 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4048 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4049 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4050 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4051 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4053 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4054 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4055 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4056 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4058 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4059 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4060 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4061 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4063 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4064 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4065 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4066 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4069 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
4071 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4072 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
4074 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4075 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
4077 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4081 // EDIT byte mask: scalar
4082 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4083 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4084 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4085 // The movi_edit node has the immediate value already encoded, so we use
4086 // a plain imm0_255 here.
4087 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4088 (MOVID imm0_255:$shift)>;
4090 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4091 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4092 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4093 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4095 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4096 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4097 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4098 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4100 // EDIT byte mask: 2d
4102 // The movi_edit node has the immediate value already encoded, so we use
4103 // a plain imm0_255 in the pattern
4104 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4105 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
4108 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4111 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4112 // Complexity is added to break a tie with a plain MOVI.
4113 let AddedComplexity = 1 in {
4114 def : Pat<(f32 fpimm0),
4115 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4117 def : Pat<(f64 fpimm0),
4118 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4122 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4123 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4124 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4125 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4127 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4128 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4129 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4130 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4132 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4133 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4135 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4136 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4138 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4139 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4140 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4141 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4143 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4144 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4145 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4146 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4148 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4149 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4150 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4151 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4152 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4153 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4154 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4155 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4157 // EDIT per word: 2s & 4s with MSL shifter
4158 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4159 [(set (v2i32 V64:$Rd),
4160 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4161 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4162 [(set (v4i32 V128:$Rd),
4163 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4165 // Per byte: 8b & 16b
4166 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4168 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4169 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4171 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4175 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4176 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4178 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4179 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4180 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4181 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4183 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4184 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4185 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4186 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4188 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4189 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4190 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4191 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4192 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4193 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4194 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4195 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4197 // EDIT per word: 2s & 4s with MSL shifter
4198 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4199 [(set (v2i32 V64:$Rd),
4200 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4201 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4202 [(set (v4i32 V128:$Rd),
4203 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4205 //----------------------------------------------------------------------------
4206 // AdvSIMD indexed element
4207 //----------------------------------------------------------------------------
4209 let hasSideEffects = 0 in {
4210 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
4211 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
4214 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4215 // instruction expects the addend first, while the intrinsic expects it last.
4217 // On the other hand, there are quite a few valid combinatorial options due to
4218 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4219 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4220 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4221 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4222 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4224 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4225 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4226 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4227 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4228 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4229 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4230 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4231 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4233 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4234 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4236 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4237 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4238 VectorIndexS:$idx))),
4239 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4240 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4241 (v2f32 (AArch64duplane32
4242 (v4f32 (insert_subvector undef,
4243 (v2f32 (fneg V64:$Rm)),
4245 VectorIndexS:$idx)))),
4246 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4247 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4248 VectorIndexS:$idx)>;
4249 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4250 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4251 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4252 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4254 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4256 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4257 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4258 VectorIndexS:$idx))),
4259 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4260 VectorIndexS:$idx)>;
4261 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4262 (v4f32 (AArch64duplane32
4263 (v4f32 (insert_subvector undef,
4264 (v2f32 (fneg V64:$Rm)),
4266 VectorIndexS:$idx)))),
4267 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4268 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4269 VectorIndexS:$idx)>;
4270 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4271 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4272 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4273 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4275 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4276 // (DUPLANE from 64-bit would be trivial).
4277 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4278 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4279 VectorIndexD:$idx))),
4281 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4282 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4283 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4284 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4285 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4287 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4288 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4289 (vector_extract (v4f32 (fneg V128:$Rm)),
4290 VectorIndexS:$idx))),
4291 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4292 V128:$Rm, VectorIndexS:$idx)>;
4293 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4294 (vector_extract (v2f32 (fneg V64:$Rm)),
4295 VectorIndexS:$idx))),
4296 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4297 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4299 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4300 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4301 (vector_extract (v2f64 (fneg V128:$Rm)),
4302 VectorIndexS:$idx))),
4303 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4304 V128:$Rm, VectorIndexS:$idx)>;
4307 defm : FMLSIndexedAfterNegPatterns<
4308 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4309 defm : FMLSIndexedAfterNegPatterns<
4310 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4312 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4313 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4315 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4316 (FMULv2i32_indexed V64:$Rn,
4317 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4319 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4320 (FMULv4i32_indexed V128:$Rn,
4321 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4323 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4324 (FMULv2i64_indexed V128:$Rn,
4325 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4328 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4329 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4330 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4331 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4332 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4333 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4334 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4335 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4336 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4337 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4338 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4339 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4340 int_aarch64_neon_smull>;
4341 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4342 int_aarch64_neon_sqadd>;
4343 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4344 int_aarch64_neon_sqsub>;
4345 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
4346 int_aarch64_neon_sqadd>;
4347 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
4348 int_aarch64_neon_sqsub>;
4349 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4350 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4351 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4352 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4353 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4354 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4355 int_aarch64_neon_umull>;
4357 // A scalar sqdmull with the second operand being a vector lane can be
4358 // handled directly with the indexed instruction encoding.
4359 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4360 (vector_extract (v4i32 V128:$Vm),
4361 VectorIndexS:$idx)),
4362 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4364 //----------------------------------------------------------------------------
4365 // AdvSIMD scalar shift instructions
4366 //----------------------------------------------------------------------------
4367 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4368 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4369 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4370 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4371 // Codegen patterns for the above. We don't put these directly on the
4372 // instructions because TableGen's type inference can't handle the truth.
4373 // Having the same base pattern for fp <--> int totally freaks it out.
4374 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4375 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4376 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4377 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4378 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4379 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4380 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4381 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4382 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4384 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4385 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4387 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4388 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4389 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4390 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4391 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4392 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4393 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4394 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4395 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4396 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4398 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4399 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4401 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4403 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4404 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4405 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4406 int_aarch64_neon_sqrshrn>;
4407 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4408 int_aarch64_neon_sqrshrun>;
4409 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4410 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4411 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4412 int_aarch64_neon_sqshrn>;
4413 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4414 int_aarch64_neon_sqshrun>;
4415 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4416 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4417 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4418 TriOpFrag<(add node:$LHS,
4419 (AArch64srshri node:$MHS, node:$RHS))>>;
4420 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4421 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4422 TriOpFrag<(add node:$LHS,
4423 (AArch64vashr node:$MHS, node:$RHS))>>;
4424 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4425 int_aarch64_neon_uqrshrn>;
4426 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4427 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4428 int_aarch64_neon_uqshrn>;
4429 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4430 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4431 TriOpFrag<(add node:$LHS,
4432 (AArch64urshri node:$MHS, node:$RHS))>>;
4433 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4434 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4435 TriOpFrag<(add node:$LHS,
4436 (AArch64vlshr node:$MHS, node:$RHS))>>;
4438 //----------------------------------------------------------------------------
4439 // AdvSIMD vector shift instructions
4440 //----------------------------------------------------------------------------
4441 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4442 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4443 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4444 int_aarch64_neon_vcvtfxs2fp>;
4445 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4446 int_aarch64_neon_rshrn>;
4447 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4448 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4449 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4450 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4451 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4452 (i32 vecshiftL64:$imm))),
4453 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4454 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4455 int_aarch64_neon_sqrshrn>;
4456 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4457 int_aarch64_neon_sqrshrun>;
4458 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4459 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4460 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4461 int_aarch64_neon_sqshrn>;
4462 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4463 int_aarch64_neon_sqshrun>;
4464 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4465 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4466 (i32 vecshiftR64:$imm))),
4467 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4468 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4469 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4470 TriOpFrag<(add node:$LHS,
4471 (AArch64srshri node:$MHS, node:$RHS))> >;
4472 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4473 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4475 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4476 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4477 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4478 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4479 int_aarch64_neon_vcvtfxu2fp>;
4480 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4481 int_aarch64_neon_uqrshrn>;
4482 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4483 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4484 int_aarch64_neon_uqshrn>;
4485 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4486 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4487 TriOpFrag<(add node:$LHS,
4488 (AArch64urshri node:$MHS, node:$RHS))> >;
4489 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4490 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4491 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4492 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4493 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4495 // SHRN patterns for when a logical right shift was used instead of arithmetic
4496 // (the immediate guarantees no sign bits actually end up in the result so it
4498 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4499 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4500 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4501 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4502 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4503 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4505 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4506 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4507 vecshiftR16Narrow:$imm)))),
4508 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4509 V128:$Rn, vecshiftR16Narrow:$imm)>;
4510 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4511 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4512 vecshiftR32Narrow:$imm)))),
4513 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4514 V128:$Rn, vecshiftR32Narrow:$imm)>;
4515 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4516 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4517 vecshiftR64Narrow:$imm)))),
4518 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4519 V128:$Rn, vecshiftR32Narrow:$imm)>;
4521 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4522 // Anyexts are implemented as zexts.
4523 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4524 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4525 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4526 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4527 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4528 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4529 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4530 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4531 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4532 // Also match an extend from the upper half of a 128 bit source register.
4533 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4534 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4535 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4536 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4537 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4538 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4539 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4540 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4541 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4542 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4543 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4544 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4545 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4546 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4547 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4548 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4549 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4550 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4552 // Vector shift sxtl aliases
4553 def : InstAlias<"sxtl.8h $dst, $src1",
4554 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4555 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4556 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4557 def : InstAlias<"sxtl.4s $dst, $src1",
4558 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4559 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4560 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4561 def : InstAlias<"sxtl.2d $dst, $src1",
4562 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4563 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4564 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4566 // Vector shift sxtl2 aliases
4567 def : InstAlias<"sxtl2.8h $dst, $src1",
4568 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4569 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4570 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4571 def : InstAlias<"sxtl2.4s $dst, $src1",
4572 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4573 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4574 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4575 def : InstAlias<"sxtl2.2d $dst, $src1",
4576 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4577 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4578 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4580 // Vector shift uxtl aliases
4581 def : InstAlias<"uxtl.8h $dst, $src1",
4582 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4583 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4584 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4585 def : InstAlias<"uxtl.4s $dst, $src1",
4586 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4587 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4588 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4589 def : InstAlias<"uxtl.2d $dst, $src1",
4590 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4591 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4592 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4594 // Vector shift uxtl2 aliases
4595 def : InstAlias<"uxtl2.8h $dst, $src1",
4596 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4597 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4598 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4599 def : InstAlias<"uxtl2.4s $dst, $src1",
4600 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4601 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4602 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4603 def : InstAlias<"uxtl2.2d $dst, $src1",
4604 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4605 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4606 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4608 // If an integer is about to be converted to a floating point value,
4609 // just load it on the floating point unit.
4610 // These patterns are more complex because floating point loads do not
4611 // support sign extension.
4612 // The sign extension has to be explicitly added and is only supported for
4613 // one step: byte-to-half, half-to-word, word-to-doubleword.
4614 // SCVTF GPR -> FPR is 9 cycles.
4615 // SCVTF FPR -> FPR is 4 cyclces.
4616 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4617 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4618 // and still being faster.
4619 // However, this is not good for code size.
4620 // 8-bits -> float. 2 sizes step-up.
4621 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4622 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4623 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4628 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4634 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4636 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4637 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4638 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4639 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4640 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4641 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4642 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4643 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4645 // 16-bits -> float. 1 size step-up.
4646 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4647 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4648 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4650 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4654 ssub)))>, Requires<[NotForCodeSize]>;
4656 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4657 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4658 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4659 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4660 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4661 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4662 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4663 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4665 // 32-bits to 32-bits are handled in target specific dag combine:
4666 // performIntToFpCombine.
4667 // 64-bits integer to 32-bits floating point, not possible with
4668 // SCVTF on floating point registers (both source and destination
4669 // must have the same size).
4671 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4672 // 8-bits -> double. 3 size step-up: give up.
4673 // 16-bits -> double. 2 size step.
4674 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4675 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4676 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4681 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4687 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4689 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4690 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4691 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4692 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4693 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4694 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4695 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4696 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4697 // 32-bits -> double. 1 size step-up.
4698 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4699 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4700 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4702 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4706 dsub)))>, Requires<[NotForCodeSize]>;
4708 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4709 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4710 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4711 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4712 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4713 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4714 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4715 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4717 // 64-bits -> double are handled in target specific dag combine:
4718 // performIntToFpCombine.
4721 //----------------------------------------------------------------------------
4722 // AdvSIMD Load-Store Structure
4723 //----------------------------------------------------------------------------
4724 defm LD1 : SIMDLd1Multiple<"ld1">;
4725 defm LD2 : SIMDLd2Multiple<"ld2">;
4726 defm LD3 : SIMDLd3Multiple<"ld3">;
4727 defm LD4 : SIMDLd4Multiple<"ld4">;
4729 defm ST1 : SIMDSt1Multiple<"st1">;
4730 defm ST2 : SIMDSt2Multiple<"st2">;
4731 defm ST3 : SIMDSt3Multiple<"st3">;
4732 defm ST4 : SIMDSt4Multiple<"st4">;
4734 class Ld1Pat<ValueType ty, Instruction INST>
4735 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4737 def : Ld1Pat<v16i8, LD1Onev16b>;
4738 def : Ld1Pat<v8i16, LD1Onev8h>;
4739 def : Ld1Pat<v4i32, LD1Onev4s>;
4740 def : Ld1Pat<v2i64, LD1Onev2d>;
4741 def : Ld1Pat<v8i8, LD1Onev8b>;
4742 def : Ld1Pat<v4i16, LD1Onev4h>;
4743 def : Ld1Pat<v2i32, LD1Onev2s>;
4744 def : Ld1Pat<v1i64, LD1Onev1d>;
4746 class St1Pat<ValueType ty, Instruction INST>
4747 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4748 (INST ty:$Vt, GPR64sp:$Rn)>;
4750 def : St1Pat<v16i8, ST1Onev16b>;
4751 def : St1Pat<v8i16, ST1Onev8h>;
4752 def : St1Pat<v4i32, ST1Onev4s>;
4753 def : St1Pat<v2i64, ST1Onev2d>;
4754 def : St1Pat<v8i8, ST1Onev8b>;
4755 def : St1Pat<v4i16, ST1Onev4h>;
4756 def : St1Pat<v2i32, ST1Onev2s>;
4757 def : St1Pat<v1i64, ST1Onev1d>;
4763 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4764 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4765 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4766 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4767 let mayLoad = 1, hasSideEffects = 0 in {
4768 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4769 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4770 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4771 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4772 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4773 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4774 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4775 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4776 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4777 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4778 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4779 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4780 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4781 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4782 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4783 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4786 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4787 (LD1Rv8b GPR64sp:$Rn)>;
4788 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4789 (LD1Rv16b GPR64sp:$Rn)>;
4790 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4791 (LD1Rv4h GPR64sp:$Rn)>;
4792 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4793 (LD1Rv8h GPR64sp:$Rn)>;
4794 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4795 (LD1Rv2s GPR64sp:$Rn)>;
4796 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4797 (LD1Rv4s GPR64sp:$Rn)>;
4798 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4799 (LD1Rv2d GPR64sp:$Rn)>;
4800 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4801 (LD1Rv1d GPR64sp:$Rn)>;
4802 // Grab the floating point version too
4803 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4804 (LD1Rv2s GPR64sp:$Rn)>;
4805 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4806 (LD1Rv4s GPR64sp:$Rn)>;
4807 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4808 (LD1Rv2d GPR64sp:$Rn)>;
4809 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4810 (LD1Rv1d GPR64sp:$Rn)>;
4811 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4812 (LD1Rv4h GPR64sp:$Rn)>;
4813 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4814 (LD1Rv8h GPR64sp:$Rn)>;
4816 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4817 ValueType VTy, ValueType STy, Instruction LD1>
4818 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4819 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4820 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4822 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4823 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4824 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4825 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4826 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4827 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4828 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4830 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4831 ValueType VTy, ValueType STy, Instruction LD1>
4832 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4833 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4835 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4836 VecIndex:$idx, GPR64sp:$Rn),
4839 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4840 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4841 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4842 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4843 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4846 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4847 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4848 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4849 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4852 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4853 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4854 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4855 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4857 let AddedComplexity = 19 in
4858 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4859 ValueType VTy, ValueType STy, Instruction ST1>
4861 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4863 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4865 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4866 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4867 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4868 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4869 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4870 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4871 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
4873 let AddedComplexity = 19 in
4874 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4875 ValueType VTy, ValueType STy, Instruction ST1>
4877 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4879 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4880 VecIndex:$idx, GPR64sp:$Rn)>;
4882 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4883 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4884 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4885 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4886 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
4888 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4889 ValueType VTy, ValueType STy, Instruction ST1,
4891 def : Pat<(scalar_store
4892 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4893 GPR64sp:$Rn, offset),
4894 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4895 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4897 def : Pat<(scalar_store
4898 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4899 GPR64sp:$Rn, GPR64:$Rm),
4900 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4901 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4904 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4905 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4907 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4908 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4909 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4910 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4911 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
4913 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4914 ValueType VTy, ValueType STy, Instruction ST1,
4916 def : Pat<(scalar_store
4917 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4918 GPR64sp:$Rn, offset),
4919 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4921 def : Pat<(scalar_store
4922 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4923 GPR64sp:$Rn, GPR64:$Rm),
4924 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4927 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4929 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4931 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4932 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4933 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4934 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4935 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
4937 let mayStore = 1, hasSideEffects = 0 in {
4938 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4939 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4940 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4941 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4942 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4943 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4944 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4945 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4946 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4947 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4948 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4949 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4952 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4953 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4954 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4955 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4957 //----------------------------------------------------------------------------
4958 // Crypto extensions
4959 //----------------------------------------------------------------------------
4961 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
4962 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
4963 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
4964 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
4966 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
4967 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
4968 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
4969 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
4970 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
4971 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
4972 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
4974 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
4975 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
4976 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
4978 //----------------------------------------------------------------------------
4980 //----------------------------------------------------------------------------
4981 // FIXME: Like for X86, these should go in their own separate .td file.
4983 // Any instruction that defines a 32-bit result leaves the high half of the
4984 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4985 // be copying from a truncate. But any other 32-bit operation will zero-extend
4987 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4988 def def32 : PatLeaf<(i32 GPR32:$src), [{
4989 return N->getOpcode() != ISD::TRUNCATE &&
4990 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4991 N->getOpcode() != ISD::CopyFromReg;
4994 // In the case of a 32-bit def that is known to implicitly zero-extend,
4995 // we can use a SUBREG_TO_REG.
4996 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4998 // For an anyext, we don't care what the high bits are, so we can perform an
4999 // INSERT_SUBREF into an IMPLICIT_DEF.
5000 def : Pat<(i64 (anyext GPR32:$src)),
5001 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
5003 // When we need to explicitly zero-extend, we use an unsigned bitfield move
5004 // instruction (UBFM) on the enclosing super-reg.
5005 def : Pat<(i64 (zext GPR32:$src)),
5006 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5008 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
5009 // containing super-reg.
5010 def : Pat<(i64 (sext GPR32:$src)),
5011 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5012 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
5013 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
5014 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
5015 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
5016 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
5017 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
5018 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
5020 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
5021 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5022 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
5023 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
5024 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5025 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
5027 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
5028 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5029 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
5030 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
5031 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5032 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
5034 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
5035 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5036 (i64 (i64shift_a imm0_63:$imm)),
5037 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
5039 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
5040 // AddedComplexity for the following patterns since we want to match sext + sra
5041 // patterns before we attempt to match a single sra node.
5042 let AddedComplexity = 20 in {
5043 // We support all sext + sra combinations which preserve at least one bit of the
5044 // original value which is to be sign extended. E.g. we support shifts up to
5046 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
5047 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
5048 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
5049 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
5051 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
5052 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
5053 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
5054 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
5056 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
5057 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5058 (i64 imm0_31:$imm), 31)>;
5059 } // AddedComplexity = 20
5061 // To truncate, we can simply extract from a subregister.
5062 def : Pat<(i32 (trunc GPR64sp:$src)),
5063 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5065 // __builtin_trap() uses the BRK instruction on AArch64.
5066 def : Pat<(trap), (BRK 1)>;
5068 // Conversions within AdvSIMD types in the same register size are free.
5069 // But because we need a consistent lane ordering, in big endian many
5070 // conversions require one or more REV instructions.
5072 // Consider a simple memory load followed by a bitconvert then a store.
5074 // v1 = BITCAST v2i32 v0 to v4i16
5077 // In big endian mode every memory access has an implicit byte swap. LDR and
5078 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5079 // is, they treat the vector as a sequence of elements to be byte-swapped.
5080 // The two pairs of instructions are fundamentally incompatible. We've decided
5081 // to use LD1/ST1 only to simplify compiler implementation.
5083 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5084 // the original code sequence:
5086 // v1 = REV v2i32 (implicit)
5087 // v2 = BITCAST v2i32 v1 to v4i16
5088 // v3 = REV v4i16 v2 (implicit)
5091 // But this is now broken - the value stored is different to the value loaded
5092 // due to lane reordering. To fix this, on every BITCAST we must perform two
5095 // v1 = REV v2i32 (implicit)
5097 // v3 = BITCAST v2i32 v2 to v4i16
5099 // v5 = REV v4i16 v4 (implicit)
5102 // This means an extra two instructions, but actually in most cases the two REV
5103 // instructions can be combined into one. For example:
5104 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5106 // There is also no 128-bit REV instruction. This must be synthesized with an
5109 // Most bitconverts require some sort of conversion. The only exceptions are:
5110 // a) Identity conversions - vNfX <-> vNiX
5111 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5114 // Natural vector casts (64 bit)
5115 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5116 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5117 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5118 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5119 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5121 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5122 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5123 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5124 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5126 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5127 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5128 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5129 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5131 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5132 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5133 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5134 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5135 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5136 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5138 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5139 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5140 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5141 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5142 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5144 // Natural vector casts (128 bit)
5145 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5146 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5147 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5148 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5149 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5151 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5152 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5153 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5154 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5156 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5157 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5158 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5159 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5161 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5162 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5163 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5164 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5165 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5166 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5168 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5169 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5170 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5171 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5172 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5174 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5175 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5176 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5177 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5178 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5180 let Predicates = [IsLE] in {
5181 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5182 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5183 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5184 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5185 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5187 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5188 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5189 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5190 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5191 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5192 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5193 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5194 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5195 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5196 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5197 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5198 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5200 let Predicates = [IsBE] in {
5201 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5202 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5203 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5204 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5205 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5206 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5207 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5208 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5209 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5210 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5212 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5213 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5214 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5215 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5216 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5217 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5218 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5219 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5220 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5221 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5223 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5224 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5225 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5226 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5227 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5228 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5229 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5230 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5231 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5233 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5234 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5235 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5236 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5237 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5238 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5239 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5240 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5241 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5242 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5244 let Predicates = [IsLE] in {
5245 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5246 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5247 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5248 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5249 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5251 let Predicates = [IsBE] in {
5252 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5253 (v1i64 (REV64v2i32 FPR64:$src))>;
5254 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5255 (v1i64 (REV64v4i16 FPR64:$src))>;
5256 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5257 (v1i64 (REV64v8i8 FPR64:$src))>;
5258 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5259 (v1i64 (REV64v4i16 FPR64:$src))>;
5260 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5261 (v1i64 (REV64v2i32 FPR64:$src))>;
5263 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5264 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5266 let Predicates = [IsLE] in {
5267 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5268 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5269 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5270 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5271 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5272 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5274 let Predicates = [IsBE] in {
5275 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5276 (v2i32 (REV64v2i32 FPR64:$src))>;
5277 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5278 (v2i32 (REV32v4i16 FPR64:$src))>;
5279 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5280 (v2i32 (REV32v8i8 FPR64:$src))>;
5281 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5282 (v2i32 (REV64v2i32 FPR64:$src))>;
5283 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5284 (v2i32 (REV64v2i32 FPR64:$src))>;
5285 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5286 (v2i32 (REV64v4i16 FPR64:$src))>;
5288 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5290 let Predicates = [IsLE] in {
5291 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5292 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5293 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5294 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5295 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5296 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5297 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5299 let Predicates = [IsBE] in {
5300 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5301 (v4i16 (REV64v4i16 FPR64:$src))>;
5302 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5303 (v4i16 (REV32v4i16 FPR64:$src))>;
5304 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5305 (v4i16 (REV16v8i8 FPR64:$src))>;
5306 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5307 (v4i16 (REV64v4i16 FPR64:$src))>;
5308 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5309 (v4i16 (REV32v4i16 FPR64:$src))>;
5310 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5311 (v4i16 (REV32v4i16 FPR64:$src))>;
5312 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5313 (v4i16 (REV64v4i16 FPR64:$src))>;
5316 let Predicates = [IsLE] in {
5317 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5318 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5319 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5320 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5321 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5322 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5323 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5325 let Predicates = [IsBE] in {
5326 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5327 (v4f16 (REV64v4i16 FPR64:$src))>;
5328 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5329 (v4f16 (REV64v4i16 FPR64:$src))>;
5330 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5331 (v4f16 (REV64v4i16 FPR64:$src))>;
5332 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5333 (v4f16 (REV16v8i8 FPR64:$src))>;
5334 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5335 (v4f16 (REV64v4i16 FPR64:$src))>;
5336 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5337 (v4f16 (REV64v4i16 FPR64:$src))>;
5338 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5339 (v4f16 (REV64v4i16 FPR64:$src))>;
5344 let Predicates = [IsLE] in {
5345 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5346 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5347 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5348 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5349 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5350 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5351 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5353 let Predicates = [IsBE] in {
5354 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5355 (v8i8 (REV64v8i8 FPR64:$src))>;
5356 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5357 (v8i8 (REV32v8i8 FPR64:$src))>;
5358 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5359 (v8i8 (REV16v8i8 FPR64:$src))>;
5360 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5361 (v8i8 (REV64v8i8 FPR64:$src))>;
5362 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5363 (v8i8 (REV32v8i8 FPR64:$src))>;
5364 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5365 (v8i8 (REV64v8i8 FPR64:$src))>;
5366 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5367 (v8i8 (REV16v8i8 FPR64:$src))>;
5370 let Predicates = [IsLE] in {
5371 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5372 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5373 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5374 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5375 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5377 let Predicates = [IsBE] in {
5378 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5379 (f64 (REV64v2i32 FPR64:$src))>;
5380 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5381 (f64 (REV64v4i16 FPR64:$src))>;
5382 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5383 (f64 (REV64v2i32 FPR64:$src))>;
5384 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5385 (f64 (REV64v8i8 FPR64:$src))>;
5386 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5387 (f64 (REV64v4i16 FPR64:$src))>;
5389 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5390 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5392 let Predicates = [IsLE] in {
5393 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5394 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5395 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5396 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5397 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5399 let Predicates = [IsBE] in {
5400 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5401 (v1f64 (REV64v2i32 FPR64:$src))>;
5402 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5403 (v1f64 (REV64v4i16 FPR64:$src))>;
5404 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5405 (v1f64 (REV64v8i8 FPR64:$src))>;
5406 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5407 (v1f64 (REV64v2i32 FPR64:$src))>;
5408 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5409 (v1f64 (REV64v4i16 FPR64:$src))>;
5411 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5412 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5414 let Predicates = [IsLE] in {
5415 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5416 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5417 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5418 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5419 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5420 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5422 let Predicates = [IsBE] in {
5423 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5424 (v2f32 (REV64v2i32 FPR64:$src))>;
5425 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5426 (v2f32 (REV32v4i16 FPR64:$src))>;
5427 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5428 (v2f32 (REV32v8i8 FPR64:$src))>;
5429 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5430 (v2f32 (REV64v2i32 FPR64:$src))>;
5431 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5432 (v2f32 (REV64v2i32 FPR64:$src))>;
5433 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5434 (v2f32 (REV64v4i16 FPR64:$src))>;
5436 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5438 let Predicates = [IsLE] in {
5439 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5440 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5441 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5442 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5443 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5444 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5445 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5447 let Predicates = [IsBE] in {
5448 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5449 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5450 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5451 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5452 (REV64v4i32 FPR128:$src), (i32 8)))>;
5453 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5454 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5455 (REV64v8i16 FPR128:$src), (i32 8)))>;
5456 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5457 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5458 (REV64v8i16 FPR128:$src), (i32 8)))>;
5459 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5460 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5461 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5462 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5463 (REV64v4i32 FPR128:$src), (i32 8)))>;
5464 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5465 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5466 (REV64v16i8 FPR128:$src), (i32 8)))>;
5469 let Predicates = [IsLE] in {
5470 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5471 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5472 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5473 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5474 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5475 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5477 let Predicates = [IsBE] in {
5478 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5479 (v2f64 (EXTv16i8 FPR128:$src,
5480 FPR128:$src, (i32 8)))>;
5481 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5482 (v2f64 (REV64v4i32 FPR128:$src))>;
5483 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5484 (v2f64 (REV64v8i16 FPR128:$src))>;
5485 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5486 (v2f64 (REV64v8i16 FPR128:$src))>;
5487 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5488 (v2f64 (REV64v16i8 FPR128:$src))>;
5489 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5490 (v2f64 (REV64v4i32 FPR128:$src))>;
5492 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5494 let Predicates = [IsLE] in {
5495 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5496 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5497 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5498 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5499 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5500 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5502 let Predicates = [IsBE] in {
5503 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5504 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5505 (REV64v4i32 FPR128:$src), (i32 8)))>;
5506 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5507 (v4f32 (REV32v8i16 FPR128:$src))>;
5508 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5509 (v4f32 (REV32v8i16 FPR128:$src))>;
5510 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5511 (v4f32 (REV32v16i8 FPR128:$src))>;
5512 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5513 (v4f32 (REV64v4i32 FPR128:$src))>;
5514 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5515 (v4f32 (REV64v4i32 FPR128:$src))>;
5517 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5519 let Predicates = [IsLE] in {
5520 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5521 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5522 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5523 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5524 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5525 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5527 let Predicates = [IsBE] in {
5528 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5529 (v2i64 (EXTv16i8 FPR128:$src,
5530 FPR128:$src, (i32 8)))>;
5531 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5532 (v2i64 (REV64v4i32 FPR128:$src))>;
5533 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5534 (v2i64 (REV64v8i16 FPR128:$src))>;
5535 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5536 (v2i64 (REV64v16i8 FPR128:$src))>;
5537 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5538 (v2i64 (REV64v4i32 FPR128:$src))>;
5539 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5540 (v2i64 (REV64v8i16 FPR128:$src))>;
5542 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5544 let Predicates = [IsLE] in {
5545 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5546 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5547 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5548 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5549 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5550 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5552 let Predicates = [IsBE] in {
5553 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5554 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5555 (REV64v4i32 FPR128:$src),
5557 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5558 (v4i32 (REV64v4i32 FPR128:$src))>;
5559 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5560 (v4i32 (REV32v8i16 FPR128:$src))>;
5561 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5562 (v4i32 (REV32v16i8 FPR128:$src))>;
5563 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5564 (v4i32 (REV64v4i32 FPR128:$src))>;
5565 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5566 (v4i32 (REV32v8i16 FPR128:$src))>;
5568 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5570 let Predicates = [IsLE] in {
5571 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5572 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5573 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5574 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5575 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5576 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5577 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5579 let Predicates = [IsBE] in {
5580 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5581 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5582 (REV64v8i16 FPR128:$src),
5584 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5585 (v8i16 (REV64v8i16 FPR128:$src))>;
5586 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5587 (v8i16 (REV32v8i16 FPR128:$src))>;
5588 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5589 (v8i16 (REV16v16i8 FPR128:$src))>;
5590 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5591 (v8i16 (REV64v8i16 FPR128:$src))>;
5592 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5593 (v8i16 (REV32v8i16 FPR128:$src))>;
5594 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5595 (v8i16 (REV32v8i16 FPR128:$src))>;
5598 let Predicates = [IsLE] in {
5599 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5600 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5601 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5602 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5603 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5604 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5605 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5607 let Predicates = [IsBE] in {
5608 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5609 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5610 (REV64v8i16 FPR128:$src),
5612 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5613 (v8f16 (REV64v8i16 FPR128:$src))>;
5614 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5615 (v8f16 (REV32v8i16 FPR128:$src))>;
5616 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5617 (v8f16 (REV64v8i16 FPR128:$src))>;
5618 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5619 (v8f16 (REV16v16i8 FPR128:$src))>;
5620 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5621 (v8f16 (REV64v8i16 FPR128:$src))>;
5622 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5623 (v8f16 (REV32v8i16 FPR128:$src))>;
5626 let Predicates = [IsLE] in {
5627 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5628 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5629 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5630 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5631 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5632 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5633 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5635 let Predicates = [IsBE] in {
5636 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5637 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5638 (REV64v16i8 FPR128:$src),
5640 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5641 (v16i8 (REV64v16i8 FPR128:$src))>;
5642 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5643 (v16i8 (REV32v16i8 FPR128:$src))>;
5644 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5645 (v16i8 (REV16v16i8 FPR128:$src))>;
5646 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5647 (v16i8 (REV64v16i8 FPR128:$src))>;
5648 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5649 (v16i8 (REV32v16i8 FPR128:$src))>;
5650 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5651 (v16i8 (REV16v16i8 FPR128:$src))>;
5654 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5655 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5656 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5657 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5658 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5659 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5660 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5661 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5663 // A 64-bit subvector insert to the first 128-bit vector position
5664 // is a subregister copy that needs no instruction.
5665 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5666 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5667 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5668 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5669 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5670 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5671 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5672 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5673 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5674 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5675 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5676 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5677 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5678 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5680 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5682 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5683 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5684 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5685 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5686 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5687 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5688 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5689 // so we match on v4f32 here, not v2f32. This will also catch adding
5690 // the low two lanes of a true v4f32 vector.
5691 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5692 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5693 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5695 // Scalar 64-bit shifts in FPR64 registers.
5696 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5697 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5698 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5699 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5700 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5701 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5702 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5703 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5705 // Tail call return handling. These are all compiler pseudo-instructions,
5706 // so no encoding information or anything like that.
5707 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5708 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5709 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5712 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5713 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5714 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5715 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5716 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5717 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5719 include "AArch64InstrAtomics.td"