1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
27 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
29 //===----------------------------------------------------------------------===//
30 // AArch64-specific DAG Nodes.
33 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
34 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
39 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
40 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
46 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
47 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
54 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
55 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
57 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
58 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
59 SDTCisVT<2, OtherVT>]>;
62 def SDT_AArch64CSel : SDTypeProfile<1, 4,
67 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
70 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
71 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
72 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
75 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
76 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
77 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
78 SDTCisInt<2>, SDTCisInt<3>]>;
79 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
80 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
82 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
84 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
85 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
86 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
87 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
89 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
92 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
93 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
95 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
97 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
99 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
100 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
101 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
102 SDTCisSameAs<1, 4>]>;
106 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
107 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
108 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
109 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
110 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
111 [SDNPHasChain, SDNPOutGlue]>;
112 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
113 SDCallSeqEnd<[ SDTCisVT<0, i32>,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
116 def AArch64call : SDNode<"AArch64ISD::CALL",
117 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
122 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
124 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
126 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
128 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
132 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
133 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
134 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
135 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
136 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
137 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
138 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
139 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
140 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
142 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
143 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
145 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
146 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
148 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
150 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
152 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
153 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
155 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
156 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
157 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
158 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
159 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
161 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
162 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
163 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
164 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
165 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
166 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
168 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
169 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
170 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
171 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
172 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
173 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
174 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
176 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
177 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
178 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
179 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
181 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
182 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
183 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
184 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
185 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
186 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
187 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
188 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
190 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
191 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
192 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
194 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
195 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
196 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
197 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
198 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
200 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
201 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
202 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
204 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
205 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
206 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
207 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
208 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
209 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
210 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
212 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
213 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
214 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
215 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
216 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
218 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
219 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
221 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
223 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
224 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
226 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
227 [SDNPHasChain, SDNPSideEffect]>;
229 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
230 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
232 def AArch64tlsdesc_call : SDNode<"AArch64ISD::TLSDESC_CALL",
233 SDT_AArch64TLSDescCall,
234 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
237 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
238 SDT_AArch64WrapperLarge>;
240 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
242 //===----------------------------------------------------------------------===//
244 //===----------------------------------------------------------------------===//
246 // AArch64 Instruction Predicate Definitions.
248 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
249 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
250 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
251 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
252 def ForCodeSize : Predicate<"ForCodeSize">;
253 def NotForCodeSize : Predicate<"!ForCodeSize">;
255 include "AArch64InstrFormats.td"
257 //===----------------------------------------------------------------------===//
259 //===----------------------------------------------------------------------===//
260 // Miscellaneous instructions.
261 //===----------------------------------------------------------------------===//
263 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
264 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
265 [(AArch64callseq_start timm:$amt)]>;
266 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
267 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
268 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
270 let isReMaterializable = 1, isCodeGenOnly = 1 in {
271 // FIXME: The following pseudo instructions are only needed because remat
272 // cannot handle multiple instructions. When that changes, they can be
273 // removed, along with the AArch64Wrapper node.
275 let AddedComplexity = 10 in
276 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
277 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
280 // The MOVaddr instruction should match only when the add is not folded
281 // into a load or store address.
283 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
284 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
285 tglobaladdr:$low))]>,
286 Sched<[WriteAdrAdr]>;
288 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
289 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
291 Sched<[WriteAdrAdr]>;
293 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
294 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
296 Sched<[WriteAdrAdr]>;
298 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
299 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
300 tblockaddress:$low))]>,
301 Sched<[WriteAdrAdr]>;
303 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
304 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
305 tglobaltlsaddr:$low))]>,
306 Sched<[WriteAdrAdr]>;
308 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
309 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
310 texternalsym:$low))]>,
311 Sched<[WriteAdrAdr]>;
313 } // isReMaterializable, isCodeGenOnly
315 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
316 (LOADgot tglobaltlsaddr:$addr)>;
318 def : Pat<(AArch64LOADgot texternalsym:$addr),
319 (LOADgot texternalsym:$addr)>;
321 def : Pat<(AArch64LOADgot tconstpool:$addr),
322 (LOADgot tconstpool:$addr)>;
324 //===----------------------------------------------------------------------===//
325 // System instructions.
326 //===----------------------------------------------------------------------===//
328 def HINT : HintI<"hint">;
329 def : InstAlias<"nop", (HINT 0b000)>;
330 def : InstAlias<"yield",(HINT 0b001)>;
331 def : InstAlias<"wfe", (HINT 0b010)>;
332 def : InstAlias<"wfi", (HINT 0b011)>;
333 def : InstAlias<"sev", (HINT 0b100)>;
334 def : InstAlias<"sevl", (HINT 0b101)>;
336 // As far as LLVM is concerned this writes to the system's exclusive monitors.
337 let mayLoad = 1, mayStore = 1 in
338 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
340 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
341 // model patterns with sufficiently fine granularity.
342 let mayLoad = ?, mayStore = ? in {
343 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
344 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
346 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
347 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
349 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
350 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
353 def : InstAlias<"clrex", (CLREX 0xf)>;
354 def : InstAlias<"isb", (ISB 0xf)>;
358 def MSRpstate: MSRpstateI;
360 // The thread pointer (on Linux, at least, where this has been implemented) is
362 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
364 // Generic system instructions
365 def SYSxt : SystemXtI<0, "sys">;
366 def SYSLxt : SystemLXtI<1, "sysl">;
368 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
369 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
370 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
372 //===----------------------------------------------------------------------===//
373 // Move immediate instructions.
374 //===----------------------------------------------------------------------===//
376 defm MOVK : InsertImmediate<0b11, "movk">;
377 defm MOVN : MoveImmediate<0b00, "movn">;
379 let PostEncoderMethod = "fixMOVZ" in
380 defm MOVZ : MoveImmediate<0b10, "movz">;
382 // First group of aliases covers an implicit "lsl #0".
383 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
384 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
385 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
386 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
387 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
388 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
390 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
391 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
392 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
393 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
394 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
396 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
397 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
398 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
399 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
401 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
402 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
403 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
404 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
406 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
407 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
409 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
410 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
412 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
413 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
415 // Final group of aliases covers true "mov $Rd, $imm" cases.
416 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
417 int width, int shift> {
418 def _asmoperand : AsmOperandClass {
419 let Name = basename # width # "_lsl" # shift # "MovAlias";
420 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
422 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
425 def _movimm : Operand<i32> {
426 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
429 def : InstAlias<"mov $Rd, $imm",
430 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
433 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
434 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
436 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
437 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
438 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
439 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
441 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
442 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
444 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
445 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
446 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
447 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
449 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
450 isAsCheapAsAMove = 1 in {
451 // FIXME: The following pseudo instructions are only needed because remat
452 // cannot handle multiple instructions. When that changes, we can select
453 // directly to the real instructions and get rid of these pseudos.
456 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
457 [(set GPR32:$dst, imm:$src)]>,
460 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
461 [(set GPR64:$dst, imm:$src)]>,
463 } // isReMaterializable, isCodeGenOnly
465 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
466 // eventual expansion code fewer bits to worry about getting right. Marshalling
467 // the types is a little tricky though:
468 def i64imm_32bit : ImmLeaf<i64, [{
469 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
472 def trunc_imm : SDNodeXForm<imm, [{
473 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
476 def : Pat<(i64 i64imm_32bit:$src),
477 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
479 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
481 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
482 tglobaladdr:$g1, tglobaladdr:$g0),
483 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
484 tglobaladdr:$g2, 32),
485 tglobaladdr:$g1, 16),
486 tglobaladdr:$g0, 0)>;
488 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
489 tblockaddress:$g1, tblockaddress:$g0),
490 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
491 tblockaddress:$g2, 32),
492 tblockaddress:$g1, 16),
493 tblockaddress:$g0, 0)>;
495 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
496 tconstpool:$g1, tconstpool:$g0),
497 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
502 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
503 tjumptable:$g1, tjumptable:$g0),
504 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
510 //===----------------------------------------------------------------------===//
511 // Arithmetic instructions.
512 //===----------------------------------------------------------------------===//
514 // Add/subtract with carry.
515 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
516 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
518 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
519 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
520 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
521 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
524 defm ADD : AddSub<0, "add", add>;
525 defm SUB : AddSub<1, "sub">;
527 def : InstAlias<"mov $dst, $src",
528 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
529 def : InstAlias<"mov $dst, $src",
530 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
531 def : InstAlias<"mov $dst, $src",
532 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
533 def : InstAlias<"mov $dst, $src",
534 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
536 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
537 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
539 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
540 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
541 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
542 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
543 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
544 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
545 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
546 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
547 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
548 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
549 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
550 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
551 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
552 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
553 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
554 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
555 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
557 // Because of the immediate format for add/sub-imm instructions, the
558 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
559 // These patterns capture that transformation.
560 let AddedComplexity = 1 in {
561 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
562 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
563 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
564 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
565 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
566 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
567 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
568 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
571 // Because of the immediate format for add/sub-imm instructions, the
572 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
573 // These patterns capture that transformation.
574 let AddedComplexity = 1 in {
575 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
576 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
577 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
578 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
579 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
580 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
581 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
582 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
585 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
586 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
587 def : InstAlias<"neg $dst, $src$shift",
588 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
589 def : InstAlias<"neg $dst, $src$shift",
590 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
592 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
593 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
594 def : InstAlias<"negs $dst, $src$shift",
595 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
596 def : InstAlias<"negs $dst, $src$shift",
597 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
600 // Unsigned/Signed divide
601 defm UDIV : Div<0, "udiv", udiv>;
602 defm SDIV : Div<1, "sdiv", sdiv>;
603 let isCodeGenOnly = 1 in {
604 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
605 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
609 defm ASRV : Shift<0b10, "asr", sra>;
610 defm LSLV : Shift<0b00, "lsl", shl>;
611 defm LSRV : Shift<0b01, "lsr", srl>;
612 defm RORV : Shift<0b11, "ror", rotr>;
614 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
615 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
616 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
617 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
618 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
619 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
620 def : ShiftAlias<"rorv", RORVWr, GPR32>;
621 def : ShiftAlias<"rorv", RORVXr, GPR64>;
624 let AddedComplexity = 7 in {
625 defm MADD : MulAccum<0, "madd", add>;
626 defm MSUB : MulAccum<1, "msub", sub>;
628 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
629 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
630 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
631 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
633 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
634 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
635 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
636 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
637 } // AddedComplexity = 7
639 let AddedComplexity = 5 in {
640 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
641 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
642 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
643 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
645 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
646 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
647 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
648 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
650 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
651 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
652 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
653 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
654 } // AddedComplexity = 5
656 def : MulAccumWAlias<"mul", MADDWrrr>;
657 def : MulAccumXAlias<"mul", MADDXrrr>;
658 def : MulAccumWAlias<"mneg", MSUBWrrr>;
659 def : MulAccumXAlias<"mneg", MSUBXrrr>;
660 def : WideMulAccumAlias<"smull", SMADDLrrr>;
661 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
662 def : WideMulAccumAlias<"umull", UMADDLrrr>;
663 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
666 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
667 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
670 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
671 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
672 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
673 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
675 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
676 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
677 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
678 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
681 //===----------------------------------------------------------------------===//
682 // Logical instructions.
683 //===----------------------------------------------------------------------===//
686 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
687 defm AND : LogicalImm<0b00, "and", and, "bic">;
688 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
689 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
691 // FIXME: these aliases *are* canonical sometimes (when movz can't be
692 // used). Actually, it seems to be working right now, but putting logical_immXX
693 // here is a bit dodgy on the AsmParser side too.
694 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
695 logical_imm32:$imm), 0>;
696 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
697 logical_imm64:$imm), 0>;
701 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
702 defm BICS : LogicalRegS<0b11, 1, "bics",
703 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
704 defm AND : LogicalReg<0b00, 0, "and", and>;
705 defm BIC : LogicalReg<0b00, 1, "bic",
706 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
707 defm EON : LogicalReg<0b10, 1, "eon",
708 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
709 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
710 defm ORN : LogicalReg<0b01, 1, "orn",
711 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
712 defm ORR : LogicalReg<0b01, 0, "orr", or>;
714 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
715 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
717 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
718 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
720 def : InstAlias<"mvn $Wd, $Wm$sh",
721 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
722 def : InstAlias<"mvn $Xd, $Xm$sh",
723 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
725 def : InstAlias<"tst $src1, $src2",
726 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
727 def : InstAlias<"tst $src1, $src2",
728 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
730 def : InstAlias<"tst $src1, $src2",
731 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
732 def : InstAlias<"tst $src1, $src2",
733 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
735 def : InstAlias<"tst $src1, $src2$sh",
736 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
737 def : InstAlias<"tst $src1, $src2$sh",
738 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
741 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
742 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
745 //===----------------------------------------------------------------------===//
746 // One operand data processing instructions.
747 //===----------------------------------------------------------------------===//
749 defm CLS : OneOperandData<0b101, "cls">;
750 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
751 defm RBIT : OneOperandData<0b000, "rbit">;
753 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
754 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
756 def REV16Wr : OneWRegData<0b001, "rev16",
757 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
758 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
760 def : Pat<(cttz GPR32:$Rn),
761 (CLZWr (RBITWr GPR32:$Rn))>;
762 def : Pat<(cttz GPR64:$Rn),
763 (CLZXr (RBITXr GPR64:$Rn))>;
764 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
767 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
771 // Unlike the other one operand instructions, the instructions with the "rev"
772 // mnemonic do *not* just different in the size bit, but actually use different
773 // opcode bits for the different sizes.
774 def REVWr : OneWRegData<0b010, "rev", bswap>;
775 def REVXr : OneXRegData<0b011, "rev", bswap>;
776 def REV32Xr : OneXRegData<0b010, "rev32",
777 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
779 // The bswap commutes with the rotr so we want a pattern for both possible
781 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
782 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
784 //===----------------------------------------------------------------------===//
785 // Bitfield immediate extraction instruction.
786 //===----------------------------------------------------------------------===//
787 let neverHasSideEffects = 1 in
788 defm EXTR : ExtractImm<"extr">;
789 def : InstAlias<"ror $dst, $src, $shift",
790 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
791 def : InstAlias<"ror $dst, $src, $shift",
792 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
794 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
795 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
796 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
797 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
799 //===----------------------------------------------------------------------===//
800 // Other bitfield immediate instructions.
801 //===----------------------------------------------------------------------===//
802 let neverHasSideEffects = 1 in {
803 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
804 defm SBFM : BitfieldImm<0b00, "sbfm">;
805 defm UBFM : BitfieldImm<0b10, "ubfm">;
808 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
809 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
810 return CurDAG->getTargetConstant(enc, MVT::i64);
813 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
814 uint64_t enc = 31 - N->getZExtValue();
815 return CurDAG->getTargetConstant(enc, MVT::i64);
818 // min(7, 31 - shift_amt)
819 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
820 uint64_t enc = 31 - N->getZExtValue();
821 enc = enc > 7 ? 7 : enc;
822 return CurDAG->getTargetConstant(enc, MVT::i64);
825 // min(15, 31 - shift_amt)
826 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
827 uint64_t enc = 31 - N->getZExtValue();
828 enc = enc > 15 ? 15 : enc;
829 return CurDAG->getTargetConstant(enc, MVT::i64);
832 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
833 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
834 return CurDAG->getTargetConstant(enc, MVT::i64);
837 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
838 uint64_t enc = 63 - N->getZExtValue();
839 return CurDAG->getTargetConstant(enc, MVT::i64);
842 // min(7, 63 - shift_amt)
843 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
844 uint64_t enc = 63 - N->getZExtValue();
845 enc = enc > 7 ? 7 : enc;
846 return CurDAG->getTargetConstant(enc, MVT::i64);
849 // min(15, 63 - shift_amt)
850 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
851 uint64_t enc = 63 - N->getZExtValue();
852 enc = enc > 15 ? 15 : enc;
853 return CurDAG->getTargetConstant(enc, MVT::i64);
856 // min(31, 63 - shift_amt)
857 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
858 uint64_t enc = 63 - N->getZExtValue();
859 enc = enc > 31 ? 31 : enc;
860 return CurDAG->getTargetConstant(enc, MVT::i64);
863 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
864 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
865 (i64 (i32shift_b imm0_31:$imm)))>;
866 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
867 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
868 (i64 (i64shift_b imm0_63:$imm)))>;
870 let AddedComplexity = 10 in {
871 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
872 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
873 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
874 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
877 def : InstAlias<"asr $dst, $src, $shift",
878 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
879 def : InstAlias<"asr $dst, $src, $shift",
880 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
881 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
882 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
883 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
884 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
885 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
887 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
888 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
889 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
890 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
892 def : InstAlias<"lsr $dst, $src, $shift",
893 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
894 def : InstAlias<"lsr $dst, $src, $shift",
895 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
896 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
897 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
898 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
899 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
900 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
902 //===----------------------------------------------------------------------===//
903 // Conditionally set flags instructions.
904 //===----------------------------------------------------------------------===//
905 defm CCMN : CondSetFlagsImm<0, "ccmn">;
906 defm CCMP : CondSetFlagsImm<1, "ccmp">;
908 defm CCMN : CondSetFlagsReg<0, "ccmn">;
909 defm CCMP : CondSetFlagsReg<1, "ccmp">;
911 //===----------------------------------------------------------------------===//
912 // Conditional select instructions.
913 //===----------------------------------------------------------------------===//
914 defm CSEL : CondSelect<0, 0b00, "csel">;
916 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
917 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
918 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
919 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
921 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
922 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
923 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
924 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
925 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
926 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
927 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
928 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
929 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
930 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
931 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
932 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
934 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
935 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
936 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
937 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
938 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
939 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
940 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
941 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
943 // The inverse of the condition code from the alias instruction is what is used
944 // in the aliased instruction. The parser all ready inverts the condition code
945 // for these aliases.
946 def : InstAlias<"cset $dst, $cc",
947 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
948 def : InstAlias<"cset $dst, $cc",
949 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
951 def : InstAlias<"csetm $dst, $cc",
952 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
953 def : InstAlias<"csetm $dst, $cc",
954 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
956 def : InstAlias<"cinc $dst, $src, $cc",
957 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
958 def : InstAlias<"cinc $dst, $src, $cc",
959 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
961 def : InstAlias<"cinv $dst, $src, $cc",
962 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
963 def : InstAlias<"cinv $dst, $src, $cc",
964 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
966 def : InstAlias<"cneg $dst, $src, $cc",
967 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
968 def : InstAlias<"cneg $dst, $src, $cc",
969 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
971 //===----------------------------------------------------------------------===//
972 // PC-relative instructions.
973 //===----------------------------------------------------------------------===//
974 let isReMaterializable = 1 in {
975 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
976 def ADR : ADRI<0, "adr", adrlabel, []>;
977 } // neverHasSideEffects = 1
979 def ADRP : ADRI<1, "adrp", adrplabel,
980 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
981 } // isReMaterializable = 1
983 // page address of a constant pool entry, block address
984 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
985 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
987 //===----------------------------------------------------------------------===//
988 // Unconditional branch (register) instructions.
989 //===----------------------------------------------------------------------===//
991 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
992 def RET : BranchReg<0b0010, "ret", []>;
993 def DRPS : SpecialReturn<0b0101, "drps">;
994 def ERET : SpecialReturn<0b0100, "eret">;
995 } // isReturn = 1, isTerminator = 1, isBarrier = 1
997 // Default to the LR register.
998 def : InstAlias<"ret", (RET LR)>;
1000 let isCall = 1, Defs = [LR], Uses = [SP] in {
1001 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1004 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1005 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1006 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1008 // Create a separate pseudo-instruction for codegen to use so that we don't
1009 // flag lr as used in every function. It'll be restored before the RET by the
1010 // epilogue if it's legitimately used.
1011 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1012 let isTerminator = 1;
1017 // This is a directive-like pseudo-instruction. The purpose is to insert an
1018 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1019 // (which in the usual case is a BLR).
1020 let hasSideEffects = 1 in
1021 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1022 let AsmString = ".tlsdesccall $sym";
1025 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
1026 // gets expanded to two MCInsts during lowering.
1027 let isCall = 1, Defs = [LR] in
1029 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
1030 [(AArch64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
1032 def : Pat<(AArch64tlsdesc_call GPR64:$dest, texternalsym:$sym),
1033 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
1034 //===----------------------------------------------------------------------===//
1035 // Conditional branch (immediate) instruction.
1036 //===----------------------------------------------------------------------===//
1037 def Bcc : BranchCond;
1039 //===----------------------------------------------------------------------===//
1040 // Compare-and-branch instructions.
1041 //===----------------------------------------------------------------------===//
1042 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1043 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1045 //===----------------------------------------------------------------------===//
1046 // Test-bit-and-branch instructions.
1047 //===----------------------------------------------------------------------===//
1048 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1049 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1051 //===----------------------------------------------------------------------===//
1052 // Unconditional branch (immediate) instructions.
1053 //===----------------------------------------------------------------------===//
1054 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1055 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1056 } // isBranch, isTerminator, isBarrier
1058 let isCall = 1, Defs = [LR], Uses = [SP] in {
1059 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1061 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1063 //===----------------------------------------------------------------------===//
1064 // Exception generation instructions.
1065 //===----------------------------------------------------------------------===//
1066 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1067 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1068 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1069 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1070 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1071 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1072 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1073 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1075 // DCPSn defaults to an immediate operand of zero if unspecified.
1076 def : InstAlias<"dcps1", (DCPS1 0)>;
1077 def : InstAlias<"dcps2", (DCPS2 0)>;
1078 def : InstAlias<"dcps3", (DCPS3 0)>;
1080 //===----------------------------------------------------------------------===//
1081 // Load instructions.
1082 //===----------------------------------------------------------------------===//
1084 // Pair (indexed, offset)
1085 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1086 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1087 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1088 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1089 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1091 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1093 // Pair (pre-indexed)
1094 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1095 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1096 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1097 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1098 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1100 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1102 // Pair (post-indexed)
1103 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1104 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1105 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1106 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1107 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1109 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1112 // Pair (no allocate)
1113 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1114 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1115 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1116 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1117 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1120 // (register offset)
1124 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1125 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1126 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1127 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1130 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1131 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1132 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1133 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1134 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1136 // Load sign-extended half-word
1137 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1138 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1140 // Load sign-extended byte
1141 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1142 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1144 // Load sign-extended word
1145 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1148 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1150 // For regular load, we do not have any alignment requirement.
1151 // Thus, it is safe to directly map the vector loads with interesting
1152 // addressing modes.
1153 // FIXME: We could do the same for bitconvert to floating point vectors.
1154 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1155 ValueType ScalTy, ValueType VecTy,
1156 Instruction LOADW, Instruction LOADX,
1158 def : Pat<(VecTy (scalar_to_vector (ScalTy
1159 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1160 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1161 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1164 def : Pat<(VecTy (scalar_to_vector (ScalTy
1165 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1166 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1167 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1171 let AddedComplexity = 10 in {
1172 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1173 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1175 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1176 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1178 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1179 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1181 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1182 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1184 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1185 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1187 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1189 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1192 def : Pat <(v1i64 (scalar_to_vector (i64
1193 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1194 ro_Wextend64:$extend))))),
1195 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1197 def : Pat <(v1i64 (scalar_to_vector (i64
1198 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1199 ro_Xextend64:$extend))))),
1200 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1203 // Match all load 64 bits width whose type is compatible with FPR64
1204 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1205 Instruction LOADW, Instruction LOADX> {
1207 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1208 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1210 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1211 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1214 let AddedComplexity = 10 in {
1215 let Predicates = [IsLE] in {
1216 // We must do vector loads with LD1 in big-endian.
1217 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1218 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1219 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1220 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1221 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1224 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1225 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1227 // Match all load 128 bits width whose type is compatible with FPR128
1228 let Predicates = [IsLE] in {
1229 // We must do vector loads with LD1 in big-endian.
1230 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1231 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1232 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1233 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1234 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1235 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1236 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1238 } // AddedComplexity = 10
1241 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1242 Instruction INSTW, Instruction INSTX> {
1243 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1244 (SUBREG_TO_REG (i64 0),
1245 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1248 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1249 (SUBREG_TO_REG (i64 0),
1250 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1254 let AddedComplexity = 10 in {
1255 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1256 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1257 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1259 // zextloadi1 -> zextloadi8
1260 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1262 // extload -> zextload
1263 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1264 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1265 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1267 // extloadi1 -> zextloadi8
1268 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1273 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1274 Instruction INSTW, Instruction INSTX> {
1275 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1276 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1278 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1279 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1283 let AddedComplexity = 10 in {
1284 // extload -> zextload
1285 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1286 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1287 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1289 // zextloadi1 -> zextloadi8
1290 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1294 // (unsigned immediate)
1296 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1298 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1299 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1301 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1302 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1304 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1305 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1306 [(set (f16 FPR16:$Rt),
1307 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1308 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1309 [(set (f32 FPR32:$Rt),
1310 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1311 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1312 [(set (f64 FPR64:$Rt),
1313 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1314 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1315 [(set (f128 FPR128:$Rt),
1316 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1318 // For regular load, we do not have any alignment requirement.
1319 // Thus, it is safe to directly map the vector loads with interesting
1320 // addressing modes.
1321 // FIXME: We could do the same for bitconvert to floating point vectors.
1322 def : Pat <(v8i8 (scalar_to_vector (i32
1323 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1324 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1325 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1326 def : Pat <(v16i8 (scalar_to_vector (i32
1327 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1328 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1329 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1330 def : Pat <(v4i16 (scalar_to_vector (i32
1331 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1332 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1333 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1334 def : Pat <(v8i16 (scalar_to_vector (i32
1335 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1336 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1337 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1338 def : Pat <(v2i32 (scalar_to_vector (i32
1339 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1340 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1341 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1342 def : Pat <(v4i32 (scalar_to_vector (i32
1343 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1344 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1345 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1346 def : Pat <(v1i64 (scalar_to_vector (i64
1347 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1348 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1349 def : Pat <(v2i64 (scalar_to_vector (i64
1350 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1351 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1352 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1354 // Match all load 64 bits width whose type is compatible with FPR64
1355 let Predicates = [IsLE] in {
1356 // We must use LD1 to perform vector loads in big-endian.
1357 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1358 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1359 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1360 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1361 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1362 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1363 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1364 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1365 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1366 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1368 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1369 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1370 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1371 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1373 // Match all load 128 bits width whose type is compatible with FPR128
1374 let Predicates = [IsLE] in {
1375 // We must use LD1 to perform vector loads in big-endian.
1376 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1377 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1378 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1379 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1380 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1381 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1382 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1383 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1384 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1385 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1386 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1387 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1388 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1389 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1391 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1392 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1394 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1396 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1397 uimm12s2:$offset)))]>;
1398 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1400 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1401 uimm12s1:$offset)))]>;
1403 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1404 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1405 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1406 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1408 // zextloadi1 -> zextloadi8
1409 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1410 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1411 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1412 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1414 // extload -> zextload
1415 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1416 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1417 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1418 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1419 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1420 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1421 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1422 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1423 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1424 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1425 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1426 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1427 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1428 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1430 // load sign-extended half-word
1431 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1433 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1434 uimm12s2:$offset)))]>;
1435 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1437 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1438 uimm12s2:$offset)))]>;
1440 // load sign-extended byte
1441 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1443 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1444 uimm12s1:$offset)))]>;
1445 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1447 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1448 uimm12s1:$offset)))]>;
1450 // load sign-extended word
1451 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1453 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1454 uimm12s4:$offset)))]>;
1456 // load zero-extended word
1457 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1458 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1461 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1462 [(AArch64Prefetch imm:$Rt,
1463 (am_indexed64 GPR64sp:$Rn,
1464 uimm12s8:$offset))]>;
1466 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1470 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1471 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1472 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1473 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1474 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1476 // load sign-extended word
1477 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1480 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1481 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1484 // (unscaled immediate)
1485 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1487 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1488 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1490 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1491 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1493 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1494 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1496 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1497 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1498 [(set (f32 FPR32:$Rt),
1499 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1500 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1501 [(set (f64 FPR64:$Rt),
1502 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1503 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1504 [(set (f128 FPR128:$Rt),
1505 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1508 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1510 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1512 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1514 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1516 // Match all load 64 bits width whose type is compatible with FPR64
1517 let Predicates = [IsLE] in {
1518 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1519 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1520 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1521 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1522 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1523 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1524 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1525 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1526 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1527 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1529 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1530 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1531 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1532 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1534 // Match all load 128 bits width whose type is compatible with FPR128
1535 let Predicates = [IsLE] in {
1536 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1537 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1538 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1539 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1540 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1541 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1542 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1543 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1544 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1545 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1546 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1547 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1548 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1549 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1553 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1554 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1555 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1556 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1557 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1558 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1559 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1560 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1561 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1562 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1563 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1564 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1565 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1566 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1568 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1569 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1570 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1571 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1572 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1573 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1574 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1575 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1576 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1577 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1578 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1579 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1580 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1581 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1585 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1587 // Define new assembler match classes as we want to only match these when
1588 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1589 // associate a DiagnosticType either, as we want the diagnostic for the
1590 // canonical form (the scaled operand) to take precedence.
1591 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1592 let Name = "SImm9OffsetFB" # Width;
1593 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1594 let RenderMethod = "addImmOperands";
1597 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1598 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1599 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1600 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1601 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1603 def simm9_offset_fb8 : Operand<i64> {
1604 let ParserMatchClass = SImm9OffsetFB8Operand;
1606 def simm9_offset_fb16 : Operand<i64> {
1607 let ParserMatchClass = SImm9OffsetFB16Operand;
1609 def simm9_offset_fb32 : Operand<i64> {
1610 let ParserMatchClass = SImm9OffsetFB32Operand;
1612 def simm9_offset_fb64 : Operand<i64> {
1613 let ParserMatchClass = SImm9OffsetFB64Operand;
1615 def simm9_offset_fb128 : Operand<i64> {
1616 let ParserMatchClass = SImm9OffsetFB128Operand;
1619 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1620 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1621 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1622 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1623 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1624 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1625 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1626 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1627 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1628 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1629 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1630 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1631 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1632 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1635 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1636 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1637 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1638 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1640 // load sign-extended half-word
1642 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1644 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1646 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1648 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1650 // load sign-extended byte
1652 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1654 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1656 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1658 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1660 // load sign-extended word
1662 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1664 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1666 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1667 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1668 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1669 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1670 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1671 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1672 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1673 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1674 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1675 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1676 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1677 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1678 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1679 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1680 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1683 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1684 [(AArch64Prefetch imm:$Rt,
1685 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1688 // (unscaled immediate, unprivileged)
1689 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1690 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1692 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1693 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1695 // load sign-extended half-word
1696 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1697 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1699 // load sign-extended byte
1700 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1701 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1703 // load sign-extended word
1704 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1707 // (immediate pre-indexed)
1708 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1709 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1710 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1711 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1712 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1713 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1714 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1716 // load sign-extended half-word
1717 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1718 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1720 // load sign-extended byte
1721 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1722 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1724 // load zero-extended byte
1725 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1726 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1728 // load sign-extended word
1729 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1732 // (immediate post-indexed)
1733 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1734 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1735 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1736 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1737 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1738 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1739 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1741 // load sign-extended half-word
1742 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1743 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1745 // load sign-extended byte
1746 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1747 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1749 // load zero-extended byte
1750 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1751 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1753 // load sign-extended word
1754 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1756 //===----------------------------------------------------------------------===//
1757 // Store instructions.
1758 //===----------------------------------------------------------------------===//
1760 // Pair (indexed, offset)
1761 // FIXME: Use dedicated range-checked addressing mode operand here.
1762 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1763 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1764 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1765 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1766 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1768 // Pair (pre-indexed)
1769 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1770 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1771 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1772 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1773 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1775 // Pair (pre-indexed)
1776 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1777 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1778 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1779 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1780 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1782 // Pair (no allocate)
1783 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1784 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1785 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1786 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1787 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1790 // (Register offset)
1793 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1794 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1795 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1796 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1800 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1801 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1802 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1803 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1804 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1806 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1807 Instruction STRW, Instruction STRX> {
1809 def : Pat<(storeop GPR64:$Rt,
1810 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1811 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1812 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1814 def : Pat<(storeop GPR64:$Rt,
1815 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1816 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1817 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1820 let AddedComplexity = 10 in {
1822 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1823 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1824 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1827 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1828 Instruction STRW, Instruction STRX> {
1829 def : Pat<(store (VecTy FPR:$Rt),
1830 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1831 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1833 def : Pat<(store (VecTy FPR:$Rt),
1834 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1835 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1838 let AddedComplexity = 10 in {
1839 // Match all store 64 bits width whose type is compatible with FPR64
1840 let Predicates = [IsLE] in {
1841 // We must use ST1 to store vectors in big-endian.
1842 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1843 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1844 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1845 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1846 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1849 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1850 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1852 // Match all store 128 bits width whose type is compatible with FPR128
1853 let Predicates = [IsLE] in {
1854 // We must use ST1 to store vectors in big-endian.
1855 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1856 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1857 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1858 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1859 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1860 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1861 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
1863 } // AddedComplexity = 10
1866 // (unsigned immediate)
1867 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1869 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1870 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1872 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1873 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1875 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
1876 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1877 [(store (f16 FPR16:$Rt),
1878 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
1879 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1880 [(store (f32 FPR32:$Rt),
1881 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1882 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1883 [(store (f64 FPR64:$Rt),
1884 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1885 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1887 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1888 [(truncstorei16 GPR32:$Rt,
1889 (am_indexed16 GPR64sp:$Rn,
1890 uimm12s2:$offset))]>;
1891 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
1892 [(truncstorei8 GPR32:$Rt,
1893 (am_indexed8 GPR64sp:$Rn,
1894 uimm12s1:$offset))]>;
1896 // Match all store 64 bits width whose type is compatible with FPR64
1897 let AddedComplexity = 10 in {
1898 let Predicates = [IsLE] in {
1899 // We must use ST1 to store vectors in big-endian.
1900 def : Pat<(store (v2f32 FPR64:$Rt),
1901 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1902 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1903 def : Pat<(store (v8i8 FPR64:$Rt),
1904 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1905 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1906 def : Pat<(store (v4i16 FPR64:$Rt),
1907 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1908 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1909 def : Pat<(store (v2i32 FPR64:$Rt),
1910 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1911 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1912 def : Pat<(store (v4f16 FPR64:$Rt),
1913 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1914 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1916 def : Pat<(store (v1f64 FPR64:$Rt),
1917 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1918 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1919 def : Pat<(store (v1i64 FPR64:$Rt),
1920 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1921 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1923 // Match all store 128 bits width whose type is compatible with FPR128
1924 let Predicates = [IsLE] in {
1925 // We must use ST1 to store vectors in big-endian.
1926 def : Pat<(store (v4f32 FPR128:$Rt),
1927 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1928 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1929 def : Pat<(store (v2f64 FPR128:$Rt),
1930 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1931 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1932 def : Pat<(store (v16i8 FPR128:$Rt),
1933 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1934 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1935 def : Pat<(store (v8i16 FPR128:$Rt),
1936 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1937 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1938 def : Pat<(store (v4i32 FPR128:$Rt),
1939 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1940 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1941 def : Pat<(store (v2i64 FPR128:$Rt),
1942 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1943 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1944 def : Pat<(store (v8f16 FPR128:$Rt),
1945 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1946 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1948 def : Pat<(store (f128 FPR128:$Rt),
1949 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1950 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1953 def : Pat<(truncstorei32 GPR64:$Rt,
1954 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
1955 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
1956 def : Pat<(truncstorei16 GPR64:$Rt,
1957 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
1958 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
1959 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
1960 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
1962 } // AddedComplexity = 10
1965 // (unscaled immediate)
1966 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
1968 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1969 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
1971 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1972 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
1974 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1975 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
1976 [(store (f16 FPR16:$Rt),
1977 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1978 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
1979 [(store (f32 FPR32:$Rt),
1980 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1981 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
1982 [(store (f64 FPR64:$Rt),
1983 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1984 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
1985 [(store (f128 FPR128:$Rt),
1986 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
1987 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
1988 [(truncstorei16 GPR32:$Rt,
1989 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1990 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
1991 [(truncstorei8 GPR32:$Rt,
1992 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1994 // Match all store 64 bits width whose type is compatible with FPR64
1995 let Predicates = [IsLE] in {
1996 // We must use ST1 to store vectors in big-endian.
1997 def : Pat<(store (v2f32 FPR64:$Rt),
1998 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1999 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2000 def : Pat<(store (v8i8 FPR64:$Rt),
2001 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2002 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2003 def : Pat<(store (v4i16 FPR64:$Rt),
2004 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2005 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2006 def : Pat<(store (v2i32 FPR64:$Rt),
2007 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2008 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2009 def : Pat<(store (v4f16 FPR64:$Rt),
2010 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2011 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2013 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2014 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2015 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2016 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2018 // Match all store 128 bits width whose type is compatible with FPR128
2019 let Predicates = [IsLE] in {
2020 // We must use ST1 to store vectors in big-endian.
2021 def : Pat<(store (v4f32 FPR128:$Rt),
2022 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2023 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2024 def : Pat<(store (v2f64 FPR128:$Rt),
2025 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2026 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2027 def : Pat<(store (v16i8 FPR128:$Rt),
2028 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2029 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2030 def : Pat<(store (v8i16 FPR128:$Rt),
2031 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2032 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2033 def : Pat<(store (v4i32 FPR128:$Rt),
2034 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2035 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2036 def : Pat<(store (v2i64 FPR128:$Rt),
2037 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2038 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2039 def : Pat<(store (v2f64 FPR128:$Rt),
2040 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2041 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2042 def : Pat<(store (v8f16 FPR128:$Rt),
2043 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2044 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2047 // unscaled i64 truncating stores
2048 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2049 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2050 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2051 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2052 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2053 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2056 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2057 def : InstAlias<"str $Rt, [$Rn, $offset]",
2058 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2059 def : InstAlias<"str $Rt, [$Rn, $offset]",
2060 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2061 def : InstAlias<"str $Rt, [$Rn, $offset]",
2062 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2063 def : InstAlias<"str $Rt, [$Rn, $offset]",
2064 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2065 def : InstAlias<"str $Rt, [$Rn, $offset]",
2066 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2067 def : InstAlias<"str $Rt, [$Rn, $offset]",
2068 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2069 def : InstAlias<"str $Rt, [$Rn, $offset]",
2070 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2072 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2073 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2074 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2075 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2078 // (unscaled immediate, unprivileged)
2079 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2080 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2082 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2083 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2086 // (immediate pre-indexed)
2087 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2088 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2089 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2090 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2091 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2092 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2093 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2095 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2096 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2099 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2100 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2102 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2103 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2105 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2106 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2109 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2110 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2111 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2112 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2113 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2114 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2115 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2116 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2117 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2118 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2119 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2120 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2121 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2122 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2124 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2125 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2126 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2127 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2128 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2129 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2130 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2131 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2132 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2133 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2134 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2135 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2136 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2137 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2140 // (immediate post-indexed)
2141 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2142 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2143 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2144 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2145 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2146 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2147 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2149 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2150 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2153 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2154 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2156 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2157 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2159 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2160 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2163 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2164 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2165 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2166 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2167 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2168 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2169 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2170 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2171 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2172 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2173 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2174 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2175 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2176 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2178 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2179 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2180 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2181 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2182 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2183 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2184 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2185 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2186 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2187 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2188 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2189 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2190 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2191 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2193 //===----------------------------------------------------------------------===//
2194 // Load/store exclusive instructions.
2195 //===----------------------------------------------------------------------===//
2197 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2198 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2199 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2200 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2202 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2203 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2204 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2205 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2207 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2208 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2209 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2210 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2212 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2213 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2214 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2215 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2217 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2218 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2219 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2220 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2222 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2223 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2224 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2225 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2227 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2228 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2230 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2231 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2233 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2234 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2236 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2237 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2239 //===----------------------------------------------------------------------===//
2240 // Scaled floating point to integer conversion instructions.
2241 //===----------------------------------------------------------------------===//
2243 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2244 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2245 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2246 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2247 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2248 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2249 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2250 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2251 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2252 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2253 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2254 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2255 let isCodeGenOnly = 1 in {
2256 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2257 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2258 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2259 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2262 //===----------------------------------------------------------------------===//
2263 // Scaled integer to floating point conversion instructions.
2264 //===----------------------------------------------------------------------===//
2266 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2267 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2269 //===----------------------------------------------------------------------===//
2270 // Unscaled integer to floating point conversion instruction.
2271 //===----------------------------------------------------------------------===//
2273 defm FMOV : UnscaledConversion<"fmov">;
2275 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
2276 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
2278 //===----------------------------------------------------------------------===//
2279 // Floating point conversion instruction.
2280 //===----------------------------------------------------------------------===//
2282 defm FCVT : FPConversion<"fcvt">;
2284 //===----------------------------------------------------------------------===//
2285 // Floating point single operand instructions.
2286 //===----------------------------------------------------------------------===//
2288 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2289 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2290 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2291 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2292 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2293 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2294 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2295 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2297 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2298 (FRINTNDr FPR64:$Rn)>;
2300 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2301 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2302 // <rdar://problem/13715968>
2303 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2304 let hasSideEffects = 1 in {
2305 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2308 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2310 let SchedRW = [WriteFDiv] in {
2311 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2314 //===----------------------------------------------------------------------===//
2315 // Floating point two operand instructions.
2316 //===----------------------------------------------------------------------===//
2318 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2319 let SchedRW = [WriteFDiv] in {
2320 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2322 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2323 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2324 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2325 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2326 let SchedRW = [WriteFMul] in {
2327 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2328 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2330 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2332 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2333 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2334 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2335 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2336 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2337 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2338 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2339 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2341 //===----------------------------------------------------------------------===//
2342 // Floating point three operand instructions.
2343 //===----------------------------------------------------------------------===//
2345 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2346 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2347 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2348 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2349 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2350 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2351 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2353 // The following def pats catch the case where the LHS of an FMA is negated.
2354 // The TriOpFrag above catches the case where the middle operand is negated.
2356 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2357 // the NEON variant.
2358 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2359 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2361 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2362 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2364 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2366 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2367 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2369 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2370 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2372 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2373 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2375 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2376 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2378 //===----------------------------------------------------------------------===//
2379 // Floating point comparison instructions.
2380 //===----------------------------------------------------------------------===//
2382 defm FCMPE : FPComparison<1, "fcmpe">;
2383 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2385 //===----------------------------------------------------------------------===//
2386 // Floating point conditional comparison instructions.
2387 //===----------------------------------------------------------------------===//
2389 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2390 defm FCCMP : FPCondComparison<0, "fccmp">;
2392 //===----------------------------------------------------------------------===//
2393 // Floating point conditional select instruction.
2394 //===----------------------------------------------------------------------===//
2396 defm FCSEL : FPCondSelect<"fcsel">;
2398 // CSEL instructions providing f128 types need to be handled by a
2399 // pseudo-instruction since the eventual code will need to introduce basic
2400 // blocks and control flow.
2401 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2402 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2403 [(set (f128 FPR128:$Rd),
2404 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2405 (i32 imm:$cond), NZCV))]> {
2407 let usesCustomInserter = 1;
2411 //===----------------------------------------------------------------------===//
2412 // Floating point immediate move.
2413 //===----------------------------------------------------------------------===//
2415 let isReMaterializable = 1 in {
2416 defm FMOV : FPMoveImmediate<"fmov">;
2419 //===----------------------------------------------------------------------===//
2420 // Advanced SIMD two vector instructions.
2421 //===----------------------------------------------------------------------===//
2423 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2424 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2425 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2426 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2427 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2428 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2429 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2430 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2431 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2432 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2434 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2435 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2436 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2437 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2438 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2439 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2440 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2441 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2442 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2443 (FCVTLv4i16 V64:$Rn)>;
2444 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2446 (FCVTLv8i16 V128:$Rn)>;
2447 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2448 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2450 (FCVTLv4i32 V128:$Rn)>;
2452 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2453 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2455 (FCVTLv8i16 V128:$Rn)>;
2457 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2458 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2459 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2460 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2461 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2462 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2463 (FCVTNv4i16 V128:$Rn)>;
2464 def : Pat<(concat_vectors V64:$Rd,
2465 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2466 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2467 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2468 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2469 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2470 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2471 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2472 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2473 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2474 int_aarch64_neon_fcvtxn>;
2475 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2476 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2477 let isCodeGenOnly = 1 in {
2478 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2479 int_aarch64_neon_fcvtzs>;
2480 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2481 int_aarch64_neon_fcvtzu>;
2483 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2484 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2485 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2486 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2487 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2488 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2489 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2490 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2491 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2492 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2493 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2494 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2495 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2496 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2497 // Aliases for MVN -> NOT.
2498 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2499 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2500 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2501 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2503 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2504 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2505 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2506 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2507 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2508 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2509 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2511 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2512 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2513 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2514 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2515 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2516 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2517 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2518 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2520 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2521 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2522 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2523 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2524 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2526 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2527 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2528 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2529 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2530 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2531 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2532 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2533 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2534 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2535 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2536 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2537 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2538 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2539 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2540 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2541 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2542 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2543 int_aarch64_neon_uaddlp>;
2544 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2545 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2546 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2547 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2548 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2549 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2551 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2552 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2553 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2554 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2555 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2556 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2558 // Patterns for vector long shift (by element width). These need to match all
2559 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2561 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2562 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2563 (SHLLv8i8 V64:$Rn)>;
2564 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2565 (SHLLv16i8 V128:$Rn)>;
2566 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2567 (SHLLv4i16 V64:$Rn)>;
2568 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2569 (SHLLv8i16 V128:$Rn)>;
2570 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2571 (SHLLv2i32 V64:$Rn)>;
2572 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2573 (SHLLv4i32 V128:$Rn)>;
2576 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2577 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2578 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2580 //===----------------------------------------------------------------------===//
2581 // Advanced SIMD three vector instructions.
2582 //===----------------------------------------------------------------------===//
2584 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2585 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2586 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2587 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2588 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2589 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2590 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2591 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2592 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2593 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2594 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2595 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2596 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2597 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2598 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2599 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2600 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2601 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2602 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2603 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2604 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2605 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2606 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2607 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2608 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2610 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2611 // instruction expects the addend first, while the fma intrinsic puts it last.
2612 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2613 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2614 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2615 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2617 // The following def pats catch the case where the LHS of an FMA is negated.
2618 // The TriOpFrag above catches the case where the middle operand is negated.
2619 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2620 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2622 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2623 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2625 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2626 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2628 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2629 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2630 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2631 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2632 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2633 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2634 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2635 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2636 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2637 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2638 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2639 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2640 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2641 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2642 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2643 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2644 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2645 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2646 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2647 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2648 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2649 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2650 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2651 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2652 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2653 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2654 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2655 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2656 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2657 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2658 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2659 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2660 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2661 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2662 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2663 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2664 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2665 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2666 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2667 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2668 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2669 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2670 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2671 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2672 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2673 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2675 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2676 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2677 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2678 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2679 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2680 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2681 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2682 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2683 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2684 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2685 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2687 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2688 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2689 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2690 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2691 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2692 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2693 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2694 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2696 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2697 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2698 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2699 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2700 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2701 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2702 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2703 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2705 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2706 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2707 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2708 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2709 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2710 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2711 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2712 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2714 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2715 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2716 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2717 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2718 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2719 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2720 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2721 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2723 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2724 "|cmls.8b\t$dst, $src1, $src2}",
2725 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2726 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2727 "|cmls.16b\t$dst, $src1, $src2}",
2728 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2729 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2730 "|cmls.4h\t$dst, $src1, $src2}",
2731 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2732 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2733 "|cmls.8h\t$dst, $src1, $src2}",
2734 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2735 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2736 "|cmls.2s\t$dst, $src1, $src2}",
2737 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2738 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2739 "|cmls.4s\t$dst, $src1, $src2}",
2740 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2741 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2742 "|cmls.2d\t$dst, $src1, $src2}",
2743 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2745 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2746 "|cmlo.8b\t$dst, $src1, $src2}",
2747 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2748 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2749 "|cmlo.16b\t$dst, $src1, $src2}",
2750 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2751 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2752 "|cmlo.4h\t$dst, $src1, $src2}",
2753 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2754 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2755 "|cmlo.8h\t$dst, $src1, $src2}",
2756 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2757 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2758 "|cmlo.2s\t$dst, $src1, $src2}",
2759 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2760 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2761 "|cmlo.4s\t$dst, $src1, $src2}",
2762 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2763 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2764 "|cmlo.2d\t$dst, $src1, $src2}",
2765 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2767 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2768 "|cmle.8b\t$dst, $src1, $src2}",
2769 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2770 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2771 "|cmle.16b\t$dst, $src1, $src2}",
2772 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2773 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2774 "|cmle.4h\t$dst, $src1, $src2}",
2775 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2776 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2777 "|cmle.8h\t$dst, $src1, $src2}",
2778 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2779 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2780 "|cmle.2s\t$dst, $src1, $src2}",
2781 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2782 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2783 "|cmle.4s\t$dst, $src1, $src2}",
2784 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2785 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2786 "|cmle.2d\t$dst, $src1, $src2}",
2787 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2789 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2790 "|cmlt.8b\t$dst, $src1, $src2}",
2791 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2792 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2793 "|cmlt.16b\t$dst, $src1, $src2}",
2794 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2795 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2796 "|cmlt.4h\t$dst, $src1, $src2}",
2797 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2798 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2799 "|cmlt.8h\t$dst, $src1, $src2}",
2800 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2801 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2802 "|cmlt.2s\t$dst, $src1, $src2}",
2803 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2804 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2805 "|cmlt.4s\t$dst, $src1, $src2}",
2806 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2807 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2808 "|cmlt.2d\t$dst, $src1, $src2}",
2809 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2811 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2812 "|fcmle.2s\t$dst, $src1, $src2}",
2813 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2814 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2815 "|fcmle.4s\t$dst, $src1, $src2}",
2816 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2817 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2818 "|fcmle.2d\t$dst, $src1, $src2}",
2819 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2821 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2822 "|fcmlt.2s\t$dst, $src1, $src2}",
2823 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2824 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2825 "|fcmlt.4s\t$dst, $src1, $src2}",
2826 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2827 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2828 "|fcmlt.2d\t$dst, $src1, $src2}",
2829 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2831 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2832 "|facle.2s\t$dst, $src1, $src2}",
2833 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2834 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2835 "|facle.4s\t$dst, $src1, $src2}",
2836 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2837 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2838 "|facle.2d\t$dst, $src1, $src2}",
2839 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2841 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2842 "|faclt.2s\t$dst, $src1, $src2}",
2843 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2844 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2845 "|faclt.4s\t$dst, $src1, $src2}",
2846 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2847 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2848 "|faclt.2d\t$dst, $src1, $src2}",
2849 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2851 //===----------------------------------------------------------------------===//
2852 // Advanced SIMD three scalar instructions.
2853 //===----------------------------------------------------------------------===//
2855 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2856 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
2857 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
2858 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
2859 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
2860 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
2861 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
2862 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
2863 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2864 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2865 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2866 int_aarch64_neon_facge>;
2867 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2868 int_aarch64_neon_facgt>;
2869 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2870 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2871 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2872 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
2873 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
2874 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
2875 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
2876 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
2877 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
2878 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
2879 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
2880 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
2881 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
2882 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
2883 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2884 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
2885 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
2886 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
2887 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
2888 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
2889 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
2891 def : InstAlias<"cmls $dst, $src1, $src2",
2892 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2893 def : InstAlias<"cmle $dst, $src1, $src2",
2894 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2895 def : InstAlias<"cmlo $dst, $src1, $src2",
2896 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2897 def : InstAlias<"cmlt $dst, $src1, $src2",
2898 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2899 def : InstAlias<"fcmle $dst, $src1, $src2",
2900 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2901 def : InstAlias<"fcmle $dst, $src1, $src2",
2902 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2903 def : InstAlias<"fcmlt $dst, $src1, $src2",
2904 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2905 def : InstAlias<"fcmlt $dst, $src1, $src2",
2906 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2907 def : InstAlias<"facle $dst, $src1, $src2",
2908 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2909 def : InstAlias<"facle $dst, $src1, $src2",
2910 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2911 def : InstAlias<"faclt $dst, $src1, $src2",
2912 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2913 def : InstAlias<"faclt $dst, $src1, $src2",
2914 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2916 //===----------------------------------------------------------------------===//
2917 // Advanced SIMD three scalar instructions (mixed operands).
2918 //===----------------------------------------------------------------------===//
2919 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2920 int_aarch64_neon_sqdmulls_scalar>;
2921 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2922 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2924 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
2925 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2926 (i32 FPR32:$Rm))))),
2927 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2928 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
2929 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2930 (i32 FPR32:$Rm))))),
2931 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2933 //===----------------------------------------------------------------------===//
2934 // Advanced SIMD two scalar instructions.
2935 //===----------------------------------------------------------------------===//
2937 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
2938 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
2939 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
2940 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
2941 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
2942 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
2943 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2944 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2945 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2946 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2947 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2948 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2949 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2950 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2951 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2952 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2953 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2954 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2955 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2956 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2957 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2958 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2959 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2960 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2961 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2962 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2963 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2964 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
2965 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2966 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2967 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
2968 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
2969 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2970 int_aarch64_neon_suqadd>;
2971 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
2972 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
2973 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2974 int_aarch64_neon_usqadd>;
2976 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
2978 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
2979 (FCVTASv1i64 FPR64:$Rn)>;
2980 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
2981 (FCVTAUv1i64 FPR64:$Rn)>;
2982 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
2983 (FCVTMSv1i64 FPR64:$Rn)>;
2984 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2985 (FCVTMUv1i64 FPR64:$Rn)>;
2986 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
2987 (FCVTNSv1i64 FPR64:$Rn)>;
2988 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2989 (FCVTNUv1i64 FPR64:$Rn)>;
2990 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
2991 (FCVTPSv1i64 FPR64:$Rn)>;
2992 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2993 (FCVTPUv1i64 FPR64:$Rn)>;
2995 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
2996 (FRECPEv1i32 FPR32:$Rn)>;
2997 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
2998 (FRECPEv1i64 FPR64:$Rn)>;
2999 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3000 (FRECPEv1i64 FPR64:$Rn)>;
3002 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3003 (FRECPXv1i32 FPR32:$Rn)>;
3004 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3005 (FRECPXv1i64 FPR64:$Rn)>;
3007 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3008 (FRSQRTEv1i32 FPR32:$Rn)>;
3009 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3010 (FRSQRTEv1i64 FPR64:$Rn)>;
3011 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3012 (FRSQRTEv1i64 FPR64:$Rn)>;
3014 // If an integer is about to be converted to a floating point value,
3015 // just load it on the floating point unit.
3016 // Here are the patterns for 8 and 16-bits to float.
3018 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3019 SDPatternOperator loadop, Instruction UCVTF,
3020 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3022 def : Pat<(DstTy (uint_to_fp (SrcTy
3023 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3024 ro.Wext:$extend))))),
3025 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3026 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3029 def : Pat<(DstTy (uint_to_fp (SrcTy
3030 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3031 ro.Wext:$extend))))),
3032 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3033 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3037 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3038 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3039 def : Pat <(f32 (uint_to_fp (i32
3040 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3041 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3042 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3043 def : Pat <(f32 (uint_to_fp (i32
3044 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3045 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3046 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3047 // 16-bits -> float.
3048 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3049 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3050 def : Pat <(f32 (uint_to_fp (i32
3051 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3052 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3053 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3054 def : Pat <(f32 (uint_to_fp (i32
3055 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3056 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3057 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3058 // 32-bits are handled in target specific dag combine:
3059 // performIntToFpCombine.
3060 // 64-bits integer to 32-bits floating point, not possible with
3061 // UCVTF on floating point registers (both source and destination
3062 // must have the same size).
3064 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3065 // 8-bits -> double.
3066 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3067 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3068 def : Pat <(f64 (uint_to_fp (i32
3069 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3070 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3071 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3072 def : Pat <(f64 (uint_to_fp (i32
3073 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3074 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3075 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3076 // 16-bits -> double.
3077 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3078 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3079 def : Pat <(f64 (uint_to_fp (i32
3080 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3081 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3082 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3083 def : Pat <(f64 (uint_to_fp (i32
3084 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3085 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3086 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3087 // 32-bits -> double.
3088 defm : UIntToFPROLoadPat<f64, i32, load,
3089 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3090 def : Pat <(f64 (uint_to_fp (i32
3091 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3092 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3093 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3094 def : Pat <(f64 (uint_to_fp (i32
3095 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3096 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3097 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3098 // 64-bits -> double are handled in target specific dag combine:
3099 // performIntToFpCombine.
3101 //===----------------------------------------------------------------------===//
3102 // Advanced SIMD three different-sized vector instructions.
3103 //===----------------------------------------------------------------------===//
3105 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3106 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3107 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3108 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3109 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3110 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3111 int_aarch64_neon_sabd>;
3112 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3113 int_aarch64_neon_sabd>;
3114 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3115 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3116 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3117 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3118 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3119 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3120 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3121 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3122 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3123 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3124 int_aarch64_neon_sqadd>;
3125 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3126 int_aarch64_neon_sqsub>;
3127 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3128 int_aarch64_neon_sqdmull>;
3129 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3130 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3131 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3132 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3133 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3134 int_aarch64_neon_uabd>;
3135 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3136 int_aarch64_neon_uabd>;
3137 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3138 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3139 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3140 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3141 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3142 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3143 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3144 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3145 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3146 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3147 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3148 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3149 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3151 // Patterns for 64-bit pmull
3152 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3153 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3154 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3155 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3156 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3158 // CodeGen patterns for addhn and subhn instructions, which can actually be
3159 // written in LLVM IR without too much difficulty.
3162 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3163 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3164 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3166 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3167 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3169 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3170 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3171 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3173 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3174 V128:$Rn, V128:$Rm)>;
3175 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3176 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3178 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3179 V128:$Rn, V128:$Rm)>;
3180 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3181 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3183 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3184 V128:$Rn, V128:$Rm)>;
3187 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3188 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3189 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3191 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3192 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3194 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3195 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3196 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3198 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3199 V128:$Rn, V128:$Rm)>;
3200 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3201 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3203 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3204 V128:$Rn, V128:$Rm)>;
3205 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3206 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3208 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3209 V128:$Rn, V128:$Rm)>;
3211 //----------------------------------------------------------------------------
3212 // AdvSIMD bitwise extract from vector instruction.
3213 //----------------------------------------------------------------------------
3215 defm EXT : SIMDBitwiseExtract<"ext">;
3217 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3218 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3219 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3220 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3221 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3222 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3223 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3224 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3225 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3226 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3227 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3228 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3229 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3230 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3231 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3232 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3233 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3234 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3235 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3236 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3238 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3240 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3241 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3242 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3243 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3244 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3245 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3246 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3247 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3248 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3249 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3250 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3251 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3252 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3253 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3256 //----------------------------------------------------------------------------
3257 // AdvSIMD zip vector
3258 //----------------------------------------------------------------------------
3260 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3261 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3262 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3263 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3264 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3265 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3267 //----------------------------------------------------------------------------
3268 // AdvSIMD TBL/TBX instructions
3269 //----------------------------------------------------------------------------
3271 defm TBL : SIMDTableLookup< 0, "tbl">;
3272 defm TBX : SIMDTableLookupTied<1, "tbx">;
3274 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3275 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3276 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3277 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3279 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3280 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3281 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3282 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3283 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3284 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3287 //----------------------------------------------------------------------------
3288 // AdvSIMD scalar CPY instruction
3289 //----------------------------------------------------------------------------
3291 defm CPY : SIMDScalarCPY<"cpy">;
3293 //----------------------------------------------------------------------------
3294 // AdvSIMD scalar pairwise instructions
3295 //----------------------------------------------------------------------------
3297 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3298 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3299 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3300 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3301 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3302 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3303 def : Pat<(i64 (int_aarch64_neon_saddv (v2i64 V128:$Rn))),
3304 (ADDPv2i64p V128:$Rn)>;
3305 def : Pat<(i64 (int_aarch64_neon_uaddv (v2i64 V128:$Rn))),
3306 (ADDPv2i64p V128:$Rn)>;
3307 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3308 (FADDPv2i32p V64:$Rn)>;
3309 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3310 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3311 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3312 (FADDPv2i64p V128:$Rn)>;
3313 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3314 (FMAXNMPv2i32p V64:$Rn)>;
3315 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3316 (FMAXNMPv2i64p V128:$Rn)>;
3317 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3318 (FMAXPv2i32p V64:$Rn)>;
3319 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3320 (FMAXPv2i64p V128:$Rn)>;
3321 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3322 (FMINNMPv2i32p V64:$Rn)>;
3323 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3324 (FMINNMPv2i64p V128:$Rn)>;
3325 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3326 (FMINPv2i32p V64:$Rn)>;
3327 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3328 (FMINPv2i64p V128:$Rn)>;
3330 //----------------------------------------------------------------------------
3331 // AdvSIMD INS/DUP instructions
3332 //----------------------------------------------------------------------------
3334 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3335 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3336 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3337 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3338 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3339 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3340 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3342 def DUPv2i64lane : SIMDDup64FromElement;
3343 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3344 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3345 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3346 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3347 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3348 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3350 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3351 (v2f32 (DUPv2i32lane
3352 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3354 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3355 (v4f32 (DUPv4i32lane
3356 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3358 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3359 (v2f64 (DUPv2i64lane
3360 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3362 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3363 (v4f16 (DUPv4i16lane
3364 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3366 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3367 (v8f16 (DUPv8i16lane
3368 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3371 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3372 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3373 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3374 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3376 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3377 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3378 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3379 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3380 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3381 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3383 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3384 // instruction even if the types don't match: we just have to remap the lane
3385 // carefully. N.b. this trick only applies to truncations.
3386 def VecIndex_x2 : SDNodeXForm<imm, [{
3387 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3389 def VecIndex_x4 : SDNodeXForm<imm, [{
3390 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3392 def VecIndex_x8 : SDNodeXForm<imm, [{
3393 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3396 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3397 ValueType Src128VT, ValueType ScalVT,
3398 Instruction DUP, SDNodeXForm IdxXFORM> {
3399 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3401 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3403 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3405 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3408 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3409 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3410 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3412 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3413 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3414 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3416 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3417 SDNodeXForm IdxXFORM> {
3418 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3420 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3422 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3424 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3427 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3428 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3429 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3431 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3432 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3433 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3435 // SMOV and UMOV definitions, with some extra patterns for convenience
3439 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3440 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3441 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3442 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3443 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3444 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3445 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3446 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3447 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3448 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3449 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3450 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3452 // Extracting i8 or i16 elements will have the zero-extend transformed to
3453 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3454 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3455 // bits of the destination register.
3456 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3458 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3459 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3461 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3465 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3466 (SUBREG_TO_REG (i32 0),
3467 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3468 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3469 (SUBREG_TO_REG (i32 0),
3470 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3472 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3473 (SUBREG_TO_REG (i32 0),
3474 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3475 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3476 (SUBREG_TO_REG (i32 0),
3477 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3479 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3480 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3481 (i32 FPR32:$Rn), ssub))>;
3482 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3483 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3484 (i32 FPR32:$Rn), ssub))>;
3485 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3486 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3487 (i64 FPR64:$Rn), dsub))>;
3489 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3490 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3491 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3492 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3493 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3494 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3496 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3497 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3500 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3502 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3506 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3507 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3509 V128:$Rn, VectorIndexH:$imm,
3510 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3513 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3514 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3517 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3519 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3522 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3523 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3525 V128:$Rn, VectorIndexS:$imm,
3526 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3528 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3529 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3531 V128:$Rn, VectorIndexD:$imm,
3532 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3535 // Copy an element at a constant index in one vector into a constant indexed
3536 // element of another.
3537 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3538 // index type and INS extension
3539 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3540 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3541 VectorIndexB:$idx2)),
3543 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3545 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3546 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3547 VectorIndexH:$idx2)),
3549 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3551 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3552 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3553 VectorIndexS:$idx2)),
3555 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3557 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3558 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3559 VectorIndexD:$idx2)),
3561 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3564 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3565 ValueType VTScal, Instruction INS> {
3566 def : Pat<(VT128 (vector_insert V128:$src,
3567 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3569 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3571 def : Pat<(VT128 (vector_insert V128:$src,
3572 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3574 (INS V128:$src, imm:$Immd,
3575 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3577 def : Pat<(VT64 (vector_insert V64:$src,
3578 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3580 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3581 imm:$Immd, V128:$Rn, imm:$Immn),
3584 def : Pat<(VT64 (vector_insert V64:$src,
3585 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3588 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3589 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3593 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3594 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3595 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3596 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3597 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3598 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3599 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3602 // Floating point vector extractions are codegen'd as either a sequence of
3603 // subregister extractions, possibly fed by an INS if the lane number is
3604 // anything other than zero.
3605 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3606 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3607 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3608 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3609 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3610 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3611 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3612 (f64 (EXTRACT_SUBREG
3613 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3614 V128:$Rn, VectorIndexD:$idx),
3616 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3617 (f32 (EXTRACT_SUBREG
3618 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3619 V128:$Rn, VectorIndexS:$idx),
3621 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3622 (f16 (EXTRACT_SUBREG
3623 (INSvi16lane (v8f16 (IMPLICIT_DEF)), 0,
3624 V128:$Rn, VectorIndexH:$idx),
3627 // All concat_vectors operations are canonicalised to act on i64 vectors for
3628 // AArch64. In the general case we need an instruction, which had just as well be
3630 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3631 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3632 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3633 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3635 def : ConcatPat<v2i64, v1i64>;
3636 def : ConcatPat<v2f64, v1f64>;
3637 def : ConcatPat<v4i32, v2i32>;
3638 def : ConcatPat<v4f32, v2f32>;
3639 def : ConcatPat<v8i16, v4i16>;
3640 def : ConcatPat<v8f16, v4f16>;
3641 def : ConcatPat<v16i8, v8i8>;
3643 // If the high lanes are undef, though, we can just ignore them:
3644 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3645 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3646 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3648 def : ConcatUndefPat<v2i64, v1i64>;
3649 def : ConcatUndefPat<v2f64, v1f64>;
3650 def : ConcatUndefPat<v4i32, v2i32>;
3651 def : ConcatUndefPat<v4f32, v2f32>;
3652 def : ConcatUndefPat<v8i16, v4i16>;
3653 def : ConcatUndefPat<v16i8, v8i8>;
3655 //----------------------------------------------------------------------------
3656 // AdvSIMD across lanes instructions
3657 //----------------------------------------------------------------------------
3659 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3660 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3661 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3662 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3663 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3664 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3665 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3666 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3667 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3668 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3669 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3671 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3672 // If there is a sign extension after this intrinsic, consume it as smov already
3674 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3676 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3677 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3679 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3681 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3682 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3684 // If there is a sign extension after this intrinsic, consume it as smov already
3686 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3688 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3689 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3691 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3693 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3694 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3696 // If there is a sign extension after this intrinsic, consume it as smov already
3698 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3700 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3701 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3703 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3705 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3706 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3708 // If there is a sign extension after this intrinsic, consume it as smov already
3710 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3712 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3713 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3715 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3717 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3718 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3721 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3722 (i32 (EXTRACT_SUBREG
3723 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3724 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3728 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3729 // If there is a masking operation keeping only what has been actually
3730 // generated, consume it.
3731 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3732 (i32 (EXTRACT_SUBREG
3733 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3734 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3736 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3737 (i32 (EXTRACT_SUBREG
3738 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3739 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3741 // If there is a masking operation keeping only what has been actually
3742 // generated, consume it.
3743 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3744 (i32 (EXTRACT_SUBREG
3745 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3746 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3748 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3749 (i32 (EXTRACT_SUBREG
3750 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3751 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3754 // If there is a masking operation keeping only what has been actually
3755 // generated, consume it.
3756 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3757 (i32 (EXTRACT_SUBREG
3758 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3759 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3761 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3762 (i32 (EXTRACT_SUBREG
3763 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3764 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3766 // If there is a masking operation keeping only what has been actually
3767 // generated, consume it.
3768 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3769 (i32 (EXTRACT_SUBREG
3770 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3771 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3773 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3774 (i32 (EXTRACT_SUBREG
3775 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3776 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3779 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3780 (i32 (EXTRACT_SUBREG
3781 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3782 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3787 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3788 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3790 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3791 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3793 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3795 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3796 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3799 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3800 (i32 (EXTRACT_SUBREG
3801 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3802 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3804 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3805 (i32 (EXTRACT_SUBREG
3806 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3807 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3810 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3811 (i64 (EXTRACT_SUBREG
3812 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3813 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3817 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3819 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3820 (i32 (EXTRACT_SUBREG
3821 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3822 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3824 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3825 (i32 (EXTRACT_SUBREG
3826 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3827 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3830 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3831 (i32 (EXTRACT_SUBREG
3832 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3833 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3835 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3836 (i32 (EXTRACT_SUBREG
3837 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3838 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3841 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3842 (i64 (EXTRACT_SUBREG
3843 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3844 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3848 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_aarch64_neon_saddv>;
3849 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3850 def : Pat<(i32 (int_aarch64_neon_saddv (v2i32 V64:$Rn))),
3851 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3853 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_aarch64_neon_uaddv>;
3854 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3855 def : Pat<(i32 (int_aarch64_neon_uaddv (v2i32 V64:$Rn))),
3856 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3858 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_aarch64_neon_smaxv>;
3859 def : Pat<(i32 (int_aarch64_neon_smaxv (v2i32 V64:$Rn))),
3860 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3862 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_aarch64_neon_sminv>;
3863 def : Pat<(i32 (int_aarch64_neon_sminv (v2i32 V64:$Rn))),
3864 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3866 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_aarch64_neon_umaxv>;
3867 def : Pat<(i32 (int_aarch64_neon_umaxv (v2i32 V64:$Rn))),
3868 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3870 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_aarch64_neon_uminv>;
3871 def : Pat<(i32 (int_aarch64_neon_uminv (v2i32 V64:$Rn))),
3872 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3874 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
3875 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
3877 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3878 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
3879 (i64 (EXTRACT_SUBREG
3880 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3881 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3883 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3884 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
3885 (i64 (EXTRACT_SUBREG
3886 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3887 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3890 //------------------------------------------------------------------------------
3891 // AdvSIMD modified immediate instructions
3892 //------------------------------------------------------------------------------
3895 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
3897 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
3899 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3900 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3901 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3902 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3904 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3905 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3906 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3907 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3909 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3910 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3911 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3912 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3914 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3915 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3916 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3917 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3920 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3922 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3923 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3925 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3926 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3928 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3932 // EDIT byte mask: scalar
3933 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3934 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3935 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3936 // The movi_edit node has the immediate value already encoded, so we use
3937 // a plain imm0_255 here.
3938 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
3939 (MOVID imm0_255:$shift)>;
3941 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3942 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3943 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3944 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3946 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3947 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3948 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3949 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3951 // EDIT byte mask: 2d
3953 // The movi_edit node has the immediate value already encoded, so we use
3954 // a plain imm0_255 in the pattern
3955 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3956 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3959 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
3962 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3963 // Complexity is added to break a tie with a plain MOVI.
3964 let AddedComplexity = 1 in {
3965 def : Pat<(f32 fpimm0),
3966 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3968 def : Pat<(f64 fpimm0),
3969 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3973 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3974 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3975 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3976 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3978 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3979 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3980 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3981 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3983 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
3984 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
3986 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3987 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3989 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3990 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3991 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3992 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3994 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3995 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3996 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3997 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3999 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4000 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4001 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4002 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4003 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4004 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4005 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4006 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4008 // EDIT per word: 2s & 4s with MSL shifter
4009 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4010 [(set (v2i32 V64:$Rd),
4011 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4012 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4013 [(set (v4i32 V128:$Rd),
4014 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4016 // Per byte: 8b & 16b
4017 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4019 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4020 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4022 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4026 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4027 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4029 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4030 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4031 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4032 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4034 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4035 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4036 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4037 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4039 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4040 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4041 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4042 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4043 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4044 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4045 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4046 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4048 // EDIT per word: 2s & 4s with MSL shifter
4049 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4050 [(set (v2i32 V64:$Rd),
4051 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4052 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4053 [(set (v4i32 V128:$Rd),
4054 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4056 //----------------------------------------------------------------------------
4057 // AdvSIMD indexed element
4058 //----------------------------------------------------------------------------
4060 let neverHasSideEffects = 1 in {
4061 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
4062 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
4065 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4066 // instruction expects the addend first, while the intrinsic expects it last.
4068 // On the other hand, there are quite a few valid combinatorial options due to
4069 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4070 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4071 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4072 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4073 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4075 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4076 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4077 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4078 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4079 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4080 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4081 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4082 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4084 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4085 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4087 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4088 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4089 VectorIndexS:$idx))),
4090 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4091 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4092 (v2f32 (AArch64duplane32
4093 (v4f32 (insert_subvector undef,
4094 (v2f32 (fneg V64:$Rm)),
4096 VectorIndexS:$idx)))),
4097 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4098 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4099 VectorIndexS:$idx)>;
4100 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4101 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4102 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4103 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4105 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4107 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4108 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4109 VectorIndexS:$idx))),
4110 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4111 VectorIndexS:$idx)>;
4112 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4113 (v4f32 (AArch64duplane32
4114 (v4f32 (insert_subvector undef,
4115 (v2f32 (fneg V64:$Rm)),
4117 VectorIndexS:$idx)))),
4118 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4119 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4120 VectorIndexS:$idx)>;
4121 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4122 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4123 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4124 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4126 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4127 // (DUPLANE from 64-bit would be trivial).
4128 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4129 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4130 VectorIndexD:$idx))),
4132 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4133 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4134 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4135 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4136 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4138 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4139 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4140 (vector_extract (v4f32 (fneg V128:$Rm)),
4141 VectorIndexS:$idx))),
4142 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4143 V128:$Rm, VectorIndexS:$idx)>;
4144 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4145 (vector_extract (v2f32 (fneg V64:$Rm)),
4146 VectorIndexS:$idx))),
4147 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4148 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4150 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4151 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4152 (vector_extract (v2f64 (fneg V128:$Rm)),
4153 VectorIndexS:$idx))),
4154 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4155 V128:$Rm, VectorIndexS:$idx)>;
4158 defm : FMLSIndexedAfterNegPatterns<
4159 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4160 defm : FMLSIndexedAfterNegPatterns<
4161 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4163 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4164 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4166 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4167 (FMULv2i32_indexed V64:$Rn,
4168 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4170 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4171 (FMULv4i32_indexed V128:$Rn,
4172 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4174 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4175 (FMULv2i64_indexed V128:$Rn,
4176 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4179 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4180 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4181 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4182 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4183 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4184 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4185 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4186 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4187 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4188 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4189 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4190 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4191 int_aarch64_neon_smull>;
4192 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4193 int_aarch64_neon_sqadd>;
4194 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4195 int_aarch64_neon_sqsub>;
4196 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4197 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4198 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4199 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4200 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4201 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4202 int_aarch64_neon_umull>;
4204 // A scalar sqdmull with the second operand being a vector lane can be
4205 // handled directly with the indexed instruction encoding.
4206 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4207 (vector_extract (v4i32 V128:$Vm),
4208 VectorIndexS:$idx)),
4209 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4211 //----------------------------------------------------------------------------
4212 // AdvSIMD scalar shift instructions
4213 //----------------------------------------------------------------------------
4214 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4215 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4216 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4217 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4218 // Codegen patterns for the above. We don't put these directly on the
4219 // instructions because TableGen's type inference can't handle the truth.
4220 // Having the same base pattern for fp <--> int totally freaks it out.
4221 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4222 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4223 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4224 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4225 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4226 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4227 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4228 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4229 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4231 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4232 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4234 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4235 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4236 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4237 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4238 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4239 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4240 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4241 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4242 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4243 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4245 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4246 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4248 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4250 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4251 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4252 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4253 int_aarch64_neon_sqrshrn>;
4254 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4255 int_aarch64_neon_sqrshrun>;
4256 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4257 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4258 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4259 int_aarch64_neon_sqshrn>;
4260 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4261 int_aarch64_neon_sqshrun>;
4262 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4263 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4264 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4265 TriOpFrag<(add node:$LHS,
4266 (AArch64srshri node:$MHS, node:$RHS))>>;
4267 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4268 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4269 TriOpFrag<(add node:$LHS,
4270 (AArch64vashr node:$MHS, node:$RHS))>>;
4271 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4272 int_aarch64_neon_uqrshrn>;
4273 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4274 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4275 int_aarch64_neon_uqshrn>;
4276 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4277 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4278 TriOpFrag<(add node:$LHS,
4279 (AArch64urshri node:$MHS, node:$RHS))>>;
4280 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4281 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4282 TriOpFrag<(add node:$LHS,
4283 (AArch64vlshr node:$MHS, node:$RHS))>>;
4285 //----------------------------------------------------------------------------
4286 // AdvSIMD vector shift instructions
4287 //----------------------------------------------------------------------------
4288 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4289 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4290 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4291 int_aarch64_neon_vcvtfxs2fp>;
4292 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4293 int_aarch64_neon_rshrn>;
4294 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4295 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4296 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4297 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4298 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4299 (i32 vecshiftL64:$imm))),
4300 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4301 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4302 int_aarch64_neon_sqrshrn>;
4303 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4304 int_aarch64_neon_sqrshrun>;
4305 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4306 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4307 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4308 int_aarch64_neon_sqshrn>;
4309 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4310 int_aarch64_neon_sqshrun>;
4311 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4312 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4313 (i32 vecshiftR64:$imm))),
4314 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4315 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4316 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4317 TriOpFrag<(add node:$LHS,
4318 (AArch64srshri node:$MHS, node:$RHS))> >;
4319 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4320 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4322 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4323 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4324 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4325 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4326 int_aarch64_neon_vcvtfxu2fp>;
4327 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4328 int_aarch64_neon_uqrshrn>;
4329 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4330 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4331 int_aarch64_neon_uqshrn>;
4332 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4333 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4334 TriOpFrag<(add node:$LHS,
4335 (AArch64urshri node:$MHS, node:$RHS))> >;
4336 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4337 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4338 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4339 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4340 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4342 // SHRN patterns for when a logical right shift was used instead of arithmetic
4343 // (the immediate guarantees no sign bits actually end up in the result so it
4345 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4346 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4347 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4348 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4349 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4350 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4352 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4353 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4354 vecshiftR16Narrow:$imm)))),
4355 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4356 V128:$Rn, vecshiftR16Narrow:$imm)>;
4357 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4358 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4359 vecshiftR32Narrow:$imm)))),
4360 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4361 V128:$Rn, vecshiftR32Narrow:$imm)>;
4362 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4363 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4364 vecshiftR64Narrow:$imm)))),
4365 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4366 V128:$Rn, vecshiftR32Narrow:$imm)>;
4368 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4369 // Anyexts are implemented as zexts.
4370 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4371 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4372 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4373 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4374 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4375 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4376 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4377 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4378 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4379 // Also match an extend from the upper half of a 128 bit source register.
4380 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4381 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4382 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4383 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4384 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4385 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4386 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4387 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4388 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4389 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4390 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4391 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4392 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4393 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4394 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4395 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4396 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4397 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4399 // Vector shift sxtl aliases
4400 def : InstAlias<"sxtl.8h $dst, $src1",
4401 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4402 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4403 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4404 def : InstAlias<"sxtl.4s $dst, $src1",
4405 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4406 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4407 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4408 def : InstAlias<"sxtl.2d $dst, $src1",
4409 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4410 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4411 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4413 // Vector shift sxtl2 aliases
4414 def : InstAlias<"sxtl2.8h $dst, $src1",
4415 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4416 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4417 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4418 def : InstAlias<"sxtl2.4s $dst, $src1",
4419 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4420 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4421 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4422 def : InstAlias<"sxtl2.2d $dst, $src1",
4423 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4424 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4425 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4427 // Vector shift uxtl aliases
4428 def : InstAlias<"uxtl.8h $dst, $src1",
4429 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4430 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4431 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4432 def : InstAlias<"uxtl.4s $dst, $src1",
4433 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4434 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4435 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4436 def : InstAlias<"uxtl.2d $dst, $src1",
4437 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4438 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4439 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4441 // Vector shift uxtl2 aliases
4442 def : InstAlias<"uxtl2.8h $dst, $src1",
4443 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4444 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4445 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4446 def : InstAlias<"uxtl2.4s $dst, $src1",
4447 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4448 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4449 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4450 def : InstAlias<"uxtl2.2d $dst, $src1",
4451 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4452 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4453 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4455 // If an integer is about to be converted to a floating point value,
4456 // just load it on the floating point unit.
4457 // These patterns are more complex because floating point loads do not
4458 // support sign extension.
4459 // The sign extension has to be explicitly added and is only supported for
4460 // one step: byte-to-half, half-to-word, word-to-doubleword.
4461 // SCVTF GPR -> FPR is 9 cycles.
4462 // SCVTF FPR -> FPR is 4 cyclces.
4463 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4464 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4465 // and still being faster.
4466 // However, this is not good for code size.
4467 // 8-bits -> float. 2 sizes step-up.
4468 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4469 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4470 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4475 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4481 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4483 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4484 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4485 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4486 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4487 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4488 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4489 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4490 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4492 // 16-bits -> float. 1 size step-up.
4493 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4494 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4495 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4497 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4501 ssub)))>, Requires<[NotForCodeSize]>;
4503 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4504 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4505 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4506 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4507 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4508 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4509 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4510 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4512 // 32-bits to 32-bits are handled in target specific dag combine:
4513 // performIntToFpCombine.
4514 // 64-bits integer to 32-bits floating point, not possible with
4515 // SCVTF on floating point registers (both source and destination
4516 // must have the same size).
4518 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4519 // 8-bits -> double. 3 size step-up: give up.
4520 // 16-bits -> double. 2 size step.
4521 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4522 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4523 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4528 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4534 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4536 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4537 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4538 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4539 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4540 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4541 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4542 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4543 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4544 // 32-bits -> double. 1 size step-up.
4545 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4546 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4547 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4549 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4553 dsub)))>, Requires<[NotForCodeSize]>;
4555 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4556 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4557 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4558 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4559 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4560 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4561 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4562 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4564 // 64-bits -> double are handled in target specific dag combine:
4565 // performIntToFpCombine.
4568 //----------------------------------------------------------------------------
4569 // AdvSIMD Load-Store Structure
4570 //----------------------------------------------------------------------------
4571 defm LD1 : SIMDLd1Multiple<"ld1">;
4572 defm LD2 : SIMDLd2Multiple<"ld2">;
4573 defm LD3 : SIMDLd3Multiple<"ld3">;
4574 defm LD4 : SIMDLd4Multiple<"ld4">;
4576 defm ST1 : SIMDSt1Multiple<"st1">;
4577 defm ST2 : SIMDSt2Multiple<"st2">;
4578 defm ST3 : SIMDSt3Multiple<"st3">;
4579 defm ST4 : SIMDSt4Multiple<"st4">;
4581 class Ld1Pat<ValueType ty, Instruction INST>
4582 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4584 def : Ld1Pat<v16i8, LD1Onev16b>;
4585 def : Ld1Pat<v8i16, LD1Onev8h>;
4586 def : Ld1Pat<v4i32, LD1Onev4s>;
4587 def : Ld1Pat<v2i64, LD1Onev2d>;
4588 def : Ld1Pat<v8i8, LD1Onev8b>;
4589 def : Ld1Pat<v4i16, LD1Onev4h>;
4590 def : Ld1Pat<v2i32, LD1Onev2s>;
4591 def : Ld1Pat<v1i64, LD1Onev1d>;
4593 class St1Pat<ValueType ty, Instruction INST>
4594 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4595 (INST ty:$Vt, GPR64sp:$Rn)>;
4597 def : St1Pat<v16i8, ST1Onev16b>;
4598 def : St1Pat<v8i16, ST1Onev8h>;
4599 def : St1Pat<v4i32, ST1Onev4s>;
4600 def : St1Pat<v2i64, ST1Onev2d>;
4601 def : St1Pat<v8i8, ST1Onev8b>;
4602 def : St1Pat<v4i16, ST1Onev4h>;
4603 def : St1Pat<v2i32, ST1Onev2s>;
4604 def : St1Pat<v1i64, ST1Onev1d>;
4610 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4611 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4612 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4613 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4614 let mayLoad = 1, neverHasSideEffects = 1 in {
4615 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4616 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4617 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4618 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4619 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4620 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4621 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4622 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4623 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4624 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4625 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4626 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4627 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4628 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4629 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4630 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4633 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4634 (LD1Rv8b GPR64sp:$Rn)>;
4635 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4636 (LD1Rv16b GPR64sp:$Rn)>;
4637 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4638 (LD1Rv4h GPR64sp:$Rn)>;
4639 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4640 (LD1Rv8h GPR64sp:$Rn)>;
4641 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4642 (LD1Rv2s GPR64sp:$Rn)>;
4643 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4644 (LD1Rv4s GPR64sp:$Rn)>;
4645 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4646 (LD1Rv2d GPR64sp:$Rn)>;
4647 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4648 (LD1Rv1d GPR64sp:$Rn)>;
4649 // Grab the floating point version too
4650 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4651 (LD1Rv2s GPR64sp:$Rn)>;
4652 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4653 (LD1Rv4s GPR64sp:$Rn)>;
4654 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4655 (LD1Rv2d GPR64sp:$Rn)>;
4656 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4657 (LD1Rv1d GPR64sp:$Rn)>;
4658 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4659 (LD1Rv4h GPR64sp:$Rn)>;
4660 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4661 (LD1Rv8h GPR64sp:$Rn)>;
4663 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4664 ValueType VTy, ValueType STy, Instruction LD1>
4665 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4666 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4667 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4669 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4670 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4671 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4672 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4673 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4674 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4675 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4677 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4678 ValueType VTy, ValueType STy, Instruction LD1>
4679 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4680 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4682 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4683 VecIndex:$idx, GPR64sp:$Rn),
4686 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4687 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4688 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4689 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4690 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4693 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4694 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4695 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4696 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4699 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4700 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4701 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4702 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4704 let AddedComplexity = 15 in
4705 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4706 ValueType VTy, ValueType STy, Instruction ST1>
4708 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4710 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4712 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4713 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4714 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4715 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4716 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4717 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4718 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
4720 let AddedComplexity = 15 in
4721 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4722 ValueType VTy, ValueType STy, Instruction ST1>
4724 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4726 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4727 VecIndex:$idx, GPR64sp:$Rn)>;
4729 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4730 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4731 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4732 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4733 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
4735 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4736 ValueType VTy, ValueType STy, Instruction ST1,
4738 def : Pat<(scalar_store
4739 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4740 GPR64sp:$Rn, offset),
4741 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4742 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4744 def : Pat<(scalar_store
4745 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4746 GPR64sp:$Rn, GPR64:$Rm),
4747 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4748 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4751 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4752 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4754 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4755 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4756 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4757 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4758 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
4760 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4761 ValueType VTy, ValueType STy, Instruction ST1,
4763 def : Pat<(scalar_store
4764 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4765 GPR64sp:$Rn, offset),
4766 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4768 def : Pat<(scalar_store
4769 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4770 GPR64sp:$Rn, GPR64:$Rm),
4771 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4774 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4776 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4778 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4779 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4780 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4781 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4782 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
4784 let mayStore = 1, neverHasSideEffects = 1 in {
4785 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4786 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4787 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4788 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4789 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4790 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4791 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4792 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4793 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4794 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4795 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4796 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4799 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4800 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4801 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4802 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4804 //----------------------------------------------------------------------------
4805 // Crypto extensions
4806 //----------------------------------------------------------------------------
4808 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
4809 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
4810 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
4811 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
4813 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
4814 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
4815 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
4816 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
4817 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
4818 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
4819 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
4821 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
4822 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
4823 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
4825 //----------------------------------------------------------------------------
4827 //----------------------------------------------------------------------------
4828 // FIXME: Like for X86, these should go in their own separate .td file.
4830 // Any instruction that defines a 32-bit result leaves the high half of the
4831 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4832 // be copying from a truncate. But any other 32-bit operation will zero-extend
4834 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4835 def def32 : PatLeaf<(i32 GPR32:$src), [{
4836 return N->getOpcode() != ISD::TRUNCATE &&
4837 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4838 N->getOpcode() != ISD::CopyFromReg;
4841 // In the case of a 32-bit def that is known to implicitly zero-extend,
4842 // we can use a SUBREG_TO_REG.
4843 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4845 // For an anyext, we don't care what the high bits are, so we can perform an
4846 // INSERT_SUBREF into an IMPLICIT_DEF.
4847 def : Pat<(i64 (anyext GPR32:$src)),
4848 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4850 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4851 // instruction (UBFM) on the enclosing super-reg.
4852 def : Pat<(i64 (zext GPR32:$src)),
4853 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4855 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4856 // containing super-reg.
4857 def : Pat<(i64 (sext GPR32:$src)),
4858 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4859 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4860 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4861 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4862 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4863 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4864 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4865 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4867 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4868 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4869 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4870 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4871 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4872 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4874 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4875 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4876 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4877 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4878 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4879 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4881 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4882 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4883 (i64 (i64shift_a imm0_63:$imm)),
4884 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4886 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4887 // AddedComplexity for the following patterns since we want to match sext + sra
4888 // patterns before we attempt to match a single sra node.
4889 let AddedComplexity = 20 in {
4890 // We support all sext + sra combinations which preserve at least one bit of the
4891 // original value which is to be sign extended. E.g. we support shifts up to
4893 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4894 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4895 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4896 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4898 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4899 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4900 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4901 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4903 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4904 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4905 (i64 imm0_31:$imm), 31)>;
4906 } // AddedComplexity = 20
4908 // To truncate, we can simply extract from a subregister.
4909 def : Pat<(i32 (trunc GPR64sp:$src)),
4910 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4912 // __builtin_trap() uses the BRK instruction on AArch64.
4913 def : Pat<(trap), (BRK 1)>;
4915 // Conversions within AdvSIMD types in the same register size are free.
4916 // But because we need a consistent lane ordering, in big endian many
4917 // conversions require one or more REV instructions.
4919 // Consider a simple memory load followed by a bitconvert then a store.
4921 // v1 = BITCAST v2i32 v0 to v4i16
4924 // In big endian mode every memory access has an implicit byte swap. LDR and
4925 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
4926 // is, they treat the vector as a sequence of elements to be byte-swapped.
4927 // The two pairs of instructions are fundamentally incompatible. We've decided
4928 // to use LD1/ST1 only to simplify compiler implementation.
4930 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
4931 // the original code sequence:
4933 // v1 = REV v2i32 (implicit)
4934 // v2 = BITCAST v2i32 v1 to v4i16
4935 // v3 = REV v4i16 v2 (implicit)
4938 // But this is now broken - the value stored is different to the value loaded
4939 // due to lane reordering. To fix this, on every BITCAST we must perform two
4942 // v1 = REV v2i32 (implicit)
4944 // v3 = BITCAST v2i32 v2 to v4i16
4946 // v5 = REV v4i16 v4 (implicit)
4949 // This means an extra two instructions, but actually in most cases the two REV
4950 // instructions can be combined into one. For example:
4951 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
4953 // There is also no 128-bit REV instruction. This must be synthesized with an
4956 // Most bitconverts require some sort of conversion. The only exceptions are:
4957 // a) Identity conversions - vNfX <-> vNiX
4958 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
4961 // Natural vector casts (64 bit)
4962 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4963 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4964 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
4966 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4967 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
4968 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4970 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
4971 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4972 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4974 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4975 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4976 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4977 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4979 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4980 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4981 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4983 // Natural vector casts (128 bit)
4984 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
4985 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
4986 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
4988 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
4989 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
4990 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
4992 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
4993 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
4994 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
4996 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
4997 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
4998 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
4999 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5000 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5001 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5003 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5004 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5005 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5006 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5008 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5009 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5010 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5011 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5012 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5014 let Predicates = [IsLE] in {
5015 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5016 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5017 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5018 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5019 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5021 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5022 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5023 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5024 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5025 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5026 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5027 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5028 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5029 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5030 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5031 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5032 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5034 let Predicates = [IsBE] in {
5035 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5036 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5037 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5038 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5039 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5040 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5041 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5042 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5043 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5044 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5046 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5047 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5048 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5049 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5050 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5051 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5052 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5053 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5054 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5055 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5057 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5058 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5059 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5060 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5061 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5062 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5063 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5064 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5065 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5067 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5068 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5069 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5070 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5071 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5072 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5073 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5074 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5075 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5076 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5078 let Predicates = [IsLE] in {
5079 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5080 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5081 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5082 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5083 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5085 let Predicates = [IsBE] in {
5086 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5087 (v1i64 (REV64v2i32 FPR64:$src))>;
5088 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5089 (v1i64 (REV64v4i16 FPR64:$src))>;
5090 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5091 (v1i64 (REV64v8i8 FPR64:$src))>;
5092 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5093 (v1i64 (REV64v4i16 FPR64:$src))>;
5094 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5095 (v1i64 (REV64v2i32 FPR64:$src))>;
5097 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5098 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5100 let Predicates = [IsLE] in {
5101 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5102 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5103 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5104 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5105 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5106 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5108 let Predicates = [IsBE] in {
5109 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5110 (v2i32 (REV64v2i32 FPR64:$src))>;
5111 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5112 (v2i32 (REV32v4i16 FPR64:$src))>;
5113 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5114 (v2i32 (REV32v8i8 FPR64:$src))>;
5115 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5116 (v2i32 (REV64v2i32 FPR64:$src))>;
5117 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5118 (v2i32 (REV64v2i32 FPR64:$src))>;
5119 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5120 (v2i32 (REV64v4i16 FPR64:$src))>;
5122 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5124 let Predicates = [IsLE] in {
5125 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5126 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5127 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5128 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5129 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5130 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5131 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5133 let Predicates = [IsBE] in {
5134 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5135 (v4i16 (REV64v4i16 FPR64:$src))>;
5136 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5137 (v4i16 (REV32v4i16 FPR64:$src))>;
5138 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5139 (v4i16 (REV16v8i8 FPR64:$src))>;
5140 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5141 (v4i16 (REV64v4i16 FPR64:$src))>;
5142 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5143 (v4i16 (REV32v4i16 FPR64:$src))>;
5144 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5145 (v4i16 (REV32v4i16 FPR64:$src))>;
5146 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5147 (v4i16 (REV64v4i16 FPR64:$src))>;
5150 let Predicates = [IsLE] in {
5151 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5152 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5153 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5154 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5155 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5156 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5157 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5159 let Predicates = [IsBE] in {
5160 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5161 (v4f16 (REV64v4i16 FPR64:$src))>;
5162 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5163 (v4f16 (REV64v4i16 FPR64:$src))>;
5164 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5165 (v4f16 (REV64v4i16 FPR64:$src))>;
5166 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5167 (v4f16 (REV16v8i8 FPR64:$src))>;
5168 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5169 (v4f16 (REV64v4i16 FPR64:$src))>;
5170 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5171 (v4f16 (REV64v4i16 FPR64:$src))>;
5172 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5173 (v4f16 (REV64v4i16 FPR64:$src))>;
5178 let Predicates = [IsLE] in {
5179 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5180 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5181 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5182 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5183 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5184 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5185 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5187 let Predicates = [IsBE] in {
5188 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5189 (v8i8 (REV64v8i8 FPR64:$src))>;
5190 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5191 (v8i8 (REV32v8i8 FPR64:$src))>;
5192 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5193 (v8i8 (REV16v8i8 FPR64:$src))>;
5194 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5195 (v8i8 (REV64v8i8 FPR64:$src))>;
5196 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5197 (v8i8 (REV32v8i8 FPR64:$src))>;
5198 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5199 (v8i8 (REV64v8i8 FPR64:$src))>;
5200 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5201 (v8i8 (REV16v8i8 FPR64:$src))>;
5204 let Predicates = [IsLE] in {
5205 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5206 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5207 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5208 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5209 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5211 let Predicates = [IsBE] in {
5212 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5213 (f64 (REV64v2i32 FPR64:$src))>;
5214 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5215 (f64 (REV64v4i16 FPR64:$src))>;
5216 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5217 (f64 (REV64v2i32 FPR64:$src))>;
5218 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5219 (f64 (REV64v8i8 FPR64:$src))>;
5220 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5221 (f64 (REV64v4i16 FPR64:$src))>;
5223 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5224 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5226 let Predicates = [IsLE] in {
5227 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5228 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5229 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5230 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5231 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5233 let Predicates = [IsBE] in {
5234 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5235 (v1f64 (REV64v2i32 FPR64:$src))>;
5236 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5237 (v1f64 (REV64v4i16 FPR64:$src))>;
5238 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5239 (v1f64 (REV64v8i8 FPR64:$src))>;
5240 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5241 (v1f64 (REV64v2i32 FPR64:$src))>;
5242 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5243 (v1f64 (REV64v4i16 FPR64:$src))>;
5245 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5246 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5248 let Predicates = [IsLE] in {
5249 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5250 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5251 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5252 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5253 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5254 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5256 let Predicates = [IsBE] in {
5257 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5258 (v2f32 (REV64v2i32 FPR64:$src))>;
5259 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5260 (v2f32 (REV32v4i16 FPR64:$src))>;
5261 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5262 (v2f32 (REV32v8i8 FPR64:$src))>;
5263 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5264 (v2f32 (REV64v2i32 FPR64:$src))>;
5265 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5266 (v2f32 (REV64v2i32 FPR64:$src))>;
5267 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5268 (v2f32 (REV64v4i16 FPR64:$src))>;
5270 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5272 let Predicates = [IsLE] in {
5273 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5274 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5275 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5276 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5277 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5278 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5279 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5281 let Predicates = [IsBE] in {
5282 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5283 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5284 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5285 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5286 (REV64v4i32 FPR128:$src), (i32 8)))>;
5287 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5288 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5289 (REV64v8i16 FPR128:$src), (i32 8)))>;
5290 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5291 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5292 (REV64v8i16 FPR128:$src), (i32 8)))>;
5293 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5294 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5295 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5296 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5297 (REV64v4i32 FPR128:$src), (i32 8)))>;
5298 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5299 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5300 (REV64v16i8 FPR128:$src), (i32 8)))>;
5303 let Predicates = [IsLE] in {
5304 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5305 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5306 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5307 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5308 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5309 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5311 let Predicates = [IsBE] in {
5312 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5313 (v2f64 (EXTv16i8 FPR128:$src,
5314 FPR128:$src, (i32 8)))>;
5315 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5316 (v2f64 (REV64v4i32 FPR128:$src))>;
5317 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5318 (v2f64 (REV64v8i16 FPR128:$src))>;
5319 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5320 (v2f64 (REV64v8i16 FPR128:$src))>;
5321 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5322 (v2f64 (REV64v16i8 FPR128:$src))>;
5323 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5324 (v2f64 (REV64v4i32 FPR128:$src))>;
5326 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5328 let Predicates = [IsLE] in {
5329 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5330 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5331 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5332 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5333 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5334 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5336 let Predicates = [IsBE] in {
5337 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5338 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5339 (REV64v4i32 FPR128:$src), (i32 8)))>;
5340 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5341 (v4f32 (REV32v8i16 FPR128:$src))>;
5342 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5343 (v4f32 (REV32v8i16 FPR128:$src))>;
5344 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5345 (v4f32 (REV32v16i8 FPR128:$src))>;
5346 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5347 (v4f32 (REV64v4i32 FPR128:$src))>;
5348 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5349 (v4f32 (REV64v4i32 FPR128:$src))>;
5351 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5353 let Predicates = [IsLE] in {
5354 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5355 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5356 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5357 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5358 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5359 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5361 let Predicates = [IsBE] in {
5362 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5363 (v2i64 (EXTv16i8 FPR128:$src,
5364 FPR128:$src, (i32 8)))>;
5365 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5366 (v2i64 (REV64v4i32 FPR128:$src))>;
5367 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5368 (v2i64 (REV64v8i16 FPR128:$src))>;
5369 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5370 (v2i64 (REV64v16i8 FPR128:$src))>;
5371 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5372 (v2i64 (REV64v4i32 FPR128:$src))>;
5373 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5374 (v2i64 (REV64v8i16 FPR128:$src))>;
5376 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5378 let Predicates = [IsLE] in {
5379 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5380 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5381 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5382 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5383 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5384 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5386 let Predicates = [IsBE] in {
5387 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5388 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5389 (REV64v4i32 FPR128:$src),
5391 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5392 (v4i32 (REV64v4i32 FPR128:$src))>;
5393 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5394 (v4i32 (REV32v8i16 FPR128:$src))>;
5395 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5396 (v4i32 (REV32v16i8 FPR128:$src))>;
5397 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5398 (v4i32 (REV64v4i32 FPR128:$src))>;
5399 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5400 (v4i32 (REV32v8i16 FPR128:$src))>;
5402 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5404 let Predicates = [IsLE] in {
5405 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5406 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5407 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5408 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5409 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5410 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5411 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5413 let Predicates = [IsBE] in {
5414 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5415 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5416 (REV64v8i16 FPR128:$src),
5418 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5419 (v8i16 (REV64v8i16 FPR128:$src))>;
5420 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5421 (v8i16 (REV32v8i16 FPR128:$src))>;
5422 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5423 (v8i16 (REV16v16i8 FPR128:$src))>;
5424 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5425 (v8i16 (REV64v8i16 FPR128:$src))>;
5426 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5427 (v8i16 (REV32v8i16 FPR128:$src))>;
5428 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5429 (v8i16 (REV32v8i16 FPR128:$src))>;
5432 let Predicates = [IsLE] in {
5433 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5434 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5435 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5436 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5437 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5438 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5439 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5441 let Predicates = [IsBE] in {
5442 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5443 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5444 (REV64v8i16 FPR128:$src),
5446 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5447 (v8f16 (REV64v8i16 FPR128:$src))>;
5448 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5449 (v8f16 (REV32v8i16 FPR128:$src))>;
5450 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5451 (v8f16 (REV64v8i16 FPR128:$src))>;
5452 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5453 (v8f16 (REV16v16i8 FPR128:$src))>;
5454 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5455 (v8f16 (REV64v8i16 FPR128:$src))>;
5456 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5457 (v8f16 (REV32v8i16 FPR128:$src))>;
5460 let Predicates = [IsLE] in {
5461 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5462 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5463 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5464 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5465 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5466 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5467 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5469 let Predicates = [IsBE] in {
5470 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5471 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5472 (REV64v16i8 FPR128:$src),
5474 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5475 (v16i8 (REV64v16i8 FPR128:$src))>;
5476 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5477 (v16i8 (REV32v16i8 FPR128:$src))>;
5478 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5479 (v16i8 (REV16v16i8 FPR128:$src))>;
5480 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5481 (v16i8 (REV64v16i8 FPR128:$src))>;
5482 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5483 (v16i8 (REV32v16i8 FPR128:$src))>;
5484 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5485 (v16i8 (REV16v16i8 FPR128:$src))>;
5488 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5489 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5490 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5491 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5492 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5493 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5494 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5495 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5497 // A 64-bit subvector insert to the first 128-bit vector position
5498 // is a subregister copy that needs no instruction.
5499 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5500 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5501 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5502 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5503 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5504 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5505 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5506 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5507 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5508 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5509 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5510 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5511 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5512 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5514 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5516 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5517 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5518 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5519 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5520 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5521 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5522 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5523 // so we match on v4f32 here, not v2f32. This will also catch adding
5524 // the low two lanes of a true v4f32 vector.
5525 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5526 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5527 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5529 // Scalar 64-bit shifts in FPR64 registers.
5530 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5531 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5532 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5533 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5534 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5535 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5536 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5537 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5539 // Tail call return handling. These are all compiler pseudo-instructions,
5540 // so no encoding information or anything like that.
5541 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5542 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5543 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5546 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5547 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5548 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5549 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5550 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5551 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5553 include "AArch64InstrAtomics.td"