1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // (outs Result), (ins Imm, OpCmode)
19 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
21 def Neon_movi : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
23 def Neon_mvni : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
25 // (outs Result), (ins Imm)
26 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
27 [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
29 // (outs Result), (ins LHS, RHS, CondCode)
30 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
31 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
33 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
34 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
35 [SDTCisVec<0>, SDTCisVec<1>]>>;
37 // (outs Result), (ins LHS, RHS)
38 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
39 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
41 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
43 def Neon_sqrshlImm : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
44 def Neon_uqrshlImm : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
46 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
48 def Neon_uzp1 : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
49 def Neon_uzp2 : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
50 def Neon_zip1 : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
51 def Neon_zip2 : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
52 def Neon_trn1 : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
53 def Neon_trn2 : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
55 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
56 def Neon_rev64 : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
57 def Neon_rev32 : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
58 def Neon_rev16 : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
59 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
61 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
62 [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
63 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
64 [SDTCisVec<0>, SDTCisSameAs<0, 1>,
65 SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
67 def SDT_assertext : SDTypeProfile<1, 1,
68 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
69 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
70 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
72 //===----------------------------------------------------------------------===//
73 // Addressing-mode instantiations
74 //===----------------------------------------------------------------------===//
76 multiclass ls_64_pats<dag address, dag Base, dag Offset, ValueType Ty> {
77 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
78 !foreach(decls.pattern, Offset,
79 !subst(OFFSET, dword_uimm12, decls.pattern)),
80 !foreach(decls.pattern, address,
81 !subst(OFFSET, dword_uimm12,
82 !subst(ALIGN, min_align8, decls.pattern))),
86 multiclass ls_128_pats<dag address, dag Base, dag Offset, ValueType Ty> {
87 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
88 !foreach(decls.pattern, Offset,
89 !subst(OFFSET, qword_uimm12, decls.pattern)),
90 !foreach(decls.pattern, address,
91 !subst(OFFSET, qword_uimm12,
92 !subst(ALIGN, min_align16, decls.pattern))),
96 multiclass uimm12_neon_pats<dag address, dag Base, dag Offset> {
97 defm : ls_64_pats<address, Base, Offset, v8i8>;
98 defm : ls_64_pats<address, Base, Offset, v4i16>;
99 defm : ls_64_pats<address, Base, Offset, v2i32>;
100 defm : ls_64_pats<address, Base, Offset, v1i64>;
101 defm : ls_64_pats<address, Base, Offset, v2f32>;
102 defm : ls_64_pats<address, Base, Offset, v1f64>;
104 defm : ls_128_pats<address, Base, Offset, v16i8>;
105 defm : ls_128_pats<address, Base, Offset, v8i16>;
106 defm : ls_128_pats<address, Base, Offset, v4i32>;
107 defm : ls_128_pats<address, Base, Offset, v2i64>;
108 defm : ls_128_pats<address, Base, Offset, v4f32>;
109 defm : ls_128_pats<address, Base, Offset, v2f64>;
112 defm : uimm12_neon_pats<(A64WrapperSmall
113 tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
114 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
116 //===----------------------------------------------------------------------===//
118 //===----------------------------------------------------------------------===//
120 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size, bits<5> opcode,
121 string asmop, SDPatternOperator opnode8B,
122 SDPatternOperator opnode16B,
123 bit Commutable = 0> {
124 let isCommutable = Commutable in {
125 def _8B : NeonI_3VSame<0b0, u, size, opcode,
126 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
127 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
128 [(set (v8i8 VPR64:$Rd),
129 (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
132 def _16B : NeonI_3VSame<0b1, u, size, opcode,
133 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
134 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
135 [(set (v16i8 VPR128:$Rd),
136 (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
142 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
143 string asmop, SDPatternOperator opnode,
144 bit Commutable = 0> {
145 let isCommutable = Commutable in {
146 def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
147 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
148 asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
149 [(set (v4i16 VPR64:$Rd),
150 (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
153 def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
154 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
155 asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
156 [(set (v8i16 VPR128:$Rd),
157 (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
160 def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
161 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
162 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
163 [(set (v2i32 VPR64:$Rd),
164 (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
167 def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
168 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
169 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
170 [(set (v4i32 VPR128:$Rd),
171 (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
175 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
176 string asmop, SDPatternOperator opnode,
178 : NeonI_3VSame_HS_sizes<u, opcode, asmop, opnode, Commutable> {
179 let isCommutable = Commutable in {
180 def _8B : NeonI_3VSame<0b0, u, 0b00, opcode,
181 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
182 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
183 [(set (v8i8 VPR64:$Rd),
184 (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
187 def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
188 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
189 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
190 [(set (v16i8 VPR128:$Rd),
191 (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
196 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
197 string asmop, SDPatternOperator opnode,
199 : NeonI_3VSame_BHS_sizes<u, opcode, asmop, opnode, Commutable> {
200 let isCommutable = Commutable in {
201 def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
202 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
203 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
204 [(set (v2i64 VPR128:$Rd),
205 (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
210 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
211 // but Result types can be integer or floating point types.
212 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
213 string asmop, SDPatternOperator opnode2S,
214 SDPatternOperator opnode4S,
215 SDPatternOperator opnode2D,
216 ValueType ResTy2S, ValueType ResTy4S,
217 ValueType ResTy2D, bit Commutable = 0> {
218 let isCommutable = Commutable in {
219 def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
220 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
221 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
222 [(set (ResTy2S VPR64:$Rd),
223 (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
226 def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
227 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
228 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
229 [(set (ResTy4S VPR128:$Rd),
230 (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
233 def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
234 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
235 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
236 [(set (ResTy2D VPR128:$Rd),
237 (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
242 //===----------------------------------------------------------------------===//
243 // Instruction Definitions
244 //===----------------------------------------------------------------------===//
246 // Vector Arithmetic Instructions
248 // Vector Add (Integer and Floating-Point)
250 defm ADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
251 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
252 v2f32, v4f32, v2f64, 1>;
254 // Vector Sub (Integer and Floating-Point)
256 defm SUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
257 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
258 v2f32, v4f32, v2f64, 0>;
260 // Vector Multiply (Integer and Floating-Point)
262 defm MULvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
263 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
264 v2f32, v4f32, v2f64, 1>;
266 // Vector Multiply (Polynomial)
268 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
269 int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
271 // Vector Multiply-accumulate and Multiply-subtract (Integer)
273 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
274 // two operands constraints.
275 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
276 RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
277 bits<5> opcode, SDPatternOperator opnode>
278 : NeonI_3VSame<q, u, size, opcode,
279 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
280 asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
281 [(set (OpTy VPRC:$Rd),
282 (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
284 let Constraints = "$src = $Rd";
287 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
288 (add node:$Ra, (mul node:$Rn, node:$Rm))>;
290 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
291 (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
294 def MLAvvv_8B: NeonI_3VSame_Constraint_impl<"mla", ".8b", VPR64, v8i8,
295 0b0, 0b0, 0b00, 0b10010, Neon_mla>;
296 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
297 0b1, 0b0, 0b00, 0b10010, Neon_mla>;
298 def MLAvvv_4H: NeonI_3VSame_Constraint_impl<"mla", ".4h", VPR64, v4i16,
299 0b0, 0b0, 0b01, 0b10010, Neon_mla>;
300 def MLAvvv_8H: NeonI_3VSame_Constraint_impl<"mla", ".8h", VPR128, v8i16,
301 0b1, 0b0, 0b01, 0b10010, Neon_mla>;
302 def MLAvvv_2S: NeonI_3VSame_Constraint_impl<"mla", ".2s", VPR64, v2i32,
303 0b0, 0b0, 0b10, 0b10010, Neon_mla>;
304 def MLAvvv_4S: NeonI_3VSame_Constraint_impl<"mla", ".4s", VPR128, v4i32,
305 0b1, 0b0, 0b10, 0b10010, Neon_mla>;
307 def MLSvvv_8B: NeonI_3VSame_Constraint_impl<"mls", ".8b", VPR64, v8i8,
308 0b0, 0b1, 0b00, 0b10010, Neon_mls>;
309 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
310 0b1, 0b1, 0b00, 0b10010, Neon_mls>;
311 def MLSvvv_4H: NeonI_3VSame_Constraint_impl<"mls", ".4h", VPR64, v4i16,
312 0b0, 0b1, 0b01, 0b10010, Neon_mls>;
313 def MLSvvv_8H: NeonI_3VSame_Constraint_impl<"mls", ".8h", VPR128, v8i16,
314 0b1, 0b1, 0b01, 0b10010, Neon_mls>;
315 def MLSvvv_2S: NeonI_3VSame_Constraint_impl<"mls", ".2s", VPR64, v2i32,
316 0b0, 0b1, 0b10, 0b10010, Neon_mls>;
317 def MLSvvv_4S: NeonI_3VSame_Constraint_impl<"mls", ".4s", VPR128, v4i32,
318 0b1, 0b1, 0b10, 0b10010, Neon_mls>;
320 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
322 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
323 (fadd node:$Ra, (fmul_su node:$Rn, node:$Rm))>;
325 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
326 (fsub node:$Ra, (fmul_su node:$Rn, node:$Rm))>;
328 let Predicates = [HasNEON, UseFusedMAC] in {
329 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s", VPR64, v2f32,
330 0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
331 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s", VPR128, v4f32,
332 0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
333 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d", VPR128, v2f64,
334 0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
336 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s", VPR64, v2f32,
337 0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
338 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s", VPR128, v4f32,
339 0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
340 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d", VPR128, v2f64,
341 0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
344 // We're also allowed to match the fma instruction regardless of compile
346 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
347 (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
348 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
349 (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
350 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
351 (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
353 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
354 (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
355 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
356 (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
357 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
358 (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
360 // Vector Divide (Floating-Point)
362 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
363 v2f32, v4f32, v2f64, 0>;
365 // Vector Bitwise Operations
367 // Vector Bitwise AND
369 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
371 // Vector Bitwise Exclusive OR
373 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
377 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
379 // ORR disassembled as MOV if Vn==Vm
381 // Vector Move - register
382 // Alias for ORR if Vn=Vm.
383 // FIXME: This is actually the preferred syntax but TableGen can't deal with
384 // custom printing of aliases.
385 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
386 (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
387 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
388 (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
390 // The MOVI instruction takes two immediate operands. The first is the
391 // immediate encoding, while the second is the cmode. A cmode of 14, or
392 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
393 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
394 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
396 def Neon_not8B : PatFrag<(ops node:$in),
397 (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
398 def Neon_not16B : PatFrag<(ops node:$in),
399 (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
401 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
402 (or node:$Rn, (Neon_not8B node:$Rm))>;
404 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
405 (or node:$Rn, (Neon_not16B node:$Rm))>;
407 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
408 (and node:$Rn, (Neon_not8B node:$Rm))>;
410 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
411 (and node:$Rn, (Neon_not16B node:$Rm))>;
414 // Vector Bitwise OR NOT - register
416 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
417 Neon_orn8B, Neon_orn16B, 0>;
419 // Vector Bitwise Bit Clear (AND NOT) - register
421 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
422 Neon_bic8B, Neon_bic16B, 0>;
424 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
425 SDPatternOperator opnode16B,
427 Instruction INST16B> {
428 def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
429 (INST8B VPR64:$Rn, VPR64:$Rm)>;
430 def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
431 (INST8B VPR64:$Rn, VPR64:$Rm)>;
432 def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
433 (INST8B VPR64:$Rn, VPR64:$Rm)>;
434 def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
435 (INST16B VPR128:$Rn, VPR128:$Rm)>;
436 def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
437 (INST16B VPR128:$Rn, VPR128:$Rm)>;
438 def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
439 (INST16B VPR128:$Rn, VPR128:$Rm)>;
442 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
443 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
444 defm : Neon_bitwise2V_patterns<or, or, ORRvvv_8B, ORRvvv_16B>;
445 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
446 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
447 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
449 // Vector Bitwise Select
450 def BSLvvv_8B : NeonI_3VSame_Constraint_impl<"bsl", ".8b", VPR64, v8i8,
451 0b0, 0b1, 0b01, 0b00011, vselect>;
453 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
454 0b1, 0b1, 0b01, 0b00011, vselect>;
456 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
458 Instruction INST16B> {
459 // Disassociate type from instruction definition
460 def : Pat<(v8i8 (opnode (v8i8 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
461 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
462 def : Pat<(v2i32 (opnode (v2i32 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
463 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
464 def : Pat<(v4i16 (opnode (v4i16 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
465 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
466 def : Pat<(v1i64 (opnode (v1i64 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
467 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
468 def : Pat<(v16i8 (opnode (v16i8 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
469 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
470 def : Pat<(v4i32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
471 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
472 def : Pat<(v8i16 (opnode (v8i16 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
473 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
474 def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
475 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
477 // Allow to match BSL instruction pattern with non-constant operand
478 def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
479 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
480 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
481 def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
482 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
483 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
484 def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
485 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
486 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
487 def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
488 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
489 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
490 def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
491 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
492 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
493 def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
494 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
495 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
496 def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
497 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
498 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
499 def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
500 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
501 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
503 // Allow to match llvm.arm.* intrinsics.
504 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
505 (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
506 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
507 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
508 (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
509 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
510 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
511 (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
512 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
513 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
514 (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
515 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
516 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
517 (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
518 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
519 def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
520 (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
521 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
522 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
523 (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
524 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
525 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
526 (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
527 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
528 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
529 (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
530 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
531 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
532 (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
533 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
534 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
535 (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
536 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
537 def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
538 (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
539 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
542 // Additional patterns for bitwise instruction BSL
543 defm: Neon_bitwise3V_patterns<vselect, BSLvvv_8B, BSLvvv_16B>;
545 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
546 (vselect node:$src, node:$Rn, node:$Rm),
547 [{ (void)N; return false; }]>;
549 // Vector Bitwise Insert if True
551 def BITvvv_8B : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64, v8i8,
552 0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
553 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
554 0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
556 // Vector Bitwise Insert if False
558 def BIFvvv_8B : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64, v8i8,
559 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
560 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
561 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
563 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
565 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
566 (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
567 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
568 (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
570 // Vector Absolute Difference and Accumulate (Unsigned)
571 def UABAvvv_8B : NeonI_3VSame_Constraint_impl<"uaba", ".8b", VPR64, v8i8,
572 0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
573 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
574 0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
575 def UABAvvv_4H : NeonI_3VSame_Constraint_impl<"uaba", ".4h", VPR64, v4i16,
576 0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
577 def UABAvvv_8H : NeonI_3VSame_Constraint_impl<"uaba", ".8h", VPR128, v8i16,
578 0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
579 def UABAvvv_2S : NeonI_3VSame_Constraint_impl<"uaba", ".2s", VPR64, v2i32,
580 0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
581 def UABAvvv_4S : NeonI_3VSame_Constraint_impl<"uaba", ".4s", VPR128, v4i32,
582 0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
584 // Vector Absolute Difference and Accumulate (Signed)
585 def SABAvvv_8B : NeonI_3VSame_Constraint_impl<"saba", ".8b", VPR64, v8i8,
586 0b0, 0b0, 0b00, 0b01111, Neon_saba>;
587 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
588 0b1, 0b0, 0b00, 0b01111, Neon_saba>;
589 def SABAvvv_4H : NeonI_3VSame_Constraint_impl<"saba", ".4h", VPR64, v4i16,
590 0b0, 0b0, 0b01, 0b01111, Neon_saba>;
591 def SABAvvv_8H : NeonI_3VSame_Constraint_impl<"saba", ".8h", VPR128, v8i16,
592 0b1, 0b0, 0b01, 0b01111, Neon_saba>;
593 def SABAvvv_2S : NeonI_3VSame_Constraint_impl<"saba", ".2s", VPR64, v2i32,
594 0b0, 0b0, 0b10, 0b01111, Neon_saba>;
595 def SABAvvv_4S : NeonI_3VSame_Constraint_impl<"saba", ".4s", VPR128, v4i32,
596 0b1, 0b0, 0b10, 0b01111, Neon_saba>;
599 // Vector Absolute Difference (Signed, Unsigned)
600 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
601 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
603 // Vector Absolute Difference (Floating Point)
604 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
605 int_arm_neon_vabds, int_arm_neon_vabds,
606 int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
608 // Vector Reciprocal Step (Floating Point)
609 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
610 int_arm_neon_vrecps, int_arm_neon_vrecps,
612 v2f32, v4f32, v2f64, 0>;
614 // Vector Reciprocal Square Root Step (Floating Point)
615 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
616 int_arm_neon_vrsqrts,
617 int_arm_neon_vrsqrts,
618 int_arm_neon_vrsqrts,
619 v2f32, v4f32, v2f64, 0>;
621 // Vector Comparisons
623 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
624 (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
625 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
626 (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
627 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
628 (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
629 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
630 (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
631 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
632 (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
634 // NeonI_compare_aliases class: swaps register operands to implement
635 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
636 class NeonI_compare_aliases<string asmop, string asmlane,
637 Instruction inst, RegisterOperand VPRC>
638 : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
640 (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
642 // Vector Comparisons (Integer)
644 // Vector Compare Mask Equal (Integer)
645 let isCommutable =1 in {
646 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
649 // Vector Compare Mask Higher or Same (Unsigned Integer)
650 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
652 // Vector Compare Mask Greater Than or Equal (Integer)
653 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
655 // Vector Compare Mask Higher (Unsigned Integer)
656 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
658 // Vector Compare Mask Greater Than (Integer)
659 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
661 // Vector Compare Mask Bitwise Test (Integer)
662 defm CMTSTvvv: NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
664 // Vector Compare Mask Less or Same (Unsigned Integer)
665 // CMLS is alias for CMHS with operands reversed.
666 def CMLSvvv_8B : NeonI_compare_aliases<"cmls", ".8b", CMHSvvv_8B, VPR64>;
667 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
668 def CMLSvvv_4H : NeonI_compare_aliases<"cmls", ".4h", CMHSvvv_4H, VPR64>;
669 def CMLSvvv_8H : NeonI_compare_aliases<"cmls", ".8h", CMHSvvv_8H, VPR128>;
670 def CMLSvvv_2S : NeonI_compare_aliases<"cmls", ".2s", CMHSvvv_2S, VPR64>;
671 def CMLSvvv_4S : NeonI_compare_aliases<"cmls", ".4s", CMHSvvv_4S, VPR128>;
672 def CMLSvvv_2D : NeonI_compare_aliases<"cmls", ".2d", CMHSvvv_2D, VPR128>;
674 // Vector Compare Mask Less Than or Equal (Integer)
675 // CMLE is alias for CMGE with operands reversed.
676 def CMLEvvv_8B : NeonI_compare_aliases<"cmle", ".8b", CMGEvvv_8B, VPR64>;
677 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
678 def CMLEvvv_4H : NeonI_compare_aliases<"cmle", ".4h", CMGEvvv_4H, VPR64>;
679 def CMLEvvv_8H : NeonI_compare_aliases<"cmle", ".8h", CMGEvvv_8H, VPR128>;
680 def CMLEvvv_2S : NeonI_compare_aliases<"cmle", ".2s", CMGEvvv_2S, VPR64>;
681 def CMLEvvv_4S : NeonI_compare_aliases<"cmle", ".4s", CMGEvvv_4S, VPR128>;
682 def CMLEvvv_2D : NeonI_compare_aliases<"cmle", ".2d", CMGEvvv_2D, VPR128>;
684 // Vector Compare Mask Lower (Unsigned Integer)
685 // CMLO is alias for CMHI with operands reversed.
686 def CMLOvvv_8B : NeonI_compare_aliases<"cmlo", ".8b", CMHIvvv_8B, VPR64>;
687 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
688 def CMLOvvv_4H : NeonI_compare_aliases<"cmlo", ".4h", CMHIvvv_4H, VPR64>;
689 def CMLOvvv_8H : NeonI_compare_aliases<"cmlo", ".8h", CMHIvvv_8H, VPR128>;
690 def CMLOvvv_2S : NeonI_compare_aliases<"cmlo", ".2s", CMHIvvv_2S, VPR64>;
691 def CMLOvvv_4S : NeonI_compare_aliases<"cmlo", ".4s", CMHIvvv_4S, VPR128>;
692 def CMLOvvv_2D : NeonI_compare_aliases<"cmlo", ".2d", CMHIvvv_2D, VPR128>;
694 // Vector Compare Mask Less Than (Integer)
695 // CMLT is alias for CMGT with operands reversed.
696 def CMLTvvv_8B : NeonI_compare_aliases<"cmlt", ".8b", CMGTvvv_8B, VPR64>;
697 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
698 def CMLTvvv_4H : NeonI_compare_aliases<"cmlt", ".4h", CMGTvvv_4H, VPR64>;
699 def CMLTvvv_8H : NeonI_compare_aliases<"cmlt", ".8h", CMGTvvv_8H, VPR128>;
700 def CMLTvvv_2S : NeonI_compare_aliases<"cmlt", ".2s", CMGTvvv_2S, VPR64>;
701 def CMLTvvv_4S : NeonI_compare_aliases<"cmlt", ".4s", CMGTvvv_4S, VPR128>;
702 def CMLTvvv_2D : NeonI_compare_aliases<"cmlt", ".2d", CMGTvvv_2D, VPR128>;
705 def neon_uimm0_asmoperand : AsmOperandClass
708 let PredicateMethod = "isUImm<0>";
709 let RenderMethod = "addImmOperands";
712 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
713 let ParserMatchClass = neon_uimm0_asmoperand;
714 let PrintMethod = "printNeonUImm0Operand";
718 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
720 def _8B : NeonI_2VMisc<0b0, u, 0b00, opcode,
721 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
722 asmop # "\t$Rd.8b, $Rn.8b, $Imm",
723 [(set (v8i8 VPR64:$Rd),
724 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
727 def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
728 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
729 asmop # "\t$Rd.16b, $Rn.16b, $Imm",
730 [(set (v16i8 VPR128:$Rd),
731 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
734 def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
735 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
736 asmop # "\t$Rd.4h, $Rn.4h, $Imm",
737 [(set (v4i16 VPR64:$Rd),
738 (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
741 def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
742 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
743 asmop # "\t$Rd.8h, $Rn.8h, $Imm",
744 [(set (v8i16 VPR128:$Rd),
745 (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
748 def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
749 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
750 asmop # "\t$Rd.2s, $Rn.2s, $Imm",
751 [(set (v2i32 VPR64:$Rd),
752 (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
755 def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
756 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
757 asmop # "\t$Rd.4s, $Rn.4s, $Imm",
758 [(set (v4i32 VPR128:$Rd),
759 (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
762 def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
763 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
764 asmop # "\t$Rd.2d, $Rn.2d, $Imm",
765 [(set (v2i64 VPR128:$Rd),
766 (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
770 // Vector Compare Mask Equal to Zero (Integer)
771 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
773 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
774 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
776 // Vector Compare Mask Greater Than Zero (Signed Integer)
777 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
779 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
780 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
782 // Vector Compare Mask Less Than Zero (Signed Integer)
783 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
785 // Vector Comparisons (Floating Point)
787 // Vector Compare Mask Equal (Floating Point)
788 let isCommutable =1 in {
789 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
790 Neon_cmeq, Neon_cmeq,
791 v2i32, v4i32, v2i64, 0>;
794 // Vector Compare Mask Greater Than Or Equal (Floating Point)
795 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
796 Neon_cmge, Neon_cmge,
797 v2i32, v4i32, v2i64, 0>;
799 // Vector Compare Mask Greater Than (Floating Point)
800 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
801 Neon_cmgt, Neon_cmgt,
802 v2i32, v4i32, v2i64, 0>;
804 // Vector Compare Mask Less Than Or Equal (Floating Point)
805 // FCMLE is alias for FCMGE with operands reversed.
806 def FCMLEvvv_2S : NeonI_compare_aliases<"fcmle", ".2s", FCMGEvvv_2S, VPR64>;
807 def FCMLEvvv_4S : NeonI_compare_aliases<"fcmle", ".4s", FCMGEvvv_4S, VPR128>;
808 def FCMLEvvv_2D : NeonI_compare_aliases<"fcmle", ".2d", FCMGEvvv_2D, VPR128>;
810 // Vector Compare Mask Less Than (Floating Point)
811 // FCMLT is alias for FCMGT with operands reversed.
812 def FCMLTvvv_2S : NeonI_compare_aliases<"fcmlt", ".2s", FCMGTvvv_2S, VPR64>;
813 def FCMLTvvv_4S : NeonI_compare_aliases<"fcmlt", ".4s", FCMGTvvv_4S, VPR128>;
814 def FCMLTvvv_2D : NeonI_compare_aliases<"fcmlt", ".2d", FCMGTvvv_2D, VPR128>;
816 def fpzero_izero_asmoperand : AsmOperandClass {
817 let Name = "FPZeroIZero";
818 let ParserMethod = "ParseFPImm0AndImm0Operand";
819 let DiagnosticType = "FPZero";
822 def fpzz32 : Operand<f32>,
823 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
824 let ParserMatchClass = fpzero_izero_asmoperand;
825 let PrintMethod = "printFPZeroOperand";
826 let DecoderMethod = "DecodeFPZeroOperand";
829 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
830 string asmop, CondCode CC>
832 def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
833 (outs VPR64:$Rd), (ins VPR64:$Rn, fpzz32:$FPImm),
834 asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
835 [(set (v2i32 VPR64:$Rd),
836 (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpzz32:$FPImm), CC)))],
839 def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
840 (outs VPR128:$Rd), (ins VPR128:$Rn, fpzz32:$FPImm),
841 asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
842 [(set (v4i32 VPR128:$Rd),
843 (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpzz32:$FPImm), CC)))],
846 def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
847 (outs VPR128:$Rd), (ins VPR128:$Rn, fpzz32:$FPImm),
848 asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
849 [(set (v2i64 VPR128:$Rd),
850 (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpzz32:$FPImm), CC)))],
854 // Vector Compare Mask Equal to Zero (Floating Point)
855 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
857 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
858 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
860 // Vector Compare Mask Greater Than Zero (Floating Point)
861 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
863 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
864 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
866 // Vector Compare Mask Less Than Zero (Floating Point)
867 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
869 // Vector Absolute Comparisons (Floating Point)
871 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
872 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
873 int_arm_neon_vacged, int_arm_neon_vacgeq,
874 int_aarch64_neon_vacgeq,
875 v2i32, v4i32, v2i64, 0>;
877 // Vector Absolute Compare Mask Greater Than (Floating Point)
878 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
879 int_arm_neon_vacgtd, int_arm_neon_vacgtq,
880 int_aarch64_neon_vacgtq,
881 v2i32, v4i32, v2i64, 0>;
883 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
884 // FACLE is alias for FACGE with operands reversed.
885 def FACLEvvv_2S : NeonI_compare_aliases<"facle", ".2s", FACGEvvv_2S, VPR64>;
886 def FACLEvvv_4S : NeonI_compare_aliases<"facle", ".4s", FACGEvvv_4S, VPR128>;
887 def FACLEvvv_2D : NeonI_compare_aliases<"facle", ".2d", FACGEvvv_2D, VPR128>;
889 // Vector Absolute Compare Mask Less Than (Floating Point)
890 // FACLT is alias for FACGT with operands reversed.
891 def FACLTvvv_2S : NeonI_compare_aliases<"faclt", ".2s", FACGTvvv_2S, VPR64>;
892 def FACLTvvv_4S : NeonI_compare_aliases<"faclt", ".4s", FACGTvvv_4S, VPR128>;
893 def FACLTvvv_2D : NeonI_compare_aliases<"faclt", ".2d", FACGTvvv_2D, VPR128>;
895 // Vector halving add (Integer Signed, Unsigned)
896 defm SHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
897 int_arm_neon_vhadds, 1>;
898 defm UHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
899 int_arm_neon_vhaddu, 1>;
901 // Vector halving sub (Integer Signed, Unsigned)
902 defm SHSUBvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
903 int_arm_neon_vhsubs, 0>;
904 defm UHSUBvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
905 int_arm_neon_vhsubu, 0>;
907 // Vector rouding halving add (Integer Signed, Unsigned)
908 defm SRHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
909 int_arm_neon_vrhadds, 1>;
910 defm URHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
911 int_arm_neon_vrhaddu, 1>;
913 // Vector Saturating add (Integer Signed, Unsigned)
914 defm SQADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
915 int_arm_neon_vqadds, 1>;
916 defm UQADDvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
917 int_arm_neon_vqaddu, 1>;
919 // Vector Saturating sub (Integer Signed, Unsigned)
920 defm SQSUBvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
921 int_arm_neon_vqsubs, 1>;
922 defm UQSUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
923 int_arm_neon_vqsubu, 1>;
925 // Vector Shift Left (Signed and Unsigned Integer)
926 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
927 int_arm_neon_vshifts, 1>;
928 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
929 int_arm_neon_vshiftu, 1>;
931 // Vector Saturating Shift Left (Signed and Unsigned Integer)
932 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
933 int_arm_neon_vqshifts, 1>;
934 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
935 int_arm_neon_vqshiftu, 1>;
937 // Vector Rouding Shift Left (Signed and Unsigned Integer)
938 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
939 int_arm_neon_vrshifts, 1>;
940 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
941 int_arm_neon_vrshiftu, 1>;
943 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
944 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
945 int_arm_neon_vqrshifts, 1>;
946 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
947 int_arm_neon_vqrshiftu, 1>;
949 // Vector Maximum (Signed and Unsigned Integer)
950 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
951 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
953 // Vector Minimum (Signed and Unsigned Integer)
954 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
955 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
957 // Vector Maximum (Floating Point)
958 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
959 int_arm_neon_vmaxs, int_arm_neon_vmaxs,
960 int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
962 // Vector Minimum (Floating Point)
963 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
964 int_arm_neon_vmins, int_arm_neon_vmins,
965 int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
967 // Vector maxNum (Floating Point) - prefer a number over a quiet NaN)
968 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
969 int_aarch64_neon_vmaxnm,
970 int_aarch64_neon_vmaxnm,
971 int_aarch64_neon_vmaxnm,
972 v2f32, v4f32, v2f64, 1>;
974 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
975 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
976 int_aarch64_neon_vminnm,
977 int_aarch64_neon_vminnm,
978 int_aarch64_neon_vminnm,
979 v2f32, v4f32, v2f64, 1>;
981 // Vector Maximum Pairwise (Signed and Unsigned Integer)
982 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
983 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
985 // Vector Minimum Pairwise (Signed and Unsigned Integer)
986 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
987 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
989 // Vector Maximum Pairwise (Floating Point)
990 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
991 int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
992 int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
994 // Vector Minimum Pairwise (Floating Point)
995 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
996 int_arm_neon_vpmins, int_arm_neon_vpmins,
997 int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
999 // Vector maxNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
1000 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
1001 int_aarch64_neon_vpmaxnm,
1002 int_aarch64_neon_vpmaxnm,
1003 int_aarch64_neon_vpmaxnm,
1004 v2f32, v4f32, v2f64, 1>;
1006 // Vector minNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
1007 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
1008 int_aarch64_neon_vpminnm,
1009 int_aarch64_neon_vpminnm,
1010 int_aarch64_neon_vpminnm,
1011 v2f32, v4f32, v2f64, 1>;
1013 // Vector Addition Pairwise (Integer)
1014 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
1016 // Vector Addition Pairwise (Floating Point)
1017 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
1021 v2f32, v4f32, v2f64, 1>;
1023 // Vector Saturating Doubling Multiply High
1024 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
1025 int_arm_neon_vqdmulh, 1>;
1027 // Vector Saturating Rouding Doubling Multiply High
1028 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
1029 int_arm_neon_vqrdmulh, 1>;
1031 // Vector Multiply Extended (Floating Point)
1032 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
1033 int_aarch64_neon_vmulx,
1034 int_aarch64_neon_vmulx,
1035 int_aarch64_neon_vmulx,
1036 v2f32, v4f32, v2f64, 1>;
1038 // Patterns to match llvm.aarch64.* intrinsic for
1039 // ADDP, SMINP, UMINP, SMAXP, UMAXP having i32 as output
1040 class Neon_VectorPair_v2i32_pattern<SDPatternOperator opnode, Instruction INST>
1041 : Pat<(v1i32 (opnode (v2i32 VPR64:$Rn))),
1043 (v2i32 (INST (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rn))),
1046 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_sminv, SMINPvvv_2S>;
1047 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_uminv, UMINPvvv_2S>;
1048 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_smaxv, SMAXPvvv_2S>;
1049 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_umaxv, UMAXPvvv_2S>;
1050 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_vaddv, ADDP_2S>;
1052 // Vector Immediate Instructions
1054 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
1056 def _asmoperand : AsmOperandClass
1058 let Name = "NeonMovImmShift" # PREFIX;
1059 let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
1060 let PredicateMethod = "isNeonMovImmShift" # PREFIX;
1064 // Definition of vector immediates shift operands
1066 // The selectable use-cases extract the shift operation
1067 // information from the OpCmode fields encoded in the immediate.
1068 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
1069 uint64_t OpCmode = N->getZExtValue();
1071 unsigned ShiftOnesIn;
1073 A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1074 if (!HasShift) return SDValue();
1075 return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1078 // Vector immediates shift operands which accept LSL and MSL
1079 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1080 // or 0, 8 (LSLH) or 8, 16 (MSL).
1081 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1082 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1083 // LSLH restricts shift amount to 0, 8 out of 0, 8, 16, 24
1084 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1086 multiclass neon_mov_imm_shift_operands<string PREFIX,
1087 string HALF, string ISHALF, code pred>
1089 def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1092 "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1094 "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1095 let ParserMatchClass =
1096 !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1100 defm neon_mov_imm_LSL : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1102 unsigned ShiftOnesIn;
1104 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1105 return (HasShift && !ShiftOnesIn);
1108 defm neon_mov_imm_MSL : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1110 unsigned ShiftOnesIn;
1112 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1113 return (HasShift && ShiftOnesIn);
1116 defm neon_mov_imm_LSLH : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1118 unsigned ShiftOnesIn;
1120 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1121 return (HasShift && !ShiftOnesIn);
1124 def neon_uimm1_asmoperand : AsmOperandClass
1127 let PredicateMethod = "isUImm<1>";
1128 let RenderMethod = "addImmOperands";
1131 def neon_uimm2_asmoperand : AsmOperandClass
1134 let PredicateMethod = "isUImm<2>";
1135 let RenderMethod = "addImmOperands";
1138 def neon_uimm8_asmoperand : AsmOperandClass
1141 let PredicateMethod = "isUImm<8>";
1142 let RenderMethod = "addImmOperands";
1145 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1146 let ParserMatchClass = neon_uimm8_asmoperand;
1147 let PrintMethod = "printUImmHexOperand";
1150 def neon_uimm64_mask_asmoperand : AsmOperandClass
1152 let Name = "NeonUImm64Mask";
1153 let PredicateMethod = "isNeonUImm64Mask";
1154 let RenderMethod = "addNeonUImm64MaskOperands";
1157 // MCOperand for 64-bit bytemask with each byte having only the
1158 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1159 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1160 let ParserMatchClass = neon_uimm64_mask_asmoperand;
1161 let PrintMethod = "printNeonUImm64MaskOperand";
1164 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1165 SDPatternOperator opnode>
1167 // shift zeros, per word
1168 def _2S : NeonI_1VModImm<0b0, op,
1170 (ins neon_uimm8:$Imm,
1171 neon_mov_imm_LSL_operand:$Simm),
1172 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1173 [(set (v2i32 VPR64:$Rd),
1174 (v2i32 (opnode (timm:$Imm),
1175 (neon_mov_imm_LSL_operand:$Simm))))],
1178 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1181 def _4S : NeonI_1VModImm<0b1, op,
1183 (ins neon_uimm8:$Imm,
1184 neon_mov_imm_LSL_operand:$Simm),
1185 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1186 [(set (v4i32 VPR128:$Rd),
1187 (v4i32 (opnode (timm:$Imm),
1188 (neon_mov_imm_LSL_operand:$Simm))))],
1191 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1194 // shift zeros, per halfword
1195 def _4H : NeonI_1VModImm<0b0, op,
1197 (ins neon_uimm8:$Imm,
1198 neon_mov_imm_LSLH_operand:$Simm),
1199 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1200 [(set (v4i16 VPR64:$Rd),
1201 (v4i16 (opnode (timm:$Imm),
1202 (neon_mov_imm_LSLH_operand:$Simm))))],
1205 let cmode = {0b1, 0b0, Simm, 0b0};
1208 def _8H : NeonI_1VModImm<0b1, op,
1210 (ins neon_uimm8:$Imm,
1211 neon_mov_imm_LSLH_operand:$Simm),
1212 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1213 [(set (v8i16 VPR128:$Rd),
1214 (v8i16 (opnode (timm:$Imm),
1215 (neon_mov_imm_LSLH_operand:$Simm))))],
1218 let cmode = {0b1, 0b0, Simm, 0b0};
1222 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1223 SDPatternOperator opnode,
1224 SDPatternOperator neonopnode>
1226 let Constraints = "$src = $Rd" in {
1227 // shift zeros, per word
1228 def _2S : NeonI_1VModImm<0b0, op,
1230 (ins VPR64:$src, neon_uimm8:$Imm,
1231 neon_mov_imm_LSL_operand:$Simm),
1232 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1233 [(set (v2i32 VPR64:$Rd),
1234 (v2i32 (opnode (v2i32 VPR64:$src),
1235 (v2i32 (neonopnode timm:$Imm,
1236 neon_mov_imm_LSL_operand:$Simm)))))],
1239 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1242 def _4S : NeonI_1VModImm<0b1, op,
1244 (ins VPR128:$src, neon_uimm8:$Imm,
1245 neon_mov_imm_LSL_operand:$Simm),
1246 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1247 [(set (v4i32 VPR128:$Rd),
1248 (v4i32 (opnode (v4i32 VPR128:$src),
1249 (v4i32 (neonopnode timm:$Imm,
1250 neon_mov_imm_LSL_operand:$Simm)))))],
1253 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1256 // shift zeros, per halfword
1257 def _4H : NeonI_1VModImm<0b0, op,
1259 (ins VPR64:$src, neon_uimm8:$Imm,
1260 neon_mov_imm_LSLH_operand:$Simm),
1261 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1262 [(set (v4i16 VPR64:$Rd),
1263 (v4i16 (opnode (v4i16 VPR64:$src),
1264 (v4i16 (neonopnode timm:$Imm,
1265 neon_mov_imm_LSL_operand:$Simm)))))],
1268 let cmode = {0b1, 0b0, Simm, 0b1};
1271 def _8H : NeonI_1VModImm<0b1, op,
1273 (ins VPR128:$src, neon_uimm8:$Imm,
1274 neon_mov_imm_LSLH_operand:$Simm),
1275 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1276 [(set (v8i16 VPR128:$Rd),
1277 (v8i16 (opnode (v8i16 VPR128:$src),
1278 (v8i16 (neonopnode timm:$Imm,
1279 neon_mov_imm_LSL_operand:$Simm)))))],
1282 let cmode = {0b1, 0b0, Simm, 0b1};
1287 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1288 SDPatternOperator opnode>
1290 // shift ones, per word
1291 def _2S : NeonI_1VModImm<0b0, op,
1293 (ins neon_uimm8:$Imm,
1294 neon_mov_imm_MSL_operand:$Simm),
1295 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1296 [(set (v2i32 VPR64:$Rd),
1297 (v2i32 (opnode (timm:$Imm),
1298 (neon_mov_imm_MSL_operand:$Simm))))],
1301 let cmode = {0b1, 0b1, 0b0, Simm};
1304 def _4S : NeonI_1VModImm<0b1, op,
1306 (ins neon_uimm8:$Imm,
1307 neon_mov_imm_MSL_operand:$Simm),
1308 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1309 [(set (v4i32 VPR128:$Rd),
1310 (v4i32 (opnode (timm:$Imm),
1311 (neon_mov_imm_MSL_operand:$Simm))))],
1314 let cmode = {0b1, 0b1, 0b0, Simm};
1318 // Vector Move Immediate Shifted
1319 let isReMaterializable = 1 in {
1320 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1323 // Vector Move Inverted Immediate Shifted
1324 let isReMaterializable = 1 in {
1325 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1328 // Vector Bitwise Bit Clear (AND NOT) - immediate
1329 let isReMaterializable = 1 in {
1330 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1334 // Vector Bitwise OR - immedidate
1336 let isReMaterializable = 1 in {
1337 defm ORRvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1341 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1342 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1343 // BIC immediate instructions selection requires additional patterns to
1344 // transform Neon_movi operands into BIC immediate operands
1346 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1347 uint64_t OpCmode = N->getZExtValue();
1349 unsigned ShiftOnesIn;
1350 (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1351 // LSLH restricts shift amount to 0, 8 which are encoded as 0 and 1
1352 // Transform encoded shift amount 0 to 1 and 1 to 0.
1353 return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1356 def neon_mov_imm_LSLH_transform_operand
1359 unsigned ShiftOnesIn;
1361 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1362 return (HasShift && !ShiftOnesIn); }],
1363 neon_mov_imm_LSLH_transform_XFORM>;
1365 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0xff, LSL 8)
1366 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0xff)
1367 def : Pat<(v4i16 (and VPR64:$src,
1368 (v4i16 (Neon_movi 255,
1369 neon_mov_imm_LSLH_transform_operand:$Simm)))),
1370 (BICvi_lsl_4H VPR64:$src, 255,
1371 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1373 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0xff, LSL 8)
1374 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0xff)
1375 def : Pat<(v8i16 (and VPR128:$src,
1376 (v8i16 (Neon_movi 255,
1377 neon_mov_imm_LSLH_transform_operand:$Simm)))),
1378 (BICvi_lsl_8H VPR128:$src, 255,
1379 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1381 def : Pat<(v8i8 (and VPR64:$src,
1382 (bitconvert(v4i16 (Neon_movi 255,
1383 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1384 (BICvi_lsl_4H VPR64:$src, 255,
1385 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1386 def : Pat<(v2i32 (and VPR64:$src,
1387 (bitconvert(v4i16 (Neon_movi 255,
1388 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1389 (BICvi_lsl_4H VPR64:$src, 255,
1390 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1391 def : Pat<(v1i64 (and VPR64:$src,
1392 (bitconvert(v4i16 (Neon_movi 255,
1393 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1394 (BICvi_lsl_4H VPR64:$src, 255,
1395 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1397 def : Pat<(v16i8 (and VPR128:$src,
1398 (bitconvert(v8i16 (Neon_movi 255,
1399 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1400 (BICvi_lsl_8H VPR128:$src, 255,
1401 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1402 def : Pat<(v4i32 (and VPR128:$src,
1403 (bitconvert(v8i16 (Neon_movi 255,
1404 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1405 (BICvi_lsl_8H VPR128:$src, 255,
1406 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1407 def : Pat<(v2i64 (and VPR128:$src,
1408 (bitconvert(v8i16 (Neon_movi 255,
1409 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1410 (BICvi_lsl_8H VPR128:$src, 255,
1411 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1413 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1414 SDPatternOperator neonopnode,
1418 Instruction INST4S> {
1419 def : Pat<(v8i8 (opnode VPR64:$src,
1420 (bitconvert(v4i16 (neonopnode timm:$Imm,
1421 neon_mov_imm_LSLH_operand:$Simm))))),
1422 (INST4H VPR64:$src, neon_uimm8:$Imm,
1423 neon_mov_imm_LSLH_operand:$Simm)>;
1424 def : Pat<(v2i32 (opnode VPR64:$src,
1425 (bitconvert(v4i16 (neonopnode timm:$Imm,
1426 neon_mov_imm_LSLH_operand:$Simm))))),
1427 (INST4H VPR64:$src, neon_uimm8:$Imm,
1428 neon_mov_imm_LSLH_operand:$Simm)>;
1429 def : Pat<(v1i64 (opnode VPR64:$src,
1430 (bitconvert(v4i16 (neonopnode timm:$Imm,
1431 neon_mov_imm_LSLH_operand:$Simm))))),
1432 (INST4H VPR64:$src, neon_uimm8:$Imm,
1433 neon_mov_imm_LSLH_operand:$Simm)>;
1435 def : Pat<(v16i8 (opnode VPR128:$src,
1436 (bitconvert(v8i16 (neonopnode timm:$Imm,
1437 neon_mov_imm_LSLH_operand:$Simm))))),
1438 (INST8H VPR128:$src, neon_uimm8:$Imm,
1439 neon_mov_imm_LSLH_operand:$Simm)>;
1440 def : Pat<(v4i32 (opnode VPR128:$src,
1441 (bitconvert(v8i16 (neonopnode timm:$Imm,
1442 neon_mov_imm_LSLH_operand:$Simm))))),
1443 (INST8H VPR128:$src, neon_uimm8:$Imm,
1444 neon_mov_imm_LSLH_operand:$Simm)>;
1445 def : Pat<(v2i64 (opnode VPR128:$src,
1446 (bitconvert(v8i16 (neonopnode timm:$Imm,
1447 neon_mov_imm_LSLH_operand:$Simm))))),
1448 (INST8H VPR128:$src, neon_uimm8:$Imm,
1449 neon_mov_imm_LSLH_operand:$Simm)>;
1451 def : Pat<(v8i8 (opnode VPR64:$src,
1452 (bitconvert(v2i32 (neonopnode timm:$Imm,
1453 neon_mov_imm_LSLH_operand:$Simm))))),
1454 (INST2S VPR64:$src, neon_uimm8:$Imm,
1455 neon_mov_imm_LSLH_operand:$Simm)>;
1456 def : Pat<(v4i16 (opnode VPR64:$src,
1457 (bitconvert(v2i32 (neonopnode timm:$Imm,
1458 neon_mov_imm_LSLH_operand:$Simm))))),
1459 (INST2S VPR64:$src, neon_uimm8:$Imm,
1460 neon_mov_imm_LSLH_operand:$Simm)>;
1461 def : Pat<(v1i64 (opnode VPR64:$src,
1462 (bitconvert(v2i32 (neonopnode timm:$Imm,
1463 neon_mov_imm_LSLH_operand:$Simm))))),
1464 (INST2S VPR64:$src, neon_uimm8:$Imm,
1465 neon_mov_imm_LSLH_operand:$Simm)>;
1467 def : Pat<(v16i8 (opnode VPR128:$src,
1468 (bitconvert(v4i32 (neonopnode timm:$Imm,
1469 neon_mov_imm_LSLH_operand:$Simm))))),
1470 (INST4S VPR128:$src, neon_uimm8:$Imm,
1471 neon_mov_imm_LSLH_operand:$Simm)>;
1472 def : Pat<(v8i16 (opnode VPR128:$src,
1473 (bitconvert(v4i32 (neonopnode timm:$Imm,
1474 neon_mov_imm_LSLH_operand:$Simm))))),
1475 (INST4S VPR128:$src, neon_uimm8:$Imm,
1476 neon_mov_imm_LSLH_operand:$Simm)>;
1477 def : Pat<(v2i64 (opnode VPR128:$src,
1478 (bitconvert(v4i32 (neonopnode timm:$Imm,
1479 neon_mov_imm_LSLH_operand:$Simm))))),
1480 (INST4S VPR128:$src, neon_uimm8:$Imm,
1481 neon_mov_imm_LSLH_operand:$Simm)>;
1484 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1485 defm : Neon_bitwiseVi_patterns<and, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H,
1486 BICvi_lsl_2S, BICvi_lsl_4S>;
1488 // Additional patterns for Vector Bitwise OR - immedidate
1489 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H,
1490 ORRvi_lsl_2S, ORRvi_lsl_4S>;
1493 // Vector Move Immediate Masked
1494 let isReMaterializable = 1 in {
1495 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1498 // Vector Move Inverted Immediate Masked
1499 let isReMaterializable = 1 in {
1500 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1503 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1504 Instruction inst, RegisterOperand VPRC>
1505 : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1506 (inst VPRC:$Rd, neon_uimm8:$Imm, 0), 0b0>;
1508 // Aliases for Vector Move Immediate Shifted
1509 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1510 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1511 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1512 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1514 // Aliases for Vector Move Inverted Immediate Shifted
1515 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1516 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1517 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1518 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1520 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1521 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1522 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1523 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1524 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1526 // Aliases for Vector Bitwise OR - immedidate
1527 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1528 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1529 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1530 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1532 // Vector Move Immediate - per byte
1533 let isReMaterializable = 1 in {
1534 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1535 (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1536 "movi\t$Rd.8b, $Imm",
1537 [(set (v8i8 VPR64:$Rd),
1538 (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1543 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1544 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1545 "movi\t$Rd.16b, $Imm",
1546 [(set (v16i8 VPR128:$Rd),
1547 (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1553 // Vector Move Immediate - bytemask, per double word
1554 let isReMaterializable = 1 in {
1555 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1556 (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1557 "movi\t $Rd.2d, $Imm",
1558 [(set (v2i64 VPR128:$Rd),
1559 (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1565 // Vector Move Immediate - bytemask, one doubleword
1567 let isReMaterializable = 1 in {
1568 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1569 (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1571 [(set (v1i64 FPR64:$Rd),
1572 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1578 // Vector Floating Point Move Immediate
1580 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1581 Operand immOpType, bit q, bit op>
1582 : NeonI_1VModImm<q, op,
1583 (outs VPRC:$Rd), (ins immOpType:$Imm),
1584 "fmov\t$Rd" # asmlane # ", $Imm",
1585 [(set (OpTy VPRC:$Rd),
1586 (OpTy (Neon_fmovi (timm:$Imm))))],
1591 let isReMaterializable = 1 in {
1592 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64, v2f32, fmov32_operand, 0b0, 0b0>;
1593 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1594 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1597 // Vector Shift (Immediate)
1598 // Immediate in [0, 63]
1599 def imm0_63 : Operand<i32> {
1600 let ParserMatchClass = uimm6_asmoperand;
1603 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1607 // 8 immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1608 // 16 immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1609 // 32 immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1610 // 64 immh:immb<6> = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1612 // The shift right immediate amount, in the range 1 to element bits, is computed
1613 // as Offset - UInt(immh:immb). The shift left immediate amount, in the range 0
1614 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1616 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1617 let Name = "ShrImm" # OFFSET;
1618 let RenderMethod = "addImmOperands";
1619 let DiagnosticType = "ShrImm" # OFFSET;
1622 class shr_imm<string OFFSET> : Operand<i32> {
1623 let EncoderMethod = "getShiftRightImm" # OFFSET;
1624 let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1625 let ParserMatchClass =
1626 !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1629 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1630 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1631 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1632 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1634 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1635 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1636 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1637 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1639 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1640 let Name = "ShlImm" # OFFSET;
1641 let RenderMethod = "addImmOperands";
1642 let DiagnosticType = "ShlImm" # OFFSET;
1645 class shl_imm<string OFFSET> : Operand<i32> {
1646 let EncoderMethod = "getShiftLeftImm" # OFFSET;
1647 let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1648 let ParserMatchClass =
1649 !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1652 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1653 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1654 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1655 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1657 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1658 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1659 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1660 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1662 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1663 RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1664 : NeonI_2VShiftImm<q, u, opcode,
1665 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1666 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1667 [(set (Ty VPRC:$Rd),
1668 (Ty (OpNode (Ty VPRC:$Rn),
1669 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1672 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1673 // 64-bit vector types.
1674 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1675 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1678 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1679 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1682 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1683 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1686 // 128-bit vector types.
1687 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1688 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1691 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1692 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1695 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1696 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1699 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1700 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
1704 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1705 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1707 let Inst{22-19} = 0b0001;
1710 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1712 let Inst{22-20} = 0b001;
1715 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1717 let Inst{22-21} = 0b01;
1720 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1722 let Inst{22-19} = 0b0001;
1725 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1727 let Inst{22-20} = 0b001;
1730 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1732 let Inst{22-21} = 0b01;
1735 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1742 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1745 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1746 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1748 def Neon_High16B : PatFrag<(ops node:$in),
1749 (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1750 def Neon_High8H : PatFrag<(ops node:$in),
1751 (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1752 def Neon_High4S : PatFrag<(ops node:$in),
1753 (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1754 def Neon_High2D : PatFrag<(ops node:$in),
1755 (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1756 def Neon_High4float : PatFrag<(ops node:$in),
1757 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1758 def Neon_High2double : PatFrag<(ops node:$in),
1759 (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1761 def Neon_Low16B : PatFrag<(ops node:$in),
1762 (v8i8 (extract_subvector (v16i8 node:$in),
1764 def Neon_Low8H : PatFrag<(ops node:$in),
1765 (v4i16 (extract_subvector (v8i16 node:$in),
1767 def Neon_Low4S : PatFrag<(ops node:$in),
1768 (v2i32 (extract_subvector (v4i32 node:$in),
1770 def Neon_Low2D : PatFrag<(ops node:$in),
1771 (v1i64 (extract_subvector (v2i64 node:$in),
1773 def Neon_Low4float : PatFrag<(ops node:$in),
1774 (v2f32 (extract_subvector (v4f32 node:$in),
1776 def Neon_Low2double : PatFrag<(ops node:$in),
1777 (v1f64 (extract_subvector (v2f64 node:$in),
1780 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1781 string SrcT, ValueType DestTy, ValueType SrcTy,
1782 Operand ImmTy, SDPatternOperator ExtOp>
1783 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1784 (ins VPR64:$Rn, ImmTy:$Imm),
1785 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1786 [(set (DestTy VPR128:$Rd),
1788 (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1789 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1792 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1793 string SrcT, ValueType DestTy, ValueType SrcTy,
1794 int StartIndex, Operand ImmTy,
1795 SDPatternOperator ExtOp, PatFrag getTop>
1796 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1797 (ins VPR128:$Rn, ImmTy:$Imm),
1798 asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1799 [(set (DestTy VPR128:$Rd),
1802 (SrcTy (getTop VPR128:$Rn)))),
1803 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1806 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1808 // 64-bit vector types.
1809 def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1811 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1814 def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1816 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1819 def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1821 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1824 // 128-bit vector types
1825 def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1826 8, shl_imm8, ExtOp, Neon_High16B> {
1827 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1830 def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1831 4, shl_imm16, ExtOp, Neon_High8H> {
1832 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1835 def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1836 2, shl_imm32, ExtOp, Neon_High4S> {
1837 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1840 // Use other patterns to match when the immediate is 0.
1841 def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1842 (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1844 def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1845 (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1847 def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1848 (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1850 def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1851 (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1853 def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1854 (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1856 def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1857 (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1861 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1862 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1864 class NeonI_ext_len_alias<string asmop, string lane, string laneOp,
1865 Instruction inst, RegisterOperand VPRC,
1866 RegisterOperand VPRCOp>
1867 : NeonInstAlias<asmop # "\t$Rd" # lane #", $Rn" # laneOp,
1868 (inst VPRC:$Rd, VPRCOp:$Rn, 0), 0b0>;
1870 // Signed integer lengthen (vector) is alias for SSHLL Vd, Vn, #0
1871 // Signed integer lengthen (vector, second part) is alias for SSHLL2 Vd, Vn, #0
1872 // FIXME: This is actually the preferred syntax but TableGen can't deal with
1873 // custom printing of aliases.
1874 def SXTLvv_8B : NeonI_ext_len_alias<"sxtl", ".8h", ".8b", SSHLLvvi_8B, VPR128, VPR64>;
1875 def SXTLvv_4H : NeonI_ext_len_alias<"sxtl", ".4s", ".4h", SSHLLvvi_4H, VPR128, VPR64>;
1876 def SXTLvv_2S : NeonI_ext_len_alias<"sxtl", ".2d", ".2s", SSHLLvvi_2S, VPR128, VPR64>;
1877 def SXTL2vv_16B : NeonI_ext_len_alias<"sxtl2", ".8h", ".16b", SSHLLvvi_16B, VPR128, VPR128>;
1878 def SXTL2vv_8H : NeonI_ext_len_alias<"sxtl2", ".4s", ".8h", SSHLLvvi_8H, VPR128, VPR128>;
1879 def SXTL2vv_4S : NeonI_ext_len_alias<"sxtl2", ".2d", ".4s", SSHLLvvi_4S, VPR128, VPR128>;
1881 // Unsigned integer lengthen (vector) is alias for USHLL Vd, Vn, #0
1882 // Unsigned integer lengthen (vector, second part) is alias for USHLL2 Vd, Vn, #0
1883 // FIXME: This is actually the preferred syntax but TableGen can't deal with
1884 // custom printing of aliases.
1885 def UXTLvv_8B : NeonI_ext_len_alias<"uxtl", ".8h", ".8b", USHLLvvi_8B, VPR128, VPR64>;
1886 def UXTLvv_4H : NeonI_ext_len_alias<"uxtl", ".4s", ".4h", USHLLvvi_4H, VPR128, VPR64>;
1887 def UXTLvv_2S : NeonI_ext_len_alias<"uxtl", ".2d", ".2s", USHLLvvi_2S, VPR128, VPR64>;
1888 def UXTL2vv_16B : NeonI_ext_len_alias<"uxtl2", ".8h", ".16b", USHLLvvi_16B, VPR128, VPR128>;
1889 def UXTL2vv_8H : NeonI_ext_len_alias<"uxtl2", ".4s", ".8h", USHLLvvi_8H, VPR128, VPR128>;
1890 def UXTL2vv_4S : NeonI_ext_len_alias<"uxtl2", ".2d", ".4s", USHLLvvi_4S, VPR128, VPR128>;
1892 def : Pat<(v8i16 (anyext (v8i8 VPR64:$Rn))), (USHLLvvi_8B VPR64:$Rn, 0)>;
1893 def : Pat<(v4i32 (anyext (v4i16 VPR64:$Rn))), (USHLLvvi_4H VPR64:$Rn, 0)>;
1894 def : Pat<(v2i64 (anyext (v2i32 VPR64:$Rn))), (USHLLvvi_2S VPR64:$Rn, 0)>;
1896 // Rounding/Saturating shift
1897 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1898 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1899 SDPatternOperator OpNode>
1900 : NeonI_2VShiftImm<q, u, opcode,
1901 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1902 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1903 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1904 (i32 ImmTy:$Imm))))],
1907 // shift right (vector by immediate)
1908 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1909 SDPatternOperator OpNode> {
1910 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1912 let Inst{22-19} = 0b0001;
1915 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1917 let Inst{22-20} = 0b001;
1920 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1922 let Inst{22-21} = 0b01;
1925 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1927 let Inst{22-19} = 0b0001;
1930 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1932 let Inst{22-20} = 0b001;
1935 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1937 let Inst{22-21} = 0b01;
1940 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1946 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1947 SDPatternOperator OpNode> {
1948 // 64-bit vector types.
1949 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1951 let Inst{22-19} = 0b0001;
1954 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1956 let Inst{22-20} = 0b001;
1959 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1961 let Inst{22-21} = 0b01;
1964 // 128-bit vector types.
1965 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1967 let Inst{22-19} = 0b0001;
1970 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1972 let Inst{22-20} = 0b001;
1975 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1977 let Inst{22-21} = 0b01;
1980 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1986 // Rounding shift right
1987 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1988 int_aarch64_neon_vsrshr>;
1989 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1990 int_aarch64_neon_vurshr>;
1992 // Saturating shift left unsigned
1993 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1995 // Saturating shift left
1996 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1997 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1999 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
2000 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2002 : NeonI_2VShiftImm<q, u, opcode,
2003 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2004 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2005 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
2006 (Ty (OpNode (Ty VPRC:$Rn),
2007 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
2009 let Constraints = "$src = $Rd";
2012 // Shift Right accumulate
2013 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
2014 def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2016 let Inst{22-19} = 0b0001;
2019 def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2021 let Inst{22-20} = 0b001;
2024 def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2026 let Inst{22-21} = 0b01;
2029 def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2031 let Inst{22-19} = 0b0001;
2034 def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2036 let Inst{22-20} = 0b001;
2039 def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2041 let Inst{22-21} = 0b01;
2044 def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2050 // Shift right and accumulate
2051 defm SSRAvvi : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
2052 defm USRAvvi : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
2054 // Rounding shift accumulate
2055 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
2056 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2057 SDPatternOperator OpNode>
2058 : NeonI_2VShiftImm<q, u, opcode,
2059 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2060 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2061 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
2062 (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
2064 let Constraints = "$src = $Rd";
2067 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
2068 SDPatternOperator OpNode> {
2069 def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2071 let Inst{22-19} = 0b0001;
2074 def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2076 let Inst{22-20} = 0b001;
2079 def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2081 let Inst{22-21} = 0b01;
2084 def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2086 let Inst{22-19} = 0b0001;
2089 def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2091 let Inst{22-20} = 0b001;
2094 def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2096 let Inst{22-21} = 0b01;
2099 def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2105 // Rounding shift right and accumulate
2106 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
2107 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
2109 // Shift insert by immediate
2110 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
2111 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2112 SDPatternOperator OpNode>
2113 : NeonI_2VShiftImm<q, u, opcode,
2114 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2115 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2116 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
2117 (i32 ImmTy:$Imm))))],
2119 let Constraints = "$src = $Rd";
2122 // shift left insert (vector by immediate)
2123 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
2124 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
2125 int_aarch64_neon_vsli> {
2126 let Inst{22-19} = 0b0001;
2129 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
2130 int_aarch64_neon_vsli> {
2131 let Inst{22-20} = 0b001;
2134 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
2135 int_aarch64_neon_vsli> {
2136 let Inst{22-21} = 0b01;
2139 // 128-bit vector types
2140 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
2141 int_aarch64_neon_vsli> {
2142 let Inst{22-19} = 0b0001;
2145 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
2146 int_aarch64_neon_vsli> {
2147 let Inst{22-20} = 0b001;
2150 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
2151 int_aarch64_neon_vsli> {
2152 let Inst{22-21} = 0b01;
2155 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
2156 int_aarch64_neon_vsli> {
2161 // shift right insert (vector by immediate)
2162 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
2163 // 64-bit vector types.
2164 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2165 int_aarch64_neon_vsri> {
2166 let Inst{22-19} = 0b0001;
2169 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2170 int_aarch64_neon_vsri> {
2171 let Inst{22-20} = 0b001;
2174 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2175 int_aarch64_neon_vsri> {
2176 let Inst{22-21} = 0b01;
2179 // 128-bit vector types
2180 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2181 int_aarch64_neon_vsri> {
2182 let Inst{22-19} = 0b0001;
2185 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2186 int_aarch64_neon_vsri> {
2187 let Inst{22-20} = 0b001;
2190 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2191 int_aarch64_neon_vsri> {
2192 let Inst{22-21} = 0b01;
2195 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2196 int_aarch64_neon_vsri> {
2201 // Shift left and insert
2202 defm SLIvvi : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2204 // Shift right and insert
2205 defm SRIvvi : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2207 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2208 string SrcT, Operand ImmTy>
2209 : NeonI_2VShiftImm<q, u, opcode,
2210 (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2211 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2214 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2215 string SrcT, Operand ImmTy>
2216 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2217 (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2218 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2220 let Constraints = "$src = $Rd";
2223 // left long shift by immediate
2224 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2225 def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2226 let Inst{22-19} = 0b0001;
2229 def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2230 let Inst{22-20} = 0b001;
2233 def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2234 let Inst{22-21} = 0b01;
2237 // Shift Narrow High
2238 def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2240 let Inst{22-19} = 0b0001;
2243 def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2245 let Inst{22-20} = 0b001;
2248 def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2250 let Inst{22-21} = 0b01;
2254 // Shift right narrow
2255 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2257 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2258 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2259 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2260 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2261 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2262 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2263 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2264 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2266 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2267 (v2i64 (concat_vectors (v1i64 node:$Rm),
2268 (v1i64 node:$Rn)))>;
2269 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2270 (v8i16 (concat_vectors (v4i16 node:$Rm),
2271 (v4i16 node:$Rn)))>;
2272 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2273 (v4i32 (concat_vectors (v2i32 node:$Rm),
2274 (v2i32 node:$Rn)))>;
2275 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2276 (v4f32 (concat_vectors (v2f32 node:$Rm),
2277 (v2f32 node:$Rn)))>;
2278 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2279 (v2f64 (concat_vectors (v1f64 node:$Rm),
2280 (v1f64 node:$Rn)))>;
2282 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2283 (v8i16 (srl (v8i16 node:$lhs),
2284 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2285 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2286 (v4i32 (srl (v4i32 node:$lhs),
2287 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2288 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2289 (v2i64 (srl (v2i64 node:$lhs),
2290 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2291 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2292 (v8i16 (sra (v8i16 node:$lhs),
2293 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2294 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2295 (v4i32 (sra (v4i32 node:$lhs),
2296 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2297 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2298 (v2i64 (sra (v2i64 node:$lhs),
2299 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2301 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2302 multiclass Neon_shiftNarrow_patterns<string shr> {
2303 def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2304 (i32 shr_imm8:$Imm)))),
2305 (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2306 def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2307 (i32 shr_imm16:$Imm)))),
2308 (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2309 def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2310 (i32 shr_imm32:$Imm)))),
2311 (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2313 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2314 (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2315 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2316 (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2317 VPR128:$Rn, imm:$Imm)>;
2318 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2319 (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2320 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2321 (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2322 VPR128:$Rn, imm:$Imm)>;
2323 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2324 (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2325 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2326 (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2327 VPR128:$Rn, imm:$Imm)>;
2330 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2331 def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2332 (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2333 def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2334 (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2335 def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2336 (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2338 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2339 (v1i64 (bitconvert (v8i8
2340 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2341 (!cast<Instruction>(prefix # "_16B")
2342 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2343 VPR128:$Rn, imm:$Imm)>;
2344 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2345 (v1i64 (bitconvert (v4i16
2346 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2347 (!cast<Instruction>(prefix # "_8H")
2348 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2349 VPR128:$Rn, imm:$Imm)>;
2350 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2351 (v1i64 (bitconvert (v2i32
2352 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2353 (!cast<Instruction>(prefix # "_4S")
2354 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2355 VPR128:$Rn, imm:$Imm)>;
2358 defm : Neon_shiftNarrow_patterns<"lshr">;
2359 defm : Neon_shiftNarrow_patterns<"ashr">;
2361 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2362 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2363 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2364 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2365 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2366 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2367 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2369 // Convert fix-point and float-pointing
2370 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2371 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2372 Operand ImmTy, SDPatternOperator IntOp>
2373 : NeonI_2VShiftImm<q, u, opcode,
2374 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2375 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2376 [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2377 (i32 ImmTy:$Imm))))],
2380 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2381 SDPatternOperator IntOp> {
2382 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2384 let Inst{22-21} = 0b01;
2387 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2389 let Inst{22-21} = 0b01;
2392 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2398 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2399 SDPatternOperator IntOp> {
2400 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2402 let Inst{22-21} = 0b01;
2405 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2407 let Inst{22-21} = 0b01;
2410 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2416 // Convert fixed-point to floating-point
2417 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2418 int_arm_neon_vcvtfxs2fp>;
2419 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2420 int_arm_neon_vcvtfxu2fp>;
2422 // Convert floating-point to fixed-point
2423 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2424 int_arm_neon_vcvtfp2fxs>;
2425 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2426 int_arm_neon_vcvtfp2fxu>;
2428 multiclass Neon_sshll2_0<SDNode ext>
2430 def _v8i8 : PatFrag<(ops node:$Rn),
2431 (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2432 def _v4i16 : PatFrag<(ops node:$Rn),
2433 (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2434 def _v2i32 : PatFrag<(ops node:$Rn),
2435 (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2438 defm NI_sext_high : Neon_sshll2_0<sext>;
2439 defm NI_zext_high : Neon_sshll2_0<zext>;
2442 //===----------------------------------------------------------------------===//
2443 // Multiclasses for NeonI_Across
2444 //===----------------------------------------------------------------------===//
2448 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2449 string asmop, SDPatternOperator opnode>
2451 def _1h8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2452 (outs FPR16:$Rd), (ins VPR64:$Rn),
2453 asmop # "\t$Rd, $Rn.8b",
2454 [(set (v1i16 FPR16:$Rd),
2455 (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2458 def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2459 (outs FPR16:$Rd), (ins VPR128:$Rn),
2460 asmop # "\t$Rd, $Rn.16b",
2461 [(set (v1i16 FPR16:$Rd),
2462 (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2465 def _1s4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2466 (outs FPR32:$Rd), (ins VPR64:$Rn),
2467 asmop # "\t$Rd, $Rn.4h",
2468 [(set (v1i32 FPR32:$Rd),
2469 (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2472 def _1s8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2473 (outs FPR32:$Rd), (ins VPR128:$Rn),
2474 asmop # "\t$Rd, $Rn.8h",
2475 [(set (v1i32 FPR32:$Rd),
2476 (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2479 // _1d2s doesn't exist!
2481 def _1d4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2482 (outs FPR64:$Rd), (ins VPR128:$Rn),
2483 asmop # "\t$Rd, $Rn.4s",
2484 [(set (v1i64 FPR64:$Rd),
2485 (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2489 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2490 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2494 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2495 string asmop, SDPatternOperator opnode>
2497 def _1b8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2498 (outs FPR8:$Rd), (ins VPR64:$Rn),
2499 asmop # "\t$Rd, $Rn.8b",
2500 [(set (v1i8 FPR8:$Rd),
2501 (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2504 def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2505 (outs FPR8:$Rd), (ins VPR128:$Rn),
2506 asmop # "\t$Rd, $Rn.16b",
2507 [(set (v1i8 FPR8:$Rd),
2508 (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2511 def _1h4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2512 (outs FPR16:$Rd), (ins VPR64:$Rn),
2513 asmop # "\t$Rd, $Rn.4h",
2514 [(set (v1i16 FPR16:$Rd),
2515 (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2518 def _1h8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2519 (outs FPR16:$Rd), (ins VPR128:$Rn),
2520 asmop # "\t$Rd, $Rn.8h",
2521 [(set (v1i16 FPR16:$Rd),
2522 (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2525 // _1s2s doesn't exist!
2527 def _1s4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2528 (outs FPR32:$Rd), (ins VPR128:$Rn),
2529 asmop # "\t$Rd, $Rn.4s",
2530 [(set (v1i32 FPR32:$Rd),
2531 (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2535 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2536 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2538 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2539 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2541 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2545 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2546 string asmop, SDPatternOperator opnode> {
2547 def _1s4s: NeonI_2VAcross<0b1, u, size, opcode,
2548 (outs FPR32:$Rd), (ins VPR128:$Rn),
2549 asmop # "\t$Rd, $Rn.4s",
2550 [(set (f32 FPR32:$Rd),
2551 (f32 (opnode (v4f32 VPR128:$Rn))))],
2555 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2556 int_aarch64_neon_vmaxnmv>;
2557 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2558 int_aarch64_neon_vminnmv>;
2560 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2561 int_aarch64_neon_vmaxv>;
2562 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2563 int_aarch64_neon_vminv>;
2565 // The followings are for instruction class (Perm)
2567 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2568 string asmop, RegisterOperand OpVPR, string OpS,
2569 SDPatternOperator opnode, ValueType Ty>
2570 : NeonI_Perm<q, size, opcode,
2571 (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2572 asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2573 [(set (Ty OpVPR:$Rd),
2574 (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2577 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2578 SDPatternOperator opnode> {
2579 def _8b : NeonI_Permute<0b0, 0b00, opcode, asmop,
2580 VPR64, "8b", opnode, v8i8>;
2581 def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2582 VPR128, "16b",opnode, v16i8>;
2583 def _4h : NeonI_Permute<0b0, 0b01, opcode, asmop,
2584 VPR64, "4h", opnode, v4i16>;
2585 def _8h : NeonI_Permute<0b1, 0b01, opcode, asmop,
2586 VPR128, "8h", opnode, v8i16>;
2587 def _2s : NeonI_Permute<0b0, 0b10, opcode, asmop,
2588 VPR64, "2s", opnode, v2i32>;
2589 def _4s : NeonI_Permute<0b1, 0b10, opcode, asmop,
2590 VPR128, "4s", opnode, v4i32>;
2591 def _2d : NeonI_Permute<0b1, 0b11, opcode, asmop,
2592 VPR128, "2d", opnode, v2i64>;
2595 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2596 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2597 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2598 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2599 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2600 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2602 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2603 def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2604 (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2606 def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2607 (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2609 def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2610 (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2613 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2614 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2615 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2616 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2617 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2618 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2620 // The followings are for instruction class (3V Diff)
2622 // normal long/long2 pattern
2623 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2624 string asmop, string ResS, string OpS,
2625 SDPatternOperator opnode, SDPatternOperator ext,
2626 RegisterOperand OpVPR,
2627 ValueType ResTy, ValueType OpTy>
2628 : NeonI_3VDiff<q, u, size, opcode,
2629 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2630 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2631 [(set (ResTy VPR128:$Rd),
2632 (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2633 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2636 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2637 string asmop, SDPatternOperator opnode,
2638 bit Commutable = 0> {
2639 let isCommutable = Commutable in {
2640 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2641 opnode, sext, VPR64, v8i16, v8i8>;
2642 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2643 opnode, sext, VPR64, v4i32, v4i16>;
2644 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2645 opnode, sext, VPR64, v2i64, v2i32>;
2649 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2650 SDPatternOperator opnode, bit Commutable = 0> {
2651 let isCommutable = Commutable in {
2652 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2653 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2654 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2655 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2656 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2657 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2661 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2662 SDPatternOperator opnode, bit Commutable = 0> {
2663 let isCommutable = Commutable in {
2664 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2665 opnode, zext, VPR64, v8i16, v8i8>;
2666 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2667 opnode, zext, VPR64, v4i32, v4i16>;
2668 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2669 opnode, zext, VPR64, v2i64, v2i32>;
2673 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2674 SDPatternOperator opnode, bit Commutable = 0> {
2675 let isCommutable = Commutable in {
2676 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2677 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2678 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2679 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2680 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2681 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2685 defm SADDLvvv : NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2686 defm UADDLvvv : NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2688 defm SADDL2vvv : NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2689 defm UADDL2vvv : NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2691 defm SSUBLvvv : NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2692 defm USUBLvvv : NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2694 defm SSUBL2vvv : NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2695 defm USUBL2vvv : NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2697 // normal wide/wide2 pattern
2698 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2699 string asmop, string ResS, string OpS,
2700 SDPatternOperator opnode, SDPatternOperator ext,
2701 RegisterOperand OpVPR,
2702 ValueType ResTy, ValueType OpTy>
2703 : NeonI_3VDiff<q, u, size, opcode,
2704 (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2705 asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2706 [(set (ResTy VPR128:$Rd),
2707 (ResTy (opnode (ResTy VPR128:$Rn),
2708 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2711 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2712 SDPatternOperator opnode> {
2713 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2714 opnode, sext, VPR64, v8i16, v8i8>;
2715 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2716 opnode, sext, VPR64, v4i32, v4i16>;
2717 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2718 opnode, sext, VPR64, v2i64, v2i32>;
2721 defm SADDWvvv : NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2722 defm SSUBWvvv : NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2724 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2725 SDPatternOperator opnode> {
2726 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2727 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2728 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2729 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2730 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2731 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2734 defm SADDW2vvv : NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2735 defm SSUBW2vvv : NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2737 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2738 SDPatternOperator opnode> {
2739 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2740 opnode, zext, VPR64, v8i16, v8i8>;
2741 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2742 opnode, zext, VPR64, v4i32, v4i16>;
2743 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2744 opnode, zext, VPR64, v2i64, v2i32>;
2747 defm UADDWvvv : NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2748 defm USUBWvvv : NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2750 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2751 SDPatternOperator opnode> {
2752 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2753 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2754 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2755 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2756 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2757 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2760 defm UADDW2vvv : NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2761 defm USUBW2vvv : NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2763 // Get the high half part of the vector element.
2764 multiclass NeonI_get_high {
2765 def _8h : PatFrag<(ops node:$Rn),
2766 (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2767 (v8i16 (Neon_vdup (i32 8)))))))>;
2768 def _4s : PatFrag<(ops node:$Rn),
2769 (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2770 (v4i32 (Neon_vdup (i32 16)))))))>;
2771 def _2d : PatFrag<(ops node:$Rn),
2772 (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2773 (v2i64 (Neon_vdup (i32 32)))))))>;
2776 defm NI_get_hi : NeonI_get_high;
2778 // pattern for addhn/subhn with 2 operands
2779 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2780 string asmop, string ResS, string OpS,
2781 SDPatternOperator opnode, SDPatternOperator get_hi,
2782 ValueType ResTy, ValueType OpTy>
2783 : NeonI_3VDiff<q, u, size, opcode,
2784 (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2785 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2786 [(set (ResTy VPR64:$Rd),
2788 (OpTy (opnode (OpTy VPR128:$Rn),
2789 (OpTy VPR128:$Rm))))))],
2792 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2793 SDPatternOperator opnode, bit Commutable = 0> {
2794 let isCommutable = Commutable in {
2795 def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2796 opnode, NI_get_hi_8h, v8i8, v8i16>;
2797 def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2798 opnode, NI_get_hi_4s, v4i16, v4i32>;
2799 def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2800 opnode, NI_get_hi_2d, v2i32, v2i64>;
2804 defm ADDHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2805 defm SUBHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2807 // pattern for operation with 2 operands
2808 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2809 string asmop, string ResS, string OpS,
2810 SDPatternOperator opnode,
2811 RegisterOperand ResVPR, RegisterOperand OpVPR,
2812 ValueType ResTy, ValueType OpTy>
2813 : NeonI_3VDiff<q, u, size, opcode,
2814 (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2815 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2816 [(set (ResTy ResVPR:$Rd),
2817 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2820 // normal narrow pattern
2821 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2822 SDPatternOperator opnode, bit Commutable = 0> {
2823 let isCommutable = Commutable in {
2824 def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2825 opnode, VPR64, VPR128, v8i8, v8i16>;
2826 def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2827 opnode, VPR64, VPR128, v4i16, v4i32>;
2828 def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2829 opnode, VPR64, VPR128, v2i32, v2i64>;
2833 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2834 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2836 // pattern for acle intrinsic with 3 operands
2837 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2838 string asmop, string ResS, string OpS>
2839 : NeonI_3VDiff<q, u, size, opcode,
2840 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2841 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2843 let Constraints = "$src = $Rd";
2844 let neverHasSideEffects = 1;
2847 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2848 def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2849 def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2850 def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2853 defm ADDHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2854 defm SUBHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2856 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2857 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2859 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2861 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2862 SDPatternOperator coreop>
2863 : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2864 (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2865 (SrcTy VPR128:$Rm)))))),
2866 (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2867 VPR128:$Rn, VPR128:$Rm)>;
2870 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8, v8i16,
2871 BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2872 def : NarrowHighHalfPat<ADDHN2vvv_8h4s, v4i16, v4i32,
2873 BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2874 def : NarrowHighHalfPat<ADDHN2vvv_4s2d, v2i32, v2i64,
2875 BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2878 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8, v8i16,
2879 BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2880 def : NarrowHighHalfPat<SUBHN2vvv_8h4s, v4i16, v4i32,
2881 BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2882 def : NarrowHighHalfPat<SUBHN2vvv_4s2d, v2i32, v2i64,
2883 BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2886 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vraddhn>;
2887 def : NarrowHighHalfPat<RADDHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vraddhn>;
2888 def : NarrowHighHalfPat<RADDHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vraddhn>;
2891 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vrsubhn>;
2892 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vrsubhn>;
2893 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vrsubhn>;
2895 // pattern that need to extend result
2896 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2897 string asmop, string ResS, string OpS,
2898 SDPatternOperator opnode,
2899 RegisterOperand OpVPR,
2900 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2901 : NeonI_3VDiff<q, u, size, opcode,
2902 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2903 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2904 [(set (ResTy VPR128:$Rd),
2905 (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2906 (OpTy OpVPR:$Rm))))))],
2909 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2910 SDPatternOperator opnode, bit Commutable = 0> {
2911 let isCommutable = Commutable in {
2912 def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2913 opnode, VPR64, v8i16, v8i8, v8i8>;
2914 def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2915 opnode, VPR64, v4i32, v4i16, v4i16>;
2916 def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2917 opnode, VPR64, v2i64, v2i32, v2i32>;
2921 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2922 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2924 multiclass NeonI_Op_High<SDPatternOperator op> {
2925 def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2926 (op (v8i8 (Neon_High16B node:$Rn)),
2927 (v8i8 (Neon_High16B node:$Rm)))>;
2928 def _8H : PatFrag<(ops node:$Rn, node:$Rm),
2929 (op (v4i16 (Neon_High8H node:$Rn)),
2930 (v4i16 (Neon_High8H node:$Rm)))>;
2931 def _4S : PatFrag<(ops node:$Rn, node:$Rm),
2932 (op (v2i32 (Neon_High4S node:$Rn)),
2933 (v2i32 (Neon_High4S node:$Rm)))>;
2936 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2937 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2938 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2939 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2940 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2941 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2943 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2944 bit Commutable = 0> {
2945 let isCommutable = Commutable in {
2946 def _8h8b : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2947 !cast<PatFrag>(opnode # "_16B"),
2948 VPR128, v8i16, v16i8, v8i8>;
2949 def _4s4h : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2950 !cast<PatFrag>(opnode # "_8H"),
2951 VPR128, v4i32, v8i16, v4i16>;
2952 def _2d2s : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2953 !cast<PatFrag>(opnode # "_4S"),
2954 VPR128, v2i64, v4i32, v2i32>;
2958 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2959 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2961 // For pattern that need two operators being chained.
2962 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2963 string asmop, string ResS, string OpS,
2964 SDPatternOperator opnode, SDPatternOperator subop,
2965 RegisterOperand OpVPR,
2966 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2967 : NeonI_3VDiff<q, u, size, opcode,
2968 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2969 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2970 [(set (ResTy VPR128:$Rd),
2972 (ResTy VPR128:$src),
2973 (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2974 (OpTy OpVPR:$Rm))))))))],
2976 let Constraints = "$src = $Rd";
2979 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2980 SDPatternOperator opnode, SDPatternOperator subop>{
2981 def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2982 opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2983 def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2984 opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2985 def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2986 opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2989 defm SABALvvv : NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2990 add, int_arm_neon_vabds>;
2991 defm UABALvvv : NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2992 add, int_arm_neon_vabdu>;
2994 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2995 SDPatternOperator opnode, string subop> {
2996 def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2997 opnode, !cast<PatFrag>(subop # "_16B"),
2998 VPR128, v8i16, v16i8, v8i8>;
2999 def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3000 opnode, !cast<PatFrag>(subop # "_8H"),
3001 VPR128, v4i32, v8i16, v4i16>;
3002 def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3003 opnode, !cast<PatFrag>(subop # "_4S"),
3004 VPR128, v2i64, v4i32, v2i32>;
3007 defm SABAL2vvv : NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
3009 defm UABAL2vvv : NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
3012 // Long pattern with 2 operands
3013 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
3014 SDPatternOperator opnode, bit Commutable = 0> {
3015 let isCommutable = Commutable in {
3016 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3017 opnode, VPR128, VPR64, v8i16, v8i8>;
3018 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3019 opnode, VPR128, VPR64, v4i32, v4i16>;
3020 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3021 opnode, VPR128, VPR64, v2i64, v2i32>;
3025 defm SMULLvvv : NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
3026 defm UMULLvvv : NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
3028 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
3029 string asmop, string ResS, string OpS,
3030 SDPatternOperator opnode,
3031 ValueType ResTy, ValueType OpTy>
3032 : NeonI_3VDiff<q, u, size, opcode,
3033 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3034 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3035 [(set (ResTy VPR128:$Rd),
3036 (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
3039 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
3040 string opnode, bit Commutable = 0> {
3041 let isCommutable = Commutable in {
3042 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3043 !cast<PatFrag>(opnode # "_16B"),
3045 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3046 !cast<PatFrag>(opnode # "_8H"),
3048 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3049 !cast<PatFrag>(opnode # "_4S"),
3054 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
3056 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
3059 // Long pattern with 3 operands
3060 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
3061 string asmop, string ResS, string OpS,
3062 SDPatternOperator opnode,
3063 ValueType ResTy, ValueType OpTy>
3064 : NeonI_3VDiff<q, u, size, opcode,
3065 (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
3066 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3067 [(set (ResTy VPR128:$Rd),
3069 (ResTy VPR128:$src),
3070 (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
3072 let Constraints = "$src = $Rd";
3075 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
3076 SDPatternOperator opnode> {
3077 def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3078 opnode, v8i16, v8i8>;
3079 def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3080 opnode, v4i32, v4i16>;
3081 def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3082 opnode, v2i64, v2i32>;
3085 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3087 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3089 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3091 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3093 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3095 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3097 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3099 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3101 defm SMLALvvv : NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
3102 defm UMLALvvv : NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
3104 defm SMLSLvvv : NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
3105 defm UMLSLvvv : NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
3107 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
3108 string asmop, string ResS, string OpS,
3109 SDPatternOperator subop, SDPatternOperator opnode,
3110 RegisterOperand OpVPR,
3111 ValueType ResTy, ValueType OpTy>
3112 : NeonI_3VDiff<q, u, size, opcode,
3113 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
3114 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3115 [(set (ResTy VPR128:$Rd),
3117 (ResTy VPR128:$src),
3118 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
3120 let Constraints = "$src = $Rd";
3123 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
3124 SDPatternOperator subop, string opnode> {
3125 def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3126 subop, !cast<PatFrag>(opnode # "_16B"),
3127 VPR128, v8i16, v16i8>;
3128 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3129 subop, !cast<PatFrag>(opnode # "_8H"),
3130 VPR128, v4i32, v8i16>;
3131 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3132 subop, !cast<PatFrag>(opnode # "_4S"),
3133 VPR128, v2i64, v4i32>;
3136 defm SMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
3137 add, "NI_smull_hi">;
3138 defm UMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
3139 add, "NI_umull_hi">;
3141 defm SMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
3142 sub, "NI_smull_hi">;
3143 defm UMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
3144 sub, "NI_umull_hi">;
3146 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
3147 SDPatternOperator opnode> {
3148 def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3149 opnode, int_arm_neon_vqdmull,
3150 VPR64, v4i32, v4i16>;
3151 def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3152 opnode, int_arm_neon_vqdmull,
3153 VPR64, v2i64, v2i32>;
3156 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
3157 int_arm_neon_vqadds>;
3158 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
3159 int_arm_neon_vqsubs>;
3161 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
3162 SDPatternOperator opnode, bit Commutable = 0> {
3163 let isCommutable = Commutable in {
3164 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3165 opnode, VPR128, VPR64, v4i32, v4i16>;
3166 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3167 opnode, VPR128, VPR64, v2i64, v2i32>;
3171 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3172 int_arm_neon_vqdmull, 1>;
3174 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3175 string opnode, bit Commutable = 0> {
3176 let isCommutable = Commutable in {
3177 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3178 !cast<PatFrag>(opnode # "_8H"),
3180 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3181 !cast<PatFrag>(opnode # "_4S"),
3186 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3189 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3190 SDPatternOperator opnode> {
3191 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3192 opnode, NI_qdmull_hi_8H,
3193 VPR128, v4i32, v8i16>;
3194 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3195 opnode, NI_qdmull_hi_4S,
3196 VPR128, v2i64, v4i32>;
3199 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3200 int_arm_neon_vqadds>;
3201 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3202 int_arm_neon_vqsubs>;
3204 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3205 SDPatternOperator opnode_8h8b,
3206 SDPatternOperator opnode_1q1d, bit Commutable = 0> {
3207 let isCommutable = Commutable in {
3208 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3209 opnode_8h8b, VPR128, VPR64, v8i16, v8i8>;
3211 def _1q1d : NeonI_3VD_2Op<0b0, u, 0b11, opcode, asmop, "1q", "1d",
3212 opnode_1q1d, VPR128, VPR64, v16i8, v1i64>;
3216 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp,
3217 int_aarch64_neon_vmull_p64, 1>;
3219 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3220 string opnode, bit Commutable = 0> {
3221 let isCommutable = Commutable in {
3222 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3223 !cast<PatFrag>(opnode # "_16B"),
3227 NeonI_3VDiff<0b1, u, 0b11, opcode,
3228 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3229 asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3230 [(set (v16i8 VPR128:$Rd),
3231 (v16i8 (int_aarch64_neon_vmull_p64
3232 (v1i64 (scalar_to_vector
3233 (i64 (vector_extract (v2i64 VPR128:$Rn), 1)))),
3234 (v1i64 (scalar_to_vector
3235 (i64 (vector_extract (v2i64 VPR128:$Rm), 1)))))))],
3240 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3243 // End of implementation for instruction class (3V Diff)
3245 // The followings are vector load/store multiple N-element structure
3246 // (class SIMD lselem).
3248 // ld1: load multiple 1-element structure to 1/2/3/4 registers.
3249 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3250 // The structure consists of a sequence of sets of N values.
3251 // The first element of the structure is placed in the first lane
3252 // of the first first vector, the second element in the first lane
3253 // of the second vector, and so on.
3254 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3255 // the three 64-bit vectors list {BA, DC, FE}.
3256 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3257 // 64-bit vectors list {DA, EB, FC}.
3258 // Store instructions store multiple structure to N registers like load.
3261 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3262 RegisterOperand VecList, string asmop>
3263 : NeonI_LdStMult<q, 1, opcode, size,
3264 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3265 asmop # "\t$Rt, [$Rn]",
3269 let neverHasSideEffects = 1;
3272 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3273 def _8B : NeonI_LDVList<0, opcode, 0b00,
3274 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3276 def _4H : NeonI_LDVList<0, opcode, 0b01,
3277 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3279 def _2S : NeonI_LDVList<0, opcode, 0b10,
3280 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3282 def _16B : NeonI_LDVList<1, opcode, 0b00,
3283 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3285 def _8H : NeonI_LDVList<1, opcode, 0b01,
3286 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3288 def _4S : NeonI_LDVList<1, opcode, 0b10,
3289 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3291 def _2D : NeonI_LDVList<1, opcode, 0b11,
3292 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3295 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3296 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3297 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3299 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3301 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3303 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3305 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3306 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3307 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3309 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3310 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3312 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3313 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3315 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3316 RegisterOperand VecList, string asmop>
3317 : NeonI_LdStMult<q, 0, opcode, size,
3318 (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3319 asmop # "\t$Rt, [$Rn]",
3323 let neverHasSideEffects = 1;
3326 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3327 def _8B : NeonI_STVList<0, opcode, 0b00,
3328 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3330 def _4H : NeonI_STVList<0, opcode, 0b01,
3331 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3333 def _2S : NeonI_STVList<0, opcode, 0b10,
3334 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3336 def _16B : NeonI_STVList<1, opcode, 0b00,
3337 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3339 def _8H : NeonI_STVList<1, opcode, 0b01,
3340 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3342 def _4S : NeonI_STVList<1, opcode, 0b10,
3343 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3345 def _2D : NeonI_STVList<1, opcode, 0b11,
3346 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3349 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3350 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3351 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3353 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3355 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3357 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3359 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3360 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3361 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3363 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3364 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3366 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3367 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3369 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3370 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3372 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3373 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3375 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3376 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3378 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3379 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3381 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3382 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3384 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3385 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3387 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3388 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3389 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3390 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3392 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3393 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3394 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3395 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3397 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3398 (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3399 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3400 (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3402 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3403 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3404 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3405 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3407 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3408 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3409 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3410 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3412 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3413 (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3414 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3415 (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3417 // Match load/store of v1i8/v1i16/v1i32 type to FPR8/FPR16/FPR32 load/store.
3418 // FIXME: for now we have v1i8, v1i16, v1i32 legal types, if they are illegal,
3419 // these patterns are not needed any more.
3420 def : Pat<(v1i8 (load GPR64xsp:$addr)), (LSFP8_LDR $addr, 0)>;
3421 def : Pat<(v1i16 (load GPR64xsp:$addr)), (LSFP16_LDR $addr, 0)>;
3422 def : Pat<(v1i32 (load GPR64xsp:$addr)), (LSFP32_LDR $addr, 0)>;
3424 def : Pat<(store (v1i8 FPR8:$value), GPR64xsp:$addr),
3425 (LSFP8_STR $value, $addr, 0)>;
3426 def : Pat<(store (v1i16 FPR16:$value), GPR64xsp:$addr),
3427 (LSFP16_STR $value, $addr, 0)>;
3428 def : Pat<(store (v1i32 FPR32:$value), GPR64xsp:$addr),
3429 (LSFP32_STR $value, $addr, 0)>;
3432 // End of vector load/store multiple N-element structure(class SIMD lselem)
3434 // The followings are post-index vector load/store multiple N-element
3435 // structure(class SIMD lselem-post)
3436 def exact1_asmoperand : AsmOperandClass {
3437 let Name = "Exact1";
3438 let PredicateMethod = "isExactImm<1>";
3439 let RenderMethod = "addImmOperands";
3441 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3442 let ParserMatchClass = exact1_asmoperand;
3445 def exact2_asmoperand : AsmOperandClass {
3446 let Name = "Exact2";
3447 let PredicateMethod = "isExactImm<2>";
3448 let RenderMethod = "addImmOperands";
3450 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3451 let ParserMatchClass = exact2_asmoperand;
3454 def exact3_asmoperand : AsmOperandClass {
3455 let Name = "Exact3";
3456 let PredicateMethod = "isExactImm<3>";
3457 let RenderMethod = "addImmOperands";
3459 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3460 let ParserMatchClass = exact3_asmoperand;
3463 def exact4_asmoperand : AsmOperandClass {
3464 let Name = "Exact4";
3465 let PredicateMethod = "isExactImm<4>";
3466 let RenderMethod = "addImmOperands";
3468 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3469 let ParserMatchClass = exact4_asmoperand;
3472 def exact6_asmoperand : AsmOperandClass {
3473 let Name = "Exact6";
3474 let PredicateMethod = "isExactImm<6>";
3475 let RenderMethod = "addImmOperands";
3477 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3478 let ParserMatchClass = exact6_asmoperand;
3481 def exact8_asmoperand : AsmOperandClass {
3482 let Name = "Exact8";
3483 let PredicateMethod = "isExactImm<8>";
3484 let RenderMethod = "addImmOperands";
3486 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3487 let ParserMatchClass = exact8_asmoperand;
3490 def exact12_asmoperand : AsmOperandClass {
3491 let Name = "Exact12";
3492 let PredicateMethod = "isExactImm<12>";
3493 let RenderMethod = "addImmOperands";
3495 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3496 let ParserMatchClass = exact12_asmoperand;
3499 def exact16_asmoperand : AsmOperandClass {
3500 let Name = "Exact16";
3501 let PredicateMethod = "isExactImm<16>";
3502 let RenderMethod = "addImmOperands";
3504 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3505 let ParserMatchClass = exact16_asmoperand;
3508 def exact24_asmoperand : AsmOperandClass {
3509 let Name = "Exact24";
3510 let PredicateMethod = "isExactImm<24>";
3511 let RenderMethod = "addImmOperands";
3513 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3514 let ParserMatchClass = exact24_asmoperand;
3517 def exact32_asmoperand : AsmOperandClass {
3518 let Name = "Exact32";
3519 let PredicateMethod = "isExactImm<32>";
3520 let RenderMethod = "addImmOperands";
3522 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3523 let ParserMatchClass = exact32_asmoperand;
3526 def exact48_asmoperand : AsmOperandClass {
3527 let Name = "Exact48";
3528 let PredicateMethod = "isExactImm<48>";
3529 let RenderMethod = "addImmOperands";
3531 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3532 let ParserMatchClass = exact48_asmoperand;
3535 def exact64_asmoperand : AsmOperandClass {
3536 let Name = "Exact64";
3537 let PredicateMethod = "isExactImm<64>";
3538 let RenderMethod = "addImmOperands";
3540 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3541 let ParserMatchClass = exact64_asmoperand;
3544 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3545 RegisterOperand VecList, Operand ImmTy,
3547 let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3548 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3549 def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3550 (outs VecList:$Rt, GPR64xsp:$wb),
3551 (ins GPR64xsp:$Rn, ImmTy:$amt),
3552 asmop # "\t$Rt, [$Rn], $amt",
3558 def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3559 (outs VecList:$Rt, GPR64xsp:$wb),
3560 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3561 asmop # "\t$Rt, [$Rn], $Rm",
3567 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3568 Operand ImmTy2, string asmop> {
3569 defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3570 !cast<RegisterOperand>(List # "8B_operand"),
3573 defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3574 !cast<RegisterOperand>(List # "4H_operand"),
3577 defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3578 !cast<RegisterOperand>(List # "2S_operand"),
3581 defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3582 !cast<RegisterOperand>(List # "16B_operand"),
3585 defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3586 !cast<RegisterOperand>(List # "8H_operand"),
3589 defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3590 !cast<RegisterOperand>(List # "4S_operand"),
3593 defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3594 !cast<RegisterOperand>(List # "2D_operand"),
3598 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3599 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3600 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3603 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3605 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3608 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3610 // Post-index load multiple 1-element structures from N consecutive registers
3612 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3614 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3615 uimm_exact16, "ld1">;
3617 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3619 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3620 uimm_exact24, "ld1">;
3622 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3624 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3625 uimm_exact32, "ld1">;
3627 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3628 RegisterOperand VecList, Operand ImmTy,
3630 let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3631 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3632 def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3633 (outs GPR64xsp:$wb),
3634 (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3635 asmop # "\t$Rt, [$Rn], $amt",
3641 def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3642 (outs GPR64xsp:$wb),
3643 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3644 asmop # "\t$Rt, [$Rn], $Rm",
3650 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3651 Operand ImmTy2, string asmop> {
3652 defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3653 !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3655 defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3656 !cast<RegisterOperand>(List # "4H_operand"),
3659 defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3660 !cast<RegisterOperand>(List # "2S_operand"),
3663 defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3664 !cast<RegisterOperand>(List # "16B_operand"),
3667 defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3668 !cast<RegisterOperand>(List # "8H_operand"),
3671 defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3672 !cast<RegisterOperand>(List # "4S_operand"),
3675 defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3676 !cast<RegisterOperand>(List # "2D_operand"),
3680 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3681 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3682 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3685 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3687 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3690 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3692 // Post-index load multiple 1-element structures from N consecutive registers
3694 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3696 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3697 uimm_exact16, "st1">;
3699 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3701 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3702 uimm_exact24, "st1">;
3704 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3706 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3707 uimm_exact32, "st1">;
3709 // End of post-index vector load/store multiple N-element structure
3710 // (class SIMD lselem-post)
3712 // The followings are vector load/store single N-element structure
3713 // (class SIMD lsone).
3714 def neon_uimm0_bare : Operand<i64>,
3715 ImmLeaf<i64, [{return Imm == 0;}]> {
3716 let ParserMatchClass = neon_uimm0_asmoperand;
3717 let PrintMethod = "printUImmBareOperand";
3720 def neon_uimm1_bare : Operand<i64>,
3721 ImmLeaf<i64, [{return Imm < 2;}]> {
3722 let ParserMatchClass = neon_uimm1_asmoperand;
3723 let PrintMethod = "printUImmBareOperand";
3726 def neon_uimm2_bare : Operand<i64>,
3727 ImmLeaf<i64, [{return Imm < 4;}]> {
3728 let ParserMatchClass = neon_uimm2_asmoperand;
3729 let PrintMethod = "printUImmBareOperand";
3732 def neon_uimm3_bare : Operand<i64>,
3733 ImmLeaf<i64, [{return Imm < 8;}]> {
3734 let ParserMatchClass = uimm3_asmoperand;
3735 let PrintMethod = "printUImmBareOperand";
3738 def neon_uimm4_bare : Operand<i64>,
3739 ImmLeaf<i64, [{return Imm < 16;}]> {
3740 let ParserMatchClass = uimm4_asmoperand;
3741 let PrintMethod = "printUImmBareOperand";
3744 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3745 RegisterOperand VecList, string asmop>
3746 : NeonI_LdOne_Dup<q, r, opcode, size,
3747 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3748 asmop # "\t$Rt, [$Rn]",
3752 let neverHasSideEffects = 1;
3755 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3756 def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3757 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3759 def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3760 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3762 def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3763 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3765 def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3766 !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3768 def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3769 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3771 def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3772 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3774 def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3775 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3777 def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3778 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3781 // Load single 1-element structure to all lanes of 1 register
3782 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3784 // Load single N-element structure to all lanes of N consecutive
3785 // registers (N = 2,3,4)
3786 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3787 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3788 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3791 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3793 : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3794 (VTy (INST GPR64xsp:$Rn))>;
3796 // Match all LD1R instructions
3797 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3799 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3801 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3803 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3805 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3806 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3808 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3809 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3811 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3812 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3814 class LD1R_pattern_v1 <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3816 : Pat<(VTy (scalar_to_vector (DTy (LoadOp GPR64xsp:$Rn)))),
3817 (VTy (INST GPR64xsp:$Rn))>;
3819 def : LD1R_pattern_v1<v1i64, i64, load, LD1R_1D>;
3820 def : LD1R_pattern_v1<v1f64, f64, load, LD1R_1D>;
3822 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3823 RegisterClass RegList> {
3824 defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3825 defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3826 defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3827 defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3830 // Special vector list operand of 128-bit vectors with bare layout.
3831 // i.e. only show ".b", ".h", ".s", ".d"
3832 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3833 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3834 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3835 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3837 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3838 Operand ImmOp, string asmop>
3839 : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3841 (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3842 asmop # "\t$Rt[$lane], [$Rn]",
3846 let neverHasSideEffects = 1;
3847 let hasExtraDefRegAllocReq = 1;
3848 let Constraints = "$src = $Rt";
3851 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3852 def _B : NeonI_LDN_Lane<r, 0b00, op0,
3853 !cast<RegisterOperand>(List # "B_operand"),
3854 neon_uimm4_bare, asmop> {
3855 let Inst{12-10} = lane{2-0};
3856 let Inst{30} = lane{3};
3859 def _H : NeonI_LDN_Lane<r, 0b01, op0,
3860 !cast<RegisterOperand>(List # "H_operand"),
3861 neon_uimm3_bare, asmop> {
3862 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3863 let Inst{30} = lane{2};
3866 def _S : NeonI_LDN_Lane<r, 0b10, op0,
3867 !cast<RegisterOperand>(List # "S_operand"),
3868 neon_uimm2_bare, asmop> {
3869 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3870 let Inst{30} = lane{1};
3873 def _D : NeonI_LDN_Lane<r, 0b10, op0,
3874 !cast<RegisterOperand>(List # "D_operand"),
3875 neon_uimm1_bare, asmop> {
3876 let Inst{12-10} = 0b001;
3877 let Inst{30} = lane{0};
3881 // Load single 1-element structure to one lane of 1 register.
3882 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3884 // Load single N-element structure to one lane of N consecutive registers
3886 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3887 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3888 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3890 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3891 Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3893 def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3894 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3895 (VTy (EXTRACT_SUBREG
3897 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3901 def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3902 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3903 (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3906 // Match all LD1LN instructions
3907 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3908 extloadi8, LD1LN_B>;
3910 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3911 extloadi16, LD1LN_H>;
3913 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3915 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3918 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3920 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3923 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3924 Operand ImmOp, string asmop>
3925 : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3926 (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3927 asmop # "\t$Rt[$lane], [$Rn]",
3931 let neverHasSideEffects = 1;
3932 let hasExtraDefRegAllocReq = 1;
3935 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3936 def _B : NeonI_STN_Lane<r, 0b00, op0,
3937 !cast<RegisterOperand>(List # "B_operand"),
3938 neon_uimm4_bare, asmop> {
3939 let Inst{12-10} = lane{2-0};
3940 let Inst{30} = lane{3};
3943 def _H : NeonI_STN_Lane<r, 0b01, op0,
3944 !cast<RegisterOperand>(List # "H_operand"),
3945 neon_uimm3_bare, asmop> {
3946 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3947 let Inst{30} = lane{2};
3950 def _S : NeonI_STN_Lane<r, 0b10, op0,
3951 !cast<RegisterOperand>(List # "S_operand"),
3952 neon_uimm2_bare, asmop> {
3953 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3954 let Inst{30} = lane{1};
3957 def _D : NeonI_STN_Lane<r, 0b10, op0,
3958 !cast<RegisterOperand>(List # "D_operand"),
3959 neon_uimm1_bare, asmop>{
3960 let Inst{12-10} = 0b001;
3961 let Inst{30} = lane{0};
3965 // Store single 1-element structure from one lane of 1 register.
3966 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3968 // Store single N-element structure from one lane of N consecutive registers
3970 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3971 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3972 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3974 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3975 Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3977 def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3980 (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3983 def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3985 (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3988 // Match all ST1LN instructions
3989 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3990 truncstorei8, ST1LN_B>;
3992 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3993 truncstorei16, ST1LN_H>;
3995 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3997 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
4000 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
4002 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
4005 // End of vector load/store single N-element structure (class SIMD lsone).
4008 // The following are post-index load/store single N-element instructions
4009 // (class SIMD lsone-post)
4011 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
4012 RegisterOperand VecList, Operand ImmTy,
4014 let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
4015 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4016 def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4017 (outs VecList:$Rt, GPR64xsp:$wb),
4018 (ins GPR64xsp:$Rn, ImmTy:$amt),
4019 asmop # "\t$Rt, [$Rn], $amt",
4025 def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4026 (outs VecList:$Rt, GPR64xsp:$wb),
4027 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
4028 asmop # "\t$Rt, [$Rn], $Rm",
4034 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
4035 Operand uimm_b, Operand uimm_h,
4036 Operand uimm_s, Operand uimm_d> {
4037 defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
4038 !cast<RegisterOperand>(List # "8B_operand"),
4041 defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
4042 !cast<RegisterOperand>(List # "4H_operand"),
4045 defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
4046 !cast<RegisterOperand>(List # "2S_operand"),
4049 defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
4050 !cast<RegisterOperand>(List # "1D_operand"),
4053 defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
4054 !cast<RegisterOperand>(List # "16B_operand"),
4057 defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
4058 !cast<RegisterOperand>(List # "8H_operand"),
4061 defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
4062 !cast<RegisterOperand>(List # "4S_operand"),
4065 defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
4066 !cast<RegisterOperand>(List # "2D_operand"),
4070 // Post-index load single 1-element structure to all lanes of 1 register
4071 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
4072 uimm_exact2, uimm_exact4, uimm_exact8>;
4074 // Post-index load single N-element structure to all lanes of N consecutive
4075 // registers (N = 2,3,4)
4076 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
4077 uimm_exact4, uimm_exact8, uimm_exact16>;
4078 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
4079 uimm_exact6, uimm_exact12, uimm_exact24>;
4080 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
4081 uimm_exact8, uimm_exact16, uimm_exact32>;
4083 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
4084 Constraints = "$Rn = $wb, $Rt = $src",
4085 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4086 class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4087 Operand ImmTy, Operand ImmOp, string asmop>
4088 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4089 (outs VList:$Rt, GPR64xsp:$wb),
4090 (ins GPR64xsp:$Rn, ImmTy:$amt,
4091 VList:$src, ImmOp:$lane),
4092 asmop # "\t$Rt[$lane], [$Rn], $amt",
4098 class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4099 Operand ImmTy, Operand ImmOp, string asmop>
4100 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4101 (outs VList:$Rt, GPR64xsp:$wb),
4102 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
4103 VList:$src, ImmOp:$lane),
4104 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4109 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4110 Operand uimm_b, Operand uimm_h,
4111 Operand uimm_s, Operand uimm_d> {
4112 def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
4113 !cast<RegisterOperand>(List # "B_operand"),
4114 uimm_b, neon_uimm4_bare, asmop> {
4115 let Inst{12-10} = lane{2-0};
4116 let Inst{30} = lane{3};
4119 def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
4120 !cast<RegisterOperand>(List # "B_operand"),
4121 uimm_b, neon_uimm4_bare, asmop> {
4122 let Inst{12-10} = lane{2-0};
4123 let Inst{30} = lane{3};
4126 def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
4127 !cast<RegisterOperand>(List # "H_operand"),
4128 uimm_h, neon_uimm3_bare, asmop> {
4129 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4130 let Inst{30} = lane{2};
4133 def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
4134 !cast<RegisterOperand>(List # "H_operand"),
4135 uimm_h, neon_uimm3_bare, asmop> {
4136 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4137 let Inst{30} = lane{2};
4140 def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4141 !cast<RegisterOperand>(List # "S_operand"),
4142 uimm_s, neon_uimm2_bare, asmop> {
4143 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4144 let Inst{30} = lane{1};
4147 def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
4148 !cast<RegisterOperand>(List # "S_operand"),
4149 uimm_s, neon_uimm2_bare, asmop> {
4150 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4151 let Inst{30} = lane{1};
4154 def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4155 !cast<RegisterOperand>(List # "D_operand"),
4156 uimm_d, neon_uimm1_bare, asmop> {
4157 let Inst{12-10} = 0b001;
4158 let Inst{30} = lane{0};
4161 def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
4162 !cast<RegisterOperand>(List # "D_operand"),
4163 uimm_d, neon_uimm1_bare, asmop> {
4164 let Inst{12-10} = 0b001;
4165 let Inst{30} = lane{0};
4169 // Post-index load single 1-element structure to one lane of 1 register.
4170 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
4171 uimm_exact2, uimm_exact4, uimm_exact8>;
4173 // Post-index load single N-element structure to one lane of N consecutive
4176 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
4177 uimm_exact4, uimm_exact8, uimm_exact16>;
4178 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
4179 uimm_exact6, uimm_exact12, uimm_exact24>;
4180 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
4181 uimm_exact8, uimm_exact16, uimm_exact32>;
4183 let mayStore = 1, neverHasSideEffects = 1,
4184 hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
4185 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4186 class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4187 Operand ImmTy, Operand ImmOp, string asmop>
4188 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4189 (outs GPR64xsp:$wb),
4190 (ins GPR64xsp:$Rn, ImmTy:$amt,
4191 VList:$Rt, ImmOp:$lane),
4192 asmop # "\t$Rt[$lane], [$Rn], $amt",
4198 class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4199 Operand ImmTy, Operand ImmOp, string asmop>
4200 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4201 (outs GPR64xsp:$wb),
4202 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4204 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4209 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4210 Operand uimm_b, Operand uimm_h,
4211 Operand uimm_s, Operand uimm_d> {
4212 def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4213 !cast<RegisterOperand>(List # "B_operand"),
4214 uimm_b, neon_uimm4_bare, asmop> {
4215 let Inst{12-10} = lane{2-0};
4216 let Inst{30} = lane{3};
4219 def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4220 !cast<RegisterOperand>(List # "B_operand"),
4221 uimm_b, neon_uimm4_bare, asmop> {
4222 let Inst{12-10} = lane{2-0};
4223 let Inst{30} = lane{3};
4226 def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4227 !cast<RegisterOperand>(List # "H_operand"),
4228 uimm_h, neon_uimm3_bare, asmop> {
4229 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4230 let Inst{30} = lane{2};
4233 def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4234 !cast<RegisterOperand>(List # "H_operand"),
4235 uimm_h, neon_uimm3_bare, asmop> {
4236 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4237 let Inst{30} = lane{2};
4240 def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4241 !cast<RegisterOperand>(List # "S_operand"),
4242 uimm_s, neon_uimm2_bare, asmop> {
4243 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4244 let Inst{30} = lane{1};
4247 def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4248 !cast<RegisterOperand>(List # "S_operand"),
4249 uimm_s, neon_uimm2_bare, asmop> {
4250 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4251 let Inst{30} = lane{1};
4254 def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4255 !cast<RegisterOperand>(List # "D_operand"),
4256 uimm_d, neon_uimm1_bare, asmop> {
4257 let Inst{12-10} = 0b001;
4258 let Inst{30} = lane{0};
4261 def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4262 !cast<RegisterOperand>(List # "D_operand"),
4263 uimm_d, neon_uimm1_bare, asmop> {
4264 let Inst{12-10} = 0b001;
4265 let Inst{30} = lane{0};
4269 // Post-index store single 1-element structure from one lane of 1 register.
4270 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4271 uimm_exact2, uimm_exact4, uimm_exact8>;
4273 // Post-index store single N-element structure from one lane of N consecutive
4274 // registers (N = 2,3,4)
4275 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4276 uimm_exact4, uimm_exact8, uimm_exact16>;
4277 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4278 uimm_exact6, uimm_exact12, uimm_exact24>;
4279 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4280 uimm_exact8, uimm_exact16, uimm_exact32>;
4282 // End of post-index load/store single N-element instructions
4283 // (class SIMD lsone-post)
4285 // Neon Scalar instructions implementation
4286 // Scalar Three Same
4288 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4290 : NeonI_Scalar3Same<u, size, opcode,
4291 (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4292 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4296 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4297 : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4299 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4300 bit Commutable = 0> {
4301 let isCommutable = Commutable in {
4302 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4303 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4307 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4308 string asmop, bit Commutable = 0> {
4309 let isCommutable = Commutable in {
4310 def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4311 def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4315 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4316 string asmop, bit Commutable = 0> {
4317 let isCommutable = Commutable in {
4318 def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4319 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4320 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4321 def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4325 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4326 Instruction INSTD> {
4327 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4328 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4331 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4336 : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4337 def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4338 (INSTB FPR8:$Rn, FPR8:$Rm)>;
4339 def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4340 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4341 def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4342 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4345 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4347 Instruction INSTS> {
4348 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4349 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4350 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4351 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4354 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4355 ValueType SResTy, ValueType STy,
4356 Instruction INSTS, ValueType DResTy,
4357 ValueType DTy, Instruction INSTD> {
4358 def : Pat<(SResTy (opnode (STy FPR32:$Rn), (STy FPR32:$Rm))),
4359 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4360 def : Pat<(DResTy (opnode (DTy FPR64:$Rn), (DTy FPR64:$Rm))),
4361 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4364 class Neon_Scalar3Same_cmp_V1_D_size_patterns<CondCode CC,
4366 : Pat<(v1i64 (Neon_cmp (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm), CC)),
4367 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4369 // Scalar Three Different
4371 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4372 RegisterClass FPRCD, RegisterClass FPRCS>
4373 : NeonI_Scalar3Diff<u, size, opcode,
4374 (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4375 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4379 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4380 def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4381 def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4384 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4385 let Constraints = "$Src = $Rd" in {
4386 def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4387 (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4388 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4391 def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4392 (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4393 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4399 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4401 Instruction INSTS> {
4402 def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4403 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4404 def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4405 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4408 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4410 Instruction INSTS> {
4411 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4412 (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4413 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4414 (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4417 // Scalar Two Registers Miscellaneous
4419 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4420 RegisterClass FPRCD, RegisterClass FPRCS>
4421 : NeonI_Scalar2SameMisc<u, size, opcode,
4422 (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4423 !strconcat(asmop, "\t$Rd, $Rn"),
4427 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4429 def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4431 def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4435 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4436 def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4439 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4440 : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4441 def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4442 def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4443 def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4446 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4447 : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4449 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4451 def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4452 def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4453 def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4456 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4457 string asmop, RegisterClass FPRC>
4458 : NeonI_Scalar2SameMisc<u, size, opcode,
4459 (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4460 !strconcat(asmop, "\t$Rd, $Rn"),
4464 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4467 let Constraints = "$Src = $Rd" in {
4468 def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4469 def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4470 def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4471 def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4475 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4477 : Pat<(f32 (opnode (f64 FPR64:$Rn))),
4480 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4482 Instruction INSTD> {
4483 def : Pat<(v1i32 (opnode (f32 FPR32:$Rn))),
4485 def : Pat<(v1i64 (opnode (f64 FPR64:$Rn))),
4489 class Neon_Scalar2SameMisc_vcvt_D_size_patterns<SDPatternOperator opnode,
4491 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4494 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator opnode,
4496 Instruction INSTD> {
4497 def : Pat<(f32 (opnode (v1i32 FPR32:$Rn))),
4499 def : Pat<(f64 (opnode (v1i64 FPR64:$Rn))),
4503 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4505 Instruction INSTD> {
4506 def : Pat<(f32 (opnode (f32 FPR32:$Rn))),
4508 def : Pat<(f64 (opnode (f64 FPR64:$Rn))),
4512 class Neon_Scalar2SameMisc_V1_D_size_patterns<SDPatternOperator opnode,
4514 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4517 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4518 : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4519 (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4520 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4524 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4526 def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4527 (outs FPR32:$Rd), (ins FPR32:$Rn, fpzz32:$FPImm),
4528 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4531 def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4532 (outs FPR64:$Rd), (ins FPR64:$Rn, fpzz32:$FPImm),
4533 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4538 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4540 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4541 (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4542 (INSTD FPR64:$Rn, 0)>;
4544 class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
4546 : Pat<(v1i64 (Neon_cmpz (v1i64 FPR64:$Rn),
4547 (i32 neon_uimm0:$Imm), CC)),
4548 (INSTD FPR64:$Rn, neon_uimm0:$Imm)>;
4550 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4553 Instruction INSTD> {
4554 def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 fpzz32:$FPImm))),
4555 (INSTS FPR32:$Rn, fpzz32:$FPImm)>;
4556 def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f32 fpzz32:$FPImm))),
4557 (INSTD FPR64:$Rn, fpzz32:$FPImm)>;
4558 def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpzz32:$FPImm), CC)),
4559 (INSTD FPR64:$Rn, fpzz32:$FPImm)>;
4562 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4563 Instruction INSTD> {
4564 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4568 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4573 : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4574 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4576 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4578 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4582 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4583 SDPatternOperator opnode,
4586 Instruction INSTD> {
4587 def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4589 def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4591 def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4596 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4597 SDPatternOperator opnode,
4601 Instruction INSTD> {
4602 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4603 (INSTB FPR8:$Src, FPR8:$Rn)>;
4604 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4605 (INSTH FPR16:$Src, FPR16:$Rn)>;
4606 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4607 (INSTS FPR32:$Src, FPR32:$Rn)>;
4608 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4609 (INSTD FPR64:$Src, FPR64:$Rn)>;
4612 // Scalar Shift By Immediate
4614 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4615 RegisterClass FPRC, Operand ImmTy>
4616 : NeonI_ScalarShiftImm<u, opcode,
4617 (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4618 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4621 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4623 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4625 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4626 let Inst{21-16} = Imm;
4630 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4632 : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4633 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4635 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4636 let Inst{18-16} = Imm;
4638 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4640 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4641 let Inst{19-16} = Imm;
4643 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4645 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4646 let Inst{20-16} = Imm;
4650 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4652 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4654 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4655 let Inst{21-16} = Imm;
4659 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4661 : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4662 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4664 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4665 let Inst{18-16} = Imm;
4667 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4669 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4670 let Inst{19-16} = Imm;
4672 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4674 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4675 let Inst{20-16} = Imm;
4679 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4680 : NeonI_ScalarShiftImm<u, opcode,
4682 (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4683 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4686 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4687 let Inst{21-16} = Imm;
4688 let Constraints = "$Src = $Rd";
4691 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4692 : NeonI_ScalarShiftImm<u, opcode,
4694 (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4695 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4698 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4699 let Inst{21-16} = Imm;
4700 let Constraints = "$Src = $Rd";
4703 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4704 RegisterClass FPRCD, RegisterClass FPRCS,
4706 : NeonI_ScalarShiftImm<u, opcode,
4707 (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4708 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4711 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4713 def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4716 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4717 let Inst{18-16} = Imm;
4719 def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4722 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4723 let Inst{19-16} = Imm;
4725 def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4728 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4729 let Inst{20-16} = Imm;
4733 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4734 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4736 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4737 let Inst{20-16} = Imm;
4739 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4741 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4742 let Inst{21-16} = Imm;
4746 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4747 Instruction INSTD> {
4748 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4749 (INSTD FPR64:$Rn, imm:$Imm)>;
4752 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4753 Instruction INSTD> {
4754 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4755 (INSTD FPR64:$Rn, imm:$Imm)>;
4758 class Neon_ScalarShiftLImm_V1_D_size_patterns<SDPatternOperator opnode,
4760 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4761 (v1i64 (Neon_vdup (i32 shl_imm64:$Imm))))),
4762 (INSTD FPR64:$Rn, imm:$Imm)>;
4764 class Neon_ScalarShiftRImm_V1_D_size_patterns<SDPatternOperator opnode,
4766 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4767 (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4768 (INSTD FPR64:$Rn, imm:$Imm)>;
4770 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4775 : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4776 def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4777 (INSTB FPR8:$Rn, imm:$Imm)>;
4778 def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4779 (INSTH FPR16:$Rn, imm:$Imm)>;
4780 def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4781 (INSTS FPR32:$Rn, imm:$Imm)>;
4784 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4786 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4787 (i32 shl_imm64:$Imm))),
4788 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4790 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4792 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4793 (i32 shr_imm64:$Imm))),
4794 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4796 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4797 SDPatternOperator opnode,
4800 Instruction INSTD> {
4801 def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4802 (INSTH FPR16:$Rn, imm:$Imm)>;
4803 def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4804 (INSTS FPR32:$Rn, imm:$Imm)>;
4805 def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4806 (INSTD FPR64:$Rn, imm:$Imm)>;
4809 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator opnode,
4811 Instruction INSTD> {
4812 def ssi : Pat<(f32 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4813 (INSTS FPR32:$Rn, imm:$Imm)>;
4814 def ddi : Pat<(f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4815 (INSTD FPR64:$Rn, imm:$Imm)>;
4818 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
4820 Instruction INSTD> {
4821 def ssi : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4822 (INSTS FPR32:$Rn, imm:$Imm)>;
4823 def ddi : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4824 (INSTD FPR64:$Rn, imm:$Imm)>;
4827 // Scalar Signed Shift Right (Immediate)
4828 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4829 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4830 // Pattern to match llvm.arm.* intrinsic.
4831 def : Neon_ScalarShiftRImm_V1_D_size_patterns<sra, SSHRddi>;
4833 // Scalar Unsigned Shift Right (Immediate)
4834 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4835 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4836 // Pattern to match llvm.arm.* intrinsic.
4837 def : Neon_ScalarShiftRImm_V1_D_size_patterns<srl, USHRddi>;
4839 // Scalar Signed Rounding Shift Right (Immediate)
4840 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4841 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4843 // Scalar Unigned Rounding Shift Right (Immediate)
4844 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4845 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4847 // Scalar Signed Shift Right and Accumulate (Immediate)
4848 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4849 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4850 <int_aarch64_neon_vsrads_n, SSRA>;
4852 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4853 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4854 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4855 <int_aarch64_neon_vsradu_n, USRA>;
4857 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4858 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4859 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4860 <int_aarch64_neon_vrsrads_n, SRSRA>;
4862 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4863 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4864 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4865 <int_aarch64_neon_vrsradu_n, URSRA>;
4867 // Scalar Shift Left (Immediate)
4868 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4869 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4870 // Pattern to match llvm.arm.* intrinsic.
4871 def : Neon_ScalarShiftLImm_V1_D_size_patterns<shl, SHLddi>;
4873 // Signed Saturating Shift Left (Immediate)
4874 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4875 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4877 SQSHLssi, SQSHLddi>;
4878 // Pattern to match llvm.arm.* intrinsic.
4879 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4881 // Unsigned Saturating Shift Left (Immediate)
4882 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4883 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4885 UQSHLssi, UQSHLddi>;
4886 // Pattern to match llvm.arm.* intrinsic.
4887 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4889 // Signed Saturating Shift Left Unsigned (Immediate)
4890 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4891 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4892 SQSHLUbbi, SQSHLUhhi,
4893 SQSHLUssi, SQSHLUddi>;
4895 // Shift Right And Insert (Immediate)
4896 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4897 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4898 <int_aarch64_neon_vsri, SRI>;
4900 // Shift Left And Insert (Immediate)
4901 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4902 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4903 <int_aarch64_neon_vsli, SLI>;
4905 // Signed Saturating Shift Right Narrow (Immediate)
4906 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4907 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4908 SQSHRNbhi, SQSHRNhsi,
4911 // Unsigned Saturating Shift Right Narrow (Immediate)
4912 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4913 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4914 UQSHRNbhi, UQSHRNhsi,
4917 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4918 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4919 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4920 SQRSHRNbhi, SQRSHRNhsi,
4923 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4924 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4925 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4926 UQRSHRNbhi, UQRSHRNhsi,
4929 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4930 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4931 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4932 SQSHRUNbhi, SQSHRUNhsi,
4935 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4936 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4937 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4938 SQRSHRUNbhi, SQRSHRUNhsi,
4941 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4942 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4943 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxs2fp_n,
4944 SCVTF_Nssi, SCVTF_Nddi>;
4946 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4947 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4948 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxu2fp_n,
4949 UCVTF_Nssi, UCVTF_Nddi>;
4951 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4952 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4953 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxs_n,
4954 FCVTZS_Nssi, FCVTZS_Nddi>;
4956 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4957 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4958 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxu_n,
4959 FCVTZU_Nssi, FCVTZU_Nddi>;
4961 // Patterns For Convert Instructions Between v1f64 and v1i64
4962 class Neon_ScalarShiftImm_cvtf_v1f64_pattern<SDPatternOperator opnode,
4964 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4965 (INST FPR64:$Rn, imm:$Imm)>;
4967 class Neon_ScalarShiftImm_fcvt_v1f64_pattern<SDPatternOperator opnode,
4969 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4970 (INST FPR64:$Rn, imm:$Imm)>;
4972 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxs2fp,
4975 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxu2fp,
4978 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxs,
4981 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxu,
4984 // Scalar Integer Add
4985 let isCommutable = 1 in {
4986 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4989 // Scalar Integer Sub
4990 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4992 // Pattern for Scalar Integer Add and Sub with D register only
4993 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4994 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4996 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4997 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4998 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4999 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
5000 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
5002 // Scalar Integer Saturating Add (Signed, Unsigned)
5003 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
5004 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
5006 // Scalar Integer Saturating Sub (Signed, Unsigned)
5007 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
5008 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
5011 // Patterns to match llvm.aarch64.* intrinsic for
5012 // Scalar Integer Saturating Add, Sub (Signed, Unsigned)
5013 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
5014 SQADDhhh, SQADDsss, SQADDddd>;
5015 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
5016 UQADDhhh, UQADDsss, UQADDddd>;
5017 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
5018 SQSUBhhh, SQSUBsss, SQSUBddd>;
5019 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
5020 UQSUBhhh, UQSUBsss, UQSUBddd>;
5022 // Scalar Integer Saturating Doubling Multiply Half High
5023 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
5025 // Scalar Integer Saturating Rounding Doubling Multiply Half High
5026 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
5028 // Patterns to match llvm.arm.* intrinsic for
5029 // Scalar Integer Saturating Doubling Multiply Half High and
5030 // Scalar Integer Saturating Rounding Doubling Multiply Half High
5031 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
5033 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
5036 // Scalar Floating-point Multiply Extended
5037 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
5039 // Scalar Floating-point Reciprocal Step
5040 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
5041 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrecps, f32, f32,
5042 FRECPSsss, f64, f64, FRECPSddd>;
5043 def : Pat<(v1f64 (int_arm_neon_vrecps (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5044 (FRECPSddd FPR64:$Rn, FPR64:$Rm)>;
5046 // Scalar Floating-point Reciprocal Square Root Step
5047 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
5048 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrsqrts, f32, f32,
5049 FRSQRTSsss, f64, f64, FRSQRTSddd>;
5050 def : Pat<(v1f64 (int_arm_neon_vrsqrts (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5051 (FRSQRTSddd FPR64:$Rn, FPR64:$Rm)>;
5052 def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>;
5054 // Patterns to match llvm.aarch64.* intrinsic for
5055 // Scalar Floating-point Multiply Extended,
5056 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
5058 Instruction INSTD> {
5059 def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
5060 (INSTS FPR32:$Rn, FPR32:$Rm)>;
5061 def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
5062 (INSTD FPR64:$Rn, FPR64:$Rm)>;
5065 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
5066 FMULXsss, FMULXddd>;
5067 def : Pat<(v1f64 (int_aarch64_neon_vmulx (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5068 (FMULXddd FPR64:$Rn, FPR64:$Rm)>;
5070 // Scalar Integer Shift Left (Signed, Unsigned)
5071 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
5072 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
5074 // Patterns to match llvm.arm.* intrinsic for
5075 // Scalar Integer Shift Left (Signed, Unsigned)
5076 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
5077 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
5079 // Patterns to match llvm.aarch64.* intrinsic for
5080 // Scalar Integer Shift Left (Signed, Unsigned)
5081 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
5082 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
5084 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
5085 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
5086 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
5088 // Patterns to match llvm.aarch64.* intrinsic for
5089 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
5090 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
5091 SQSHLhhh, SQSHLsss, SQSHLddd>;
5092 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
5093 UQSHLhhh, UQSHLsss, UQSHLddd>;
5095 // Patterns to match llvm.arm.* intrinsic for
5096 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
5097 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
5098 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
5100 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5101 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
5102 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
5104 // Patterns to match llvm.aarch64.* intrinsic for
5105 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5106 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
5107 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
5109 // Patterns to match llvm.arm.* intrinsic for
5110 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5111 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
5112 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
5114 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5115 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
5116 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
5118 // Patterns to match llvm.aarch64.* intrinsic for
5119 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5120 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
5121 SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
5122 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
5123 UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
5125 // Patterns to match llvm.arm.* intrinsic for
5126 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5127 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
5128 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
5130 // Signed Saturating Doubling Multiply-Add Long
5131 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
5132 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
5133 SQDMLALshh, SQDMLALdss>;
5135 // Signed Saturating Doubling Multiply-Subtract Long
5136 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
5137 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
5138 SQDMLSLshh, SQDMLSLdss>;
5140 // Signed Saturating Doubling Multiply Long
5141 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
5142 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
5143 SQDMULLshh, SQDMULLdss>;
5145 // Scalar Signed Integer Convert To Floating-point
5146 defm SCVTF : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
5147 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fps,
5150 // Scalar Unsigned Integer Convert To Floating-point
5151 defm UCVTF : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
5152 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fpu,
5155 // Scalar Floating-point Converts
5156 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
5157 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
5160 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
5161 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
5162 FCVTNSss, FCVTNSdd>;
5163 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtns, FCVTNSdd>;
5165 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
5166 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
5167 FCVTNUss, FCVTNUdd>;
5168 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtnu, FCVTNUdd>;
5170 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
5171 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
5172 FCVTMSss, FCVTMSdd>;
5173 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtms, FCVTMSdd>;
5175 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
5176 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
5177 FCVTMUss, FCVTMUdd>;
5178 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtmu, FCVTMUdd>;
5180 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
5181 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
5182 FCVTASss, FCVTASdd>;
5183 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtas, FCVTASdd>;
5185 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
5186 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
5187 FCVTAUss, FCVTAUdd>;
5188 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtau, FCVTAUdd>;
5190 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
5191 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
5192 FCVTPSss, FCVTPSdd>;
5193 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtps, FCVTPSdd>;
5195 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
5196 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
5197 FCVTPUss, FCVTPUdd>;
5198 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtpu, FCVTPUdd>;
5200 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
5201 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
5202 FCVTZSss, FCVTZSdd>;
5203 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzs,
5206 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
5207 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
5208 FCVTZUss, FCVTZUdd>;
5209 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzu,
5212 // Patterns For Convert Instructions Between v1f64 and v1i64
5213 class Neon_Scalar2SameMisc_cvtf_v1f64_pattern<SDPatternOperator opnode,
5215 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5217 class Neon_Scalar2SameMisc_fcvt_v1f64_pattern<SDPatternOperator opnode,
5219 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5221 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<sint_to_fp, SCVTFdd>;
5222 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<uint_to_fp, UCVTFdd>;
5224 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_sint, FCVTZSdd>;
5225 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_uint, FCVTZUdd>;
5227 // Scalar Floating-point Reciprocal Estimate
5228 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5229 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpe,
5230 FRECPEss, FRECPEdd>;
5231 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrecpe,
5234 // Scalar Floating-point Reciprocal Exponent
5235 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5236 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5237 FRECPXss, FRECPXdd>;
5239 // Scalar Floating-point Reciprocal Square Root Estimate
5240 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5241 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrsqrte,
5242 FRSQRTEss, FRSQRTEdd>;
5243 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrsqrte,
5246 // Scalar Floating-point Round
5247 class Neon_ScalarFloatRound_pattern<SDPatternOperator opnode, Instruction INST>
5248 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5250 def : Neon_ScalarFloatRound_pattern<fceil, FRINTPdd>;
5251 def : Neon_ScalarFloatRound_pattern<ffloor, FRINTMdd>;
5252 def : Neon_ScalarFloatRound_pattern<ftrunc, FRINTZdd>;
5253 def : Neon_ScalarFloatRound_pattern<frint, FRINTXdd>;
5254 def : Neon_ScalarFloatRound_pattern<fnearbyint, FRINTIdd>;
5255 def : Neon_ScalarFloatRound_pattern<frnd, FRINTAdd>;
5256 def : Neon_ScalarFloatRound_pattern<int_aarch64_neon_frintn, FRINTNdd>;
5258 // Scalar Integer Compare
5260 // Scalar Compare Bitwise Equal
5261 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5262 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5264 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5267 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5268 (INSTD FPR64:$Rn, FPR64:$Rm)>;
5270 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5272 // Scalar Compare Signed Greather Than Or Equal
5273 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5274 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5275 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGEddd, SETGE>;
5277 // Scalar Compare Unsigned Higher Or Same
5278 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5279 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5280 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHSddd, SETUGE>;
5282 // Scalar Compare Unsigned Higher
5283 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5284 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5285 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHIddd, SETUGT>;
5287 // Scalar Compare Signed Greater Than
5288 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5289 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5290 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGTddd, SETGT>;
5292 // Scalar Compare Bitwise Test Bits
5293 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5294 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5295 defm : Neon_Scalar3Same_D_size_patterns<Neon_tst, CMTSTddd>;
5297 // Scalar Compare Bitwise Equal To Zero
5298 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5299 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5301 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETEQ, CMEQddi>;
5303 // Scalar Compare Signed Greather Than Or Equal To Zero
5304 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5305 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5307 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGE, CMGEddi>;
5309 // Scalar Compare Signed Greater Than Zero
5310 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5311 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5313 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGT, CMGTddi>;
5315 // Scalar Compare Signed Less Than Or Equal To Zero
5316 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5317 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5319 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLE, CMLEddi>;
5321 // Scalar Compare Less Than Zero
5322 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5323 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5325 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
5327 // Scalar Floating-point Compare
5329 // Scalar Floating-point Compare Mask Equal
5330 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5331 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fceq, v1i32, f32,
5332 FCMEQsss, v1i64, f64, FCMEQddd>;
5333 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
5335 // Scalar Floating-point Compare Mask Equal To Zero
5336 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5337 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fceq, SETEQ,
5338 FCMEQZssi, FCMEQZddi>;
5340 // Scalar Floating-point Compare Mask Greater Than Or Equal
5341 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5342 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcge, v1i32, f32,
5343 FCMGEsss, v1i64, f64, FCMGEddd>;
5344 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
5346 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5347 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5348 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcge, SETGE,
5349 FCMGEZssi, FCMGEZddi>;
5351 // Scalar Floating-point Compare Mask Greather Than
5352 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5353 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcgt, v1i32, f32,
5354 FCMGTsss, v1i64, f64, FCMGTddd>;
5355 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
5357 // Scalar Floating-point Compare Mask Greather Than Zero
5358 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5359 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcgt, SETGT,
5360 FCMGTZssi, FCMGTZddi>;
5362 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5363 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5364 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fclez, SETLE,
5365 FCMLEZssi, FCMLEZddi>;
5367 // Scalar Floating-point Compare Mask Less Than Zero
5368 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5369 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcltz, SETLT,
5370 FCMLTZssi, FCMLTZddi>;
5372 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5373 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5374 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcage, v1i32, f32,
5375 FACGEsss, v1i64, f64, FACGEddd>;
5376 def : Pat<(v1i64 (int_aarch64_neon_vcage (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5377 (FACGEddd FPR64:$Rn, FPR64:$Rm)>;
5379 // Scalar Floating-point Absolute Compare Mask Greater Than
5380 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5381 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcagt, v1i32, f32,
5382 FACGTsss, v1i64, f64, FACGTddd>;
5383 def : Pat<(v1i64 (int_aarch64_neon_vcagt (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5384 (FACGTddd FPR64:$Rn, FPR64:$Rm)>;
5386 // Scalar Floating-point Absolute Difference
5387 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5388 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vabd, f32, f32,
5389 FABDsss, f64, f64, FABDddd>;
5391 // Scalar Absolute Value
5392 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5393 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5395 // Scalar Signed Saturating Absolute Value
5396 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5397 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5398 SQABSbb, SQABShh, SQABSss, SQABSdd>;
5401 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5402 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5404 // Scalar Signed Saturating Negate
5405 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5406 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5407 SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5409 // Scalar Signed Saturating Accumulated of Unsigned Value
5410 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5411 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5413 SUQADDss, SUQADDdd>;
5415 // Scalar Unsigned Saturating Accumulated of Signed Value
5416 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5417 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5419 USQADDss, USQADDdd>;
5421 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5422 (v1i64 FPR64:$Rn))),
5423 (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5425 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5426 (v1i64 FPR64:$Rn))),
5427 (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5429 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5432 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5433 (SQABSdd FPR64:$Rn)>;
5435 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5436 (SQNEGdd FPR64:$Rn)>;
5438 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5439 (v1i64 FPR64:$Rn))),
5442 // Scalar Signed Saturating Extract Unsigned Narrow
5443 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5444 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5448 // Scalar Signed Saturating Extract Narrow
5449 defm SQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5450 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5454 // Scalar Unsigned Saturating Extract Narrow
5455 defm UQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5456 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5460 // Scalar Reduce Pairwise
5462 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5463 string asmop, bit Commutable = 0> {
5464 let isCommutable = Commutable in {
5465 def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5466 (outs FPR64:$Rd), (ins VPR128:$Rn),
5467 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5473 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5474 string asmop, bit Commutable = 0>
5475 : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5476 let isCommutable = Commutable in {
5477 def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5478 (outs FPR32:$Rd), (ins VPR64:$Rn),
5479 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5485 // Scalar Reduce Addition Pairwise (Integer) with
5486 // Pattern to match llvm.arm.* intrinsic
5487 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5489 // Pattern to match llvm.aarch64.* intrinsic for
5490 // Scalar Reduce Addition Pairwise (Integer)
5491 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5492 (ADDPvv_D_2D VPR128:$Rn)>;
5493 def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
5494 (ADDPvv_D_2D VPR128:$Rn)>;
5496 // Scalar Reduce Addition Pairwise (Floating Point)
5497 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5499 // Scalar Reduce Maximum Pairwise (Floating Point)
5500 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5502 // Scalar Reduce Minimum Pairwise (Floating Point)
5503 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5505 // Scalar Reduce maxNum Pairwise (Floating Point)
5506 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5508 // Scalar Reduce minNum Pairwise (Floating Point)
5509 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5511 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnode,
5513 Instruction INSTD> {
5514 def : Pat<(f32 (opnode (v2f32 VPR64:$Rn))),
5516 def : Pat<(f64 (opnode (v2f64 VPR128:$Rn))),
5517 (INSTD VPR128:$Rn)>;
5520 // Patterns to match llvm.aarch64.* intrinsic for
5521 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5522 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5523 FADDPvv_S_2S, FADDPvv_D_2D>;
5525 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5526 FMAXPvv_S_2S, FMAXPvv_D_2D>;
5528 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5529 FMINPvv_S_2S, FMINPvv_D_2D>;
5531 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5532 FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5534 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5535 FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5537 def : Pat<(f32 (int_aarch64_neon_vpfadd (v4f32 VPR128:$Rn))),
5538 (FADDPvv_S_2S (v2f32
5540 (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
5543 // Scalar by element Arithmetic
5545 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5546 string rmlane, bit u, bit szhi, bit szlo,
5547 RegisterClass ResFPR, RegisterClass OpFPR,
5548 RegisterOperand OpVPR, Operand OpImm>
5549 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5551 (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5552 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5559 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5561 bit u, bit szhi, bit szlo,
5562 RegisterClass ResFPR,
5563 RegisterClass OpFPR,
5564 RegisterOperand OpVPR,
5566 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5568 (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5569 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5572 let Constraints = "$src = $Rd";
5577 // Scalar Floating Point multiply (scalar, by element)
5578 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5579 0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5580 let Inst{11} = Imm{1}; // h
5581 let Inst{21} = Imm{0}; // l
5582 let Inst{20-16} = MRm;
5584 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5585 0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5586 let Inst{11} = Imm{0}; // h
5587 let Inst{21} = 0b0; // l
5588 let Inst{20-16} = MRm;
5591 // Scalar Floating Point multiply extended (scalar, by element)
5592 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5593 0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5594 let Inst{11} = Imm{1}; // h
5595 let Inst{21} = Imm{0}; // l
5596 let Inst{20-16} = MRm;
5598 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5599 0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5600 let Inst{11} = Imm{0}; // h
5601 let Inst{21} = 0b0; // l
5602 let Inst{20-16} = MRm;
5605 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5606 SDPatternOperator opnode,
5608 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5609 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5611 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5612 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5613 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5615 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5616 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5617 (ResTy (INST (ResTy FPRC:$Rn),
5618 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5622 def : Pat<(ResTy (opnode
5623 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5625 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5627 def : Pat<(ResTy (opnode
5628 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5630 (ResTy (INST (ResTy FPRC:$Rn),
5631 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5635 // Patterns for Scalar Floating Point multiply (scalar, by element)
5636 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5637 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5638 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5639 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5641 // Patterns for Scalar Floating Point multiply extended (scalar, by element)
5642 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5643 FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5644 v2f32, v4f32, neon_uimm1_bare>;
5645 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5646 FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5647 v1f64, v2f64, neon_uimm0_bare>;
5649 // Scalar Floating Point fused multiply-add (scalar, by element)
5650 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5651 0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5652 let Inst{11} = Imm{1}; // h
5653 let Inst{21} = Imm{0}; // l
5654 let Inst{20-16} = MRm;
5656 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5657 0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5658 let Inst{11} = Imm{0}; // h
5659 let Inst{21} = 0b0; // l
5660 let Inst{20-16} = MRm;
5663 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5664 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5665 0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5666 let Inst{11} = Imm{1}; // h
5667 let Inst{21} = Imm{0}; // l
5668 let Inst{20-16} = MRm;
5670 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5671 0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5672 let Inst{11} = Imm{0}; // h
5673 let Inst{21} = 0b0; // l
5674 let Inst{20-16} = MRm;
5676 // We are allowed to match the fma instruction regardless of compile options.
5677 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5678 Instruction FMLAI, Instruction FMLSI,
5679 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5680 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5682 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5683 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5685 (ResTy (FMLAI (ResTy FPRC:$Ra),
5686 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5688 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5689 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5691 (ResTy (FMLAI (ResTy FPRC:$Ra),
5693 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5696 // swapped fmla operands
5697 def : Pat<(ResTy (fma
5698 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5701 (ResTy (FMLAI (ResTy FPRC:$Ra),
5702 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5704 def : Pat<(ResTy (fma
5705 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5708 (ResTy (FMLAI (ResTy FPRC:$Ra),
5710 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5714 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5715 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5717 (ResTy (FMLSI (ResTy FPRC:$Ra),
5718 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5720 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5721 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5723 (ResTy (FMLSI (ResTy FPRC:$Ra),
5725 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5728 // swapped fmls operands
5729 def : Pat<(ResTy (fma
5730 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5733 (ResTy (FMLSI (ResTy FPRC:$Ra),
5734 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5736 def : Pat<(ResTy (fma
5737 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5740 (ResTy (FMLSI (ResTy FPRC:$Ra),
5742 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5746 // Scalar Floating Point fused multiply-add and
5747 // multiply-subtract (scalar, by element)
5748 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5749 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5750 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5751 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5752 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5753 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5755 // Scalar Signed saturating doubling multiply long (scalar, by element)
5756 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5757 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5758 let Inst{11} = 0b0; // h
5759 let Inst{21} = Imm{1}; // l
5760 let Inst{20} = Imm{0}; // m
5761 let Inst{19-16} = MRm{3-0};
5763 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5764 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5765 let Inst{11} = Imm{2}; // h
5766 let Inst{21} = Imm{1}; // l
5767 let Inst{20} = Imm{0}; // m
5768 let Inst{19-16} = MRm{3-0};
5770 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5771 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5772 let Inst{11} = 0b0; // h
5773 let Inst{21} = Imm{0}; // l
5774 let Inst{20-16} = MRm;
5776 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5777 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5778 let Inst{11} = Imm{1}; // h
5779 let Inst{21} = Imm{0}; // l
5780 let Inst{20-16} = MRm;
5783 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5784 SDPatternOperator opnode,
5786 ValueType ResTy, RegisterClass FPRC,
5787 ValueType OpVTy, ValueType OpTy,
5788 ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5790 def : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5791 (OpVTy (scalar_to_vector
5792 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5793 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5796 def : Pat<(ResTy (opnode
5797 (OpVTy (scalar_to_vector
5798 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5800 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5804 // Patterns for Scalar Signed saturating doubling
5805 // multiply long (scalar, by element)
5806 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5807 SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5808 i32, VPR64Lo, neon_uimm2_bare>;
5809 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5810 SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5811 i32, VPR128Lo, neon_uimm3_bare>;
5812 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5813 SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5814 i32, VPR64Lo, neon_uimm1_bare>;
5815 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5816 SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5817 i32, VPR128Lo, neon_uimm2_bare>;
5819 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5820 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5821 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5822 let Inst{11} = 0b0; // h
5823 let Inst{21} = Imm{1}; // l
5824 let Inst{20} = Imm{0}; // m
5825 let Inst{19-16} = MRm{3-0};
5827 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5828 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5829 let Inst{11} = Imm{2}; // h
5830 let Inst{21} = Imm{1}; // l
5831 let Inst{20} = Imm{0}; // m
5832 let Inst{19-16} = MRm{3-0};
5834 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5835 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5836 let Inst{11} = 0b0; // h
5837 let Inst{21} = Imm{0}; // l
5838 let Inst{20-16} = MRm;
5840 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5841 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5842 let Inst{11} = Imm{1}; // h
5843 let Inst{21} = Imm{0}; // l
5844 let Inst{20-16} = MRm;
5847 // Scalar Signed saturating doubling
5848 // multiply-subtract long (scalar, by element)
5849 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5850 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5851 let Inst{11} = 0b0; // h
5852 let Inst{21} = Imm{1}; // l
5853 let Inst{20} = Imm{0}; // m
5854 let Inst{19-16} = MRm{3-0};
5856 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5857 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5858 let Inst{11} = Imm{2}; // h
5859 let Inst{21} = Imm{1}; // l
5860 let Inst{20} = Imm{0}; // m
5861 let Inst{19-16} = MRm{3-0};
5863 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5864 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5865 let Inst{11} = 0b0; // h
5866 let Inst{21} = Imm{0}; // l
5867 let Inst{20-16} = MRm;
5869 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5870 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5871 let Inst{11} = Imm{1}; // h
5872 let Inst{21} = Imm{0}; // l
5873 let Inst{20-16} = MRm;
5876 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5877 SDPatternOperator opnode,
5878 SDPatternOperator coreopnode,
5880 ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5882 ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5884 def : Pat<(ResTy (opnode
5885 (ResTy ResFPRC:$Ra),
5886 (ResTy (coreopnode (OpTy FPRC:$Rn),
5887 (OpTy (scalar_to_vector
5888 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5889 (ResTy (INST (ResTy ResFPRC:$Ra),
5890 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5893 def : Pat<(ResTy (opnode
5894 (ResTy ResFPRC:$Ra),
5896 (OpTy (scalar_to_vector
5897 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5898 (OpTy FPRC:$Rn))))),
5899 (ResTy (INST (ResTy ResFPRC:$Ra),
5900 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5903 // Patterns for Scalar Signed saturating
5904 // doubling multiply-add long (scalar, by element)
5905 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5906 int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5907 i32, VPR64Lo, neon_uimm2_bare>;
5908 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5909 int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5910 i32, VPR128Lo, neon_uimm3_bare>;
5911 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5912 int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5913 i32, VPR64Lo, neon_uimm1_bare>;
5914 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5915 int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5916 i32, VPR128Lo, neon_uimm2_bare>;
5918 // Patterns for Scalar Signed saturating
5919 // doubling multiply-sub long (scalar, by element)
5920 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5921 int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5922 i32, VPR64Lo, neon_uimm2_bare>;
5923 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5924 int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5925 i32, VPR128Lo, neon_uimm3_bare>;
5926 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5927 int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5928 i32, VPR64Lo, neon_uimm1_bare>;
5929 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5930 int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5931 i32, VPR128Lo, neon_uimm2_bare>;
5933 // Scalar Signed saturating doubling multiply returning
5934 // high half (scalar, by element)
5935 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5936 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5937 let Inst{11} = 0b0; // h
5938 let Inst{21} = Imm{1}; // l
5939 let Inst{20} = Imm{0}; // m
5940 let Inst{19-16} = MRm{3-0};
5942 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5943 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5944 let Inst{11} = Imm{2}; // h
5945 let Inst{21} = Imm{1}; // l
5946 let Inst{20} = Imm{0}; // m
5947 let Inst{19-16} = MRm{3-0};
5949 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5950 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5951 let Inst{11} = 0b0; // h
5952 let Inst{21} = Imm{0}; // l
5953 let Inst{20-16} = MRm;
5955 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5956 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5957 let Inst{11} = Imm{1}; // h
5958 let Inst{21} = Imm{0}; // l
5959 let Inst{20-16} = MRm;
5962 // Patterns for Scalar Signed saturating doubling multiply returning
5963 // high half (scalar, by element)
5964 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5965 SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5966 i32, VPR64Lo, neon_uimm2_bare>;
5967 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5968 SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5969 i32, VPR128Lo, neon_uimm3_bare>;
5970 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5971 SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5972 i32, VPR64Lo, neon_uimm1_bare>;
5973 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5974 SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5975 i32, VPR128Lo, neon_uimm2_bare>;
5977 // Scalar Signed saturating rounding doubling multiply
5978 // returning high half (scalar, by element)
5979 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5980 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5981 let Inst{11} = 0b0; // h
5982 let Inst{21} = Imm{1}; // l
5983 let Inst{20} = Imm{0}; // m
5984 let Inst{19-16} = MRm{3-0};
5986 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5987 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5988 let Inst{11} = Imm{2}; // h
5989 let Inst{21} = Imm{1}; // l
5990 let Inst{20} = Imm{0}; // m
5991 let Inst{19-16} = MRm{3-0};
5993 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5994 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5995 let Inst{11} = 0b0; // h
5996 let Inst{21} = Imm{0}; // l
5997 let Inst{20-16} = MRm;
5999 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
6000 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
6001 let Inst{11} = Imm{1}; // h
6002 let Inst{21} = Imm{0}; // l
6003 let Inst{20-16} = MRm;
6006 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6007 SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
6008 VPR64Lo, neon_uimm2_bare>;
6009 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6010 SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
6011 VPR128Lo, neon_uimm3_bare>;
6012 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6013 SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
6014 VPR64Lo, neon_uimm1_bare>;
6015 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6016 SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
6017 VPR128Lo, neon_uimm2_bare>;
6019 // Scalar general arithmetic operation
6020 class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
6022 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
6024 class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
6026 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
6027 (INST FPR64:$Rn, FPR64:$Rm)>;
6029 class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
6031 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
6032 (v1f64 FPR64:$Ra))),
6033 (INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
6035 def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
6036 def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
6037 def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
6038 def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
6039 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
6040 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
6041 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
6042 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
6043 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
6045 def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
6046 def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
6048 def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
6049 def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
6051 // Scalar Copy - DUP element to scalar
6052 class NeonI_Scalar_DUP<string asmop, string asmlane,
6053 RegisterClass ResRC, RegisterOperand VPRC,
6055 : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
6056 asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
6062 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
6063 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6065 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
6066 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6068 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
6069 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6071 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
6072 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6075 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 0)),
6076 (f32 (EXTRACT_SUBREG (v4f32 VPR128:$Rn), sub_32))>;
6077 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 1)),
6078 (f32 (DUPsv_S (v4f32 VPR128:$Rn), 1))>;
6079 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 2)),
6080 (f32 (DUPsv_S (v4f32 VPR128:$Rn), 2))>;
6081 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 3)),
6082 (f32 (DUPsv_S (v4f32 VPR128:$Rn), 3))>;
6084 def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 0)),
6085 (f64 (EXTRACT_SUBREG (v2f64 VPR128:$Rn), sub_64))>;
6086 def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 1)),
6087 (f64 (DUPdv_D (v2f64 VPR128:$Rn), 1))>;
6089 def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 0)),
6090 (f32 (EXTRACT_SUBREG (v2f32 VPR64:$Rn), sub_32))>;
6091 def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 1)),
6092 (f32 (DUPsv_S (v4f32 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6095 def : Pat<(f64 (vector_extract (v1f64 VPR64:$Rn), 0)),
6096 (f64 (EXTRACT_SUBREG (v1f64 VPR64:$Rn), sub_64))>;
6098 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
6099 ValueType ResTy, ValueType OpTy,Operand OpLImm,
6100 ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
6102 def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
6103 (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
6105 def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
6107 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6111 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
6112 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
6113 v8i8, v16i8, neon_uimm3_bare>;
6114 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
6115 v4i16, v8i16, neon_uimm2_bare>;
6116 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
6117 v2i32, v4i32, neon_uimm1_bare>;
6119 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
6120 ValueType OpTy, ValueType ElemTy,
6121 Operand OpImm, ValueType OpNTy,
6122 ValueType ExTy, Operand OpNImm> {
6124 def : Pat<(ResTy (vector_insert (ResTy undef),
6125 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
6126 (neon_uimm0_bare:$Imm))),
6127 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
6129 def : Pat<(ResTy (vector_insert (ResTy undef),
6130 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
6133 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6137 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
6138 ValueType OpTy, ValueType ElemTy,
6139 Operand OpImm, ValueType OpNTy,
6140 ValueType ExTy, Operand OpNImm> {
6142 def : Pat<(ResTy (scalar_to_vector
6143 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
6144 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
6146 def : Pat<(ResTy (scalar_to_vector
6147 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
6149 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6153 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
6155 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
6156 v1i64, v2i64, i64, neon_uimm1_bare,
6157 v1i64, v2i64, neon_uimm0_bare>;
6158 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
6159 v1i32, v4i32, i32, neon_uimm2_bare,
6160 v2i32, v4i32, neon_uimm1_bare>;
6161 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
6162 v1i16, v8i16, i32, neon_uimm3_bare,
6163 v4i16, v8i16, neon_uimm2_bare>;
6164 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
6165 v1i8, v16i8, i32, neon_uimm4_bare,
6166 v8i8, v16i8, neon_uimm3_bare>;
6167 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
6168 v1i64, v2i64, i64, neon_uimm1_bare,
6169 v1i64, v2i64, neon_uimm0_bare>;
6170 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
6171 v1i32, v4i32, i32, neon_uimm2_bare,
6172 v2i32, v4i32, neon_uimm1_bare>;
6173 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
6174 v1i16, v8i16, i32, neon_uimm3_bare,
6175 v4i16, v8i16, neon_uimm2_bare>;
6176 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
6177 v1i8, v16i8, i32, neon_uimm4_bare,
6178 v8i8, v16i8, neon_uimm3_bare>;
6180 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
6181 Instruction DUPI, Operand OpImm,
6182 RegisterClass ResRC> {
6183 def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
6184 (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
6187 // Aliases for Scalar copy - DUP element (scalar)
6188 // FIXME: This is actually the preferred syntax but TableGen can't deal with
6189 // custom printing of aliases.
6190 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
6191 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
6192 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
6193 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
6195 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
6197 def : Pat<(ResTy (GetLow VPR128:$Rn)),
6198 (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
6199 def : Pat<(ResTy (GetHigh VPR128:$Rn)),
6200 (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
6203 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
6204 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
6205 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
6206 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
6207 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
6208 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
6210 //===----------------------------------------------------------------------===//
6211 // Non-Instruction Patterns
6212 //===----------------------------------------------------------------------===//
6214 // 64-bit vector bitcasts...
6216 def : Pat<(v1i64 (bitconvert (v8i8 VPR64:$src))), (v1i64 VPR64:$src)>;
6217 def : Pat<(v2f32 (bitconvert (v8i8 VPR64:$src))), (v2f32 VPR64:$src)>;
6218 def : Pat<(v2i32 (bitconvert (v8i8 VPR64:$src))), (v2i32 VPR64:$src)>;
6219 def : Pat<(v4i16 (bitconvert (v8i8 VPR64:$src))), (v4i16 VPR64:$src)>;
6221 def : Pat<(v1i64 (bitconvert (v4i16 VPR64:$src))), (v1i64 VPR64:$src)>;
6222 def : Pat<(v2i32 (bitconvert (v4i16 VPR64:$src))), (v2i32 VPR64:$src)>;
6223 def : Pat<(v2f32 (bitconvert (v4i16 VPR64:$src))), (v2f32 VPR64:$src)>;
6224 def : Pat<(v8i8 (bitconvert (v4i16 VPR64:$src))), (v8i8 VPR64:$src)>;
6226 def : Pat<(v1i64 (bitconvert (v2i32 VPR64:$src))), (v1i64 VPR64:$src)>;
6227 def : Pat<(v2f32 (bitconvert (v2i32 VPR64:$src))), (v2f32 VPR64:$src)>;
6228 def : Pat<(v4i16 (bitconvert (v2i32 VPR64:$src))), (v4i16 VPR64:$src)>;
6229 def : Pat<(v8i8 (bitconvert (v2i32 VPR64:$src))), (v8i8 VPR64:$src)>;
6231 def : Pat<(v1i64 (bitconvert (v2f32 VPR64:$src))), (v1i64 VPR64:$src)>;
6232 def : Pat<(v2i32 (bitconvert (v2f32 VPR64:$src))), (v2i32 VPR64:$src)>;
6233 def : Pat<(v4i16 (bitconvert (v2f32 VPR64:$src))), (v4i16 VPR64:$src)>;
6234 def : Pat<(v8i8 (bitconvert (v2f32 VPR64:$src))), (v8i8 VPR64:$src)>;
6236 def : Pat<(v2f32 (bitconvert (v1i64 VPR64:$src))), (v2f32 VPR64:$src)>;
6237 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6238 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6239 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6241 def : Pat<(v1i64 (bitconvert (v1f64 VPR64:$src))), (v1i64 VPR64:$src)>;
6242 def : Pat<(v2f32 (bitconvert (v1f64 VPR64:$src))), (v2f32 VPR64:$src)>;
6243 def : Pat<(v2i32 (bitconvert (v1f64 VPR64:$src))), (v2i32 VPR64:$src)>;
6244 def : Pat<(v4i16 (bitconvert (v1f64 VPR64:$src))), (v4i16 VPR64:$src)>;
6245 def : Pat<(v8i8 (bitconvert (v1f64 VPR64:$src))), (v8i8 VPR64:$src)>;
6246 def : Pat<(f64 (bitconvert (v1f64 VPR64:$src))), (f64 VPR64:$src)>;
6248 def : Pat<(v1f64 (bitconvert (v1i64 VPR64:$src))), (v1f64 VPR64:$src)>;
6249 def : Pat<(v1f64 (bitconvert (v2f32 VPR64:$src))), (v1f64 VPR64:$src)>;
6250 def : Pat<(v1f64 (bitconvert (v2i32 VPR64:$src))), (v1f64 VPR64:$src)>;
6251 def : Pat<(v1f64 (bitconvert (v4i16 VPR64:$src))), (v1f64 VPR64:$src)>;
6252 def : Pat<(v1f64 (bitconvert (v8i8 VPR64:$src))), (v1f64 VPR64:$src)>;
6253 def : Pat<(v1f64 (bitconvert (f64 VPR64:$src))), (v1f64 VPR64:$src)>;
6255 // ..and 128-bit vector bitcasts...
6257 def : Pat<(v2f64 (bitconvert (v16i8 VPR128:$src))), (v2f64 VPR128:$src)>;
6258 def : Pat<(v2i64 (bitconvert (v16i8 VPR128:$src))), (v2i64 VPR128:$src)>;
6259 def : Pat<(v4f32 (bitconvert (v16i8 VPR128:$src))), (v4f32 VPR128:$src)>;
6260 def : Pat<(v4i32 (bitconvert (v16i8 VPR128:$src))), (v4i32 VPR128:$src)>;
6261 def : Pat<(v8i16 (bitconvert (v16i8 VPR128:$src))), (v8i16 VPR128:$src)>;
6263 def : Pat<(v2f64 (bitconvert (v8i16 VPR128:$src))), (v2f64 VPR128:$src)>;
6264 def : Pat<(v2i64 (bitconvert (v8i16 VPR128:$src))), (v2i64 VPR128:$src)>;
6265 def : Pat<(v4i32 (bitconvert (v8i16 VPR128:$src))), (v4i32 VPR128:$src)>;
6266 def : Pat<(v4f32 (bitconvert (v8i16 VPR128:$src))), (v4f32 VPR128:$src)>;
6267 def : Pat<(v16i8 (bitconvert (v8i16 VPR128:$src))), (v16i8 VPR128:$src)>;
6269 def : Pat<(v2f64 (bitconvert (v4i32 VPR128:$src))), (v2f64 VPR128:$src)>;
6270 def : Pat<(v2i64 (bitconvert (v4i32 VPR128:$src))), (v2i64 VPR128:$src)>;
6271 def : Pat<(v4f32 (bitconvert (v4i32 VPR128:$src))), (v4f32 VPR128:$src)>;
6272 def : Pat<(v8i16 (bitconvert (v4i32 VPR128:$src))), (v8i16 VPR128:$src)>;
6273 def : Pat<(v16i8 (bitconvert (v4i32 VPR128:$src))), (v16i8 VPR128:$src)>;
6275 def : Pat<(v2f64 (bitconvert (v4f32 VPR128:$src))), (v2f64 VPR128:$src)>;
6276 def : Pat<(v2i64 (bitconvert (v4f32 VPR128:$src))), (v2i64 VPR128:$src)>;
6277 def : Pat<(v4i32 (bitconvert (v4f32 VPR128:$src))), (v4i32 VPR128:$src)>;
6278 def : Pat<(v8i16 (bitconvert (v4f32 VPR128:$src))), (v8i16 VPR128:$src)>;
6279 def : Pat<(v16i8 (bitconvert (v4f32 VPR128:$src))), (v16i8 VPR128:$src)>;
6281 def : Pat<(v2f64 (bitconvert (v2i64 VPR128:$src))), (v2f64 VPR128:$src)>;
6282 def : Pat<(v4f32 (bitconvert (v2i64 VPR128:$src))), (v4f32 VPR128:$src)>;
6283 def : Pat<(v4i32 (bitconvert (v2i64 VPR128:$src))), (v4i32 VPR128:$src)>;
6284 def : Pat<(v8i16 (bitconvert (v2i64 VPR128:$src))), (v8i16 VPR128:$src)>;
6285 def : Pat<(v16i8 (bitconvert (v2i64 VPR128:$src))), (v16i8 VPR128:$src)>;
6287 def : Pat<(v2i64 (bitconvert (v2f64 VPR128:$src))), (v2i64 VPR128:$src)>;
6288 def : Pat<(v4f32 (bitconvert (v2f64 VPR128:$src))), (v4f32 VPR128:$src)>;
6289 def : Pat<(v4i32 (bitconvert (v2f64 VPR128:$src))), (v4i32 VPR128:$src)>;
6290 def : Pat<(v8i16 (bitconvert (v2f64 VPR128:$src))), (v8i16 VPR128:$src)>;
6291 def : Pat<(v16i8 (bitconvert (v2f64 VPR128:$src))), (v16i8 VPR128:$src)>;
6293 // ...and scalar bitcasts...
6294 def : Pat<(f16 (bitconvert (v1i16 FPR16:$src))), (f16 FPR16:$src)>;
6295 def : Pat<(f32 (bitconvert (v1i32 FPR32:$src))), (f32 FPR32:$src)>;
6296 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
6297 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
6299 def : Pat<(i64 (bitconvert (v1i64 FPR64:$src))), (FMOVxd $src)>;
6300 def : Pat<(i64 (bitconvert (v1f64 FPR64:$src))), (FMOVxd $src)>;
6301 def : Pat<(i64 (bitconvert (v2i32 FPR64:$src))), (FMOVxd $src)>;
6302 def : Pat<(i64 (bitconvert (v2f32 FPR64:$src))), (FMOVxd $src)>;
6303 def : Pat<(i64 (bitconvert (v4i16 FPR64:$src))), (FMOVxd $src)>;
6304 def : Pat<(i64 (bitconvert (v8i8 FPR64:$src))), (FMOVxd $src)>;
6306 def : Pat<(i32 (bitconvert (v1i32 FPR32:$src))), (FMOVws $src)>;
6308 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6309 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6310 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6312 def : Pat<(f64 (bitconvert (v8i8 VPR64:$src))), (f64 VPR64:$src)>;
6313 def : Pat<(f64 (bitconvert (v4i16 VPR64:$src))), (f64 VPR64:$src)>;
6314 def : Pat<(f64 (bitconvert (v2i32 VPR64:$src))), (f64 VPR64:$src)>;
6315 def : Pat<(f64 (bitconvert (v2f32 VPR64:$src))), (f64 VPR64:$src)>;
6316 def : Pat<(f64 (bitconvert (v1i64 VPR64:$src))), (f64 VPR64:$src)>;
6318 def : Pat<(f128 (bitconvert (v16i8 VPR128:$src))), (f128 VPR128:$src)>;
6319 def : Pat<(f128 (bitconvert (v8i16 VPR128:$src))), (f128 VPR128:$src)>;
6320 def : Pat<(f128 (bitconvert (v4i32 VPR128:$src))), (f128 VPR128:$src)>;
6321 def : Pat<(f128 (bitconvert (v2i64 VPR128:$src))), (f128 VPR128:$src)>;
6322 def : Pat<(f128 (bitconvert (v4f32 VPR128:$src))), (f128 VPR128:$src)>;
6323 def : Pat<(f128 (bitconvert (v2f64 VPR128:$src))), (f128 VPR128:$src)>;
6325 def : Pat<(v1i16 (bitconvert (f16 FPR16:$src))), (v1i16 FPR16:$src)>;
6326 def : Pat<(v1i32 (bitconvert (f32 FPR32:$src))), (v1i32 FPR32:$src)>;
6327 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6328 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
6330 def : Pat<(v1i64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6331 def : Pat<(v1f64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6332 def : Pat<(v2i32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6333 def : Pat<(v2f32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6334 def : Pat<(v4i16 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6335 def : Pat<(v8i8 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6337 def : Pat<(v1i32 (bitconvert (i32 GPR32:$src))), (FMOVsw $src)>;
6339 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
6340 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
6341 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
6342 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
6343 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6345 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
6346 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
6347 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
6348 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
6349 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
6350 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
6352 // Scalar Three Same
6354 def neon_uimm3 : Operand<i64>,
6355 ImmLeaf<i64, [{return Imm < 8;}]> {
6356 let ParserMatchClass = uimm3_asmoperand;
6357 let PrintMethod = "printUImmHexOperand";
6360 def neon_uimm4 : Operand<i64>,
6361 ImmLeaf<i64, [{return Imm < 16;}]> {
6362 let ParserMatchClass = uimm4_asmoperand;
6363 let PrintMethod = "printUImmHexOperand";
6367 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6368 string OpS, RegisterOperand OpVPR, Operand OpImm>
6369 : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6370 (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6371 asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6372 ", $Rm." # OpS # ", $Index",
6378 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6379 VPR64, neon_uimm3> {
6380 let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6383 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6384 VPR128, neon_uimm4> {
6385 let Inst{14-11} = Index;
6388 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6390 : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6392 (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6394 def : NI_Extract<v8i8, VPR64, EXTvvvi_8b, neon_uimm3>;
6395 def : NI_Extract<v4i16, VPR64, EXTvvvi_8b, neon_uimm3>;
6396 def : NI_Extract<v2i32, VPR64, EXTvvvi_8b, neon_uimm3>;
6397 def : NI_Extract<v1i64, VPR64, EXTvvvi_8b, neon_uimm3>;
6398 def : NI_Extract<v2f32, VPR64, EXTvvvi_8b, neon_uimm3>;
6399 def : NI_Extract<v1f64, VPR64, EXTvvvi_8b, neon_uimm3>;
6400 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6401 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6402 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6403 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6404 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6405 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6408 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6409 string asmop, string OpS, RegisterOperand OpVPR,
6410 RegisterOperand VecList>
6411 : NeonI_TBL<q, op2, len, op,
6412 (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6413 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6417 // The vectors in look up table are always 16b
6418 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6419 def _8b : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6420 !cast<RegisterOperand>(List # "16B_operand")>;
6422 def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6423 !cast<RegisterOperand>(List # "16B_operand")>;
6426 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6427 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6428 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6429 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6431 // Table lookup extention
6432 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6433 string asmop, string OpS, RegisterOperand OpVPR,
6434 RegisterOperand VecList>
6435 : NeonI_TBL<q, op2, len, op,
6436 (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6437 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6440 let Constraints = "$src = $Rd";
6443 // The vectors in look up table are always 16b
6444 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6445 def _8b : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6446 !cast<RegisterOperand>(List # "16B_operand")>;
6448 def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6449 !cast<RegisterOperand>(List # "16B_operand")>;
6452 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6453 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6454 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6455 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6457 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6458 RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6459 : NeonI_copy<0b1, 0b0, 0b0011,
6460 (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6461 asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6462 [(set (ResTy VPR128:$Rd),
6463 (ResTy (vector_insert
6464 (ResTy VPR128:$src),
6469 let Constraints = "$src = $Rd";
6472 //Insert element (vector, from main)
6473 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6475 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6477 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6479 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6481 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6483 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6485 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6487 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6490 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6491 (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6492 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6493 (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6494 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6495 (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6496 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6497 (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6499 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6500 RegisterClass OpGPR, ValueType OpTy,
6501 Operand OpImm, Instruction INS>
6502 : Pat<(ResTy (vector_insert
6506 (ResTy (EXTRACT_SUBREG
6507 (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6508 OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6510 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6511 neon_uimm3_bare, INSbw>;
6512 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6513 neon_uimm2_bare, INShw>;
6514 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6515 neon_uimm1_bare, INSsw>;
6516 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6517 neon_uimm0_bare, INSdx>;
6519 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6520 : NeonI_insert<0b1, 0b1,
6521 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6522 ResImm:$Immd, ResImm:$Immn),
6523 asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6526 let Constraints = "$src = $Rd";
6531 //Insert element (vector, from element)
6532 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6533 let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6534 let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6536 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6537 let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6538 let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6539 // bit 11 is unspecified, but should be set to zero.
6541 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6542 let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6543 let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6544 // bits 11-12 are unspecified, but should be set to zero.
6546 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6547 let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6548 let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6549 // bits 11-13 are unspecified, but should be set to zero.
6552 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6553 (INSELb VPR128:$Rd, VPR128:$Rn,
6554 neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6555 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6556 (INSELh VPR128:$Rd, VPR128:$Rn,
6557 neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6558 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6559 (INSELs VPR128:$Rd, VPR128:$Rn,
6560 neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6561 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6562 (INSELd VPR128:$Rd, VPR128:$Rn,
6563 neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6565 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6566 ValueType MidTy, Operand StImm, Operand NaImm,
6568 def : Pat<(ResTy (vector_insert
6569 (ResTy VPR128:$src),
6570 (MidTy (vector_extract
6574 (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6575 StImm:$Immd, StImm:$Immn)>;
6577 def : Pat <(ResTy (vector_insert
6578 (ResTy VPR128:$src),
6579 (MidTy (vector_extract
6583 (INS (ResTy VPR128:$src),
6584 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6585 StImm:$Immd, NaImm:$Immn)>;
6587 def : Pat <(NaTy (vector_insert
6589 (MidTy (vector_extract
6593 (NaTy (EXTRACT_SUBREG
6595 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6597 NaImm:$Immd, StImm:$Immn)),
6600 def : Pat <(NaTy (vector_insert
6602 (MidTy (vector_extract
6606 (NaTy (EXTRACT_SUBREG
6608 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6609 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6610 NaImm:$Immd, NaImm:$Immn)),
6614 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6615 neon_uimm1_bare, INSELs>;
6616 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6617 neon_uimm0_bare, INSELd>;
6618 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6619 neon_uimm3_bare, INSELb>;
6620 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6621 neon_uimm2_bare, INSELh>;
6622 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6623 neon_uimm1_bare, INSELs>;
6624 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6625 neon_uimm0_bare, INSELd>;
6627 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6629 RegisterClass OpFPR, Operand ResImm,
6630 SubRegIndex SubIndex, Instruction INS> {
6631 def : Pat <(ResTy (vector_insert
6632 (ResTy VPR128:$src),
6635 (INS (ResTy VPR128:$src),
6636 (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6640 def : Pat <(NaTy (vector_insert
6644 (NaTy (EXTRACT_SUBREG
6646 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6647 (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6653 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6655 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6658 class NeonI_SMOV<string asmop, string Res, bit Q,
6659 ValueType OpTy, ValueType eleTy,
6660 Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6661 : NeonI_copy<Q, 0b0, 0b0101,
6662 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6663 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6664 [(set (ResTy ResGPR:$Rd),
6666 (ResTy (vector_extract
6667 (OpTy VPR128:$Rn), (OpImm:$Imm))),
6673 //Signed integer move (main, from element)
6674 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6676 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6678 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6680 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6682 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6684 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6686 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6688 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6690 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6692 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6695 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6696 ValueType eleTy, Operand StImm, Operand NaImm,
6697 Instruction SMOVI> {
6698 def : Pat<(i64 (sext_inreg
6700 (i32 (vector_extract
6701 (StTy VPR128:$Rn), (StImm:$Imm))))),
6703 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6705 def : Pat<(i64 (sext
6706 (i32 (vector_extract
6707 (StTy VPR128:$Rn), (StImm:$Imm))))),
6708 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6710 def : Pat<(i64 (sext_inreg
6711 (i64 (vector_extract
6712 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6714 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6717 def : Pat<(i64 (sext_inreg
6719 (i32 (vector_extract
6720 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6722 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6725 def : Pat<(i64 (sext
6726 (i32 (vector_extract
6727 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6728 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6732 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6733 neon_uimm3_bare, SMOVxb>;
6734 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6735 neon_uimm2_bare, SMOVxh>;
6736 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6737 neon_uimm1_bare, SMOVxs>;
6739 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6740 ValueType eleTy, Operand StImm, Operand NaImm,
6742 : Pat<(i32 (sext_inreg
6743 (i32 (vector_extract
6744 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6746 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6749 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6750 neon_uimm3_bare, SMOVwb>;
6751 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6752 neon_uimm2_bare, SMOVwh>;
6754 class NeonI_UMOV<string asmop, string Res, bit Q,
6755 ValueType OpTy, Operand OpImm,
6756 RegisterClass ResGPR, ValueType ResTy>
6757 : NeonI_copy<Q, 0b0, 0b0111,
6758 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6759 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6760 [(set (ResTy ResGPR:$Rd),
6761 (ResTy (vector_extract
6762 (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6767 //Unsigned integer move (main, from element)
6768 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6770 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6772 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6774 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6776 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6778 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6780 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6782 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6785 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6786 (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6787 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6788 (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6790 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6791 Operand StImm, Operand NaImm,
6793 : Pat<(ResTy (vector_extract
6794 (NaTy VPR64:$Rn), NaImm:$Imm)),
6795 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6798 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6799 neon_uimm3_bare, UMOVwb>;
6800 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6801 neon_uimm2_bare, UMOVwh>;
6802 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6803 neon_uimm1_bare, UMOVws>;
6806 (i32 (vector_extract
6807 (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6809 (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6812 (i32 (vector_extract
6813 (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6815 (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6817 def : Pat<(i64 (zext
6818 (i32 (vector_extract
6819 (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6820 (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6823 (i32 (vector_extract
6824 (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6826 (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6827 neon_uimm3_bare:$Imm)>;
6830 (i32 (vector_extract
6831 (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6833 (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6834 neon_uimm2_bare:$Imm)>;
6836 def : Pat<(i64 (zext
6837 (i32 (vector_extract
6838 (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6839 (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6840 neon_uimm0_bare:$Imm)>;
6842 // Additional copy patterns for scalar types
6843 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6845 (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6847 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6849 (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6851 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6852 (FMOVws FPR32:$Rn)>;
6854 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6855 (FMOVxd FPR64:$Rn)>;
6857 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6860 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6861 (v1i8 (EXTRACT_SUBREG (v16i8
6862 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6865 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6866 (v1i16 (EXTRACT_SUBREG (v8i16
6867 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6870 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6873 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6876 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
6877 (v8i8 (EXTRACT_SUBREG (v16i8
6878 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6881 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
6882 (v4i16 (EXTRACT_SUBREG (v8i16
6883 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6886 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6887 (v2i32 (EXTRACT_SUBREG (v16i8
6888 (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6891 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
6892 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6894 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
6895 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6897 def : Pat<(v4i32 (scalar_to_vector GPR32:$Rn)),
6898 (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6900 def : Pat<(v2i64 (scalar_to_vector GPR64:$Rn)),
6901 (INSdx (v2i64 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6903 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
6904 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>;
6905 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
6906 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>;
6908 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6911 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6912 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6913 (f64 FPR64:$src), sub_64)>;
6915 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane, string rnlane,
6916 RegisterOperand ResVPR, Operand OpImm>
6917 : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6918 (ins VPR128:$Rn, OpImm:$Imm),
6919 asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6925 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6927 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6930 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6932 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6935 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6937 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6940 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6942 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6945 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6947 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6950 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6952 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6955 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6957 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6960 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6961 ValueType OpTy,ValueType NaTy,
6962 ValueType ExTy, Operand OpLImm,
6964 def : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6965 (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6967 def : Pat<(ResTy (Neon_vduplane
6968 (NaTy VPR64:$Rn), OpNImm:$Imm)),
6970 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6972 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6973 neon_uimm4_bare, neon_uimm3_bare>;
6974 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6975 neon_uimm4_bare, neon_uimm3_bare>;
6976 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6977 neon_uimm3_bare, neon_uimm2_bare>;
6978 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6979 neon_uimm3_bare, neon_uimm2_bare>;
6980 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6981 neon_uimm2_bare, neon_uimm1_bare>;
6982 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6983 neon_uimm2_bare, neon_uimm1_bare>;
6984 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6985 neon_uimm1_bare, neon_uimm0_bare>;
6986 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6987 neon_uimm2_bare, neon_uimm1_bare>;
6988 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6989 neon_uimm2_bare, neon_uimm1_bare>;
6990 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6991 neon_uimm1_bare, neon_uimm0_bare>;
6993 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6995 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6997 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6999 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
7001 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
7003 (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
7006 class NeonI_DUP<bit Q, string asmop, string rdlane,
7007 RegisterOperand ResVPR, ValueType ResTy,
7008 RegisterClass OpGPR, ValueType OpTy>
7009 : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
7010 asmop # "\t$Rd" # rdlane # ", $Rn",
7011 [(set (ResTy ResVPR:$Rd),
7012 (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
7015 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
7016 let Inst{20-16} = 0b00001;
7017 // bits 17-20 are unspecified, but should be set to zero.
7020 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
7021 let Inst{20-16} = 0b00010;
7022 // bits 18-20 are unspecified, but should be set to zero.
7025 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
7026 let Inst{20-16} = 0b00100;
7027 // bits 19-20 are unspecified, but should be set to zero.
7030 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
7031 let Inst{20-16} = 0b01000;
7032 // bit 20 is unspecified, but should be set to zero.
7035 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
7036 let Inst{20-16} = 0b00001;
7037 // bits 17-20 are unspecified, but should be set to zero.
7040 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
7041 let Inst{20-16} = 0b00010;
7042 // bits 18-20 are unspecified, but should be set to zero.
7045 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
7046 let Inst{20-16} = 0b00100;
7047 // bits 19-20 are unspecified, but should be set to zero.
7050 // patterns for CONCAT_VECTORS
7051 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
7052 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
7053 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
7054 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
7056 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7057 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
7060 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
7062 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7066 defm : Concat_Vector_Pattern<v16i8, v8i8>;
7067 defm : Concat_Vector_Pattern<v8i16, v4i16>;
7068 defm : Concat_Vector_Pattern<v4i32, v2i32>;
7069 defm : Concat_Vector_Pattern<v2i64, v1i64>;
7070 defm : Concat_Vector_Pattern<v4f32, v2f32>;
7071 defm : Concat_Vector_Pattern<v2f64, v1f64>;
7073 def : Pat<(v2i32 (concat_vectors (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rn))),
7074 (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>;
7075 def : Pat<(v2i32 (concat_vectors undef, (v1i32 FPR32:$Rn))),
7076 (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>;
7078 //patterns for EXTRACT_SUBVECTOR
7079 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
7080 (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7081 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
7082 (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7083 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
7084 (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7085 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
7086 (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7087 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
7088 (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7089 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
7090 (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7092 // The followings are for instruction class (3V Elem)
7096 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
7097 string asmop, string ResS, string OpS, string EleOpS,
7098 Operand OpImm, RegisterOperand ResVPR,
7099 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7100 : NeonI_2VElem<q, u, size, opcode,
7101 (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
7102 EleOpVPR:$Re, OpImm:$Index),
7103 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7104 ", $Re." # EleOpS # "[$Index]",
7110 let Constraints = "$src = $Rd";
7113 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
7114 // vector register class for element is always 128-bit to cover the max index
7115 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7116 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7117 let Inst{11} = {Index{1}};
7118 let Inst{21} = {Index{0}};
7119 let Inst{20-16} = Re;
7122 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7123 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7124 let Inst{11} = {Index{1}};
7125 let Inst{21} = {Index{0}};
7126 let Inst{20-16} = Re;
7129 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7130 def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7131 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7132 let Inst{11} = {Index{2}};
7133 let Inst{21} = {Index{1}};
7134 let Inst{20} = {Index{0}};
7135 let Inst{19-16} = Re{3-0};
7138 def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7139 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7140 let Inst{11} = {Index{2}};
7141 let Inst{21} = {Index{1}};
7142 let Inst{20} = {Index{0}};
7143 let Inst{19-16} = Re{3-0};
7147 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
7148 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
7150 // Pattern for lane in 128-bit vector
7151 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7152 RegisterOperand ResVPR, RegisterOperand OpVPR,
7153 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
7155 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
7156 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7157 (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7159 // Pattern for lane in 64-bit vector
7160 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7161 RegisterOperand ResVPR, RegisterOperand OpVPR,
7162 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
7164 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
7165 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7166 (INST ResVPR:$src, OpVPR:$Rn,
7167 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7169 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
7171 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7172 op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
7174 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7175 op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
7177 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7178 op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7180 def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7181 op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7183 // Index can only be half of the max value for lane in 64-bit vector
7185 def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7186 op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
7188 def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7189 op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7192 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
7193 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
7195 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
7196 string asmop, string ResS, string OpS, string EleOpS,
7197 Operand OpImm, RegisterOperand ResVPR,
7198 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7199 : NeonI_2VElem<q, u, size, opcode,
7200 (outs ResVPR:$Rd), (ins OpVPR:$Rn,
7201 EleOpVPR:$Re, OpImm:$Index),
7202 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7203 ", $Re." # EleOpS # "[$Index]",
7210 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
7211 // vector register class for element is always 128-bit to cover the max index
7212 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7213 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7214 let Inst{11} = {Index{1}};
7215 let Inst{21} = {Index{0}};
7216 let Inst{20-16} = Re;
7219 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7220 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7221 let Inst{11} = {Index{1}};
7222 let Inst{21} = {Index{0}};
7223 let Inst{20-16} = Re;
7226 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7227 def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7228 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7229 let Inst{11} = {Index{2}};
7230 let Inst{21} = {Index{1}};
7231 let Inst{20} = {Index{0}};
7232 let Inst{19-16} = Re{3-0};
7235 def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7236 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7237 let Inst{11} = {Index{2}};
7238 let Inst{21} = {Index{1}};
7239 let Inst{20} = {Index{0}};
7240 let Inst{19-16} = Re{3-0};
7244 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
7245 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
7246 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
7248 // Pattern for lane in 128-bit vector
7249 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7250 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7251 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7252 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7253 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7254 (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7256 // Pattern for lane in 64-bit vector
7257 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7258 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7259 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7260 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7261 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7263 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7265 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
7266 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7267 op, VPR64, VPR128, v2i32, v2i32, v4i32>;
7269 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7270 op, VPR128, VPR128, v4i32, v4i32, v4i32>;
7272 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7273 op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7275 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7276 op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7278 // Index can only be half of the max value for lane in 64-bit vector
7280 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7281 op, VPR64, VPR64, v2i32, v2i32, v2i32>;
7283 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7284 op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7287 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
7288 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
7289 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
7293 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
7294 // vector register class for element is always 128-bit to cover the max index
7295 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7296 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7297 let Inst{11} = {Index{1}};
7298 let Inst{21} = {Index{0}};
7299 let Inst{20-16} = Re;
7302 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7303 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7304 let Inst{11} = {Index{1}};
7305 let Inst{21} = {Index{0}};
7306 let Inst{20-16} = Re;
7309 // _1d2d doesn't exist!
7311 def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7312 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7313 let Inst{11} = {Index{0}};
7315 let Inst{20-16} = Re;
7319 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
7320 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
7322 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
7323 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7324 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
7325 SDPatternOperator coreop>
7326 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7327 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
7329 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
7331 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
7332 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7333 op, VPR64, VPR128, v2f32, v2f32, v4f32>;
7335 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7336 op, VPR128, VPR128, v4f32, v4f32, v4f32>;
7338 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7339 op, VPR128, VPR128, v2f64, v2f64, v2f64>;
7341 // Index can only be half of the max value for lane in 64-bit vector
7343 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7344 op, VPR64, VPR64, v2f32, v2f32, v2f32>;
7346 def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7347 op, VPR128, VPR64, v2f64, v2f64, v1f64,
7348 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7351 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
7352 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
7354 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
7355 (v2f32 VPR64:$Rn))),
7356 (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7358 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
7359 (v4f32 VPR128:$Rn))),
7360 (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7362 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
7363 (v2f64 VPR128:$Rn))),
7364 (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7366 // The followings are patterns using fma
7367 // -ffp-contract=fast generates fma
7369 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7370 // vector register class for element is always 128-bit to cover the max index
7371 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7372 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7373 let Inst{11} = {Index{1}};
7374 let Inst{21} = {Index{0}};
7375 let Inst{20-16} = Re;
7378 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7379 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7380 let Inst{11} = {Index{1}};
7381 let Inst{21} = {Index{0}};
7382 let Inst{20-16} = Re;
7385 // _1d2d doesn't exist!
7387 def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7388 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7389 let Inst{11} = {Index{0}};
7391 let Inst{20-16} = Re;
7395 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7396 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7398 // Pattern for lane in 128-bit vector
7399 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7400 RegisterOperand ResVPR, RegisterOperand OpVPR,
7401 ValueType ResTy, ValueType OpTy,
7402 SDPatternOperator coreop>
7403 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7404 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7405 (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7407 // Pattern for lane 0
7408 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7409 RegisterOperand ResVPR, ValueType ResTy>
7410 : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7411 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7412 (ResTy ResVPR:$src))),
7413 (INST ResVPR:$src, ResVPR:$Rn,
7414 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7416 // Pattern for lane in 64-bit vector
7417 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7418 RegisterOperand ResVPR, RegisterOperand OpVPR,
7419 ValueType ResTy, ValueType OpTy,
7420 SDPatternOperator coreop>
7421 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7422 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7423 (INST ResVPR:$src, ResVPR:$Rn,
7424 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7426 // Pattern for lane in 64-bit vector
7427 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7428 SDPatternOperator op,
7429 RegisterOperand ResVPR, RegisterOperand OpVPR,
7430 ValueType ResTy, ValueType OpTy,
7431 SDPatternOperator coreop>
7432 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7433 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7434 (INST ResVPR:$src, ResVPR:$Rn,
7435 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7438 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7439 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7440 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7441 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7443 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7446 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7447 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7448 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7450 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7453 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7454 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7455 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7457 // Index can only be half of the max value for lane in 64-bit vector
7459 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7460 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7461 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7463 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7464 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7465 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7468 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7470 // Pattern for lane 0
7471 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7472 RegisterOperand ResVPR, ValueType ResTy>
7473 : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7474 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7475 (ResTy ResVPR:$src))),
7476 (INST ResVPR:$src, ResVPR:$Rn,
7477 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7479 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7481 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7482 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7483 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7485 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7486 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7487 BinOpFrag<(Neon_vduplane
7488 (fneg node:$LHS), node:$RHS)>>;
7490 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7493 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7494 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7495 BinOpFrag<(fneg (Neon_vduplane
7496 node:$LHS, node:$RHS))>>;
7498 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7499 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7500 BinOpFrag<(Neon_vduplane
7501 (fneg node:$LHS), node:$RHS)>>;
7503 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7506 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7507 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7508 BinOpFrag<(fneg (Neon_vduplane
7509 node:$LHS, node:$RHS))>>;
7511 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7512 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7513 BinOpFrag<(Neon_vduplane
7514 (fneg node:$LHS), node:$RHS)>>;
7516 // Index can only be half of the max value for lane in 64-bit vector
7518 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7519 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7520 BinOpFrag<(fneg (Neon_vduplane
7521 node:$LHS, node:$RHS))>>;
7523 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7524 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7525 BinOpFrag<(Neon_vduplane
7526 (fneg node:$LHS), node:$RHS)>>;
7528 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7529 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7530 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7532 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7533 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7534 BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7536 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7537 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7538 BinOpFrag<(fneg (Neon_combine_2d
7539 node:$LHS, node:$RHS))>>;
7541 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7542 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7543 BinOpFrag<(Neon_combine_2d
7544 (fneg node:$LHS), (fneg node:$RHS))>>;
7547 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7549 // Variant 3: Long type
7550 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7551 // SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7553 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7554 // vector register class for element is always 128-bit to cover the max index
7555 def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7556 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7557 let Inst{11} = {Index{1}};
7558 let Inst{21} = {Index{0}};
7559 let Inst{20-16} = Re;
7562 def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7563 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7564 let Inst{11} = {Index{1}};
7565 let Inst{21} = {Index{0}};
7566 let Inst{20-16} = Re;
7569 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7570 def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7571 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7572 let Inst{11} = {Index{2}};
7573 let Inst{21} = {Index{1}};
7574 let Inst{20} = {Index{0}};
7575 let Inst{19-16} = Re{3-0};
7578 def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7579 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7580 let Inst{11} = {Index{2}};
7581 let Inst{21} = {Index{1}};
7582 let Inst{20} = {Index{0}};
7583 let Inst{19-16} = Re{3-0};
7587 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7588 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7589 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7590 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7591 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7592 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7594 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7595 // vector register class for element is always 128-bit to cover the max index
7596 def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7597 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7598 let Inst{11} = {Index{1}};
7599 let Inst{21} = {Index{0}};
7600 let Inst{20-16} = Re;
7603 def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7604 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7605 let Inst{11} = {Index{1}};
7606 let Inst{21} = {Index{0}};
7607 let Inst{20-16} = Re;
7610 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7611 def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7612 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7613 let Inst{11} = {Index{2}};
7614 let Inst{21} = {Index{1}};
7615 let Inst{20} = {Index{0}};
7616 let Inst{19-16} = Re{3-0};
7619 def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7620 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7621 let Inst{11} = {Index{2}};
7622 let Inst{21} = {Index{1}};
7623 let Inst{20} = {Index{0}};
7624 let Inst{19-16} = Re{3-0};
7628 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7629 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7630 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7632 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7635 // Pattern for lane in 128-bit vector
7636 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7637 RegisterOperand EleOpVPR, ValueType ResTy,
7638 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7639 SDPatternOperator hiop>
7640 : Pat<(ResTy (op (ResTy VPR128:$src),
7641 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7642 (HalfOpTy (Neon_vduplane
7643 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7644 (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7646 // Pattern for lane in 64-bit vector
7647 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7648 RegisterOperand EleOpVPR, ValueType ResTy,
7649 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7650 SDPatternOperator hiop>
7651 : Pat<(ResTy (op (ResTy VPR128:$src),
7652 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7653 (HalfOpTy (Neon_vduplane
7654 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7655 (INST VPR128:$src, VPR128:$Rn,
7656 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7658 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7659 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7660 SDPatternOperator hiop, Instruction DupInst>
7661 : Pat<(ResTy (op (ResTy VPR128:$src),
7662 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7663 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7664 (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7666 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7667 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7668 op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7670 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7671 op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7673 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7674 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7676 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7677 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7679 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7680 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7682 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7683 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7685 // Index can only be half of the max value for lane in 64-bit vector
7687 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7688 op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7690 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7691 op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7693 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7694 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7696 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7697 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7700 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7701 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7702 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7703 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7705 // Pattern for lane in 128-bit vector
7706 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7707 RegisterOperand EleOpVPR, ValueType ResTy,
7708 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7709 SDPatternOperator hiop>
7711 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7712 (HalfOpTy (Neon_vduplane
7713 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7714 (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7716 // Pattern for lane in 64-bit vector
7717 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7718 RegisterOperand EleOpVPR, ValueType ResTy,
7719 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7720 SDPatternOperator hiop>
7722 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7723 (HalfOpTy (Neon_vduplane
7724 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7726 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7728 // Pattern for fixed lane 0
7729 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7730 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7731 SDPatternOperator hiop, Instruction DupInst>
7733 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7734 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7735 (INST VPR128:$Rn, (DupInst $Re), 0)>;
7737 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7738 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7739 op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7741 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7742 op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7744 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7745 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7747 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7748 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7750 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7751 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7753 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7754 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7756 // Index can only be half of the max value for lane in 64-bit vector
7758 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7759 op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7761 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7762 op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7764 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7765 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7767 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7768 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7771 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7772 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7773 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7775 multiclass NI_qdma<SDPatternOperator op> {
7776 def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7778 (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7780 def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7782 (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7785 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7786 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7788 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7789 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7790 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7791 v4i32, v4i16, v8i16>;
7793 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7794 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7795 v2i64, v2i32, v4i32>;
7797 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7798 !cast<PatFrag>(op # "_4s"), VPR128Lo,
7799 v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7801 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7802 !cast<PatFrag>(op # "_2d"), VPR128,
7803 v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7805 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7806 !cast<PatFrag>(op # "_4s"),
7807 v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7809 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7810 !cast<PatFrag>(op # "_2d"),
7811 v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7813 // Index can only be half of the max value for lane in 64-bit vector
7815 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7816 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7817 v4i32, v4i16, v4i16>;
7819 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7820 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7821 v2i64, v2i32, v2i32>;
7823 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7824 !cast<PatFrag>(op # "_4s"), VPR64Lo,
7825 v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7827 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7828 !cast<PatFrag>(op # "_2d"), VPR64,
7829 v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7832 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7833 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7835 // End of implementation for instruction class (3V Elem)
7837 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7838 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7839 SDPatternOperator Neon_Rev>
7840 : NeonI_2VMisc<Q, U, size, opcode,
7841 (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7842 asmop # "\t$Rd." # Res # ", $Rn." # Res,
7843 [(set (ResTy ResVPR:$Rd),
7844 (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7847 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7849 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7851 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7853 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7855 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7857 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7860 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7861 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7863 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7865 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7867 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7869 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7872 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7874 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7877 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7878 SDPatternOperator Neon_Padd> {
7879 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7880 (outs VPR128:$Rd), (ins VPR128:$Rn),
7881 asmop # "\t$Rd.8h, $Rn.16b",
7882 [(set (v8i16 VPR128:$Rd),
7883 (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7886 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7887 (outs VPR64:$Rd), (ins VPR64:$Rn),
7888 asmop # "\t$Rd.4h, $Rn.8b",
7889 [(set (v4i16 VPR64:$Rd),
7890 (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7893 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7894 (outs VPR128:$Rd), (ins VPR128:$Rn),
7895 asmop # "\t$Rd.4s, $Rn.8h",
7896 [(set (v4i32 VPR128:$Rd),
7897 (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7900 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7901 (outs VPR64:$Rd), (ins VPR64:$Rn),
7902 asmop # "\t$Rd.2s, $Rn.4h",
7903 [(set (v2i32 VPR64:$Rd),
7904 (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7907 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7908 (outs VPR128:$Rd), (ins VPR128:$Rn),
7909 asmop # "\t$Rd.2d, $Rn.4s",
7910 [(set (v2i64 VPR128:$Rd),
7911 (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7914 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7915 (outs VPR64:$Rd), (ins VPR64:$Rn),
7916 asmop # "\t$Rd.1d, $Rn.2s",
7917 [(set (v1i64 VPR64:$Rd),
7918 (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7922 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7923 int_arm_neon_vpaddls>;
7924 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7925 int_arm_neon_vpaddlu>;
7927 def : Pat<(v1i64 (int_aarch64_neon_saddlv (v2i32 VPR64:$Rn))),
7929 def : Pat<(v1i64 (int_aarch64_neon_uaddlv (v2i32 VPR64:$Rn))),
7932 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7933 SDPatternOperator Neon_Padd> {
7934 let Constraints = "$src = $Rd" in {
7935 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7936 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7937 asmop # "\t$Rd.8h, $Rn.16b",
7938 [(set (v8i16 VPR128:$Rd),
7940 (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7943 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7944 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7945 asmop # "\t$Rd.4h, $Rn.8b",
7946 [(set (v4i16 VPR64:$Rd),
7948 (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7951 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7952 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7953 asmop # "\t$Rd.4s, $Rn.8h",
7954 [(set (v4i32 VPR128:$Rd),
7956 (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7959 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7960 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7961 asmop # "\t$Rd.2s, $Rn.4h",
7962 [(set (v2i32 VPR64:$Rd),
7964 (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7967 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7968 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7969 asmop # "\t$Rd.2d, $Rn.4s",
7970 [(set (v2i64 VPR128:$Rd),
7972 (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7975 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7976 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7977 asmop # "\t$Rd.1d, $Rn.2s",
7978 [(set (v1i64 VPR64:$Rd),
7980 (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7985 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7986 int_arm_neon_vpadals>;
7987 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7988 int_arm_neon_vpadalu>;
7990 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7991 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7992 (outs VPR128:$Rd), (ins VPR128:$Rn),
7993 asmop # "\t$Rd.16b, $Rn.16b",
7996 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7997 (outs VPR128:$Rd), (ins VPR128:$Rn),
7998 asmop # "\t$Rd.8h, $Rn.8h",
8001 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8002 (outs VPR128:$Rd), (ins VPR128:$Rn),
8003 asmop # "\t$Rd.4s, $Rn.4s",
8006 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8007 (outs VPR128:$Rd), (ins VPR128:$Rn),
8008 asmop # "\t$Rd.2d, $Rn.2d",
8011 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8012 (outs VPR64:$Rd), (ins VPR64:$Rn),
8013 asmop # "\t$Rd.8b, $Rn.8b",
8016 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8017 (outs VPR64:$Rd), (ins VPR64:$Rn),
8018 asmop # "\t$Rd.4h, $Rn.4h",
8021 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8022 (outs VPR64:$Rd), (ins VPR64:$Rn),
8023 asmop # "\t$Rd.2s, $Rn.2s",
8027 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
8028 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
8029 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
8030 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
8032 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
8033 SDPatternOperator Neon_Op> {
8034 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
8035 (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
8037 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
8038 (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
8040 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
8041 (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
8043 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
8044 (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
8046 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
8047 (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
8049 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
8050 (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
8052 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
8053 (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
8056 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
8057 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
8058 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
8060 def : Pat<(v16i8 (sub
8061 (v16i8 Neon_AllZero),
8062 (v16i8 VPR128:$Rn))),
8063 (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
8064 def : Pat<(v8i8 (sub
8065 (v8i8 Neon_AllZero),
8067 (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
8068 def : Pat<(v8i16 (sub
8069 (v8i16 (bitconvert (v16i8 Neon_AllZero))),
8070 (v8i16 VPR128:$Rn))),
8071 (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
8072 def : Pat<(v4i16 (sub
8073 (v4i16 (bitconvert (v8i8 Neon_AllZero))),
8074 (v4i16 VPR64:$Rn))),
8075 (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
8076 def : Pat<(v4i32 (sub
8077 (v4i32 (bitconvert (v16i8 Neon_AllZero))),
8078 (v4i32 VPR128:$Rn))),
8079 (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
8080 def : Pat<(v2i32 (sub
8081 (v2i32 (bitconvert (v8i8 Neon_AllZero))),
8082 (v2i32 VPR64:$Rn))),
8083 (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
8084 def : Pat<(v2i64 (sub
8085 (v2i64 (bitconvert (v16i8 Neon_AllZero))),
8086 (v2i64 VPR128:$Rn))),
8087 (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
8089 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
8090 let Constraints = "$src = $Rd" in {
8091 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8092 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8093 asmop # "\t$Rd.16b, $Rn.16b",
8096 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8097 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8098 asmop # "\t$Rd.8h, $Rn.8h",
8101 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8102 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8103 asmop # "\t$Rd.4s, $Rn.4s",
8106 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8107 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8108 asmop # "\t$Rd.2d, $Rn.2d",
8111 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8112 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8113 asmop # "\t$Rd.8b, $Rn.8b",
8116 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8117 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8118 asmop # "\t$Rd.4h, $Rn.4h",
8121 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8122 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8123 asmop # "\t$Rd.2s, $Rn.2s",
8128 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
8129 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
8131 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
8132 SDPatternOperator Neon_Op> {
8133 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
8134 (v16i8 (!cast<Instruction>(Prefix # 16b)
8135 (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
8137 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
8138 (v8i16 (!cast<Instruction>(Prefix # 8h)
8139 (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
8141 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
8142 (v4i32 (!cast<Instruction>(Prefix # 4s)
8143 (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
8145 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
8146 (v2i64 (!cast<Instruction>(Prefix # 2d)
8147 (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
8149 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
8150 (v8i8 (!cast<Instruction>(Prefix # 8b)
8151 (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
8153 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
8154 (v4i16 (!cast<Instruction>(Prefix # 4h)
8155 (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
8157 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
8158 (v2i32 (!cast<Instruction>(Prefix # 2s)
8159 (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
8162 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
8163 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
8165 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
8166 SDPatternOperator Neon_Op> {
8167 def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
8168 (outs VPR128:$Rd), (ins VPR128:$Rn),
8169 asmop # "\t$Rd.16b, $Rn.16b",
8170 [(set (v16i8 VPR128:$Rd),
8171 (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
8174 def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
8175 (outs VPR128:$Rd), (ins VPR128:$Rn),
8176 asmop # "\t$Rd.8h, $Rn.8h",
8177 [(set (v8i16 VPR128:$Rd),
8178 (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
8181 def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
8182 (outs VPR128:$Rd), (ins VPR128:$Rn),
8183 asmop # "\t$Rd.4s, $Rn.4s",
8184 [(set (v4i32 VPR128:$Rd),
8185 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8188 def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
8189 (outs VPR64:$Rd), (ins VPR64:$Rn),
8190 asmop # "\t$Rd.8b, $Rn.8b",
8191 [(set (v8i8 VPR64:$Rd),
8192 (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
8195 def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
8196 (outs VPR64:$Rd), (ins VPR64:$Rn),
8197 asmop # "\t$Rd.4h, $Rn.4h",
8198 [(set (v4i16 VPR64:$Rd),
8199 (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
8202 def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
8203 (outs VPR64:$Rd), (ins VPR64:$Rn),
8204 asmop # "\t$Rd.2s, $Rn.2s",
8205 [(set (v2i32 VPR64:$Rd),
8206 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8210 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
8211 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
8213 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
8215 def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
8216 (outs VPR128:$Rd), (ins VPR128:$Rn),
8217 asmop # "\t$Rd.16b, $Rn.16b",
8220 def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
8221 (outs VPR64:$Rd), (ins VPR64:$Rn),
8222 asmop # "\t$Rd.8b, $Rn.8b",
8226 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
8227 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
8228 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
8230 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
8231 (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
8232 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
8233 (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
8235 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
8236 (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
8237 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
8238 (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
8240 def : Pat<(v16i8 (xor
8242 (v16i8 Neon_AllOne))),
8243 (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
8244 def : Pat<(v8i8 (xor
8246 (v8i8 Neon_AllOne))),
8247 (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
8248 def : Pat<(v8i16 (xor
8250 (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
8251 (NOT16b VPR128:$Rn)>;
8252 def : Pat<(v4i16 (xor
8254 (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
8256 def : Pat<(v4i32 (xor
8258 (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
8259 (NOT16b VPR128:$Rn)>;
8260 def : Pat<(v2i32 (xor
8262 (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
8264 def : Pat<(v2i64 (xor
8266 (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
8267 (NOT16b VPR128:$Rn)>;
8269 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
8270 (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
8271 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
8272 (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
8274 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
8275 SDPatternOperator Neon_Op> {
8276 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8277 (outs VPR128:$Rd), (ins VPR128:$Rn),
8278 asmop # "\t$Rd.4s, $Rn.4s",
8279 [(set (v4f32 VPR128:$Rd),
8280 (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
8283 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8284 (outs VPR128:$Rd), (ins VPR128:$Rn),
8285 asmop # "\t$Rd.2d, $Rn.2d",
8286 [(set (v2f64 VPR128:$Rd),
8287 (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
8290 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8291 (outs VPR64:$Rd), (ins VPR64:$Rn),
8292 asmop # "\t$Rd.2s, $Rn.2s",
8293 [(set (v2f32 VPR64:$Rd),
8294 (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
8298 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
8299 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
8301 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
8302 def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8303 (outs VPR64:$Rd), (ins VPR128:$Rn),
8304 asmop # "\t$Rd.8b, $Rn.8h",
8307 def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8308 (outs VPR64:$Rd), (ins VPR128:$Rn),
8309 asmop # "\t$Rd.4h, $Rn.4s",
8312 def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8313 (outs VPR64:$Rd), (ins VPR128:$Rn),
8314 asmop # "\t$Rd.2s, $Rn.2d",
8317 let Constraints = "$Rd = $src" in {
8318 def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8319 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8320 asmop # "2\t$Rd.16b, $Rn.8h",
8323 def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8324 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8325 asmop # "2\t$Rd.8h, $Rn.4s",
8328 def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8329 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8330 asmop # "2\t$Rd.4s, $Rn.2d",
8335 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
8336 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
8337 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
8338 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
8340 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
8341 SDPatternOperator Neon_Op> {
8342 def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8343 (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8345 def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8346 (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8348 def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8349 (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8351 def : Pat<(v16i8 (concat_vectors
8353 (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8354 (!cast<Instruction>(Prefix # 8h16b)
8355 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8358 def : Pat<(v8i16 (concat_vectors
8360 (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8361 (!cast<Instruction>(Prefix # 4s8h)
8362 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8365 def : Pat<(v4i32 (concat_vectors
8367 (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8368 (!cast<Instruction>(Prefix # 2d4s)
8369 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8373 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8374 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8375 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8376 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8378 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8379 let DecoderMethod = "DecodeSHLLInstruction" in {
8380 def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8382 (ins VPR64:$Rn, uimm_exact8:$Imm),
8383 asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8386 def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8388 (ins VPR64:$Rn, uimm_exact16:$Imm),
8389 asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8392 def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8394 (ins VPR64:$Rn, uimm_exact32:$Imm),
8395 asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8398 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8400 (ins VPR128:$Rn, uimm_exact8:$Imm),
8401 asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8404 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8406 (ins VPR128:$Rn, uimm_exact16:$Imm),
8407 asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8410 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8412 (ins VPR128:$Rn, uimm_exact32:$Imm),
8413 asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8418 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8420 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8421 SDPatternOperator ExtOp, Operand Neon_Imm,
8424 (DesTy (ExtOp (OpTy VPR64:$Rn))),
8426 (i32 Neon_Imm:$Imm))))),
8427 (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8429 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8430 SDPatternOperator ExtOp, Operand Neon_Imm,
8431 string suffix, PatFrag GetHigh>
8434 (OpTy (GetHigh VPR128:$Rn)))),
8436 (i32 Neon_Imm:$Imm))))),
8437 (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8439 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8440 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8441 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8442 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8443 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8444 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8445 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8447 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8449 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8451 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8453 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8455 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8458 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8459 def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8460 (outs VPR64:$Rd), (ins VPR128:$Rn),
8461 asmop # "\t$Rd.4h, $Rn.4s",
8464 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8465 (outs VPR64:$Rd), (ins VPR128:$Rn),
8466 asmop # "\t$Rd.2s, $Rn.2d",
8469 let Constraints = "$src = $Rd" in {
8470 def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8471 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8472 asmop # "2\t$Rd.8h, $Rn.4s",
8475 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8476 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8477 asmop # "2\t$Rd.4s, $Rn.2d",
8482 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8484 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8485 SDPatternOperator f32_to_f16_Op,
8486 SDPatternOperator f64_to_f32_Op> {
8488 def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8489 (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8491 def : Pat<(v8i16 (concat_vectors
8493 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8494 (!cast<Instruction>(prefix # "4s8h")
8495 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8496 (v4f32 VPR128:$Rn))>;
8498 def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8499 (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8501 def : Pat<(v4f32 (concat_vectors
8503 (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8504 (!cast<Instruction>(prefix # "2d4s")
8505 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8506 (v2f64 VPR128:$Rn))>;
8509 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8511 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8513 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8514 (outs VPR64:$Rd), (ins VPR128:$Rn),
8515 asmop # "\t$Rd.2s, $Rn.2d",
8518 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8519 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8520 asmop # "2\t$Rd.4s, $Rn.2d",
8522 let Constraints = "$src = $Rd";
8525 def : Pat<(v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))),
8526 (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8528 def : Pat<(v4f32 (concat_vectors
8530 (v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))))),
8531 (!cast<Instruction>(prefix # "2d4s")
8532 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8536 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8538 def Neon_High4Float : PatFrag<(ops node:$in),
8539 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8541 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8542 def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8543 (outs VPR128:$Rd), (ins VPR64:$Rn),
8544 asmop # "\t$Rd.4s, $Rn.4h",
8547 def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8548 (outs VPR128:$Rd), (ins VPR64:$Rn),
8549 asmop # "\t$Rd.2d, $Rn.2s",
8552 def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8553 (outs VPR128:$Rd), (ins VPR128:$Rn),
8554 asmop # "2\t$Rd.4s, $Rn.8h",
8557 def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8558 (outs VPR128:$Rd), (ins VPR128:$Rn),
8559 asmop # "2\t$Rd.2d, $Rn.4s",
8563 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8565 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8566 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8567 (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8569 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8571 (v8i16 VPR128:$Rn))))),
8572 (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8574 def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8575 (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8577 def : Pat<(v2f64 (fextend
8578 (v2f32 (Neon_High4Float
8579 (v4f32 VPR128:$Rn))))),
8580 (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8583 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8585 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8586 ValueType ResTy4s, ValueType OpTy4s,
8587 ValueType ResTy2d, ValueType OpTy2d,
8588 ValueType ResTy2s, ValueType OpTy2s,
8589 SDPatternOperator Neon_Op> {
8591 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8592 (outs VPR128:$Rd), (ins VPR128:$Rn),
8593 asmop # "\t$Rd.4s, $Rn.4s",
8594 [(set (ResTy4s VPR128:$Rd),
8595 (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8598 def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8599 (outs VPR128:$Rd), (ins VPR128:$Rn),
8600 asmop # "\t$Rd.2d, $Rn.2d",
8601 [(set (ResTy2d VPR128:$Rd),
8602 (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8605 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8606 (outs VPR64:$Rd), (ins VPR64:$Rn),
8607 asmop # "\t$Rd.2s, $Rn.2s",
8608 [(set (ResTy2s VPR64:$Rd),
8609 (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8613 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8614 bits<5> opcode, SDPatternOperator Neon_Op> {
8615 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8616 v2f64, v2i32, v2f32, Neon_Op>;
8619 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8620 int_arm_neon_vcvtns>;
8621 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8622 int_arm_neon_vcvtnu>;
8623 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8624 int_arm_neon_vcvtps>;
8625 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8626 int_arm_neon_vcvtpu>;
8627 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8628 int_arm_neon_vcvtms>;
8629 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8630 int_arm_neon_vcvtmu>;
8631 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8632 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8633 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8634 int_arm_neon_vcvtas>;
8635 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8636 int_arm_neon_vcvtau>;
8638 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8639 bits<5> opcode, SDPatternOperator Neon_Op> {
8640 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8641 v2i64, v2f32, v2i32, Neon_Op>;
8644 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8645 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8647 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8648 bits<5> opcode, SDPatternOperator Neon_Op> {
8649 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8650 v2f64, v2f32, v2f32, Neon_Op>;
8653 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8654 int_aarch64_neon_frintn>;
8655 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8656 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8657 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8658 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8659 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8660 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8661 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8662 int_arm_neon_vrecpe>;
8663 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8664 int_arm_neon_vrsqrte>;
8665 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
8667 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8668 bits<5> opcode, SDPatternOperator Neon_Op> {
8669 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8670 (outs VPR128:$Rd), (ins VPR128:$Rn),
8671 asmop # "\t$Rd.4s, $Rn.4s",
8672 [(set (v4i32 VPR128:$Rd),
8673 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8676 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8677 (outs VPR64:$Rd), (ins VPR64:$Rn),
8678 asmop # "\t$Rd.2s, $Rn.2s",
8679 [(set (v2i32 VPR64:$Rd),
8680 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8684 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8685 int_arm_neon_vrecpe>;
8686 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8687 int_arm_neon_vrsqrte>;
8690 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8691 string asmop, SDPatternOperator opnode>
8692 : NeonI_Crypto_AES<size, opcode,
8693 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8694 asmop # "\t$Rd.16b, $Rn.16b",
8695 [(set (v16i8 VPR128:$Rd),
8696 (v16i8 (opnode (v16i8 VPR128:$src),
8697 (v16i8 VPR128:$Rn))))],
8699 let Constraints = "$src = $Rd";
8700 let Predicates = [HasNEON, HasCrypto];
8703 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8704 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8706 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8707 string asmop, SDPatternOperator opnode>
8708 : NeonI_Crypto_AES<size, opcode,
8709 (outs VPR128:$Rd), (ins VPR128:$Rn),
8710 asmop # "\t$Rd.16b, $Rn.16b",
8711 [(set (v16i8 VPR128:$Rd),
8712 (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8715 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8716 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8718 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8719 string asmop, SDPatternOperator opnode>
8720 : NeonI_Crypto_SHA<size, opcode,
8721 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8722 asmop # "\t$Rd.4s, $Rn.4s",
8723 [(set (v4i32 VPR128:$Rd),
8724 (v4i32 (opnode (v4i32 VPR128:$src),
8725 (v4i32 VPR128:$Rn))))],
8727 let Constraints = "$src = $Rd";
8728 let Predicates = [HasNEON, HasCrypto];
8731 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8732 int_arm_neon_sha1su1>;
8733 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8734 int_arm_neon_sha256su0>;
8736 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8737 string asmop, SDPatternOperator opnode>
8738 : NeonI_Crypto_SHA<size, opcode,
8739 (outs FPR32:$Rd), (ins FPR32:$Rn),
8740 asmop # "\t$Rd, $Rn",
8741 [(set (v1i32 FPR32:$Rd),
8742 (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8744 let Predicates = [HasNEON, HasCrypto];
8747 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8749 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8750 SDPatternOperator opnode>
8751 : NeonI_Crypto_3VSHA<size, opcode,
8753 (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8754 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8755 [(set (v4i32 VPR128:$Rd),
8756 (v4i32 (opnode (v4i32 VPR128:$src),
8758 (v4i32 VPR128:$Rm))))],
8760 let Constraints = "$src = $Rd";
8761 let Predicates = [HasNEON, HasCrypto];
8764 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8765 int_arm_neon_sha1su0>;
8766 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8767 int_arm_neon_sha256su1>;
8769 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8770 SDPatternOperator opnode>
8771 : NeonI_Crypto_3VSHA<size, opcode,
8773 (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8774 asmop # "\t$Rd, $Rn, $Rm.4s",
8775 [(set (v4i32 FPR128:$Rd),
8776 (v4i32 (opnode (v4i32 FPR128:$src),
8778 (v4i32 VPR128:$Rm))))],
8780 let Constraints = "$src = $Rd";
8781 let Predicates = [HasNEON, HasCrypto];
8784 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8785 int_arm_neon_sha256h>;
8786 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8787 int_arm_neon_sha256h2>;
8789 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8790 SDPatternOperator opnode>
8791 : NeonI_Crypto_3VSHA<size, opcode,
8793 (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8794 asmop # "\t$Rd, $Rn, $Rm.4s",
8795 [(set (v4i32 FPR128:$Rd),
8796 (v4i32 (opnode (v4i32 FPR128:$src),
8798 (v4i32 VPR128:$Rm))))],
8800 let Constraints = "$src = $Rd";
8801 let Predicates = [HasNEON, HasCrypto];
8804 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8805 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8806 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8808 // Additional patterns to match shl to USHL.
8809 def : Pat<(v8i8 (shl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8810 (USHLvvv_8B $Rn, $Rm)>;
8811 def : Pat<(v4i16 (shl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8812 (USHLvvv_4H $Rn, $Rm)>;
8813 def : Pat<(v2i32 (shl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8814 (USHLvvv_2S $Rn, $Rm)>;
8815 def : Pat<(v1i64 (shl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8816 (USHLddd $Rn, $Rm)>;
8817 def : Pat<(v16i8 (shl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8818 (USHLvvv_16B $Rn, $Rm)>;
8819 def : Pat<(v8i16 (shl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8820 (USHLvvv_8H $Rn, $Rm)>;
8821 def : Pat<(v4i32 (shl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8822 (USHLvvv_4S $Rn, $Rm)>;
8823 def : Pat<(v2i64 (shl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8824 (USHLvvv_2D $Rn, $Rm)>;
8826 // Additional patterns to match sra, srl.
8827 // For a vector right shift by vector, the shift amounts of SSHL/USHL are
8828 // negative. Negate the vector of shift amount first.
8829 def : Pat<(v8i8 (srl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8830 (USHLvvv_8B $Rn, (NEG8b $Rm))>;
8831 def : Pat<(v4i16 (srl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8832 (USHLvvv_4H $Rn, (NEG4h $Rm))>;
8833 def : Pat<(v2i32 (srl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8834 (USHLvvv_2S $Rn, (NEG2s $Rm))>;
8835 def : Pat<(v1i64 (srl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8836 (USHLddd $Rn, (NEGdd $Rm))>;
8837 def : Pat<(v16i8 (srl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8838 (USHLvvv_16B $Rn, (NEG16b $Rm))>;
8839 def : Pat<(v8i16 (srl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8840 (USHLvvv_8H $Rn, (NEG8h $Rm))>;
8841 def : Pat<(v4i32 (srl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8842 (USHLvvv_4S $Rn, (NEG4s $Rm))>;
8843 def : Pat<(v2i64 (srl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8844 (USHLvvv_2D $Rn, (NEG2d $Rm))>;
8846 def : Pat<(v8i8 (sra (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8847 (SSHLvvv_8B $Rn, (NEG8b $Rm))>;
8848 def : Pat<(v4i16 (sra (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8849 (SSHLvvv_4H $Rn, (NEG4h $Rm))>;
8850 def : Pat<(v2i32 (sra (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8851 (SSHLvvv_2S $Rn, (NEG2s $Rm))>;
8852 def : Pat<(v1i64 (sra (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8853 (SSHLddd $Rn, (NEGdd $Rm))>;
8854 def : Pat<(v16i8 (sra (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8855 (SSHLvvv_16B $Rn, (NEG16b $Rm))>;
8856 def : Pat<(v8i16 (sra (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8857 (SSHLvvv_8H $Rn, (NEG8h $Rm))>;
8858 def : Pat<(v4i32 (sra (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8859 (SSHLvvv_4S $Rn, (NEG4s $Rm))>;
8860 def : Pat<(v2i64 (sra (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8861 (SSHLvvv_2D $Rn, (NEG2d $Rm))>;
8864 // Patterns for handling half-precision values
8867 // Convert between f16 value and f32 value
8868 def : Pat<(f32 (f16_to_f32 (i32 GPR32:$Rn))),
8869 (FCVTsh (EXTRACT_SUBREG (FMOVsw $Rn), sub_16))>;
8870 def : Pat<(i32 (f32_to_f16 (f32 FPR32:$Rn))),
8871 (FMOVws (SUBREG_TO_REG (i64 0), (f16 (FCVThs $Rn)), sub_16))>;
8873 // Convert f16 value coming in as i16 value to f32
8874 def : Pat<(f32 (f16_to_f32 (i32 (and (i32 GPR32:$Rn), 65535)))),
8875 (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8876 def : Pat<(f32 (f16_to_f32 (i32 (assertzext GPR32:$Rn)))),
8877 (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8879 def : Pat<(f32 (f16_to_f32 (i32 (assertzext (i32 (
8880 f32_to_f16 (f32 FPR32:$Rn))))))),
8883 // Patterns for vector extract of half-precision FP value in i16 storage type
8884 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8885 (v4i16 VPR64:$Rn), neon_uimm2_bare:$Imm)), 65535)))),
8886 (FCVTsh (f16 (DUPhv_H
8887 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8888 neon_uimm2_bare:$Imm)))>;
8890 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8891 (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)), 65535)))),
8892 (FCVTsh (f16 (DUPhv_H (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)))>;
8894 // Patterns for vector insert of half-precision FP value 0 in i16 storage type
8895 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8896 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8897 (neon_uimm3_bare:$Imm))),
8898 (v8i16 (INSELh (v8i16 VPR128:$Rn),
8899 (v8i16 (SUBREG_TO_REG (i64 0),
8900 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8902 neon_uimm3_bare:$Imm, 0))>;
8904 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8905 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8906 (neon_uimm2_bare:$Imm))),
8907 (v4i16 (EXTRACT_SUBREG
8909 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8910 (v8i16 (SUBREG_TO_REG (i64 0),
8911 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8913 neon_uimm2_bare:$Imm, 0)),
8916 // Patterns for vector insert of half-precision FP value in i16 storage type
8917 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8918 (i32 (assertsext (i32 (fp_to_sint
8919 (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8920 (neon_uimm3_bare:$Imm))),
8921 (v8i16 (INSELh (v8i16 VPR128:$Rn),
8922 (v8i16 (SUBREG_TO_REG (i64 0),
8923 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8925 neon_uimm3_bare:$Imm, 0))>;
8927 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8928 (i32 (assertsext (i32 (fp_to_sint
8929 (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8930 (neon_uimm2_bare:$Imm))),
8931 (v4i16 (EXTRACT_SUBREG
8933 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8934 (v8i16 (SUBREG_TO_REG (i64 0),
8935 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8937 neon_uimm2_bare:$Imm, 0)),
8940 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8941 (i32 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8942 (neon_uimm3_bare:$Imm1))),
8943 (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8944 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8946 // Patterns for vector copy of half-precision FP value in i16 storage type
8947 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8948 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8949 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8951 (neon_uimm3_bare:$Imm1))),
8952 (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8953 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8955 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8956 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8957 (vector_extract (v4i16 VPR64:$src), neon_uimm3_bare:$Imm2)),
8959 (neon_uimm3_bare:$Imm1))),
8960 (v4i16 (EXTRACT_SUBREG
8962 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8963 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
8964 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2)),