lib/Target/AArch64/AArch64InstrNEON.td

   1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the AArch64 NEON instruction set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // NEON-specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // (outs Result), (ins Imm, OpCmode)
  19 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
  20
  21 def Neon_movi     : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
  22
  23 def Neon_mvni     : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
  24
  25 // (outs Result), (ins Imm)
  26 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
  27                         [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
  28
  29 // (outs Result), (ins LHS, RHS, CondCode)
  30 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
  31                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  32
  33 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
  34 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
  35                  [SDTCisVec<0>,  SDTCisVec<1>]>>;
  36
  37 // (outs Result), (ins LHS, RHS)
  38 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
  39                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  40
  41 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  42                                      SDTCisVT<2, i32>]>;
  43 def Neon_sqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
  44 def Neon_uqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
  45
  46 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  47                                SDTCisSameAs<0, 2>]>;
  48 def Neon_uzp1    : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
  49 def Neon_uzp2    : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
  50 def Neon_zip1    : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
  51 def Neon_zip2    : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
  52 def Neon_trn1    : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
  53 def Neon_trn2    : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
  54
  55 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
  56 def Neon_rev64    : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
  57 def Neon_rev32    : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
  58 def Neon_rev16    : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
  59 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
  60                        [SDTCisVec<0>]>>;
  61 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
  62                            [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
  63 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
  64                            [SDTCisVec<0>,  SDTCisSameAs<0, 1>,
  65                            SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
  66
  67 def SDT_assertext : SDTypeProfile<1, 1,
  68   [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
  69 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
  70 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
  71
  72 //===----------------------------------------------------------------------===//
  73 // Addressing-mode instantiations
  74 //===----------------------------------------------------------------------===//
  75
  76 multiclass ls_64_pats<dag address, dag Base, dag Offset, ValueType Ty> {
  77 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
  78                       !foreach(decls.pattern, Offset,
  79                                !subst(OFFSET, dword_uimm12, decls.pattern)),
  80                       !foreach(decls.pattern, address,
  81                                !subst(OFFSET, dword_uimm12,
  82                                !subst(ALIGN, min_align8, decls.pattern))),
  83                       Ty>;
  84 }
  85
  86 multiclass ls_128_pats<dag address, dag Base, dag Offset, ValueType Ty> {
  87 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
  88                        !foreach(decls.pattern, Offset,
  89                                 !subst(OFFSET, qword_uimm12, decls.pattern)),
  90                        !foreach(decls.pattern, address,
  91                                 !subst(OFFSET, qword_uimm12,
  92                                 !subst(ALIGN, min_align16, decls.pattern))),
  93                       Ty>;
  94 }
  95
  96 multiclass uimm12_neon_pats<dag address, dag Base, dag Offset> {
  97   defm : ls_64_pats<address, Base, Offset, v8i8>;
  98   defm : ls_64_pats<address, Base, Offset, v4i16>;
  99   defm : ls_64_pats<address, Base, Offset, v2i32>;
 100   defm : ls_64_pats<address, Base, Offset, v1i64>;
 101   defm : ls_64_pats<address, Base, Offset, v2f32>;
 102   defm : ls_64_pats<address, Base, Offset, v1f64>;
 103
 104   defm : ls_128_pats<address, Base, Offset, v16i8>;
 105   defm : ls_128_pats<address, Base, Offset, v8i16>;
 106   defm : ls_128_pats<address, Base, Offset, v4i32>;
 107   defm : ls_128_pats<address, Base, Offset, v2i64>;
 108   defm : ls_128_pats<address, Base, Offset, v4f32>;
 109   defm : ls_128_pats<address, Base, Offset, v2f64>;
 110 }
 111
 112 defm : uimm12_neon_pats<(A64WrapperSmall
 113                           tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
 114                         (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
 115
 116 //===----------------------------------------------------------------------===//
 117 // Multiclasses
 118 //===----------------------------------------------------------------------===//
 119
 120 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size,  bits<5> opcode,
 121                                 string asmop, SDPatternOperator opnode8B,
 122                                 SDPatternOperator opnode16B,
 123                                 bit Commutable = 0> {
 124   let isCommutable = Commutable in {
 125     def _8B :  NeonI_3VSame<0b0, u, size, opcode,
 126                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 127                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 128                [(set (v8i8 VPR64:$Rd),
 129                   (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 130                NoItinerary>;
 131
 132     def _16B : NeonI_3VSame<0b1, u, size, opcode,
 133                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 134                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 135                [(set (v16i8 VPR128:$Rd),
 136                   (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 137                NoItinerary>;
 138   }
 139
 140 }
 141
 142 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
 143                                   string asmop, SDPatternOperator opnode,
 144                                   bit Commutable = 0> {
 145   let isCommutable = Commutable in {
 146     def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
 147               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 148               asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
 149               [(set (v4i16 VPR64:$Rd),
 150                  (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
 151               NoItinerary>;
 152
 153     def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
 154               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 155               asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
 156               [(set (v8i16 VPR128:$Rd),
 157                  (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
 158               NoItinerary>;
 159
 160     def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
 161               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 162               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 163               [(set (v2i32 VPR64:$Rd),
 164                  (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
 165               NoItinerary>;
 166
 167     def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
 168               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 169               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 170               [(set (v4i32 VPR128:$Rd),
 171                  (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
 172               NoItinerary>;
 173   }
 174 }
 175 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
 176                                   string asmop, SDPatternOperator opnode,
 177                                   bit Commutable = 0>
 178    : NeonI_3VSame_HS_sizes<u, opcode,  asmop, opnode, Commutable> {
 179   let isCommutable = Commutable in {
 180     def _8B :  NeonI_3VSame<0b0, u, 0b00, opcode,
 181                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 182                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 183                [(set (v8i8 VPR64:$Rd),
 184                   (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 185                NoItinerary>;
 186
 187     def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
 188                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 189                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 190                [(set (v16i8 VPR128:$Rd),
 191                   (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 192                NoItinerary>;
 193   }
 194 }
 195
 196 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
 197                                    string asmop, SDPatternOperator opnode,
 198                                    bit Commutable = 0>
 199    : NeonI_3VSame_BHS_sizes<u, opcode,  asmop, opnode, Commutable> {
 200   let isCommutable = Commutable in {
 201     def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
 202               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 203               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 204               [(set (v2i64 VPR128:$Rd),
 205                  (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
 206               NoItinerary>;
 207   }
 208 }
 209
 210 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
 211 // but Result types can be integer or floating point types.
 212 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
 213                                  string asmop, SDPatternOperator opnode2S,
 214                                  SDPatternOperator opnode4S,
 215                                  SDPatternOperator opnode2D,
 216                                  ValueType ResTy2S, ValueType ResTy4S,
 217                                  ValueType ResTy2D, bit Commutable = 0> {
 218   let isCommutable = Commutable in {
 219     def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
 220               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 221               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 222               [(set (ResTy2S VPR64:$Rd),
 223                  (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
 224               NoItinerary>;
 225
 226     def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
 227               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 228               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 229               [(set (ResTy4S VPR128:$Rd),
 230                  (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
 231               NoItinerary>;
 232
 233     def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
 234               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 235               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 236               [(set (ResTy2D VPR128:$Rd),
 237                  (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
 238                NoItinerary>;
 239   }
 240 }
 241
 242 //===----------------------------------------------------------------------===//
 243 // Instruction Definitions
 244 //===----------------------------------------------------------------------===//
 245
 246 // Vector Arithmetic Instructions
 247
 248 // Vector Add (Integer and Floating-Point)
 249
 250 defm ADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
 251 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
 252                                      v2f32, v4f32, v2f64, 1>;
 253
 254 // Vector Sub (Integer and Floating-Point)
 255
 256 defm SUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
 257 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
 258                                      v2f32, v4f32, v2f64, 0>;
 259
 260 // Vector Multiply (Integer and Floating-Point)
 261
 262 defm MULvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
 263 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
 264                                      v2f32, v4f32, v2f64, 1>;
 265
 266 // Vector Multiply (Polynomial)
 267
 268 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
 269                                     int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
 270
 271 // Vector Multiply-accumulate and Multiply-subtract (Integer)
 272
 273 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
 274 // two operands constraints.
 275 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
 276   RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
 277   bits<5> opcode, SDPatternOperator opnode>
 278   : NeonI_3VSame<q, u, size, opcode,
 279     (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
 280     asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
 281     [(set (OpTy VPRC:$Rd),
 282        (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
 283     NoItinerary> {
 284   let Constraints = "$src = $Rd";
 285 }
 286
 287 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 288                        (add node:$Ra, (mul node:$Rn, node:$Rm))>;
 289
 290 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 291                        (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
 292
 293
 294 def MLAvvv_8B:  NeonI_3VSame_Constraint_impl<"mla", ".8b",  VPR64,  v8i8,
 295                                              0b0, 0b0, 0b00, 0b10010, Neon_mla>;
 296 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
 297                                              0b1, 0b0, 0b00, 0b10010, Neon_mla>;
 298 def MLAvvv_4H:  NeonI_3VSame_Constraint_impl<"mla", ".4h",  VPR64,  v4i16,
 299                                              0b0, 0b0, 0b01, 0b10010, Neon_mla>;
 300 def MLAvvv_8H:  NeonI_3VSame_Constraint_impl<"mla", ".8h",  VPR128, v8i16,
 301                                              0b1, 0b0, 0b01, 0b10010, Neon_mla>;
 302 def MLAvvv_2S:  NeonI_3VSame_Constraint_impl<"mla", ".2s",  VPR64,  v2i32,
 303                                              0b0, 0b0, 0b10, 0b10010, Neon_mla>;
 304 def MLAvvv_4S:  NeonI_3VSame_Constraint_impl<"mla", ".4s",  VPR128, v4i32,
 305                                              0b1, 0b0, 0b10, 0b10010, Neon_mla>;
 306
 307 def MLSvvv_8B:  NeonI_3VSame_Constraint_impl<"mls", ".8b",  VPR64,  v8i8,
 308                                              0b0, 0b1, 0b00, 0b10010, Neon_mls>;
 309 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
 310                                              0b1, 0b1, 0b00, 0b10010, Neon_mls>;
 311 def MLSvvv_4H:  NeonI_3VSame_Constraint_impl<"mls", ".4h",  VPR64,  v4i16,
 312                                              0b0, 0b1, 0b01, 0b10010, Neon_mls>;
 313 def MLSvvv_8H:  NeonI_3VSame_Constraint_impl<"mls", ".8h",  VPR128, v8i16,
 314                                              0b1, 0b1, 0b01, 0b10010, Neon_mls>;
 315 def MLSvvv_2S:  NeonI_3VSame_Constraint_impl<"mls", ".2s",  VPR64,  v2i32,
 316                                              0b0, 0b1, 0b10, 0b10010, Neon_mls>;
 317 def MLSvvv_4S:  NeonI_3VSame_Constraint_impl<"mls", ".4s",  VPR128, v4i32,
 318                                              0b1, 0b1, 0b10, 0b10010, Neon_mls>;
 319
 320 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
 321
 322 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 323                         (fadd node:$Ra, (fmul_su node:$Rn, node:$Rm))>;
 324
 325 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 326                         (fsub node:$Ra, (fmul_su node:$Rn, node:$Rm))>;
 327
 328 let Predicates = [HasNEON, UseFusedMAC] in {
 329 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s",  VPR64,  v2f32,
 330                                              0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
 331 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s",  VPR128, v4f32,
 332                                              0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
 333 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d",  VPR128, v2f64,
 334                                              0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
 335
 336 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s",  VPR64,  v2f32,
 337                                               0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
 338 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s",  VPR128, v4f32,
 339                                              0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
 340 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d",  VPR128, v2f64,
 341                                              0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
 342 }
 343
 344 // We're also allowed to match the fma instruction regardless of compile
 345 // options.
 346 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
 347           (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 348 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 349           (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 350 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 351           (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 352
 353 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
 354           (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 355 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 356           (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 357 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 358           (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 359
 360 // Vector Divide (Floating-Point)
 361
 362 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
 363                                      v2f32, v4f32, v2f64, 0>;
 364
 365 // Vector Bitwise Operations
 366
 367 // Vector Bitwise AND
 368
 369 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
 370
 371 // Vector Bitwise Exclusive OR
 372
 373 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
 374
 375 // Vector Bitwise OR
 376
 377 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
 378
 379 // ORR disassembled as MOV if Vn==Vm
 380
 381 // Vector Move - register
 382 // Alias for ORR if Vn=Vm.
 383 // FIXME: This is actually the preferred syntax but TableGen can't deal with
 384 // custom printing of aliases.
 385 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
 386                     (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
 387 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
 388                     (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
 389
 390 // The MOVI instruction takes two immediate operands.  The first is the
 391 // immediate encoding, while the second is the cmode.  A cmode of 14, or
 392 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
 393 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
 394 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
 395
 396 def Neon_not8B  : PatFrag<(ops node:$in),
 397                           (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
 398 def Neon_not16B : PatFrag<(ops node:$in),
 399                           (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
 400
 401 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
 402                          (or node:$Rn, (Neon_not8B node:$Rm))>;
 403
 404 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
 405                           (or node:$Rn, (Neon_not16B node:$Rm))>;
 406
 407 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
 408                          (and node:$Rn, (Neon_not8B node:$Rm))>;
 409
 410 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
 411                           (and node:$Rn, (Neon_not16B node:$Rm))>;
 412
 413
 414 // Vector Bitwise OR NOT - register
 415
 416 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
 417                                    Neon_orn8B, Neon_orn16B, 0>;
 418
 419 // Vector Bitwise Bit Clear (AND NOT) - register
 420
 421 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
 422                                    Neon_bic8B, Neon_bic16B, 0>;
 423
 424 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
 425                                    SDPatternOperator opnode16B,
 426                                    Instruction INST8B,
 427                                    Instruction INST16B> {
 428   def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 429             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 430   def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 431             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 432   def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 433             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 434   def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 435             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 436   def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 437             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 438   def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 439             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 440 }
 441
 442 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
 443 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
 444 defm : Neon_bitwise2V_patterns<or,  or,  ORRvvv_8B, ORRvvv_16B>;
 445 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
 446 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
 447 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
 448
 449 //   Vector Bitwise Select
 450 def BSLvvv_8B  : NeonI_3VSame_Constraint_impl<"bsl", ".8b",  VPR64, v8i8,
 451                                               0b0, 0b1, 0b01, 0b00011, vselect>;
 452
 453 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
 454                                               0b1, 0b1, 0b01, 0b00011, vselect>;
 455
 456 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
 457                                    Instruction INST8B,
 458                                    Instruction INST16B> {
 459   // Disassociate type from instruction definition
 460   def : Pat<(v8i8 (opnode (v8i8 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 461             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 462   def : Pat<(v2i32 (opnode (v2i32 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 463             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 464   def : Pat<(v4i16 (opnode (v4i16 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 465             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 466   def : Pat<(v1i64 (opnode (v1i64 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 467             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 468   def : Pat<(v16i8 (opnode (v16i8 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 469             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 470   def : Pat<(v4i32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 471             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 472   def : Pat<(v8i16 (opnode (v8i16 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 473             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 474   def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 475             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 476
 477   // Allow to match BSL instruction pattern with non-constant operand
 478   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
 479                     (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 480           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 481   def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
 482                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 483           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 484   def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
 485                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 486           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 487   def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
 488                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 489           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 490   def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
 491                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 492           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 493   def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
 494                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 495           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 496   def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
 497                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 498           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 499   def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
 500                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 501           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 502
 503   // Allow to match llvm.arm.* intrinsics.
 504   def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
 505                     (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
 506             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 507   def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
 508                     (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
 509             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 510   def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
 511                     (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
 512             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 513   def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
 514                     (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
 515             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 516   def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
 517                     (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
 518             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 519   def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
 520                     (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
 521             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 522   def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
 523                     (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
 524             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 525   def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
 526                     (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
 527             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 528   def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
 529                     (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
 530             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 531   def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
 532                     (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
 533             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 534   def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
 535                     (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
 536             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 537   def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
 538                     (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
 539             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 540 }
 541
 542 // Additional patterns for bitwise instruction BSL
 543 defm: Neon_bitwise3V_patterns<vselect, BSLvvv_8B, BSLvvv_16B>;
 544
 545 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
 546                            (vselect node:$src, node:$Rn, node:$Rm),
 547                            [{ (void)N; return false; }]>;
 548
 549 // Vector Bitwise Insert if True
 550
 551 def BITvvv_8B  : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64,   v8i8,
 552                    0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 553 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
 554                    0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 555
 556 // Vector Bitwise Insert if False
 557
 558 def BIFvvv_8B  : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64,  v8i8,
 559                                 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 560 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
 561                                 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 562
 563 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
 564
 565 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 566                        (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
 567 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 568                        (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
 569
 570 // Vector Absolute Difference and Accumulate (Unsigned)
 571 def UABAvvv_8B :  NeonI_3VSame_Constraint_impl<"uaba", ".8b",  VPR64,  v8i8,
 572                     0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
 573 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
 574                     0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
 575 def UABAvvv_4H :  NeonI_3VSame_Constraint_impl<"uaba", ".4h",  VPR64,  v4i16,
 576                     0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
 577 def UABAvvv_8H :  NeonI_3VSame_Constraint_impl<"uaba", ".8h",  VPR128, v8i16,
 578                     0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
 579 def UABAvvv_2S :  NeonI_3VSame_Constraint_impl<"uaba", ".2s",  VPR64,  v2i32,
 580                     0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
 581 def UABAvvv_4S :  NeonI_3VSame_Constraint_impl<"uaba", ".4s",  VPR128, v4i32,
 582                     0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
 583
 584 // Vector Absolute Difference and Accumulate (Signed)
 585 def SABAvvv_8B :  NeonI_3VSame_Constraint_impl<"saba", ".8b",  VPR64,  v8i8,
 586                     0b0, 0b0, 0b00, 0b01111, Neon_saba>;
 587 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
 588                     0b1, 0b0, 0b00, 0b01111, Neon_saba>;
 589 def SABAvvv_4H :  NeonI_3VSame_Constraint_impl<"saba", ".4h",  VPR64,  v4i16,
 590                     0b0, 0b0, 0b01, 0b01111, Neon_saba>;
 591 def SABAvvv_8H :  NeonI_3VSame_Constraint_impl<"saba", ".8h",  VPR128, v8i16,
 592                     0b1, 0b0, 0b01, 0b01111, Neon_saba>;
 593 def SABAvvv_2S :  NeonI_3VSame_Constraint_impl<"saba", ".2s",  VPR64,  v2i32,
 594                     0b0, 0b0, 0b10, 0b01111, Neon_saba>;
 595 def SABAvvv_4S :  NeonI_3VSame_Constraint_impl<"saba", ".4s",  VPR128, v4i32,
 596                     0b1, 0b0, 0b10, 0b01111, Neon_saba>;
 597
 598
 599 // Vector Absolute Difference (Signed, Unsigned)
 600 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
 601 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
 602
 603 // Vector Absolute Difference (Floating Point)
 604 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
 605                                     int_arm_neon_vabds, int_arm_neon_vabds,
 606                                     int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
 607
 608 // Vector Reciprocal Step (Floating Point)
 609 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
 610                                        int_arm_neon_vrecps, int_arm_neon_vrecps,
 611                                        int_arm_neon_vrecps,
 612                                        v2f32, v4f32, v2f64, 0>;
 613
 614 // Vector Reciprocal Square Root Step (Floating Point)
 615 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
 616                                         int_arm_neon_vrsqrts,
 617                                         int_arm_neon_vrsqrts,
 618                                         int_arm_neon_vrsqrts,
 619                                         v2f32, v4f32, v2f64, 0>;
 620
 621 // Vector Comparisons
 622
 623 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
 624                         (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
 625 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
 626                          (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
 627 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
 628                         (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
 629 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
 630                         (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
 631 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
 632                         (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
 633
 634 // NeonI_compare_aliases class: swaps register operands to implement
 635 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
 636 class NeonI_compare_aliases<string asmop, string asmlane,
 637                             Instruction inst, RegisterOperand VPRC>
 638   : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
 639                     ", $Rm" # asmlane,
 640                   (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
 641
 642 // Vector Comparisons (Integer)
 643
 644 // Vector Compare Mask Equal (Integer)
 645 let isCommutable =1 in {
 646 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
 647 }
 648
 649 // Vector Compare Mask Higher or Same (Unsigned Integer)
 650 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
 651
 652 // Vector Compare Mask Greater Than or Equal (Integer)
 653 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
 654
 655 // Vector Compare Mask Higher (Unsigned Integer)
 656 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
 657
 658 // Vector Compare Mask Greater Than (Integer)
 659 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
 660
 661 // Vector Compare Mask Bitwise Test (Integer)
 662 defm CMTSTvvv:  NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
 663
 664 // Vector Compare Mask Less or Same (Unsigned Integer)
 665 // CMLS is alias for CMHS with operands reversed.
 666 def CMLSvvv_8B  : NeonI_compare_aliases<"cmls", ".8b",  CMHSvvv_8B,  VPR64>;
 667 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
 668 def CMLSvvv_4H  : NeonI_compare_aliases<"cmls", ".4h",  CMHSvvv_4H,  VPR64>;
 669 def CMLSvvv_8H  : NeonI_compare_aliases<"cmls", ".8h",  CMHSvvv_8H,  VPR128>;
 670 def CMLSvvv_2S  : NeonI_compare_aliases<"cmls", ".2s",  CMHSvvv_2S,  VPR64>;
 671 def CMLSvvv_4S  : NeonI_compare_aliases<"cmls", ".4s",  CMHSvvv_4S,  VPR128>;
 672 def CMLSvvv_2D  : NeonI_compare_aliases<"cmls", ".2d",  CMHSvvv_2D,  VPR128>;
 673
 674 // Vector Compare Mask Less Than or Equal (Integer)
 675 // CMLE is alias for CMGE with operands reversed.
 676 def CMLEvvv_8B  : NeonI_compare_aliases<"cmle", ".8b",  CMGEvvv_8B,  VPR64>;
 677 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
 678 def CMLEvvv_4H  : NeonI_compare_aliases<"cmle", ".4h",  CMGEvvv_4H,  VPR64>;
 679 def CMLEvvv_8H  : NeonI_compare_aliases<"cmle", ".8h",  CMGEvvv_8H,  VPR128>;
 680 def CMLEvvv_2S  : NeonI_compare_aliases<"cmle", ".2s",  CMGEvvv_2S,  VPR64>;
 681 def CMLEvvv_4S  : NeonI_compare_aliases<"cmle", ".4s",  CMGEvvv_4S,  VPR128>;
 682 def CMLEvvv_2D  : NeonI_compare_aliases<"cmle", ".2d",  CMGEvvv_2D,  VPR128>;
 683
 684 // Vector Compare Mask Lower (Unsigned Integer)
 685 // CMLO is alias for CMHI with operands reversed.
 686 def CMLOvvv_8B  : NeonI_compare_aliases<"cmlo", ".8b",  CMHIvvv_8B,  VPR64>;
 687 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
 688 def CMLOvvv_4H  : NeonI_compare_aliases<"cmlo", ".4h",  CMHIvvv_4H,  VPR64>;
 689 def CMLOvvv_8H  : NeonI_compare_aliases<"cmlo", ".8h",  CMHIvvv_8H,  VPR128>;
 690 def CMLOvvv_2S  : NeonI_compare_aliases<"cmlo", ".2s",  CMHIvvv_2S,  VPR64>;
 691 def CMLOvvv_4S  : NeonI_compare_aliases<"cmlo", ".4s",  CMHIvvv_4S,  VPR128>;
 692 def CMLOvvv_2D  : NeonI_compare_aliases<"cmlo", ".2d",  CMHIvvv_2D,  VPR128>;
 693
 694 // Vector Compare Mask Less Than (Integer)
 695 // CMLT is alias for CMGT with operands reversed.
 696 def CMLTvvv_8B  : NeonI_compare_aliases<"cmlt", ".8b",  CMGTvvv_8B,  VPR64>;
 697 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
 698 def CMLTvvv_4H  : NeonI_compare_aliases<"cmlt", ".4h",  CMGTvvv_4H,  VPR64>;
 699 def CMLTvvv_8H  : NeonI_compare_aliases<"cmlt", ".8h",  CMGTvvv_8H,  VPR128>;
 700 def CMLTvvv_2S  : NeonI_compare_aliases<"cmlt", ".2s",  CMGTvvv_2S,  VPR64>;
 701 def CMLTvvv_4S  : NeonI_compare_aliases<"cmlt", ".4s",  CMGTvvv_4S,  VPR128>;
 702 def CMLTvvv_2D  : NeonI_compare_aliases<"cmlt", ".2d",  CMGTvvv_2D,  VPR128>;
 703
 704
 705 def neon_uimm0_asmoperand : AsmOperandClass
 706 {
 707   let Name = "UImm0";
 708   let PredicateMethod = "isUImm<0>";
 709   let RenderMethod = "addImmOperands";
 710 }
 711
 712 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
 713   let ParserMatchClass = neon_uimm0_asmoperand;
 714   let PrintMethod = "printNeonUImm0Operand";
 715
 716 }
 717
 718 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
 719 {
 720   def _8B :  NeonI_2VMisc<0b0, u, 0b00, opcode,
 721              (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 722              asmop # "\t$Rd.8b, $Rn.8b, $Imm",
 723              [(set (v8i8 VPR64:$Rd),
 724                 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 725              NoItinerary>;
 726
 727   def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
 728              (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 729              asmop # "\t$Rd.16b, $Rn.16b, $Imm",
 730              [(set (v16i8 VPR128:$Rd),
 731                 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 732              NoItinerary>;
 733
 734   def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
 735             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 736             asmop # "\t$Rd.4h, $Rn.4h, $Imm",
 737             [(set (v4i16 VPR64:$Rd),
 738                (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 739             NoItinerary>;
 740
 741   def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
 742             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 743             asmop # "\t$Rd.8h, $Rn.8h, $Imm",
 744             [(set (v8i16 VPR128:$Rd),
 745                (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 746             NoItinerary>;
 747
 748   def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
 749             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 750             asmop # "\t$Rd.2s, $Rn.2s, $Imm",
 751             [(set (v2i32 VPR64:$Rd),
 752                (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 753             NoItinerary>;
 754
 755   def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
 756             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 757             asmop # "\t$Rd.4s, $Rn.4s, $Imm",
 758             [(set (v4i32 VPR128:$Rd),
 759                (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 760             NoItinerary>;
 761
 762   def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
 763             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 764             asmop # "\t$Rd.2d, $Rn.2d, $Imm",
 765             [(set (v2i64 VPR128:$Rd),
 766                (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 767             NoItinerary>;
 768 }
 769
 770 // Vector Compare Mask Equal to Zero (Integer)
 771 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
 772
 773 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
 774 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
 775
 776 // Vector Compare Mask Greater Than Zero (Signed Integer)
 777 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
 778
 779 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
 780 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
 781
 782 // Vector Compare Mask Less Than Zero (Signed Integer)
 783 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
 784
 785 // Vector Comparisons (Floating Point)
 786
 787 // Vector Compare Mask Equal (Floating Point)
 788 let isCommutable =1 in {
 789 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
 790                                       Neon_cmeq, Neon_cmeq,
 791                                       v2i32, v4i32, v2i64, 0>;
 792 }
 793
 794 // Vector Compare Mask Greater Than Or Equal (Floating Point)
 795 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
 796                                       Neon_cmge, Neon_cmge,
 797                                       v2i32, v4i32, v2i64, 0>;
 798
 799 // Vector Compare Mask Greater Than (Floating Point)
 800 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
 801                                       Neon_cmgt, Neon_cmgt,
 802                                       v2i32, v4i32, v2i64, 0>;
 803
 804 // Vector Compare Mask Less Than Or Equal (Floating Point)
 805 // FCMLE is alias for FCMGE with operands reversed.
 806 def FCMLEvvv_2S  : NeonI_compare_aliases<"fcmle", ".2s",  FCMGEvvv_2S,  VPR64>;
 807 def FCMLEvvv_4S  : NeonI_compare_aliases<"fcmle", ".4s",  FCMGEvvv_4S,  VPR128>;
 808 def FCMLEvvv_2D  : NeonI_compare_aliases<"fcmle", ".2d",  FCMGEvvv_2D,  VPR128>;
 809
 810 // Vector Compare Mask Less Than (Floating Point)
 811 // FCMLT is alias for FCMGT with operands reversed.
 812 def FCMLTvvv_2S  : NeonI_compare_aliases<"fcmlt", ".2s",  FCMGTvvv_2S,  VPR64>;
 813 def FCMLTvvv_4S  : NeonI_compare_aliases<"fcmlt", ".4s",  FCMGTvvv_4S,  VPR128>;
 814 def FCMLTvvv_2D  : NeonI_compare_aliases<"fcmlt", ".2d",  FCMGTvvv_2D,  VPR128>;
 815
 816
 817 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
 818                               string asmop, CondCode CC>
 819 {
 820   def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
 821             (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
 822             asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
 823             [(set (v2i32 VPR64:$Rd),
 824                (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpz32:$FPImm), CC)))],
 825             NoItinerary>;
 826
 827   def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
 828             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 829             asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
 830             [(set (v4i32 VPR128:$Rd),
 831                (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
 832             NoItinerary>;
 833
 834   def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
 835             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 836             asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
 837             [(set (v2i64 VPR128:$Rd),
 838                (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
 839             NoItinerary>;
 840 }
 841
 842 // Vector Compare Mask Equal to Zero (Floating Point)
 843 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
 844
 845 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
 846 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
 847
 848 // Vector Compare Mask Greater Than Zero (Floating Point)
 849 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
 850
 851 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
 852 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
 853
 854 // Vector Compare Mask Less Than Zero (Floating Point)
 855 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
 856
 857 // Vector Absolute Comparisons (Floating Point)
 858
 859 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
 860 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
 861                                       int_arm_neon_vacged, int_arm_neon_vacgeq,
 862                                       int_aarch64_neon_vacgeq,
 863                                       v2i32, v4i32, v2i64, 0>;
 864
 865 // Vector Absolute Compare Mask Greater Than (Floating Point)
 866 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
 867                                       int_arm_neon_vacgtd, int_arm_neon_vacgtq,
 868                                       int_aarch64_neon_vacgtq,
 869                                       v2i32, v4i32, v2i64, 0>;
 870
 871 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
 872 // FACLE is alias for FACGE with operands reversed.
 873 def FACLEvvv_2S  : NeonI_compare_aliases<"facle", ".2s",  FACGEvvv_2S,  VPR64>;
 874 def FACLEvvv_4S  : NeonI_compare_aliases<"facle", ".4s",  FACGEvvv_4S,  VPR128>;
 875 def FACLEvvv_2D  : NeonI_compare_aliases<"facle", ".2d",  FACGEvvv_2D,  VPR128>;
 876
 877 // Vector Absolute Compare Mask Less Than (Floating Point)
 878 // FACLT is alias for FACGT with operands reversed.
 879 def FACLTvvv_2S  : NeonI_compare_aliases<"faclt", ".2s",  FACGTvvv_2S,  VPR64>;
 880 def FACLTvvv_4S  : NeonI_compare_aliases<"faclt", ".4s",  FACGTvvv_4S,  VPR128>;
 881 def FACLTvvv_2D  : NeonI_compare_aliases<"faclt", ".2d",  FACGTvvv_2D,  VPR128>;
 882
 883 // Vector halving add (Integer Signed, Unsigned)
 884 defm SHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
 885                                         int_arm_neon_vhadds, 1>;
 886 defm UHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
 887                                         int_arm_neon_vhaddu, 1>;
 888
 889 // Vector halving sub (Integer Signed, Unsigned)
 890 defm SHSUBvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
 891                                         int_arm_neon_vhsubs, 0>;
 892 defm UHSUBvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
 893                                         int_arm_neon_vhsubu, 0>;
 894
 895 // Vector rouding halving add (Integer Signed, Unsigned)
 896 defm SRHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
 897                                          int_arm_neon_vrhadds, 1>;
 898 defm URHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
 899                                          int_arm_neon_vrhaddu, 1>;
 900
 901 // Vector Saturating add (Integer Signed, Unsigned)
 902 defm SQADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
 903                    int_arm_neon_vqadds, 1>;
 904 defm UQADDvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
 905                    int_arm_neon_vqaddu, 1>;
 906
 907 // Vector Saturating sub (Integer Signed, Unsigned)
 908 defm SQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
 909                    int_arm_neon_vqsubs, 1>;
 910 defm UQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
 911                    int_arm_neon_vqsubu, 1>;
 912
 913 // Vector Shift Left (Signed and Unsigned Integer)
 914 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
 915                  int_arm_neon_vshifts, 1>;
 916 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
 917                  int_arm_neon_vshiftu, 1>;
 918
 919 // Vector Saturating Shift Left (Signed and Unsigned Integer)
 920 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
 921                   int_arm_neon_vqshifts, 1>;
 922 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
 923                   int_arm_neon_vqshiftu, 1>;
 924
 925 // Vector Rouding Shift Left (Signed and Unsigned Integer)
 926 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
 927                   int_arm_neon_vrshifts, 1>;
 928 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
 929                   int_arm_neon_vrshiftu, 1>;
 930
 931 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
 932 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
 933                    int_arm_neon_vqrshifts, 1>;
 934 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
 935                    int_arm_neon_vqrshiftu, 1>;
 936
 937 // Vector Maximum (Signed and Unsigned Integer)
 938 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
 939 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
 940
 941 // Vector Minimum (Signed and Unsigned Integer)
 942 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
 943 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
 944
 945 // Vector Maximum (Floating Point)
 946 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
 947                                      int_arm_neon_vmaxs, int_arm_neon_vmaxs,
 948                                      int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
 949
 950 // Vector Minimum (Floating Point)
 951 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
 952                                      int_arm_neon_vmins, int_arm_neon_vmins,
 953                                      int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
 954
 955 // Vector maxNum (Floating Point) -  prefer a number over a quiet NaN)
 956 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
 957                                        int_aarch64_neon_vmaxnm,
 958                                        int_aarch64_neon_vmaxnm,
 959                                        int_aarch64_neon_vmaxnm,
 960                                        v2f32, v4f32, v2f64, 1>;
 961
 962 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
 963 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
 964                                        int_aarch64_neon_vminnm,
 965                                        int_aarch64_neon_vminnm,
 966                                        int_aarch64_neon_vminnm,
 967                                        v2f32, v4f32, v2f64, 1>;
 968
 969 // Vector Maximum Pairwise (Signed and Unsigned Integer)
 970 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
 971 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
 972
 973 // Vector Minimum Pairwise (Signed and Unsigned Integer)
 974 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
 975 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
 976
 977 // Vector Maximum Pairwise (Floating Point)
 978 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
 979                                      int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
 980                                      int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
 981
 982 // Vector Minimum Pairwise (Floating Point)
 983 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
 984                                      int_arm_neon_vpmins, int_arm_neon_vpmins,
 985                                      int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
 986
 987 // Vector maxNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 988 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
 989                                        int_aarch64_neon_vpmaxnm,
 990                                        int_aarch64_neon_vpmaxnm,
 991                                        int_aarch64_neon_vpmaxnm,
 992                                        v2f32, v4f32, v2f64, 1>;
 993
 994 // Vector minNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 995 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
 996                                        int_aarch64_neon_vpminnm,
 997                                        int_aarch64_neon_vpminnm,
 998                                        int_aarch64_neon_vpminnm,
 999                                        v2f32, v4f32, v2f64, 1>;
1000
1001 // Vector Addition Pairwise (Integer)
1002 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
1003
1004 // Vector Addition Pairwise (Floating Point)
1005 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
1006                                        int_arm_neon_vpadd,
1007                                        int_arm_neon_vpadd,
1008                                        int_arm_neon_vpadd,
1009                                        v2f32, v4f32, v2f64, 1>;
1010
1011 // Vector Saturating Doubling Multiply High
1012 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
1013                     int_arm_neon_vqdmulh, 1>;
1014
1015 // Vector Saturating Rouding Doubling Multiply High
1016 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
1017                      int_arm_neon_vqrdmulh, 1>;
1018
1019 // Vector Multiply Extended (Floating Point)
1020 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
1021                                       int_aarch64_neon_vmulx,
1022                                       int_aarch64_neon_vmulx,
1023                                       int_aarch64_neon_vmulx,
1024                                       v2f32, v4f32, v2f64, 1>;
1025
1026 // Patterns to match llvm.aarch64.* intrinsic for
1027 // ADDP, SMINP, UMINP, SMAXP, UMAXP having i32 as output
1028 class Neon_VectorPair_v2i32_pattern<SDPatternOperator opnode, Instruction INST>
1029   : Pat<(v1i32 (opnode (v2i32 VPR64:$Rn))),
1030         (EXTRACT_SUBREG
1031              (v2i32 (INST (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rn))),
1032              sub_32)>;
1033
1034 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_sminv, SMINPvvv_2S>;
1035 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_uminv, UMINPvvv_2S>;
1036 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_smaxv, SMAXPvvv_2S>;
1037 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_umaxv, UMAXPvvv_2S>;
1038 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_vaddv, ADDP_2S>;
1039
1040 // Vector Immediate Instructions
1041
1042 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
1043 {
1044   def _asmoperand : AsmOperandClass
1045     {
1046       let Name = "NeonMovImmShift" # PREFIX;
1047       let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
1048       let PredicateMethod = "isNeonMovImmShift" # PREFIX;
1049     }
1050 }
1051
1052 // Definition of vector immediates shift operands
1053
1054 // The selectable use-cases extract the shift operation
1055 // information from the OpCmode fields encoded in the immediate.
1056 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
1057   uint64_t OpCmode = N->getZExtValue();
1058   unsigned ShiftImm;
1059   unsigned ShiftOnesIn;
1060   unsigned HasShift =
1061     A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1062   if (!HasShift) return SDValue();
1063   return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1064 }]>;
1065
1066 // Vector immediates shift operands which accept LSL and MSL
1067 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1068 // or 0, 8 (LSLH) or 8, 16 (MSL).
1069 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1070 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1071 // LSLH restricts shift amount to  0, 8 out of 0, 8, 16, 24
1072 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1073
1074 multiclass neon_mov_imm_shift_operands<string PREFIX,
1075                                        string HALF, string ISHALF, code pred>
1076 {
1077    def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1078     {
1079       let PrintMethod =
1080         "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1081       let DecoderMethod =
1082         "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1083       let ParserMatchClass =
1084         !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1085     }
1086 }
1087
1088 defm neon_mov_imm_LSL  : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1089   unsigned ShiftImm;
1090   unsigned ShiftOnesIn;
1091   unsigned HasShift =
1092     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1093   return (HasShift && !ShiftOnesIn);
1094 }]>;
1095
1096 defm neon_mov_imm_MSL  : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1097   unsigned ShiftImm;
1098   unsigned ShiftOnesIn;
1099   unsigned HasShift =
1100     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1101   return (HasShift && ShiftOnesIn);
1102 }]>;
1103
1104 defm neon_mov_imm_LSLH  : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1105   unsigned ShiftImm;
1106   unsigned ShiftOnesIn;
1107   unsigned HasShift =
1108     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1109   return (HasShift && !ShiftOnesIn);
1110 }]>;
1111
1112 def neon_uimm1_asmoperand : AsmOperandClass
1113 {
1114   let Name = "UImm1";
1115   let PredicateMethod = "isUImm<1>";
1116   let RenderMethod = "addImmOperands";
1117 }
1118
1119 def neon_uimm2_asmoperand : AsmOperandClass
1120 {
1121   let Name = "UImm2";
1122   let PredicateMethod = "isUImm<2>";
1123   let RenderMethod = "addImmOperands";
1124 }
1125
1126 def neon_uimm8_asmoperand : AsmOperandClass
1127 {
1128   let Name = "UImm8";
1129   let PredicateMethod = "isUImm<8>";
1130   let RenderMethod = "addImmOperands";
1131 }
1132
1133 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1134   let ParserMatchClass = neon_uimm8_asmoperand;
1135   let PrintMethod = "printUImmHexOperand";
1136 }
1137
1138 def neon_uimm64_mask_asmoperand : AsmOperandClass
1139 {
1140   let Name = "NeonUImm64Mask";
1141   let PredicateMethod = "isNeonUImm64Mask";
1142   let RenderMethod = "addNeonUImm64MaskOperands";
1143 }
1144
1145 // MCOperand for 64-bit bytemask with each byte having only the
1146 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1147 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1148   let ParserMatchClass = neon_uimm64_mask_asmoperand;
1149   let PrintMethod = "printNeonUImm64MaskOperand";
1150 }
1151
1152 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1153                                    SDPatternOperator opnode>
1154 {
1155     // shift zeros, per word
1156     def _2S  : NeonI_1VModImm<0b0, op,
1157                               (outs VPR64:$Rd),
1158                               (ins neon_uimm8:$Imm,
1159                                 neon_mov_imm_LSL_operand:$Simm),
1160                               !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1161                               [(set (v2i32 VPR64:$Rd),
1162                                  (v2i32 (opnode (timm:$Imm),
1163                                    (neon_mov_imm_LSL_operand:$Simm))))],
1164                               NoItinerary> {
1165        bits<2> Simm;
1166        let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1167      }
1168
1169     def _4S  : NeonI_1VModImm<0b1, op,
1170                               (outs VPR128:$Rd),
1171                               (ins neon_uimm8:$Imm,
1172                                 neon_mov_imm_LSL_operand:$Simm),
1173                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1174                               [(set (v4i32 VPR128:$Rd),
1175                                  (v4i32 (opnode (timm:$Imm),
1176                                    (neon_mov_imm_LSL_operand:$Simm))))],
1177                               NoItinerary> {
1178       bits<2> Simm;
1179       let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1180     }
1181
1182     // shift zeros, per halfword
1183     def _4H  : NeonI_1VModImm<0b0, op,
1184                               (outs VPR64:$Rd),
1185                               (ins neon_uimm8:$Imm,
1186                                 neon_mov_imm_LSLH_operand:$Simm),
1187                               !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1188                               [(set (v4i16 VPR64:$Rd),
1189                                  (v4i16 (opnode (timm:$Imm),
1190                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1191                               NoItinerary> {
1192       bit  Simm;
1193       let cmode = {0b1, 0b0, Simm, 0b0};
1194     }
1195
1196     def _8H  : NeonI_1VModImm<0b1, op,
1197                               (outs VPR128:$Rd),
1198                               (ins neon_uimm8:$Imm,
1199                                 neon_mov_imm_LSLH_operand:$Simm),
1200                               !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1201                               [(set (v8i16 VPR128:$Rd),
1202                                  (v8i16 (opnode (timm:$Imm),
1203                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1204                               NoItinerary> {
1205       bit Simm;
1206       let cmode = {0b1, 0b0, Simm, 0b0};
1207      }
1208 }
1209
1210 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1211                                                    SDPatternOperator opnode,
1212                                                    SDPatternOperator neonopnode>
1213 {
1214   let Constraints = "$src = $Rd" in {
1215     // shift zeros, per word
1216     def _2S  : NeonI_1VModImm<0b0, op,
1217                  (outs VPR64:$Rd),
1218                  (ins VPR64:$src, neon_uimm8:$Imm,
1219                    neon_mov_imm_LSL_operand:$Simm),
1220                  !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1221                  [(set (v2i32 VPR64:$Rd),
1222                     (v2i32 (opnode (v2i32 VPR64:$src),
1223                       (v2i32 (neonopnode timm:$Imm,
1224                         neon_mov_imm_LSL_operand:$Simm)))))],
1225                  NoItinerary> {
1226       bits<2> Simm;
1227       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1228     }
1229
1230     def _4S  : NeonI_1VModImm<0b1, op,
1231                  (outs VPR128:$Rd),
1232                  (ins VPR128:$src, neon_uimm8:$Imm,
1233                    neon_mov_imm_LSL_operand:$Simm),
1234                  !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1235                  [(set (v4i32 VPR128:$Rd),
1236                     (v4i32 (opnode (v4i32 VPR128:$src),
1237                       (v4i32 (neonopnode timm:$Imm,
1238                         neon_mov_imm_LSL_operand:$Simm)))))],
1239                  NoItinerary> {
1240       bits<2> Simm;
1241       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1242     }
1243
1244     // shift zeros, per halfword
1245     def _4H  : NeonI_1VModImm<0b0, op,
1246                  (outs VPR64:$Rd),
1247                  (ins VPR64:$src, neon_uimm8:$Imm,
1248                    neon_mov_imm_LSLH_operand:$Simm),
1249                  !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1250                  [(set (v4i16 VPR64:$Rd),
1251                     (v4i16 (opnode (v4i16 VPR64:$src),
1252                        (v4i16 (neonopnode timm:$Imm,
1253                           neon_mov_imm_LSL_operand:$Simm)))))],
1254                  NoItinerary> {
1255       bit  Simm;
1256       let cmode = {0b1, 0b0, Simm, 0b1};
1257     }
1258
1259     def _8H  : NeonI_1VModImm<0b1, op,
1260                  (outs VPR128:$Rd),
1261                  (ins VPR128:$src, neon_uimm8:$Imm,
1262                    neon_mov_imm_LSLH_operand:$Simm),
1263                  !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1264                  [(set (v8i16 VPR128:$Rd),
1265                     (v8i16 (opnode (v8i16 VPR128:$src),
1266                       (v8i16 (neonopnode timm:$Imm,
1267                         neon_mov_imm_LSL_operand:$Simm)))))],
1268                  NoItinerary> {
1269       bit Simm;
1270       let cmode = {0b1, 0b0, Simm, 0b1};
1271     }
1272   }
1273 }
1274
1275 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1276                                    SDPatternOperator opnode>
1277 {
1278     // shift ones, per word
1279     def _2S  : NeonI_1VModImm<0b0, op,
1280                              (outs VPR64:$Rd),
1281                              (ins neon_uimm8:$Imm,
1282                                neon_mov_imm_MSL_operand:$Simm),
1283                              !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1284                               [(set (v2i32 VPR64:$Rd),
1285                                  (v2i32 (opnode (timm:$Imm),
1286                                    (neon_mov_imm_MSL_operand:$Simm))))],
1287                              NoItinerary> {
1288        bit Simm;
1289        let cmode = {0b1, 0b1, 0b0, Simm};
1290      }
1291
1292    def _4S  : NeonI_1VModImm<0b1, op,
1293                               (outs VPR128:$Rd),
1294                               (ins neon_uimm8:$Imm,
1295                                 neon_mov_imm_MSL_operand:$Simm),
1296                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1297                               [(set (v4i32 VPR128:$Rd),
1298                                  (v4i32 (opnode (timm:$Imm),
1299                                    (neon_mov_imm_MSL_operand:$Simm))))],
1300                               NoItinerary> {
1301      bit Simm;
1302      let cmode = {0b1, 0b1, 0b0, Simm};
1303    }
1304 }
1305
1306 // Vector Move Immediate Shifted
1307 let isReMaterializable = 1 in {
1308 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1309 }
1310
1311 // Vector Move Inverted Immediate Shifted
1312 let isReMaterializable = 1 in {
1313 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1314 }
1315
1316 // Vector Bitwise Bit Clear (AND NOT) - immediate
1317 let isReMaterializable = 1 in {
1318 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1319                                                          and, Neon_mvni>;
1320 }
1321
1322 // Vector Bitwise OR - immedidate
1323
1324 let isReMaterializable = 1 in {
1325 defm ORRvi_lsl   : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1326                                                            or, Neon_movi>;
1327 }
1328
1329 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1330 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1331 // BIC immediate instructions selection requires additional patterns to
1332 // transform Neon_movi operands into BIC immediate operands
1333
1334 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1335   uint64_t OpCmode = N->getZExtValue();
1336   unsigned ShiftImm;
1337   unsigned ShiftOnesIn;
1338   (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1339   // LSLH restricts shift amount to  0, 8 which are encoded as 0 and 1
1340   // Transform encoded shift amount 0 to 1 and 1 to 0.
1341   return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1342 }]>;
1343
1344 def neon_mov_imm_LSLH_transform_operand
1345   : ImmLeaf<i32, [{
1346     unsigned ShiftImm;
1347     unsigned ShiftOnesIn;
1348     unsigned HasShift =
1349       A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1350     return (HasShift && !ShiftOnesIn); }],
1351   neon_mov_imm_LSLH_transform_XFORM>;
1352
1353 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0xff, LSL 8)
1354 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0xff)
1355 def : Pat<(v4i16 (and VPR64:$src,
1356             (v4i16 (Neon_movi 255,
1357               neon_mov_imm_LSLH_transform_operand:$Simm)))),
1358           (BICvi_lsl_4H VPR64:$src, 255,
1359             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1360
1361 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0xff, LSL 8)
1362 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0xff)
1363 def : Pat<(v8i16 (and VPR128:$src,
1364             (v8i16 (Neon_movi 255,
1365               neon_mov_imm_LSLH_transform_operand:$Simm)))),
1366           (BICvi_lsl_8H VPR128:$src, 255,
1367             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1368
1369 def : Pat<(v8i8 (and VPR64:$src,
1370                   (bitconvert(v4i16 (Neon_movi 255,
1371                     neon_mov_imm_LSLH_transform_operand:$Simm))))),
1372           (BICvi_lsl_4H VPR64:$src, 255,
1373             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1374 def : Pat<(v2i32 (and VPR64:$src,
1375                  (bitconvert(v4i16 (Neon_movi 255,
1376                    neon_mov_imm_LSLH_transform_operand:$Simm))))),
1377           (BICvi_lsl_4H VPR64:$src, 255,
1378             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1379 def : Pat<(v1i64 (and VPR64:$src,
1380                 (bitconvert(v4i16 (Neon_movi 255,
1381                   neon_mov_imm_LSLH_transform_operand:$Simm))))),
1382         (BICvi_lsl_4H VPR64:$src, 255,
1383           neon_mov_imm_LSLH_transform_operand:$Simm)>;
1384
1385 def : Pat<(v16i8 (and VPR128:$src,
1386                  (bitconvert(v8i16 (Neon_movi 255,
1387                    neon_mov_imm_LSLH_transform_operand:$Simm))))),
1388         (BICvi_lsl_8H VPR128:$src, 255,
1389           neon_mov_imm_LSLH_transform_operand:$Simm)>;
1390 def : Pat<(v4i32 (and VPR128:$src,
1391                  (bitconvert(v8i16 (Neon_movi 255,
1392                    neon_mov_imm_LSLH_transform_operand:$Simm))))),
1393         (BICvi_lsl_8H VPR128:$src, 255,
1394           neon_mov_imm_LSLH_transform_operand:$Simm)>;
1395 def : Pat<(v2i64 (and VPR128:$src,
1396                  (bitconvert(v8i16 (Neon_movi 255,
1397                    neon_mov_imm_LSLH_transform_operand:$Simm))))),
1398         (BICvi_lsl_8H VPR128:$src, 255,
1399           neon_mov_imm_LSLH_transform_operand:$Simm)>;
1400
1401 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1402                                    SDPatternOperator neonopnode,
1403                                    Instruction INST4H,
1404                                    Instruction INST8H,
1405                                    Instruction INST2S,
1406                                    Instruction INST4S> {
1407   def : Pat<(v8i8 (opnode VPR64:$src,
1408                     (bitconvert(v4i16 (neonopnode timm:$Imm,
1409                       neon_mov_imm_LSLH_operand:$Simm))))),
1410             (INST4H VPR64:$src, neon_uimm8:$Imm,
1411               neon_mov_imm_LSLH_operand:$Simm)>;
1412   def : Pat<(v2i32 (opnode VPR64:$src,
1413                    (bitconvert(v4i16 (neonopnode timm:$Imm,
1414                      neon_mov_imm_LSLH_operand:$Simm))))),
1415             (INST4H VPR64:$src, neon_uimm8:$Imm,
1416               neon_mov_imm_LSLH_operand:$Simm)>;
1417   def : Pat<(v1i64 (opnode VPR64:$src,
1418                   (bitconvert(v4i16 (neonopnode timm:$Imm,
1419                     neon_mov_imm_LSLH_operand:$Simm))))),
1420           (INST4H VPR64:$src, neon_uimm8:$Imm,
1421             neon_mov_imm_LSLH_operand:$Simm)>;
1422
1423   def : Pat<(v16i8 (opnode VPR128:$src,
1424                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1425                      neon_mov_imm_LSLH_operand:$Simm))))),
1426           (INST8H VPR128:$src, neon_uimm8:$Imm,
1427             neon_mov_imm_LSLH_operand:$Simm)>;
1428   def : Pat<(v4i32 (opnode VPR128:$src,
1429                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1430                      neon_mov_imm_LSLH_operand:$Simm))))),
1431           (INST8H VPR128:$src, neon_uimm8:$Imm,
1432             neon_mov_imm_LSLH_operand:$Simm)>;
1433   def : Pat<(v2i64 (opnode VPR128:$src,
1434                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1435                      neon_mov_imm_LSLH_operand:$Simm))))),
1436           (INST8H VPR128:$src, neon_uimm8:$Imm,
1437             neon_mov_imm_LSLH_operand:$Simm)>;
1438
1439   def : Pat<(v8i8 (opnode VPR64:$src,
1440                     (bitconvert(v2i32 (neonopnode timm:$Imm,
1441                       neon_mov_imm_LSLH_operand:$Simm))))),
1442             (INST2S VPR64:$src, neon_uimm8:$Imm,
1443               neon_mov_imm_LSLH_operand:$Simm)>;
1444   def : Pat<(v4i16 (opnode VPR64:$src,
1445                    (bitconvert(v2i32 (neonopnode timm:$Imm,
1446                      neon_mov_imm_LSLH_operand:$Simm))))),
1447             (INST2S VPR64:$src, neon_uimm8:$Imm,
1448               neon_mov_imm_LSLH_operand:$Simm)>;
1449   def : Pat<(v1i64 (opnode VPR64:$src,
1450                   (bitconvert(v2i32 (neonopnode timm:$Imm,
1451                     neon_mov_imm_LSLH_operand:$Simm))))),
1452           (INST2S VPR64:$src, neon_uimm8:$Imm,
1453             neon_mov_imm_LSLH_operand:$Simm)>;
1454
1455   def : Pat<(v16i8 (opnode VPR128:$src,
1456                    (bitconvert(v4i32 (neonopnode timm:$Imm,
1457                      neon_mov_imm_LSLH_operand:$Simm))))),
1458           (INST4S VPR128:$src, neon_uimm8:$Imm,
1459             neon_mov_imm_LSLH_operand:$Simm)>;
1460   def : Pat<(v8i16 (opnode VPR128:$src,
1461                    (bitconvert(v4i32 (neonopnode timm:$Imm,
1462                      neon_mov_imm_LSLH_operand:$Simm))))),
1463           (INST4S VPR128:$src, neon_uimm8:$Imm,
1464             neon_mov_imm_LSLH_operand:$Simm)>;
1465   def : Pat<(v2i64 (opnode VPR128:$src,
1466                    (bitconvert(v4i32 (neonopnode timm:$Imm,
1467                      neon_mov_imm_LSLH_operand:$Simm))))),
1468           (INST4S VPR128:$src, neon_uimm8:$Imm,
1469             neon_mov_imm_LSLH_operand:$Simm)>;
1470 }
1471
1472 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1473 defm : Neon_bitwiseVi_patterns<and, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H,
1474                                BICvi_lsl_2S, BICvi_lsl_4S>;
1475
1476 // Additional patterns for Vector Bitwise OR - immedidate
1477 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H,
1478                                ORRvi_lsl_2S, ORRvi_lsl_4S>;
1479
1480
1481 // Vector Move Immediate Masked
1482 let isReMaterializable = 1 in {
1483 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1484 }
1485
1486 // Vector Move Inverted Immediate Masked
1487 let isReMaterializable = 1 in {
1488 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1489 }
1490
1491 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1492                                 Instruction inst, RegisterOperand VPRC>
1493   : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1494                         (inst VPRC:$Rd, neon_uimm8:$Imm,  0), 0b0>;
1495
1496 // Aliases for Vector Move Immediate Shifted
1497 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1498 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1499 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1500 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1501
1502 // Aliases for Vector Move Inverted Immediate Shifted
1503 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1504 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1505 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1506 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1507
1508 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1509 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1510 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1511 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1512 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1513
1514 // Aliases for Vector Bitwise OR - immedidate
1515 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1516 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1517 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1518 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1519
1520 //  Vector Move Immediate - per byte
1521 let isReMaterializable = 1 in {
1522 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1523                                (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1524                                "movi\t$Rd.8b, $Imm",
1525                                [(set (v8i8 VPR64:$Rd),
1526                                   (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1527                                 NoItinerary> {
1528   let cmode = 0b1110;
1529 }
1530
1531 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1532                                 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1533                                 "movi\t$Rd.16b, $Imm",
1534                                 [(set (v16i8 VPR128:$Rd),
1535                                    (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1536                                  NoItinerary> {
1537   let cmode = 0b1110;
1538 }
1539 }
1540
1541 // Vector Move Immediate - bytemask, per double word
1542 let isReMaterializable = 1 in {
1543 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1544                                (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1545                                "movi\t $Rd.2d, $Imm",
1546                                [(set (v2i64 VPR128:$Rd),
1547                                   (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1548                                NoItinerary> {
1549   let cmode = 0b1110;
1550 }
1551 }
1552
1553 // Vector Move Immediate - bytemask, one doubleword
1554
1555 let isReMaterializable = 1 in {
1556 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1557                            (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1558                            "movi\t $Rd, $Imm",
1559                            [(set (v1i64 FPR64:$Rd),
1560                              (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1561                            NoItinerary> {
1562   let cmode = 0b1110;
1563 }
1564 }
1565
1566 // Vector Floating Point Move Immediate
1567
1568 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1569                       Operand immOpType, bit q, bit op>
1570   : NeonI_1VModImm<q, op,
1571                    (outs VPRC:$Rd), (ins immOpType:$Imm),
1572                    "fmov\t$Rd" # asmlane # ", $Imm",
1573                    [(set (OpTy VPRC:$Rd),
1574                       (OpTy (Neon_fmovi (timm:$Imm))))],
1575                    NoItinerary> {
1576      let cmode = 0b1111;
1577    }
1578
1579 let isReMaterializable = 1 in {
1580 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64,  v2f32, fmov32_operand, 0b0, 0b0>;
1581 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1582 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1583 }
1584
1585 // Vector Shift (Immediate)
1586 // Immediate in [0, 63]
1587 def imm0_63 : Operand<i32> {
1588   let ParserMatchClass = uimm6_asmoperand;
1589 }
1590
1591 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1592 // as follows:
1593 //
1594 //    Offset    Encoding
1595 //     8        immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1596 //     16       immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1597 //     32       immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1598 //     64       immh:immb<6>   = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1599 //
1600 // The shift right immediate amount, in the range 1 to element bits, is computed
1601 // as Offset - UInt(immh:immb).  The shift left immediate amount, in the range 0
1602 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1603
1604 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1605   let Name = "ShrImm" # OFFSET;
1606   let RenderMethod = "addImmOperands";
1607   let DiagnosticType = "ShrImm" # OFFSET;
1608 }
1609
1610 class shr_imm<string OFFSET> : Operand<i32> {
1611   let EncoderMethod = "getShiftRightImm" # OFFSET;
1612   let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1613   let ParserMatchClass =
1614     !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1615 }
1616
1617 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1618 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1619 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1620 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1621
1622 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1623 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1624 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1625 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1626
1627 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1628   let Name = "ShlImm" # OFFSET;
1629   let RenderMethod = "addImmOperands";
1630   let DiagnosticType = "ShlImm" # OFFSET;
1631 }
1632
1633 class shl_imm<string OFFSET> : Operand<i32> {
1634   let EncoderMethod = "getShiftLeftImm" # OFFSET;
1635   let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1636   let ParserMatchClass =
1637     !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1638 }
1639
1640 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1641 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1642 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1643 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1644
1645 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1646 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1647 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1648 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1649
1650 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1651                RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1652   : NeonI_2VShiftImm<q, u, opcode,
1653                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1654                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1655                      [(set (Ty VPRC:$Rd),
1656                         (Ty (OpNode (Ty VPRC:$Rn),
1657                           (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1658                      NoItinerary>;
1659
1660 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1661   // 64-bit vector types.
1662   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1663     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1664   }
1665
1666   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1667     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1668   }
1669
1670   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1671     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1672   }
1673
1674   // 128-bit vector types.
1675   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1676     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1677   }
1678
1679   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1680     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1681   }
1682
1683   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1684     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1685   }
1686
1687   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1688     let Inst{22} = 0b1;        // immh:immb = 1xxxxxx
1689   }
1690 }
1691
1692 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1693   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1694                      OpNode> {
1695     let Inst{22-19} = 0b0001;
1696   }
1697
1698   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1699                      OpNode> {
1700     let Inst{22-20} = 0b001;
1701   }
1702
1703   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1704                      OpNode> {
1705      let Inst{22-21} = 0b01;
1706   }
1707
1708   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1709                       OpNode> {
1710                       let Inst{22-19} = 0b0001;
1711                     }
1712
1713   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1714                      OpNode> {
1715                      let Inst{22-20} = 0b001;
1716                     }
1717
1718   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1719                      OpNode> {
1720                       let Inst{22-21} = 0b01;
1721                     }
1722
1723   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1724                      OpNode> {
1725                       let Inst{22} = 0b1;
1726                     }
1727 }
1728
1729 // Shift left
1730 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1731
1732 // Shift right
1733 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1734 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1735
1736 def Neon_High16B : PatFrag<(ops node:$in),
1737                            (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1738 def Neon_High8H  : PatFrag<(ops node:$in),
1739                            (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1740 def Neon_High4S  : PatFrag<(ops node:$in),
1741                            (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1742 def Neon_High2D  : PatFrag<(ops node:$in),
1743                            (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1744 def Neon_High4float : PatFrag<(ops node:$in),
1745                                (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1746 def Neon_High2double : PatFrag<(ops node:$in),
1747                                (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1748
1749 def Neon_Low16B : PatFrag<(ops node:$in),
1750                           (v8i8 (extract_subvector (v16i8 node:$in),
1751                                                    (iPTR 0)))>;
1752 def Neon_Low8H : PatFrag<(ops node:$in),
1753                          (v4i16 (extract_subvector (v8i16 node:$in),
1754                                                    (iPTR 0)))>;
1755 def Neon_Low4S : PatFrag<(ops node:$in),
1756                          (v2i32 (extract_subvector (v4i32 node:$in),
1757                                                    (iPTR 0)))>;
1758 def Neon_Low2D : PatFrag<(ops node:$in),
1759                          (v1i64 (extract_subvector (v2i64 node:$in),
1760                                                    (iPTR 0)))>;
1761 def Neon_Low4float : PatFrag<(ops node:$in),
1762                              (v2f32 (extract_subvector (v4f32 node:$in),
1763                                                        (iPTR 0)))>;
1764 def Neon_Low2double : PatFrag<(ops node:$in),
1765                               (v1f64 (extract_subvector (v2f64 node:$in),
1766                                                         (iPTR 0)))>;
1767
1768 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1769                    string SrcT, ValueType DestTy, ValueType SrcTy,
1770                    Operand ImmTy, SDPatternOperator ExtOp>
1771   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1772                      (ins VPR64:$Rn, ImmTy:$Imm),
1773                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1774                      [(set (DestTy VPR128:$Rd),
1775                         (DestTy (shl
1776                           (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1777                             (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1778                      NoItinerary>;
1779
1780 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1781                        string SrcT, ValueType DestTy, ValueType SrcTy,
1782                        int StartIndex, Operand ImmTy,
1783                        SDPatternOperator ExtOp, PatFrag getTop>
1784   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1785                      (ins VPR128:$Rn, ImmTy:$Imm),
1786                      asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1787                      [(set (DestTy VPR128:$Rd),
1788                         (DestTy (shl
1789                           (DestTy (ExtOp
1790                             (SrcTy (getTop VPR128:$Rn)))),
1791                               (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1792                      NoItinerary>;
1793
1794 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1795                          SDNode ExtOp> {
1796   // 64-bit vector types.
1797   def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1798                          shl_imm8, ExtOp> {
1799     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1800   }
1801
1802   def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1803                          shl_imm16, ExtOp> {
1804     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1805   }
1806
1807   def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1808                          shl_imm32, ExtOp> {
1809     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1810   }
1811
1812   // 128-bit vector types
1813   def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1814                               8, shl_imm8, ExtOp, Neon_High16B> {
1815     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1816   }
1817
1818   def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1819                              4, shl_imm16, ExtOp, Neon_High8H> {
1820     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1821   }
1822
1823   def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1824                              2, shl_imm32, ExtOp, Neon_High4S> {
1825     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1826   }
1827
1828   // Use other patterns to match when the immediate is 0.
1829   def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1830             (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1831
1832   def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1833             (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1834
1835   def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1836             (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1837
1838   def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1839             (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1840
1841   def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1842             (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1843
1844   def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1845             (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1846 }
1847
1848 // Shift left long
1849 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1850 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1851
1852 class NeonI_ext_len_alias<string asmop, string lane, string laneOp,
1853                        Instruction inst, RegisterOperand VPRC,
1854                        RegisterOperand VPRCOp>
1855   : NeonInstAlias<asmop # "\t$Rd" # lane #", $Rn" # laneOp,
1856                   (inst VPRC:$Rd, VPRCOp:$Rn, 0), 0b0>;
1857
1858 // Signed integer lengthen (vector) is alias for SSHLL Vd, Vn, #0
1859 // Signed integer lengthen (vector, second part) is alias for SSHLL2 Vd, Vn, #0
1860 // FIXME: This is actually the preferred syntax but TableGen can't deal with
1861 // custom printing of aliases.
1862 def SXTLvv_8B  : NeonI_ext_len_alias<"sxtl", ".8h", ".8b",  SSHLLvvi_8B, VPR128, VPR64>;
1863 def SXTLvv_4H  : NeonI_ext_len_alias<"sxtl", ".4s", ".4h",  SSHLLvvi_4H, VPR128, VPR64>;
1864 def SXTLvv_2S  : NeonI_ext_len_alias<"sxtl", ".2d", ".2s",  SSHLLvvi_2S, VPR128, VPR64>;
1865 def SXTL2vv_16B : NeonI_ext_len_alias<"sxtl2", ".8h", ".16b",  SSHLLvvi_16B, VPR128, VPR128>;
1866 def SXTL2vv_8H  : NeonI_ext_len_alias<"sxtl2", ".4s", ".8h",  SSHLLvvi_8H, VPR128, VPR128>;
1867 def SXTL2vv_4S  : NeonI_ext_len_alias<"sxtl2", ".2d", ".4s",  SSHLLvvi_4S, VPR128, VPR128>;
1868
1869 // Unsigned integer lengthen (vector) is alias for USHLL Vd, Vn, #0
1870 // Unsigned integer lengthen (vector, second part) is alias for USHLL2 Vd, Vn, #0
1871 // FIXME: This is actually the preferred syntax but TableGen can't deal with
1872 // custom printing of aliases.
1873 def UXTLvv_8B  : NeonI_ext_len_alias<"uxtl", ".8h", ".8b",  USHLLvvi_8B, VPR128, VPR64>;
1874 def UXTLvv_4H  : NeonI_ext_len_alias<"uxtl", ".4s", ".4h",  USHLLvvi_4H, VPR128, VPR64>;
1875 def UXTLvv_2S  : NeonI_ext_len_alias<"uxtl", ".2d", ".2s",  USHLLvvi_2S, VPR128, VPR64>;
1876 def UXTL2vv_16B : NeonI_ext_len_alias<"uxtl2", ".8h", ".16b",  USHLLvvi_16B, VPR128, VPR128>;
1877 def UXTL2vv_8H  : NeonI_ext_len_alias<"uxtl2", ".4s", ".8h",  USHLLvvi_8H, VPR128, VPR128>;
1878 def UXTL2vv_4S  : NeonI_ext_len_alias<"uxtl2", ".2d", ".4s",  USHLLvvi_4S, VPR128, VPR128>;
1879
1880 def : Pat<(v8i16 (anyext (v8i8 VPR64:$Rn))), (USHLLvvi_8B VPR64:$Rn, 0)>;
1881 def : Pat<(v4i32 (anyext (v4i16 VPR64:$Rn))), (USHLLvvi_4H VPR64:$Rn, 0)>;
1882 def : Pat<(v2i64 (anyext (v2i32 VPR64:$Rn))), (USHLLvvi_2S VPR64:$Rn, 0)>;
1883
1884 // Rounding/Saturating shift
1885 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1886                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1887                   SDPatternOperator OpNode>
1888   : NeonI_2VShiftImm<q, u, opcode,
1889                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1890                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1891                      [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1892                         (i32 ImmTy:$Imm))))],
1893                      NoItinerary>;
1894
1895 // shift right (vector by immediate)
1896 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1897                            SDPatternOperator OpNode> {
1898   def _8B  : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1899                          OpNode> {
1900     let Inst{22-19} = 0b0001;
1901   }
1902
1903   def _4H  : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1904                          OpNode> {
1905     let Inst{22-20} = 0b001;
1906   }
1907
1908   def _2S  : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1909                          OpNode> {
1910     let Inst{22-21} = 0b01;
1911   }
1912
1913   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1914                          OpNode> {
1915     let Inst{22-19} = 0b0001;
1916   }
1917
1918   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1919                         OpNode> {
1920     let Inst{22-20} = 0b001;
1921   }
1922
1923   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1924                         OpNode> {
1925     let Inst{22-21} = 0b01;
1926   }
1927
1928   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1929                         OpNode> {
1930     let Inst{22} = 0b1;
1931   }
1932 }
1933
1934 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1935                           SDPatternOperator OpNode> {
1936   // 64-bit vector types.
1937   def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1938                         OpNode> {
1939     let Inst{22-19} = 0b0001;
1940   }
1941
1942   def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1943                         OpNode> {
1944     let Inst{22-20} = 0b001;
1945   }
1946
1947   def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1948                         OpNode> {
1949     let Inst{22-21} = 0b01;
1950   }
1951
1952   // 128-bit vector types.
1953   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1954                          OpNode> {
1955     let Inst{22-19} = 0b0001;
1956   }
1957
1958   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1959                         OpNode> {
1960     let Inst{22-20} = 0b001;
1961   }
1962
1963   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1964                         OpNode> {
1965     let Inst{22-21} = 0b01;
1966   }
1967
1968   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1969                         OpNode> {
1970     let Inst{22} = 0b1;
1971   }
1972 }
1973
1974 // Rounding shift right
1975 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1976                                 int_aarch64_neon_vsrshr>;
1977 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1978                                 int_aarch64_neon_vurshr>;
1979
1980 // Saturating shift left unsigned
1981 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1982
1983 // Saturating shift left
1984 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1985 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1986
1987 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1988                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1989                   SDNode OpNode>
1990   : NeonI_2VShiftImm<q, u, opcode,
1991            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1992            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1993            [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1994               (Ty (OpNode (Ty VPRC:$Rn),
1995                 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
1996            NoItinerary> {
1997   let Constraints = "$src = $Rd";
1998 }
1999
2000 // Shift Right accumulate
2001 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
2002   def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2003                         OpNode> {
2004     let Inst{22-19} = 0b0001;
2005   }
2006
2007   def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2008                         OpNode> {
2009     let Inst{22-20} = 0b001;
2010   }
2011
2012   def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2013                         OpNode> {
2014     let Inst{22-21} = 0b01;
2015   }
2016
2017   def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2018                          OpNode> {
2019     let Inst{22-19} = 0b0001;
2020   }
2021
2022   def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2023                         OpNode> {
2024     let Inst{22-20} = 0b001;
2025   }
2026
2027   def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2028                         OpNode> {
2029     let Inst{22-21} = 0b01;
2030   }
2031
2032   def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2033                         OpNode> {
2034     let Inst{22} = 0b1;
2035   }
2036 }
2037
2038 // Shift right and accumulate
2039 defm SSRAvvi    : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
2040 defm USRAvvi    : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
2041
2042 // Rounding shift accumulate
2043 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
2044                     RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2045                     SDPatternOperator OpNode>
2046   : NeonI_2VShiftImm<q, u, opcode,
2047                      (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2048                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2049                      [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
2050                         (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
2051                      NoItinerary> {
2052   let Constraints = "$src = $Rd";
2053 }
2054
2055 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
2056                              SDPatternOperator OpNode> {
2057   def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2058                           OpNode> {
2059     let Inst{22-19} = 0b0001;
2060   }
2061
2062   def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2063                           OpNode> {
2064     let Inst{22-20} = 0b001;
2065   }
2066
2067   def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2068                           OpNode> {
2069     let Inst{22-21} = 0b01;
2070   }
2071
2072   def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2073                            OpNode> {
2074     let Inst{22-19} = 0b0001;
2075   }
2076
2077   def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2078                           OpNode> {
2079     let Inst{22-20} = 0b001;
2080   }
2081
2082   def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2083                           OpNode> {
2084     let Inst{22-21} = 0b01;
2085   }
2086
2087   def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2088                           OpNode> {
2089     let Inst{22} = 0b1;
2090   }
2091 }
2092
2093 // Rounding shift right and accumulate
2094 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
2095 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
2096
2097 // Shift insert by immediate
2098 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
2099                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2100                   SDPatternOperator OpNode>
2101     : NeonI_2VShiftImm<q, u, opcode,
2102            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2103            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2104            [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
2105              (i32 ImmTy:$Imm))))],
2106            NoItinerary> {
2107   let Constraints = "$src = $Rd";
2108 }
2109
2110 // shift left insert (vector by immediate)
2111 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
2112   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
2113                         int_aarch64_neon_vsli> {
2114     let Inst{22-19} = 0b0001;
2115   }
2116
2117   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
2118                         int_aarch64_neon_vsli> {
2119     let Inst{22-20} = 0b001;
2120   }
2121
2122   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
2123                         int_aarch64_neon_vsli> {
2124     let Inst{22-21} = 0b01;
2125   }
2126
2127     // 128-bit vector types
2128   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
2129                          int_aarch64_neon_vsli> {
2130     let Inst{22-19} = 0b0001;
2131   }
2132
2133   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
2134                         int_aarch64_neon_vsli> {
2135     let Inst{22-20} = 0b001;
2136   }
2137
2138   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
2139                         int_aarch64_neon_vsli> {
2140     let Inst{22-21} = 0b01;
2141   }
2142
2143   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
2144                         int_aarch64_neon_vsli> {
2145     let Inst{22} = 0b1;
2146   }
2147 }
2148
2149 // shift right insert (vector by immediate)
2150 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
2151     // 64-bit vector types.
2152   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2153                         int_aarch64_neon_vsri> {
2154     let Inst{22-19} = 0b0001;
2155   }
2156
2157   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2158                         int_aarch64_neon_vsri> {
2159     let Inst{22-20} = 0b001;
2160   }
2161
2162   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2163                         int_aarch64_neon_vsri> {
2164     let Inst{22-21} = 0b01;
2165   }
2166
2167     // 128-bit vector types
2168   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2169                          int_aarch64_neon_vsri> {
2170     let Inst{22-19} = 0b0001;
2171   }
2172
2173   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2174                         int_aarch64_neon_vsri> {
2175     let Inst{22-20} = 0b001;
2176   }
2177
2178   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2179                         int_aarch64_neon_vsri> {
2180     let Inst{22-21} = 0b01;
2181   }
2182
2183   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2184                         int_aarch64_neon_vsri> {
2185     let Inst{22} = 0b1;
2186   }
2187 }
2188
2189 // Shift left and insert
2190 defm SLIvvi   : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2191
2192 // Shift right and insert
2193 defm SRIvvi   : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2194
2195 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2196                     string SrcT, Operand ImmTy>
2197   : NeonI_2VShiftImm<q, u, opcode,
2198                      (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2199                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2200                      [], NoItinerary>;
2201
2202 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2203                        string SrcT, Operand ImmTy>
2204   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2205                      (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2206                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2207                      [], NoItinerary> {
2208   let Constraints = "$src = $Rd";
2209 }
2210
2211 // left long shift by immediate
2212 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2213   def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2214     let Inst{22-19} = 0b0001;
2215   }
2216
2217   def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2218     let Inst{22-20} = 0b001;
2219   }
2220
2221   def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2222     let Inst{22-21} = 0b01;
2223   }
2224
2225   // Shift Narrow High
2226   def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2227                               shr_imm8> {
2228     let Inst{22-19} = 0b0001;
2229   }
2230
2231   def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2232                              shr_imm16> {
2233     let Inst{22-20} = 0b001;
2234   }
2235
2236   def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2237                              shr_imm32> {
2238     let Inst{22-21} = 0b01;
2239   }
2240 }
2241
2242 // Shift right narrow
2243 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2244
2245 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2246 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2247 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2248 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2249 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2250 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2251 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2252 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2253
2254 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2255                               (v2i64 (concat_vectors (v1i64 node:$Rm),
2256                                                      (v1i64 node:$Rn)))>;
2257 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2258                               (v8i16 (concat_vectors (v4i16 node:$Rm),
2259                                                      (v4i16 node:$Rn)))>;
2260 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2261                               (v4i32 (concat_vectors (v2i32 node:$Rm),
2262                                                      (v2i32 node:$Rn)))>;
2263 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2264                               (v4f32 (concat_vectors (v2f32 node:$Rm),
2265                                                      (v2f32 node:$Rn)))>;
2266 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2267                               (v2f64 (concat_vectors (v1f64 node:$Rm),
2268                                                      (v1f64 node:$Rn)))>;
2269
2270 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2271                              (v8i16 (srl (v8i16 node:$lhs),
2272                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2273 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2274                              (v4i32 (srl (v4i32 node:$lhs),
2275                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2276 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2277                              (v2i64 (srl (v2i64 node:$lhs),
2278                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2279 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2280                              (v8i16 (sra (v8i16 node:$lhs),
2281                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2282 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2283                              (v4i32 (sra (v4i32 node:$lhs),
2284                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2285 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2286                              (v2i64 (sra (v2i64 node:$lhs),
2287                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2288
2289 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2290 multiclass Neon_shiftNarrow_patterns<string shr> {
2291   def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2292               (i32 shr_imm8:$Imm)))),
2293             (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2294   def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2295               (i32 shr_imm16:$Imm)))),
2296             (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2297   def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2298               (i32 shr_imm32:$Imm)))),
2299             (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2300
2301   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2302               (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2303                 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2304             (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2305                          VPR128:$Rn, imm:$Imm)>;
2306   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2307               (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2308                 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2309             (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2310                         VPR128:$Rn, imm:$Imm)>;
2311   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2312               (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2313                 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2314             (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2315                         VPR128:$Rn, imm:$Imm)>;
2316 }
2317
2318 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2319   def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2320             (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2321   def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2322             (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2323   def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2324             (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2325
2326   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2327                 (v1i64 (bitconvert (v8i8
2328                     (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2329             (!cast<Instruction>(prefix # "_16B")
2330                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2331                 VPR128:$Rn, imm:$Imm)>;
2332   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2333                 (v1i64 (bitconvert (v4i16
2334                     (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2335             (!cast<Instruction>(prefix # "_8H")
2336                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2337                 VPR128:$Rn, imm:$Imm)>;
2338   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2339                 (v1i64 (bitconvert (v2i32
2340                     (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2341             (!cast<Instruction>(prefix # "_4S")
2342                   (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2343                   VPR128:$Rn, imm:$Imm)>;
2344 }
2345
2346 defm : Neon_shiftNarrow_patterns<"lshr">;
2347 defm : Neon_shiftNarrow_patterns<"ashr">;
2348
2349 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2350 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2351 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2352 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2353 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2354 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2355 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2356
2357 // Convert fix-point and float-pointing
2358 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2359                 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2360                 Operand ImmTy, SDPatternOperator IntOp>
2361   : NeonI_2VShiftImm<q, u, opcode,
2362                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2363                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2364                      [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2365                        (i32 ImmTy:$Imm))))],
2366                      NoItinerary>;
2367
2368 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2369                               SDPatternOperator IntOp> {
2370   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2371                       shr_imm32, IntOp> {
2372     let Inst{22-21} = 0b01;
2373   }
2374
2375   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2376                       shr_imm32, IntOp> {
2377     let Inst{22-21} = 0b01;
2378   }
2379
2380   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2381                       shr_imm64, IntOp> {
2382     let Inst{22} = 0b1;
2383   }
2384 }
2385
2386 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2387                               SDPatternOperator IntOp> {
2388   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2389                       shr_imm32, IntOp> {
2390     let Inst{22-21} = 0b01;
2391   }
2392
2393   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2394                       shr_imm32, IntOp> {
2395     let Inst{22-21} = 0b01;
2396   }
2397
2398   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2399                       shr_imm64, IntOp> {
2400     let Inst{22} = 0b1;
2401   }
2402 }
2403
2404 // Convert fixed-point to floating-point
2405 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2406                                    int_arm_neon_vcvtfxs2fp>;
2407 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2408                                    int_arm_neon_vcvtfxu2fp>;
2409
2410 // Convert floating-point to fixed-point
2411 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2412                                    int_arm_neon_vcvtfp2fxs>;
2413 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2414                                    int_arm_neon_vcvtfp2fxu>;
2415
2416 multiclass Neon_sshll2_0<SDNode ext>
2417 {
2418   def _v8i8  : PatFrag<(ops node:$Rn),
2419                        (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2420   def _v4i16 : PatFrag<(ops node:$Rn),
2421                        (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2422   def _v2i32 : PatFrag<(ops node:$Rn),
2423                        (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2424 }
2425
2426 defm NI_sext_high : Neon_sshll2_0<sext>;
2427 defm NI_zext_high : Neon_sshll2_0<zext>;
2428
2429
2430 //===----------------------------------------------------------------------===//
2431 // Multiclasses for NeonI_Across
2432 //===----------------------------------------------------------------------===//
2433
2434 // Variant 1
2435
2436 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2437                             string asmop, SDPatternOperator opnode>
2438 {
2439     def _1h8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2440                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2441                 asmop # "\t$Rd, $Rn.8b",
2442                 [(set (v1i16 FPR16:$Rd),
2443                     (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2444                 NoItinerary>;
2445
2446     def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2447                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2448                 asmop # "\t$Rd, $Rn.16b",
2449                 [(set (v1i16 FPR16:$Rd),
2450                     (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2451                 NoItinerary>;
2452
2453     def _1s4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2454                 (outs FPR32:$Rd), (ins VPR64:$Rn),
2455                 asmop # "\t$Rd, $Rn.4h",
2456                 [(set (v1i32 FPR32:$Rd),
2457                     (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2458                 NoItinerary>;
2459
2460     def _1s8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2461                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2462                 asmop # "\t$Rd, $Rn.8h",
2463                 [(set (v1i32 FPR32:$Rd),
2464                     (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2465                 NoItinerary>;
2466
2467     // _1d2s doesn't exist!
2468
2469     def _1d4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2470                 (outs FPR64:$Rd), (ins VPR128:$Rn),
2471                 asmop # "\t$Rd, $Rn.4s",
2472                 [(set (v1i64 FPR64:$Rd),
2473                     (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2474                 NoItinerary>;
2475 }
2476
2477 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2478 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2479
2480 // Variant 2
2481
2482 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2483                             string asmop, SDPatternOperator opnode>
2484 {
2485     def _1b8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2486                 (outs FPR8:$Rd), (ins VPR64:$Rn),
2487                 asmop # "\t$Rd, $Rn.8b",
2488                 [(set (v1i8 FPR8:$Rd),
2489                     (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2490                 NoItinerary>;
2491
2492     def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2493                 (outs FPR8:$Rd), (ins VPR128:$Rn),
2494                 asmop # "\t$Rd, $Rn.16b",
2495                 [(set (v1i8 FPR8:$Rd),
2496                     (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2497                 NoItinerary>;
2498
2499     def _1h4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2500                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2501                 asmop # "\t$Rd, $Rn.4h",
2502                 [(set (v1i16 FPR16:$Rd),
2503                     (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2504                 NoItinerary>;
2505
2506     def _1h8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2507                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2508                 asmop # "\t$Rd, $Rn.8h",
2509                 [(set (v1i16 FPR16:$Rd),
2510                     (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2511                 NoItinerary>;
2512
2513     // _1s2s doesn't exist!
2514
2515     def _1s4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2516                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2517                 asmop # "\t$Rd, $Rn.4s",
2518                 [(set (v1i32 FPR32:$Rd),
2519                     (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2520                 NoItinerary>;
2521 }
2522
2523 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2524 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2525
2526 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2527 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2528
2529 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2530
2531 // Variant 3
2532
2533 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2534                             string asmop, SDPatternOperator opnode> {
2535     def _1s4s:  NeonI_2VAcross<0b1, u, size, opcode,
2536                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2537                 asmop # "\t$Rd, $Rn.4s",
2538                 [(set (f32 FPR32:$Rd),
2539                     (f32 (opnode (v4f32 VPR128:$Rn))))],
2540                 NoItinerary>;
2541 }
2542
2543 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2544                                 int_aarch64_neon_vmaxnmv>;
2545 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2546                                 int_aarch64_neon_vminnmv>;
2547
2548 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2549                               int_aarch64_neon_vmaxv>;
2550 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2551                               int_aarch64_neon_vminv>;
2552
2553 // The followings are for instruction class (Perm)
2554
2555 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2556                     string asmop, RegisterOperand OpVPR, string OpS,
2557                     SDPatternOperator opnode, ValueType Ty>
2558   : NeonI_Perm<q, size, opcode,
2559                (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2560                asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2561                [(set (Ty OpVPR:$Rd),
2562                   (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2563                NoItinerary>;
2564
2565 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2566                           SDPatternOperator opnode> {
2567   def _8b  : NeonI_Permute<0b0, 0b00, opcode, asmop,
2568                            VPR64, "8b", opnode, v8i8>;
2569   def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2570                            VPR128, "16b",opnode, v16i8>;
2571   def _4h  : NeonI_Permute<0b0, 0b01, opcode, asmop,
2572                            VPR64, "4h", opnode, v4i16>;
2573   def _8h  : NeonI_Permute<0b1, 0b01, opcode, asmop,
2574                            VPR128, "8h", opnode, v8i16>;
2575   def _2s  : NeonI_Permute<0b0, 0b10, opcode, asmop,
2576                            VPR64, "2s", opnode, v2i32>;
2577   def _4s  : NeonI_Permute<0b1, 0b10, opcode, asmop,
2578                            VPR128, "4s", opnode, v4i32>;
2579   def _2d  : NeonI_Permute<0b1, 0b11, opcode, asmop,
2580                            VPR128, "2d", opnode, v2i64>;
2581 }
2582
2583 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2584 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2585 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2586 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2587 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2588 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2589
2590 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2591   def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2592             (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2593
2594   def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2595             (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2596
2597   def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2598             (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2599 }
2600
2601 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2602 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2603 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2604 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2605 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2606 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2607
2608 // The followings are for instruction class (3V Diff)
2609
2610 // normal long/long2 pattern
2611 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2612                  string asmop, string ResS, string OpS,
2613                  SDPatternOperator opnode, SDPatternOperator ext,
2614                  RegisterOperand OpVPR,
2615                  ValueType ResTy, ValueType OpTy>
2616   : NeonI_3VDiff<q, u, size, opcode,
2617                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2618                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2619                  [(set (ResTy VPR128:$Rd),
2620                     (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2621                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2622                  NoItinerary>;
2623
2624 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2625                         string asmop, SDPatternOperator opnode,
2626                         bit Commutable = 0> {
2627   let isCommutable = Commutable in {
2628     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2629                            opnode, sext, VPR64, v8i16, v8i8>;
2630     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2631                            opnode, sext, VPR64, v4i32, v4i16>;
2632     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2633                            opnode, sext, VPR64, v2i64, v2i32>;
2634   }
2635 }
2636
2637 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2638                          SDPatternOperator opnode, bit Commutable = 0> {
2639   let isCommutable = Commutable in {
2640     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2641                             opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2642     def _4s8h  : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2643                             opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2644     def _2d4s  : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2645                             opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2646   }
2647 }
2648
2649 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2650                         SDPatternOperator opnode, bit Commutable = 0> {
2651   let isCommutable = Commutable in {
2652     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2653                            opnode, zext, VPR64, v8i16, v8i8>;
2654     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2655                            opnode, zext, VPR64, v4i32, v4i16>;
2656     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2657                            opnode, zext, VPR64, v2i64, v2i32>;
2658   }
2659 }
2660
2661 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2662                          SDPatternOperator opnode, bit Commutable = 0> {
2663   let isCommutable = Commutable in {
2664     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2665                             opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2666     def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2667                            opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2668     def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2669                            opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2670   }
2671 }
2672
2673 defm SADDLvvv :  NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2674 defm UADDLvvv :  NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2675
2676 defm SADDL2vvv :  NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2677 defm UADDL2vvv :  NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2678
2679 defm SSUBLvvv :  NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2680 defm USUBLvvv :  NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2681
2682 defm SSUBL2vvv :  NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2683 defm USUBL2vvv :  NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2684
2685 // normal wide/wide2 pattern
2686 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2687                  string asmop, string ResS, string OpS,
2688                  SDPatternOperator opnode, SDPatternOperator ext,
2689                  RegisterOperand OpVPR,
2690                  ValueType ResTy, ValueType OpTy>
2691   : NeonI_3VDiff<q, u, size, opcode,
2692                  (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2693                  asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2694                  [(set (ResTy VPR128:$Rd),
2695                     (ResTy (opnode (ResTy VPR128:$Rn),
2696                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2697                  NoItinerary>;
2698
2699 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2700                         SDPatternOperator opnode> {
2701   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2702                          opnode, sext, VPR64, v8i16, v8i8>;
2703   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2704                          opnode, sext, VPR64, v4i32, v4i16>;
2705   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2706                          opnode, sext, VPR64, v2i64, v2i32>;
2707 }
2708
2709 defm SADDWvvv :  NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2710 defm SSUBWvvv :  NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2711
2712 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2713                          SDPatternOperator opnode> {
2714   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2715                           opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2716   def _4s8h  : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2717                           opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2718   def _2d4s  : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2719                           opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2720 }
2721
2722 defm SADDW2vvv :  NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2723 defm SSUBW2vvv :  NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2724
2725 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2726                         SDPatternOperator opnode> {
2727   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2728                          opnode, zext, VPR64, v8i16, v8i8>;
2729   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2730                          opnode, zext, VPR64, v4i32, v4i16>;
2731   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2732                          opnode, zext, VPR64, v2i64, v2i32>;
2733 }
2734
2735 defm UADDWvvv :  NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2736 defm USUBWvvv :  NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2737
2738 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2739                          SDPatternOperator opnode> {
2740   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2741                           opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2742   def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2743                          opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2744   def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2745                          opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2746 }
2747
2748 defm UADDW2vvv :  NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2749 defm USUBW2vvv :  NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2750
2751 // Get the high half part of the vector element.
2752 multiclass NeonI_get_high {
2753   def _8h : PatFrag<(ops node:$Rn),
2754                     (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2755                                              (v8i16 (Neon_vdup (i32 8)))))))>;
2756   def _4s : PatFrag<(ops node:$Rn),
2757                     (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2758                                               (v4i32 (Neon_vdup (i32 16)))))))>;
2759   def _2d : PatFrag<(ops node:$Rn),
2760                     (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2761                                               (v2i64 (Neon_vdup (i32 32)))))))>;
2762 }
2763
2764 defm NI_get_hi : NeonI_get_high;
2765
2766 // pattern for addhn/subhn with 2 operands
2767 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2768                            string asmop, string ResS, string OpS,
2769                            SDPatternOperator opnode, SDPatternOperator get_hi,
2770                            ValueType ResTy, ValueType OpTy>
2771   : NeonI_3VDiff<q, u, size, opcode,
2772                  (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2773                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2774                  [(set (ResTy VPR64:$Rd),
2775                     (ResTy (get_hi
2776                       (OpTy (opnode (OpTy VPR128:$Rn),
2777                                     (OpTy VPR128:$Rm))))))],
2778                  NoItinerary>;
2779
2780 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2781                                 SDPatternOperator opnode, bit Commutable = 0> {
2782   let isCommutable = Commutable in {
2783     def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2784                                      opnode, NI_get_hi_8h, v8i8, v8i16>;
2785     def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2786                                      opnode, NI_get_hi_4s, v4i16, v4i32>;
2787     def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2788                                      opnode, NI_get_hi_2d, v2i32, v2i64>;
2789   }
2790 }
2791
2792 defm ADDHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2793 defm SUBHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2794
2795 // pattern for operation with 2 operands
2796 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2797                     string asmop, string ResS, string OpS,
2798                     SDPatternOperator opnode,
2799                     RegisterOperand ResVPR, RegisterOperand OpVPR,
2800                     ValueType ResTy, ValueType OpTy>
2801   : NeonI_3VDiff<q, u, size, opcode,
2802                  (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2803                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2804                  [(set (ResTy ResVPR:$Rd),
2805                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2806                  NoItinerary>;
2807
2808 // normal narrow pattern
2809 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2810                           SDPatternOperator opnode, bit Commutable = 0> {
2811   let isCommutable = Commutable in {
2812     def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2813                               opnode, VPR64, VPR128, v8i8, v8i16>;
2814     def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2815                               opnode, VPR64, VPR128, v4i16, v4i32>;
2816     def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2817                               opnode, VPR64, VPR128, v2i32, v2i64>;
2818   }
2819 }
2820
2821 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2822 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2823
2824 // pattern for acle intrinsic with 3 operands
2825 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2826                      string asmop, string ResS, string OpS>
2827   : NeonI_3VDiff<q, u, size, opcode,
2828                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2829                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2830                  [], NoItinerary> {
2831   let Constraints = "$src = $Rd";
2832   let neverHasSideEffects = 1;
2833 }
2834
2835 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2836   def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2837   def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2838   def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2839 }
2840
2841 defm ADDHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2842 defm SUBHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2843
2844 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2845 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2846
2847 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2848 // part.
2849 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2850                         SDPatternOperator coreop>
2851   : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2852                       (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2853                                                         (SrcTy VPR128:$Rm)))))),
2854         (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2855               VPR128:$Rn, VPR128:$Rm)>;
2856
2857 // addhn2 patterns
2858 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8,  v8i16,
2859           BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2860 def : NarrowHighHalfPat<ADDHN2vvv_8h4s,  v4i16, v4i32,
2861           BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2862 def : NarrowHighHalfPat<ADDHN2vvv_4s2d,  v2i32, v2i64,
2863           BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2864
2865 // subhn2 patterns
2866 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8,  v8i16,
2867           BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2868 def : NarrowHighHalfPat<SUBHN2vvv_8h4s,  v4i16, v4i32,
2869           BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2870 def : NarrowHighHalfPat<SUBHN2vvv_4s2d,  v2i32, v2i64,
2871           BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2872
2873 // raddhn2 patterns
2874 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vraddhn>;
2875 def : NarrowHighHalfPat<RADDHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vraddhn>;
2876 def : NarrowHighHalfPat<RADDHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vraddhn>;
2877
2878 // rsubhn2 patterns
2879 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vrsubhn>;
2880 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vrsubhn>;
2881 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vrsubhn>;
2882
2883 // pattern that need to extend result
2884 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2885                      string asmop, string ResS, string OpS,
2886                      SDPatternOperator opnode,
2887                      RegisterOperand OpVPR,
2888                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2889   : NeonI_3VDiff<q, u, size, opcode,
2890                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2891                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2892                  [(set (ResTy VPR128:$Rd),
2893                     (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2894                                                 (OpTy OpVPR:$Rm))))))],
2895                  NoItinerary>;
2896
2897 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2898                            SDPatternOperator opnode, bit Commutable = 0> {
2899   let isCommutable = Commutable in {
2900     def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2901                                opnode, VPR64, v8i16, v8i8, v8i8>;
2902     def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2903                                opnode, VPR64, v4i32, v4i16, v4i16>;
2904     def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2905                                opnode, VPR64, v2i64, v2i32, v2i32>;
2906   }
2907 }
2908
2909 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2910 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2911
2912 multiclass NeonI_Op_High<SDPatternOperator op> {
2913   def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2914                      (op (v8i8 (Neon_High16B node:$Rn)),
2915                          (v8i8 (Neon_High16B node:$Rm)))>;
2916   def _8H  : PatFrag<(ops node:$Rn, node:$Rm),
2917                      (op (v4i16 (Neon_High8H node:$Rn)),
2918                          (v4i16 (Neon_High8H node:$Rm)))>;
2919   def _4S  : PatFrag<(ops node:$Rn, node:$Rm),
2920                      (op (v2i32 (Neon_High4S node:$Rn)),
2921                          (v2i32 (Neon_High4S node:$Rm)))>;
2922 }
2923
2924 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2925 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2926 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2927 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2928 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2929 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2930
2931 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2932                             bit Commutable = 0> {
2933   let isCommutable = Commutable in {
2934     def _8h8b  : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2935                                 !cast<PatFrag>(opnode # "_16B"),
2936                                 VPR128, v8i16, v16i8, v8i8>;
2937     def _4s4h  : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2938                                 !cast<PatFrag>(opnode # "_8H"),
2939                                 VPR128, v4i32, v8i16, v4i16>;
2940     def _2d2s  : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2941                                 !cast<PatFrag>(opnode # "_4S"),
2942                                 VPR128, v2i64, v4i32, v2i32>;
2943   }
2944 }
2945
2946 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2947 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2948
2949 // For pattern that need two operators being chained.
2950 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2951                      string asmop, string ResS, string OpS,
2952                      SDPatternOperator opnode, SDPatternOperator subop,
2953                      RegisterOperand OpVPR,
2954                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2955   : NeonI_3VDiff<q, u, size, opcode,
2956                  (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2957                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2958                  [(set (ResTy VPR128:$Rd),
2959                     (ResTy (opnode
2960                       (ResTy VPR128:$src),
2961                       (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2962                                                  (OpTy OpVPR:$Rm))))))))],
2963                  NoItinerary> {
2964   let Constraints = "$src = $Rd";
2965 }
2966
2967 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2968                              SDPatternOperator opnode, SDPatternOperator subop>{
2969   def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2970                              opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2971   def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2972                              opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2973   def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2974                              opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2975 }
2976
2977 defm SABALvvv :  NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2978                                    add, int_arm_neon_vabds>;
2979 defm UABALvvv :  NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2980                                    add, int_arm_neon_vabdu>;
2981
2982 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2983                               SDPatternOperator opnode, string subop> {
2984   def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2985                              opnode, !cast<PatFrag>(subop # "_16B"),
2986                              VPR128, v8i16, v16i8, v8i8>;
2987   def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2988                              opnode, !cast<PatFrag>(subop # "_8H"),
2989                              VPR128, v4i32, v8i16, v4i16>;
2990   def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2991                              opnode, !cast<PatFrag>(subop # "_4S"),
2992                              VPR128, v2i64, v4i32, v2i32>;
2993 }
2994
2995 defm SABAL2vvv :  NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2996                                      "NI_sabdl_hi">;
2997 defm UABAL2vvv :  NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2998                                      "NI_uabdl_hi">;
2999
3000 // Long pattern with 2 operands
3001 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
3002                           SDPatternOperator opnode, bit Commutable = 0> {
3003   let isCommutable = Commutable in {
3004     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3005                               opnode, VPR128, VPR64, v8i16, v8i8>;
3006     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3007                               opnode, VPR128, VPR64, v4i32, v4i16>;
3008     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3009                               opnode, VPR128, VPR64, v2i64, v2i32>;
3010   }
3011 }
3012
3013 defm SMULLvvv :  NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
3014 defm UMULLvvv :  NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
3015
3016 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
3017                            string asmop, string ResS, string OpS,
3018                            SDPatternOperator opnode,
3019                            ValueType ResTy, ValueType OpTy>
3020   : NeonI_3VDiff<q, u, size, opcode,
3021                  (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3022                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3023                  [(set (ResTy VPR128:$Rd),
3024                     (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
3025                  NoItinerary>;
3026
3027 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
3028                                    string opnode, bit Commutable = 0> {
3029   let isCommutable = Commutable in {
3030     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3031                                       !cast<PatFrag>(opnode # "_16B"),
3032                                       v8i16, v16i8>;
3033     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3034                                      !cast<PatFrag>(opnode # "_8H"),
3035                                      v4i32, v8i16>;
3036     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3037                                      !cast<PatFrag>(opnode # "_4S"),
3038                                      v2i64, v4i32>;
3039   }
3040 }
3041
3042 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
3043                                          "NI_smull_hi", 1>;
3044 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
3045                                          "NI_umull_hi", 1>;
3046
3047 // Long pattern with 3 operands
3048 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
3049                      string asmop, string ResS, string OpS,
3050                      SDPatternOperator opnode,
3051                      ValueType ResTy, ValueType OpTy>
3052   : NeonI_3VDiff<q, u, size, opcode,
3053                  (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
3054                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3055                  [(set (ResTy VPR128:$Rd),
3056                     (ResTy (opnode
3057                       (ResTy VPR128:$src),
3058                       (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
3059                NoItinerary> {
3060   let Constraints = "$src = $Rd";
3061 }
3062
3063 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
3064                              SDPatternOperator opnode> {
3065   def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3066                              opnode, v8i16, v8i8>;
3067   def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3068                              opnode, v4i32, v4i16>;
3069   def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3070                              opnode, v2i64, v2i32>;
3071 }
3072
3073 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3074                          (add node:$Rd,
3075                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3076
3077 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3078                          (add node:$Rd,
3079                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3080
3081 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3082                          (sub node:$Rd,
3083                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3084
3085 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3086                          (sub node:$Rd,
3087                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3088
3089 defm SMLALvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
3090 defm UMLALvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
3091
3092 defm SMLSLvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
3093 defm UMLSLvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
3094
3095 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
3096                            string asmop, string ResS, string OpS,
3097                            SDPatternOperator subop, SDPatternOperator opnode,
3098                            RegisterOperand OpVPR,
3099                            ValueType ResTy, ValueType OpTy>
3100   : NeonI_3VDiff<q, u, size, opcode,
3101                (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
3102                asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3103                [(set (ResTy VPR128:$Rd),
3104                   (ResTy (subop
3105                     (ResTy VPR128:$src),
3106                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
3107                NoItinerary> {
3108   let Constraints = "$src = $Rd";
3109 }
3110
3111 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
3112                                    SDPatternOperator subop, string opnode> {
3113   def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3114                                     subop, !cast<PatFrag>(opnode # "_16B"),
3115                                     VPR128, v8i16, v16i8>;
3116   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3117                                    subop, !cast<PatFrag>(opnode # "_8H"),
3118                                    VPR128, v4i32, v8i16>;
3119   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3120                                    subop, !cast<PatFrag>(opnode # "_4S"),
3121                                    VPR128, v2i64, v4i32>;
3122 }
3123
3124 defm SMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
3125                                           add, "NI_smull_hi">;
3126 defm UMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
3127                                           add, "NI_umull_hi">;
3128
3129 defm SMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
3130                                           sub, "NI_smull_hi">;
3131 defm UMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
3132                                           sub, "NI_umull_hi">;
3133
3134 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
3135                                     SDPatternOperator opnode> {
3136   def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3137                                    opnode, int_arm_neon_vqdmull,
3138                                    VPR64, v4i32, v4i16>;
3139   def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3140                                    opnode, int_arm_neon_vqdmull,
3141                                    VPR64, v2i64, v2i32>;
3142 }
3143
3144 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
3145                                            int_arm_neon_vqadds>;
3146 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
3147                                            int_arm_neon_vqsubs>;
3148
3149 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
3150                          SDPatternOperator opnode, bit Commutable = 0> {
3151   let isCommutable = Commutable in {
3152     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3153                               opnode, VPR128, VPR64, v4i32, v4i16>;
3154     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3155                               opnode, VPR128, VPR64, v2i64, v2i32>;
3156   }
3157 }
3158
3159 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3160                                 int_arm_neon_vqdmull, 1>;
3161
3162 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3163                                    string opnode, bit Commutable = 0> {
3164   let isCommutable = Commutable in {
3165     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3166                                      !cast<PatFrag>(opnode # "_8H"),
3167                                      v4i32, v8i16>;
3168     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3169                                      !cast<PatFrag>(opnode # "_4S"),
3170                                      v2i64, v4i32>;
3171   }
3172 }
3173
3174 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3175                                            "NI_qdmull_hi", 1>;
3176
3177 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3178                                      SDPatternOperator opnode> {
3179   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3180                                    opnode, NI_qdmull_hi_8H,
3181                                    VPR128, v4i32, v8i16>;
3182   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3183                                    opnode, NI_qdmull_hi_4S,
3184                                    VPR128, v2i64, v4i32>;
3185 }
3186
3187 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3188                                              int_arm_neon_vqadds>;
3189 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3190                                              int_arm_neon_vqsubs>;
3191
3192 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3193                          SDPatternOperator opnode_8h8b,
3194                          SDPatternOperator opnode_1q1d, bit Commutable = 0> {
3195   let isCommutable = Commutable in {
3196     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3197                               opnode_8h8b, VPR128, VPR64, v8i16, v8i8>;
3198
3199     def _1q1d : NeonI_3VD_2Op<0b0, u, 0b11, opcode, asmop, "1q", "1d",
3200                               opnode_1q1d, VPR128, VPR64, v16i8, v1i64>;
3201   }
3202 }
3203
3204 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp,
3205                               int_aarch64_neon_vmull_p64, 1>;
3206
3207 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3208                                    string opnode, bit Commutable = 0> {
3209   let isCommutable = Commutable in {
3210     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3211                                       !cast<PatFrag>(opnode # "_16B"),
3212                                       v8i16, v16i8>;
3213
3214     def _1q2d :
3215       NeonI_3VDiff<0b1, u, 0b11, opcode,
3216                    (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3217                    asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3218                    [(set (v16i8 VPR128:$Rd),
3219                       (v16i8 (int_aarch64_neon_vmull_p64
3220                         (v1i64 (scalar_to_vector
3221                           (i64 (vector_extract (v2i64 VPR128:$Rn), 1)))),
3222                         (v1i64 (scalar_to_vector
3223                           (i64 (vector_extract (v2i64 VPR128:$Rm), 1)))))))],
3224                    NoItinerary>;
3225   }
3226 }
3227
3228 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3229                                          1>;
3230
3231 // End of implementation for instruction class (3V Diff)
3232
3233 // The followings are vector load/store multiple N-element structure
3234 // (class SIMD lselem).
3235
3236 // ld1:         load multiple 1-element structure to 1/2/3/4 registers.
3237 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3238 //              The structure consists of a sequence of sets of N values.
3239 //              The first element of the structure is placed in the first lane
3240 //              of the first first vector, the second element in the first lane
3241 //              of the second vector, and so on.
3242 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3243 // the three 64-bit vectors list {BA, DC, FE}.
3244 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3245 // 64-bit vectors list {DA, EB, FC}.
3246 // Store instructions store multiple structure to N registers like load.
3247
3248
3249 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3250                     RegisterOperand VecList, string asmop>
3251   : NeonI_LdStMult<q, 1, opcode, size,
3252                  (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3253                  asmop # "\t$Rt, [$Rn]",
3254                  [],
3255                  NoItinerary> {
3256   let mayLoad = 1;
3257   let neverHasSideEffects = 1;
3258 }
3259
3260 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3261   def _8B : NeonI_LDVList<0, opcode, 0b00,
3262                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3263
3264   def _4H : NeonI_LDVList<0, opcode, 0b01,
3265                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3266
3267   def _2S : NeonI_LDVList<0, opcode, 0b10,
3268                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3269
3270   def _16B : NeonI_LDVList<1, opcode, 0b00,
3271                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3272
3273   def _8H : NeonI_LDVList<1, opcode, 0b01,
3274                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3275
3276   def _4S : NeonI_LDVList<1, opcode, 0b10,
3277                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3278
3279   def _2D : NeonI_LDVList<1, opcode, 0b11,
3280                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3281 }
3282
3283 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3284 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3285 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3286
3287 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3288
3289 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3290
3291 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3292
3293 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3294 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3295 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3296
3297 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3298 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3299
3300 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3301 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3302
3303 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3304                     RegisterOperand VecList, string asmop>
3305   : NeonI_LdStMult<q, 0, opcode, size,
3306                  (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3307                  asmop # "\t$Rt, [$Rn]",
3308                  [],
3309                  NoItinerary> {
3310   let mayStore = 1;
3311   let neverHasSideEffects = 1;
3312 }
3313
3314 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3315   def _8B : NeonI_STVList<0, opcode, 0b00,
3316                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3317
3318   def _4H : NeonI_STVList<0, opcode, 0b01,
3319                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3320
3321   def _2S : NeonI_STVList<0, opcode, 0b10,
3322                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3323
3324   def _16B : NeonI_STVList<1, opcode, 0b00,
3325                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3326
3327   def _8H : NeonI_STVList<1, opcode, 0b01,
3328                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3329
3330   def _4S : NeonI_STVList<1, opcode, 0b10,
3331                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3332
3333   def _2D : NeonI_STVList<1, opcode, 0b11,
3334                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3335 }
3336
3337 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3338 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3339 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3340
3341 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3342
3343 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3344
3345 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3346
3347 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3348 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3349 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3350
3351 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3352 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3353
3354 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3355 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3356
3357 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3358 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3359
3360 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3361 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3362
3363 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3364 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3365
3366 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3367 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3368
3369 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3370 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3371
3372 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3373 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3374
3375 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3376           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3377 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3378           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3379
3380 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3381           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3382 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3383           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3384
3385 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3386           (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3387 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3388           (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3389
3390 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3391           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3392 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3393           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3394
3395 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3396           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3397 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3398           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3399
3400 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3401           (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3402 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3403           (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3404
3405 // Match load/store of v1i8/v1i16/v1i32 type to FPR8/FPR16/FPR32 load/store.
3406 // FIXME: for now we have v1i8, v1i16, v1i32 legal types, if they are illegal,
3407 // these patterns are not needed any more.
3408 def : Pat<(v1i8 (load GPR64xsp:$addr)), (LSFP8_LDR $addr, 0)>;
3409 def : Pat<(v1i16 (load GPR64xsp:$addr)), (LSFP16_LDR $addr, 0)>;
3410 def : Pat<(v1i32 (load GPR64xsp:$addr)), (LSFP32_LDR $addr, 0)>;
3411
3412 def : Pat<(store (v1i8 FPR8:$value), GPR64xsp:$addr),
3413           (LSFP8_STR $value, $addr, 0)>;
3414 def : Pat<(store (v1i16 FPR16:$value), GPR64xsp:$addr),
3415           (LSFP16_STR $value, $addr, 0)>;
3416 def : Pat<(store (v1i32 FPR32:$value), GPR64xsp:$addr),
3417           (LSFP32_STR $value, $addr, 0)>;
3418
3419
3420 // End of vector load/store multiple N-element structure(class SIMD lselem)
3421
3422 // The followings are post-index vector load/store multiple N-element
3423 // structure(class SIMD lselem-post)
3424 def exact1_asmoperand : AsmOperandClass {
3425   let Name = "Exact1";
3426   let PredicateMethod = "isExactImm<1>";
3427   let RenderMethod = "addImmOperands";
3428 }
3429 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3430   let ParserMatchClass = exact1_asmoperand;
3431 }
3432
3433 def exact2_asmoperand : AsmOperandClass {
3434   let Name = "Exact2";
3435   let PredicateMethod = "isExactImm<2>";
3436   let RenderMethod = "addImmOperands";
3437 }
3438 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3439   let ParserMatchClass = exact2_asmoperand;
3440 }
3441
3442 def exact3_asmoperand : AsmOperandClass {
3443   let Name = "Exact3";
3444   let PredicateMethod = "isExactImm<3>";
3445   let RenderMethod = "addImmOperands";
3446 }
3447 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3448   let ParserMatchClass = exact3_asmoperand;
3449 }
3450
3451 def exact4_asmoperand : AsmOperandClass {
3452   let Name = "Exact4";
3453   let PredicateMethod = "isExactImm<4>";
3454   let RenderMethod = "addImmOperands";
3455 }
3456 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3457   let ParserMatchClass = exact4_asmoperand;
3458 }
3459
3460 def exact6_asmoperand : AsmOperandClass {
3461   let Name = "Exact6";
3462   let PredicateMethod = "isExactImm<6>";
3463   let RenderMethod = "addImmOperands";
3464 }
3465 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3466   let ParserMatchClass = exact6_asmoperand;
3467 }
3468
3469 def exact8_asmoperand : AsmOperandClass {
3470   let Name = "Exact8";
3471   let PredicateMethod = "isExactImm<8>";
3472   let RenderMethod = "addImmOperands";
3473 }
3474 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3475   let ParserMatchClass = exact8_asmoperand;
3476 }
3477
3478 def exact12_asmoperand : AsmOperandClass {
3479   let Name = "Exact12";
3480   let PredicateMethod = "isExactImm<12>";
3481   let RenderMethod = "addImmOperands";
3482 }
3483 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3484   let ParserMatchClass = exact12_asmoperand;
3485 }
3486
3487 def exact16_asmoperand : AsmOperandClass {
3488   let Name = "Exact16";
3489   let PredicateMethod = "isExactImm<16>";
3490   let RenderMethod = "addImmOperands";
3491 }
3492 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3493   let ParserMatchClass = exact16_asmoperand;
3494 }
3495
3496 def exact24_asmoperand : AsmOperandClass {
3497   let Name = "Exact24";
3498   let PredicateMethod = "isExactImm<24>";
3499   let RenderMethod = "addImmOperands";
3500 }
3501 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3502   let ParserMatchClass = exact24_asmoperand;
3503 }
3504
3505 def exact32_asmoperand : AsmOperandClass {
3506   let Name = "Exact32";
3507   let PredicateMethod = "isExactImm<32>";
3508   let RenderMethod = "addImmOperands";
3509 }
3510 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3511   let ParserMatchClass = exact32_asmoperand;
3512 }
3513
3514 def exact48_asmoperand : AsmOperandClass {
3515   let Name = "Exact48";
3516   let PredicateMethod = "isExactImm<48>";
3517   let RenderMethod = "addImmOperands";
3518 }
3519 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3520   let ParserMatchClass = exact48_asmoperand;
3521 }
3522
3523 def exact64_asmoperand : AsmOperandClass {
3524   let Name = "Exact64";
3525   let PredicateMethod = "isExactImm<64>";
3526   let RenderMethod = "addImmOperands";
3527 }
3528 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3529   let ParserMatchClass = exact64_asmoperand;
3530 }
3531
3532 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3533                            RegisterOperand VecList, Operand ImmTy,
3534                            string asmop> {
3535   let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3536       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3537     def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3538                      (outs VecList:$Rt, GPR64xsp:$wb),
3539                      (ins GPR64xsp:$Rn, ImmTy:$amt),
3540                      asmop # "\t$Rt, [$Rn], $amt",
3541                      [],
3542                      NoItinerary> {
3543       let Rm = 0b11111;
3544     }
3545
3546     def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3547                         (outs VecList:$Rt, GPR64xsp:$wb),
3548                         (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3549                         asmop # "\t$Rt, [$Rn], $Rm",
3550                         [],
3551                         NoItinerary>;
3552   }
3553 }
3554
3555 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3556     Operand ImmTy2, string asmop> {
3557   defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3558                               !cast<RegisterOperand>(List # "8B_operand"),
3559                               ImmTy, asmop>;
3560
3561   defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3562                               !cast<RegisterOperand>(List # "4H_operand"),
3563                               ImmTy, asmop>;
3564
3565   defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3566                               !cast<RegisterOperand>(List # "2S_operand"),
3567                               ImmTy, asmop>;
3568
3569   defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3570                                !cast<RegisterOperand>(List # "16B_operand"),
3571                                ImmTy2, asmop>;
3572
3573   defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3574                               !cast<RegisterOperand>(List # "8H_operand"),
3575                               ImmTy2, asmop>;
3576
3577   defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3578                               !cast<RegisterOperand>(List # "4S_operand"),
3579                               ImmTy2, asmop>;
3580
3581   defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3582                               !cast<RegisterOperand>(List # "2D_operand"),
3583                               ImmTy2, asmop>;
3584 }
3585
3586 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3587 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3588 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3589                                  "ld1">;
3590
3591 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3592
3593 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3594                              "ld3">;
3595
3596 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3597
3598 // Post-index load multiple 1-element structures from N consecutive registers
3599 // (N = 2,3,4)
3600 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3601                                "ld1">;
3602 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3603                                    uimm_exact16, "ld1">;
3604
3605 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3606                                "ld1">;
3607 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3608                                    uimm_exact24, "ld1">;
3609
3610 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3611                                 "ld1">;
3612 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3613                                    uimm_exact32, "ld1">;
3614
3615 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3616                             RegisterOperand VecList, Operand ImmTy,
3617                             string asmop> {
3618   let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3619       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3620     def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3621                      (outs GPR64xsp:$wb),
3622                      (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3623                      asmop # "\t$Rt, [$Rn], $amt",
3624                      [],
3625                      NoItinerary> {
3626       let Rm = 0b11111;
3627     }
3628
3629     def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3630                       (outs GPR64xsp:$wb),
3631                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3632                       asmop # "\t$Rt, [$Rn], $Rm",
3633                       [],
3634                       NoItinerary>;
3635   }
3636 }
3637
3638 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3639                            Operand ImmTy2, string asmop> {
3640   defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3641                  !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3642
3643   defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3644                               !cast<RegisterOperand>(List # "4H_operand"),
3645                               ImmTy, asmop>;
3646
3647   defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3648                               !cast<RegisterOperand>(List # "2S_operand"),
3649                               ImmTy, asmop>;
3650
3651   defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3652                                !cast<RegisterOperand>(List # "16B_operand"),
3653                                ImmTy2, asmop>;
3654
3655   defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3656                               !cast<RegisterOperand>(List # "8H_operand"),
3657                               ImmTy2, asmop>;
3658
3659   defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3660                               !cast<RegisterOperand>(List # "4S_operand"),
3661                               ImmTy2, asmop>;
3662
3663   defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3664                               !cast<RegisterOperand>(List # "2D_operand"),
3665                               ImmTy2, asmop>;
3666 }
3667
3668 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3669 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3670 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3671                                  "st1">;
3672
3673 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3674
3675 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3676                              "st3">;
3677
3678 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3679
3680 // Post-index load multiple 1-element structures from N consecutive registers
3681 // (N = 2,3,4)
3682 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3683                                "st1">;
3684 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3685                                    uimm_exact16, "st1">;
3686
3687 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3688                                "st1">;
3689 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3690                                    uimm_exact24, "st1">;
3691
3692 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3693                                "st1">;
3694 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3695                                    uimm_exact32, "st1">;
3696
3697 // End of post-index vector load/store multiple N-element structure
3698 // (class SIMD lselem-post)
3699
3700 // The followings are vector load/store single N-element structure
3701 // (class SIMD lsone).
3702 def neon_uimm0_bare : Operand<i64>,
3703                         ImmLeaf<i64, [{return Imm == 0;}]> {
3704   let ParserMatchClass = neon_uimm0_asmoperand;
3705   let PrintMethod = "printUImmBareOperand";
3706 }
3707
3708 def neon_uimm1_bare : Operand<i64>,
3709                         ImmLeaf<i64, [{return Imm < 2;}]> {
3710   let ParserMatchClass = neon_uimm1_asmoperand;
3711   let PrintMethod = "printUImmBareOperand";
3712 }
3713
3714 def neon_uimm2_bare : Operand<i64>,
3715                         ImmLeaf<i64, [{return Imm < 4;}]> {
3716   let ParserMatchClass = neon_uimm2_asmoperand;
3717   let PrintMethod = "printUImmBareOperand";
3718 }
3719
3720 def neon_uimm3_bare : Operand<i64>,
3721                         ImmLeaf<i64, [{return Imm < 8;}]> {
3722   let ParserMatchClass = uimm3_asmoperand;
3723   let PrintMethod = "printUImmBareOperand";
3724 }
3725
3726 def neon_uimm4_bare : Operand<i64>,
3727                         ImmLeaf<i64, [{return Imm < 16;}]> {
3728   let ParserMatchClass = uimm4_asmoperand;
3729   let PrintMethod = "printUImmBareOperand";
3730 }
3731
3732 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3733                     RegisterOperand VecList, string asmop>
3734     : NeonI_LdOne_Dup<q, r, opcode, size,
3735                       (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3736                       asmop # "\t$Rt, [$Rn]",
3737                       [],
3738                       NoItinerary> {
3739   let mayLoad = 1;
3740   let neverHasSideEffects = 1;
3741 }
3742
3743 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3744   def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3745                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3746
3747   def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3748                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3749
3750   def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3751                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3752
3753   def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3754                           !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3755
3756   def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3757                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3758
3759   def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3760                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3761
3762   def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3763                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3764
3765   def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3766                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3767 }
3768
3769 // Load single 1-element structure to all lanes of 1 register
3770 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3771
3772 // Load single N-element structure to all lanes of N consecutive
3773 // registers (N = 2,3,4)
3774 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3775 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3776 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3777
3778
3779 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3780                     Instruction INST>
3781     : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3782           (VTy (INST GPR64xsp:$Rn))>;
3783
3784 // Match all LD1R instructions
3785 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3786
3787 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3788
3789 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3790
3791 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3792
3793 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3794 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3795
3796 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3797 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3798
3799 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3800 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3801
3802 class LD1R_pattern_v1 <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3803                        Instruction INST>
3804   : Pat<(VTy (scalar_to_vector (DTy (LoadOp GPR64xsp:$Rn)))),
3805         (VTy (INST GPR64xsp:$Rn))>;
3806
3807 def : LD1R_pattern_v1<v1i64, i64, load, LD1R_1D>;
3808 def : LD1R_pattern_v1<v1f64, f64, load, LD1R_1D>;
3809
3810 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3811                                 RegisterClass RegList> {
3812   defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3813   defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3814   defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3815   defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3816 }
3817
3818 // Special vector list operand of 128-bit vectors with bare layout.
3819 // i.e. only show ".b", ".h", ".s", ".d"
3820 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3821 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3822 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3823 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3824
3825 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3826                      Operand ImmOp, string asmop>
3827     : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3828                          (outs VList:$Rt),
3829                          (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3830                          asmop # "\t$Rt[$lane], [$Rn]",
3831                          [],
3832                          NoItinerary> {
3833   let mayLoad = 1;
3834   let neverHasSideEffects = 1;
3835   let hasExtraDefRegAllocReq = 1;
3836   let Constraints = "$src = $Rt";
3837 }
3838
3839 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3840   def _B : NeonI_LDN_Lane<r, 0b00, op0,
3841                           !cast<RegisterOperand>(List # "B_operand"),
3842                           neon_uimm4_bare, asmop> {
3843     let Inst{12-10} = lane{2-0};
3844     let Inst{30} = lane{3};
3845   }
3846
3847   def _H : NeonI_LDN_Lane<r, 0b01, op0,
3848                           !cast<RegisterOperand>(List # "H_operand"),
3849                           neon_uimm3_bare, asmop> {
3850     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3851     let Inst{30} = lane{2};
3852   }
3853
3854   def _S : NeonI_LDN_Lane<r, 0b10, op0,
3855                           !cast<RegisterOperand>(List # "S_operand"),
3856                           neon_uimm2_bare, asmop> {
3857     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3858     let Inst{30} = lane{1};
3859   }
3860
3861   def _D : NeonI_LDN_Lane<r, 0b10, op0,
3862                           !cast<RegisterOperand>(List # "D_operand"),
3863                           neon_uimm1_bare, asmop> {
3864     let Inst{12-10} = 0b001;
3865     let Inst{30} = lane{0};
3866   }
3867 }
3868
3869 // Load single 1-element structure to one lane of 1 register.
3870 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3871
3872 // Load single N-element structure to one lane of N consecutive registers
3873 // (N = 2,3,4)
3874 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3875 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3876 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3877
3878 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3879                           Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3880                           Instruction INST> {
3881   def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3882                      (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3883             (VTy (EXTRACT_SUBREG
3884                      (INST GPR64xsp:$Rn,
3885                            (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3886                            ImmOp:$lane),
3887                      sub_64))>;
3888
3889   def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3890                       (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3891             (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3892 }
3893
3894 // Match all LD1LN instructions
3895 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3896                       extloadi8, LD1LN_B>;
3897
3898 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3899                       extloadi16, LD1LN_H>;
3900
3901 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3902                       load, LD1LN_S>;
3903 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3904                       load, LD1LN_S>;
3905
3906 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3907                       load, LD1LN_D>;
3908 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3909                       load, LD1LN_D>;
3910
3911 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3912                      Operand ImmOp, string asmop>
3913     : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3914                          (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3915                          asmop # "\t$Rt[$lane], [$Rn]",
3916                          [],
3917                          NoItinerary> {
3918   let mayStore = 1;
3919   let neverHasSideEffects = 1;
3920   let hasExtraDefRegAllocReq = 1;
3921 }
3922
3923 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3924   def _B : NeonI_STN_Lane<r, 0b00, op0,
3925                           !cast<RegisterOperand>(List # "B_operand"),
3926                           neon_uimm4_bare, asmop> {
3927     let Inst{12-10} = lane{2-0};
3928     let Inst{30} = lane{3};
3929   }
3930
3931   def _H : NeonI_STN_Lane<r, 0b01, op0,
3932                           !cast<RegisterOperand>(List # "H_operand"),
3933                           neon_uimm3_bare, asmop> {
3934     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3935     let Inst{30} = lane{2};
3936   }
3937
3938   def _S : NeonI_STN_Lane<r, 0b10, op0,
3939                           !cast<RegisterOperand>(List # "S_operand"),
3940                            neon_uimm2_bare, asmop> {
3941     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3942     let Inst{30} = lane{1};
3943   }
3944
3945   def _D : NeonI_STN_Lane<r, 0b10, op0,
3946                           !cast<RegisterOperand>(List # "D_operand"),
3947                           neon_uimm1_bare, asmop>{
3948     let Inst{12-10} = 0b001;
3949     let Inst{30} = lane{0};
3950   }
3951 }
3952
3953 // Store single 1-element structure from one lane of 1 register.
3954 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3955
3956 // Store single N-element structure from one lane of N consecutive registers
3957 // (N = 2,3,4)
3958 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3959 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3960 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3961
3962 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3963                           Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3964                           Instruction INST> {
3965   def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3966                      GPR64xsp:$Rn),
3967             (INST GPR64xsp:$Rn,
3968                   (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3969                   ImmOp:$lane)>;
3970
3971   def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3972                      GPR64xsp:$Rn),
3973             (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3974 }
3975
3976 // Match all ST1LN instructions
3977 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3978                       truncstorei8, ST1LN_B>;
3979
3980 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3981                       truncstorei16, ST1LN_H>;
3982
3983 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3984                       store, ST1LN_S>;
3985 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3986                       store, ST1LN_S>;
3987
3988 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3989                       store, ST1LN_D>;
3990 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3991                       store, ST1LN_D>;
3992
3993 // End of vector load/store single N-element structure (class SIMD lsone).
3994
3995
3996 // The following are post-index load/store single N-element instructions
3997 // (class SIMD lsone-post)
3998
3999 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
4000                             RegisterOperand VecList, Operand ImmTy,
4001                             string asmop> {
4002   let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
4003   DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4004     def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4005                       (outs VecList:$Rt, GPR64xsp:$wb),
4006                       (ins GPR64xsp:$Rn, ImmTy:$amt),
4007                       asmop # "\t$Rt, [$Rn], $amt",
4008                       [],
4009                       NoItinerary> {
4010                         let Rm = 0b11111;
4011                       }
4012
4013     def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4014                       (outs VecList:$Rt, GPR64xsp:$wb),
4015                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
4016                       asmop # "\t$Rt, [$Rn], $Rm",
4017                       [],
4018                       NoItinerary>;
4019   }
4020 }
4021
4022 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
4023                          Operand uimm_b, Operand uimm_h,
4024                          Operand uimm_s, Operand uimm_d> {
4025   defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
4026                               !cast<RegisterOperand>(List # "8B_operand"),
4027                               uimm_b, asmop>;
4028
4029   defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
4030                               !cast<RegisterOperand>(List # "4H_operand"),
4031                               uimm_h, asmop>;
4032
4033   defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
4034                               !cast<RegisterOperand>(List # "2S_operand"),
4035                               uimm_s, asmop>;
4036
4037   defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
4038                               !cast<RegisterOperand>(List # "1D_operand"),
4039                               uimm_d, asmop>;
4040
4041   defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
4042                                !cast<RegisterOperand>(List # "16B_operand"),
4043                                uimm_b, asmop>;
4044
4045   defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
4046                               !cast<RegisterOperand>(List # "8H_operand"),
4047                               uimm_h, asmop>;
4048
4049   defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
4050                               !cast<RegisterOperand>(List # "4S_operand"),
4051                               uimm_s, asmop>;
4052
4053   defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
4054                               !cast<RegisterOperand>(List # "2D_operand"),
4055                               uimm_d, asmop>;
4056 }
4057
4058 // Post-index load single 1-element structure to all lanes of 1 register
4059 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
4060                              uimm_exact2, uimm_exact4, uimm_exact8>;
4061
4062 // Post-index load single N-element structure to all lanes of N consecutive
4063 // registers (N = 2,3,4)
4064 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
4065                              uimm_exact4, uimm_exact8, uimm_exact16>;
4066 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
4067                              uimm_exact6, uimm_exact12, uimm_exact24>;
4068 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
4069                              uimm_exact8, uimm_exact16, uimm_exact32>;
4070
4071 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
4072     Constraints = "$Rn = $wb, $Rt = $src",
4073     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4074   class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4075                                 Operand ImmTy, Operand ImmOp, string asmop>
4076       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4077                                 (outs VList:$Rt, GPR64xsp:$wb),
4078                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
4079                                     VList:$src, ImmOp:$lane),
4080                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
4081                                 [],
4082                                 NoItinerary> {
4083     let Rm = 0b11111;
4084   }
4085
4086   class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4087                                  Operand ImmTy, Operand ImmOp, string asmop>
4088       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4089                                 (outs VList:$Rt, GPR64xsp:$wb),
4090                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
4091                                     VList:$src, ImmOp:$lane),
4092                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4093                                 [],
4094                                 NoItinerary>;
4095 }
4096
4097 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4098                            Operand uimm_b, Operand uimm_h,
4099                            Operand uimm_s, Operand uimm_d> {
4100   def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
4101                                !cast<RegisterOperand>(List # "B_operand"),
4102                                uimm_b, neon_uimm4_bare, asmop> {
4103     let Inst{12-10} = lane{2-0};
4104     let Inst{30} = lane{3};
4105   }
4106
4107   def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
4108                                    !cast<RegisterOperand>(List # "B_operand"),
4109                                    uimm_b, neon_uimm4_bare, asmop> {
4110     let Inst{12-10} = lane{2-0};
4111     let Inst{30} = lane{3};
4112   }
4113
4114   def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
4115                                !cast<RegisterOperand>(List # "H_operand"),
4116                                uimm_h, neon_uimm3_bare, asmop> {
4117     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4118     let Inst{30} = lane{2};
4119   }
4120
4121   def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
4122                                    !cast<RegisterOperand>(List # "H_operand"),
4123                                    uimm_h, neon_uimm3_bare, asmop> {
4124     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4125     let Inst{30} = lane{2};
4126   }
4127
4128   def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4129                                !cast<RegisterOperand>(List # "S_operand"),
4130                                uimm_s, neon_uimm2_bare, asmop> {
4131     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4132     let Inst{30} = lane{1};
4133   }
4134
4135   def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
4136                                    !cast<RegisterOperand>(List # "S_operand"),
4137                                    uimm_s, neon_uimm2_bare, asmop> {
4138     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4139     let Inst{30} = lane{1};
4140   }
4141
4142   def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4143                                !cast<RegisterOperand>(List # "D_operand"),
4144                                uimm_d, neon_uimm1_bare, asmop> {
4145     let Inst{12-10} = 0b001;
4146     let Inst{30} = lane{0};
4147   }
4148
4149   def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
4150                                    !cast<RegisterOperand>(List # "D_operand"),
4151                                    uimm_d, neon_uimm1_bare, asmop> {
4152     let Inst{12-10} = 0b001;
4153     let Inst{30} = lane{0};
4154   }
4155 }
4156
4157 // Post-index load single 1-element structure to one lane of 1 register.
4158 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
4159                                 uimm_exact2, uimm_exact4, uimm_exact8>;
4160
4161 // Post-index load single N-element structure to one lane of N consecutive
4162 // registers
4163 // (N = 2,3,4)
4164 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
4165                                 uimm_exact4, uimm_exact8, uimm_exact16>;
4166 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
4167                                 uimm_exact6, uimm_exact12, uimm_exact24>;
4168 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
4169                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4170
4171 let mayStore = 1, neverHasSideEffects = 1,
4172     hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
4173     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4174   class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4175                       Operand ImmTy, Operand ImmOp, string asmop>
4176       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4177                                 (outs GPR64xsp:$wb),
4178                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
4179                                     VList:$Rt, ImmOp:$lane),
4180                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
4181                                 [],
4182                                 NoItinerary> {
4183     let Rm = 0b11111;
4184   }
4185
4186   class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4187                        Operand ImmTy, Operand ImmOp, string asmop>
4188       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4189                                 (outs GPR64xsp:$wb),
4190                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4191                                     ImmOp:$lane),
4192                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4193                                 [],
4194                                 NoItinerary>;
4195 }
4196
4197 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4198                            Operand uimm_b, Operand uimm_h,
4199                            Operand uimm_s, Operand uimm_d> {
4200   def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4201                                !cast<RegisterOperand>(List # "B_operand"),
4202                                uimm_b, neon_uimm4_bare, asmop> {
4203     let Inst{12-10} = lane{2-0};
4204     let Inst{30} = lane{3};
4205   }
4206
4207   def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4208                                    !cast<RegisterOperand>(List # "B_operand"),
4209                                    uimm_b, neon_uimm4_bare, asmop> {
4210     let Inst{12-10} = lane{2-0};
4211     let Inst{30} = lane{3};
4212   }
4213
4214   def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4215                                !cast<RegisterOperand>(List # "H_operand"),
4216                                uimm_h, neon_uimm3_bare, asmop> {
4217     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4218     let Inst{30} = lane{2};
4219   }
4220
4221   def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4222                                    !cast<RegisterOperand>(List # "H_operand"),
4223                                    uimm_h, neon_uimm3_bare, asmop> {
4224     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4225     let Inst{30} = lane{2};
4226   }
4227
4228   def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4229                                !cast<RegisterOperand>(List # "S_operand"),
4230                                uimm_s, neon_uimm2_bare, asmop> {
4231     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4232     let Inst{30} = lane{1};
4233   }
4234
4235   def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4236                                    !cast<RegisterOperand>(List # "S_operand"),
4237                                    uimm_s, neon_uimm2_bare, asmop> {
4238     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4239     let Inst{30} = lane{1};
4240   }
4241
4242   def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4243                                !cast<RegisterOperand>(List # "D_operand"),
4244                                uimm_d, neon_uimm1_bare, asmop> {
4245     let Inst{12-10} = 0b001;
4246     let Inst{30} = lane{0};
4247   }
4248
4249   def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4250                                    !cast<RegisterOperand>(List # "D_operand"),
4251                                    uimm_d, neon_uimm1_bare, asmop> {
4252     let Inst{12-10} = 0b001;
4253     let Inst{30} = lane{0};
4254   }
4255 }
4256
4257 // Post-index store single 1-element structure from one lane of 1 register.
4258 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4259                                 uimm_exact2, uimm_exact4, uimm_exact8>;
4260
4261 // Post-index store single N-element structure from one lane of N consecutive
4262 // registers (N = 2,3,4)
4263 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4264                                 uimm_exact4, uimm_exact8, uimm_exact16>;
4265 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4266                                 uimm_exact6, uimm_exact12, uimm_exact24>;
4267 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4268                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4269
4270 // End of post-index load/store single N-element instructions
4271 // (class SIMD lsone-post)
4272
4273 // Neon Scalar instructions implementation
4274 // Scalar Three Same
4275
4276 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4277                              RegisterClass FPRC>
4278   : NeonI_Scalar3Same<u, size, opcode,
4279                       (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4280                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4281                       [],
4282                       NoItinerary>;
4283
4284 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4285   : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4286
4287 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4288                                       bit Commutable = 0> {
4289   let isCommutable = Commutable in {
4290     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4291     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4292   }
4293 }
4294
4295 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4296                                       string asmop, bit Commutable = 0> {
4297   let isCommutable = Commutable in {
4298     def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4299     def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4300   }
4301 }
4302
4303 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4304                                         string asmop, bit Commutable = 0> {
4305   let isCommutable = Commutable in {
4306     def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4307     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4308     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4309     def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4310   }
4311 }
4312
4313 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4314                                             Instruction INSTD> {
4315   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4316             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4317 }
4318
4319 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4320                                                Instruction INSTB,
4321                                                Instruction INSTH,
4322                                                Instruction INSTS,
4323                                                Instruction INSTD>
4324   : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4325   def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4326            (INSTB FPR8:$Rn, FPR8:$Rm)>;
4327   def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4328            (INSTH FPR16:$Rn, FPR16:$Rm)>;
4329   def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4330            (INSTS FPR32:$Rn, FPR32:$Rm)>;
4331 }
4332
4333 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4334                                              Instruction INSTH,
4335                                              Instruction INSTS> {
4336   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4337             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4338   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4339             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4340 }
4341
4342 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4343                                              ValueType SResTy, ValueType STy,
4344                                              Instruction INSTS, ValueType DResTy,
4345                                              ValueType DTy, Instruction INSTD> {
4346   def : Pat<(SResTy (opnode (STy FPR32:$Rn), (STy FPR32:$Rm))),
4347             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4348   def : Pat<(DResTy (opnode (DTy FPR64:$Rn), (DTy FPR64:$Rm))),
4349             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4350 }
4351
4352 class Neon_Scalar3Same_cmp_V1_D_size_patterns<CondCode CC,
4353                                               Instruction INSTD>
4354   : Pat<(v1i64 (Neon_cmp (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm), CC)),
4355         (INSTD FPR64:$Rn, FPR64:$Rm)>;
4356
4357 // Scalar Three Different
4358
4359 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4360                              RegisterClass FPRCD, RegisterClass FPRCS>
4361   : NeonI_Scalar3Diff<u, size, opcode,
4362                       (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4363                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4364                       [],
4365                       NoItinerary>;
4366
4367 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4368   def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4369   def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4370 }
4371
4372 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4373   let Constraints = "$Src = $Rd" in {
4374     def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4375                        (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4376                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4377                        [],
4378                        NoItinerary>;
4379     def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4380                        (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4381                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4382                        [],
4383                        NoItinerary>;
4384   }
4385 }
4386
4387 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4388                                              Instruction INSTH,
4389                                              Instruction INSTS> {
4390   def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4391             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4392   def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4393             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4394 }
4395
4396 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4397                                              Instruction INSTH,
4398                                              Instruction INSTS> {
4399   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4400             (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4401   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4402             (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4403 }
4404
4405 // Scalar Two Registers Miscellaneous
4406
4407 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4408                              RegisterClass FPRCD, RegisterClass FPRCS>
4409   : NeonI_Scalar2SameMisc<u, size, opcode,
4410                           (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4411                           !strconcat(asmop, "\t$Rd, $Rn"),
4412                           [],
4413                           NoItinerary>;
4414
4415 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4416                                          string asmop> {
4417   def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4418                                       FPR32>;
4419   def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4420                                       FPR64>;
4421 }
4422
4423 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4424   def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4425 }
4426
4427 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4428   : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4429   def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4430   def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4431   def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4432 }
4433
4434 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4435   : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4436
4437 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4438                                                  string asmop> {
4439   def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4440   def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4441   def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4442 }
4443
4444 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4445                                        string asmop, RegisterClass FPRC>
4446   : NeonI_Scalar2SameMisc<u, size, opcode,
4447                           (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4448                           !strconcat(asmop, "\t$Rd, $Rn"),
4449                           [],
4450                           NoItinerary>;
4451
4452 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4453                                                  string asmop> {
4454
4455   let Constraints = "$Src = $Rd" in {
4456     def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4457     def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4458     def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4459     def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4460   }
4461 }
4462
4463 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4464                                                   Instruction INSTD>
4465   : Pat<(f32 (opnode (f64 FPR64:$Rn))),
4466         (INSTD FPR64:$Rn)>;
4467
4468 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4469                                                       Instruction INSTS,
4470                                                       Instruction INSTD> {
4471   def : Pat<(v1i32 (opnode (f32 FPR32:$Rn))),
4472             (INSTS FPR32:$Rn)>;
4473   def : Pat<(v1i64 (opnode (f64 FPR64:$Rn))),
4474             (INSTD FPR64:$Rn)>;
4475 }
4476
4477 class Neon_Scalar2SameMisc_vcvt_D_size_patterns<SDPatternOperator opnode,
4478                                                 Instruction INSTD>
4479   : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4480             (INSTD FPR64:$Rn)>;
4481
4482 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator opnode,
4483                                                      Instruction INSTS,
4484                                                      Instruction INSTD> {
4485   def : Pat<(f32 (opnode (v1i32 FPR32:$Rn))),
4486             (INSTS FPR32:$Rn)>;
4487   def : Pat<(f64 (opnode (v1i64 FPR64:$Rn))),
4488             (INSTD FPR64:$Rn)>;
4489 }
4490
4491 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4492                                                  Instruction INSTS,
4493                                                  Instruction INSTD> {
4494   def : Pat<(f32 (opnode (f32 FPR32:$Rn))),
4495             (INSTS FPR32:$Rn)>;
4496   def : Pat<(f64 (opnode (f64 FPR64:$Rn))),
4497             (INSTD FPR64:$Rn)>;
4498 }
4499
4500 class Neon_Scalar2SameMisc_V1_D_size_patterns<SDPatternOperator opnode,
4501                                               Instruction INSTD>
4502   : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4503         (INSTD FPR64:$Rn)>;
4504
4505 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4506   : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4507                           (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4508                           !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4509                           [],
4510                           NoItinerary>;
4511
4512 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4513                                               string asmop> {
4514   def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4515                            (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4516                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4517                            [],
4518                            NoItinerary>;
4519   def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4520                            (outs FPR64:$Rd), (ins FPR64:$Rn, fpz32:$FPImm),
4521                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4522                            [],
4523                            NoItinerary>;
4524 }
4525
4526 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4527                                                 Instruction INSTD>
4528   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4529                        (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4530         (INSTD FPR64:$Rn, 0)>;
4531
4532 class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
4533                                                    Instruction INSTD>
4534   : Pat<(v1i64 (Neon_cmpz (v1i64 FPR64:$Rn),
4535                           (i32 neon_uimm0:$Imm), CC)),
4536         (INSTD FPR64:$Rn, neon_uimm0:$Imm)>;
4537
4538 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4539                                                       CondCode CC,
4540                                                       Instruction INSTS,
4541                                                       Instruction INSTD> {
4542   def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 fpz32:$FPImm))),
4543             (INSTS FPR32:$Rn, fpz32:$FPImm)>;
4544   def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f32 fpz32:$FPImm))),
4545             (INSTD FPR64:$Rn, fpz32:$FPImm)>;
4546   def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpz32:$FPImm), CC)),
4547             (INSTD FPR64:$Rn, fpz32:$FPImm)>;
4548 }
4549
4550 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4551                                                 Instruction INSTD> {
4552   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4553             (INSTD FPR64:$Rn)>;
4554 }
4555
4556 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4557                                                    Instruction INSTB,
4558                                                    Instruction INSTH,
4559                                                    Instruction INSTS,
4560                                                    Instruction INSTD>
4561   : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4562   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4563             (INSTB FPR8:$Rn)>;
4564   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4565             (INSTH FPR16:$Rn)>;
4566   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4567             (INSTS FPR32:$Rn)>;
4568 }
4569
4570 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4571                                                        SDPatternOperator opnode,
4572                                                        Instruction INSTH,
4573                                                        Instruction INSTS,
4574                                                        Instruction INSTD> {
4575   def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4576             (INSTH FPR16:$Rn)>;
4577   def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4578             (INSTS FPR32:$Rn)>;
4579   def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4580             (INSTD FPR64:$Rn)>;
4581
4582 }
4583
4584 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4585                                                        SDPatternOperator opnode,
4586                                                        Instruction INSTB,
4587                                                        Instruction INSTH,
4588                                                        Instruction INSTS,
4589                                                        Instruction INSTD> {
4590   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4591             (INSTB FPR8:$Src, FPR8:$Rn)>;
4592   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4593             (INSTH FPR16:$Src, FPR16:$Rn)>;
4594   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4595             (INSTS FPR32:$Src, FPR32:$Rn)>;
4596   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4597             (INSTD FPR64:$Src, FPR64:$Rn)>;
4598 }
4599
4600 // Scalar Shift By Immediate
4601
4602 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4603                                 RegisterClass FPRC, Operand ImmTy>
4604   : NeonI_ScalarShiftImm<u, opcode,
4605                          (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4606                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4607                          [], NoItinerary>;
4608
4609 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4610                                             string asmop> {
4611   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4612     bits<6> Imm;
4613     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4614     let Inst{21-16} = Imm;
4615   }
4616 }
4617
4618 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4619                                                string asmop>
4620   : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4621   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4622     bits<3> Imm;
4623     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4624     let Inst{18-16} = Imm;
4625   }
4626   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4627     bits<4> Imm;
4628     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4629     let Inst{19-16} = Imm;
4630   }
4631   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4632     bits<5> Imm;
4633     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4634     let Inst{20-16} = Imm;
4635   }
4636 }
4637
4638 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4639                                             string asmop> {
4640   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4641     bits<6> Imm;
4642     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4643     let Inst{21-16} = Imm;
4644   }
4645 }
4646
4647 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4648                                               string asmop>
4649   : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4650   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4651     bits<3> Imm;
4652     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4653     let Inst{18-16} = Imm;
4654   }
4655   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4656     bits<4> Imm;
4657     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4658     let Inst{19-16} = Imm;
4659   }
4660   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4661     bits<5> Imm;
4662     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4663     let Inst{20-16} = Imm;
4664   }
4665 }
4666
4667 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4668   : NeonI_ScalarShiftImm<u, opcode,
4669                          (outs FPR64:$Rd),
4670                          (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4671                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4672                          [], NoItinerary> {
4673     bits<6> Imm;
4674     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4675     let Inst{21-16} = Imm;
4676     let Constraints = "$Src = $Rd";
4677 }
4678
4679 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4680   : NeonI_ScalarShiftImm<u, opcode,
4681                          (outs FPR64:$Rd),
4682                          (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4683                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4684                          [], NoItinerary> {
4685     bits<6> Imm;
4686     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4687     let Inst{21-16} = Imm;
4688     let Constraints = "$Src = $Rd";
4689 }
4690
4691 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4692                                        RegisterClass FPRCD, RegisterClass FPRCS,
4693                                        Operand ImmTy>
4694   : NeonI_ScalarShiftImm<u, opcode,
4695                          (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4696                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4697                          [], NoItinerary>;
4698
4699 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4700                                                 string asmop> {
4701   def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4702                                              shr_imm8> {
4703     bits<3> Imm;
4704     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4705     let Inst{18-16} = Imm;
4706   }
4707   def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4708                                              shr_imm16> {
4709     bits<4> Imm;
4710     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4711     let Inst{19-16} = Imm;
4712   }
4713   def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4714                                              shr_imm32> {
4715     bits<5> Imm;
4716     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4717     let Inst{20-16} = Imm;
4718   }
4719 }
4720
4721 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4722   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4723     bits<5> Imm;
4724     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4725     let Inst{20-16} = Imm;
4726   }
4727   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4728     bits<6> Imm;
4729     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4730     let Inst{21-16} = Imm;
4731   }
4732 }
4733
4734 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4735                                                Instruction INSTD> {
4736   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4737                 (INSTD FPR64:$Rn, imm:$Imm)>;
4738 }
4739
4740 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4741                                                Instruction INSTD> {
4742   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4743                 (INSTD FPR64:$Rn, imm:$Imm)>;
4744 }
4745
4746 class Neon_ScalarShiftLImm_V1_D_size_patterns<SDPatternOperator opnode,
4747                                              Instruction INSTD>
4748   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4749             (v1i64 (Neon_vdup (i32 shl_imm64:$Imm))))),
4750         (INSTD FPR64:$Rn, imm:$Imm)>;
4751
4752 class Neon_ScalarShiftRImm_V1_D_size_patterns<SDPatternOperator opnode,
4753                                              Instruction INSTD>
4754   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4755             (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4756         (INSTD FPR64:$Rn, imm:$Imm)>;
4757
4758 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4759                                                    Instruction INSTB,
4760                                                    Instruction INSTH,
4761                                                    Instruction INSTS,
4762                                                    Instruction INSTD>
4763   : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4764   def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4765                 (INSTB FPR8:$Rn, imm:$Imm)>;
4766   def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4767                 (INSTH FPR16:$Rn, imm:$Imm)>;
4768   def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4769                 (INSTS FPR32:$Rn, imm:$Imm)>;
4770 }
4771
4772 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4773                                                 Instruction INSTD>
4774   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4775             (i32 shl_imm64:$Imm))),
4776         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4777
4778 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4779                                                 Instruction INSTD>
4780   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4781             (i32 shr_imm64:$Imm))),
4782         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4783
4784 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4785                                                        SDPatternOperator opnode,
4786                                                        Instruction INSTH,
4787                                                        Instruction INSTS,
4788                                                        Instruction INSTD> {
4789   def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4790                 (INSTH FPR16:$Rn, imm:$Imm)>;
4791   def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4792                 (INSTS FPR32:$Rn, imm:$Imm)>;
4793   def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4794                 (INSTD FPR64:$Rn, imm:$Imm)>;
4795 }
4796
4797 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator opnode,
4798                                                       Instruction INSTS,
4799                                                       Instruction INSTD> {
4800   def ssi : Pat<(f32 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4801                 (INSTS FPR32:$Rn, imm:$Imm)>;
4802   def ddi : Pat<(f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4803                 (INSTD FPR64:$Rn, imm:$Imm)>;
4804 }
4805
4806 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
4807                                                       Instruction INSTS,
4808                                                       Instruction INSTD> {
4809   def ssi : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4810                 (INSTS FPR32:$Rn, imm:$Imm)>;
4811   def ddi : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4812                 (INSTD FPR64:$Rn, imm:$Imm)>;
4813 }
4814
4815 // Scalar Signed Shift Right (Immediate)
4816 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4817 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4818 // Pattern to match llvm.arm.* intrinsic.
4819 def : Neon_ScalarShiftRImm_V1_D_size_patterns<sra, SSHRddi>;
4820
4821 // Scalar Unsigned Shift Right (Immediate)
4822 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4823 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4824 // Pattern to match llvm.arm.* intrinsic.
4825 def : Neon_ScalarShiftRImm_V1_D_size_patterns<srl, USHRddi>;
4826
4827 // Scalar Signed Rounding Shift Right (Immediate)
4828 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4829 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4830
4831 // Scalar Unigned Rounding Shift Right (Immediate)
4832 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4833 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4834
4835 // Scalar Signed Shift Right and Accumulate (Immediate)
4836 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4837 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4838           <int_aarch64_neon_vsrads_n, SSRA>;
4839
4840 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4841 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4842 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4843           <int_aarch64_neon_vsradu_n, USRA>;
4844
4845 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4846 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4847 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4848           <int_aarch64_neon_vrsrads_n, SRSRA>;
4849
4850 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4851 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4852 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4853           <int_aarch64_neon_vrsradu_n, URSRA>;
4854
4855 // Scalar Shift Left (Immediate)
4856 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4857 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4858 // Pattern to match llvm.arm.* intrinsic.
4859 def : Neon_ScalarShiftLImm_V1_D_size_patterns<shl, SHLddi>;
4860
4861 // Signed Saturating Shift Left (Immediate)
4862 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4863 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4864                                                SQSHLbbi, SQSHLhhi,
4865                                                SQSHLssi, SQSHLddi>;
4866 // Pattern to match llvm.arm.* intrinsic.
4867 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4868
4869 // Unsigned Saturating Shift Left (Immediate)
4870 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4871 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4872                                                UQSHLbbi, UQSHLhhi,
4873                                                UQSHLssi, UQSHLddi>;
4874 // Pattern to match llvm.arm.* intrinsic.
4875 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4876
4877 // Signed Saturating Shift Left Unsigned (Immediate)
4878 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4879 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4880                                                SQSHLUbbi, SQSHLUhhi,
4881                                                SQSHLUssi, SQSHLUddi>;
4882
4883 // Shift Right And Insert (Immediate)
4884 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4885 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4886           <int_aarch64_neon_vsri, SRI>;
4887
4888 // Shift Left And Insert (Immediate)
4889 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4890 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4891           <int_aarch64_neon_vsli, SLI>;
4892
4893 // Signed Saturating Shift Right Narrow (Immediate)
4894 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4895 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4896                                                     SQSHRNbhi, SQSHRNhsi,
4897                                                     SQSHRNsdi>;
4898
4899 // Unsigned Saturating Shift Right Narrow (Immediate)
4900 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4901 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4902                                                     UQSHRNbhi, UQSHRNhsi,
4903                                                     UQSHRNsdi>;
4904
4905 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4906 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4907 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4908                                                     SQRSHRNbhi, SQRSHRNhsi,
4909                                                     SQRSHRNsdi>;
4910
4911 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4912 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4913 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4914                                                     UQRSHRNbhi, UQRSHRNhsi,
4915                                                     UQRSHRNsdi>;
4916
4917 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4918 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4919 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4920                                                     SQSHRUNbhi, SQSHRUNhsi,
4921                                                     SQSHRUNsdi>;
4922
4923 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4924 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4925 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4926                                                     SQRSHRUNbhi, SQRSHRUNhsi,
4927                                                     SQRSHRUNsdi>;
4928
4929 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4930 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4931 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxs2fp_n,
4932                                                   SCVTF_Nssi, SCVTF_Nddi>;
4933
4934 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4935 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4936 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxu2fp_n,
4937                                                   UCVTF_Nssi, UCVTF_Nddi>;
4938
4939 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4940 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4941 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxs_n,
4942                                                   FCVTZS_Nssi, FCVTZS_Nddi>;
4943
4944 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4945 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4946 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxu_n,
4947                                                   FCVTZU_Nssi, FCVTZU_Nddi>;
4948
4949 // Patterns For Convert Instructions Between v1f64 and v1i64
4950 class Neon_ScalarShiftImm_cvtf_v1f64_pattern<SDPatternOperator opnode,
4951                                              Instruction INST>
4952     : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4953           (INST FPR64:$Rn, imm:$Imm)>;
4954
4955 class Neon_ScalarShiftImm_fcvt_v1f64_pattern<SDPatternOperator opnode,
4956                                              Instruction INST>
4957     : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4958           (INST FPR64:$Rn, imm:$Imm)>;
4959
4960 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxs2fp,
4961                                              SCVTF_Nddi>;
4962
4963 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxu2fp,
4964                                              UCVTF_Nddi>;
4965
4966 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxs,
4967                                              FCVTZS_Nddi>;
4968
4969 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxu,
4970                                              FCVTZU_Nddi>;
4971
4972 // Scalar Integer Add
4973 let isCommutable = 1 in {
4974 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4975 }
4976
4977 // Scalar Integer Sub
4978 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4979
4980 // Pattern for Scalar Integer Add and Sub with D register only
4981 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4982 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4983
4984 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4985 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4986 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4987 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4988 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4989
4990 // Scalar Integer Saturating Add (Signed, Unsigned)
4991 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4992 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4993
4994 // Scalar Integer Saturating Sub (Signed, Unsigned)
4995 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4996 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4997
4998
4999 // Patterns to match llvm.aarch64.* intrinsic for
5000 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
5001 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
5002                                            SQADDhhh, SQADDsss, SQADDddd>;
5003 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
5004                                            UQADDhhh, UQADDsss, UQADDddd>;
5005 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
5006                                            SQSUBhhh, SQSUBsss, SQSUBddd>;
5007 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
5008                                            UQSUBhhh, UQSUBsss, UQSUBddd>;
5009
5010 // Scalar Integer Saturating Doubling Multiply Half High
5011 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
5012
5013 // Scalar Integer Saturating Rounding Doubling Multiply Half High
5014 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
5015
5016 // Patterns to match llvm.arm.* intrinsic for
5017 // Scalar Integer Saturating Doubling Multiply Half High and
5018 // Scalar Integer Saturating Rounding Doubling Multiply Half High
5019 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
5020                                                                SQDMULHsss>;
5021 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
5022                                                                 SQRDMULHsss>;
5023
5024 // Scalar Floating-point Multiply Extended
5025 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
5026
5027 // Scalar Floating-point Reciprocal Step
5028 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
5029 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrecps, f32, f32,
5030                                          FRECPSsss, f64, f64, FRECPSddd>;
5031 def : Pat<(v1f64 (int_arm_neon_vrecps (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5032           (FRECPSddd FPR64:$Rn, FPR64:$Rm)>;
5033
5034 // Scalar Floating-point Reciprocal Square Root Step
5035 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
5036 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrsqrts, f32, f32,
5037                                          FRSQRTSsss, f64, f64, FRSQRTSddd>;
5038 def : Pat<(v1f64 (int_arm_neon_vrsqrts (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5039           (FRSQRTSddd FPR64:$Rn, FPR64:$Rm)>;
5040 def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>;
5041
5042 // Patterns to match llvm.aarch64.* intrinsic for
5043 // Scalar Floating-point Multiply Extended,
5044 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
5045                                                   Instruction INSTS,
5046                                                   Instruction INSTD> {
5047   def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
5048             (INSTS FPR32:$Rn, FPR32:$Rm)>;
5049   def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
5050             (INSTD FPR64:$Rn, FPR64:$Rm)>;
5051 }
5052
5053 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
5054                                               FMULXsss, FMULXddd>;
5055 def : Pat<(v1f64 (int_aarch64_neon_vmulx (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5056           (FMULXddd FPR64:$Rn, FPR64:$Rm)>;
5057
5058 // Scalar Integer Shift Left (Signed, Unsigned)
5059 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
5060 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
5061
5062 // Patterns to match llvm.arm.* intrinsic for
5063 // Scalar Integer Shift Left (Signed, Unsigned)
5064 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
5065 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
5066
5067 // Patterns to match llvm.aarch64.* intrinsic for
5068 // Scalar Integer Shift Left (Signed, Unsigned)
5069 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
5070 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
5071
5072 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
5073 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
5074 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
5075
5076 // Patterns to match llvm.aarch64.* intrinsic for
5077 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
5078 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
5079                                            SQSHLhhh, SQSHLsss, SQSHLddd>;
5080 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
5081                                            UQSHLhhh, UQSHLsss, UQSHLddd>;
5082
5083 // Patterns to match llvm.arm.* intrinsic for
5084 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
5085 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
5086 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
5087
5088 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5089 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
5090 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
5091
5092 // Patterns to match llvm.aarch64.* intrinsic for
5093 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5094 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
5095 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
5096
5097 // Patterns to match llvm.arm.* intrinsic for
5098 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5099 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
5100 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
5101
5102 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5103 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
5104 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
5105
5106 // Patterns to match llvm.aarch64.* intrinsic for
5107 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5108 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
5109                                            SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
5110 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
5111                                            UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
5112
5113 // Patterns to match llvm.arm.* intrinsic for
5114 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5115 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
5116 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
5117
5118 // Signed Saturating Doubling Multiply-Add Long
5119 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
5120 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
5121                                             SQDMLALshh, SQDMLALdss>;
5122
5123 // Signed Saturating Doubling Multiply-Subtract Long
5124 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
5125 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
5126                                             SQDMLSLshh, SQDMLSLdss>;
5127
5128 // Signed Saturating Doubling Multiply Long
5129 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
5130 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
5131                                          SQDMULLshh, SQDMULLdss>;
5132
5133 // Scalar Signed Integer Convert To Floating-point
5134 defm SCVTF  : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
5135 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fps,
5136                                                  SCVTFss, SCVTFdd>;
5137
5138 // Scalar Unsigned Integer Convert To Floating-point
5139 defm UCVTF  : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
5140 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fpu,
5141                                                  UCVTFss, UCVTFdd>;
5142
5143 // Scalar Floating-point Converts
5144 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
5145 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
5146                                                   FCVTXN>;
5147
5148 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
5149 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
5150                                                   FCVTNSss, FCVTNSdd>;
5151 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtns, FCVTNSdd>;
5152
5153 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
5154 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
5155                                                   FCVTNUss, FCVTNUdd>;
5156 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtnu, FCVTNUdd>;
5157
5158 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
5159 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
5160                                                   FCVTMSss, FCVTMSdd>;
5161 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtms, FCVTMSdd>;
5162
5163 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
5164 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
5165                                                   FCVTMUss, FCVTMUdd>;
5166 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtmu, FCVTMUdd>;
5167
5168 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
5169 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
5170                                                   FCVTASss, FCVTASdd>;
5171 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtas, FCVTASdd>;
5172
5173 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
5174 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
5175                                                   FCVTAUss, FCVTAUdd>;
5176 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtau, FCVTAUdd>;
5177
5178 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
5179 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
5180                                                   FCVTPSss, FCVTPSdd>;
5181 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtps, FCVTPSdd>;
5182
5183 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
5184 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
5185                                                   FCVTPUss, FCVTPUdd>;
5186 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtpu, FCVTPUdd>;
5187
5188 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
5189 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
5190                                                   FCVTZSss, FCVTZSdd>;
5191 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzs,
5192                                                 FCVTZSdd>;
5193
5194 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
5195 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
5196                                                   FCVTZUss, FCVTZUdd>;
5197 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzu,
5198                                                 FCVTZUdd>;
5199
5200 // Patterns For Convert Instructions Between v1f64 and v1i64
5201 class Neon_Scalar2SameMisc_cvtf_v1f64_pattern<SDPatternOperator opnode,
5202                                               Instruction INST>
5203     : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5204
5205 class Neon_Scalar2SameMisc_fcvt_v1f64_pattern<SDPatternOperator opnode,
5206                                               Instruction INST>
5207     : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5208
5209 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<sint_to_fp, SCVTFdd>;
5210 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<uint_to_fp, UCVTFdd>;
5211
5212 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_sint, FCVTZSdd>;
5213 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_uint, FCVTZUdd>;
5214
5215 // Scalar Floating-point Reciprocal Estimate
5216 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5217 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpe,
5218                                              FRECPEss, FRECPEdd>;
5219 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrecpe,
5220                                               FRECPEdd>;
5221
5222 // Scalar Floating-point Reciprocal Exponent
5223 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5224 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5225                                              FRECPXss, FRECPXdd>;
5226
5227 // Scalar Floating-point Reciprocal Square Root Estimate
5228 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5229 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrsqrte,
5230                                                  FRSQRTEss, FRSQRTEdd>;
5231 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrsqrte,
5232                                               FRSQRTEdd>;
5233
5234 // Scalar Floating-point Round
5235 class Neon_ScalarFloatRound_pattern<SDPatternOperator opnode, Instruction INST>
5236     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5237
5238 def : Neon_ScalarFloatRound_pattern<fceil, FRINTPdd>;
5239 def : Neon_ScalarFloatRound_pattern<ffloor, FRINTMdd>;
5240 def : Neon_ScalarFloatRound_pattern<ftrunc, FRINTZdd>;
5241 def : Neon_ScalarFloatRound_pattern<frint, FRINTXdd>;
5242 def : Neon_ScalarFloatRound_pattern<fnearbyint, FRINTIdd>;
5243 def : Neon_ScalarFloatRound_pattern<frnd, FRINTAdd>;
5244 def : Neon_ScalarFloatRound_pattern<int_aarch64_neon_frintn, FRINTNdd>;
5245
5246 // Scalar Integer Compare
5247
5248 // Scalar Compare Bitwise Equal
5249 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5250 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5251
5252 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5253                                               Instruction INSTD,
5254                                               CondCode CC>
5255   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5256         (INSTD FPR64:$Rn, FPR64:$Rm)>;
5257
5258 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5259
5260 // Scalar Compare Signed Greather Than Or Equal
5261 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5262 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5263 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGEddd, SETGE>;
5264
5265 // Scalar Compare Unsigned Higher Or Same
5266 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5267 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5268 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHSddd, SETUGE>;
5269
5270 // Scalar Compare Unsigned Higher
5271 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5272 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5273 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHIddd, SETUGT>;
5274
5275 // Scalar Compare Signed Greater Than
5276 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5277 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5278 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGTddd, SETGT>;
5279
5280 // Scalar Compare Bitwise Test Bits
5281 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5282 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5283 defm : Neon_Scalar3Same_D_size_patterns<Neon_tst, CMTSTddd>;
5284
5285 // Scalar Compare Bitwise Equal To Zero
5286 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5287 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5288                                                 CMEQddi>;
5289 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETEQ, CMEQddi>;
5290
5291 // Scalar Compare Signed Greather Than Or Equal To Zero
5292 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5293 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5294                                                 CMGEddi>;
5295 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGE, CMGEddi>;
5296
5297 // Scalar Compare Signed Greater Than Zero
5298 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5299 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5300                                                 CMGTddi>;
5301 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGT, CMGTddi>;
5302
5303 // Scalar Compare Signed Less Than Or Equal To Zero
5304 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5305 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5306                                                 CMLEddi>;
5307 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLE, CMLEddi>;
5308
5309 // Scalar Compare Less Than Zero
5310 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5311 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5312                                                 CMLTddi>;
5313 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
5314
5315 // Scalar Floating-point Compare
5316
5317 // Scalar Floating-point Compare Mask Equal
5318 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5319 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fceq, v1i32, f32,
5320                                          FCMEQsss, v1i64, f64, FCMEQddd>;
5321 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
5322
5323 // Scalar Floating-point Compare Mask Equal To Zero
5324 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5325 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fceq, SETEQ,
5326                                                   FCMEQZssi, FCMEQZddi>;
5327
5328 // Scalar Floating-point Compare Mask Greater Than Or Equal
5329 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5330 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcge, v1i32, f32,
5331                                          FCMGEsss, v1i64, f64, FCMGEddd>;
5332 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
5333
5334 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5335 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5336 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcge, SETGE,
5337                                                   FCMGEZssi, FCMGEZddi>;
5338
5339 // Scalar Floating-point Compare Mask Greather Than
5340 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5341 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcgt, v1i32, f32,
5342                                          FCMGTsss, v1i64, f64, FCMGTddd>;
5343 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
5344
5345 // Scalar Floating-point Compare Mask Greather Than Zero
5346 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5347 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcgt, SETGT,
5348                                                   FCMGTZssi, FCMGTZddi>;
5349
5350 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5351 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5352 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fclez, SETLE,
5353                                                   FCMLEZssi, FCMLEZddi>;
5354
5355 // Scalar Floating-point Compare Mask Less Than Zero
5356 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5357 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcltz, SETLT,
5358                                                   FCMLTZssi, FCMLTZddi>;
5359
5360 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5361 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5362 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcage, v1i32, f32,
5363                                          FACGEsss, v1i64, f64, FACGEddd>;
5364 def : Pat<(v1i64 (int_aarch64_neon_vcage (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5365           (FACGEddd FPR64:$Rn, FPR64:$Rm)>;
5366
5367 // Scalar Floating-point Absolute Compare Mask Greater Than
5368 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5369 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcagt, v1i32, f32,
5370                                          FACGTsss, v1i64, f64, FACGTddd>;
5371 def : Pat<(v1i64 (int_aarch64_neon_vcagt (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5372           (FACGTddd FPR64:$Rn, FPR64:$Rm)>;
5373
5374 // Scalar Floating-point Absolute Difference
5375 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5376 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vabd, f32, f32,
5377                                          FABDsss, f64, f64, FABDddd>;
5378
5379 // Scalar Absolute Value
5380 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5381 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5382
5383 // Scalar Signed Saturating Absolute Value
5384 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5385 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5386                                                SQABSbb, SQABShh, SQABSss, SQABSdd>;
5387
5388 // Scalar Negate
5389 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5390 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5391
5392 // Scalar Signed Saturating Negate
5393 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5394 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5395                                                SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5396
5397 // Scalar Signed Saturating Accumulated of Unsigned Value
5398 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5399 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5400                                                      SUQADDbb, SUQADDhh,
5401                                                      SUQADDss, SUQADDdd>;
5402
5403 // Scalar Unsigned Saturating Accumulated of Signed Value
5404 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5405 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5406                                                      USQADDbb, USQADDhh,
5407                                                      USQADDss, USQADDdd>;
5408
5409 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5410                                           (v1i64 FPR64:$Rn))),
5411           (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5412
5413 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5414                                           (v1i64 FPR64:$Rn))),
5415           (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5416
5417 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5418           (ABSdd FPR64:$Rn)>;
5419
5420 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5421           (SQABSdd FPR64:$Rn)>;
5422
5423 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5424           (SQNEGdd FPR64:$Rn)>;
5425
5426 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5427                       (v1i64 FPR64:$Rn))),
5428           (NEGdd FPR64:$Rn)>;
5429
5430 // Scalar Signed Saturating Extract Unsigned Narrow
5431 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5432 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5433                                                      SQXTUNbh, SQXTUNhs,
5434                                                      SQXTUNsd>;
5435
5436 // Scalar Signed Saturating Extract Narrow
5437 defm SQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5438 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5439                                                      SQXTNbh, SQXTNhs,
5440                                                      SQXTNsd>;
5441
5442 // Scalar Unsigned Saturating Extract Narrow
5443 defm UQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5444 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5445                                                      UQXTNbh, UQXTNhs,
5446                                                      UQXTNsd>;
5447
5448 // Scalar Reduce Pairwise
5449
5450 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5451                                      string asmop, bit Commutable = 0> {
5452   let isCommutable = Commutable in {
5453     def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5454                                 (outs FPR64:$Rd), (ins VPR128:$Rn),
5455                                 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5456                                 [],
5457                                 NoItinerary>;
5458   }
5459 }
5460
5461 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5462                                      string asmop, bit Commutable = 0>
5463   : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5464   let isCommutable = Commutable in {
5465     def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5466                                 (outs FPR32:$Rd), (ins VPR64:$Rn),
5467                                 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5468                                 [],
5469                                 NoItinerary>;
5470   }
5471 }
5472
5473 // Scalar Reduce Addition Pairwise (Integer) with
5474 // Pattern to match llvm.arm.* intrinsic
5475 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5476
5477 // Pattern to match llvm.aarch64.* intrinsic for
5478 // Scalar Reduce Addition Pairwise (Integer)
5479 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5480           (ADDPvv_D_2D VPR128:$Rn)>;
5481 def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
5482           (ADDPvv_D_2D VPR128:$Rn)>;
5483
5484 // Scalar Reduce Addition Pairwise (Floating Point)
5485 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5486
5487 // Scalar Reduce Maximum Pairwise (Floating Point)
5488 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5489
5490 // Scalar Reduce Minimum Pairwise (Floating Point)
5491 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5492
5493 // Scalar Reduce maxNum Pairwise (Floating Point)
5494 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5495
5496 // Scalar Reduce minNum Pairwise (Floating Point)
5497 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5498
5499 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnode,
5500                                             Instruction INSTS,
5501                                             Instruction INSTD> {
5502   def : Pat<(f32 (opnode (v2f32 VPR64:$Rn))),
5503             (INSTS VPR64:$Rn)>;
5504   def : Pat<(f64 (opnode (v2f64 VPR128:$Rn))),
5505             (INSTD VPR128:$Rn)>;
5506 }
5507
5508 // Patterns to match llvm.aarch64.* intrinsic for
5509 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5510 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5511                                         FADDPvv_S_2S, FADDPvv_D_2D>;
5512
5513 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5514                                         FMAXPvv_S_2S, FMAXPvv_D_2D>;
5515
5516 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5517                                         FMINPvv_S_2S, FMINPvv_D_2D>;
5518
5519 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5520                                         FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5521
5522 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5523                                         FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5524
5525 def : Pat<(f32 (int_aarch64_neon_vpfadd (v4f32 VPR128:$Rn))),
5526           (FADDPvv_S_2S (v2f32
5527                (EXTRACT_SUBREG
5528                    (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
5529                    sub_64)))>;
5530
5531 // Scalar by element Arithmetic
5532
5533 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5534                                     string rmlane, bit u, bit szhi, bit szlo,
5535                                     RegisterClass ResFPR, RegisterClass OpFPR,
5536                                     RegisterOperand OpVPR, Operand OpImm>
5537   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5538                              (outs ResFPR:$Rd),
5539                              (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5540                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5541                              [],
5542                              NoItinerary> {
5543   bits<3> Imm;
5544   bits<5> MRm;
5545 }
5546
5547 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5548                                                     string rmlane,
5549                                                     bit u, bit szhi, bit szlo,
5550                                                     RegisterClass ResFPR,
5551                                                     RegisterClass OpFPR,
5552                                                     RegisterOperand OpVPR,
5553                                                     Operand OpImm>
5554   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5555                              (outs ResFPR:$Rd),
5556                              (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5557                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5558                              [],
5559                              NoItinerary> {
5560   let Constraints = "$src = $Rd";
5561   bits<3> Imm;
5562   bits<5> MRm;
5563 }
5564
5565 // Scalar Floating Point  multiply (scalar, by element)
5566 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5567   0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5568   let Inst{11} = Imm{1}; // h
5569   let Inst{21} = Imm{0}; // l
5570   let Inst{20-16} = MRm;
5571 }
5572 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5573   0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5574   let Inst{11} = Imm{0}; // h
5575   let Inst{21} = 0b0;    // l
5576   let Inst{20-16} = MRm;
5577 }
5578
5579 // Scalar Floating Point  multiply extended (scalar, by element)
5580 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5581   0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5582   let Inst{11} = Imm{1}; // h
5583   let Inst{21} = Imm{0}; // l
5584   let Inst{20-16} = MRm;
5585 }
5586 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5587   0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5588   let Inst{11} = Imm{0}; // h
5589   let Inst{21} = 0b0;    // l
5590   let Inst{20-16} = MRm;
5591 }
5592
5593 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5594   SDPatternOperator opnode,
5595   Instruction INST,
5596   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5597   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5598
5599   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5600                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5601              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5602
5603   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5604                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5605              (ResTy (INST (ResTy FPRC:$Rn),
5606                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5607                OpNImm:$Imm))>;
5608
5609   // swapped operands
5610   def  : Pat<(ResTy (opnode
5611                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5612                (ResTy FPRC:$Rn))),
5613              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5614
5615   def  : Pat<(ResTy (opnode
5616                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5617                (ResTy FPRC:$Rn))),
5618              (ResTy (INST (ResTy FPRC:$Rn),
5619                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5620                OpNImm:$Imm))>;
5621 }
5622
5623 // Patterns for Scalar Floating Point  multiply (scalar, by element)
5624 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5625   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5626 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5627   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5628
5629 // Patterns for Scalar Floating Point  multiply extended (scalar, by element)
5630 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5631   FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5632   v2f32, v4f32, neon_uimm1_bare>;
5633 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5634   FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5635   v1f64, v2f64, neon_uimm0_bare>;
5636
5637 // Scalar Floating Point fused multiply-add (scalar, by element)
5638 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5639   0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5640   let Inst{11} = Imm{1}; // h
5641   let Inst{21} = Imm{0}; // l
5642   let Inst{20-16} = MRm;
5643 }
5644 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5645   0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5646   let Inst{11} = Imm{0}; // h
5647   let Inst{21} = 0b0;    // l
5648   let Inst{20-16} = MRm;
5649 }
5650
5651 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5652 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5653   0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5654   let Inst{11} = Imm{1}; // h
5655   let Inst{21} = Imm{0}; // l
5656   let Inst{20-16} = MRm;
5657 }
5658 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5659   0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5660   let Inst{11} = Imm{0}; // h
5661   let Inst{21} = 0b0;    // l
5662   let Inst{20-16} = MRm;
5663 }
5664 // We are allowed to match the fma instruction regardless of compile options.
5665 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5666   Instruction FMLAI, Instruction FMLSI,
5667   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5668   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5669   // fmla
5670   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5671                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5672                (ResTy FPRC:$Ra))),
5673              (ResTy (FMLAI (ResTy FPRC:$Ra),
5674                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5675
5676   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5677                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5678                (ResTy FPRC:$Ra))),
5679              (ResTy (FMLAI (ResTy FPRC:$Ra),
5680                (ResTy FPRC:$Rn),
5681                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5682                OpNImm:$Imm))>;
5683
5684   // swapped fmla operands
5685   def  : Pat<(ResTy (fma
5686                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5687                (ResTy FPRC:$Rn),
5688                (ResTy FPRC:$Ra))),
5689              (ResTy (FMLAI (ResTy FPRC:$Ra),
5690                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5691
5692   def  : Pat<(ResTy (fma
5693                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5694                (ResTy FPRC:$Rn),
5695                (ResTy FPRC:$Ra))),
5696              (ResTy (FMLAI (ResTy FPRC:$Ra),
5697                (ResTy FPRC:$Rn),
5698                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5699                OpNImm:$Imm))>;
5700
5701   // fmls
5702   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5703                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5704                (ResTy FPRC:$Ra))),
5705              (ResTy (FMLSI (ResTy FPRC:$Ra),
5706                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5707
5708   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5709                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5710                (ResTy FPRC:$Ra))),
5711              (ResTy (FMLSI (ResTy FPRC:$Ra),
5712                (ResTy FPRC:$Rn),
5713                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5714                OpNImm:$Imm))>;
5715
5716   // swapped fmls operands
5717   def  : Pat<(ResTy (fma
5718                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5719                (ResTy FPRC:$Rn),
5720                (ResTy FPRC:$Ra))),
5721              (ResTy (FMLSI (ResTy FPRC:$Ra),
5722                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5723
5724   def  : Pat<(ResTy (fma
5725                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5726                (ResTy FPRC:$Rn),
5727                (ResTy FPRC:$Ra))),
5728              (ResTy (FMLSI (ResTy FPRC:$Ra),
5729                (ResTy FPRC:$Rn),
5730                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5731                OpNImm:$Imm))>;
5732 }
5733
5734 // Scalar Floating Point fused multiply-add and
5735 // multiply-subtract (scalar, by element)
5736 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5737   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5738 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5739   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5740 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5741   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5742
5743 // Scalar Signed saturating doubling multiply long (scalar, by element)
5744 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5745   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5746   let Inst{11} = 0b0; // h
5747   let Inst{21} = Imm{1}; // l
5748   let Inst{20} = Imm{0}; // m
5749   let Inst{19-16} = MRm{3-0};
5750 }
5751 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5752   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5753   let Inst{11} = Imm{2}; // h
5754   let Inst{21} = Imm{1}; // l
5755   let Inst{20} = Imm{0}; // m
5756   let Inst{19-16} = MRm{3-0};
5757 }
5758 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5759   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5760   let Inst{11} = 0b0;    // h
5761   let Inst{21} = Imm{0}; // l
5762   let Inst{20-16} = MRm;
5763 }
5764 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5765   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5766   let Inst{11} = Imm{1};    // h
5767   let Inst{21} = Imm{0};    // l
5768   let Inst{20-16} = MRm;
5769 }
5770
5771 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5772   SDPatternOperator opnode,
5773   Instruction INST,
5774   ValueType ResTy, RegisterClass FPRC,
5775   ValueType OpVTy, ValueType OpTy,
5776   ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5777
5778   def  : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5779                (OpVTy (scalar_to_vector
5780                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5781              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5782
5783   //swapped operands
5784   def  : Pat<(ResTy (opnode
5785                (OpVTy (scalar_to_vector
5786                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5787                  (OpVTy FPRC:$Rn))),
5788              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5789 }
5790
5791
5792 // Patterns for Scalar Signed saturating doubling
5793 // multiply long (scalar, by element)
5794 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5795   SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5796   i32, VPR64Lo, neon_uimm2_bare>;
5797 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5798   SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5799   i32, VPR128Lo, neon_uimm3_bare>;
5800 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5801   SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5802   i32, VPR64Lo, neon_uimm1_bare>;
5803 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5804   SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5805   i32, VPR128Lo, neon_uimm2_bare>;
5806
5807 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5808 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5809   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5810   let Inst{11} = 0b0; // h
5811   let Inst{21} = Imm{1}; // l
5812   let Inst{20} = Imm{0}; // m
5813   let Inst{19-16} = MRm{3-0};
5814 }
5815 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5816   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5817   let Inst{11} = Imm{2}; // h
5818   let Inst{21} = Imm{1}; // l
5819   let Inst{20} = Imm{0}; // m
5820   let Inst{19-16} = MRm{3-0};
5821 }
5822 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5823   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5824   let Inst{11} = 0b0;    // h
5825   let Inst{21} = Imm{0}; // l
5826   let Inst{20-16} = MRm;
5827 }
5828 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5829   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5830   let Inst{11} = Imm{1};    // h
5831   let Inst{21} = Imm{0};    // l
5832   let Inst{20-16} = MRm;
5833 }
5834
5835 // Scalar Signed saturating doubling
5836 // multiply-subtract long (scalar, by element)
5837 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5838   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5839   let Inst{11} = 0b0; // h
5840   let Inst{21} = Imm{1}; // l
5841   let Inst{20} = Imm{0}; // m
5842   let Inst{19-16} = MRm{3-0};
5843 }
5844 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5845   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5846   let Inst{11} = Imm{2}; // h
5847   let Inst{21} = Imm{1}; // l
5848   let Inst{20} = Imm{0}; // m
5849   let Inst{19-16} = MRm{3-0};
5850 }
5851 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5852   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5853   let Inst{11} = 0b0;    // h
5854   let Inst{21} = Imm{0}; // l
5855   let Inst{20-16} = MRm;
5856 }
5857 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5858   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5859   let Inst{11} = Imm{1};    // h
5860   let Inst{21} = Imm{0};    // l
5861   let Inst{20-16} = MRm;
5862 }
5863
5864 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5865   SDPatternOperator opnode,
5866   SDPatternOperator coreopnode,
5867   Instruction INST,
5868   ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5869   ValueType OpTy,
5870   ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5871
5872   def  : Pat<(ResTy (opnode
5873                (ResTy ResFPRC:$Ra),
5874                (ResTy (coreopnode (OpTy FPRC:$Rn),
5875                  (OpTy (scalar_to_vector
5876                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5877              (ResTy (INST (ResTy ResFPRC:$Ra),
5878                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5879
5880   // swapped operands
5881   def  : Pat<(ResTy (opnode
5882                (ResTy ResFPRC:$Ra),
5883                (ResTy (coreopnode
5884                  (OpTy (scalar_to_vector
5885                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5886                  (OpTy FPRC:$Rn))))),
5887              (ResTy (INST (ResTy ResFPRC:$Ra),
5888                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5889 }
5890
5891 // Patterns for Scalar Signed saturating
5892 // doubling multiply-add long (scalar, by element)
5893 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5894   int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5895   i32, VPR64Lo, neon_uimm2_bare>;
5896 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5897   int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5898   i32, VPR128Lo, neon_uimm3_bare>;
5899 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5900   int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5901   i32, VPR64Lo, neon_uimm1_bare>;
5902 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5903   int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5904   i32, VPR128Lo, neon_uimm2_bare>;
5905
5906 // Patterns for Scalar Signed saturating
5907 // doubling multiply-sub long (scalar, by element)
5908 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5909   int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5910   i32, VPR64Lo, neon_uimm2_bare>;
5911 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5912   int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5913   i32, VPR128Lo, neon_uimm3_bare>;
5914 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5915   int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5916   i32, VPR64Lo, neon_uimm1_bare>;
5917 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5918   int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5919   i32, VPR128Lo, neon_uimm2_bare>;
5920
5921 // Scalar Signed saturating doubling multiply returning
5922 // high half (scalar, by element)
5923 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5924   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5925   let Inst{11} = 0b0; // h
5926   let Inst{21} = Imm{1}; // l
5927   let Inst{20} = Imm{0}; // m
5928   let Inst{19-16} = MRm{3-0};
5929 }
5930 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5931   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5932   let Inst{11} = Imm{2}; // h
5933   let Inst{21} = Imm{1}; // l
5934   let Inst{20} = Imm{0}; // m
5935   let Inst{19-16} = MRm{3-0};
5936 }
5937 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5938   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5939   let Inst{11} = 0b0;    // h
5940   let Inst{21} = Imm{0}; // l
5941   let Inst{20-16} = MRm;
5942 }
5943 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5944   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5945   let Inst{11} = Imm{1};    // h
5946   let Inst{21} = Imm{0};    // l
5947   let Inst{20-16} = MRm;
5948 }
5949
5950 // Patterns for Scalar Signed saturating doubling multiply returning
5951 // high half (scalar, by element)
5952 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5953   SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5954   i32, VPR64Lo, neon_uimm2_bare>;
5955 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5956   SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5957   i32, VPR128Lo, neon_uimm3_bare>;
5958 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5959   SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5960   i32, VPR64Lo, neon_uimm1_bare>;
5961 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5962   SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5963   i32, VPR128Lo, neon_uimm2_bare>;
5964
5965 // Scalar Signed saturating rounding doubling multiply
5966 // returning high half (scalar, by element)
5967 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5968   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5969   let Inst{11} = 0b0; // h
5970   let Inst{21} = Imm{1}; // l
5971   let Inst{20} = Imm{0}; // m
5972   let Inst{19-16} = MRm{3-0};
5973 }
5974 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5975   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5976   let Inst{11} = Imm{2}; // h
5977   let Inst{21} = Imm{1}; // l
5978   let Inst{20} = Imm{0}; // m
5979   let Inst{19-16} = MRm{3-0};
5980 }
5981 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5982   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5983   let Inst{11} = 0b0;    // h
5984   let Inst{21} = Imm{0}; // l
5985   let Inst{20-16} = MRm;
5986 }
5987 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5988   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5989   let Inst{11} = Imm{1};    // h
5990   let Inst{21} = Imm{0};    // l
5991   let Inst{20-16} = MRm;
5992 }
5993
5994 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5995   SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
5996   VPR64Lo, neon_uimm2_bare>;
5997 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5998   SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
5999   VPR128Lo, neon_uimm3_bare>;
6000 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6001   SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
6002   VPR64Lo, neon_uimm1_bare>;
6003 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6004   SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
6005   VPR128Lo, neon_uimm2_bare>;
6006
6007 // Scalar general arithmetic operation
6008 class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
6009                                         Instruction INST>
6010     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
6011
6012 class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
6013                                         Instruction INST>
6014     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
6015           (INST FPR64:$Rn, FPR64:$Rm)>;
6016
6017 class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
6018                                         Instruction INST>
6019     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
6020               (v1f64 FPR64:$Ra))),
6021           (INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
6022
6023 def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
6024 def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
6025 def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
6026 def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
6027 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
6028 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
6029 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
6030 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
6031 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
6032
6033 def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
6034 def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
6035
6036 def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
6037 def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
6038
6039 // Scalar Copy - DUP element to scalar
6040 class NeonI_Scalar_DUP<string asmop, string asmlane,
6041                        RegisterClass ResRC, RegisterOperand VPRC,
6042                        Operand OpImm>
6043   : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
6044                      asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
6045                      [],
6046                      NoItinerary> {
6047   bits<4> Imm;
6048 }
6049
6050 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
6051   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6052 }
6053 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
6054   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6055 }
6056 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
6057   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6058 }
6059 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
6060   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6061 }
6062
6063 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 0)),
6064           (f32 (EXTRACT_SUBREG (v4f32 VPR128:$Rn), sub_32))>;
6065 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 1)),
6066           (f32 (DUPsv_S (v4f32 VPR128:$Rn), 1))>;
6067 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 2)),
6068           (f32 (DUPsv_S (v4f32 VPR128:$Rn), 2))>;
6069 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 3)),
6070           (f32 (DUPsv_S (v4f32 VPR128:$Rn), 3))>;
6071
6072 def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 0)),
6073           (f64 (EXTRACT_SUBREG (v2f64 VPR128:$Rn), sub_64))>;
6074 def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 1)),
6075           (f64 (DUPdv_D (v2f64 VPR128:$Rn), 1))>;
6076
6077 def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 0)),
6078           (f32 (EXTRACT_SUBREG (v2f32 VPR64:$Rn), sub_32))>;
6079 def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 1)),
6080           (f32 (DUPsv_S (v4f32 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6081             1))>;
6082
6083 def : Pat<(f64 (vector_extract (v1f64 VPR64:$Rn), 0)),
6084           (f64 (EXTRACT_SUBREG (v1f64 VPR64:$Rn), sub_64))>;
6085
6086 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
6087   ValueType ResTy, ValueType OpTy,Operand OpLImm,
6088   ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
6089
6090   def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
6091             (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
6092
6093   def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
6094             (ResTy (DUPI
6095               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6096                 OpNImm:$Imm))>;
6097 }
6098
6099 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
6100 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
6101                                         v8i8, v16i8, neon_uimm3_bare>;
6102 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
6103                                         v4i16, v8i16, neon_uimm2_bare>;
6104 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
6105                                         v2i32, v4i32, neon_uimm1_bare>;
6106
6107 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
6108                                           ValueType OpTy, ValueType ElemTy,
6109                                           Operand OpImm, ValueType OpNTy,
6110                                           ValueType ExTy, Operand OpNImm> {
6111
6112   def : Pat<(ResTy (vector_insert (ResTy undef),
6113               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
6114               (neon_uimm0_bare:$Imm))),
6115             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
6116
6117   def : Pat<(ResTy (vector_insert (ResTy undef),
6118               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
6119               (OpNImm:$Imm))),
6120             (ResTy (DUPI
6121               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6122               OpNImm:$Imm))>;
6123 }
6124
6125 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
6126                                           ValueType OpTy, ValueType ElemTy,
6127                                           Operand OpImm, ValueType OpNTy,
6128                                           ValueType ExTy, Operand OpNImm> {
6129
6130   def : Pat<(ResTy (scalar_to_vector
6131               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
6132             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
6133
6134   def : Pat<(ResTy (scalar_to_vector
6135               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
6136             (ResTy (DUPI
6137               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6138               OpNImm:$Imm))>;
6139 }
6140
6141 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
6142 // instructions.
6143 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
6144   v1i64, v2i64, i64, neon_uimm1_bare,
6145   v1i64, v2i64, neon_uimm0_bare>;
6146 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
6147   v1i32, v4i32, i32, neon_uimm2_bare,
6148   v2i32, v4i32, neon_uimm1_bare>;
6149 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
6150   v1i16, v8i16, i32, neon_uimm3_bare,
6151   v4i16, v8i16, neon_uimm2_bare>;
6152 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
6153   v1i8, v16i8, i32, neon_uimm4_bare,
6154   v8i8, v16i8, neon_uimm3_bare>;
6155 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
6156   v1i64, v2i64, i64, neon_uimm1_bare,
6157   v1i64, v2i64, neon_uimm0_bare>;
6158 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
6159   v1i32, v4i32, i32, neon_uimm2_bare,
6160   v2i32, v4i32, neon_uimm1_bare>;
6161 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
6162   v1i16, v8i16, i32, neon_uimm3_bare,
6163   v4i16, v8i16, neon_uimm2_bare>;
6164 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
6165   v1i8, v16i8, i32, neon_uimm4_bare,
6166   v8i8, v16i8, neon_uimm3_bare>;
6167
6168 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
6169                                   Instruction DUPI, Operand OpImm,
6170                                   RegisterClass ResRC> {
6171   def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
6172           (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
6173 }
6174
6175 // Aliases for Scalar copy - DUP element (scalar)
6176 // FIXME: This is actually the preferred syntax but TableGen can't deal with
6177 // custom printing of aliases.
6178 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
6179 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
6180 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
6181 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
6182
6183 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
6184                       ValueType OpTy> {
6185   def : Pat<(ResTy (GetLow VPR128:$Rn)),
6186             (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
6187   def : Pat<(ResTy (GetHigh VPR128:$Rn)),
6188             (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
6189 }
6190
6191 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
6192 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
6193 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
6194 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
6195 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
6196 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
6197
6198 //===----------------------------------------------------------------------===//
6199 // Non-Instruction Patterns
6200 //===----------------------------------------------------------------------===//
6201
6202 // 64-bit vector bitcasts...
6203
6204 def : Pat<(v1i64 (bitconvert (v8i8  VPR64:$src))), (v1i64 VPR64:$src)>;
6205 def : Pat<(v2f32 (bitconvert (v8i8  VPR64:$src))), (v2f32 VPR64:$src)>;
6206 def : Pat<(v2i32 (bitconvert (v8i8  VPR64:$src))), (v2i32 VPR64:$src)>;
6207 def : Pat<(v4i16 (bitconvert (v8i8  VPR64:$src))), (v4i16 VPR64:$src)>;
6208
6209 def : Pat<(v1i64 (bitconvert (v4i16  VPR64:$src))), (v1i64 VPR64:$src)>;
6210 def : Pat<(v2i32 (bitconvert (v4i16  VPR64:$src))), (v2i32 VPR64:$src)>;
6211 def : Pat<(v2f32 (bitconvert (v4i16  VPR64:$src))), (v2f32 VPR64:$src)>;
6212 def : Pat<(v8i8  (bitconvert (v4i16  VPR64:$src))), (v8i8 VPR64:$src)>;
6213
6214 def : Pat<(v1i64 (bitconvert (v2i32  VPR64:$src))), (v1i64 VPR64:$src)>;
6215 def : Pat<(v2f32 (bitconvert (v2i32  VPR64:$src))), (v2f32 VPR64:$src)>;
6216 def : Pat<(v4i16 (bitconvert (v2i32  VPR64:$src))), (v4i16 VPR64:$src)>;
6217 def : Pat<(v8i8  (bitconvert (v2i32  VPR64:$src))), (v8i8 VPR64:$src)>;
6218
6219 def : Pat<(v1i64 (bitconvert (v2f32  VPR64:$src))), (v1i64 VPR64:$src)>;
6220 def : Pat<(v2i32 (bitconvert (v2f32  VPR64:$src))), (v2i32 VPR64:$src)>;
6221 def : Pat<(v4i16 (bitconvert (v2f32  VPR64:$src))), (v4i16 VPR64:$src)>;
6222 def : Pat<(v8i8  (bitconvert (v2f32  VPR64:$src))), (v8i8 VPR64:$src)>;
6223
6224 def : Pat<(v2f32 (bitconvert (v1i64  VPR64:$src))), (v2f32 VPR64:$src)>;
6225 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
6226 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
6227 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
6228
6229 def : Pat<(v1i64 (bitconvert (v1f64  VPR64:$src))), (v1i64 VPR64:$src)>;
6230 def : Pat<(v2f32 (bitconvert (v1f64  VPR64:$src))), (v2f32 VPR64:$src)>;
6231 def : Pat<(v2i32 (bitconvert (v1f64  VPR64:$src))), (v2i32 VPR64:$src)>;
6232 def : Pat<(v4i16 (bitconvert (v1f64  VPR64:$src))), (v4i16 VPR64:$src)>;
6233 def : Pat<(v8i8 (bitconvert (v1f64  VPR64:$src))), (v8i8 VPR64:$src)>;
6234 def : Pat<(f64   (bitconvert (v1f64  VPR64:$src))), (f64 VPR64:$src)>;
6235
6236 def : Pat<(v1f64 (bitconvert (v1i64  VPR64:$src))), (v1f64 VPR64:$src)>;
6237 def : Pat<(v1f64 (bitconvert (v2f32  VPR64:$src))), (v1f64 VPR64:$src)>;
6238 def : Pat<(v1f64 (bitconvert (v2i32  VPR64:$src))), (v1f64 VPR64:$src)>;
6239 def : Pat<(v1f64 (bitconvert (v4i16  VPR64:$src))), (v1f64 VPR64:$src)>;
6240 def : Pat<(v1f64 (bitconvert (v8i8  VPR64:$src))), (v1f64 VPR64:$src)>;
6241 def : Pat<(v1f64 (bitconvert (f64  VPR64:$src))), (v1f64 VPR64:$src)>;
6242
6243 // ..and 128-bit vector bitcasts...
6244
6245 def : Pat<(v2f64 (bitconvert (v16i8  VPR128:$src))), (v2f64 VPR128:$src)>;
6246 def : Pat<(v2i64 (bitconvert (v16i8  VPR128:$src))), (v2i64 VPR128:$src)>;
6247 def : Pat<(v4f32 (bitconvert (v16i8  VPR128:$src))), (v4f32 VPR128:$src)>;
6248 def : Pat<(v4i32 (bitconvert (v16i8  VPR128:$src))), (v4i32 VPR128:$src)>;
6249 def : Pat<(v8i16 (bitconvert (v16i8  VPR128:$src))), (v8i16 VPR128:$src)>;
6250
6251 def : Pat<(v2f64 (bitconvert (v8i16  VPR128:$src))), (v2f64 VPR128:$src)>;
6252 def : Pat<(v2i64 (bitconvert (v8i16  VPR128:$src))), (v2i64 VPR128:$src)>;
6253 def : Pat<(v4i32 (bitconvert (v8i16  VPR128:$src))), (v4i32 VPR128:$src)>;
6254 def : Pat<(v4f32 (bitconvert (v8i16  VPR128:$src))), (v4f32 VPR128:$src)>;
6255 def : Pat<(v16i8 (bitconvert (v8i16  VPR128:$src))), (v16i8 VPR128:$src)>;
6256
6257 def : Pat<(v2f64 (bitconvert (v4i32  VPR128:$src))), (v2f64 VPR128:$src)>;
6258 def : Pat<(v2i64 (bitconvert (v4i32  VPR128:$src))), (v2i64 VPR128:$src)>;
6259 def : Pat<(v4f32 (bitconvert (v4i32  VPR128:$src))), (v4f32 VPR128:$src)>;
6260 def : Pat<(v8i16 (bitconvert (v4i32  VPR128:$src))), (v8i16 VPR128:$src)>;
6261 def : Pat<(v16i8 (bitconvert (v4i32  VPR128:$src))), (v16i8 VPR128:$src)>;
6262
6263 def : Pat<(v2f64 (bitconvert (v4f32  VPR128:$src))), (v2f64 VPR128:$src)>;
6264 def : Pat<(v2i64 (bitconvert (v4f32  VPR128:$src))), (v2i64 VPR128:$src)>;
6265 def : Pat<(v4i32 (bitconvert (v4f32  VPR128:$src))), (v4i32 VPR128:$src)>;
6266 def : Pat<(v8i16 (bitconvert (v4f32  VPR128:$src))), (v8i16 VPR128:$src)>;
6267 def : Pat<(v16i8 (bitconvert (v4f32  VPR128:$src))), (v16i8 VPR128:$src)>;
6268
6269 def : Pat<(v2f64 (bitconvert (v2i64  VPR128:$src))), (v2f64 VPR128:$src)>;
6270 def : Pat<(v4f32 (bitconvert (v2i64  VPR128:$src))), (v4f32 VPR128:$src)>;
6271 def : Pat<(v4i32 (bitconvert (v2i64  VPR128:$src))), (v4i32 VPR128:$src)>;
6272 def : Pat<(v8i16 (bitconvert (v2i64  VPR128:$src))), (v8i16 VPR128:$src)>;
6273 def : Pat<(v16i8 (bitconvert (v2i64  VPR128:$src))), (v16i8 VPR128:$src)>;
6274
6275 def : Pat<(v2i64 (bitconvert (v2f64  VPR128:$src))), (v2i64 VPR128:$src)>;
6276 def : Pat<(v4f32 (bitconvert (v2f64  VPR128:$src))), (v4f32 VPR128:$src)>;
6277 def : Pat<(v4i32 (bitconvert (v2f64  VPR128:$src))), (v4i32 VPR128:$src)>;
6278 def : Pat<(v8i16 (bitconvert (v2f64  VPR128:$src))), (v8i16 VPR128:$src)>;
6279 def : Pat<(v16i8 (bitconvert (v2f64  VPR128:$src))), (v16i8 VPR128:$src)>;
6280
6281 // ...and scalar bitcasts...
6282 def : Pat<(f16 (bitconvert (v1i16  FPR16:$src))), (f16 FPR16:$src)>;
6283 def : Pat<(f32 (bitconvert (v1i32  FPR32:$src))), (f32 FPR32:$src)>;
6284 def : Pat<(f64 (bitconvert (v1i64  FPR64:$src))), (f64 FPR64:$src)>;
6285 def : Pat<(f64 (bitconvert (v1f64  FPR64:$src))), (f64 FPR64:$src)>;
6286
6287 def : Pat<(i64 (bitconvert (v1i64  FPR64:$src))), (FMOVxd $src)>;
6288 def : Pat<(i64 (bitconvert (v1f64  FPR64:$src))), (FMOVxd $src)>;
6289 def : Pat<(i64 (bitconvert (v2i32  FPR64:$src))), (FMOVxd $src)>;
6290 def : Pat<(i64 (bitconvert (v2f32  FPR64:$src))), (FMOVxd $src)>;
6291 def : Pat<(i64 (bitconvert (v4i16  FPR64:$src))), (FMOVxd $src)>;
6292 def : Pat<(i64 (bitconvert (v8i8  FPR64:$src))), (FMOVxd $src)>;
6293
6294 def : Pat<(i32 (bitconvert (v1i32  FPR32:$src))), (FMOVws $src)>;
6295
6296 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
6297 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
6298 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
6299
6300 def : Pat<(f64   (bitconvert (v8i8  VPR64:$src))), (f64 VPR64:$src)>;
6301 def : Pat<(f64   (bitconvert (v4i16  VPR64:$src))), (f64 VPR64:$src)>;
6302 def : Pat<(f64   (bitconvert (v2i32  VPR64:$src))), (f64 VPR64:$src)>;
6303 def : Pat<(f64   (bitconvert (v2f32  VPR64:$src))), (f64 VPR64:$src)>;
6304 def : Pat<(f64   (bitconvert (v1i64  VPR64:$src))), (f64 VPR64:$src)>;
6305
6306 def : Pat<(f128  (bitconvert (v16i8  VPR128:$src))), (f128 VPR128:$src)>;
6307 def : Pat<(f128  (bitconvert (v8i16  VPR128:$src))), (f128 VPR128:$src)>;
6308 def : Pat<(f128  (bitconvert (v4i32  VPR128:$src))), (f128 VPR128:$src)>;
6309 def : Pat<(f128  (bitconvert (v2i64  VPR128:$src))), (f128 VPR128:$src)>;
6310 def : Pat<(f128  (bitconvert (v4f32  VPR128:$src))), (f128 VPR128:$src)>;
6311 def : Pat<(f128  (bitconvert (v2f64  VPR128:$src))), (f128 VPR128:$src)>;
6312
6313 def : Pat<(v1i16 (bitconvert (f16  FPR16:$src))), (v1i16 FPR16:$src)>;
6314 def : Pat<(v1i32 (bitconvert (f32  FPR32:$src))), (v1i32 FPR32:$src)>;
6315 def : Pat<(v1i64 (bitconvert (f64  FPR64:$src))), (v1i64 FPR64:$src)>;
6316 def : Pat<(v1f64 (bitconvert (f64  FPR64:$src))), (v1f64 FPR64:$src)>;
6317
6318 def : Pat<(v1i64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6319 def : Pat<(v1f64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6320 def : Pat<(v2i32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6321 def : Pat<(v2f32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6322 def : Pat<(v4i16 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6323 def : Pat<(v8i8 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6324
6325 def : Pat<(v1i32 (bitconvert (i32  GPR32:$src))), (FMOVsw $src)>;
6326
6327 def : Pat<(v8i8   (bitconvert (f64   FPR64:$src))), (v8i8 FPR64:$src)>;
6328 def : Pat<(v4i16  (bitconvert (f64   FPR64:$src))), (v4i16 FPR64:$src)>;
6329 def : Pat<(v2i32  (bitconvert (f64   FPR64:$src))), (v2i32 FPR64:$src)>;
6330 def : Pat<(v2f32  (bitconvert (f64   FPR64:$src))), (v2f32 FPR64:$src)>;
6331 def : Pat<(v1i64  (bitconvert (f64   FPR64:$src))), (v1i64 FPR64:$src)>;
6332
6333 def : Pat<(v16i8  (bitconvert (f128   FPR128:$src))), (v16i8 FPR128:$src)>;
6334 def : Pat<(v8i16  (bitconvert (f128   FPR128:$src))), (v8i16 FPR128:$src)>;
6335 def : Pat<(v4i32  (bitconvert (f128   FPR128:$src))), (v4i32 FPR128:$src)>;
6336 def : Pat<(v2i64  (bitconvert (f128   FPR128:$src))), (v2i64 FPR128:$src)>;
6337 def : Pat<(v4f32  (bitconvert (f128   FPR128:$src))), (v4f32 FPR128:$src)>;
6338 def : Pat<(v2f64  (bitconvert (f128   FPR128:$src))), (v2f64 FPR128:$src)>;
6339
6340 // Scalar Three Same
6341
6342 def neon_uimm3 : Operand<i64>,
6343                    ImmLeaf<i64, [{return Imm < 8;}]> {
6344   let ParserMatchClass = uimm3_asmoperand;
6345   let PrintMethod = "printUImmHexOperand";
6346 }
6347
6348 def neon_uimm4 : Operand<i64>,
6349                    ImmLeaf<i64, [{return Imm < 16;}]> {
6350   let ParserMatchClass = uimm4_asmoperand;
6351   let PrintMethod = "printUImmHexOperand";
6352 }
6353
6354 // Bitwise Extract
6355 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6356                     string OpS, RegisterOperand OpVPR, Operand OpImm>
6357   : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6358                      (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6359                      asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6360                      ", $Rm." # OpS # ", $Index",
6361                      [],
6362                      NoItinerary>{
6363   bits<4> Index;
6364 }
6365
6366 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6367                                VPR64, neon_uimm3> {
6368   let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6369 }
6370
6371 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6372                                VPR128, neon_uimm4> {
6373   let Inst{14-11} = Index;
6374 }
6375
6376 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6377                  Operand OpImm>
6378   : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6379                                  (i64 OpImm:$Imm))),
6380               (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6381
6382 def : NI_Extract<v8i8,  VPR64,  EXTvvvi_8b,  neon_uimm3>;
6383 def : NI_Extract<v4i16, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6384 def : NI_Extract<v2i32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6385 def : NI_Extract<v1i64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6386 def : NI_Extract<v2f32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6387 def : NI_Extract<v1f64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6388 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6389 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6390 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6391 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6392 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6393 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6394
6395 // Table lookup
6396 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6397              string asmop, string OpS, RegisterOperand OpVPR,
6398              RegisterOperand VecList>
6399   : NeonI_TBL<q, op2, len, op,
6400               (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6401               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6402               [],
6403               NoItinerary>;
6404
6405 // The vectors in look up table are always 16b
6406 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6407   def _8b  : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6408                     !cast<RegisterOperand>(List # "16B_operand")>;
6409
6410   def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6411                     !cast<RegisterOperand>(List # "16B_operand")>;
6412 }
6413
6414 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6415 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6416 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6417 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6418
6419 // Table lookup extention
6420 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6421              string asmop, string OpS, RegisterOperand OpVPR,
6422              RegisterOperand VecList>
6423   : NeonI_TBL<q, op2, len, op,
6424               (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6425               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6426               [],
6427               NoItinerary> {
6428   let Constraints = "$src = $Rd";
6429 }
6430
6431 // The vectors in look up table are always 16b
6432 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6433   def _8b  : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6434                     !cast<RegisterOperand>(List # "16B_operand")>;
6435
6436   def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6437                     !cast<RegisterOperand>(List # "16B_operand")>;
6438 }
6439
6440 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6441 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6442 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6443 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6444
6445 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6446                      RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6447   : NeonI_copy<0b1, 0b0, 0b0011,
6448                (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6449                asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6450                [(set (ResTy VPR128:$Rd),
6451                  (ResTy (vector_insert
6452                    (ResTy VPR128:$src),
6453                    (OpTy OpGPR:$Rn),
6454                    (OpImm:$Imm))))],
6455                NoItinerary> {
6456   bits<4> Imm;
6457   let Constraints = "$src = $Rd";
6458 }
6459
6460 //Insert element (vector, from main)
6461 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6462                            neon_uimm4_bare> {
6463   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6464 }
6465 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6466                            neon_uimm3_bare> {
6467   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6468 }
6469 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6470                            neon_uimm2_bare> {
6471   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6472 }
6473 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6474                            neon_uimm1_bare> {
6475   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6476 }
6477
6478 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6479                     (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6480 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6481                     (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6482 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6483                     (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6484 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6485                     (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6486
6487 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6488                              RegisterClass OpGPR, ValueType OpTy,
6489                              Operand OpImm, Instruction INS>
6490   : Pat<(ResTy (vector_insert
6491               (ResTy VPR64:$src),
6492               (OpTy OpGPR:$Rn),
6493               (OpImm:$Imm))),
6494         (ResTy (EXTRACT_SUBREG
6495           (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6496             OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6497
6498 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6499                                           neon_uimm3_bare, INSbw>;
6500 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6501                                           neon_uimm2_bare, INShw>;
6502 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6503                                           neon_uimm1_bare, INSsw>;
6504 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6505                                           neon_uimm0_bare, INSdx>;
6506
6507 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6508   : NeonI_insert<0b1, 0b1,
6509                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6510                  ResImm:$Immd, ResImm:$Immn),
6511                  asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6512                  [],
6513                  NoItinerary> {
6514   let Constraints = "$src = $Rd";
6515   bits<4> Immd;
6516   bits<4> Immn;
6517 }
6518
6519 //Insert element (vector, from element)
6520 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6521   let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6522   let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6523 }
6524 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6525   let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6526   let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6527   // bit 11 is unspecified, but should be set to zero.
6528 }
6529 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6530   let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6531   let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6532   // bits 11-12 are unspecified, but should be set to zero.
6533 }
6534 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6535   let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6536   let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6537   // bits 11-13 are unspecified, but should be set to zero.
6538 }
6539
6540 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6541                     (INSELb VPR128:$Rd, VPR128:$Rn,
6542                       neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6543 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6544                     (INSELh VPR128:$Rd, VPR128:$Rn,
6545                       neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6546 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6547                     (INSELs VPR128:$Rd, VPR128:$Rn,
6548                       neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6549 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6550                     (INSELd VPR128:$Rd, VPR128:$Rn,
6551                       neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6552
6553 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6554                                 ValueType MidTy, Operand StImm, Operand NaImm,
6555                                 Instruction INS> {
6556 def : Pat<(ResTy (vector_insert
6557             (ResTy VPR128:$src),
6558             (MidTy (vector_extract
6559               (ResTy VPR128:$Rn),
6560               (StImm:$Immn))),
6561             (StImm:$Immd))),
6562           (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6563               StImm:$Immd, StImm:$Immn)>;
6564
6565 def : Pat <(ResTy (vector_insert
6566              (ResTy VPR128:$src),
6567              (MidTy (vector_extract
6568                (NaTy VPR64:$Rn),
6569                (NaImm:$Immn))),
6570              (StImm:$Immd))),
6571            (INS (ResTy VPR128:$src),
6572              (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6573              StImm:$Immd, NaImm:$Immn)>;
6574
6575 def : Pat <(NaTy (vector_insert
6576              (NaTy VPR64:$src),
6577              (MidTy (vector_extract
6578                (ResTy VPR128:$Rn),
6579                (StImm:$Immn))),
6580              (NaImm:$Immd))),
6581            (NaTy (EXTRACT_SUBREG
6582              (ResTy (INS
6583                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6584                (ResTy VPR128:$Rn),
6585                NaImm:$Immd, StImm:$Immn)),
6586              sub_64))>;
6587
6588 def : Pat <(NaTy (vector_insert
6589              (NaTy VPR64:$src),
6590              (MidTy (vector_extract
6591                (NaTy VPR64:$Rn),
6592                (NaImm:$Immn))),
6593              (NaImm:$Immd))),
6594            (NaTy (EXTRACT_SUBREG
6595              (ResTy (INS
6596                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6597                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6598                NaImm:$Immd, NaImm:$Immn)),
6599              sub_64))>;
6600 }
6601
6602 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6603                             neon_uimm1_bare, INSELs>;
6604 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6605                             neon_uimm0_bare, INSELd>;
6606 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6607                             neon_uimm3_bare, INSELb>;
6608 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6609                             neon_uimm2_bare, INSELh>;
6610 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6611                             neon_uimm1_bare, INSELs>;
6612 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6613                             neon_uimm0_bare, INSELd>;
6614
6615 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6616                                       ValueType MidTy,
6617                                       RegisterClass OpFPR, Operand ResImm,
6618                                       SubRegIndex SubIndex, Instruction INS> {
6619 def : Pat <(ResTy (vector_insert
6620              (ResTy VPR128:$src),
6621              (MidTy OpFPR:$Rn),
6622              (ResImm:$Imm))),
6623            (INS (ResTy VPR128:$src),
6624              (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6625              ResImm:$Imm,
6626              (i64 0))>;
6627
6628 def : Pat <(NaTy (vector_insert
6629              (NaTy VPR64:$src),
6630              (MidTy OpFPR:$Rn),
6631              (ResImm:$Imm))),
6632            (NaTy (EXTRACT_SUBREG
6633              (ResTy (INS
6634                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6635                (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6636                ResImm:$Imm,
6637                (i64 0))),
6638              sub_64))>;
6639 }
6640
6641 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6642                                   sub_32, INSELs>;
6643 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6644                                   sub_64, INSELd>;
6645
6646 class NeonI_SMOV<string asmop, string Res, bit Q,
6647                  ValueType OpTy, ValueType eleTy,
6648                  Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6649   : NeonI_copy<Q, 0b0, 0b0101,
6650                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6651                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6652                [(set (ResTy ResGPR:$Rd),
6653                  (ResTy (sext_inreg
6654                    (ResTy (vector_extract
6655                      (OpTy VPR128:$Rn), (OpImm:$Imm))),
6656                    eleTy)))],
6657                NoItinerary> {
6658   bits<4> Imm;
6659 }
6660
6661 //Signed integer move (main, from element)
6662 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6663                         GPR32, i32> {
6664   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6665 }
6666 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6667                         GPR32, i32> {
6668   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6669 }
6670 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6671                         GPR64, i64> {
6672   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6673 }
6674 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6675                         GPR64, i64> {
6676   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6677 }
6678 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6679                         GPR64, i64> {
6680   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6681 }
6682
6683 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6684                                ValueType eleTy, Operand StImm,  Operand NaImm,
6685                                Instruction SMOVI> {
6686   def : Pat<(i64 (sext_inreg
6687               (i64 (anyext
6688                 (i32 (vector_extract
6689                   (StTy VPR128:$Rn), (StImm:$Imm))))),
6690               eleTy)),
6691             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6692
6693   def : Pat<(i64 (sext
6694               (i32 (vector_extract
6695                 (StTy VPR128:$Rn), (StImm:$Imm))))),
6696             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6697
6698   def : Pat<(i64 (sext_inreg
6699               (i64 (vector_extract
6700                 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6701               eleTy)),
6702             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6703               NaImm:$Imm)>;
6704
6705   def : Pat<(i64 (sext_inreg
6706               (i64 (anyext
6707                 (i32 (vector_extract
6708                   (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6709               eleTy)),
6710             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6711               NaImm:$Imm)>;
6712
6713   def : Pat<(i64 (sext
6714               (i32 (vector_extract
6715                 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6716             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6717               NaImm:$Imm)>;
6718 }
6719
6720 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6721                           neon_uimm3_bare, SMOVxb>;
6722 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6723                           neon_uimm2_bare, SMOVxh>;
6724 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6725                           neon_uimm1_bare, SMOVxs>;
6726
6727 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6728                           ValueType eleTy, Operand StImm,  Operand NaImm,
6729                           Instruction SMOVI>
6730   : Pat<(i32 (sext_inreg
6731           (i32 (vector_extract
6732             (NaTy VPR64:$Rn), (NaImm:$Imm))),
6733           eleTy)),
6734         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6735           NaImm:$Imm)>;
6736
6737 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6738                          neon_uimm3_bare, SMOVwb>;
6739 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6740                          neon_uimm2_bare, SMOVwh>;
6741
6742 class NeonI_UMOV<string asmop, string Res, bit Q,
6743                  ValueType OpTy, Operand OpImm,
6744                  RegisterClass ResGPR, ValueType ResTy>
6745   : NeonI_copy<Q, 0b0, 0b0111,
6746                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6747                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6748                [(set (ResTy ResGPR:$Rd),
6749                   (ResTy (vector_extract
6750                     (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6751                NoItinerary> {
6752   bits<4> Imm;
6753 }
6754
6755 //Unsigned integer move (main, from element)
6756 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6757                          GPR32, i32> {
6758   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6759 }
6760 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6761                          GPR32, i32> {
6762   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6763 }
6764 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6765                          GPR32, i32> {
6766   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6767 }
6768 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6769                          GPR64, i64> {
6770   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6771 }
6772
6773 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6774                     (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6775 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6776                     (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6777
6778 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6779                          Operand StImm,  Operand NaImm,
6780                          Instruction SMOVI>
6781   : Pat<(ResTy (vector_extract
6782           (NaTy VPR64:$Rn), NaImm:$Imm)),
6783         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6784           NaImm:$Imm)>;
6785
6786 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6787                         neon_uimm3_bare, UMOVwb>;
6788 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6789                         neon_uimm2_bare, UMOVwh>;
6790 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6791                         neon_uimm1_bare, UMOVws>;
6792
6793 def : Pat<(i32 (and
6794             (i32 (vector_extract
6795               (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6796             255)),
6797           (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6798
6799 def : Pat<(i32 (and
6800             (i32 (vector_extract
6801               (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6802             65535)),
6803           (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6804
6805 def : Pat<(i64 (zext
6806             (i32 (vector_extract
6807               (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6808           (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6809
6810 def : Pat<(i32 (and
6811             (i32 (vector_extract
6812               (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6813             255)),
6814           (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6815             neon_uimm3_bare:$Imm)>;
6816
6817 def : Pat<(i32 (and
6818             (i32 (vector_extract
6819               (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6820             65535)),
6821           (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6822             neon_uimm2_bare:$Imm)>;
6823
6824 def : Pat<(i64 (zext
6825             (i32 (vector_extract
6826               (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6827           (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6828             neon_uimm0_bare:$Imm)>;
6829
6830 // Additional copy patterns for scalar types
6831 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6832           (UMOVwb (v16i8
6833             (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6834
6835 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6836           (UMOVwh (v8i16
6837             (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6838
6839 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6840           (FMOVws FPR32:$Rn)>;
6841
6842 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6843           (FMOVxd FPR64:$Rn)>;
6844
6845 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6846           (f64 FPR64:$Rn)>;
6847
6848 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6849           (v1i8 (EXTRACT_SUBREG (v16i8
6850             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6851             sub_8))>;
6852
6853 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6854           (v1i16 (EXTRACT_SUBREG (v8i16
6855             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6856             sub_16))>;
6857
6858 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6859           (FMOVsw $src)>;
6860
6861 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6862           (FMOVdx $src)>;
6863
6864 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
6865           (v8i8 (EXTRACT_SUBREG (v16i8
6866             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6867             sub_64))>;
6868
6869 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
6870           (v4i16 (EXTRACT_SUBREG (v8i16
6871             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6872             sub_64))>;
6873
6874 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6875           (v2i32 (EXTRACT_SUBREG (v16i8
6876             (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6877             sub_64))>;
6878
6879 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
6880           (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6881
6882 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
6883           (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6884
6885 def : Pat<(v4i32 (scalar_to_vector GPR32:$Rn)),
6886           (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6887
6888 def : Pat<(v2i64 (scalar_to_vector GPR64:$Rn)),
6889           (INSdx (v2i64 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6890
6891 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
6892           (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>;
6893 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
6894           (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>;
6895
6896 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6897           (v1f64 FPR64:$Rn)>;
6898
6899 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6900           (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6901                          (f64 FPR64:$src), sub_64)>;
6902
6903 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane,  string rnlane,
6904                     RegisterOperand ResVPR, Operand OpImm>
6905   : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6906                (ins VPR128:$Rn, OpImm:$Imm),
6907                asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6908                [],
6909                NoItinerary> {
6910   bits<4> Imm;
6911 }
6912
6913 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6914                               neon_uimm4_bare> {
6915   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6916 }
6917
6918 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6919                               neon_uimm3_bare> {
6920   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6921 }
6922
6923 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6924                               neon_uimm2_bare> {
6925   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6926 }
6927
6928 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6929                               neon_uimm1_bare> {
6930   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6931 }
6932
6933 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6934                               neon_uimm4_bare> {
6935   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6936 }
6937
6938 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6939                               neon_uimm3_bare> {
6940   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6941 }
6942
6943 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6944                               neon_uimm2_bare> {
6945   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6946 }
6947
6948 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6949                                        ValueType OpTy,ValueType NaTy,
6950                                        ValueType ExTy, Operand OpLImm,
6951                                        Operand OpNImm> {
6952 def  : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6953         (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6954
6955 def : Pat<(ResTy (Neon_vduplane
6956             (NaTy VPR64:$Rn), OpNImm:$Imm)),
6957           (ResTy (DUPELT
6958             (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6959 }
6960 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6961                              neon_uimm4_bare, neon_uimm3_bare>;
6962 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6963                              neon_uimm4_bare, neon_uimm3_bare>;
6964 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6965                              neon_uimm3_bare, neon_uimm2_bare>;
6966 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6967                              neon_uimm3_bare, neon_uimm2_bare>;
6968 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6969                              neon_uimm2_bare, neon_uimm1_bare>;
6970 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6971                              neon_uimm2_bare, neon_uimm1_bare>;
6972 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6973                              neon_uimm1_bare, neon_uimm0_bare>;
6974 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6975                              neon_uimm2_bare, neon_uimm1_bare>;
6976 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6977                              neon_uimm2_bare, neon_uimm1_bare>;
6978 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6979                              neon_uimm1_bare, neon_uimm0_bare>;
6980
6981 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6982           (v2f32 (DUPELT2s
6983             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6984             (i64 0)))>;
6985 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6986           (v4f32 (DUPELT4s
6987             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6988             (i64 0)))>;
6989 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
6990           (v2f64 (DUPELT2d
6991             (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
6992             (i64 0)))>;
6993
6994 class NeonI_DUP<bit Q, string asmop, string rdlane,
6995                 RegisterOperand ResVPR, ValueType ResTy,
6996                 RegisterClass OpGPR, ValueType OpTy>
6997   : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
6998                asmop # "\t$Rd" # rdlane # ", $Rn",
6999                [(set (ResTy ResVPR:$Rd),
7000                  (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
7001                NoItinerary>;
7002
7003 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
7004   let Inst{20-16} = 0b00001;
7005   // bits 17-20 are unspecified, but should be set to zero.
7006 }
7007
7008 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
7009   let Inst{20-16} = 0b00010;
7010   // bits 18-20 are unspecified, but should be set to zero.
7011 }
7012
7013 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
7014   let Inst{20-16} = 0b00100;
7015   // bits 19-20 are unspecified, but should be set to zero.
7016 }
7017
7018 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
7019   let Inst{20-16} = 0b01000;
7020   // bit 20 is unspecified, but should be set to zero.
7021 }
7022
7023 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
7024   let Inst{20-16} = 0b00001;
7025   // bits 17-20 are unspecified, but should be set to zero.
7026 }
7027
7028 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
7029   let Inst{20-16} = 0b00010;
7030   // bits 18-20 are unspecified, but should be set to zero.
7031 }
7032
7033 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
7034   let Inst{20-16} = 0b00100;
7035   // bits 19-20 are unspecified, but should be set to zero.
7036 }
7037
7038 // patterns for CONCAT_VECTORS
7039 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
7040 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
7041           (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
7042 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
7043           (INSELd
7044             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7045             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
7046             (i64 1),
7047             (i64 0))>;
7048 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
7049           (DUPELT2d
7050             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7051             (i64 0))> ;
7052 }
7053
7054 defm : Concat_Vector_Pattern<v16i8, v8i8>;
7055 defm : Concat_Vector_Pattern<v8i16, v4i16>;
7056 defm : Concat_Vector_Pattern<v4i32, v2i32>;
7057 defm : Concat_Vector_Pattern<v2i64, v1i64>;
7058 defm : Concat_Vector_Pattern<v4f32, v2f32>;
7059 defm : Concat_Vector_Pattern<v2f64, v1f64>;
7060
7061 def : Pat<(v2i32 (concat_vectors (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rn))),
7062           (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>;
7063 def : Pat<(v2i32 (concat_vectors undef, (v1i32 FPR32:$Rn))),
7064           (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>;
7065
7066 //patterns for EXTRACT_SUBVECTOR
7067 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
7068           (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7069 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
7070           (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7071 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
7072           (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7073 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
7074           (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7075 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
7076           (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7077 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
7078           (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7079
7080 // The followings are for instruction class (3V Elem)
7081
7082 // Variant 1
7083
7084 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
7085              string asmop, string ResS, string OpS, string EleOpS,
7086              Operand OpImm, RegisterOperand ResVPR,
7087              RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7088   : NeonI_2VElem<q, u, size, opcode,
7089                  (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
7090                                          EleOpVPR:$Re, OpImm:$Index),
7091                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7092                  ", $Re." # EleOpS # "[$Index]",
7093                  [],
7094                  NoItinerary> {
7095   bits<3> Index;
7096   bits<5> Re;
7097
7098   let Constraints = "$src = $Rd";
7099 }
7100
7101 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
7102   // vector register class for element is always 128-bit to cover the max index
7103   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7104                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
7105     let Inst{11} = {Index{1}};
7106     let Inst{21} = {Index{0}};
7107     let Inst{20-16} = Re;
7108   }
7109
7110   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7111                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7112     let Inst{11} = {Index{1}};
7113     let Inst{21} = {Index{0}};
7114     let Inst{20-16} = Re;
7115   }
7116
7117   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7118   def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7119                      neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7120     let Inst{11} = {Index{2}};
7121     let Inst{21} = {Index{1}};
7122     let Inst{20} = {Index{0}};
7123     let Inst{19-16} = Re{3-0};
7124   }
7125
7126   def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7127                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7128     let Inst{11} = {Index{2}};
7129     let Inst{21} = {Index{1}};
7130     let Inst{20} = {Index{0}};
7131     let Inst{19-16} = Re{3-0};
7132   }
7133 }
7134
7135 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
7136 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
7137
7138 // Pattern for lane in 128-bit vector
7139 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7140                    RegisterOperand ResVPR, RegisterOperand OpVPR,
7141                    RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
7142                    ValueType EleOpTy>
7143   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
7144           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7145         (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7146
7147 // Pattern for lane in 64-bit vector
7148 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7149                   RegisterOperand ResVPR, RegisterOperand OpVPR,
7150                   RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
7151                   ValueType EleOpTy>
7152   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
7153           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7154         (INST ResVPR:$src, OpVPR:$Rn,
7155           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7156
7157 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
7158 {
7159   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7160                      op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
7161
7162   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7163                      op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
7164
7165   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7166                      op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7167
7168   def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7169                      op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7170
7171   // Index can only be half of the max value for lane in 64-bit vector
7172
7173   def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7174                     op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
7175
7176   def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7177                     op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7178 }
7179
7180 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
7181 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
7182
7183 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
7184                  string asmop, string ResS, string OpS, string EleOpS,
7185                  Operand OpImm, RegisterOperand ResVPR,
7186                  RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7187   : NeonI_2VElem<q, u, size, opcode,
7188                  (outs ResVPR:$Rd), (ins OpVPR:$Rn,
7189                                          EleOpVPR:$Re, OpImm:$Index),
7190                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7191                  ", $Re." # EleOpS # "[$Index]",
7192                  [],
7193                  NoItinerary> {
7194   bits<3> Index;
7195   bits<5> Re;
7196 }
7197
7198 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
7199   // vector register class for element is always 128-bit to cover the max index
7200   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7201                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
7202     let Inst{11} = {Index{1}};
7203     let Inst{21} = {Index{0}};
7204     let Inst{20-16} = Re;
7205   }
7206
7207   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7208                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7209     let Inst{11} = {Index{1}};
7210     let Inst{21} = {Index{0}};
7211     let Inst{20-16} = Re;
7212   }
7213
7214   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7215   def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7216                          neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7217     let Inst{11} = {Index{2}};
7218     let Inst{21} = {Index{1}};
7219     let Inst{20} = {Index{0}};
7220     let Inst{19-16} = Re{3-0};
7221   }
7222
7223   def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7224                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7225     let Inst{11} = {Index{2}};
7226     let Inst{21} = {Index{1}};
7227     let Inst{20} = {Index{0}};
7228     let Inst{19-16} = Re{3-0};
7229   }
7230 }
7231
7232 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
7233 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
7234 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
7235
7236 // Pattern for lane in 128-bit vector
7237 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7238                        RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7239                        ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7240   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7241           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7242         (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7243
7244 // Pattern for lane in 64-bit vector
7245 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7246                       RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7247                       ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7248   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7249           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7250         (INST OpVPR:$Rn,
7251           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7252
7253 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
7254   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7255                          op, VPR64, VPR128, v2i32, v2i32, v4i32>;
7256
7257   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7258                          op, VPR128, VPR128, v4i32, v4i32, v4i32>;
7259
7260   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7261                          op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7262
7263   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7264                          op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7265
7266   // Index can only be half of the max value for lane in 64-bit vector
7267
7268   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7269                         op, VPR64, VPR64, v2i32, v2i32, v2i32>;
7270
7271   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7272                         op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7273 }
7274
7275 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
7276 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
7277 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
7278
7279 // Variant 2
7280
7281 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
7282   // vector register class for element is always 128-bit to cover the max index
7283   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7284                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
7285     let Inst{11} = {Index{1}};
7286     let Inst{21} = {Index{0}};
7287     let Inst{20-16} = Re;
7288   }
7289
7290   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7291                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7292     let Inst{11} = {Index{1}};
7293     let Inst{21} = {Index{0}};
7294     let Inst{20-16} = Re;
7295   }
7296
7297   // _1d2d doesn't exist!
7298
7299   def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7300                          neon_uimm1_bare, VPR128, VPR128, VPR128> {
7301     let Inst{11} = {Index{0}};
7302     let Inst{21} = 0b0;
7303     let Inst{20-16} = Re;
7304   }
7305 }
7306
7307 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
7308 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
7309
7310 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
7311                          RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7312                          ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
7313                          SDPatternOperator coreop>
7314   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7315           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
7316         (INST OpVPR:$Rn,
7317           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
7318
7319 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
7320   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7321                          op, VPR64, VPR128, v2f32, v2f32, v4f32>;
7322
7323   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7324                          op, VPR128, VPR128, v4f32, v4f32, v4f32>;
7325
7326   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7327                          op, VPR128, VPR128, v2f64, v2f64, v2f64>;
7328
7329   // Index can only be half of the max value for lane in 64-bit vector
7330
7331   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7332                         op, VPR64, VPR64, v2f32, v2f32, v2f32>;
7333
7334   def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7335                            op, VPR128, VPR64, v2f64, v2f64, v1f64,
7336                            BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7337 }
7338
7339 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
7340 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
7341
7342 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
7343                        (v2f32 VPR64:$Rn))),
7344           (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7345
7346 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
7347                        (v4f32 VPR128:$Rn))),
7348           (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7349
7350 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
7351                        (v2f64 VPR128:$Rn))),
7352           (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7353
7354 // The followings are patterns using fma
7355 // -ffp-contract=fast generates fma
7356
7357 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7358   // vector register class for element is always 128-bit to cover the max index
7359   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7360                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
7361     let Inst{11} = {Index{1}};
7362     let Inst{21} = {Index{0}};
7363     let Inst{20-16} = Re;
7364   }
7365
7366   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7367                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7368     let Inst{11} = {Index{1}};
7369     let Inst{21} = {Index{0}};
7370     let Inst{20-16} = Re;
7371   }
7372
7373   // _1d2d doesn't exist!
7374
7375   def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7376                      neon_uimm1_bare, VPR128, VPR128, VPR128> {
7377     let Inst{11} = {Index{0}};
7378     let Inst{21} = 0b0;
7379     let Inst{20-16} = Re;
7380   }
7381 }
7382
7383 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7384 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7385
7386 // Pattern for lane in 128-bit vector
7387 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7388                        RegisterOperand ResVPR, RegisterOperand OpVPR,
7389                        ValueType ResTy, ValueType OpTy,
7390                        SDPatternOperator coreop>
7391   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7392                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7393         (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7394
7395 // Pattern for lane 0
7396 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7397                       RegisterOperand ResVPR, ValueType ResTy>
7398   : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7399                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7400                    (ResTy ResVPR:$src))),
7401         (INST ResVPR:$src, ResVPR:$Rn,
7402               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7403
7404 // Pattern for lane in 64-bit vector
7405 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7406                       RegisterOperand ResVPR, RegisterOperand OpVPR,
7407                       ValueType ResTy, ValueType OpTy,
7408                       SDPatternOperator coreop>
7409   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7410                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7411         (INST ResVPR:$src, ResVPR:$Rn,
7412           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7413
7414 // Pattern for lane in 64-bit vector
7415 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7416                            SDPatternOperator op,
7417                            RegisterOperand ResVPR, RegisterOperand OpVPR,
7418                            ValueType ResTy, ValueType OpTy,
7419                            SDPatternOperator coreop>
7420   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7421                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7422         (INST ResVPR:$src, ResVPR:$Rn,
7423           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7424
7425
7426 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7427   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7428                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7429                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7430
7431   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7432                         op, VPR64, v2f32>;
7433
7434   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7435                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7436                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7437
7438   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7439                         op, VPR128, v4f32>;
7440
7441   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7442                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7443                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7444
7445   // Index can only be half of the max value for lane in 64-bit vector
7446
7447   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7448                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7449                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7450
7451   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7452                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7453                              BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7454 }
7455
7456 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7457
7458 // Pattern for lane 0
7459 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7460                       RegisterOperand ResVPR, ValueType ResTy>
7461   : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7462                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7463                    (ResTy ResVPR:$src))),
7464         (INST ResVPR:$src, ResVPR:$Rn,
7465               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7466
7467 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7468 {
7469   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7470                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7471                          BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7472
7473   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7474                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7475                          BinOpFrag<(Neon_vduplane
7476                                      (fneg node:$LHS), node:$RHS)>>;
7477
7478   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7479                         op, VPR64, v2f32>;
7480
7481   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7482                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7483                          BinOpFrag<(fneg (Neon_vduplane
7484                                      node:$LHS, node:$RHS))>>;
7485
7486   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7487                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7488                          BinOpFrag<(Neon_vduplane
7489                                      (fneg node:$LHS), node:$RHS)>>;
7490
7491   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7492                         op, VPR128, v4f32>;
7493
7494   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7495                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7496                          BinOpFrag<(fneg (Neon_vduplane
7497                                      node:$LHS, node:$RHS))>>;
7498
7499   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7500                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7501                          BinOpFrag<(Neon_vduplane
7502                                      (fneg node:$LHS), node:$RHS)>>;
7503
7504   // Index can only be half of the max value for lane in 64-bit vector
7505
7506   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7507                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7508                         BinOpFrag<(fneg (Neon_vduplane
7509                                     node:$LHS, node:$RHS))>>;
7510
7511   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7512                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7513                         BinOpFrag<(Neon_vduplane
7514                                     (fneg node:$LHS), node:$RHS)>>;
7515
7516   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7517                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7518                         BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7519
7520   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7521                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7522                         BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7523
7524   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7525                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7526                              BinOpFrag<(fneg (Neon_combine_2d
7527                                          node:$LHS, node:$RHS))>>;
7528
7529   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7530                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7531                              BinOpFrag<(Neon_combine_2d
7532                                          (fneg node:$LHS), (fneg node:$RHS))>>;
7533 }
7534
7535 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7536
7537 // Variant 3: Long type
7538 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7539 //      SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7540
7541 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7542   // vector register class for element is always 128-bit to cover the max index
7543   def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7544                      neon_uimm2_bare, VPR128, VPR64, VPR128> {
7545     let Inst{11} = {Index{1}};
7546     let Inst{21} = {Index{0}};
7547     let Inst{20-16} = Re;
7548   }
7549
7550   def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7551                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7552     let Inst{11} = {Index{1}};
7553     let Inst{21} = {Index{0}};
7554     let Inst{20-16} = Re;
7555   }
7556
7557   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7558   def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7559                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7560     let Inst{11} = {Index{2}};
7561     let Inst{21} = {Index{1}};
7562     let Inst{20} = {Index{0}};
7563     let Inst{19-16} = Re{3-0};
7564   }
7565
7566   def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7567                      neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7568     let Inst{11} = {Index{2}};
7569     let Inst{21} = {Index{1}};
7570     let Inst{20} = {Index{0}};
7571     let Inst{19-16} = Re{3-0};
7572   }
7573 }
7574
7575 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7576 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7577 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7578 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7579 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7580 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7581
7582 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7583   // vector register class for element is always 128-bit to cover the max index
7584   def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7585                          neon_uimm2_bare, VPR128, VPR64, VPR128> {
7586     let Inst{11} = {Index{1}};
7587     let Inst{21} = {Index{0}};
7588     let Inst{20-16} = Re;
7589   }
7590
7591   def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7592                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7593     let Inst{11} = {Index{1}};
7594     let Inst{21} = {Index{0}};
7595     let Inst{20-16} = Re;
7596   }
7597
7598   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7599   def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7600                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7601     let Inst{11} = {Index{2}};
7602     let Inst{21} = {Index{1}};
7603     let Inst{20} = {Index{0}};
7604     let Inst{19-16} = Re{3-0};
7605   }
7606
7607   def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7608                          neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7609     let Inst{11} = {Index{2}};
7610     let Inst{21} = {Index{1}};
7611     let Inst{20} = {Index{0}};
7612     let Inst{19-16} = Re{3-0};
7613   }
7614 }
7615
7616 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7617 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7618 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7619
7620 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7621           (FMOVdd $src)>;
7622
7623 // Pattern for lane in 128-bit vector
7624 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7625                      RegisterOperand EleOpVPR, ValueType ResTy,
7626                      ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7627                      SDPatternOperator hiop>
7628   : Pat<(ResTy (op (ResTy VPR128:$src),
7629           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7630           (HalfOpTy (Neon_vduplane
7631                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7632         (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7633
7634 // Pattern for lane in 64-bit vector
7635 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7636                     RegisterOperand EleOpVPR, ValueType ResTy,
7637                     ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7638                     SDPatternOperator hiop>
7639   : Pat<(ResTy (op (ResTy VPR128:$src),
7640           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7641           (HalfOpTy (Neon_vduplane
7642                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7643         (INST VPR128:$src, VPR128:$Rn,
7644           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7645
7646 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7647                      ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7648                      SDPatternOperator hiop, Instruction DupInst>
7649   : Pat<(ResTy (op (ResTy VPR128:$src),
7650           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7651           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7652         (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7653
7654 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7655   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7656                      op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7657
7658   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7659                      op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7660
7661   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7662                        op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7663
7664   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7665                        op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7666
7667   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7668                        op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7669
7670   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7671                        op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7672
7673   // Index can only be half of the max value for lane in 64-bit vector
7674
7675   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7676                     op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7677
7678   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7679                     op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7680
7681   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7682                       op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7683
7684   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7685                       op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7686 }
7687
7688 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7689 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7690 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7691 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7692
7693 // Pattern for lane in 128-bit vector
7694 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7695                          RegisterOperand EleOpVPR, ValueType ResTy,
7696                          ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7697                          SDPatternOperator hiop>
7698   : Pat<(ResTy (op
7699           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7700           (HalfOpTy (Neon_vduplane
7701                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7702         (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7703
7704 // Pattern for lane in 64-bit vector
7705 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7706                         RegisterOperand EleOpVPR, ValueType ResTy,
7707                         ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7708                         SDPatternOperator hiop>
7709   : Pat<(ResTy (op
7710           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7711           (HalfOpTy (Neon_vduplane
7712                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7713         (INST VPR128:$Rn,
7714           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7715
7716 // Pattern for fixed lane 0
7717 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7718                          ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7719                          SDPatternOperator hiop, Instruction DupInst>
7720   : Pat<(ResTy (op
7721           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7722           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7723         (INST VPR128:$Rn, (DupInst $Re), 0)>;
7724
7725 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7726   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7727                          op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7728
7729   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7730                          op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7731
7732   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7733                          op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7734
7735   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7736                            op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7737
7738   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7739                            op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7740
7741   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7742                            op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7743
7744   // Index can only be half of the max value for lane in 64-bit vector
7745
7746   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7747                         op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7748
7749   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7750                         op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7751
7752   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7753                           op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7754
7755   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7756                           op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7757 }
7758
7759 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7760 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7761 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7762
7763 multiclass NI_qdma<SDPatternOperator op> {
7764   def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7765                     (op node:$Ra,
7766                       (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7767
7768   def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7769                     (op node:$Ra,
7770                       (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7771 }
7772
7773 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7774 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7775
7776 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7777   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7778                      !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7779                      v4i32, v4i16, v8i16>;
7780
7781   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7782                      !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7783                      v2i64, v2i32, v4i32>;
7784
7785   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7786                        !cast<PatFrag>(op # "_4s"), VPR128Lo,
7787                        v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7788
7789   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7790                        !cast<PatFrag>(op # "_2d"), VPR128,
7791                        v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7792
7793   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7794                        !cast<PatFrag>(op # "_4s"),
7795                        v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7796
7797   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7798                        !cast<PatFrag>(op # "_2d"),
7799                        v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7800
7801   // Index can only be half of the max value for lane in 64-bit vector
7802
7803   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7804                     !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7805                     v4i32, v4i16, v4i16>;
7806
7807   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7808                     !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7809                     v2i64, v2i32, v2i32>;
7810
7811   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7812                       !cast<PatFrag>(op # "_4s"), VPR64Lo,
7813                       v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7814
7815   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7816                       !cast<PatFrag>(op # "_2d"), VPR64,
7817                       v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7818 }
7819
7820 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7821 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7822
7823 // End of implementation for instruction class (3V Elem)
7824
7825 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7826                 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7827                 SDPatternOperator Neon_Rev>
7828   : NeonI_2VMisc<Q, U, size, opcode,
7829                (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7830                asmop # "\t$Rd." # Res # ", $Rn." # Res,
7831                [(set (ResTy ResVPR:$Rd),
7832                   (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7833                NoItinerary> ;
7834
7835 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7836                           v16i8, Neon_rev64>;
7837 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7838                          v8i16, Neon_rev64>;
7839 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7840                          v4i32, Neon_rev64>;
7841 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7842                          v8i8, Neon_rev64>;
7843 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7844                          v4i16, Neon_rev64>;
7845 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7846                          v2i32, Neon_rev64>;
7847
7848 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7849 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7850
7851 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7852                           v16i8, Neon_rev32>;
7853 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7854                           v8i16, Neon_rev32>;
7855 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7856                          v8i8, Neon_rev32>;
7857 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7858                          v4i16, Neon_rev32>;
7859
7860 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7861                           v16i8, Neon_rev16>;
7862 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7863                          v8i8, Neon_rev16>;
7864
7865 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7866                              SDPatternOperator Neon_Padd> {
7867   def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7868                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7869                            asmop # "\t$Rd.8h, $Rn.16b",
7870                            [(set (v8i16 VPR128:$Rd),
7871                               (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7872                            NoItinerary>;
7873
7874   def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7875                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7876                           asmop # "\t$Rd.4h, $Rn.8b",
7877                           [(set (v4i16 VPR64:$Rd),
7878                              (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7879                           NoItinerary>;
7880
7881   def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7882                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7883                            asmop # "\t$Rd.4s, $Rn.8h",
7884                            [(set (v4i32 VPR128:$Rd),
7885                               (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7886                            NoItinerary>;
7887
7888   def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7889                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7890                           asmop # "\t$Rd.2s, $Rn.4h",
7891                           [(set (v2i32 VPR64:$Rd),
7892                              (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7893                           NoItinerary>;
7894
7895   def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7896                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7897                            asmop # "\t$Rd.2d, $Rn.4s",
7898                            [(set (v2i64 VPR128:$Rd),
7899                               (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7900                            NoItinerary>;
7901
7902   def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7903                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7904                           asmop # "\t$Rd.1d, $Rn.2s",
7905                           [(set (v1i64 VPR64:$Rd),
7906                              (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7907                           NoItinerary>;
7908 }
7909
7910 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7911                                 int_arm_neon_vpaddls>;
7912 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7913                                 int_arm_neon_vpaddlu>;
7914
7915 def : Pat<(v1i64 (int_aarch64_neon_saddlv (v2i32 VPR64:$Rn))),
7916           (SADDLP2s1d $Rn)>;
7917 def : Pat<(v1i64 (int_aarch64_neon_uaddlv (v2i32 VPR64:$Rn))),
7918           (UADDLP2s1d $Rn)>;
7919
7920 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7921                              SDPatternOperator Neon_Padd> {
7922   let Constraints = "$src = $Rd" in {
7923     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7924                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7925                              asmop # "\t$Rd.8h, $Rn.16b",
7926                              [(set (v8i16 VPR128:$Rd),
7927                                 (v8i16 (Neon_Padd
7928                                   (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7929                              NoItinerary>;
7930
7931     def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7932                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7933                             asmop # "\t$Rd.4h, $Rn.8b",
7934                             [(set (v4i16 VPR64:$Rd),
7935                                (v4i16 (Neon_Padd
7936                                  (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7937                             NoItinerary>;
7938
7939     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7940                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7941                             asmop # "\t$Rd.4s, $Rn.8h",
7942                             [(set (v4i32 VPR128:$Rd),
7943                                (v4i32 (Neon_Padd
7944                                  (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7945                             NoItinerary>;
7946
7947     def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7948                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7949                             asmop # "\t$Rd.2s, $Rn.4h",
7950                             [(set (v2i32 VPR64:$Rd),
7951                                (v2i32 (Neon_Padd
7952                                  (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7953                             NoItinerary>;
7954
7955     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7956                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7957                             asmop # "\t$Rd.2d, $Rn.4s",
7958                             [(set (v2i64 VPR128:$Rd),
7959                                (v2i64 (Neon_Padd
7960                                  (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7961                             NoItinerary>;
7962
7963     def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7964                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7965                             asmop # "\t$Rd.1d, $Rn.2s",
7966                             [(set (v1i64 VPR64:$Rd),
7967                                (v1i64 (Neon_Padd
7968                                  (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7969                             NoItinerary>;
7970   }
7971 }
7972
7973 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7974                                    int_arm_neon_vpadals>;
7975 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7976                                    int_arm_neon_vpadalu>;
7977
7978 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7979   def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7980                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7981                          asmop # "\t$Rd.16b, $Rn.16b",
7982                          [], NoItinerary>;
7983
7984   def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7985                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7986                         asmop # "\t$Rd.8h, $Rn.8h",
7987                         [], NoItinerary>;
7988
7989   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7990                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7991                         asmop # "\t$Rd.4s, $Rn.4s",
7992                         [], NoItinerary>;
7993
7994   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7995                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7996                         asmop # "\t$Rd.2d, $Rn.2d",
7997                         [], NoItinerary>;
7998
7999   def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8000                          (outs VPR64:$Rd), (ins VPR64:$Rn),
8001                          asmop # "\t$Rd.8b, $Rn.8b",
8002                          [], NoItinerary>;
8003
8004   def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8005                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8006                         asmop # "\t$Rd.4h, $Rn.4h",
8007                         [], NoItinerary>;
8008
8009   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8010                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8011                         asmop # "\t$Rd.2s, $Rn.2s",
8012                         [], NoItinerary>;
8013 }
8014
8015 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
8016 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
8017 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
8018 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
8019
8020 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
8021                                           SDPatternOperator Neon_Op> {
8022   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
8023             (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
8024
8025   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
8026             (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
8027
8028   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
8029             (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
8030
8031   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
8032             (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
8033
8034   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
8035             (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
8036
8037   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
8038             (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
8039
8040   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
8041             (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
8042 }
8043
8044 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
8045 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
8046 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
8047
8048 def : Pat<(v16i8 (sub
8049             (v16i8 Neon_AllZero),
8050             (v16i8 VPR128:$Rn))),
8051           (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
8052 def : Pat<(v8i8 (sub
8053             (v8i8 Neon_AllZero),
8054             (v8i8 VPR64:$Rn))),
8055           (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
8056 def : Pat<(v8i16 (sub
8057             (v8i16 (bitconvert (v16i8 Neon_AllZero))),
8058             (v8i16 VPR128:$Rn))),
8059           (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
8060 def : Pat<(v4i16 (sub
8061             (v4i16 (bitconvert (v8i8 Neon_AllZero))),
8062             (v4i16 VPR64:$Rn))),
8063           (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
8064 def : Pat<(v4i32 (sub
8065             (v4i32 (bitconvert (v16i8 Neon_AllZero))),
8066             (v4i32 VPR128:$Rn))),
8067           (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
8068 def : Pat<(v2i32 (sub
8069             (v2i32 (bitconvert (v8i8 Neon_AllZero))),
8070             (v2i32 VPR64:$Rn))),
8071           (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
8072 def : Pat<(v2i64 (sub
8073             (v2i64 (bitconvert (v16i8 Neon_AllZero))),
8074             (v2i64 VPR128:$Rn))),
8075           (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
8076
8077 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
8078   let Constraints = "$src = $Rd" in {
8079     def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8080                            (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8081                            asmop # "\t$Rd.16b, $Rn.16b",
8082                            [], NoItinerary>;
8083
8084     def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8085                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8086                           asmop # "\t$Rd.8h, $Rn.8h",
8087                           [], NoItinerary>;
8088
8089     def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8090                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8091                           asmop # "\t$Rd.4s, $Rn.4s",
8092                           [], NoItinerary>;
8093
8094     def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8095                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8096                           asmop # "\t$Rd.2d, $Rn.2d",
8097                           [], NoItinerary>;
8098
8099     def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8100                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8101                           asmop # "\t$Rd.8b, $Rn.8b",
8102                           [], NoItinerary>;
8103
8104     def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8105                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8106                           asmop # "\t$Rd.4h, $Rn.4h",
8107                           [], NoItinerary>;
8108
8109     def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8110                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8111                           asmop # "\t$Rd.2s, $Rn.2s",
8112                           [], NoItinerary>;
8113   }
8114 }
8115
8116 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
8117 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
8118
8119 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
8120                                            SDPatternOperator Neon_Op> {
8121   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
8122             (v16i8 (!cast<Instruction>(Prefix # 16b)
8123               (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
8124
8125   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
8126             (v8i16 (!cast<Instruction>(Prefix # 8h)
8127               (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
8128
8129   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
8130             (v4i32 (!cast<Instruction>(Prefix # 4s)
8131               (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
8132
8133   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
8134             (v2i64 (!cast<Instruction>(Prefix # 2d)
8135               (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
8136
8137   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
8138             (v8i8 (!cast<Instruction>(Prefix # 8b)
8139               (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
8140
8141   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
8142             (v4i16 (!cast<Instruction>(Prefix # 4h)
8143               (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
8144
8145   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
8146             (v2i32 (!cast<Instruction>(Prefix # 2s)
8147               (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
8148 }
8149
8150 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
8151 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
8152
8153 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
8154                           SDPatternOperator Neon_Op> {
8155   def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
8156                          (outs VPR128:$Rd), (ins VPR128:$Rn),
8157                          asmop # "\t$Rd.16b, $Rn.16b",
8158                          [(set (v16i8 VPR128:$Rd),
8159                             (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
8160                          NoItinerary>;
8161
8162   def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
8163                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8164                         asmop # "\t$Rd.8h, $Rn.8h",
8165                         [(set (v8i16 VPR128:$Rd),
8166                            (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
8167                         NoItinerary>;
8168
8169   def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
8170                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8171                         asmop # "\t$Rd.4s, $Rn.4s",
8172                         [(set (v4i32 VPR128:$Rd),
8173                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8174                         NoItinerary>;
8175
8176   def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
8177                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8178                         asmop # "\t$Rd.8b, $Rn.8b",
8179                         [(set (v8i8 VPR64:$Rd),
8180                            (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
8181                         NoItinerary>;
8182
8183   def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
8184                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8185                         asmop # "\t$Rd.4h, $Rn.4h",
8186                         [(set (v4i16 VPR64:$Rd),
8187                            (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
8188                         NoItinerary>;
8189
8190   def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
8191                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8192                         asmop # "\t$Rd.2s, $Rn.2s",
8193                         [(set (v2i32 VPR64:$Rd),
8194                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8195                         NoItinerary>;
8196 }
8197
8198 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
8199 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
8200
8201 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
8202                               bits<5> Opcode> {
8203   def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
8204                          (outs VPR128:$Rd), (ins VPR128:$Rn),
8205                          asmop # "\t$Rd.16b, $Rn.16b",
8206                          [], NoItinerary>;
8207
8208   def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
8209                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8210                         asmop # "\t$Rd.8b, $Rn.8b",
8211                         [], NoItinerary>;
8212 }
8213
8214 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
8215 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
8216 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
8217
8218 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
8219                     (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
8220 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
8221                     (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
8222
8223 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
8224           (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
8225 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
8226           (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
8227
8228 def : Pat<(v16i8 (xor
8229             (v16i8 VPR128:$Rn),
8230             (v16i8 Neon_AllOne))),
8231           (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
8232 def : Pat<(v8i8 (xor
8233             (v8i8 VPR64:$Rn),
8234             (v8i8 Neon_AllOne))),
8235           (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
8236 def : Pat<(v8i16 (xor
8237             (v8i16 VPR128:$Rn),
8238             (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
8239           (NOT16b VPR128:$Rn)>;
8240 def : Pat<(v4i16 (xor
8241             (v4i16 VPR64:$Rn),
8242             (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
8243           (NOT8b VPR64:$Rn)>;
8244 def : Pat<(v4i32 (xor
8245             (v4i32 VPR128:$Rn),
8246             (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
8247           (NOT16b VPR128:$Rn)>;
8248 def : Pat<(v2i32 (xor
8249             (v2i32 VPR64:$Rn),
8250             (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
8251           (NOT8b VPR64:$Rn)>;
8252 def : Pat<(v2i64 (xor
8253             (v2i64 VPR128:$Rn),
8254             (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
8255           (NOT16b VPR128:$Rn)>;
8256
8257 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
8258           (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
8259 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
8260           (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
8261
8262 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
8263                                 SDPatternOperator Neon_Op> {
8264   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8265                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8266                         asmop # "\t$Rd.4s, $Rn.4s",
8267                         [(set (v4f32 VPR128:$Rd),
8268                            (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
8269                         NoItinerary>;
8270
8271   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8272                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8273                         asmop # "\t$Rd.2d, $Rn.2d",
8274                         [(set (v2f64 VPR128:$Rd),
8275                            (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
8276                         NoItinerary>;
8277
8278   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8279                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8280                         asmop # "\t$Rd.2s, $Rn.2s",
8281                         [(set (v2f32 VPR64:$Rd),
8282                            (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
8283                         NoItinerary>;
8284 }
8285
8286 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
8287 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
8288
8289 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
8290   def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8291                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8292                           asmop # "\t$Rd.8b, $Rn.8h",
8293                           [], NoItinerary>;
8294
8295   def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8296                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8297                           asmop # "\t$Rd.4h, $Rn.4s",
8298                           [], NoItinerary>;
8299
8300   def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8301                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8302                           asmop # "\t$Rd.2s, $Rn.2d",
8303                           [], NoItinerary>;
8304
8305   let Constraints = "$Rd = $src" in {
8306     def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8307                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8308                              asmop # "2\t$Rd.16b, $Rn.8h",
8309                              [], NoItinerary>;
8310
8311     def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8312                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8313                             asmop # "2\t$Rd.8h, $Rn.4s",
8314                             [], NoItinerary>;
8315
8316     def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8317                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8318                             asmop # "2\t$Rd.4s, $Rn.2d",
8319                             [], NoItinerary>;
8320   }
8321 }
8322
8323 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
8324 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
8325 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
8326 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
8327
8328 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
8329                                         SDPatternOperator Neon_Op> {
8330   def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8331             (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8332
8333   def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8334             (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8335
8336   def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8337             (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8338
8339   def : Pat<(v16i8 (concat_vectors
8340               (v8i8 VPR64:$src),
8341               (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8342             (!cast<Instruction>(Prefix # 8h16b)
8343               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8344               VPR128:$Rn)>;
8345
8346   def : Pat<(v8i16 (concat_vectors
8347               (v4i16 VPR64:$src),
8348               (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8349             (!cast<Instruction>(Prefix # 4s8h)
8350               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8351               VPR128:$Rn)>;
8352
8353   def : Pat<(v4i32 (concat_vectors
8354               (v2i32 VPR64:$src),
8355               (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8356             (!cast<Instruction>(Prefix # 2d4s)
8357               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8358               VPR128:$Rn)>;
8359 }
8360
8361 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8362 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8363 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8364 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8365
8366 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8367   let DecoderMethod = "DecodeSHLLInstruction" in {
8368     def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8369                             (outs VPR128:$Rd),
8370                             (ins VPR64:$Rn, uimm_exact8:$Imm),
8371                             asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8372                             [], NoItinerary>;
8373
8374     def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8375                             (outs VPR128:$Rd),
8376                             (ins VPR64:$Rn, uimm_exact16:$Imm),
8377                             asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8378                             [], NoItinerary>;
8379
8380     def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8381                             (outs VPR128:$Rd),
8382                             (ins VPR64:$Rn, uimm_exact32:$Imm),
8383                             asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8384                             [], NoItinerary>;
8385
8386     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8387                             (outs VPR128:$Rd),
8388                             (ins VPR128:$Rn, uimm_exact8:$Imm),
8389                             asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8390                             [], NoItinerary>;
8391
8392     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8393                             (outs VPR128:$Rd),
8394                             (ins VPR128:$Rn, uimm_exact16:$Imm),
8395                             asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8396                             [], NoItinerary>;
8397
8398     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8399                             (outs VPR128:$Rd),
8400                             (ins VPR128:$Rn, uimm_exact32:$Imm),
8401                             asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8402                             [], NoItinerary>;
8403   }
8404 }
8405
8406 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8407
8408 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8409                           SDPatternOperator ExtOp, Operand Neon_Imm,
8410                           string suffix>
8411   : Pat<(DesTy (shl
8412           (DesTy (ExtOp (OpTy VPR64:$Rn))),
8413             (DesTy (Neon_vdup
8414               (i32 Neon_Imm:$Imm))))),
8415         (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8416
8417 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8418                                SDPatternOperator ExtOp, Operand Neon_Imm,
8419                                string suffix, PatFrag GetHigh>
8420   : Pat<(DesTy (shl
8421           (DesTy (ExtOp
8422             (OpTy (GetHigh VPR128:$Rn)))),
8423               (DesTy (Neon_vdup
8424                 (i32 Neon_Imm:$Imm))))),
8425         (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8426
8427 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8428 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8429 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8430 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8431 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8432 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8433 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8434                                Neon_High16B>;
8435 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8436                                Neon_High16B>;
8437 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8438                                Neon_High8H>;
8439 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8440                                Neon_High8H>;
8441 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8442                                Neon_High4S>;
8443 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8444                                Neon_High4S>;
8445
8446 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8447   def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8448                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8449                           asmop # "\t$Rd.4h, $Rn.4s",
8450                           [], NoItinerary>;
8451
8452   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8453                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8454                           asmop # "\t$Rd.2s, $Rn.2d",
8455                           [], NoItinerary>;
8456
8457   let Constraints = "$src = $Rd" in {
8458     def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8459                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8460                             asmop # "2\t$Rd.8h, $Rn.4s",
8461                             [], NoItinerary>;
8462
8463     def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8464                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8465                             asmop # "2\t$Rd.4s, $Rn.2d",
8466                             [], NoItinerary>;
8467   }
8468 }
8469
8470 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8471
8472 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8473                                        SDPatternOperator f32_to_f16_Op,
8474                                        SDPatternOperator f64_to_f32_Op> {
8475
8476   def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8477               (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8478
8479   def : Pat<(v8i16 (concat_vectors
8480                 (v4i16 VPR64:$src),
8481                 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8482                   (!cast<Instruction>(prefix # "4s8h")
8483                     (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8484                     (v4f32 VPR128:$Rn))>;
8485
8486   def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8487             (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8488
8489   def : Pat<(v4f32 (concat_vectors
8490               (v2f32 VPR64:$src),
8491               (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8492                 (!cast<Instruction>(prefix # "2d4s")
8493                   (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8494                   (v2f64 VPR128:$Rn))>;
8495 }
8496
8497 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8498
8499 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8500                                  bits<5> opcode> {
8501   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8502                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8503                           asmop # "\t$Rd.2s, $Rn.2d",
8504                           [], NoItinerary>;
8505
8506   def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8507                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8508                           asmop # "2\t$Rd.4s, $Rn.2d",
8509                           [], NoItinerary> {
8510     let Constraints = "$src = $Rd";
8511   }
8512
8513   def : Pat<(v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))),
8514             (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8515
8516   def : Pat<(v4f32 (concat_vectors
8517               (v2f32 VPR64:$src),
8518               (v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))))),
8519             (!cast<Instruction>(prefix # "2d4s")
8520                (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8521                VPR128:$Rn)>;
8522 }
8523
8524 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8525
8526 def Neon_High4Float : PatFrag<(ops node:$in),
8527                               (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8528
8529 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8530   def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8531                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8532                           asmop # "\t$Rd.4s, $Rn.4h",
8533                           [], NoItinerary>;
8534
8535   def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8536                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8537                           asmop # "\t$Rd.2d, $Rn.2s",
8538                           [], NoItinerary>;
8539
8540   def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8541                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8542                           asmop # "2\t$Rd.4s, $Rn.8h",
8543                           [], NoItinerary>;
8544
8545   def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8546                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8547                           asmop # "2\t$Rd.2d, $Rn.4s",
8548                           [], NoItinerary>;
8549 }
8550
8551 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8552
8553 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8554   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8555             (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8556
8557   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8558               (v4i16 (Neon_High8H
8559                 (v8i16 VPR128:$Rn))))),
8560             (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8561
8562   def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8563             (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8564
8565   def : Pat<(v2f64 (fextend
8566               (v2f32 (Neon_High4Float
8567                 (v4f32 VPR128:$Rn))))),
8568             (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8569 }
8570
8571 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8572
8573 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8574                                 ValueType ResTy4s, ValueType OpTy4s,
8575                                 ValueType ResTy2d, ValueType OpTy2d,
8576                                 ValueType ResTy2s, ValueType OpTy2s,
8577                                 SDPatternOperator Neon_Op> {
8578
8579   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8580                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8581                         asmop # "\t$Rd.4s, $Rn.4s",
8582                         [(set (ResTy4s VPR128:$Rd),
8583                            (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8584                         NoItinerary>;
8585
8586   def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8587                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8588                         asmop # "\t$Rd.2d, $Rn.2d",
8589                         [(set (ResTy2d VPR128:$Rd),
8590                            (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8591                         NoItinerary>;
8592
8593   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8594                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8595                         asmop # "\t$Rd.2s, $Rn.2s",
8596                         [(set (ResTy2s VPR64:$Rd),
8597                            (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8598                         NoItinerary>;
8599 }
8600
8601 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8602                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8603   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8604                                 v2f64, v2i32, v2f32, Neon_Op>;
8605 }
8606
8607 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8608                                      int_arm_neon_vcvtns>;
8609 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8610                                      int_arm_neon_vcvtnu>;
8611 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8612                                      int_arm_neon_vcvtps>;
8613 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8614                                      int_arm_neon_vcvtpu>;
8615 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8616                                      int_arm_neon_vcvtms>;
8617 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8618                                      int_arm_neon_vcvtmu>;
8619 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8620 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8621 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8622                                      int_arm_neon_vcvtas>;
8623 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8624                                      int_arm_neon_vcvtau>;
8625
8626 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8627                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8628   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8629                                 v2i64, v2f32, v2i32, Neon_Op>;
8630 }
8631
8632 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8633 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8634
8635 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8636                                  bits<5> opcode, SDPatternOperator Neon_Op> {
8637   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8638                                 v2f64, v2f32, v2f32, Neon_Op>;
8639 }
8640
8641 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8642                                      int_aarch64_neon_frintn>;
8643 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8644 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8645 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8646 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8647 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8648 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8649 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8650                                     int_arm_neon_vrecpe>;
8651 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8652                                      int_arm_neon_vrsqrte>;
8653 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
8654
8655 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8656                                bits<5> opcode, SDPatternOperator Neon_Op> {
8657   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8658                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8659                         asmop # "\t$Rd.4s, $Rn.4s",
8660                         [(set (v4i32 VPR128:$Rd),
8661                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8662                         NoItinerary>;
8663
8664   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8665                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8666                         asmop # "\t$Rd.2s, $Rn.2s",
8667                         [(set (v2i32 VPR64:$Rd),
8668                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8669                         NoItinerary>;
8670 }
8671
8672 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8673                                   int_arm_neon_vrecpe>;
8674 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8675                                    int_arm_neon_vrsqrte>;
8676
8677 // Crypto Class
8678 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8679                          string asmop, SDPatternOperator opnode>
8680   : NeonI_Crypto_AES<size, opcode,
8681                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8682                      asmop # "\t$Rd.16b, $Rn.16b",
8683                      [(set (v16i8 VPR128:$Rd),
8684                         (v16i8 (opnode (v16i8 VPR128:$src),
8685                                        (v16i8 VPR128:$Rn))))],
8686                      NoItinerary>{
8687   let Constraints = "$src = $Rd";
8688   let Predicates = [HasNEON, HasCrypto];
8689 }
8690
8691 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8692 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8693
8694 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8695                       string asmop, SDPatternOperator opnode>
8696   : NeonI_Crypto_AES<size, opcode,
8697                      (outs VPR128:$Rd), (ins VPR128:$Rn),
8698                      asmop # "\t$Rd.16b, $Rn.16b",
8699                      [(set (v16i8 VPR128:$Rd),
8700                         (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8701                      NoItinerary>;
8702
8703 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8704 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8705
8706 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8707                          string asmop, SDPatternOperator opnode>
8708   : NeonI_Crypto_SHA<size, opcode,
8709                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8710                      asmop # "\t$Rd.4s, $Rn.4s",
8711                      [(set (v4i32 VPR128:$Rd),
8712                         (v4i32 (opnode (v4i32 VPR128:$src),
8713                                        (v4i32 VPR128:$Rn))))],
8714                      NoItinerary> {
8715   let Constraints = "$src = $Rd";
8716   let Predicates = [HasNEON, HasCrypto];
8717 }
8718
8719 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8720                                  int_arm_neon_sha1su1>;
8721 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8722                                    int_arm_neon_sha256su0>;
8723
8724 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8725                          string asmop, SDPatternOperator opnode>
8726   : NeonI_Crypto_SHA<size, opcode,
8727                      (outs FPR32:$Rd), (ins FPR32:$Rn),
8728                      asmop # "\t$Rd, $Rn",
8729                      [(set (v1i32 FPR32:$Rd),
8730                         (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8731                      NoItinerary> {
8732   let Predicates = [HasNEON, HasCrypto];
8733 }
8734
8735 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8736
8737 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8738                            SDPatternOperator opnode>
8739   : NeonI_Crypto_3VSHA<size, opcode,
8740                        (outs VPR128:$Rd),
8741                        (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8742                        asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8743                        [(set (v4i32 VPR128:$Rd),
8744                           (v4i32 (opnode (v4i32 VPR128:$src),
8745                                          (v4i32 VPR128:$Rn),
8746                                          (v4i32 VPR128:$Rm))))],
8747                        NoItinerary> {
8748   let Constraints = "$src = $Rd";
8749   let Predicates = [HasNEON, HasCrypto];
8750 }
8751
8752 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8753                                    int_arm_neon_sha1su0>;
8754 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8755                                      int_arm_neon_sha256su1>;
8756
8757 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8758                            SDPatternOperator opnode>
8759   : NeonI_Crypto_3VSHA<size, opcode,
8760                        (outs FPR128:$Rd),
8761                        (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8762                        asmop # "\t$Rd, $Rn, $Rm.4s",
8763                        [(set (v4i32 FPR128:$Rd),
8764                           (v4i32 (opnode (v4i32 FPR128:$src),
8765                                          (v4i32 FPR128:$Rn),
8766                                          (v4i32 VPR128:$Rm))))],
8767                        NoItinerary> {
8768   let Constraints = "$src = $Rd";
8769   let Predicates = [HasNEON, HasCrypto];
8770 }
8771
8772 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8773                                    int_arm_neon_sha256h>;
8774 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8775                                     int_arm_neon_sha256h2>;
8776
8777 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8778                            SDPatternOperator opnode>
8779   : NeonI_Crypto_3VSHA<size, opcode,
8780                        (outs FPR128:$Rd),
8781                        (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8782                        asmop # "\t$Rd, $Rn, $Rm.4s",
8783                        [(set (v4i32 FPR128:$Rd),
8784                           (v4i32 (opnode (v4i32 FPR128:$src),
8785                                          (v1i32 FPR32:$Rn),
8786                                          (v4i32 VPR128:$Rm))))],
8787                        NoItinerary> {
8788   let Constraints = "$src = $Rd";
8789   let Predicates = [HasNEON, HasCrypto];
8790 }
8791
8792 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8793 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8794 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8795
8796 // Additional patterns to match shl to USHL.
8797 def : Pat<(v8i8 (shl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8798           (USHLvvv_8B $Rn, $Rm)>;
8799 def : Pat<(v4i16 (shl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8800           (USHLvvv_4H $Rn, $Rm)>;
8801 def : Pat<(v2i32 (shl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8802           (USHLvvv_2S $Rn, $Rm)>;
8803 def : Pat<(v1i64 (shl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8804           (USHLddd $Rn, $Rm)>;
8805 def : Pat<(v16i8 (shl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8806           (USHLvvv_16B $Rn, $Rm)>;
8807 def : Pat<(v8i16 (shl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8808           (USHLvvv_8H $Rn, $Rm)>;
8809 def : Pat<(v4i32 (shl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8810           (USHLvvv_4S $Rn, $Rm)>;
8811 def : Pat<(v2i64 (shl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8812           (USHLvvv_2D $Rn, $Rm)>;
8813
8814 // Additional patterns to match sra, srl.
8815 // For a vector right shift by vector, the shift amounts of SSHL/USHL are
8816 // negative. Negate the vector of shift amount first.
8817 def : Pat<(v8i8 (srl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8818           (USHLvvv_8B $Rn, (NEG8b $Rm))>;
8819 def : Pat<(v4i16 (srl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8820           (USHLvvv_4H $Rn, (NEG4h $Rm))>;
8821 def : Pat<(v2i32 (srl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8822           (USHLvvv_2S $Rn, (NEG2s $Rm))>;
8823 def : Pat<(v1i64 (srl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8824           (USHLddd $Rn, (NEGdd $Rm))>;
8825 def : Pat<(v16i8 (srl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8826           (USHLvvv_16B $Rn, (NEG16b $Rm))>;
8827 def : Pat<(v8i16 (srl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8828           (USHLvvv_8H $Rn, (NEG8h $Rm))>;
8829 def : Pat<(v4i32 (srl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8830           (USHLvvv_4S $Rn, (NEG4s $Rm))>;
8831 def : Pat<(v2i64 (srl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8832           (USHLvvv_2D $Rn, (NEG2d $Rm))>;
8833
8834 def : Pat<(v8i8 (sra (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8835           (SSHLvvv_8B $Rn, (NEG8b $Rm))>;
8836 def : Pat<(v4i16 (sra (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8837           (SSHLvvv_4H $Rn, (NEG4h $Rm))>;
8838 def : Pat<(v2i32 (sra (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8839           (SSHLvvv_2S $Rn, (NEG2s $Rm))>;
8840 def : Pat<(v1i64 (sra (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8841           (SSHLddd $Rn, (NEGdd $Rm))>;
8842 def : Pat<(v16i8 (sra (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8843           (SSHLvvv_16B $Rn, (NEG16b $Rm))>;
8844 def : Pat<(v8i16 (sra (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8845           (SSHLvvv_8H $Rn, (NEG8h $Rm))>;
8846 def : Pat<(v4i32 (sra (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8847           (SSHLvvv_4S $Rn, (NEG4s $Rm))>;
8848 def : Pat<(v2i64 (sra (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8849           (SSHLvvv_2D $Rn, (NEG2d $Rm))>;
8850
8851 //
8852 // Patterns for handling half-precision values
8853 //
8854
8855 // Convert between f16 value and f32 value
8856 def : Pat<(f32 (f16_to_f32 (i32 GPR32:$Rn))),
8857           (FCVTsh (EXTRACT_SUBREG (FMOVsw $Rn), sub_16))>;
8858 def : Pat<(i32 (f32_to_f16 (f32 FPR32:$Rn))),
8859           (FMOVws (SUBREG_TO_REG (i64 0), (f16 (FCVThs $Rn)), sub_16))>;
8860
8861 // Convert f16 value coming in as i16 value to f32
8862 def : Pat<(f32 (f16_to_f32 (i32 (and (i32 GPR32:$Rn), 65535)))),
8863           (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8864 def : Pat<(f32 (f16_to_f32 (i32 (assertzext GPR32:$Rn)))),
8865           (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8866
8867 def : Pat<(f32 (f16_to_f32 (i32 (assertzext (i32 (
8868             f32_to_f16 (f32 FPR32:$Rn))))))),
8869           (f32 FPR32:$Rn)>;
8870
8871 // Patterns for vector extract of half-precision FP value in i16 storage type
8872 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8873             (v4i16 VPR64:$Rn), neon_uimm2_bare:$Imm)), 65535)))),
8874           (FCVTsh (f16 (DUPhv_H
8875             (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8876             neon_uimm2_bare:$Imm)))>;
8877
8878 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8879             (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)), 65535)))),
8880           (FCVTsh (f16 (DUPhv_H (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)))>;
8881
8882 // Patterns for vector insert of half-precision FP value 0 in i16 storage type
8883 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8884             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8885             (neon_uimm3_bare:$Imm))),
8886           (v8i16 (INSELh (v8i16 VPR128:$Rn),
8887             (v8i16 (SUBREG_TO_REG (i64 0),
8888               (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8889               sub_16)),
8890             neon_uimm3_bare:$Imm, 0))>;
8891
8892 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8893             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8894             (neon_uimm2_bare:$Imm))),
8895           (v4i16 (EXTRACT_SUBREG
8896             (v8i16 (INSELh
8897               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8898               (v8i16 (SUBREG_TO_REG (i64 0),
8899                 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8900                 sub_16)),
8901               neon_uimm2_bare:$Imm, 0)),
8902             sub_64))>;
8903
8904 // Patterns for vector insert of half-precision FP value in i16 storage type
8905 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8906             (i32 (assertsext (i32 (fp_to_sint
8907               (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8908             (neon_uimm3_bare:$Imm))),
8909           (v8i16 (INSELh (v8i16 VPR128:$Rn),
8910             (v8i16 (SUBREG_TO_REG (i64 0),
8911               (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8912               sub_16)),
8913             neon_uimm3_bare:$Imm, 0))>;
8914
8915 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8916             (i32 (assertsext (i32 (fp_to_sint
8917               (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8918             (neon_uimm2_bare:$Imm))),
8919           (v4i16 (EXTRACT_SUBREG
8920             (v8i16 (INSELh
8921               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8922               (v8i16 (SUBREG_TO_REG (i64 0),
8923                 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8924                 sub_16)),
8925               neon_uimm2_bare:$Imm, 0)),
8926             sub_64))>;
8927
8928 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8929             (i32 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8930               (neon_uimm3_bare:$Imm1))),
8931           (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8932             neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8933
8934 // Patterns for vector copy of half-precision FP value in i16 storage type
8935 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8936             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8937               (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8938               65535)))))))),
8939             (neon_uimm3_bare:$Imm1))),
8940           (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8941             neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8942
8943 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8944             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8945               (vector_extract (v4i16 VPR64:$src), neon_uimm3_bare:$Imm2)),
8946               65535)))))))),
8947             (neon_uimm3_bare:$Imm1))),
8948           (v4i16 (EXTRACT_SUBREG
8949             (v8i16 (INSELh
8950               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8951               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
8952               neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2)),
8953             sub_64))>;
8954
8955