1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
17 def Neon_bsl : SDNode<"AArch64ISD::NEON_BSL", SDTypeProfile<1, 3,
18 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
19 SDTCisSameAs<0, 3>]>>;
21 // (outs Result), (ins Imm, OpCmode)
22 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
24 def Neon_movi : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
26 def Neon_mvni : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
28 // (outs Result), (ins Imm)
29 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
30 [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
32 // (outs Result), (ins LHS, RHS, CondCode)
33 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
34 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
36 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
37 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
38 [SDTCisVec<0>, SDTCisVec<1>]>>;
40 // (outs Result), (ins LHS, RHS)
41 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
42 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
44 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
46 def Neon_sqrshlImm : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
47 def Neon_uqrshlImm : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
49 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
50 def Neon_rev64 : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
51 def Neon_rev32 : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
52 def Neon_rev16 : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
53 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
55 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
56 [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
57 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
58 [SDTCisVec<0>, SDTCisSameAs<0, 1>,
59 SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
61 //===----------------------------------------------------------------------===//
63 //===----------------------------------------------------------------------===//
65 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size, bits<5> opcode,
66 string asmop, SDPatternOperator opnode8B,
67 SDPatternOperator opnode16B,
69 let isCommutable = Commutable in {
70 def _8B : NeonI_3VSame<0b0, u, size, opcode,
71 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
72 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
73 [(set (v8i8 VPR64:$Rd),
74 (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
77 def _16B : NeonI_3VSame<0b1, u, size, opcode,
78 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
79 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
80 [(set (v16i8 VPR128:$Rd),
81 (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
87 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
88 string asmop, SDPatternOperator opnode,
90 let isCommutable = Commutable in {
91 def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
92 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
93 asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
94 [(set (v4i16 VPR64:$Rd),
95 (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
98 def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
99 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
100 asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
101 [(set (v8i16 VPR128:$Rd),
102 (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
105 def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
106 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
107 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
108 [(set (v2i32 VPR64:$Rd),
109 (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
112 def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
113 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
114 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
115 [(set (v4i32 VPR128:$Rd),
116 (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
120 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
121 string asmop, SDPatternOperator opnode,
123 : NeonI_3VSame_HS_sizes<u, opcode, asmop, opnode, Commutable> {
124 let isCommutable = Commutable in {
125 def _8B : NeonI_3VSame<0b0, u, 0b00, opcode,
126 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
127 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
128 [(set (v8i8 VPR64:$Rd),
129 (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
132 def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
133 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
134 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
135 [(set (v16i8 VPR128:$Rd),
136 (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
141 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
142 string asmop, SDPatternOperator opnode,
144 : NeonI_3VSame_BHS_sizes<u, opcode, asmop, opnode, Commutable> {
145 let isCommutable = Commutable in {
146 def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
147 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
148 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
149 [(set (v2i64 VPR128:$Rd),
150 (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
155 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
156 // but Result types can be integer or floating point types.
157 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
158 string asmop, SDPatternOperator opnode2S,
159 SDPatternOperator opnode4S,
160 SDPatternOperator opnode2D,
161 ValueType ResTy2S, ValueType ResTy4S,
162 ValueType ResTy2D, bit Commutable = 0> {
163 let isCommutable = Commutable in {
164 def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
165 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
166 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
167 [(set (ResTy2S VPR64:$Rd),
168 (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
171 def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
172 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
173 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
174 [(set (ResTy4S VPR128:$Rd),
175 (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
178 def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
179 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
180 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
181 [(set (ResTy2D VPR128:$Rd),
182 (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
187 //===----------------------------------------------------------------------===//
188 // Instruction Definitions
189 //===----------------------------------------------------------------------===//
191 // Vector Arithmetic Instructions
193 // Vector Add (Integer and Floating-Point)
195 defm ADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
196 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
197 v2f32, v4f32, v2f64, 1>;
199 // Vector Sub (Integer and Floating-Point)
201 defm SUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
202 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
203 v2f32, v4f32, v2f64, 0>;
205 // Vector Multiply (Integer and Floating-Point)
207 defm MULvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
208 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
209 v2f32, v4f32, v2f64, 1>;
211 // Vector Multiply (Polynomial)
213 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
214 int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
216 // Vector Multiply-accumulate and Multiply-subtract (Integer)
218 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
219 // two operands constraints.
220 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
221 RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
222 bits<5> opcode, SDPatternOperator opnode>
223 : NeonI_3VSame<q, u, size, opcode,
224 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
225 asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
226 [(set (OpTy VPRC:$Rd),
227 (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
229 let Constraints = "$src = $Rd";
232 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
233 (add node:$Ra, (mul node:$Rn, node:$Rm))>;
235 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
236 (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
239 def MLAvvv_8B: NeonI_3VSame_Constraint_impl<"mla", ".8b", VPR64, v8i8,
240 0b0, 0b0, 0b00, 0b10010, Neon_mla>;
241 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
242 0b1, 0b0, 0b00, 0b10010, Neon_mla>;
243 def MLAvvv_4H: NeonI_3VSame_Constraint_impl<"mla", ".4h", VPR64, v4i16,
244 0b0, 0b0, 0b01, 0b10010, Neon_mla>;
245 def MLAvvv_8H: NeonI_3VSame_Constraint_impl<"mla", ".8h", VPR128, v8i16,
246 0b1, 0b0, 0b01, 0b10010, Neon_mla>;
247 def MLAvvv_2S: NeonI_3VSame_Constraint_impl<"mla", ".2s", VPR64, v2i32,
248 0b0, 0b0, 0b10, 0b10010, Neon_mla>;
249 def MLAvvv_4S: NeonI_3VSame_Constraint_impl<"mla", ".4s", VPR128, v4i32,
250 0b1, 0b0, 0b10, 0b10010, Neon_mla>;
252 def MLSvvv_8B: NeonI_3VSame_Constraint_impl<"mls", ".8b", VPR64, v8i8,
253 0b0, 0b1, 0b00, 0b10010, Neon_mls>;
254 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
255 0b1, 0b1, 0b00, 0b10010, Neon_mls>;
256 def MLSvvv_4H: NeonI_3VSame_Constraint_impl<"mls", ".4h", VPR64, v4i16,
257 0b0, 0b1, 0b01, 0b10010, Neon_mls>;
258 def MLSvvv_8H: NeonI_3VSame_Constraint_impl<"mls", ".8h", VPR128, v8i16,
259 0b1, 0b1, 0b01, 0b10010, Neon_mls>;
260 def MLSvvv_2S: NeonI_3VSame_Constraint_impl<"mls", ".2s", VPR64, v2i32,
261 0b0, 0b1, 0b10, 0b10010, Neon_mls>;
262 def MLSvvv_4S: NeonI_3VSame_Constraint_impl<"mls", ".4s", VPR128, v4i32,
263 0b1, 0b1, 0b10, 0b10010, Neon_mls>;
265 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
267 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
268 (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
270 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
271 (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
273 let Predicates = [HasNEON, UseFusedMAC] in {
274 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s", VPR64, v2f32,
275 0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
276 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s", VPR128, v4f32,
277 0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
278 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d", VPR128, v2f64,
279 0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
281 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s", VPR64, v2f32,
282 0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
283 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s", VPR128, v4f32,
284 0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
285 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d", VPR128, v2f64,
286 0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
289 // We're also allowed to match the fma instruction regardless of compile
291 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
292 (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
293 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
294 (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
295 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
296 (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
298 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
299 (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
300 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
301 (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
302 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
303 (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
305 // Vector Divide (Floating-Point)
307 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
308 v2f32, v4f32, v2f64, 0>;
310 // Vector Bitwise Operations
312 // Vector Bitwise AND
314 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
316 // Vector Bitwise Exclusive OR
318 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
322 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
324 // ORR disassembled as MOV if Vn==Vm
326 // Vector Move - register
327 // Alias for ORR if Vn=Vm.
328 // FIXME: This is actually the preferred syntax but TableGen can't deal with
329 // custom printing of aliases.
330 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
331 (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
332 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
333 (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
335 // The MOVI instruction takes two immediate operands. The first is the
336 // immediate encoding, while the second is the cmode. A cmode of 14, or
337 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
338 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
339 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
341 def Neon_not8B : PatFrag<(ops node:$in),
342 (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
343 def Neon_not16B : PatFrag<(ops node:$in),
344 (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
346 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
347 (or node:$Rn, (Neon_not8B node:$Rm))>;
349 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
350 (or node:$Rn, (Neon_not16B node:$Rm))>;
352 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
353 (and node:$Rn, (Neon_not8B node:$Rm))>;
355 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
356 (and node:$Rn, (Neon_not16B node:$Rm))>;
359 // Vector Bitwise OR NOT - register
361 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
362 Neon_orn8B, Neon_orn16B, 0>;
364 // Vector Bitwise Bit Clear (AND NOT) - register
366 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
367 Neon_bic8B, Neon_bic16B, 0>;
369 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
370 SDPatternOperator opnode16B,
372 Instruction INST16B> {
373 def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
374 (INST8B VPR64:$Rn, VPR64:$Rm)>;
375 def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
376 (INST8B VPR64:$Rn, VPR64:$Rm)>;
377 def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
378 (INST8B VPR64:$Rn, VPR64:$Rm)>;
379 def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
380 (INST16B VPR128:$Rn, VPR128:$Rm)>;
381 def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
382 (INST16B VPR128:$Rn, VPR128:$Rm)>;
383 def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
384 (INST16B VPR128:$Rn, VPR128:$Rm)>;
387 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
388 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
389 defm : Neon_bitwise2V_patterns<or, or, ORRvvv_8B, ORRvvv_16B>;
390 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
391 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
392 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
394 // Vector Bitwise Select
395 def BSLvvv_8B : NeonI_3VSame_Constraint_impl<"bsl", ".8b", VPR64, v8i8,
396 0b0, 0b1, 0b01, 0b00011, Neon_bsl>;
398 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
399 0b1, 0b1, 0b01, 0b00011, Neon_bsl>;
401 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
403 Instruction INST16B> {
404 // Disassociate type from instruction definition
405 def : Pat<(v2i32 (opnode VPR64:$src,VPR64:$Rn, VPR64:$Rm)),
406 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
407 def : Pat<(v4i16 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
408 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
409 def : Pat<(v1i64 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
410 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
411 def : Pat<(v4i32 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
412 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
413 def : Pat<(v8i16 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
414 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
415 def : Pat<(v2i64 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
416 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
418 // Allow to match BSL instruction pattern with non-constant operand
419 def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
420 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
421 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
422 def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
423 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
424 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
425 def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
426 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
427 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
428 def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
429 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
430 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
431 def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
432 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
433 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
434 def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
435 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
436 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
437 def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
438 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
439 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
440 def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
441 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
442 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
444 // Allow to match llvm.arm.* intrinsics.
445 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
446 (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
447 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
448 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
449 (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
450 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
451 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
452 (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
453 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
454 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
455 (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
456 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
457 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
458 (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
459 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
460 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
461 (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
462 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
463 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
464 (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
465 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
466 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
467 (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
468 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
469 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
470 (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
471 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
472 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
473 (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
474 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
475 def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
476 (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
477 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
480 // Additional patterns for bitwise instruction BSL
481 defm: Neon_bitwise3V_patterns<Neon_bsl, BSLvvv_8B, BSLvvv_16B>;
483 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
484 (Neon_bsl node:$src, node:$Rn, node:$Rm),
485 [{ (void)N; return false; }]>;
487 // Vector Bitwise Insert if True
489 def BITvvv_8B : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64, v8i8,
490 0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
491 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
492 0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
494 // Vector Bitwise Insert if False
496 def BIFvvv_8B : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64, v8i8,
497 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
498 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
499 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
501 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
503 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
504 (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
505 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
506 (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
508 // Vector Absolute Difference and Accumulate (Unsigned)
509 def UABAvvv_8B : NeonI_3VSame_Constraint_impl<"uaba", ".8b", VPR64, v8i8,
510 0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
511 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
512 0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
513 def UABAvvv_4H : NeonI_3VSame_Constraint_impl<"uaba", ".4h", VPR64, v4i16,
514 0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
515 def UABAvvv_8H : NeonI_3VSame_Constraint_impl<"uaba", ".8h", VPR128, v8i16,
516 0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
517 def UABAvvv_2S : NeonI_3VSame_Constraint_impl<"uaba", ".2s", VPR64, v2i32,
518 0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
519 def UABAvvv_4S : NeonI_3VSame_Constraint_impl<"uaba", ".4s", VPR128, v4i32,
520 0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
522 // Vector Absolute Difference and Accumulate (Signed)
523 def SABAvvv_8B : NeonI_3VSame_Constraint_impl<"saba", ".8b", VPR64, v8i8,
524 0b0, 0b0, 0b00, 0b01111, Neon_saba>;
525 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
526 0b1, 0b0, 0b00, 0b01111, Neon_saba>;
527 def SABAvvv_4H : NeonI_3VSame_Constraint_impl<"saba", ".4h", VPR64, v4i16,
528 0b0, 0b0, 0b01, 0b01111, Neon_saba>;
529 def SABAvvv_8H : NeonI_3VSame_Constraint_impl<"saba", ".8h", VPR128, v8i16,
530 0b1, 0b0, 0b01, 0b01111, Neon_saba>;
531 def SABAvvv_2S : NeonI_3VSame_Constraint_impl<"saba", ".2s", VPR64, v2i32,
532 0b0, 0b0, 0b10, 0b01111, Neon_saba>;
533 def SABAvvv_4S : NeonI_3VSame_Constraint_impl<"saba", ".4s", VPR128, v4i32,
534 0b1, 0b0, 0b10, 0b01111, Neon_saba>;
537 // Vector Absolute Difference (Signed, Unsigned)
538 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
539 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
541 // Vector Absolute Difference (Floating Point)
542 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
543 int_arm_neon_vabds, int_arm_neon_vabds,
544 int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
546 // Vector Reciprocal Step (Floating Point)
547 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
548 int_arm_neon_vrecps, int_arm_neon_vrecps,
550 v2f32, v4f32, v2f64, 0>;
552 // Vector Reciprocal Square Root Step (Floating Point)
553 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
554 int_arm_neon_vrsqrts,
555 int_arm_neon_vrsqrts,
556 int_arm_neon_vrsqrts,
557 v2f32, v4f32, v2f64, 0>;
559 // Vector Comparisons
561 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
562 (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
563 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
564 (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
565 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
566 (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
567 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
568 (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
569 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
570 (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
572 // NeonI_compare_aliases class: swaps register operands to implement
573 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
574 class NeonI_compare_aliases<string asmop, string asmlane,
575 Instruction inst, RegisterOperand VPRC>
576 : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
578 (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
580 // Vector Comparisons (Integer)
582 // Vector Compare Mask Equal (Integer)
583 let isCommutable =1 in {
584 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
587 // Vector Compare Mask Higher or Same (Unsigned Integer)
588 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
590 // Vector Compare Mask Greater Than or Equal (Integer)
591 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
593 // Vector Compare Mask Higher (Unsigned Integer)
594 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
596 // Vector Compare Mask Greater Than (Integer)
597 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
599 // Vector Compare Mask Bitwise Test (Integer)
600 defm CMTSTvvv: NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
602 // Vector Compare Mask Less or Same (Unsigned Integer)
603 // CMLS is alias for CMHS with operands reversed.
604 def CMLSvvv_8B : NeonI_compare_aliases<"cmls", ".8b", CMHSvvv_8B, VPR64>;
605 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
606 def CMLSvvv_4H : NeonI_compare_aliases<"cmls", ".4h", CMHSvvv_4H, VPR64>;
607 def CMLSvvv_8H : NeonI_compare_aliases<"cmls", ".8h", CMHSvvv_8H, VPR128>;
608 def CMLSvvv_2S : NeonI_compare_aliases<"cmls", ".2s", CMHSvvv_2S, VPR64>;
609 def CMLSvvv_4S : NeonI_compare_aliases<"cmls", ".4s", CMHSvvv_4S, VPR128>;
610 def CMLSvvv_2D : NeonI_compare_aliases<"cmls", ".2d", CMHSvvv_2D, VPR128>;
612 // Vector Compare Mask Less Than or Equal (Integer)
613 // CMLE is alias for CMGE with operands reversed.
614 def CMLEvvv_8B : NeonI_compare_aliases<"cmle", ".8b", CMGEvvv_8B, VPR64>;
615 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
616 def CMLEvvv_4H : NeonI_compare_aliases<"cmle", ".4h", CMGEvvv_4H, VPR64>;
617 def CMLEvvv_8H : NeonI_compare_aliases<"cmle", ".8h", CMGEvvv_8H, VPR128>;
618 def CMLEvvv_2S : NeonI_compare_aliases<"cmle", ".2s", CMGEvvv_2S, VPR64>;
619 def CMLEvvv_4S : NeonI_compare_aliases<"cmle", ".4s", CMGEvvv_4S, VPR128>;
620 def CMLEvvv_2D : NeonI_compare_aliases<"cmle", ".2d", CMGEvvv_2D, VPR128>;
622 // Vector Compare Mask Lower (Unsigned Integer)
623 // CMLO is alias for CMHI with operands reversed.
624 def CMLOvvv_8B : NeonI_compare_aliases<"cmlo", ".8b", CMHIvvv_8B, VPR64>;
625 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
626 def CMLOvvv_4H : NeonI_compare_aliases<"cmlo", ".4h", CMHIvvv_4H, VPR64>;
627 def CMLOvvv_8H : NeonI_compare_aliases<"cmlo", ".8h", CMHIvvv_8H, VPR128>;
628 def CMLOvvv_2S : NeonI_compare_aliases<"cmlo", ".2s", CMHIvvv_2S, VPR64>;
629 def CMLOvvv_4S : NeonI_compare_aliases<"cmlo", ".4s", CMHIvvv_4S, VPR128>;
630 def CMLOvvv_2D : NeonI_compare_aliases<"cmlo", ".2d", CMHIvvv_2D, VPR128>;
632 // Vector Compare Mask Less Than (Integer)
633 // CMLT is alias for CMGT with operands reversed.
634 def CMLTvvv_8B : NeonI_compare_aliases<"cmlt", ".8b", CMGTvvv_8B, VPR64>;
635 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
636 def CMLTvvv_4H : NeonI_compare_aliases<"cmlt", ".4h", CMGTvvv_4H, VPR64>;
637 def CMLTvvv_8H : NeonI_compare_aliases<"cmlt", ".8h", CMGTvvv_8H, VPR128>;
638 def CMLTvvv_2S : NeonI_compare_aliases<"cmlt", ".2s", CMGTvvv_2S, VPR64>;
639 def CMLTvvv_4S : NeonI_compare_aliases<"cmlt", ".4s", CMGTvvv_4S, VPR128>;
640 def CMLTvvv_2D : NeonI_compare_aliases<"cmlt", ".2d", CMGTvvv_2D, VPR128>;
643 def neon_uimm0_asmoperand : AsmOperandClass
646 let PredicateMethod = "isUImm<0>";
647 let RenderMethod = "addImmOperands";
650 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
651 let ParserMatchClass = neon_uimm0_asmoperand;
652 let PrintMethod = "printNeonUImm0Operand";
656 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
658 def _8B : NeonI_2VMisc<0b0, u, 0b00, opcode,
659 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
660 asmop # "\t$Rd.8b, $Rn.8b, $Imm",
661 [(set (v8i8 VPR64:$Rd),
662 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
665 def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
666 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
667 asmop # "\t$Rd.16b, $Rn.16b, $Imm",
668 [(set (v16i8 VPR128:$Rd),
669 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
672 def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
673 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
674 asmop # "\t$Rd.4h, $Rn.4h, $Imm",
675 [(set (v4i16 VPR64:$Rd),
676 (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
679 def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
680 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
681 asmop # "\t$Rd.8h, $Rn.8h, $Imm",
682 [(set (v8i16 VPR128:$Rd),
683 (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
686 def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
687 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
688 asmop # "\t$Rd.2s, $Rn.2s, $Imm",
689 [(set (v2i32 VPR64:$Rd),
690 (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
693 def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
694 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
695 asmop # "\t$Rd.4s, $Rn.4s, $Imm",
696 [(set (v4i32 VPR128:$Rd),
697 (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
700 def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
701 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
702 asmop # "\t$Rd.2d, $Rn.2d, $Imm",
703 [(set (v2i64 VPR128:$Rd),
704 (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
708 // Vector Compare Mask Equal to Zero (Integer)
709 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
711 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
712 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
714 // Vector Compare Mask Greater Than Zero (Signed Integer)
715 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
717 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
718 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
720 // Vector Compare Mask Less Than Zero (Signed Integer)
721 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
723 // Vector Comparisons (Floating Point)
725 // Vector Compare Mask Equal (Floating Point)
726 let isCommutable =1 in {
727 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
728 Neon_cmeq, Neon_cmeq,
729 v2i32, v4i32, v2i64, 0>;
732 // Vector Compare Mask Greater Than Or Equal (Floating Point)
733 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
734 Neon_cmge, Neon_cmge,
735 v2i32, v4i32, v2i64, 0>;
737 // Vector Compare Mask Greater Than (Floating Point)
738 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
739 Neon_cmgt, Neon_cmgt,
740 v2i32, v4i32, v2i64, 0>;
742 // Vector Compare Mask Less Than Or Equal (Floating Point)
743 // FCMLE is alias for FCMGE with operands reversed.
744 def FCMLEvvv_2S : NeonI_compare_aliases<"fcmle", ".2s", FCMGEvvv_2S, VPR64>;
745 def FCMLEvvv_4S : NeonI_compare_aliases<"fcmle", ".4s", FCMGEvvv_4S, VPR128>;
746 def FCMLEvvv_2D : NeonI_compare_aliases<"fcmle", ".2d", FCMGEvvv_2D, VPR128>;
748 // Vector Compare Mask Less Than (Floating Point)
749 // FCMLT is alias for FCMGT with operands reversed.
750 def FCMLTvvv_2S : NeonI_compare_aliases<"fcmlt", ".2s", FCMGTvvv_2S, VPR64>;
751 def FCMLTvvv_4S : NeonI_compare_aliases<"fcmlt", ".4s", FCMGTvvv_4S, VPR128>;
752 def FCMLTvvv_2D : NeonI_compare_aliases<"fcmlt", ".2d", FCMGTvvv_2D, VPR128>;
755 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
756 string asmop, CondCode CC>
758 def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
759 (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
760 asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
761 [(set (v2i32 VPR64:$Rd),
762 (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpimm:$FPImm), CC)))],
765 def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
766 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
767 asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
768 [(set (v4i32 VPR128:$Rd),
769 (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
772 def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
773 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
774 asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
775 [(set (v2i64 VPR128:$Rd),
776 (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
780 // Vector Compare Mask Equal to Zero (Floating Point)
781 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
783 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
784 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
786 // Vector Compare Mask Greater Than Zero (Floating Point)
787 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
789 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
790 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
792 // Vector Compare Mask Less Than Zero (Floating Point)
793 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
795 // Vector Absolute Comparisons (Floating Point)
797 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
798 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
799 int_arm_neon_vacged, int_arm_neon_vacgeq,
800 int_aarch64_neon_vacgeq,
801 v2i32, v4i32, v2i64, 0>;
803 // Vector Absolute Compare Mask Greater Than (Floating Point)
804 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
805 int_arm_neon_vacgtd, int_arm_neon_vacgtq,
806 int_aarch64_neon_vacgtq,
807 v2i32, v4i32, v2i64, 0>;
809 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
810 // FACLE is alias for FACGE with operands reversed.
811 def FACLEvvv_2S : NeonI_compare_aliases<"facle", ".2s", FACGEvvv_2S, VPR64>;
812 def FACLEvvv_4S : NeonI_compare_aliases<"facle", ".4s", FACGEvvv_4S, VPR128>;
813 def FACLEvvv_2D : NeonI_compare_aliases<"facle", ".2d", FACGEvvv_2D, VPR128>;
815 // Vector Absolute Compare Mask Less Than (Floating Point)
816 // FACLT is alias for FACGT with operands reversed.
817 def FACLTvvv_2S : NeonI_compare_aliases<"faclt", ".2s", FACGTvvv_2S, VPR64>;
818 def FACLTvvv_4S : NeonI_compare_aliases<"faclt", ".4s", FACGTvvv_4S, VPR128>;
819 def FACLTvvv_2D : NeonI_compare_aliases<"faclt", ".2d", FACGTvvv_2D, VPR128>;
821 // Vector halving add (Integer Signed, Unsigned)
822 defm SHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
823 int_arm_neon_vhadds, 1>;
824 defm UHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
825 int_arm_neon_vhaddu, 1>;
827 // Vector halving sub (Integer Signed, Unsigned)
828 defm SHSUBvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
829 int_arm_neon_vhsubs, 0>;
830 defm UHSUBvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
831 int_arm_neon_vhsubu, 0>;
833 // Vector rouding halving add (Integer Signed, Unsigned)
834 defm SRHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
835 int_arm_neon_vrhadds, 1>;
836 defm URHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
837 int_arm_neon_vrhaddu, 1>;
839 // Vector Saturating add (Integer Signed, Unsigned)
840 defm SQADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
841 int_arm_neon_vqadds, 1>;
842 defm UQADDvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
843 int_arm_neon_vqaddu, 1>;
845 // Vector Saturating sub (Integer Signed, Unsigned)
846 defm SQSUBvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
847 int_arm_neon_vqsubs, 1>;
848 defm UQSUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
849 int_arm_neon_vqsubu, 1>;
851 // Vector Shift Left (Signed and Unsigned Integer)
852 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
853 int_arm_neon_vshifts, 1>;
854 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
855 int_arm_neon_vshiftu, 1>;
857 // Vector Saturating Shift Left (Signed and Unsigned Integer)
858 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
859 int_arm_neon_vqshifts, 1>;
860 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
861 int_arm_neon_vqshiftu, 1>;
863 // Vector Rouding Shift Left (Signed and Unsigned Integer)
864 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
865 int_arm_neon_vrshifts, 1>;
866 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
867 int_arm_neon_vrshiftu, 1>;
869 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
870 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
871 int_arm_neon_vqrshifts, 1>;
872 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
873 int_arm_neon_vqrshiftu, 1>;
875 // Vector Maximum (Signed and Unsigned Integer)
876 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
877 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
879 // Vector Minimum (Signed and Unsigned Integer)
880 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
881 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
883 // Vector Maximum (Floating Point)
884 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
885 int_arm_neon_vmaxs, int_arm_neon_vmaxs,
886 int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
888 // Vector Minimum (Floating Point)
889 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
890 int_arm_neon_vmins, int_arm_neon_vmins,
891 int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
893 // Vector maxNum (Floating Point) - prefer a number over a quiet NaN)
894 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
895 int_aarch64_neon_vmaxnm,
896 int_aarch64_neon_vmaxnm,
897 int_aarch64_neon_vmaxnm,
898 v2f32, v4f32, v2f64, 1>;
900 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
901 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
902 int_aarch64_neon_vminnm,
903 int_aarch64_neon_vminnm,
904 int_aarch64_neon_vminnm,
905 v2f32, v4f32, v2f64, 1>;
907 // Vector Maximum Pairwise (Signed and Unsigned Integer)
908 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
909 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
911 // Vector Minimum Pairwise (Signed and Unsigned Integer)
912 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
913 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
915 // Vector Maximum Pairwise (Floating Point)
916 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
917 int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
918 int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
920 // Vector Minimum Pairwise (Floating Point)
921 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
922 int_arm_neon_vpmins, int_arm_neon_vpmins,
923 int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
925 // Vector maxNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
926 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
927 int_aarch64_neon_vpmaxnm,
928 int_aarch64_neon_vpmaxnm,
929 int_aarch64_neon_vpmaxnm,
930 v2f32, v4f32, v2f64, 1>;
932 // Vector minNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
933 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
934 int_aarch64_neon_vpminnm,
935 int_aarch64_neon_vpminnm,
936 int_aarch64_neon_vpminnm,
937 v2f32, v4f32, v2f64, 1>;
939 // Vector Addition Pairwise (Integer)
940 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
942 // Vector Addition Pairwise (Floating Point)
943 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
947 v2f32, v4f32, v2f64, 1>;
949 // Vector Saturating Doubling Multiply High
950 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
951 int_arm_neon_vqdmulh, 1>;
953 // Vector Saturating Rouding Doubling Multiply High
954 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
955 int_arm_neon_vqrdmulh, 1>;
957 // Vector Multiply Extended (Floating Point)
958 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
959 int_aarch64_neon_vmulx,
960 int_aarch64_neon_vmulx,
961 int_aarch64_neon_vmulx,
962 v2f32, v4f32, v2f64, 1>;
964 // Vector Immediate Instructions
966 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
968 def _asmoperand : AsmOperandClass
970 let Name = "NeonMovImmShift" # PREFIX;
971 let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
972 let PredicateMethod = "isNeonMovImmShift" # PREFIX;
976 // Definition of vector immediates shift operands
978 // The selectable use-cases extract the shift operation
979 // information from the OpCmode fields encoded in the immediate.
980 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
981 uint64_t OpCmode = N->getZExtValue();
983 unsigned ShiftOnesIn;
985 A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
986 if (!HasShift) return SDValue();
987 return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
990 // Vector immediates shift operands which accept LSL and MSL
991 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
992 // or 0, 8 (LSLH) or 8, 16 (MSL).
993 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
994 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
995 // LSLH restricts shift amount to 0, 8 out of 0, 8, 16, 24
996 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
998 multiclass neon_mov_imm_shift_operands<string PREFIX,
999 string HALF, string ISHALF, code pred>
1001 def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1004 "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1006 "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1007 let ParserMatchClass =
1008 !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1012 defm neon_mov_imm_LSL : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1014 unsigned ShiftOnesIn;
1016 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1017 return (HasShift && !ShiftOnesIn);
1020 defm neon_mov_imm_MSL : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1022 unsigned ShiftOnesIn;
1024 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1025 return (HasShift && ShiftOnesIn);
1028 defm neon_mov_imm_LSLH : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1030 unsigned ShiftOnesIn;
1032 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1033 return (HasShift && !ShiftOnesIn);
1036 def neon_uimm1_asmoperand : AsmOperandClass
1039 let PredicateMethod = "isUImm<1>";
1040 let RenderMethod = "addImmOperands";
1043 def neon_uimm2_asmoperand : AsmOperandClass
1046 let PredicateMethod = "isUImm<2>";
1047 let RenderMethod = "addImmOperands";
1050 def neon_uimm8_asmoperand : AsmOperandClass
1053 let PredicateMethod = "isUImm<8>";
1054 let RenderMethod = "addImmOperands";
1057 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1058 let ParserMatchClass = neon_uimm8_asmoperand;
1059 let PrintMethod = "printUImmHexOperand";
1062 def neon_uimm64_mask_asmoperand : AsmOperandClass
1064 let Name = "NeonUImm64Mask";
1065 let PredicateMethod = "isNeonUImm64Mask";
1066 let RenderMethod = "addNeonUImm64MaskOperands";
1069 // MCOperand for 64-bit bytemask with each byte having only the
1070 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1071 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1072 let ParserMatchClass = neon_uimm64_mask_asmoperand;
1073 let PrintMethod = "printNeonUImm64MaskOperand";
1076 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1077 SDPatternOperator opnode>
1079 // shift zeros, per word
1080 def _2S : NeonI_1VModImm<0b0, op,
1082 (ins neon_uimm8:$Imm,
1083 neon_mov_imm_LSL_operand:$Simm),
1084 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1085 [(set (v2i32 VPR64:$Rd),
1086 (v2i32 (opnode (timm:$Imm),
1087 (neon_mov_imm_LSL_operand:$Simm))))],
1090 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1093 def _4S : NeonI_1VModImm<0b1, op,
1095 (ins neon_uimm8:$Imm,
1096 neon_mov_imm_LSL_operand:$Simm),
1097 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1098 [(set (v4i32 VPR128:$Rd),
1099 (v4i32 (opnode (timm:$Imm),
1100 (neon_mov_imm_LSL_operand:$Simm))))],
1103 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1106 // shift zeros, per halfword
1107 def _4H : NeonI_1VModImm<0b0, op,
1109 (ins neon_uimm8:$Imm,
1110 neon_mov_imm_LSLH_operand:$Simm),
1111 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1112 [(set (v4i16 VPR64:$Rd),
1113 (v4i16 (opnode (timm:$Imm),
1114 (neon_mov_imm_LSLH_operand:$Simm))))],
1117 let cmode = {0b1, 0b0, Simm, 0b0};
1120 def _8H : NeonI_1VModImm<0b1, op,
1122 (ins neon_uimm8:$Imm,
1123 neon_mov_imm_LSLH_operand:$Simm),
1124 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1125 [(set (v8i16 VPR128:$Rd),
1126 (v8i16 (opnode (timm:$Imm),
1127 (neon_mov_imm_LSLH_operand:$Simm))))],
1130 let cmode = {0b1, 0b0, Simm, 0b0};
1134 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1135 SDPatternOperator opnode,
1136 SDPatternOperator neonopnode>
1138 let Constraints = "$src = $Rd" in {
1139 // shift zeros, per word
1140 def _2S : NeonI_1VModImm<0b0, op,
1142 (ins VPR64:$src, neon_uimm8:$Imm,
1143 neon_mov_imm_LSL_operand:$Simm),
1144 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1145 [(set (v2i32 VPR64:$Rd),
1146 (v2i32 (opnode (v2i32 VPR64:$src),
1147 (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1148 neon_mov_imm_LSL_operand:$Simm)))))))],
1151 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1154 def _4S : NeonI_1VModImm<0b1, op,
1156 (ins VPR128:$src, neon_uimm8:$Imm,
1157 neon_mov_imm_LSL_operand:$Simm),
1158 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1159 [(set (v4i32 VPR128:$Rd),
1160 (v4i32 (opnode (v4i32 VPR128:$src),
1161 (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1162 neon_mov_imm_LSL_operand:$Simm)))))))],
1165 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1168 // shift zeros, per halfword
1169 def _4H : NeonI_1VModImm<0b0, op,
1171 (ins VPR64:$src, neon_uimm8:$Imm,
1172 neon_mov_imm_LSLH_operand:$Simm),
1173 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1174 [(set (v4i16 VPR64:$Rd),
1175 (v4i16 (opnode (v4i16 VPR64:$src),
1176 (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1177 neon_mov_imm_LSL_operand:$Simm)))))))],
1180 let cmode = {0b1, 0b0, Simm, 0b1};
1183 def _8H : NeonI_1VModImm<0b1, op,
1185 (ins VPR128:$src, neon_uimm8:$Imm,
1186 neon_mov_imm_LSLH_operand:$Simm),
1187 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1188 [(set (v8i16 VPR128:$Rd),
1189 (v8i16 (opnode (v8i16 VPR128:$src),
1190 (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1191 neon_mov_imm_LSL_operand:$Simm)))))))],
1194 let cmode = {0b1, 0b0, Simm, 0b1};
1199 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1200 SDPatternOperator opnode>
1202 // shift ones, per word
1203 def _2S : NeonI_1VModImm<0b0, op,
1205 (ins neon_uimm8:$Imm,
1206 neon_mov_imm_MSL_operand:$Simm),
1207 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1208 [(set (v2i32 VPR64:$Rd),
1209 (v2i32 (opnode (timm:$Imm),
1210 (neon_mov_imm_MSL_operand:$Simm))))],
1213 let cmode = {0b1, 0b1, 0b0, Simm};
1216 def _4S : NeonI_1VModImm<0b1, op,
1218 (ins neon_uimm8:$Imm,
1219 neon_mov_imm_MSL_operand:$Simm),
1220 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1221 [(set (v4i32 VPR128:$Rd),
1222 (v4i32 (opnode (timm:$Imm),
1223 (neon_mov_imm_MSL_operand:$Simm))))],
1226 let cmode = {0b1, 0b1, 0b0, Simm};
1230 // Vector Move Immediate Shifted
1231 let isReMaterializable = 1 in {
1232 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1235 // Vector Move Inverted Immediate Shifted
1236 let isReMaterializable = 1 in {
1237 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1240 // Vector Bitwise Bit Clear (AND NOT) - immediate
1241 let isReMaterializable = 1 in {
1242 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1246 // Vector Bitwise OR - immedidate
1248 let isReMaterializable = 1 in {
1249 defm ORRvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1253 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1254 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1255 // BIC immediate instructions selection requires additional patterns to
1256 // transform Neon_movi operands into BIC immediate operands
1258 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1259 uint64_t OpCmode = N->getZExtValue();
1261 unsigned ShiftOnesIn;
1262 (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1263 // LSLH restricts shift amount to 0, 8 which are encoded as 0 and 1
1264 // Transform encoded shift amount 0 to 1 and 1 to 0.
1265 return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1268 def neon_mov_imm_LSLH_transform_operand
1271 unsigned ShiftOnesIn;
1273 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1274 return (HasShift && !ShiftOnesIn); }],
1275 neon_mov_imm_LSLH_transform_XFORM>;
1277 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1278 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1279 def : Pat<(v4i16 (and VPR64:$src,
1280 (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1281 (BICvi_lsl_4H VPR64:$src, 0,
1282 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1284 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1285 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1286 def : Pat<(v8i16 (and VPR128:$src,
1287 (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1288 (BICvi_lsl_8H VPR128:$src, 0,
1289 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1292 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1293 SDPatternOperator neonopnode,
1295 Instruction INST8H> {
1296 def : Pat<(v8i8 (opnode VPR64:$src,
1297 (bitconvert(v4i16 (neonopnode timm:$Imm,
1298 neon_mov_imm_LSLH_operand:$Simm))))),
1299 (INST4H VPR64:$src, neon_uimm8:$Imm,
1300 neon_mov_imm_LSLH_operand:$Simm)>;
1301 def : Pat<(v1i64 (opnode VPR64:$src,
1302 (bitconvert(v4i16 (neonopnode timm:$Imm,
1303 neon_mov_imm_LSLH_operand:$Simm))))),
1304 (INST4H VPR64:$src, neon_uimm8:$Imm,
1305 neon_mov_imm_LSLH_operand:$Simm)>;
1307 def : Pat<(v16i8 (opnode VPR128:$src,
1308 (bitconvert(v8i16 (neonopnode timm:$Imm,
1309 neon_mov_imm_LSLH_operand:$Simm))))),
1310 (INST8H VPR128:$src, neon_uimm8:$Imm,
1311 neon_mov_imm_LSLH_operand:$Simm)>;
1312 def : Pat<(v4i32 (opnode VPR128:$src,
1313 (bitconvert(v8i16 (neonopnode timm:$Imm,
1314 neon_mov_imm_LSLH_operand:$Simm))))),
1315 (INST8H VPR128:$src, neon_uimm8:$Imm,
1316 neon_mov_imm_LSLH_operand:$Simm)>;
1317 def : Pat<(v2i64 (opnode VPR128:$src,
1318 (bitconvert(v8i16 (neonopnode timm:$Imm,
1319 neon_mov_imm_LSLH_operand:$Simm))))),
1320 (INST8H VPR128:$src, neon_uimm8:$Imm,
1321 neon_mov_imm_LSLH_operand:$Simm)>;
1324 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1325 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1327 // Additional patterns for Vector Bitwise OR - immedidate
1328 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1331 // Vector Move Immediate Masked
1332 let isReMaterializable = 1 in {
1333 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1336 // Vector Move Inverted Immediate Masked
1337 let isReMaterializable = 1 in {
1338 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1341 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1342 Instruction inst, RegisterOperand VPRC>
1343 : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1344 (inst VPRC:$Rd, neon_uimm8:$Imm, 0), 0b0>;
1346 // Aliases for Vector Move Immediate Shifted
1347 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1348 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1349 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1350 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1352 // Aliases for Vector Move Inverted Immediate Shifted
1353 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1354 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1355 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1356 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1358 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1359 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1360 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1361 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1362 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1364 // Aliases for Vector Bitwise OR - immedidate
1365 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1366 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1367 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1368 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1370 // Vector Move Immediate - per byte
1371 let isReMaterializable = 1 in {
1372 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1373 (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1374 "movi\t$Rd.8b, $Imm",
1375 [(set (v8i8 VPR64:$Rd),
1376 (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1381 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1382 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1383 "movi\t$Rd.16b, $Imm",
1384 [(set (v16i8 VPR128:$Rd),
1385 (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1391 // Vector Move Immediate - bytemask, per double word
1392 let isReMaterializable = 1 in {
1393 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1394 (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1395 "movi\t $Rd.2d, $Imm",
1396 [(set (v2i64 VPR128:$Rd),
1397 (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1403 // Vector Move Immediate - bytemask, one doubleword
1405 let isReMaterializable = 1 in {
1406 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1407 (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1409 [(set (f64 FPR64:$Rd),
1411 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))))],
1417 // Vector Floating Point Move Immediate
1419 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1420 Operand immOpType, bit q, bit op>
1421 : NeonI_1VModImm<q, op,
1422 (outs VPRC:$Rd), (ins immOpType:$Imm),
1423 "fmov\t$Rd" # asmlane # ", $Imm",
1424 [(set (OpTy VPRC:$Rd),
1425 (OpTy (Neon_fmovi (timm:$Imm))))],
1430 let isReMaterializable = 1 in {
1431 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64, v2f32, fmov32_operand, 0b0, 0b0>;
1432 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1433 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1436 // Vector Shift (Immediate)
1437 // Immediate in [0, 63]
1438 def imm0_63 : Operand<i32> {
1439 let ParserMatchClass = uimm6_asmoperand;
1442 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1446 // 8 immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1447 // 16 immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1448 // 32 immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1449 // 64 immh:immb<6> = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1451 // The shift right immediate amount, in the range 1 to element bits, is computed
1452 // as Offset - UInt(immh:immb). The shift left immediate amount, in the range 0
1453 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1455 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1456 let Name = "ShrImm" # OFFSET;
1457 let RenderMethod = "addImmOperands";
1458 let DiagnosticType = "ShrImm" # OFFSET;
1461 class shr_imm<string OFFSET> : Operand<i32> {
1462 let EncoderMethod = "getShiftRightImm" # OFFSET;
1463 let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1464 let ParserMatchClass =
1465 !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1468 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1469 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1470 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1471 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1473 def shr_imm8 : shr_imm<"8">;
1474 def shr_imm16 : shr_imm<"16">;
1475 def shr_imm32 : shr_imm<"32">;
1476 def shr_imm64 : shr_imm<"64">;
1478 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1479 let Name = "ShlImm" # OFFSET;
1480 let RenderMethod = "addImmOperands";
1481 let DiagnosticType = "ShlImm" # OFFSET;
1484 class shl_imm<string OFFSET> : Operand<i32> {
1485 let EncoderMethod = "getShiftLeftImm" # OFFSET;
1486 let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1487 let ParserMatchClass =
1488 !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1491 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1492 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1493 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1494 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1496 def shl_imm8 : shl_imm<"8">;
1497 def shl_imm16 : shl_imm<"16">;
1498 def shl_imm32 : shl_imm<"32">;
1499 def shl_imm64 : shl_imm<"64">;
1501 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1502 RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1503 : NeonI_2VShiftImm<q, u, opcode,
1504 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1505 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1506 [(set (Ty VPRC:$Rd),
1507 (Ty (OpNode (Ty VPRC:$Rn),
1508 (Ty (Neon_vdup (i32 imm:$Imm))))))],
1511 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1512 // 64-bit vector types.
1513 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3, shl> {
1514 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1517 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4, shl> {
1518 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1521 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5, shl> {
1522 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1525 // 128-bit vector types.
1526 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3, shl> {
1527 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1530 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4, shl> {
1531 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1534 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5, shl> {
1535 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1538 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63, shl> {
1539 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
1543 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1544 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1546 let Inst{22-19} = 0b0001;
1549 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1551 let Inst{22-20} = 0b001;
1554 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1556 let Inst{22-21} = 0b01;
1559 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1561 let Inst{22-19} = 0b0001;
1564 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1566 let Inst{22-20} = 0b001;
1569 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1571 let Inst{22-21} = 0b01;
1574 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1581 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1584 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1585 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1587 def Neon_High16B : PatFrag<(ops node:$in),
1588 (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1589 def Neon_High8H : PatFrag<(ops node:$in),
1590 (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1591 def Neon_High4S : PatFrag<(ops node:$in),
1592 (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1593 def Neon_High2D : PatFrag<(ops node:$in),
1594 (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1595 def Neon_High4f : PatFrag<(ops node:$in),
1596 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1597 def Neon_High2d : PatFrag<(ops node:$in),
1598 (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1600 def Neon_low16B : PatFrag<(ops node:$in),
1601 (v8i8 (extract_subvector (v16i8 node:$in),
1603 def Neon_low8H : PatFrag<(ops node:$in),
1604 (v4i16 (extract_subvector (v8i16 node:$in),
1606 def Neon_low4S : PatFrag<(ops node:$in),
1607 (v2i32 (extract_subvector (v4i32 node:$in),
1609 def Neon_low2D : PatFrag<(ops node:$in),
1610 (v1i64 (extract_subvector (v2i64 node:$in),
1612 def Neon_low4f : PatFrag<(ops node:$in),
1613 (v2f32 (extract_subvector (v4f32 node:$in),
1615 def Neon_low2d : PatFrag<(ops node:$in),
1616 (v1f64 (extract_subvector (v2f64 node:$in),
1619 def neon_uimm3_shift : Operand<i32>,
1620 ImmLeaf<i32, [{return Imm < 8;}]> {
1621 let ParserMatchClass = uimm3_asmoperand;
1624 def neon_uimm4_shift : Operand<i32>,
1625 ImmLeaf<i32, [{return Imm < 16;}]> {
1626 let ParserMatchClass = uimm4_asmoperand;
1629 def neon_uimm5_shift : Operand<i32>,
1630 ImmLeaf<i32, [{return Imm < 32;}]> {
1631 let ParserMatchClass = uimm5_asmoperand;
1634 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1635 string SrcT, ValueType DestTy, ValueType SrcTy,
1636 Operand ImmTy, SDPatternOperator ExtOp>
1637 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1638 (ins VPR64:$Rn, ImmTy:$Imm),
1639 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1640 [(set (DestTy VPR128:$Rd),
1642 (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1643 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1646 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1647 string SrcT, ValueType DestTy, ValueType SrcTy,
1648 int StartIndex, Operand ImmTy,
1649 SDPatternOperator ExtOp, PatFrag getTop>
1650 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1651 (ins VPR128:$Rn, ImmTy:$Imm),
1652 asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1653 [(set (DestTy VPR128:$Rd),
1656 (SrcTy (getTop VPR128:$Rn)))),
1657 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1660 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1662 // 64-bit vector types.
1663 def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1664 neon_uimm3_shift, ExtOp> {
1665 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1668 def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1669 neon_uimm4_shift, ExtOp> {
1670 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1673 def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1674 neon_uimm5_shift, ExtOp> {
1675 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1678 // 128-bit vector types
1679 def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1680 8, neon_uimm3_shift, ExtOp, Neon_High16B> {
1681 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1684 def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1685 4, neon_uimm4_shift, ExtOp, Neon_High8H> {
1686 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1689 def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1690 2, neon_uimm5_shift, ExtOp, Neon_High4S> {
1691 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1694 // Use other patterns to match when the immediate is 0.
1695 def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1696 (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1698 def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1699 (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1701 def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1702 (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1704 def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1705 (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1707 def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1708 (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1710 def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1711 (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1715 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1716 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1718 // Rounding/Saturating shift
1719 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1720 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1721 SDPatternOperator OpNode>
1722 : NeonI_2VShiftImm<q, u, opcode,
1723 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1724 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1725 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1729 // shift right (vector by immediate)
1730 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1731 SDPatternOperator OpNode> {
1732 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1734 let Inst{22-19} = 0b0001;
1737 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1739 let Inst{22-20} = 0b001;
1742 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1744 let Inst{22-21} = 0b01;
1747 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1749 let Inst{22-19} = 0b0001;
1752 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1754 let Inst{22-20} = 0b001;
1757 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1759 let Inst{22-21} = 0b01;
1762 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1768 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1769 SDPatternOperator OpNode> {
1770 // 64-bit vector types.
1771 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1773 let Inst{22-19} = 0b0001;
1776 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1778 let Inst{22-20} = 0b001;
1781 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1783 let Inst{22-21} = 0b01;
1786 // 128-bit vector types.
1787 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1789 let Inst{22-19} = 0b0001;
1792 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1794 let Inst{22-20} = 0b001;
1797 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1799 let Inst{22-21} = 0b01;
1802 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1808 // Rounding shift right
1809 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1810 int_aarch64_neon_vsrshr>;
1811 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1812 int_aarch64_neon_vurshr>;
1814 // Saturating shift left unsigned
1815 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1817 // Saturating shift left
1818 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1819 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1821 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1822 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1824 : NeonI_2VShiftImm<q, u, opcode,
1825 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1826 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1827 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1828 (Ty (OpNode (Ty VPRC:$Rn),
1829 (Ty (Neon_vdup (i32 imm:$Imm))))))))],
1831 let Constraints = "$src = $Rd";
1834 // Shift Right accumulate
1835 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1836 def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1838 let Inst{22-19} = 0b0001;
1841 def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1843 let Inst{22-20} = 0b001;
1846 def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1848 let Inst{22-21} = 0b01;
1851 def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1853 let Inst{22-19} = 0b0001;
1856 def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1858 let Inst{22-20} = 0b001;
1861 def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1863 let Inst{22-21} = 0b01;
1866 def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1872 // Shift right and accumulate
1873 defm SSRAvvi : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1874 defm USRAvvi : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1876 // Rounding shift accumulate
1877 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1878 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1879 SDPatternOperator OpNode>
1880 : NeonI_2VShiftImm<q, u, opcode,
1881 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1882 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1883 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1884 (Ty (OpNode (Ty VPRC:$Rn), (i32 imm:$Imm))))))],
1886 let Constraints = "$src = $Rd";
1889 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1890 SDPatternOperator OpNode> {
1891 def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1893 let Inst{22-19} = 0b0001;
1896 def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1898 let Inst{22-20} = 0b001;
1901 def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1903 let Inst{22-21} = 0b01;
1906 def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1908 let Inst{22-19} = 0b0001;
1911 def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1913 let Inst{22-20} = 0b001;
1916 def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1918 let Inst{22-21} = 0b01;
1921 def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1927 // Rounding shift right and accumulate
1928 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1929 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1931 // Shift insert by immediate
1932 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1933 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1934 SDPatternOperator OpNode>
1935 : NeonI_2VShiftImm<q, u, opcode,
1936 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1937 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1938 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1941 let Constraints = "$src = $Rd";
1944 // shift left insert (vector by immediate)
1945 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1946 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1947 int_aarch64_neon_vsli> {
1948 let Inst{22-19} = 0b0001;
1951 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1952 int_aarch64_neon_vsli> {
1953 let Inst{22-20} = 0b001;
1956 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1957 int_aarch64_neon_vsli> {
1958 let Inst{22-21} = 0b01;
1961 // 128-bit vector types
1962 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1963 int_aarch64_neon_vsli> {
1964 let Inst{22-19} = 0b0001;
1967 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1968 int_aarch64_neon_vsli> {
1969 let Inst{22-20} = 0b001;
1972 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1973 int_aarch64_neon_vsli> {
1974 let Inst{22-21} = 0b01;
1977 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1978 int_aarch64_neon_vsli> {
1983 // shift right insert (vector by immediate)
1984 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
1985 // 64-bit vector types.
1986 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1987 int_aarch64_neon_vsri> {
1988 let Inst{22-19} = 0b0001;
1991 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1992 int_aarch64_neon_vsri> {
1993 let Inst{22-20} = 0b001;
1996 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1997 int_aarch64_neon_vsri> {
1998 let Inst{22-21} = 0b01;
2001 // 128-bit vector types
2002 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2003 int_aarch64_neon_vsri> {
2004 let Inst{22-19} = 0b0001;
2007 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2008 int_aarch64_neon_vsri> {
2009 let Inst{22-20} = 0b001;
2012 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2013 int_aarch64_neon_vsri> {
2014 let Inst{22-21} = 0b01;
2017 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2018 int_aarch64_neon_vsri> {
2023 // Shift left and insert
2024 defm SLIvvi : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2026 // Shift right and insert
2027 defm SRIvvi : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2029 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2030 string SrcT, Operand ImmTy>
2031 : NeonI_2VShiftImm<q, u, opcode,
2032 (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2033 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2036 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2037 string SrcT, Operand ImmTy>
2038 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2039 (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2040 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2042 let Constraints = "$src = $Rd";
2045 // left long shift by immediate
2046 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2047 def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2048 let Inst{22-19} = 0b0001;
2051 def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2052 let Inst{22-20} = 0b001;
2055 def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2056 let Inst{22-21} = 0b01;
2059 // Shift Narrow High
2060 def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2062 let Inst{22-19} = 0b0001;
2065 def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2067 let Inst{22-20} = 0b001;
2070 def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2072 let Inst{22-21} = 0b01;
2076 // Shift right narrow
2077 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2079 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2080 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2081 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2082 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2083 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2084 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2085 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2086 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2088 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2089 (v2i64 (concat_vectors (v1i64 node:$Rm),
2090 (v1i64 node:$Rn)))>;
2091 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2092 (v8i16 (concat_vectors (v4i16 node:$Rm),
2093 (v4i16 node:$Rn)))>;
2094 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2095 (v4i32 (concat_vectors (v2i32 node:$Rm),
2096 (v2i32 node:$Rn)))>;
2097 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2098 (v4f32 (concat_vectors (v2f32 node:$Rm),
2099 (v2f32 node:$Rn)))>;
2100 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2101 (v2f64 (concat_vectors (v1f64 node:$Rm),
2102 (v1f64 node:$Rn)))>;
2104 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2105 (v8i16 (srl (v8i16 node:$lhs),
2106 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2107 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2108 (v4i32 (srl (v4i32 node:$lhs),
2109 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2110 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2111 (v2i64 (srl (v2i64 node:$lhs),
2112 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2113 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2114 (v8i16 (sra (v8i16 node:$lhs),
2115 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2116 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2117 (v4i32 (sra (v4i32 node:$lhs),
2118 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2119 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2120 (v2i64 (sra (v2i64 node:$lhs),
2121 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2123 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2124 multiclass Neon_shiftNarrow_patterns<string shr> {
2125 def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2127 (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2128 def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2130 (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2131 def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2133 (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2135 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2136 (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2137 VPR128:$Rn, (i32 imm:$Imm))))))),
2138 (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2139 VPR128:$Rn, imm:$Imm)>;
2140 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2141 (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2142 VPR128:$Rn, (i32 imm:$Imm))))))),
2143 (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2144 VPR128:$Rn, imm:$Imm)>;
2145 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2146 (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2147 VPR128:$Rn, (i32 imm:$Imm))))))),
2148 (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2149 VPR128:$Rn, imm:$Imm)>;
2152 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2153 def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm)),
2154 (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2155 def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm)),
2156 (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2157 def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm)),
2158 (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2160 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2161 (v1i64 (bitconvert (v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm))))),
2162 (!cast<Instruction>(prefix # "_16B")
2163 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2164 VPR128:$Rn, imm:$Imm)>;
2165 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2166 (v1i64 (bitconvert (v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm))))),
2167 (!cast<Instruction>(prefix # "_8H")
2168 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2169 VPR128:$Rn, imm:$Imm)>;
2170 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2171 (v1i64 (bitconvert (v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm))))),
2172 (!cast<Instruction>(prefix # "_4S")
2173 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2174 VPR128:$Rn, imm:$Imm)>;
2177 defm : Neon_shiftNarrow_patterns<"lshr">;
2178 defm : Neon_shiftNarrow_patterns<"ashr">;
2180 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2181 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2182 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2183 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2184 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2185 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2186 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2188 // Convert fix-point and float-pointing
2189 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2190 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2191 Operand ImmTy, SDPatternOperator IntOp>
2192 : NeonI_2VShiftImm<q, u, opcode,
2193 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2194 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2195 [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2199 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2200 SDPatternOperator IntOp> {
2201 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2203 let Inst{22-21} = 0b01;
2206 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2208 let Inst{22-21} = 0b01;
2211 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2217 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2218 SDPatternOperator IntOp> {
2219 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2221 let Inst{22-21} = 0b01;
2224 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2226 let Inst{22-21} = 0b01;
2229 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2235 // Convert fixed-point to floating-point
2236 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2237 int_arm_neon_vcvtfxs2fp>;
2238 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2239 int_arm_neon_vcvtfxu2fp>;
2241 // Convert floating-point to fixed-point
2242 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2243 int_arm_neon_vcvtfp2fxs>;
2244 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2245 int_arm_neon_vcvtfp2fxu>;
2247 multiclass Neon_sshll2_0<SDNode ext>
2249 def _v8i8 : PatFrag<(ops node:$Rn),
2250 (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2251 def _v4i16 : PatFrag<(ops node:$Rn),
2252 (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2253 def _v2i32 : PatFrag<(ops node:$Rn),
2254 (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2257 defm NI_sext_high : Neon_sshll2_0<sext>;
2258 defm NI_zext_high : Neon_sshll2_0<zext>;
2261 //===----------------------------------------------------------------------===//
2262 // Multiclasses for NeonI_Across
2263 //===----------------------------------------------------------------------===//
2267 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2268 string asmop, SDPatternOperator opnode>
2270 def _1h8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2271 (outs FPR16:$Rd), (ins VPR64:$Rn),
2272 asmop # "\t$Rd, $Rn.8b",
2273 [(set (v1i16 FPR16:$Rd),
2274 (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2277 def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2278 (outs FPR16:$Rd), (ins VPR128:$Rn),
2279 asmop # "\t$Rd, $Rn.16b",
2280 [(set (v1i16 FPR16:$Rd),
2281 (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2284 def _1s4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2285 (outs FPR32:$Rd), (ins VPR64:$Rn),
2286 asmop # "\t$Rd, $Rn.4h",
2287 [(set (v1i32 FPR32:$Rd),
2288 (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2291 def _1s8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2292 (outs FPR32:$Rd), (ins VPR128:$Rn),
2293 asmop # "\t$Rd, $Rn.8h",
2294 [(set (v1i32 FPR32:$Rd),
2295 (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2298 // _1d2s doesn't exist!
2300 def _1d4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2301 (outs FPR64:$Rd), (ins VPR128:$Rn),
2302 asmop # "\t$Rd, $Rn.4s",
2303 [(set (v1i64 FPR64:$Rd),
2304 (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2308 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2309 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2313 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2314 string asmop, SDPatternOperator opnode>
2316 def _1b8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2317 (outs FPR8:$Rd), (ins VPR64:$Rn),
2318 asmop # "\t$Rd, $Rn.8b",
2319 [(set (v1i8 FPR8:$Rd),
2320 (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2323 def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2324 (outs FPR8:$Rd), (ins VPR128:$Rn),
2325 asmop # "\t$Rd, $Rn.16b",
2326 [(set (v1i8 FPR8:$Rd),
2327 (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2330 def _1h4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2331 (outs FPR16:$Rd), (ins VPR64:$Rn),
2332 asmop # "\t$Rd, $Rn.4h",
2333 [(set (v1i16 FPR16:$Rd),
2334 (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2337 def _1h8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2338 (outs FPR16:$Rd), (ins VPR128:$Rn),
2339 asmop # "\t$Rd, $Rn.8h",
2340 [(set (v1i16 FPR16:$Rd),
2341 (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2344 // _1s2s doesn't exist!
2346 def _1s4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2347 (outs FPR32:$Rd), (ins VPR128:$Rn),
2348 asmop # "\t$Rd, $Rn.4s",
2349 [(set (v1i32 FPR32:$Rd),
2350 (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2354 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2355 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2357 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2358 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2360 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2364 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2365 string asmop, SDPatternOperator opnode> {
2366 def _1s4s: NeonI_2VAcross<0b1, u, size, opcode,
2367 (outs FPR32:$Rd), (ins VPR128:$Rn),
2368 asmop # "\t$Rd, $Rn.4s",
2369 [(set (v1f32 FPR32:$Rd),
2370 (v1f32 (opnode (v4f32 VPR128:$Rn))))],
2374 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2375 int_aarch64_neon_vmaxnmv>;
2376 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2377 int_aarch64_neon_vminnmv>;
2379 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2380 int_aarch64_neon_vmaxv>;
2381 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2382 int_aarch64_neon_vminv>;
2384 // The followings are for instruction class (Perm)
2386 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2387 string asmop, RegisterOperand OpVPR, string OpS>
2388 : NeonI_Perm<q, size, opcode,
2389 (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2390 asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2393 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop> {
2394 def _8b : NeonI_Permute<0b0, 0b00, opcode, asmop, VPR64, "8b">;
2395 def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop, VPR128, "16b">;
2396 def _4h : NeonI_Permute<0b0, 0b01, opcode, asmop, VPR64, "4h">;
2397 def _8h : NeonI_Permute<0b1, 0b01, opcode, asmop, VPR128, "8h">;
2398 def _2s : NeonI_Permute<0b0, 0b10, opcode, asmop, VPR64, "2s">;
2399 def _4s : NeonI_Permute<0b1, 0b10, opcode, asmop, VPR128, "4s">;
2400 def _2d : NeonI_Permute<0b1, 0b11, opcode, asmop, VPR128, "2d">;
2403 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1">;
2404 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1">;
2405 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1">;
2406 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2">;
2407 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2">;
2408 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2">;
2410 // Extract and Insert
2411 def NI_ei_i32 : PatFrag<(ops node:$Rn, node:$Rm, node:$Ext, node:$Ins),
2412 (vector_insert node:$Rn,
2413 (i32 (vector_extract node:$Rm, node:$Ext)),
2416 def NI_ei_f32 : PatFrag<(ops node:$Rn, node:$Rm, node:$Ext, node:$Ins),
2417 (vector_insert node:$Rn,
2418 (f32 (vector_extract node:$Rm, node:$Ext)),
2422 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2423 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2424 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2425 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2426 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2428 (v16i8 VPR128:$Rn), 2, 1)),
2429 (v16i8 VPR128:$Rn), 4, 2)),
2430 (v16i8 VPR128:$Rn), 6, 3)),
2431 (v16i8 VPR128:$Rn), 8, 4)),
2432 (v16i8 VPR128:$Rn), 10, 5)),
2433 (v16i8 VPR128:$Rn), 12, 6)),
2434 (v16i8 VPR128:$Rn), 14, 7)),
2435 (v16i8 VPR128:$Rm), 0, 8)),
2436 (v16i8 VPR128:$Rm), 2, 9)),
2437 (v16i8 VPR128:$Rm), 4, 10)),
2438 (v16i8 VPR128:$Rm), 6, 11)),
2439 (v16i8 VPR128:$Rm), 8, 12)),
2440 (v16i8 VPR128:$Rm), 10, 13)),
2441 (v16i8 VPR128:$Rm), 12, 14)),
2442 (v16i8 VPR128:$Rm), 14, 15)),
2443 (UZP1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2445 class NI_Uzp1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2446 : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2447 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2449 (Ty VPR:$Rn), 2, 1)),
2450 (Ty VPR:$Rn), 4, 2)),
2451 (Ty VPR:$Rn), 6, 3)),
2452 (Ty VPR:$Rm), 0, 4)),
2453 (Ty VPR:$Rm), 2, 5)),
2454 (Ty VPR:$Rm), 4, 6)),
2455 (Ty VPR:$Rm), 6, 7)),
2456 (INST VPR:$Rn, VPR:$Rm)>;
2458 def : NI_Uzp1_v8<v8i8, VPR64, UZP1vvv_8b>;
2459 def : NI_Uzp1_v8<v8i16, VPR128, UZP1vvv_8h>;
2461 class NI_Uzp1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2463 : Pat<(Ty (ei (Ty (ei (Ty (ei
2465 (Ty VPR:$Rn), 2, 1)),
2466 (Ty VPR:$Rm), 0, 2)),
2467 (Ty VPR:$Rm), 2, 3)),
2468 (INST VPR:$Rn, VPR:$Rm)>;
2470 def : NI_Uzp1_v4<v4i16, VPR64, UZP1vvv_4h, NI_ei_i32>;
2471 def : NI_Uzp1_v4<v4i32, VPR128, UZP1vvv_4s, NI_ei_i32>;
2472 def : NI_Uzp1_v4<v4f32, VPR128, UZP1vvv_4s, NI_ei_f32>;
2475 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2476 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2477 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2478 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2479 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2481 (v16i8 VPR128:$Rn), 1, 0)),
2482 (v16i8 VPR128:$Rn), 3, 1)),
2483 (v16i8 VPR128:$Rn), 5, 2)),
2484 (v16i8 VPR128:$Rn), 7, 3)),
2485 (v16i8 VPR128:$Rn), 9, 4)),
2486 (v16i8 VPR128:$Rn), 11, 5)),
2487 (v16i8 VPR128:$Rn), 13, 6)),
2488 (v16i8 VPR128:$Rn), 15, 7)),
2489 (v16i8 VPR128:$Rm), 1, 8)),
2490 (v16i8 VPR128:$Rm), 3, 9)),
2491 (v16i8 VPR128:$Rm), 5, 10)),
2492 (v16i8 VPR128:$Rm), 7, 11)),
2493 (v16i8 VPR128:$Rm), 9, 12)),
2494 (v16i8 VPR128:$Rm), 11, 13)),
2495 (v16i8 VPR128:$Rm), 13, 14)),
2496 (UZP2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2498 class NI_Uzp2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2499 : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2500 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2502 (Ty VPR:$Rn), 1, 0)),
2503 (Ty VPR:$Rn), 3, 1)),
2504 (Ty VPR:$Rn), 5, 2)),
2505 (Ty VPR:$Rn), 7, 3)),
2506 (Ty VPR:$Rm), 1, 4)),
2507 (Ty VPR:$Rm), 3, 5)),
2508 (Ty VPR:$Rm), 5, 6)),
2509 (INST VPR:$Rn, VPR:$Rm)>;
2511 def : NI_Uzp2_v8<v8i8, VPR64, UZP2vvv_8b>;
2512 def : NI_Uzp2_v8<v8i16, VPR128, UZP2vvv_8h>;
2514 class NI_Uzp2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2516 : Pat<(Ty (ei (Ty (ei (Ty (ei
2518 (Ty VPR:$Rn), 1, 0)),
2519 (Ty VPR:$Rn), 3, 1)),
2520 (Ty VPR:$Rm), 1, 2)),
2521 (INST VPR:$Rn, VPR:$Rm)>;
2523 def : NI_Uzp2_v4<v4i16, VPR64, UZP2vvv_4h, NI_ei_i32>;
2524 def : NI_Uzp2_v4<v4i32, VPR128, UZP2vvv_4s, NI_ei_i32>;
2525 def : NI_Uzp2_v4<v4f32, VPR128, UZP2vvv_4s, NI_ei_f32>;
2528 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2529 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2530 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2531 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2532 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2534 (v16i8 VPR128:$Rm), 0, 1)),
2535 (v16i8 VPR128:$Rn), 1, 2)),
2536 (v16i8 VPR128:$Rm), 1, 3)),
2537 (v16i8 VPR128:$Rn), 2, 4)),
2538 (v16i8 VPR128:$Rm), 2, 5)),
2539 (v16i8 VPR128:$Rn), 3, 6)),
2540 (v16i8 VPR128:$Rm), 3, 7)),
2541 (v16i8 VPR128:$Rn), 4, 8)),
2542 (v16i8 VPR128:$Rm), 4, 9)),
2543 (v16i8 VPR128:$Rn), 5, 10)),
2544 (v16i8 VPR128:$Rm), 5, 11)),
2545 (v16i8 VPR128:$Rn), 6, 12)),
2546 (v16i8 VPR128:$Rm), 6, 13)),
2547 (v16i8 VPR128:$Rn), 7, 14)),
2548 (v16i8 VPR128:$Rm), 7, 15)),
2549 (ZIP1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2551 class NI_Zip1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2552 : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2553 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2555 (Ty VPR:$Rm), 0, 1)),
2556 (Ty VPR:$Rn), 1, 2)),
2557 (Ty VPR:$Rm), 1, 3)),
2558 (Ty VPR:$Rn), 2, 4)),
2559 (Ty VPR:$Rm), 2, 5)),
2560 (Ty VPR:$Rn), 3, 6)),
2561 (Ty VPR:$Rm), 3, 7)),
2562 (INST VPR:$Rn, VPR:$Rm)>;
2564 def : NI_Zip1_v8<v8i8, VPR64, ZIP1vvv_8b>;
2565 def : NI_Zip1_v8<v8i16, VPR128, ZIP1vvv_8h>;
2567 class NI_Zip1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2569 : Pat<(Ty (ei (Ty (ei (Ty (ei
2571 (Ty VPR:$Rm), 0, 1)),
2572 (Ty VPR:$Rn), 1, 2)),
2573 (Ty VPR:$Rm), 1, 3)),
2574 (INST VPR:$Rn, VPR:$Rm)>;
2576 def : NI_Zip1_v4<v4i16, VPR64, ZIP1vvv_4h, NI_ei_i32>;
2577 def : NI_Zip1_v4<v4i32, VPR128, ZIP1vvv_4s, NI_ei_i32>;
2578 def : NI_Zip1_v4<v4f32, VPR128, ZIP1vvv_4s, NI_ei_f32>;
2581 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2582 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2583 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2584 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2585 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2587 (v16i8 VPR128:$Rn), 8, 0)),
2588 (v16i8 VPR128:$Rm), 8, 1)),
2589 (v16i8 VPR128:$Rn), 9, 2)),
2590 (v16i8 VPR128:$Rm), 9, 3)),
2591 (v16i8 VPR128:$Rn), 10, 4)),
2592 (v16i8 VPR128:$Rm), 10, 5)),
2593 (v16i8 VPR128:$Rn), 11, 6)),
2594 (v16i8 VPR128:$Rm), 11, 7)),
2595 (v16i8 VPR128:$Rn), 12, 8)),
2596 (v16i8 VPR128:$Rm), 12, 9)),
2597 (v16i8 VPR128:$Rn), 13, 10)),
2598 (v16i8 VPR128:$Rm), 13, 11)),
2599 (v16i8 VPR128:$Rn), 14, 12)),
2600 (v16i8 VPR128:$Rm), 14, 13)),
2601 (v16i8 VPR128:$Rn), 15, 14)),
2602 (ZIP2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2604 class NI_Zip2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2605 : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2606 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2608 (Ty VPR:$Rn), 4, 0)),
2609 (Ty VPR:$Rm), 4, 1)),
2610 (Ty VPR:$Rn), 5, 2)),
2611 (Ty VPR:$Rm), 5, 3)),
2612 (Ty VPR:$Rn), 6, 4)),
2613 (Ty VPR:$Rm), 6, 5)),
2614 (Ty VPR:$Rn), 7, 6)),
2615 (INST VPR:$Rn, VPR:$Rm)>;
2617 def : NI_Zip2_v8<v8i8, VPR64, ZIP2vvv_8b>;
2618 def : NI_Zip2_v8<v8i16, VPR128, ZIP2vvv_8h>;
2620 class NI_Zip2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2622 : Pat<(Ty (ei (Ty (ei (Ty (ei
2624 (Ty VPR:$Rn), 2, 0)),
2625 (Ty VPR:$Rm), 2, 1)),
2626 (Ty VPR:$Rn), 3, 2)),
2627 (INST VPR:$Rn, VPR:$Rm)>;
2629 def : NI_Zip2_v4<v4i16, VPR64, ZIP2vvv_4h, NI_ei_i32>;
2630 def : NI_Zip2_v4<v4i32, VPR128, ZIP2vvv_4s, NI_ei_i32>;
2631 def : NI_Zip2_v4<v4f32, VPR128, ZIP2vvv_4s, NI_ei_f32>;
2634 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2635 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2636 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2638 (v16i8 VPR128:$Rm), 0, 1)),
2639 (v16i8 VPR128:$Rm), 2, 3)),
2640 (v16i8 VPR128:$Rm), 4, 5)),
2641 (v16i8 VPR128:$Rm), 6, 7)),
2642 (v16i8 VPR128:$Rm), 8, 9)),
2643 (v16i8 VPR128:$Rm), 10, 11)),
2644 (v16i8 VPR128:$Rm), 12, 13)),
2645 (v16i8 VPR128:$Rm), 14, 15)),
2646 (TRN1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2648 class NI_Trn1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2649 : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2651 (Ty VPR:$Rm), 0, 1)),
2652 (Ty VPR:$Rm), 2, 3)),
2653 (Ty VPR:$Rm), 4, 5)),
2654 (Ty VPR:$Rm), 6, 7)),
2655 (INST VPR:$Rn, VPR:$Rm)>;
2657 def : NI_Trn1_v8<v8i8, VPR64, TRN1vvv_8b>;
2658 def : NI_Trn1_v8<v8i16, VPR128, TRN1vvv_8h>;
2660 class NI_Trn1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2662 : Pat<(Ty (ei (Ty (ei
2664 (Ty VPR:$Rm), 0, 1)),
2665 (Ty VPR:$Rm), 2, 3)),
2666 (INST VPR:$Rn, VPR:$Rm)>;
2668 def : NI_Trn1_v4<v4i16, VPR64, TRN1vvv_4h, NI_ei_i32>;
2669 def : NI_Trn1_v4<v4i32, VPR128, TRN1vvv_4s, NI_ei_i32>;
2670 def : NI_Trn1_v4<v4f32, VPR128, TRN1vvv_4s, NI_ei_f32>;
2673 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2674 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2675 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2677 (v16i8 VPR128:$Rn), 1, 0)),
2678 (v16i8 VPR128:$Rn), 3, 2)),
2679 (v16i8 VPR128:$Rn), 5, 4)),
2680 (v16i8 VPR128:$Rn), 7, 6)),
2681 (v16i8 VPR128:$Rn), 9, 8)),
2682 (v16i8 VPR128:$Rn), 11, 10)),
2683 (v16i8 VPR128:$Rn), 13, 12)),
2684 (v16i8 VPR128:$Rn), 15, 14)),
2685 (TRN2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2687 class NI_Trn2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2688 : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2690 (Ty VPR:$Rn), 1, 0)),
2691 (Ty VPR:$Rn), 3, 2)),
2692 (Ty VPR:$Rn), 5, 4)),
2693 (Ty VPR:$Rn), 7, 6)),
2694 (INST VPR:$Rn, VPR:$Rm)>;
2696 def : NI_Trn2_v8<v8i8, VPR64, TRN2vvv_8b>;
2697 def : NI_Trn2_v8<v8i16, VPR128, TRN2vvv_8h>;
2699 class NI_Trn2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2701 : Pat<(Ty (ei (Ty (ei
2703 (Ty VPR:$Rn), 1, 0)),
2704 (Ty VPR:$Rn), 3, 2)),
2705 (INST VPR:$Rn, VPR:$Rm)>;
2707 def : NI_Trn2_v4<v4i16, VPR64, TRN2vvv_4h, NI_ei_i32>;
2708 def : NI_Trn2_v4<v4i32, VPR128, TRN2vvv_4s, NI_ei_i32>;
2709 def : NI_Trn2_v4<v4f32, VPR128, TRN2vvv_4s, NI_ei_f32>;
2711 // End of implementation for instruction class (Perm)
2713 // The followings are for instruction class (3V Diff)
2715 // normal long/long2 pattern
2716 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2717 string asmop, string ResS, string OpS,
2718 SDPatternOperator opnode, SDPatternOperator ext,
2719 RegisterOperand OpVPR,
2720 ValueType ResTy, ValueType OpTy>
2721 : NeonI_3VDiff<q, u, size, opcode,
2722 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2723 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2724 [(set (ResTy VPR128:$Rd),
2725 (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2726 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2729 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2730 string asmop, SDPatternOperator opnode,
2731 bit Commutable = 0> {
2732 let isCommutable = Commutable in {
2733 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2734 opnode, sext, VPR64, v8i16, v8i8>;
2735 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2736 opnode, sext, VPR64, v4i32, v4i16>;
2737 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2738 opnode, sext, VPR64, v2i64, v2i32>;
2742 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2743 SDPatternOperator opnode, bit Commutable = 0> {
2744 let isCommutable = Commutable in {
2745 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2746 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2747 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2748 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2749 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2750 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2754 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2755 SDPatternOperator opnode, bit Commutable = 0> {
2756 let isCommutable = Commutable in {
2757 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2758 opnode, zext, VPR64, v8i16, v8i8>;
2759 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2760 opnode, zext, VPR64, v4i32, v4i16>;
2761 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2762 opnode, zext, VPR64, v2i64, v2i32>;
2766 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2767 SDPatternOperator opnode, bit Commutable = 0> {
2768 let isCommutable = Commutable in {
2769 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2770 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2771 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2772 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2773 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2774 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2778 defm SADDLvvv : NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2779 defm UADDLvvv : NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2781 defm SADDL2vvv : NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2782 defm UADDL2vvv : NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2784 defm SSUBLvvv : NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2785 defm USUBLvvv : NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2787 defm SSUBL2vvv : NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2788 defm USUBL2vvv : NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2790 // normal wide/wide2 pattern
2791 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2792 string asmop, string ResS, string OpS,
2793 SDPatternOperator opnode, SDPatternOperator ext,
2794 RegisterOperand OpVPR,
2795 ValueType ResTy, ValueType OpTy>
2796 : NeonI_3VDiff<q, u, size, opcode,
2797 (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2798 asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2799 [(set (ResTy VPR128:$Rd),
2800 (ResTy (opnode (ResTy VPR128:$Rn),
2801 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2804 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2805 SDPatternOperator opnode> {
2806 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2807 opnode, sext, VPR64, v8i16, v8i8>;
2808 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2809 opnode, sext, VPR64, v4i32, v4i16>;
2810 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2811 opnode, sext, VPR64, v2i64, v2i32>;
2814 defm SADDWvvv : NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2815 defm SSUBWvvv : NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2817 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2818 SDPatternOperator opnode> {
2819 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2820 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2821 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2822 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2823 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2824 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2827 defm SADDW2vvv : NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2828 defm SSUBW2vvv : NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2830 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2831 SDPatternOperator opnode> {
2832 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2833 opnode, zext, VPR64, v8i16, v8i8>;
2834 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2835 opnode, zext, VPR64, v4i32, v4i16>;
2836 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2837 opnode, zext, VPR64, v2i64, v2i32>;
2840 defm UADDWvvv : NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2841 defm USUBWvvv : NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2843 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2844 SDPatternOperator opnode> {
2845 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2846 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2847 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2848 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2849 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2850 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2853 defm UADDW2vvv : NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2854 defm USUBW2vvv : NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2856 // Get the high half part of the vector element.
2857 multiclass NeonI_get_high {
2858 def _8h : PatFrag<(ops node:$Rn),
2859 (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2860 (v8i16 (Neon_vdup (i32 8)))))))>;
2861 def _4s : PatFrag<(ops node:$Rn),
2862 (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2863 (v4i32 (Neon_vdup (i32 16)))))))>;
2864 def _2d : PatFrag<(ops node:$Rn),
2865 (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2866 (v2i64 (Neon_vdup (i32 32)))))))>;
2869 defm NI_get_hi : NeonI_get_high;
2871 // pattern for addhn/subhn with 2 operands
2872 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2873 string asmop, string ResS, string OpS,
2874 SDPatternOperator opnode, SDPatternOperator get_hi,
2875 ValueType ResTy, ValueType OpTy>
2876 : NeonI_3VDiff<q, u, size, opcode,
2877 (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2878 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2879 [(set (ResTy VPR64:$Rd),
2881 (OpTy (opnode (OpTy VPR128:$Rn),
2882 (OpTy VPR128:$Rm))))))],
2885 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2886 SDPatternOperator opnode, bit Commutable = 0> {
2887 let isCommutable = Commutable in {
2888 def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2889 opnode, NI_get_hi_8h, v8i8, v8i16>;
2890 def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2891 opnode, NI_get_hi_4s, v4i16, v4i32>;
2892 def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2893 opnode, NI_get_hi_2d, v2i32, v2i64>;
2897 defm ADDHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2898 defm SUBHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2900 // pattern for operation with 2 operands
2901 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2902 string asmop, string ResS, string OpS,
2903 SDPatternOperator opnode,
2904 RegisterOperand ResVPR, RegisterOperand OpVPR,
2905 ValueType ResTy, ValueType OpTy>
2906 : NeonI_3VDiff<q, u, size, opcode,
2907 (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2908 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2909 [(set (ResTy ResVPR:$Rd),
2910 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2913 // normal narrow pattern
2914 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2915 SDPatternOperator opnode, bit Commutable = 0> {
2916 let isCommutable = Commutable in {
2917 def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2918 opnode, VPR64, VPR128, v8i8, v8i16>;
2919 def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2920 opnode, VPR64, VPR128, v4i16, v4i32>;
2921 def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2922 opnode, VPR64, VPR128, v2i32, v2i64>;
2926 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2927 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2929 // pattern for acle intrinsic with 3 operands
2930 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2931 string asmop, string ResS, string OpS>
2932 : NeonI_3VDiff<q, u, size, opcode,
2933 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2934 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2936 let Constraints = "$src = $Rd";
2937 let neverHasSideEffects = 1;
2940 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2941 def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2942 def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2943 def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2946 defm ADDHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2947 defm SUBHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2949 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2950 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2952 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2954 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2955 SDPatternOperator coreop>
2956 : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2957 (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2958 (SrcTy VPR128:$Rm)))))),
2959 (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2960 VPR128:$Rn, VPR128:$Rm)>;
2963 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8, v8i16,
2964 BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2965 def : NarrowHighHalfPat<ADDHN2vvv_8h4s, v4i16, v4i32,
2966 BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2967 def : NarrowHighHalfPat<ADDHN2vvv_4s2d, v2i32, v2i64,
2968 BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2971 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8, v8i16,
2972 BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2973 def : NarrowHighHalfPat<SUBHN2vvv_8h4s, v4i16, v4i32,
2974 BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2975 def : NarrowHighHalfPat<SUBHN2vvv_4s2d, v2i32, v2i64,
2976 BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2979 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vraddhn>;
2980 def : NarrowHighHalfPat<RADDHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vraddhn>;
2981 def : NarrowHighHalfPat<RADDHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vraddhn>;
2984 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vrsubhn>;
2985 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vrsubhn>;
2986 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vrsubhn>;
2988 // pattern that need to extend result
2989 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2990 string asmop, string ResS, string OpS,
2991 SDPatternOperator opnode,
2992 RegisterOperand OpVPR,
2993 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2994 : NeonI_3VDiff<q, u, size, opcode,
2995 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2996 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2997 [(set (ResTy VPR128:$Rd),
2998 (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2999 (OpTy OpVPR:$Rm))))))],
3002 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
3003 SDPatternOperator opnode, bit Commutable = 0> {
3004 let isCommutable = Commutable in {
3005 def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3006 opnode, VPR64, v8i16, v8i8, v8i8>;
3007 def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3008 opnode, VPR64, v4i32, v4i16, v4i16>;
3009 def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3010 opnode, VPR64, v2i64, v2i32, v2i32>;
3014 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
3015 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
3017 multiclass NeonI_Op_High<SDPatternOperator op> {
3018 def _16B : PatFrag<(ops node:$Rn, node:$Rm),
3019 (op (v8i8 (Neon_High16B node:$Rn)),
3020 (v8i8 (Neon_High16B node:$Rm)))>;
3021 def _8H : PatFrag<(ops node:$Rn, node:$Rm),
3022 (op (v4i16 (Neon_High8H node:$Rn)),
3023 (v4i16 (Neon_High8H node:$Rm)))>;
3024 def _4S : PatFrag<(ops node:$Rn, node:$Rm),
3025 (op (v2i32 (Neon_High4S node:$Rn)),
3026 (v2i32 (Neon_High4S node:$Rm)))>;
3029 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
3030 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
3031 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
3032 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
3033 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
3034 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
3036 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
3037 bit Commutable = 0> {
3038 let isCommutable = Commutable in {
3039 def _8h8b : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3040 !cast<PatFrag>(opnode # "_16B"),
3041 VPR128, v8i16, v16i8, v8i8>;
3042 def _4s4h : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3043 !cast<PatFrag>(opnode # "_8H"),
3044 VPR128, v4i32, v8i16, v4i16>;
3045 def _2d2s : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3046 !cast<PatFrag>(opnode # "_4S"),
3047 VPR128, v2i64, v4i32, v2i32>;
3051 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
3052 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
3054 // For pattern that need two operators being chained.
3055 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
3056 string asmop, string ResS, string OpS,
3057 SDPatternOperator opnode, SDPatternOperator subop,
3058 RegisterOperand OpVPR,
3059 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
3060 : NeonI_3VDiff<q, u, size, opcode,
3061 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
3062 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3063 [(set (ResTy VPR128:$Rd),
3065 (ResTy VPR128:$src),
3066 (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
3067 (OpTy OpVPR:$Rm))))))))],
3069 let Constraints = "$src = $Rd";
3072 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
3073 SDPatternOperator opnode, SDPatternOperator subop>{
3074 def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3075 opnode, subop, VPR64, v8i16, v8i8, v8i8>;
3076 def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3077 opnode, subop, VPR64, v4i32, v4i16, v4i16>;
3078 def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3079 opnode, subop, VPR64, v2i64, v2i32, v2i32>;
3082 defm SABALvvv : NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
3083 add, int_arm_neon_vabds>;
3084 defm UABALvvv : NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
3085 add, int_arm_neon_vabdu>;
3087 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
3088 SDPatternOperator opnode, string subop> {
3089 def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3090 opnode, !cast<PatFrag>(subop # "_16B"),
3091 VPR128, v8i16, v16i8, v8i8>;
3092 def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3093 opnode, !cast<PatFrag>(subop # "_8H"),
3094 VPR128, v4i32, v8i16, v4i16>;
3095 def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3096 opnode, !cast<PatFrag>(subop # "_4S"),
3097 VPR128, v2i64, v4i32, v2i32>;
3100 defm SABAL2vvv : NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
3102 defm UABAL2vvv : NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
3105 // Long pattern with 2 operands
3106 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
3107 SDPatternOperator opnode, bit Commutable = 0> {
3108 let isCommutable = Commutable in {
3109 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3110 opnode, VPR128, VPR64, v8i16, v8i8>;
3111 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3112 opnode, VPR128, VPR64, v4i32, v4i16>;
3113 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3114 opnode, VPR128, VPR64, v2i64, v2i32>;
3118 defm SMULLvvv : NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
3119 defm UMULLvvv : NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
3121 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
3122 string asmop, string ResS, string OpS,
3123 SDPatternOperator opnode,
3124 ValueType ResTy, ValueType OpTy>
3125 : NeonI_3VDiff<q, u, size, opcode,
3126 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3127 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3128 [(set (ResTy VPR128:$Rd),
3129 (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
3132 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
3133 string opnode, bit Commutable = 0> {
3134 let isCommutable = Commutable in {
3135 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3136 !cast<PatFrag>(opnode # "_16B"),
3138 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3139 !cast<PatFrag>(opnode # "_8H"),
3141 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3142 !cast<PatFrag>(opnode # "_4S"),
3147 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
3149 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
3152 // Long pattern with 3 operands
3153 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
3154 string asmop, string ResS, string OpS,
3155 SDPatternOperator opnode,
3156 ValueType ResTy, ValueType OpTy>
3157 : NeonI_3VDiff<q, u, size, opcode,
3158 (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
3159 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3160 [(set (ResTy VPR128:$Rd),
3162 (ResTy VPR128:$src),
3163 (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
3165 let Constraints = "$src = $Rd";
3168 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
3169 SDPatternOperator opnode> {
3170 def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3171 opnode, v8i16, v8i8>;
3172 def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3173 opnode, v4i32, v4i16>;
3174 def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3175 opnode, v2i64, v2i32>;
3178 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3180 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3182 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3184 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3186 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3188 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3190 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3192 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3194 defm SMLALvvv : NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
3195 defm UMLALvvv : NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
3197 defm SMLSLvvv : NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
3198 defm UMLSLvvv : NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
3200 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
3201 string asmop, string ResS, string OpS,
3202 SDPatternOperator subop, SDPatternOperator opnode,
3203 RegisterOperand OpVPR,
3204 ValueType ResTy, ValueType OpTy>
3205 : NeonI_3VDiff<q, u, size, opcode,
3206 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
3207 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3208 [(set (ResTy VPR128:$Rd),
3210 (ResTy VPR128:$src),
3211 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
3213 let Constraints = "$src = $Rd";
3216 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
3217 SDPatternOperator subop, string opnode> {
3218 def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3219 subop, !cast<PatFrag>(opnode # "_16B"),
3220 VPR128, v8i16, v16i8>;
3221 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3222 subop, !cast<PatFrag>(opnode # "_8H"),
3223 VPR128, v4i32, v8i16>;
3224 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3225 subop, !cast<PatFrag>(opnode # "_4S"),
3226 VPR128, v2i64, v4i32>;
3229 defm SMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
3230 add, "NI_smull_hi">;
3231 defm UMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
3232 add, "NI_umull_hi">;
3234 defm SMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
3235 sub, "NI_smull_hi">;
3236 defm UMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
3237 sub, "NI_umull_hi">;
3239 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
3240 SDPatternOperator opnode> {
3241 def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3242 opnode, int_arm_neon_vqdmull,
3243 VPR64, v4i32, v4i16>;
3244 def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3245 opnode, int_arm_neon_vqdmull,
3246 VPR64, v2i64, v2i32>;
3249 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
3250 int_arm_neon_vqadds>;
3251 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
3252 int_arm_neon_vqsubs>;
3254 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
3255 SDPatternOperator opnode, bit Commutable = 0> {
3256 let isCommutable = Commutable in {
3257 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3258 opnode, VPR128, VPR64, v4i32, v4i16>;
3259 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3260 opnode, VPR128, VPR64, v2i64, v2i32>;
3264 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3265 int_arm_neon_vqdmull, 1>;
3267 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3268 string opnode, bit Commutable = 0> {
3269 let isCommutable = Commutable in {
3270 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3271 !cast<PatFrag>(opnode # "_8H"),
3273 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3274 !cast<PatFrag>(opnode # "_4S"),
3279 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3282 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3283 SDPatternOperator opnode> {
3284 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3285 opnode, NI_qdmull_hi_8H,
3286 VPR128, v4i32, v8i16>;
3287 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3288 opnode, NI_qdmull_hi_4S,
3289 VPR128, v2i64, v4i32>;
3292 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3293 int_arm_neon_vqadds>;
3294 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3295 int_arm_neon_vqsubs>;
3297 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3298 SDPatternOperator opnode, bit Commutable = 0> {
3299 let isCommutable = Commutable in {
3300 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3301 opnode, VPR128, VPR64, v8i16, v8i8>;
3303 def _1q1d : NeonI_3VDiff<0b0, u, 0b11, opcode,
3304 (outs VPR128:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
3305 asmop # "\t$Rd.1q, $Rn.1d, $Rm.1d",
3310 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp, 1>;
3312 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3313 string opnode, bit Commutable = 0> {
3314 let isCommutable = Commutable in {
3315 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3316 !cast<PatFrag>(opnode # "_16B"),
3319 def _1q2d : NeonI_3VDiff<0b1, u, 0b11, opcode,
3320 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3321 asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3326 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3329 // End of implementation for instruction class (3V Diff)
3331 // The followings are vector load/store multiple N-element structure
3332 // (class SIMD lselem).
3334 // ld1: load multiple 1-element structure to 1/2/3/4 registers.
3335 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3336 // The structure consists of a sequence of sets of N values.
3337 // The first element of the structure is placed in the first lane
3338 // of the first first vector, the second element in the first lane
3339 // of the second vector, and so on.
3340 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3341 // the three 64-bit vectors list {BA, DC, FE}.
3342 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3343 // 64-bit vectors list {DA, EB, FC}.
3344 // Store instructions store multiple structure to N registers like load.
3347 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3348 RegisterOperand VecList, string asmop>
3349 : NeonI_LdStMult<q, 1, opcode, size,
3350 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3351 asmop # "\t$Rt, [$Rn]",
3355 let neverHasSideEffects = 1;
3358 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3359 def _8B : NeonI_LDVList<0, opcode, 0b00,
3360 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3362 def _4H : NeonI_LDVList<0, opcode, 0b01,
3363 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3365 def _2S : NeonI_LDVList<0, opcode, 0b10,
3366 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3368 def _16B : NeonI_LDVList<1, opcode, 0b00,
3369 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3371 def _8H : NeonI_LDVList<1, opcode, 0b01,
3372 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3374 def _4S : NeonI_LDVList<1, opcode, 0b10,
3375 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3377 def _2D : NeonI_LDVList<1, opcode, 0b11,
3378 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3381 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3382 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3383 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3385 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3387 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3389 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3391 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3392 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3393 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3395 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3396 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3398 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3399 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3401 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3402 RegisterOperand VecList, string asmop>
3403 : NeonI_LdStMult<q, 0, opcode, size,
3404 (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3405 asmop # "\t$Rt, [$Rn]",
3409 let neverHasSideEffects = 1;
3412 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3413 def _8B : NeonI_STVList<0, opcode, 0b00,
3414 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3416 def _4H : NeonI_STVList<0, opcode, 0b01,
3417 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3419 def _2S : NeonI_STVList<0, opcode, 0b10,
3420 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3422 def _16B : NeonI_STVList<1, opcode, 0b00,
3423 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3425 def _8H : NeonI_STVList<1, opcode, 0b01,
3426 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3428 def _4S : NeonI_STVList<1, opcode, 0b10,
3429 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3431 def _2D : NeonI_STVList<1, opcode, 0b11,
3432 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3435 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3436 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3437 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3439 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3441 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3443 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3445 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3446 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3447 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3449 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3450 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3452 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3453 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3455 // End of vector load/store multiple N-element structure(class SIMD lselem)
3457 // The followings are post-index vector load/store multiple N-element
3458 // structure(class SIMD lselem-post)
3459 def exact1_asmoperand : AsmOperandClass {
3460 let Name = "Exact1";
3461 let PredicateMethod = "isExactImm<1>";
3462 let RenderMethod = "addImmOperands";
3464 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3465 let ParserMatchClass = exact1_asmoperand;
3468 def exact2_asmoperand : AsmOperandClass {
3469 let Name = "Exact2";
3470 let PredicateMethod = "isExactImm<2>";
3471 let RenderMethod = "addImmOperands";
3473 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3474 let ParserMatchClass = exact2_asmoperand;
3477 def exact3_asmoperand : AsmOperandClass {
3478 let Name = "Exact3";
3479 let PredicateMethod = "isExactImm<3>";
3480 let RenderMethod = "addImmOperands";
3482 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3483 let ParserMatchClass = exact3_asmoperand;
3486 def exact4_asmoperand : AsmOperandClass {
3487 let Name = "Exact4";
3488 let PredicateMethod = "isExactImm<4>";
3489 let RenderMethod = "addImmOperands";
3491 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3492 let ParserMatchClass = exact4_asmoperand;
3495 def exact6_asmoperand : AsmOperandClass {
3496 let Name = "Exact6";
3497 let PredicateMethod = "isExactImm<6>";
3498 let RenderMethod = "addImmOperands";
3500 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3501 let ParserMatchClass = exact6_asmoperand;
3504 def exact8_asmoperand : AsmOperandClass {
3505 let Name = "Exact8";
3506 let PredicateMethod = "isExactImm<8>";
3507 let RenderMethod = "addImmOperands";
3509 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3510 let ParserMatchClass = exact8_asmoperand;
3513 def exact12_asmoperand : AsmOperandClass {
3514 let Name = "Exact12";
3515 let PredicateMethod = "isExactImm<12>";
3516 let RenderMethod = "addImmOperands";
3518 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3519 let ParserMatchClass = exact12_asmoperand;
3522 def exact16_asmoperand : AsmOperandClass {
3523 let Name = "Exact16";
3524 let PredicateMethod = "isExactImm<16>";
3525 let RenderMethod = "addImmOperands";
3527 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3528 let ParserMatchClass = exact16_asmoperand;
3531 def exact24_asmoperand : AsmOperandClass {
3532 let Name = "Exact24";
3533 let PredicateMethod = "isExactImm<24>";
3534 let RenderMethod = "addImmOperands";
3536 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3537 let ParserMatchClass = exact24_asmoperand;
3540 def exact32_asmoperand : AsmOperandClass {
3541 let Name = "Exact32";
3542 let PredicateMethod = "isExactImm<32>";
3543 let RenderMethod = "addImmOperands";
3545 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3546 let ParserMatchClass = exact32_asmoperand;
3549 def exact48_asmoperand : AsmOperandClass {
3550 let Name = "Exact48";
3551 let PredicateMethod = "isExactImm<48>";
3552 let RenderMethod = "addImmOperands";
3554 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3555 let ParserMatchClass = exact48_asmoperand;
3558 def exact64_asmoperand : AsmOperandClass {
3559 let Name = "Exact64";
3560 let PredicateMethod = "isExactImm<64>";
3561 let RenderMethod = "addImmOperands";
3563 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3564 let ParserMatchClass = exact64_asmoperand;
3567 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3568 RegisterOperand VecList, Operand ImmTy,
3570 let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3571 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3572 def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3573 (outs VecList:$Rt, GPR64xsp:$wb),
3574 (ins GPR64xsp:$Rn, ImmTy:$amt),
3575 asmop # "\t$Rt, [$Rn], $amt",
3581 def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3582 (outs VecList:$Rt, GPR64xsp:$wb),
3583 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3584 asmop # "\t$Rt, [$Rn], $Rm",
3590 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3591 Operand ImmTy2, string asmop> {
3592 defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3593 !cast<RegisterOperand>(List # "8B_operand"),
3596 defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3597 !cast<RegisterOperand>(List # "4H_operand"),
3600 defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3601 !cast<RegisterOperand>(List # "2S_operand"),
3604 defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3605 !cast<RegisterOperand>(List # "16B_operand"),
3608 defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3609 !cast<RegisterOperand>(List # "8H_operand"),
3612 defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3613 !cast<RegisterOperand>(List # "4S_operand"),
3616 defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3617 !cast<RegisterOperand>(List # "2D_operand"),
3621 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3622 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3623 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3626 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3628 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3631 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3633 // Post-index load multiple 1-element structures from N consecutive registers
3635 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3637 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3638 uimm_exact16, "ld1">;
3640 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3642 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3643 uimm_exact24, "ld1">;
3645 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3647 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3648 uimm_exact32, "ld1">;
3650 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3651 RegisterOperand VecList, Operand ImmTy,
3653 let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3654 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3655 def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3656 (outs GPR64xsp:$wb),
3657 (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3658 asmop # "\t$Rt, [$Rn], $amt",
3664 def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3665 (outs GPR64xsp:$wb),
3666 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3667 asmop # "\t$Rt, [$Rn], $Rm",
3673 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3674 Operand ImmTy2, string asmop> {
3675 defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3676 !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3678 defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3679 !cast<RegisterOperand>(List # "4H_operand"),
3682 defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3683 !cast<RegisterOperand>(List # "2S_operand"),
3686 defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3687 !cast<RegisterOperand>(List # "16B_operand"),
3690 defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3691 !cast<RegisterOperand>(List # "8H_operand"),
3694 defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3695 !cast<RegisterOperand>(List # "4S_operand"),
3698 defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3699 !cast<RegisterOperand>(List # "2D_operand"),
3703 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3704 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3705 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3708 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3710 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3713 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3715 // Post-index load multiple 1-element structures from N consecutive registers
3717 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3719 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3720 uimm_exact16, "st1">;
3722 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3724 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3725 uimm_exact24, "st1">;
3727 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3729 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3730 uimm_exact32, "st1">;
3732 // End of post-index vector load/store multiple N-element structure
3733 // (class SIMD lselem-post)
3735 // The followings are vector load/store single N-element structure
3736 // (class SIMD lsone).
3737 def neon_uimm0_bare : Operand<i64>,
3738 ImmLeaf<i64, [{return Imm == 0;}]> {
3739 let ParserMatchClass = neon_uimm0_asmoperand;
3740 let PrintMethod = "printUImmBareOperand";
3743 def neon_uimm1_bare : Operand<i64>,
3744 ImmLeaf<i64, [{return Imm < 2;}]> {
3745 let ParserMatchClass = neon_uimm1_asmoperand;
3746 let PrintMethod = "printUImmBareOperand";
3749 def neon_uimm2_bare : Operand<i64>,
3750 ImmLeaf<i64, [{return Imm < 4;}]> {
3751 let ParserMatchClass = neon_uimm2_asmoperand;
3752 let PrintMethod = "printUImmBareOperand";
3755 def neon_uimm3_bare : Operand<i64>,
3756 ImmLeaf<i64, [{return Imm < 8;}]> {
3757 let ParserMatchClass = uimm3_asmoperand;
3758 let PrintMethod = "printUImmBareOperand";
3761 def neon_uimm4_bare : Operand<i64>,
3762 ImmLeaf<i64, [{return Imm < 16;}]> {
3763 let ParserMatchClass = uimm4_asmoperand;
3764 let PrintMethod = "printUImmBareOperand";
3767 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3768 RegisterOperand VecList, string asmop>
3769 : NeonI_LdOne_Dup<q, r, opcode, size,
3770 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3771 asmop # "\t$Rt, [$Rn]",
3775 let neverHasSideEffects = 1;
3778 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3779 def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3780 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3782 def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3783 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3785 def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3786 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3788 def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3789 !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3791 def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3792 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3794 def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3795 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3797 def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3798 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3800 def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3801 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3804 // Load single 1-element structure to all lanes of 1 register
3805 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3807 // Load single N-element structure to all lanes of N consecutive
3808 // registers (N = 2,3,4)
3809 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3810 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3811 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3814 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3816 : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3817 (VTy (INST GPR64xsp:$Rn))>;
3819 // Match all LD1R instructions
3820 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3822 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3824 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3826 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3828 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3829 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3831 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3832 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3834 def : LD1R_pattern<v1i64, i64, load, LD1R_1D>;
3835 def : LD1R_pattern<v1f64, f64, load, LD1R_1D>;
3837 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3838 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3841 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3842 RegisterClass RegList> {
3843 defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3844 defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3845 defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3846 defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3849 // Special vector list operand of 128-bit vectors with bare layout.
3850 // i.e. only show ".b", ".h", ".s", ".d"
3851 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3852 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3853 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3854 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3856 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3857 Operand ImmOp, string asmop>
3858 : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3860 (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3861 asmop # "\t$Rt[$lane], [$Rn]",
3865 let neverHasSideEffects = 1;
3866 let hasExtraDefRegAllocReq = 1;
3867 let Constraints = "$src = $Rt";
3870 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3871 def _B : NeonI_LDN_Lane<r, 0b00, op0,
3872 !cast<RegisterOperand>(List # "B_operand"),
3873 neon_uimm4_bare, asmop> {
3874 let Inst{12-10} = lane{2-0};
3875 let Inst{30} = lane{3};
3878 def _H : NeonI_LDN_Lane<r, 0b01, op0,
3879 !cast<RegisterOperand>(List # "H_operand"),
3880 neon_uimm3_bare, asmop> {
3881 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3882 let Inst{30} = lane{2};
3885 def _S : NeonI_LDN_Lane<r, 0b10, op0,
3886 !cast<RegisterOperand>(List # "S_operand"),
3887 neon_uimm2_bare, asmop> {
3888 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3889 let Inst{30} = lane{1};
3892 def _D : NeonI_LDN_Lane<r, 0b10, op0,
3893 !cast<RegisterOperand>(List # "D_operand"),
3894 neon_uimm1_bare, asmop> {
3895 let Inst{12-10} = 0b001;
3896 let Inst{30} = lane{0};
3900 // Load single 1-element structure to one lane of 1 register.
3901 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3903 // Load single N-element structure to one lane of N consecutive registers
3905 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3906 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3907 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3909 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3910 Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3912 def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3913 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3914 (VTy (EXTRACT_SUBREG
3916 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3920 def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3921 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3922 (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3925 // Match all LD1LN instructions
3926 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3927 extloadi8, LD1LN_B>;
3929 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3930 extloadi16, LD1LN_H>;
3932 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3934 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3937 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3939 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3942 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3943 Operand ImmOp, string asmop>
3944 : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3945 (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3946 asmop # "\t$Rt[$lane], [$Rn]",
3950 let neverHasSideEffects = 1;
3951 let hasExtraDefRegAllocReq = 1;
3954 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3955 def _B : NeonI_STN_Lane<r, 0b00, op0,
3956 !cast<RegisterOperand>(List # "B_operand"),
3957 neon_uimm4_bare, asmop> {
3958 let Inst{12-10} = lane{2-0};
3959 let Inst{30} = lane{3};
3962 def _H : NeonI_STN_Lane<r, 0b01, op0,
3963 !cast<RegisterOperand>(List # "H_operand"),
3964 neon_uimm3_bare, asmop> {
3965 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3966 let Inst{30} = lane{2};
3969 def _S : NeonI_STN_Lane<r, 0b10, op0,
3970 !cast<RegisterOperand>(List # "S_operand"),
3971 neon_uimm2_bare, asmop> {
3972 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3973 let Inst{30} = lane{1};
3976 def _D : NeonI_STN_Lane<r, 0b10, op0,
3977 !cast<RegisterOperand>(List # "D_operand"),
3978 neon_uimm1_bare, asmop>{
3979 let Inst{12-10} = 0b001;
3980 let Inst{30} = lane{0};
3984 // Store single 1-element structure from one lane of 1 register.
3985 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3987 // Store single N-element structure from one lane of N consecutive registers
3989 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3990 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3991 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3993 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3994 Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3996 def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3999 (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
4002 def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
4004 (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
4007 // Match all ST1LN instructions
4008 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
4009 truncstorei8, ST1LN_B>;
4011 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
4012 truncstorei16, ST1LN_H>;
4014 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
4016 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
4019 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
4021 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
4024 // End of vector load/store single N-element structure (class SIMD lsone).
4027 // The following are post-index load/store single N-element instructions
4028 // (class SIMD lsone-post)
4030 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
4031 RegisterOperand VecList, Operand ImmTy,
4033 let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
4034 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4035 def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4036 (outs VecList:$Rt, GPR64xsp:$wb),
4037 (ins GPR64xsp:$Rn, ImmTy:$amt),
4038 asmop # "\t$Rt, [$Rn], $amt",
4044 def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4045 (outs VecList:$Rt, GPR64xsp:$wb),
4046 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
4047 asmop # "\t$Rt, [$Rn], $Rm",
4053 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
4054 Operand uimm_b, Operand uimm_h,
4055 Operand uimm_s, Operand uimm_d> {
4056 defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
4057 !cast<RegisterOperand>(List # "8B_operand"),
4060 defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
4061 !cast<RegisterOperand>(List # "4H_operand"),
4064 defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
4065 !cast<RegisterOperand>(List # "2S_operand"),
4068 defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
4069 !cast<RegisterOperand>(List # "1D_operand"),
4072 defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
4073 !cast<RegisterOperand>(List # "16B_operand"),
4076 defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
4077 !cast<RegisterOperand>(List # "8H_operand"),
4080 defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
4081 !cast<RegisterOperand>(List # "4S_operand"),
4084 defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
4085 !cast<RegisterOperand>(List # "2D_operand"),
4089 // Post-index load single 1-element structure to all lanes of 1 register
4090 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
4091 uimm_exact2, uimm_exact4, uimm_exact8>;
4093 // Post-index load single N-element structure to all lanes of N consecutive
4094 // registers (N = 2,3,4)
4095 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
4096 uimm_exact4, uimm_exact8, uimm_exact16>;
4097 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
4098 uimm_exact6, uimm_exact12, uimm_exact24>;
4099 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
4100 uimm_exact8, uimm_exact16, uimm_exact32>;
4102 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
4103 Constraints = "$Rn = $wb, $Rt = $src",
4104 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4105 class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4106 Operand ImmTy, Operand ImmOp, string asmop>
4107 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4108 (outs VList:$Rt, GPR64xsp:$wb),
4109 (ins GPR64xsp:$Rn, ImmTy:$amt,
4110 VList:$src, ImmOp:$lane),
4111 asmop # "\t$Rt[$lane], [$Rn], $amt",
4117 class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4118 Operand ImmTy, Operand ImmOp, string asmop>
4119 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4120 (outs VList:$Rt, GPR64xsp:$wb),
4121 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
4122 VList:$src, ImmOp:$lane),
4123 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4128 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4129 Operand uimm_b, Operand uimm_h,
4130 Operand uimm_s, Operand uimm_d> {
4131 def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
4132 !cast<RegisterOperand>(List # "B_operand"),
4133 uimm_b, neon_uimm4_bare, asmop> {
4134 let Inst{12-10} = lane{2-0};
4135 let Inst{30} = lane{3};
4138 def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
4139 !cast<RegisterOperand>(List # "B_operand"),
4140 uimm_b, neon_uimm4_bare, asmop> {
4141 let Inst{12-10} = lane{2-0};
4142 let Inst{30} = lane{3};
4145 def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
4146 !cast<RegisterOperand>(List # "H_operand"),
4147 uimm_h, neon_uimm3_bare, asmop> {
4148 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4149 let Inst{30} = lane{2};
4152 def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
4153 !cast<RegisterOperand>(List # "H_operand"),
4154 uimm_h, neon_uimm3_bare, asmop> {
4155 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4156 let Inst{30} = lane{2};
4159 def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4160 !cast<RegisterOperand>(List # "S_operand"),
4161 uimm_s, neon_uimm2_bare, asmop> {
4162 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4163 let Inst{30} = lane{1};
4166 def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
4167 !cast<RegisterOperand>(List # "S_operand"),
4168 uimm_s, neon_uimm2_bare, asmop> {
4169 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4170 let Inst{30} = lane{1};
4173 def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4174 !cast<RegisterOperand>(List # "D_operand"),
4175 uimm_d, neon_uimm1_bare, asmop> {
4176 let Inst{12-10} = 0b001;
4177 let Inst{30} = lane{0};
4180 def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
4181 !cast<RegisterOperand>(List # "D_operand"),
4182 uimm_d, neon_uimm1_bare, asmop> {
4183 let Inst{12-10} = 0b001;
4184 let Inst{30} = lane{0};
4188 // Post-index load single 1-element structure to one lane of 1 register.
4189 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
4190 uimm_exact2, uimm_exact4, uimm_exact8>;
4192 // Post-index load single N-element structure to one lane of N consecutive
4195 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
4196 uimm_exact4, uimm_exact8, uimm_exact16>;
4197 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
4198 uimm_exact6, uimm_exact12, uimm_exact24>;
4199 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
4200 uimm_exact8, uimm_exact16, uimm_exact32>;
4202 let mayStore = 1, neverHasSideEffects = 1,
4203 hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
4204 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4205 class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4206 Operand ImmTy, Operand ImmOp, string asmop>
4207 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4208 (outs GPR64xsp:$wb),
4209 (ins GPR64xsp:$Rn, ImmTy:$amt,
4210 VList:$Rt, ImmOp:$lane),
4211 asmop # "\t$Rt[$lane], [$Rn], $amt",
4217 class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4218 Operand ImmTy, Operand ImmOp, string asmop>
4219 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4220 (outs GPR64xsp:$wb),
4221 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4223 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4228 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4229 Operand uimm_b, Operand uimm_h,
4230 Operand uimm_s, Operand uimm_d> {
4231 def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4232 !cast<RegisterOperand>(List # "B_operand"),
4233 uimm_b, neon_uimm4_bare, asmop> {
4234 let Inst{12-10} = lane{2-0};
4235 let Inst{30} = lane{3};
4238 def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4239 !cast<RegisterOperand>(List # "B_operand"),
4240 uimm_b, neon_uimm4_bare, asmop> {
4241 let Inst{12-10} = lane{2-0};
4242 let Inst{30} = lane{3};
4245 def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4246 !cast<RegisterOperand>(List # "H_operand"),
4247 uimm_h, neon_uimm3_bare, asmop> {
4248 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4249 let Inst{30} = lane{2};
4252 def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4253 !cast<RegisterOperand>(List # "H_operand"),
4254 uimm_h, neon_uimm3_bare, asmop> {
4255 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4256 let Inst{30} = lane{2};
4259 def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4260 !cast<RegisterOperand>(List # "S_operand"),
4261 uimm_s, neon_uimm2_bare, asmop> {
4262 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4263 let Inst{30} = lane{1};
4266 def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4267 !cast<RegisterOperand>(List # "S_operand"),
4268 uimm_s, neon_uimm2_bare, asmop> {
4269 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4270 let Inst{30} = lane{1};
4273 def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4274 !cast<RegisterOperand>(List # "D_operand"),
4275 uimm_d, neon_uimm1_bare, asmop> {
4276 let Inst{12-10} = 0b001;
4277 let Inst{30} = lane{0};
4280 def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4281 !cast<RegisterOperand>(List # "D_operand"),
4282 uimm_d, neon_uimm1_bare, asmop> {
4283 let Inst{12-10} = 0b001;
4284 let Inst{30} = lane{0};
4288 // Post-index store single 1-element structure from one lane of 1 register.
4289 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4290 uimm_exact2, uimm_exact4, uimm_exact8>;
4292 // Post-index store single N-element structure from one lane of N consecutive
4293 // registers (N = 2,3,4)
4294 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4295 uimm_exact4, uimm_exact8, uimm_exact16>;
4296 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4297 uimm_exact6, uimm_exact12, uimm_exact24>;
4298 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4299 uimm_exact8, uimm_exact16, uimm_exact32>;
4301 // End of post-index load/store single N-element instructions
4302 // (class SIMD lsone-post)
4304 // Neon Scalar instructions implementation
4305 // Scalar Three Same
4307 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4309 : NeonI_Scalar3Same<u, size, opcode,
4310 (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4311 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4315 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4316 : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4318 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4319 bit Commutable = 0> {
4320 let isCommutable = Commutable in {
4321 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4322 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4326 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4327 string asmop, bit Commutable = 0> {
4328 let isCommutable = Commutable in {
4329 def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4330 def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4334 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4335 string asmop, bit Commutable = 0> {
4336 let isCommutable = Commutable in {
4337 def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4338 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4339 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4340 def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4344 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4345 Instruction INSTD> {
4346 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4347 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4350 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4355 : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4356 def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4357 (INSTB FPR8:$Rn, FPR8:$Rm)>;
4359 def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4360 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4362 def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4363 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4366 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
4368 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4369 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4371 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4373 Instruction INSTS> {
4374 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4375 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4376 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4377 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4380 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4382 Instruction INSTD> {
4383 def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4384 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4385 def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4386 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4389 multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
4391 Instruction INSTD> {
4392 def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4393 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4394 def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4395 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4398 // Scalar Three Different
4400 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4401 RegisterClass FPRCD, RegisterClass FPRCS>
4402 : NeonI_Scalar3Diff<u, size, opcode,
4403 (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4404 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4408 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4409 def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4410 def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4413 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4414 let Constraints = "$Src = $Rd" in {
4415 def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4416 (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4417 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4420 def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4421 (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4422 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4428 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4430 Instruction INSTS> {
4431 def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4432 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4433 def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4434 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4437 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4439 Instruction INSTS> {
4440 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4441 (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4442 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4443 (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4446 // Scalar Two Registers Miscellaneous
4448 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4449 RegisterClass FPRCD, RegisterClass FPRCS>
4450 : NeonI_Scalar2SameMisc<u, size, opcode,
4451 (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4452 !strconcat(asmop, "\t$Rd, $Rn"),
4456 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4458 def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4460 def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4464 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4465 def dd: NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4468 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4469 : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4470 def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4471 def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4472 def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4475 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4477 def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4478 def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4479 def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4482 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4483 string asmop, RegisterClass FPRC>
4484 : NeonI_Scalar2SameMisc<u, size, opcode,
4485 (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4486 !strconcat(asmop, "\t$Rd, $Rn"),
4490 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4493 let Constraints = "$Src = $Rd" in {
4494 def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4495 def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4496 def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4497 def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4501 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator Sopnode,
4502 SDPatternOperator Dopnode,
4504 Instruction INSTD> {
4505 def : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn))),
4507 def : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn))),
4511 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4513 Instruction INSTD> {
4514 def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn))),
4516 def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4520 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4521 : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4522 (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4523 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4527 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4529 def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4530 (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4531 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4534 def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4535 (outs FPR64:$Rd), (ins FPR64:$Rn, fpz64movi:$FPImm),
4536 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4541 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4543 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4544 (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4545 (INSTD FPR64:$Rn, 0)>;
4547 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4549 Instruction INSTD> {
4550 def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
4551 (v1f32 (scalar_to_vector (f32 fpimm:$FPImm))))),
4552 (INSTS FPR32:$Rn, fpimm:$FPImm)>;
4553 def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
4554 (v1f64 (bitconvert (v8i8 Neon_AllZero))))),
4555 (INSTD FPR64:$Rn, 0)>;
4558 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4559 Instruction INSTD> {
4560 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4564 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4569 : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4570 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4572 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4574 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4578 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4579 SDPatternOperator opnode,
4582 Instruction INSTD> {
4583 def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4585 def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4587 def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4592 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4593 SDPatternOperator opnode,
4597 Instruction INSTD> {
4598 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4599 (INSTB FPR8:$Src, FPR8:$Rn)>;
4600 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4601 (INSTH FPR16:$Src, FPR16:$Rn)>;
4602 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4603 (INSTS FPR32:$Src, FPR32:$Rn)>;
4604 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4605 (INSTD FPR64:$Src, FPR64:$Rn)>;
4608 // Scalar Shift By Immediate
4610 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4611 RegisterClass FPRC, Operand ImmTy>
4612 : NeonI_ScalarShiftImm<u, opcode,
4613 (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4614 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4617 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4619 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4621 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4622 let Inst{21-16} = Imm;
4626 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4628 : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4629 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4631 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4632 let Inst{18-16} = Imm;
4634 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4636 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4637 let Inst{19-16} = Imm;
4639 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4641 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4642 let Inst{20-16} = Imm;
4646 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4648 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4650 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4651 let Inst{21-16} = Imm;
4655 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4657 : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4658 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4660 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4661 let Inst{18-16} = Imm;
4663 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4665 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4666 let Inst{19-16} = Imm;
4668 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4670 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4671 let Inst{20-16} = Imm;
4675 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4676 : NeonI_ScalarShiftImm<u, opcode,
4677 (outs FPR64:$Rd), (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4678 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4681 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4682 let Inst{21-16} = Imm;
4683 let Constraints = "$Src = $Rd";
4686 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4687 : NeonI_ScalarShiftImm<u, opcode,
4688 (outs FPR64:$Rd), (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4689 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4692 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4693 let Inst{21-16} = Imm;
4694 let Constraints = "$Src = $Rd";
4697 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4698 RegisterClass FPRCD, RegisterClass FPRCS,
4700 : NeonI_ScalarShiftImm<u, opcode,
4701 (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4702 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4705 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4707 def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4710 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4711 let Inst{18-16} = Imm;
4713 def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4716 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4717 let Inst{19-16} = Imm;
4719 def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4722 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4723 let Inst{20-16} = Imm;
4727 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4728 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4730 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4731 let Inst{20-16} = Imm;
4733 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4735 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4736 let Inst{21-16} = Imm;
4740 multiclass Neon_ScalarShiftImm_D_size_patterns<SDPatternOperator opnode,
4741 Instruction INSTD> {
4742 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4743 (INSTD FPR64:$Rn, imm:$Imm)>;
4746 class Neon_ScalarShiftImm_arm_D_size_patterns<SDPatternOperator opnode,
4748 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 (Neon_vdup (i32 imm:$Imm))))),
4749 (INSTD FPR64:$Rn, imm:$Imm)>;
4751 multiclass Neon_ScalarShiftImm_BHSD_size_patterns<SDPatternOperator opnode,
4756 : Neon_ScalarShiftImm_D_size_patterns<opnode, INSTD> {
4757 def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 imm:$Imm))),
4758 (INSTB FPR8:$Rn, imm:$Imm)>;
4759 def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 imm:$Imm))),
4760 (INSTH FPR16:$Rn, imm:$Imm)>;
4761 def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4762 (INSTS FPR32:$Rn, imm:$Imm)>;
4765 class Neon_ScalarShiftImm_accum_D_size_patterns<SDPatternOperator opnode,
4767 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4768 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4770 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4771 SDPatternOperator opnode,
4774 Instruction INSTD> {
4775 def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 imm:$Imm))),
4776 (INSTH FPR16:$Rn, imm:$Imm)>;
4777 def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4778 (INSTS FPR32:$Rn, imm:$Imm)>;
4779 def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4780 (INSTD FPR64:$Rn, imm:$Imm)>;
4783 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator Sopnode,
4784 SDPatternOperator Dopnode,
4786 Instruction INSTD> {
4787 def ssi : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4788 (INSTS FPR32:$Rn, imm:$Imm)>;
4789 def ddi : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4790 (INSTD FPR64:$Rn, imm:$Imm)>;
4793 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator Sopnode,
4794 SDPatternOperator Dopnode,
4796 Instruction INSTD> {
4797 def ssi : Pat<(v1i32 (Sopnode (v1f32 FPR32:$Rn), (i32 imm:$Imm))),
4798 (INSTS FPR32:$Rn, imm:$Imm)>;
4799 def ddi : Pat<(v1i64 (Dopnode (v1f64 FPR64:$Rn), (i32 imm:$Imm))),
4800 (INSTD FPR64:$Rn, imm:$Imm)>;
4803 // Scalar Signed Shift Right (Immediate)
4804 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4805 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4806 // Pattern to match llvm.arm.* intrinsic.
4807 def : Neon_ScalarShiftImm_arm_D_size_patterns<sra, SSHRddi>;
4809 // Scalar Unsigned Shift Right (Immediate)
4810 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4811 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4812 // Pattern to match llvm.arm.* intrinsic.
4813 def : Neon_ScalarShiftImm_arm_D_size_patterns<srl, USHRddi>;
4815 // Scalar Signed Rounding Shift Right (Immediate)
4816 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4817 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4819 // Scalar Unigned Rounding Shift Right (Immediate)
4820 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4821 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4823 // Scalar Signed Shift Right and Accumulate (Immediate)
4824 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4825 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsrads_n, SSRA>;
4827 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4828 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4829 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsradu_n, USRA>;
4831 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4832 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4833 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vrsrads_n, SRSRA>;
4835 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4836 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4837 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vrsradu_n, URSRA>;
4839 // Scalar Shift Left (Immediate)
4840 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4841 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4842 // Pattern to match llvm.arm.* intrinsic.
4843 def : Neon_ScalarShiftImm_arm_D_size_patterns<shl, SHLddi>;
4845 // Signed Saturating Shift Left (Immediate)
4846 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4847 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4849 SQSHLssi, SQSHLddi>;
4850 // Pattern to match llvm.arm.* intrinsic.
4851 defm : Neon_ScalarShiftImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4853 // Unsigned Saturating Shift Left (Immediate)
4854 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4855 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4857 UQSHLssi, UQSHLddi>;
4858 // Pattern to match llvm.arm.* intrinsic.
4859 defm : Neon_ScalarShiftImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4861 // Signed Saturating Shift Left Unsigned (Immediate)
4862 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4863 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4864 SQSHLUbbi, SQSHLUhhi,
4865 SQSHLUssi, SQSHLUddi>;
4867 // Shift Right And Insert (Immediate)
4868 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4869 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsri, SRI>;
4871 // Shift Left And Insert (Immediate)
4872 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4873 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsli, SLI>;
4875 // Signed Saturating Shift Right Narrow (Immediate)
4876 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4877 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4878 SQSHRNbhi, SQSHRNhsi,
4881 // Unsigned Saturating Shift Right Narrow (Immediate)
4882 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4883 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4884 UQSHRNbhi, UQSHRNhsi,
4887 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4888 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4889 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4890 SQRSHRNbhi, SQRSHRNhsi,
4893 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4894 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4895 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4896 UQRSHRNbhi, UQRSHRNhsi,
4899 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4900 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4901 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4902 SQSHRUNbhi, SQSHRUNhsi,
4905 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4906 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4907 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4908 SQRSHRUNbhi, SQRSHRUNhsi,
4911 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4912 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4913 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_s32,
4914 int_aarch64_neon_vcvtf64_n_s64,
4915 SCVTF_Nssi, SCVTF_Nddi>;
4917 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4918 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4919 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_u32,
4920 int_aarch64_neon_vcvtf64_n_u64,
4921 UCVTF_Nssi, UCVTF_Nddi>;
4923 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4924 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4925 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_s32_f32,
4926 int_aarch64_neon_vcvtd_n_s64_f64,
4927 FCVTZS_Nssi, FCVTZS_Nddi>;
4929 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4930 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4931 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_u32_f32,
4932 int_aarch64_neon_vcvtd_n_u64_f64,
4933 FCVTZU_Nssi, FCVTZU_Nddi>;
4935 // Scalar Integer Add
4936 let isCommutable = 1 in {
4937 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4940 // Scalar Integer Sub
4941 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4943 // Pattern for Scalar Integer Add and Sub with D register only
4944 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4945 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4947 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4948 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4949 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4950 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4951 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4953 // Scalar Integer Saturating Add (Signed, Unsigned)
4954 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4955 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4957 // Scalar Integer Saturating Sub (Signed, Unsigned)
4958 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4959 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4961 // Patterns to match llvm.arm.* intrinsic for
4962 // Scalar Integer Saturating Add, Sub (Signed, Unsigned)
4963 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqadds, SQADDddd>;
4964 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqaddu, UQADDddd>;
4965 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubs, SQSUBddd>;
4966 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubu, UQSUBddd>;
4968 // Patterns to match llvm.aarch64.* intrinsic for
4969 // Scalar Integer Saturating Add, Sub (Signed, Unsigned)
4970 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqadds, SQADDbbb,
4971 SQADDhhh, SQADDsss, SQADDddd>;
4972 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqaddu, UQADDbbb,
4973 UQADDhhh, UQADDsss, UQADDddd>;
4974 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubs, SQSUBbbb,
4975 SQSUBhhh, SQSUBsss, SQSUBddd>;
4976 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubu, UQSUBbbb,
4977 UQSUBhhh, UQSUBsss, UQSUBddd>;
4979 // Scalar Integer Saturating Doubling Multiply Half High
4980 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
4982 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4983 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
4985 // Patterns to match llvm.arm.* intrinsic for
4986 // Scalar Integer Saturating Doubling Multiply Half High and
4987 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4988 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
4990 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
4993 // Scalar Floating-point Multiply Extended
4994 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
4996 // Scalar Floating-point Reciprocal Step
4997 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
4999 // Scalar Floating-point Reciprocal Square Root Step
5000 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
5002 // Patterns to match llvm.arm.* intrinsic for
5003 // Scalar Floating-point Reciprocal Step and
5004 // Scalar Floating-point Reciprocal Square Root Step
5005 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss,
5007 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
5010 // Patterns to match llvm.aarch64.* intrinsic for
5011 // Scalar Floating-point Multiply Extended,
5012 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
5014 Instruction INSTD> {
5015 def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
5016 (INSTS FPR32:$Rn, FPR32:$Rm)>;
5017 def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
5018 (INSTD FPR64:$Rn, FPR64:$Rm)>;
5021 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
5024 // Scalar Integer Shift Left (Signed, Unsigned)
5025 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
5026 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
5028 // Patterns to match llvm.arm.* intrinsic for
5029 // Scalar Integer Shift Left (Signed, Unsigned)
5030 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
5031 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
5033 // Patterns to match llvm.aarch64.* intrinsic for
5034 // Scalar Integer Shift Left (Signed, Unsigned)
5035 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
5036 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
5038 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
5039 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
5040 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
5042 // Patterns to match llvm.aarch64.* intrinsic for
5043 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
5044 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
5045 SQSHLhhh, SQSHLsss, SQSHLddd>;
5046 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
5047 UQSHLhhh, UQSHLsss, UQSHLddd>;
5049 // Patterns to match llvm.arm.* intrinsic for
5050 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
5051 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
5052 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
5054 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5055 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
5056 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
5058 // Patterns to match llvm.aarch64.* intrinsic for
5059 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5060 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
5061 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
5063 // Patterns to match llvm.arm.* intrinsic for
5064 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5065 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
5066 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
5068 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5069 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
5070 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
5072 // Patterns to match llvm.aarch64.* intrinsic for
5073 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5074 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
5075 SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
5076 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
5077 UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
5079 // Patterns to match llvm.arm.* intrinsic for
5080 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5081 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
5082 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
5084 // Signed Saturating Doubling Multiply-Add Long
5085 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
5086 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
5087 SQDMLALshh, SQDMLALdss>;
5089 // Signed Saturating Doubling Multiply-Subtract Long
5090 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
5091 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
5092 SQDMLSLshh, SQDMLSLdss>;
5094 // Signed Saturating Doubling Multiply Long
5095 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
5096 defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmull,
5097 SQDMULLshh, SQDMULLdss>;
5099 // Scalar Signed Integer Convert To Floating-point
5100 defm SCVTF : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
5101 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,
5102 int_aarch64_neon_vcvtf64_s64,
5105 // Scalar Unsigned Integer Convert To Floating-point
5106 defm UCVTF : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
5107 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_u32,
5108 int_aarch64_neon_vcvtf64_u64,
5111 // Scalar Floating-point Reciprocal Estimate
5112 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5113 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrecpe,
5114 FRECPEss, FRECPEdd>;
5116 // Scalar Floating-point Reciprocal Exponent
5117 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5118 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5119 FRECPXss, FRECPXdd>;
5121 // Scalar Floating-point Reciprocal Square Root Estimate
5122 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5123 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrsqrte,
5124 FRSQRTEss, FRSQRTEdd>;
5126 // Scalar Integer Compare
5128 // Scalar Compare Bitwise Equal
5129 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5130 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5132 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5135 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5136 (INSTD FPR64:$Rn, FPR64:$Rm)>;
5138 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5140 // Scalar Compare Signed Greather Than Or Equal
5141 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5142 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5144 // Scalar Compare Unsigned Higher Or Same
5145 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5146 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5148 // Scalar Compare Unsigned Higher
5149 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5150 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5152 // Scalar Compare Signed Greater Than
5153 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5154 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5156 // Scalar Compare Bitwise Test Bits
5157 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5158 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5159 def : Neon_Scalar3Same_cmp_D_size_patterns<Neon_tst, CMTSTddd>;
5161 // Scalar Compare Bitwise Equal To Zero
5162 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5163 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5166 // Scalar Compare Signed Greather Than Or Equal To Zero
5167 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5168 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5171 // Scalar Compare Signed Greater Than Zero
5172 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5173 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5176 // Scalar Compare Signed Less Than Or Equal To Zero
5177 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5178 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5181 // Scalar Compare Less Than Zero
5182 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5183 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5186 // Scalar Floating-point Compare
5188 // Scalar Floating-point Compare Mask Equal
5189 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5190 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vceq,
5191 FCMEQsss, FCMEQddd>;
5193 // Scalar Floating-point Compare Mask Equal To Zero
5194 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5195 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
5196 FCMEQZssi, FCMEQZddi>;
5198 // Scalar Floating-point Compare Mask Greater Than Or Equal
5199 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5200 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcge,
5201 FCMGEsss, FCMGEddd>;
5203 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5204 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5205 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcge,
5206 FCMGEZssi, FCMGEZddi>;
5208 // Scalar Floating-point Compare Mask Greather Than
5209 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5210 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcgt,
5211 FCMGTsss, FCMGTddd>;
5213 // Scalar Floating-point Compare Mask Greather Than Zero
5214 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5215 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcgt,
5216 FCMGTZssi, FCMGTZddi>;
5218 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5219 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5220 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vclez,
5221 FCMLEZssi, FCMLEZddi>;
5223 // Scalar Floating-point Compare Mask Less Than Zero
5224 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5225 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcltz,
5226 FCMLTZssi, FCMLTZddi>;
5228 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5229 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5230 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcage,
5231 FACGEsss, FACGEddd>;
5233 // Scalar Floating-point Absolute Compare Mask Greater Than
5234 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5235 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcagt,
5236 FACGTsss, FACGTddd>;
5238 // Scalar Absolute Value
5239 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5240 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5242 // Scalar Signed Saturating Absolute Value
5243 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5244 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5245 SQABSbb, SQABShh, SQABSss, SQABSdd>;
5248 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5249 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5251 // Scalar Signed Saturating Negate
5252 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5253 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5254 SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5256 // Scalar Signed Saturating Accumulated of Unsigned Value
5257 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5258 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5260 SUQADDss, SUQADDdd>;
5262 // Scalar Unsigned Saturating Accumulated of Signed Value
5263 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5264 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5266 USQADDss, USQADDdd>;
5268 // Scalar Signed Saturating Extract Unsigned Narrow
5269 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5270 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5274 // Scalar Signed Saturating Extract Narrow
5275 defm SQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5276 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5280 // Scalar Unsigned Saturating Extract Narrow
5281 defm UQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5282 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5286 // Scalar Reduce Pairwise
5288 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5289 string asmop, bit Commutable = 0> {
5290 let isCommutable = Commutable in {
5291 def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5292 (outs FPR64:$Rd), (ins VPR128:$Rn),
5293 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5299 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5300 string asmop, bit Commutable = 0>
5301 : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5302 let isCommutable = Commutable in {
5303 def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5304 (outs FPR32:$Rd), (ins VPR64:$Rn),
5305 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5311 // Scalar Reduce Addition Pairwise (Integer) with
5312 // Pattern to match llvm.arm.* intrinsic
5313 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5315 // Pattern to match llvm.aarch64.* intrinsic for
5316 // Scalar Reduce Addition Pairwise (Integer)
5317 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5318 (ADDPvv_D_2D VPR128:$Rn)>;
5320 // Scalar Reduce Addition Pairwise (Floating Point)
5321 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5323 // Scalar Reduce Maximum Pairwise (Floating Point)
5324 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5326 // Scalar Reduce Minimum Pairwise (Floating Point)
5327 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5329 // Scalar Reduce maxNum Pairwise (Floating Point)
5330 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5332 // Scalar Reduce minNum Pairwise (Floating Point)
5333 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5335 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnodeS,
5336 SDPatternOperator opnodeD,
5338 Instruction INSTD> {
5339 def : Pat<(v1f32 (opnodeS (v2f32 VPR64:$Rn))),
5341 def : Pat<(v1f64 (opnodeD (v2f64 VPR128:$Rn))),
5342 (INSTD VPR128:$Rn)>;
5345 // Patterns to match llvm.aarch64.* intrinsic for
5346 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5347 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5348 int_aarch64_neon_vpfaddq, FADDPvv_S_2S, FADDPvv_D_2D>;
5350 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5351 int_aarch64_neon_vpmaxq, FMAXPvv_S_2S, FMAXPvv_D_2D>;
5353 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5354 int_aarch64_neon_vpminq, FMINPvv_S_2S, FMINPvv_D_2D>;
5356 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5357 int_aarch64_neon_vpfmaxnmq, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5359 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5360 int_aarch64_neon_vpfminnmq, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5363 // Scalar by element Arithmetic
5365 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5366 string rmlane, bit u, bit szhi, bit szlo,
5367 RegisterClass ResFPR, RegisterClass OpFPR,
5368 RegisterOperand OpVPR, Operand OpImm>
5369 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5371 (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5372 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5379 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5381 bit u, bit szhi, bit szlo,
5382 RegisterClass ResFPR,
5383 RegisterClass OpFPR,
5384 RegisterOperand OpVPR,
5386 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5388 (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5389 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5392 let Constraints = "$src = $Rd";
5397 // Scalar Floating Point multiply (scalar, by element)
5398 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5399 0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5400 let Inst{11} = Imm{1}; // h
5401 let Inst{21} = Imm{0}; // l
5402 let Inst{20-16} = MRm;
5404 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5405 0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5406 let Inst{11} = Imm{0}; // h
5407 let Inst{21} = 0b0; // l
5408 let Inst{20-16} = MRm;
5411 // Scalar Floating Point multiply extended (scalar, by element)
5412 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5413 0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5414 let Inst{11} = Imm{1}; // h
5415 let Inst{21} = Imm{0}; // l
5416 let Inst{20-16} = MRm;
5418 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5419 0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5420 let Inst{11} = Imm{0}; // h
5421 let Inst{21} = 0b0; // l
5422 let Inst{20-16} = MRm;
5425 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5426 SDPatternOperator opnode,
5428 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5429 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5431 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5432 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5433 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5435 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5436 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5437 (ResTy (INST (ResTy FPRC:$Rn),
5438 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5442 def : Pat<(ResTy (opnode
5443 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5445 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5447 def : Pat<(ResTy (opnode
5448 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5450 (ResTy (INST (ResTy FPRC:$Rn),
5451 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5455 // Patterns for Scalar Floating Point multiply (scalar, by element)
5456 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5457 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5458 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5459 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5461 // Patterns for Scalar Floating Point multiply extended (scalar, by element)
5462 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5463 FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5464 v2f32, v4f32, neon_uimm1_bare>;
5465 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5466 FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5467 v1f64, v2f64, neon_uimm0_bare>;
5470 // Scalar Floating Point fused multiply-add (scalar, by element)
5471 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5472 0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5473 let Inst{11} = Imm{1}; // h
5474 let Inst{21} = Imm{0}; // l
5475 let Inst{20-16} = MRm;
5477 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5478 0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5479 let Inst{11} = Imm{0}; // h
5480 let Inst{21} = 0b0; // l
5481 let Inst{20-16} = MRm;
5484 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5485 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5486 0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5487 let Inst{11} = Imm{1}; // h
5488 let Inst{21} = Imm{0}; // l
5489 let Inst{20-16} = MRm;
5491 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5492 0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5493 let Inst{11} = Imm{0}; // h
5494 let Inst{21} = 0b0; // l
5495 let Inst{20-16} = MRm;
5497 // We are allowed to match the fma instruction regardless of compile options.
5498 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5499 Instruction FMLAI, Instruction FMLSI,
5500 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5501 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5503 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5504 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5506 (ResTy (FMLAI (ResTy FPRC:$Ra),
5507 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5509 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5510 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5512 (ResTy (FMLAI (ResTy FPRC:$Ra),
5514 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5517 // swapped fmla operands
5518 def : Pat<(ResTy (fma
5519 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5522 (ResTy (FMLAI (ResTy FPRC:$Ra),
5523 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5525 def : Pat<(ResTy (fma
5526 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5529 (ResTy (FMLAI (ResTy FPRC:$Ra),
5531 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5535 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5536 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5538 (ResTy (FMLSI (ResTy FPRC:$Ra),
5539 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5541 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5542 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5544 (ResTy (FMLSI (ResTy FPRC:$Ra),
5546 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5549 // swapped fmls operands
5550 def : Pat<(ResTy (fma
5551 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5554 (ResTy (FMLSI (ResTy FPRC:$Ra),
5555 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5557 def : Pat<(ResTy (fma
5558 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5561 (ResTy (FMLSI (ResTy FPRC:$Ra),
5563 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5567 // Scalar Floating Point fused multiply-add and multiply-subtract (scalar, by element)
5568 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5569 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5570 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5571 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5572 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5573 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5575 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5576 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5577 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5578 let Inst{11} = 0b0; // h
5579 let Inst{21} = Imm{1}; // l
5580 let Inst{20} = Imm{0}; // m
5581 let Inst{19-16} = MRm{3-0};
5583 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5584 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5585 let Inst{11} = Imm{2}; // h
5586 let Inst{21} = Imm{1}; // l
5587 let Inst{20} = Imm{0}; // m
5588 let Inst{19-16} = MRm{3-0};
5590 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5591 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5592 let Inst{11} = 0b0; // h
5593 let Inst{21} = Imm{0}; // l
5594 let Inst{20-16} = MRm;
5596 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5597 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5598 let Inst{11} = Imm{1}; // h
5599 let Inst{21} = Imm{0}; // l
5600 let Inst{20-16} = MRm;
5603 // Scalar Signed saturating doubling
5604 // multiply-subtract long (scalar, by element)
5605 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5606 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5607 let Inst{11} = 0b0; // h
5608 let Inst{21} = Imm{1}; // l
5609 let Inst{20} = Imm{0}; // m
5610 let Inst{19-16} = MRm{3-0};
5612 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5613 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5614 let Inst{11} = Imm{2}; // h
5615 let Inst{21} = Imm{1}; // l
5616 let Inst{20} = Imm{0}; // m
5617 let Inst{19-16} = MRm{3-0};
5619 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5620 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5621 let Inst{11} = 0b0; // h
5622 let Inst{21} = Imm{0}; // l
5623 let Inst{20-16} = MRm;
5625 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5626 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5627 let Inst{11} = Imm{1}; // h
5628 let Inst{21} = Imm{0}; // l
5629 let Inst{20-16} = MRm;
5632 // Scalar Signed saturating doubling multiply long (scalar, by element)
5633 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5634 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5635 let Inst{11} = 0b0; // h
5636 let Inst{21} = Imm{1}; // l
5637 let Inst{20} = Imm{0}; // m
5638 let Inst{19-16} = MRm{3-0};
5640 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5641 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5642 let Inst{11} = Imm{2}; // h
5643 let Inst{21} = Imm{1}; // l
5644 let Inst{20} = Imm{0}; // m
5645 let Inst{19-16} = MRm{3-0};
5647 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5648 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5649 let Inst{11} = 0b0; // h
5650 let Inst{21} = Imm{0}; // l
5651 let Inst{20-16} = MRm;
5653 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5654 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5655 let Inst{11} = Imm{1}; // h
5656 let Inst{21} = Imm{0}; // l
5657 let Inst{20-16} = MRm;
5660 // Scalar Signed saturating doubling multiply returning
5661 // high half (scalar, by element)
5662 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5663 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5664 let Inst{11} = 0b0; // h
5665 let Inst{21} = Imm{1}; // l
5666 let Inst{20} = Imm{0}; // m
5667 let Inst{19-16} = MRm{3-0};
5669 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5670 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5671 let Inst{11} = Imm{2}; // h
5672 let Inst{21} = Imm{1}; // l
5673 let Inst{20} = Imm{0}; // m
5674 let Inst{19-16} = MRm{3-0};
5676 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5677 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5678 let Inst{11} = 0b0; // h
5679 let Inst{21} = Imm{0}; // l
5680 let Inst{20-16} = MRm;
5682 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5683 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5684 let Inst{11} = Imm{1}; // h
5685 let Inst{21} = Imm{0}; // l
5686 let Inst{20-16} = MRm;
5689 // Scalar Signed saturating rounding doubling multiply
5690 // returning high half (scalar, by element)
5691 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5692 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5693 let Inst{11} = 0b0; // h
5694 let Inst{21} = Imm{1}; // l
5695 let Inst{20} = Imm{0}; // m
5696 let Inst{19-16} = MRm{3-0};
5698 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5699 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5700 let Inst{11} = Imm{2}; // h
5701 let Inst{21} = Imm{1}; // l
5702 let Inst{20} = Imm{0}; // m
5703 let Inst{19-16} = MRm{3-0};
5705 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5706 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5707 let Inst{11} = 0b0; // h
5708 let Inst{21} = Imm{0}; // l
5709 let Inst{20-16} = MRm;
5711 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5712 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5713 let Inst{11} = Imm{1}; // h
5714 let Inst{21} = Imm{0}; // l
5715 let Inst{20-16} = MRm;
5719 // Scalar Copy - DUP element to scalar
5720 class NeonI_Scalar_DUP<string asmop, string asmlane,
5721 RegisterClass ResRC, RegisterOperand VPRC,
5723 : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
5724 asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
5730 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
5731 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5733 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
5734 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5736 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
5737 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5739 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
5740 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5743 multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
5744 ValueType OpTy, Operand OpImm,
5745 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5746 def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5747 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5749 def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5751 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5755 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh,
5756 ValueType ResTy, ValueType OpTy> {
5757 def : Pat<(ResTy (GetLow VPR128:$Rn)),
5758 (ResTy (DUPdv_D (OpTy VPR128:$Rn), 0))>;
5759 def : Pat<(ResTy (GetHigh VPR128:$Rn)),
5760 (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
5763 defm : NeonI_SDUP<Neon_low16B, Neon_High16B, v8i8, v16i8>;
5764 defm : NeonI_SDUP<Neon_low8H, Neon_High8H, v4i16, v8i16>;
5765 defm : NeonI_SDUP<Neon_low4S, Neon_High4S, v2i32, v4i32>;
5766 defm : NeonI_SDUP<Neon_low2D, Neon_High2D, v1i64, v2i64>;
5767 defm : NeonI_SDUP<Neon_low4f, Neon_High4f, v2f32, v4f32>;
5768 defm : NeonI_SDUP<Neon_low2d, Neon_High2d, v1f64, v2f64>;
5770 // Patterns for vector extract of FP data using scalar DUP instructions
5771 defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
5772 v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5773 defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64,
5774 v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5776 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
5777 Instruction DUPI, Operand OpImm,
5778 RegisterClass ResRC> {
5779 def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn." # asmlane # "[$Imm]"),
5780 (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
5783 // Aliases for Scalar copy - DUP element (scalar)
5784 // FIXME: This is actually the preferred syntax but TableGen can't deal with
5785 // custom printing of aliases.
5786 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
5787 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
5788 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
5789 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
5792 //===----------------------------------------------------------------------===//
5793 // Non-Instruction Patterns
5794 //===----------------------------------------------------------------------===//
5796 // 64-bit vector bitcasts...
5798 def : Pat<(v1i64 (bitconvert (v8i8 VPR64:$src))), (v1i64 VPR64:$src)>;
5799 def : Pat<(v2f32 (bitconvert (v8i8 VPR64:$src))), (v2f32 VPR64:$src)>;
5800 def : Pat<(v2i32 (bitconvert (v8i8 VPR64:$src))), (v2i32 VPR64:$src)>;
5801 def : Pat<(v4i16 (bitconvert (v8i8 VPR64:$src))), (v4i16 VPR64:$src)>;
5803 def : Pat<(v1i64 (bitconvert (v4i16 VPR64:$src))), (v1i64 VPR64:$src)>;
5804 def : Pat<(v2i32 (bitconvert (v4i16 VPR64:$src))), (v2i32 VPR64:$src)>;
5805 def : Pat<(v2f32 (bitconvert (v4i16 VPR64:$src))), (v2f32 VPR64:$src)>;
5806 def : Pat<(v8i8 (bitconvert (v4i16 VPR64:$src))), (v8i8 VPR64:$src)>;
5808 def : Pat<(v1i64 (bitconvert (v2i32 VPR64:$src))), (v1i64 VPR64:$src)>;
5809 def : Pat<(v2f32 (bitconvert (v2i32 VPR64:$src))), (v2f32 VPR64:$src)>;
5810 def : Pat<(v4i16 (bitconvert (v2i32 VPR64:$src))), (v4i16 VPR64:$src)>;
5811 def : Pat<(v8i8 (bitconvert (v2i32 VPR64:$src))), (v8i8 VPR64:$src)>;
5813 def : Pat<(v1i64 (bitconvert (v2f32 VPR64:$src))), (v1i64 VPR64:$src)>;
5814 def : Pat<(v2i32 (bitconvert (v2f32 VPR64:$src))), (v2i32 VPR64:$src)>;
5815 def : Pat<(v4i16 (bitconvert (v2f32 VPR64:$src))), (v4i16 VPR64:$src)>;
5816 def : Pat<(v8i8 (bitconvert (v2f32 VPR64:$src))), (v8i8 VPR64:$src)>;
5818 def : Pat<(v2f32 (bitconvert (v1i64 VPR64:$src))), (v2f32 VPR64:$src)>;
5819 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
5820 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
5821 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
5823 // ..and 128-bit vector bitcasts...
5825 def : Pat<(v2f64 (bitconvert (v16i8 VPR128:$src))), (v2f64 VPR128:$src)>;
5826 def : Pat<(v2i64 (bitconvert (v16i8 VPR128:$src))), (v2i64 VPR128:$src)>;
5827 def : Pat<(v4f32 (bitconvert (v16i8 VPR128:$src))), (v4f32 VPR128:$src)>;
5828 def : Pat<(v4i32 (bitconvert (v16i8 VPR128:$src))), (v4i32 VPR128:$src)>;
5829 def : Pat<(v8i16 (bitconvert (v16i8 VPR128:$src))), (v8i16 VPR128:$src)>;
5831 def : Pat<(v2f64 (bitconvert (v8i16 VPR128:$src))), (v2f64 VPR128:$src)>;
5832 def : Pat<(v2i64 (bitconvert (v8i16 VPR128:$src))), (v2i64 VPR128:$src)>;
5833 def : Pat<(v4i32 (bitconvert (v8i16 VPR128:$src))), (v4i32 VPR128:$src)>;
5834 def : Pat<(v4f32 (bitconvert (v8i16 VPR128:$src))), (v4f32 VPR128:$src)>;
5835 def : Pat<(v16i8 (bitconvert (v8i16 VPR128:$src))), (v16i8 VPR128:$src)>;
5837 def : Pat<(v2f64 (bitconvert (v4i32 VPR128:$src))), (v2f64 VPR128:$src)>;
5838 def : Pat<(v2i64 (bitconvert (v4i32 VPR128:$src))), (v2i64 VPR128:$src)>;
5839 def : Pat<(v4f32 (bitconvert (v4i32 VPR128:$src))), (v4f32 VPR128:$src)>;
5840 def : Pat<(v8i16 (bitconvert (v4i32 VPR128:$src))), (v8i16 VPR128:$src)>;
5841 def : Pat<(v16i8 (bitconvert (v4i32 VPR128:$src))), (v16i8 VPR128:$src)>;
5843 def : Pat<(v2f64 (bitconvert (v4f32 VPR128:$src))), (v2f64 VPR128:$src)>;
5844 def : Pat<(v2i64 (bitconvert (v4f32 VPR128:$src))), (v2i64 VPR128:$src)>;
5845 def : Pat<(v4i32 (bitconvert (v4f32 VPR128:$src))), (v4i32 VPR128:$src)>;
5846 def : Pat<(v8i16 (bitconvert (v4f32 VPR128:$src))), (v8i16 VPR128:$src)>;
5847 def : Pat<(v16i8 (bitconvert (v4f32 VPR128:$src))), (v16i8 VPR128:$src)>;
5849 def : Pat<(v2f64 (bitconvert (v2i64 VPR128:$src))), (v2f64 VPR128:$src)>;
5850 def : Pat<(v4f32 (bitconvert (v2i64 VPR128:$src))), (v4f32 VPR128:$src)>;
5851 def : Pat<(v4i32 (bitconvert (v2i64 VPR128:$src))), (v4i32 VPR128:$src)>;
5852 def : Pat<(v8i16 (bitconvert (v2i64 VPR128:$src))), (v8i16 VPR128:$src)>;
5853 def : Pat<(v16i8 (bitconvert (v2i64 VPR128:$src))), (v16i8 VPR128:$src)>;
5855 def : Pat<(v2i64 (bitconvert (v2f64 VPR128:$src))), (v2i64 VPR128:$src)>;
5856 def : Pat<(v4f32 (bitconvert (v2f64 VPR128:$src))), (v4f32 VPR128:$src)>;
5857 def : Pat<(v4i32 (bitconvert (v2f64 VPR128:$src))), (v4i32 VPR128:$src)>;
5858 def : Pat<(v8i16 (bitconvert (v2f64 VPR128:$src))), (v8i16 VPR128:$src)>;
5859 def : Pat<(v16i8 (bitconvert (v2f64 VPR128:$src))), (v16i8 VPR128:$src)>;
5862 // ...and scalar bitcasts...
5863 def : Pat<(f16 (bitconvert (v1i16 FPR16:$src))), (f16 FPR16:$src)>;
5864 def : Pat<(f32 (bitconvert (v1i32 FPR32:$src))), (f32 FPR32:$src)>;
5865 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5866 def : Pat<(f32 (bitconvert (v1f32 FPR32:$src))), (f32 FPR32:$src)>;
5867 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5869 def : Pat<(i64 (bitconvert (v1i64 FPR64:$src))), (FMOVxd $src)>;
5870 def : Pat<(i32 (bitconvert (v1i32 FPR32:$src))), (FMOVws $src)>;
5872 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
5873 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
5874 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
5876 def : Pat<(f64 (bitconvert (v8i8 VPR64:$src))), (f64 VPR64:$src)>;
5877 def : Pat<(f64 (bitconvert (v4i16 VPR64:$src))), (f64 VPR64:$src)>;
5878 def : Pat<(f64 (bitconvert (v2i32 VPR64:$src))), (f64 VPR64:$src)>;
5879 def : Pat<(f64 (bitconvert (v2f32 VPR64:$src))), (f64 VPR64:$src)>;
5880 def : Pat<(f64 (bitconvert (v1i64 VPR64:$src))), (f64 VPR64:$src)>;
5882 def : Pat<(f128 (bitconvert (v16i8 VPR128:$src))), (f128 VPR128:$src)>;
5883 def : Pat<(f128 (bitconvert (v8i16 VPR128:$src))), (f128 VPR128:$src)>;
5884 def : Pat<(f128 (bitconvert (v4i32 VPR128:$src))), (f128 VPR128:$src)>;
5885 def : Pat<(f128 (bitconvert (v2i64 VPR128:$src))), (f128 VPR128:$src)>;
5886 def : Pat<(f128 (bitconvert (v4f32 VPR128:$src))), (f128 VPR128:$src)>;
5887 def : Pat<(f128 (bitconvert (v2f64 VPR128:$src))), (f128 VPR128:$src)>;
5889 def : Pat<(v1i16 (bitconvert (f16 FPR16:$src))), (v1i16 FPR16:$src)>;
5890 def : Pat<(v1i32 (bitconvert (f32 FPR32:$src))), (v1i32 FPR32:$src)>;
5891 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5892 def : Pat<(v1f32 (bitconvert (f32 FPR32:$src))), (v1f32 FPR32:$src)>;
5893 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5895 def : Pat<(v1i64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
5896 def : Pat<(v1i32 (bitconvert (i32 GPR32:$src))), (FMOVsw $src)>;
5898 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5899 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5900 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5901 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5902 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5904 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5905 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5906 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5907 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5908 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5909 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5911 // Scalar Three Same
5913 def neon_uimm3 : Operand<i64>,
5914 ImmLeaf<i64, [{return Imm < 8;}]> {
5915 let ParserMatchClass = uimm3_asmoperand;
5916 let PrintMethod = "printUImmHexOperand";
5919 def neon_uimm4 : Operand<i64>,
5920 ImmLeaf<i64, [{return Imm < 16;}]> {
5921 let ParserMatchClass = uimm4_asmoperand;
5922 let PrintMethod = "printUImmHexOperand";
5926 class NeonI_Extract<bit q, bits<2> op2, string asmop,
5927 string OpS, RegisterOperand OpVPR, Operand OpImm>
5928 : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
5929 (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
5930 asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
5931 ", $Rm." # OpS # ", $Index",
5937 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
5938 VPR64, neon_uimm3> {
5939 let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
5942 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
5943 VPR128, neon_uimm4> {
5944 let Inst{14-11} = Index;
5947 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
5949 : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
5951 (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
5953 def : NI_Extract<v8i8, VPR64, EXTvvvi_8b, neon_uimm3>;
5954 def : NI_Extract<v4i16, VPR64, EXTvvvi_8b, neon_uimm3>;
5955 def : NI_Extract<v2i32, VPR64, EXTvvvi_8b, neon_uimm3>;
5956 def : NI_Extract<v1i64, VPR64, EXTvvvi_8b, neon_uimm3>;
5957 def : NI_Extract<v2f32, VPR64, EXTvvvi_8b, neon_uimm3>;
5958 def : NI_Extract<v1f64, VPR64, EXTvvvi_8b, neon_uimm3>;
5959 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
5960 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
5961 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
5962 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
5963 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
5964 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
5967 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
5968 string asmop, string OpS, RegisterOperand OpVPR,
5969 RegisterOperand VecList>
5970 : NeonI_TBL<q, op2, len, op,
5971 (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
5972 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
5976 // The vectors in look up table are always 16b
5977 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
5978 def _8b : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
5979 !cast<RegisterOperand>(List # "16B_operand")>;
5981 def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
5982 !cast<RegisterOperand>(List # "16B_operand")>;
5985 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
5986 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
5987 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
5988 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
5990 // Table lookup extention
5991 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
5992 string asmop, string OpS, RegisterOperand OpVPR,
5993 RegisterOperand VecList>
5994 : NeonI_TBL<q, op2, len, op,
5995 (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
5996 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
5999 let Constraints = "$src = $Rd";
6002 // The vectors in look up table are always 16b
6003 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6004 def _8b : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6005 !cast<RegisterOperand>(List # "16B_operand")>;
6007 def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6008 !cast<RegisterOperand>(List # "16B_operand")>;
6011 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6012 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6013 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6014 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6016 // The followings are for instruction class (3V Elem)
6020 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
6021 string asmop, string ResS, string OpS, string EleOpS,
6022 Operand OpImm, RegisterOperand ResVPR,
6023 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6024 : NeonI_2VElem<q, u, size, opcode,
6025 (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
6026 EleOpVPR:$Re, OpImm:$Index),
6027 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6028 ", $Re." # EleOpS # "[$Index]",
6034 let Constraints = "$src = $Rd";
6037 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
6038 // vector register class for element is always 128-bit to cover the max index
6039 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6040 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6041 let Inst{11} = {Index{1}};
6042 let Inst{21} = {Index{0}};
6043 let Inst{20-16} = Re;
6046 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6047 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6048 let Inst{11} = {Index{1}};
6049 let Inst{21} = {Index{0}};
6050 let Inst{20-16} = Re;
6053 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6054 def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6055 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6056 let Inst{11} = {Index{2}};
6057 let Inst{21} = {Index{1}};
6058 let Inst{20} = {Index{0}};
6059 let Inst{19-16} = Re{3-0};
6062 def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6063 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6064 let Inst{11} = {Index{2}};
6065 let Inst{21} = {Index{1}};
6066 let Inst{20} = {Index{0}};
6067 let Inst{19-16} = Re{3-0};
6071 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
6072 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
6074 // Pattern for lane in 128-bit vector
6075 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6076 RegisterOperand ResVPR, RegisterOperand OpVPR,
6077 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6078 ValueType EleOpTy, SDPatternOperator coreop>
6079 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6080 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6081 (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6083 // Pattern for lane in 64-bit vector
6084 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6085 RegisterOperand ResVPR, RegisterOperand OpVPR,
6086 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6087 ValueType EleOpTy, SDPatternOperator coreop>
6088 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6089 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6090 (INST ResVPR:$src, OpVPR:$Rn,
6091 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6093 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
6095 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6096 op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32,
6097 BinOpFrag<(Neon_vduplane
6098 (Neon_low4S node:$LHS), node:$RHS)>>;
6100 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6101 op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32,
6102 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6104 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6105 op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
6106 BinOpFrag<(Neon_vduplane
6107 (Neon_low8H node:$LHS), node:$RHS)>>;
6109 def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6110 op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
6111 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6113 // Index can only be half of the max value for lane in 64-bit vector
6115 def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6116 op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32,
6117 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6119 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
6120 op, VPR128, VPR128, VPR64, v4i32, v4i32, v2i32,
6121 BinOpFrag<(Neon_vduplane
6122 (Neon_combine_4S node:$LHS, undef),
6125 def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6126 op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
6127 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6129 def : NI_2VE_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
6130 op, VPR128, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
6131 BinOpFrag<(Neon_vduplane
6132 (Neon_combine_8H node:$LHS, undef),
6136 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
6137 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
6139 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
6140 string asmop, string ResS, string OpS, string EleOpS,
6141 Operand OpImm, RegisterOperand ResVPR,
6142 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6143 : NeonI_2VElem<q, u, size, opcode,
6144 (outs ResVPR:$Rd), (ins OpVPR:$Rn,
6145 EleOpVPR:$Re, OpImm:$Index),
6146 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6147 ", $Re." # EleOpS # "[$Index]",
6154 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
6155 // vector register class for element is always 128-bit to cover the max index
6156 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6157 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6158 let Inst{11} = {Index{1}};
6159 let Inst{21} = {Index{0}};
6160 let Inst{20-16} = Re;
6163 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6164 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6165 let Inst{11} = {Index{1}};
6166 let Inst{21} = {Index{0}};
6167 let Inst{20-16} = Re;
6170 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6171 def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6172 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6173 let Inst{11} = {Index{2}};
6174 let Inst{21} = {Index{1}};
6175 let Inst{20} = {Index{0}};
6176 let Inst{19-16} = Re{3-0};
6179 def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6180 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6181 let Inst{11} = {Index{2}};
6182 let Inst{21} = {Index{1}};
6183 let Inst{20} = {Index{0}};
6184 let Inst{19-16} = Re{3-0};
6188 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
6189 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
6190 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
6192 // Pattern for lane in 128-bit vector
6193 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6194 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6195 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
6196 SDPatternOperator coreop>
6197 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6198 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6199 (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6201 // Pattern for lane in 64-bit vector
6202 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6203 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6204 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
6205 SDPatternOperator coreop>
6206 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6207 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6209 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6211 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
6212 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6213 op, VPR64, VPR128, v2i32, v2i32, v4i32,
6214 BinOpFrag<(Neon_vduplane
6215 (Neon_low4S node:$LHS), node:$RHS)>>;
6217 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6218 op, VPR128, VPR128, v4i32, v4i32, v4i32,
6219 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6221 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6222 op, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
6223 BinOpFrag<(Neon_vduplane
6224 (Neon_low8H node:$LHS), node:$RHS)>>;
6226 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6227 op, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
6228 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6230 // Index can only be half of the max value for lane in 64-bit vector
6232 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6233 op, VPR64, VPR64, v2i32, v2i32, v2i32,
6234 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6236 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
6237 op, VPR128, VPR64, v4i32, v4i32, v2i32,
6238 BinOpFrag<(Neon_vduplane
6239 (Neon_combine_4S node:$LHS, undef),
6242 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6243 op, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
6244 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6246 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
6247 op, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
6248 BinOpFrag<(Neon_vduplane
6249 (Neon_combine_8H node:$LHS, undef),
6253 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
6254 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
6255 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
6259 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
6260 // vector register class for element is always 128-bit to cover the max index
6261 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6262 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6263 let Inst{11} = {Index{1}};
6264 let Inst{21} = {Index{0}};
6265 let Inst{20-16} = Re;
6268 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6269 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6270 let Inst{11} = {Index{1}};
6271 let Inst{21} = {Index{0}};
6272 let Inst{20-16} = Re;
6275 // _1d2d doesn't exist!
6277 def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
6278 neon_uimm1_bare, VPR128, VPR128, VPR128> {
6279 let Inst{11} = {Index{0}};
6281 let Inst{20-16} = Re;
6285 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
6286 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
6288 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
6289 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6290 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
6291 SDPatternOperator coreop>
6292 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6293 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
6295 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
6297 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
6298 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6299 op, VPR64, VPR128, v2f32, v2f32, v4f32,
6300 BinOpFrag<(Neon_vduplane
6301 (Neon_low4f node:$LHS), node:$RHS)>>;
6303 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6304 op, VPR128, VPR128, v4f32, v4f32, v4f32,
6305 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6307 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
6308 op, VPR128, VPR128, v2f64, v2f64, v2f64,
6309 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6311 // Index can only be half of the max value for lane in 64-bit vector
6313 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6314 op, VPR64, VPR64, v2f32, v2f32, v2f32,
6315 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6317 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
6318 op, VPR128, VPR64, v4f32, v4f32, v2f32,
6319 BinOpFrag<(Neon_vduplane
6320 (Neon_combine_4f node:$LHS, undef),
6323 def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
6324 op, VPR128, VPR64, v2f64, v2f64, v1f64,
6325 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
6328 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
6329 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
6331 // The followings are patterns using fma
6332 // -ffp-contract=fast generates fma
6334 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
6335 // vector register class for element is always 128-bit to cover the max index
6336 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6337 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6338 let Inst{11} = {Index{1}};
6339 let Inst{21} = {Index{0}};
6340 let Inst{20-16} = Re;
6343 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6344 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6345 let Inst{11} = {Index{1}};
6346 let Inst{21} = {Index{0}};
6347 let Inst{20-16} = Re;
6350 // _1d2d doesn't exist!
6352 def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
6353 neon_uimm1_bare, VPR128, VPR128, VPR128> {
6354 let Inst{11} = {Index{0}};
6356 let Inst{20-16} = Re;
6360 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
6361 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
6363 // Pattern for lane in 128-bit vector
6364 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6365 RegisterOperand ResVPR, RegisterOperand OpVPR,
6366 ValueType ResTy, ValueType OpTy,
6367 SDPatternOperator coreop>
6368 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
6369 (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
6370 (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
6372 // Pattern for lane in 64-bit vector
6373 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6374 RegisterOperand ResVPR, RegisterOperand OpVPR,
6375 ValueType ResTy, ValueType OpTy,
6376 SDPatternOperator coreop>
6377 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
6378 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
6379 (INST ResVPR:$src, ResVPR:$Rn,
6380 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
6382 // Pattern for lane in 64-bit vector
6383 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
6384 SDPatternOperator op,
6385 RegisterOperand ResVPR, RegisterOperand OpVPR,
6386 ValueType ResTy, ValueType OpTy,
6387 SDPatternOperator coreop>
6388 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
6389 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
6390 (INST ResVPR:$src, ResVPR:$Rn,
6391 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
6394 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
6395 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
6396 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
6397 BinOpFrag<(Neon_vduplane
6398 (Neon_low4f node:$LHS), node:$RHS)>>;
6400 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
6401 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
6402 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6404 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
6405 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
6406 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6408 // Index can only be half of the max value for lane in 64-bit vector
6410 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
6411 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
6412 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6414 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
6415 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
6416 BinOpFrag<(Neon_vduplane
6417 (Neon_combine_4f node:$LHS, undef),
6420 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
6421 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
6422 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
6425 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
6427 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
6429 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
6430 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
6431 BinOpFrag<(fneg (Neon_vduplane
6432 (Neon_low4f node:$LHS), node:$RHS))>>;
6434 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
6435 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
6436 BinOpFrag<(Neon_vduplane
6437 (Neon_low4f (fneg node:$LHS)),
6440 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
6441 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
6442 BinOpFrag<(fneg (Neon_vduplane
6443 node:$LHS, node:$RHS))>>;
6445 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
6446 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
6447 BinOpFrag<(Neon_vduplane
6448 (fneg node:$LHS), node:$RHS)>>;
6450 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
6451 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
6452 BinOpFrag<(fneg (Neon_vduplane
6453 node:$LHS, node:$RHS))>>;
6455 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
6456 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
6457 BinOpFrag<(Neon_vduplane
6458 (fneg node:$LHS), node:$RHS)>>;
6460 // Index can only be half of the max value for lane in 64-bit vector
6462 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
6463 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
6464 BinOpFrag<(fneg (Neon_vduplane
6465 node:$LHS, node:$RHS))>>;
6467 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
6468 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
6469 BinOpFrag<(Neon_vduplane
6470 (fneg node:$LHS), node:$RHS)>>;
6472 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
6473 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
6474 BinOpFrag<(fneg (Neon_vduplane
6475 (Neon_combine_4f node:$LHS, undef),
6478 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
6479 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
6480 BinOpFrag<(Neon_vduplane
6481 (Neon_combine_4f (fneg node:$LHS), undef),
6484 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
6485 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
6486 BinOpFrag<(fneg (Neon_combine_2d
6487 node:$LHS, node:$RHS))>>;
6489 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
6490 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
6491 BinOpFrag<(Neon_combine_2d
6492 (fneg node:$LHS), (fneg node:$RHS))>>;
6495 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
6497 // Variant 3: Long type
6498 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
6499 // SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
6501 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
6502 // vector register class for element is always 128-bit to cover the max index
6503 def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
6504 neon_uimm2_bare, VPR128, VPR64, VPR128> {
6505 let Inst{11} = {Index{1}};
6506 let Inst{21} = {Index{0}};
6507 let Inst{20-16} = Re;
6510 def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
6511 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6512 let Inst{11} = {Index{1}};
6513 let Inst{21} = {Index{0}};
6514 let Inst{20-16} = Re;
6517 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6518 def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
6519 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6520 let Inst{11} = {Index{2}};
6521 let Inst{21} = {Index{1}};
6522 let Inst{20} = {Index{0}};
6523 let Inst{19-16} = Re{3-0};
6526 def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
6527 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
6528 let Inst{11} = {Index{2}};
6529 let Inst{21} = {Index{1}};
6530 let Inst{20} = {Index{0}};
6531 let Inst{19-16} = Re{3-0};
6535 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
6536 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
6537 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
6538 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
6539 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
6540 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
6542 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
6543 // vector register class for element is always 128-bit to cover the max index
6544 def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
6545 neon_uimm2_bare, VPR128, VPR64, VPR128> {
6546 let Inst{11} = {Index{1}};
6547 let Inst{21} = {Index{0}};
6548 let Inst{20-16} = Re;
6551 def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
6552 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6553 let Inst{11} = {Index{1}};
6554 let Inst{21} = {Index{0}};
6555 let Inst{20-16} = Re;
6558 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6559 def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
6560 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6561 let Inst{11} = {Index{2}};
6562 let Inst{21} = {Index{1}};
6563 let Inst{20} = {Index{0}};
6564 let Inst{19-16} = Re{3-0};
6567 def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
6568 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
6569 let Inst{11} = {Index{2}};
6570 let Inst{21} = {Index{1}};
6571 let Inst{20} = {Index{0}};
6572 let Inst{19-16} = Re{3-0};
6576 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
6577 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
6578 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
6580 // Pattern for lane in 128-bit vector
6581 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6582 RegisterOperand EleOpVPR, ValueType ResTy,
6583 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6584 SDPatternOperator hiop, SDPatternOperator coreop>
6585 : Pat<(ResTy (op (ResTy VPR128:$src),
6586 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6587 (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6588 (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6590 // Pattern for lane in 64-bit vector
6591 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6592 RegisterOperand EleOpVPR, ValueType ResTy,
6593 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6594 SDPatternOperator hiop, SDPatternOperator coreop>
6595 : Pat<(ResTy (op (ResTy VPR128:$src),
6596 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6597 (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6598 (INST VPR128:$src, VPR128:$Rn,
6599 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6601 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
6602 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
6603 op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
6604 BinOpFrag<(Neon_vduplane
6605 (Neon_low8H node:$LHS), node:$RHS)>>;
6607 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
6608 op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32,
6609 BinOpFrag<(Neon_vduplane
6610 (Neon_low4S node:$LHS), node:$RHS)>>;
6612 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
6613 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H,
6614 BinOpFrag<(Neon_vduplane
6615 (Neon_low8H node:$LHS), node:$RHS)>>;
6617 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
6618 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
6619 BinOpFrag<(Neon_vduplane
6620 (Neon_low4S node:$LHS), node:$RHS)>>;
6622 // Index can only be half of the max value for lane in 64-bit vector
6624 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
6625 op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
6626 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6628 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
6629 op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32,
6630 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6632 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
6633 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
6634 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6636 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
6637 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
6638 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6641 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
6642 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
6643 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
6644 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
6646 // Pattern for lane in 128-bit vector
6647 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6648 RegisterOperand EleOpVPR, ValueType ResTy,
6649 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6650 SDPatternOperator hiop, SDPatternOperator coreop>
6652 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6653 (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6654 (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6656 // Pattern for lane in 64-bit vector
6657 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6658 RegisterOperand EleOpVPR, ValueType ResTy,
6659 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6660 SDPatternOperator hiop, SDPatternOperator coreop>
6662 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6663 (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6665 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6667 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
6668 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
6669 op, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
6670 BinOpFrag<(Neon_vduplane
6671 (Neon_low8H node:$LHS), node:$RHS)>>;
6673 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
6674 op, VPR64, VPR128, v2i64, v2i32, v4i32,
6675 BinOpFrag<(Neon_vduplane
6676 (Neon_low4S node:$LHS), node:$RHS)>>;
6678 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
6679 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16,
6681 BinOpFrag<(Neon_vduplane
6682 (Neon_low8H node:$LHS), node:$RHS)>>;
6684 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
6685 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
6686 BinOpFrag<(Neon_vduplane
6687 (Neon_low4S node:$LHS), node:$RHS)>>;
6689 // Index can only be half of the max value for lane in 64-bit vector
6691 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
6692 op, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
6693 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6695 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
6696 op, VPR64, VPR64, v2i64, v2i32, v2i32,
6697 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6699 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
6700 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
6701 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6703 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
6704 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
6705 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6708 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
6709 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
6710 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
6712 multiclass NI_qdma<SDPatternOperator op> {
6713 def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
6715 (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
6717 def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
6719 (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
6722 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
6723 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
6725 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
6726 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
6727 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
6728 v4i32, v4i16, v8i16,
6729 BinOpFrag<(Neon_vduplane
6730 (Neon_low8H node:$LHS), node:$RHS)>>;
6732 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
6733 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
6734 v2i64, v2i32, v4i32,
6735 BinOpFrag<(Neon_vduplane
6736 (Neon_low4S node:$LHS), node:$RHS)>>;
6738 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
6739 !cast<PatFrag>(op # "_4s"), VPR128Lo,
6740 v4i32, v8i16, v8i16, v4i16, Neon_High8H,
6741 BinOpFrag<(Neon_vduplane
6742 (Neon_low8H node:$LHS), node:$RHS)>>;
6744 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
6745 !cast<PatFrag>(op # "_2d"), VPR128,
6746 v2i64, v4i32, v4i32, v2i32, Neon_High4S,
6747 BinOpFrag<(Neon_vduplane
6748 (Neon_low4S node:$LHS), node:$RHS)>>;
6750 // Index can only be half of the max value for lane in 64-bit vector
6752 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
6753 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
6754 v4i32, v4i16, v4i16,
6755 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6757 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
6758 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
6759 v2i64, v2i32, v2i32,
6760 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6762 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
6763 !cast<PatFrag>(op # "_4s"), VPR64Lo,
6764 v4i32, v8i16, v4i16, v4i16, Neon_High8H,
6765 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6767 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
6768 !cast<PatFrag>(op # "_2d"), VPR64,
6769 v2i64, v4i32, v2i32, v2i32, Neon_High4S,
6770 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6773 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
6774 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
6776 // End of implementation for instruction class (3V Elem)
6778 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6779 RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6780 : NeonI_copy<0b1, 0b0, 0b0011,
6781 (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6782 asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6783 [(set (ResTy VPR128:$Rd),
6784 (ResTy (vector_insert
6785 (ResTy VPR128:$src),
6790 let Constraints = "$src = $Rd";
6793 //Insert element (vector, from main)
6794 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6796 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6798 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6800 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6802 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6804 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6806 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6808 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6811 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6812 (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6813 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6814 (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6815 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6816 (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6817 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6818 (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6820 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6821 RegisterClass OpGPR, ValueType OpTy,
6822 Operand OpImm, Instruction INS>
6823 : Pat<(ResTy (vector_insert
6827 (ResTy (EXTRACT_SUBREG
6828 (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6829 OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6831 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6832 neon_uimm3_bare, INSbw>;
6833 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6834 neon_uimm2_bare, INShw>;
6835 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6836 neon_uimm1_bare, INSsw>;
6837 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6838 neon_uimm0_bare, INSdx>;
6840 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6841 : NeonI_insert<0b1, 0b1,
6842 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6843 ResImm:$Immd, ResImm:$Immn),
6844 asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6847 let Constraints = "$src = $Rd";
6852 //Insert element (vector, from element)
6853 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6854 let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6855 let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6857 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6858 let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6859 let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6860 // bit 11 is unspecified, but should be set to zero.
6862 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6863 let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6864 let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6865 // bits 11-12 are unspecified, but should be set to zero.
6867 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6868 let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6869 let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6870 // bits 11-13 are unspecified, but should be set to zero.
6873 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6874 (INSELb VPR128:$Rd, VPR128:$Rn,
6875 neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6876 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6877 (INSELh VPR128:$Rd, VPR128:$Rn,
6878 neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6879 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6880 (INSELs VPR128:$Rd, VPR128:$Rn,
6881 neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6882 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6883 (INSELd VPR128:$Rd, VPR128:$Rn,
6884 neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6886 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6887 ValueType MidTy, Operand StImm, Operand NaImm,
6889 def : Pat<(ResTy (vector_insert
6890 (ResTy VPR128:$src),
6891 (MidTy (vector_extract
6895 (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6896 StImm:$Immd, StImm:$Immn)>;
6898 def : Pat <(ResTy (vector_insert
6899 (ResTy VPR128:$src),
6900 (MidTy (vector_extract
6904 (INS (ResTy VPR128:$src),
6905 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6906 StImm:$Immd, NaImm:$Immn)>;
6908 def : Pat <(NaTy (vector_insert
6910 (MidTy (vector_extract
6914 (NaTy (EXTRACT_SUBREG
6916 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6918 NaImm:$Immd, StImm:$Immn)),
6921 def : Pat <(NaTy (vector_insert
6923 (MidTy (vector_extract
6927 (NaTy (EXTRACT_SUBREG
6929 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6930 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6931 NaImm:$Immd, NaImm:$Immn)),
6935 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6936 neon_uimm1_bare, INSELs>;
6937 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6938 neon_uimm0_bare, INSELd>;
6939 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6940 neon_uimm3_bare, INSELb>;
6941 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6942 neon_uimm2_bare, INSELh>;
6943 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6944 neon_uimm1_bare, INSELs>;
6945 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6946 neon_uimm0_bare, INSELd>;
6948 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6950 RegisterClass OpFPR, Operand ResImm,
6951 SubRegIndex SubIndex, Instruction INS> {
6952 def : Pat <(ResTy (vector_insert
6953 (ResTy VPR128:$src),
6956 (INS (ResTy VPR128:$src),
6957 (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6961 def : Pat <(NaTy (vector_insert
6965 (NaTy (EXTRACT_SUBREG
6967 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6968 (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6974 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6976 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6979 class NeonI_SMOV<string asmop, string Res, bit Q,
6980 ValueType OpTy, ValueType eleTy,
6981 Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6982 : NeonI_copy<Q, 0b0, 0b0101,
6983 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6984 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6985 [(set (ResTy ResGPR:$Rd),
6987 (ResTy (vector_extract
6988 (OpTy VPR128:$Rn), (OpImm:$Imm))),
6994 //Signed integer move (main, from element)
6995 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6997 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6999 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
7001 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7003 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
7005 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7007 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
7009 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7011 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
7013 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7016 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
7017 ValueType eleTy, Operand StImm, Operand NaImm,
7018 Instruction SMOVI> {
7019 def : Pat<(i64 (sext_inreg
7021 (i32 (vector_extract
7022 (StTy VPR128:$Rn), (StImm:$Imm))))),
7024 (SMOVI VPR128:$Rn, StImm:$Imm)>;
7026 def : Pat<(i64 (sext
7027 (i32 (vector_extract
7028 (StTy VPR128:$Rn), (StImm:$Imm))))),
7029 (SMOVI VPR128:$Rn, StImm:$Imm)>;
7031 def : Pat<(i64 (sext_inreg
7032 (i64 (vector_extract
7033 (NaTy VPR64:$Rn), (NaImm:$Imm))),
7035 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7038 def : Pat<(i64 (sext_inreg
7040 (i32 (vector_extract
7041 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
7043 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7046 def : Pat<(i64 (sext
7047 (i32 (vector_extract
7048 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
7049 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7053 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
7054 neon_uimm3_bare, SMOVxb>;
7055 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
7056 neon_uimm2_bare, SMOVxh>;
7057 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
7058 neon_uimm1_bare, SMOVxs>;
7060 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
7061 ValueType eleTy, Operand StImm, Operand NaImm,
7063 : Pat<(i32 (sext_inreg
7064 (i32 (vector_extract
7065 (NaTy VPR64:$Rn), (NaImm:$Imm))),
7067 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7070 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
7071 neon_uimm3_bare, SMOVwb>;
7072 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
7073 neon_uimm2_bare, SMOVwh>;
7075 class NeonI_UMOV<string asmop, string Res, bit Q,
7076 ValueType OpTy, Operand OpImm,
7077 RegisterClass ResGPR, ValueType ResTy>
7078 : NeonI_copy<Q, 0b0, 0b0111,
7079 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
7080 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
7081 [(set (ResTy ResGPR:$Rd),
7082 (ResTy (vector_extract
7083 (OpTy VPR128:$Rn), (OpImm:$Imm))))],
7088 //Unsigned integer move (main, from element)
7089 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
7091 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7093 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
7095 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7097 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
7099 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7101 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
7103 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
7106 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
7107 (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
7108 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
7109 (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
7111 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
7112 Operand StImm, Operand NaImm,
7114 : Pat<(ResTy (vector_extract
7115 (NaTy VPR64:$Rn), NaImm:$Imm)),
7116 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7119 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
7120 neon_uimm3_bare, UMOVwb>;
7121 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
7122 neon_uimm2_bare, UMOVwh>;
7123 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
7124 neon_uimm1_bare, UMOVws>;
7127 (i32 (vector_extract
7128 (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
7130 (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
7133 (i32 (vector_extract
7134 (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
7136 (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
7138 def : Pat<(i64 (zext
7139 (i32 (vector_extract
7140 (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
7141 (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
7144 (i32 (vector_extract
7145 (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
7147 (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
7148 neon_uimm3_bare:$Imm)>;
7151 (i32 (vector_extract
7152 (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
7154 (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
7155 neon_uimm2_bare:$Imm)>;
7157 def : Pat<(i64 (zext
7158 (i32 (vector_extract
7159 (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
7160 (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
7161 neon_uimm0_bare:$Imm)>;
7163 // Additional copy patterns for scalar types
7164 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
7166 (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
7168 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
7170 (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
7172 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
7173 (FMOVws FPR32:$Rn)>;
7175 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
7176 (FMOVxd FPR64:$Rn)>;
7178 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
7181 def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
7184 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
7185 (v1i8 (EXTRACT_SUBREG (v16i8
7186 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
7189 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
7190 (v1i16 (EXTRACT_SUBREG (v8i16
7191 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
7194 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
7197 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
7200 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
7202 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
7205 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7208 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
7209 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
7210 (f64 FPR64:$src), sub_64)>;
7212 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane, string rnlane,
7213 RegisterOperand ResVPR, Operand OpImm>
7214 : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
7215 (ins VPR128:$Rn, OpImm:$Imm),
7216 asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
7222 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
7224 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7227 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
7229 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7232 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
7234 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7237 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
7239 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
7242 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
7244 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7247 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
7249 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7252 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
7254 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7257 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
7258 ValueType OpTy,ValueType NaTy,
7259 ValueType ExTy, Operand OpLImm,
7261 def : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
7262 (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
7264 def : Pat<(ResTy (Neon_vduplane
7265 (NaTy VPR64:$Rn), OpNImm:$Imm)),
7267 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
7269 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
7270 neon_uimm4_bare, neon_uimm3_bare>;
7271 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
7272 neon_uimm4_bare, neon_uimm3_bare>;
7273 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
7274 neon_uimm3_bare, neon_uimm2_bare>;
7275 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
7276 neon_uimm3_bare, neon_uimm2_bare>;
7277 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
7278 neon_uimm2_bare, neon_uimm1_bare>;
7279 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
7280 neon_uimm2_bare, neon_uimm1_bare>;
7281 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
7282 neon_uimm1_bare, neon_uimm0_bare>;
7283 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
7284 neon_uimm2_bare, neon_uimm1_bare>;
7285 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
7286 neon_uimm2_bare, neon_uimm1_bare>;
7287 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
7288 neon_uimm1_bare, neon_uimm0_bare>;
7290 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
7292 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
7294 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
7296 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
7298 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
7300 (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
7303 class NeonI_DUP<bit Q, string asmop, string rdlane,
7304 RegisterOperand ResVPR, ValueType ResTy,
7305 RegisterClass OpGPR, ValueType OpTy>
7306 : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
7307 asmop # "\t$Rd" # rdlane # ", $Rn",
7308 [(set (ResTy ResVPR:$Rd),
7309 (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
7312 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
7313 let Inst{20-16} = 0b00001;
7314 // bits 17-20 are unspecified, but should be set to zero.
7317 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
7318 let Inst{20-16} = 0b00010;
7319 // bits 18-20 are unspecified, but should be set to zero.
7322 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
7323 let Inst{20-16} = 0b00100;
7324 // bits 19-20 are unspecified, but should be set to zero.
7327 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
7328 let Inst{20-16} = 0b01000;
7329 // bit 20 is unspecified, but should be set to zero.
7332 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
7333 let Inst{20-16} = 0b00001;
7334 // bits 17-20 are unspecified, but should be set to zero.
7337 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
7338 let Inst{20-16} = 0b00010;
7339 // bits 18-20 are unspecified, but should be set to zero.
7342 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
7343 let Inst{20-16} = 0b00100;
7344 // bits 19-20 are unspecified, but should be set to zero.
7347 // patterns for CONCAT_VECTORS
7348 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
7349 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
7350 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
7351 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
7353 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7354 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
7357 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
7359 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7363 defm : Concat_Vector_Pattern<v16i8, v8i8>;
7364 defm : Concat_Vector_Pattern<v8i16, v4i16>;
7365 defm : Concat_Vector_Pattern<v4i32, v2i32>;
7366 defm : Concat_Vector_Pattern<v2i64, v1i64>;
7367 defm : Concat_Vector_Pattern<v4f32, v2f32>;
7368 defm : Concat_Vector_Pattern<v2f64, v1f64>;
7370 //patterns for EXTRACT_SUBVECTOR
7371 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
7372 (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7373 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
7374 (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7375 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
7376 (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7377 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
7378 (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7379 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
7380 (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7381 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
7382 (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7384 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7385 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7386 SDPatternOperator Neon_Rev>
7387 : NeonI_2VMisc<Q, U, size, opcode,
7388 (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7389 asmop # "\t$Rd." # Res # ", $Rn." # Res,
7390 [(set (ResTy ResVPR:$Rd),
7391 (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7394 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7396 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7398 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7400 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7402 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7404 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7407 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7408 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7410 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7412 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7414 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7416 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7419 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7421 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7424 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7425 SDPatternOperator Neon_Padd> {
7426 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7427 (outs VPR128:$Rd), (ins VPR128:$Rn),
7428 asmop # "\t$Rd.8h, $Rn.16b",
7429 [(set (v8i16 VPR128:$Rd),
7430 (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7433 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7434 (outs VPR64:$Rd), (ins VPR64:$Rn),
7435 asmop # "\t$Rd.4h, $Rn.8b",
7436 [(set (v4i16 VPR64:$Rd),
7437 (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7440 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7441 (outs VPR128:$Rd), (ins VPR128:$Rn),
7442 asmop # "\t$Rd.4s, $Rn.8h",
7443 [(set (v4i32 VPR128:$Rd),
7444 (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7447 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7448 (outs VPR64:$Rd), (ins VPR64:$Rn),
7449 asmop # "\t$Rd.2s, $Rn.4h",
7450 [(set (v2i32 VPR64:$Rd),
7451 (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7454 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7455 (outs VPR128:$Rd), (ins VPR128:$Rn),
7456 asmop # "\t$Rd.2d, $Rn.4s",
7457 [(set (v2i64 VPR128:$Rd),
7458 (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7461 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7462 (outs VPR64:$Rd), (ins VPR64:$Rn),
7463 asmop # "\t$Rd.1d, $Rn.2s",
7464 [(set (v1i64 VPR64:$Rd),
7465 (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7469 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7470 int_arm_neon_vpaddls>;
7471 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7472 int_arm_neon_vpaddlu>;
7474 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7475 SDPatternOperator Neon_Padd> {
7476 let Constraints = "$src = $Rd" in {
7477 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7478 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7479 asmop # "\t$Rd.8h, $Rn.16b",
7480 [(set (v8i16 VPR128:$Rd),
7482 (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7485 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7486 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7487 asmop # "\t$Rd.4h, $Rn.8b",
7488 [(set (v4i16 VPR64:$Rd),
7490 (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7493 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7494 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7495 asmop # "\t$Rd.4s, $Rn.8h",
7496 [(set (v4i32 VPR128:$Rd),
7498 (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7501 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7502 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7503 asmop # "\t$Rd.2s, $Rn.4h",
7504 [(set (v2i32 VPR64:$Rd),
7506 (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7509 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7510 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7511 asmop # "\t$Rd.2d, $Rn.4s",
7512 [(set (v2i64 VPR128:$Rd),
7514 (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7517 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7518 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7519 asmop # "\t$Rd.1d, $Rn.2s",
7520 [(set (v1i64 VPR64:$Rd),
7522 (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7527 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7528 int_arm_neon_vpadals>;
7529 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7530 int_arm_neon_vpadalu>;
7532 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7533 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7534 (outs VPR128:$Rd), (ins VPR128:$Rn),
7535 asmop # "\t$Rd.16b, $Rn.16b",
7538 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7539 (outs VPR128:$Rd), (ins VPR128:$Rn),
7540 asmop # "\t$Rd.8h, $Rn.8h",
7543 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7544 (outs VPR128:$Rd), (ins VPR128:$Rn),
7545 asmop # "\t$Rd.4s, $Rn.4s",
7548 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7549 (outs VPR128:$Rd), (ins VPR128:$Rn),
7550 asmop # "\t$Rd.2d, $Rn.2d",
7553 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7554 (outs VPR64:$Rd), (ins VPR64:$Rn),
7555 asmop # "\t$Rd.8b, $Rn.8b",
7558 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7559 (outs VPR64:$Rd), (ins VPR64:$Rn),
7560 asmop # "\t$Rd.4h, $Rn.4h",
7563 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7564 (outs VPR64:$Rd), (ins VPR64:$Rn),
7565 asmop # "\t$Rd.2s, $Rn.2s",
7569 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
7570 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
7571 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
7572 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
7574 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
7575 SDPatternOperator Neon_Op> {
7576 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
7577 (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
7579 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
7580 (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
7582 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
7583 (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
7585 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
7586 (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
7588 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
7589 (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
7591 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
7592 (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
7594 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
7595 (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
7598 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
7599 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
7600 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
7602 def : Pat<(v16i8 (sub
7603 (v16i8 Neon_AllZero),
7604 (v16i8 VPR128:$Rn))),
7605 (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
7606 def : Pat<(v8i8 (sub
7607 (v8i8 Neon_AllZero),
7609 (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
7610 def : Pat<(v8i16 (sub
7611 (v8i16 (bitconvert (v16i8 Neon_AllZero))),
7612 (v8i16 VPR128:$Rn))),
7613 (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
7614 def : Pat<(v4i16 (sub
7615 (v4i16 (bitconvert (v8i8 Neon_AllZero))),
7616 (v4i16 VPR64:$Rn))),
7617 (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
7618 def : Pat<(v4i32 (sub
7619 (v4i32 (bitconvert (v16i8 Neon_AllZero))),
7620 (v4i32 VPR128:$Rn))),
7621 (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
7622 def : Pat<(v2i32 (sub
7623 (v2i32 (bitconvert (v8i8 Neon_AllZero))),
7624 (v2i32 VPR64:$Rn))),
7625 (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
7626 def : Pat<(v2i64 (sub
7627 (v2i64 (bitconvert (v16i8 Neon_AllZero))),
7628 (v2i64 VPR128:$Rn))),
7629 (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
7631 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
7632 let Constraints = "$src = $Rd" in {
7633 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7634 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7635 asmop # "\t$Rd.16b, $Rn.16b",
7638 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7639 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7640 asmop # "\t$Rd.8h, $Rn.8h",
7643 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7644 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7645 asmop # "\t$Rd.4s, $Rn.4s",
7648 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7649 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7650 asmop # "\t$Rd.2d, $Rn.2d",
7653 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7654 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7655 asmop # "\t$Rd.8b, $Rn.8b",
7658 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7659 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7660 asmop # "\t$Rd.4h, $Rn.4h",
7663 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7664 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7665 asmop # "\t$Rd.2s, $Rn.2s",
7670 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
7671 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
7673 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
7674 SDPatternOperator Neon_Op> {
7675 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
7676 (v16i8 (!cast<Instruction>(Prefix # 16b)
7677 (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
7679 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
7680 (v8i16 (!cast<Instruction>(Prefix # 8h)
7681 (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
7683 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
7684 (v4i32 (!cast<Instruction>(Prefix # 4s)
7685 (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
7687 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
7688 (v2i64 (!cast<Instruction>(Prefix # 2d)
7689 (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
7691 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
7692 (v8i8 (!cast<Instruction>(Prefix # 8b)
7693 (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
7695 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
7696 (v4i16 (!cast<Instruction>(Prefix # 4h)
7697 (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
7699 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
7700 (v2i32 (!cast<Instruction>(Prefix # 2s)
7701 (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
7704 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
7705 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
7707 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
7708 SDPatternOperator Neon_Op> {
7709 def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
7710 (outs VPR128:$Rd), (ins VPR128:$Rn),
7711 asmop # "\t$Rd.16b, $Rn.16b",
7712 [(set (v16i8 VPR128:$Rd),
7713 (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
7716 def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
7717 (outs VPR128:$Rd), (ins VPR128:$Rn),
7718 asmop # "\t$Rd.8h, $Rn.8h",
7719 [(set (v8i16 VPR128:$Rd),
7720 (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
7723 def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
7724 (outs VPR128:$Rd), (ins VPR128:$Rn),
7725 asmop # "\t$Rd.4s, $Rn.4s",
7726 [(set (v4i32 VPR128:$Rd),
7727 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
7730 def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
7731 (outs VPR64:$Rd), (ins VPR64:$Rn),
7732 asmop # "\t$Rd.8b, $Rn.8b",
7733 [(set (v8i8 VPR64:$Rd),
7734 (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
7737 def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
7738 (outs VPR64:$Rd), (ins VPR64:$Rn),
7739 asmop # "\t$Rd.4h, $Rn.4h",
7740 [(set (v4i16 VPR64:$Rd),
7741 (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
7744 def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
7745 (outs VPR64:$Rd), (ins VPR64:$Rn),
7746 asmop # "\t$Rd.2s, $Rn.2s",
7747 [(set (v2i32 VPR64:$Rd),
7748 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
7752 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
7753 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
7755 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
7757 def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
7758 (outs VPR128:$Rd), (ins VPR128:$Rn),
7759 asmop # "\t$Rd.16b, $Rn.16b",
7762 def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
7763 (outs VPR64:$Rd), (ins VPR64:$Rn),
7764 asmop # "\t$Rd.8b, $Rn.8b",
7768 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
7769 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
7770 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
7772 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
7773 (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
7774 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
7775 (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
7777 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
7778 (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
7779 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
7780 (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
7782 def : Pat<(v16i8 (xor
7784 (v16i8 Neon_AllOne))),
7785 (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
7786 def : Pat<(v8i8 (xor
7788 (v8i8 Neon_AllOne))),
7789 (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
7790 def : Pat<(v8i16 (xor
7792 (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
7793 (NOT16b VPR128:$Rn)>;
7794 def : Pat<(v4i16 (xor
7796 (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
7798 def : Pat<(v4i32 (xor
7800 (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
7801 (NOT16b VPR128:$Rn)>;
7802 def : Pat<(v2i32 (xor
7804 (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
7806 def : Pat<(v2i64 (xor
7808 (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
7809 (NOT16b VPR128:$Rn)>;
7811 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
7812 (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
7813 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
7814 (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
7816 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
7817 SDPatternOperator Neon_Op> {
7818 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7819 (outs VPR128:$Rd), (ins VPR128:$Rn),
7820 asmop # "\t$Rd.4s, $Rn.4s",
7821 [(set (v4f32 VPR128:$Rd),
7822 (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
7825 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7826 (outs VPR128:$Rd), (ins VPR128:$Rn),
7827 asmop # "\t$Rd.2d, $Rn.2d",
7828 [(set (v2f64 VPR128:$Rd),
7829 (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
7832 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7833 (outs VPR64:$Rd), (ins VPR64:$Rn),
7834 asmop # "\t$Rd.2s, $Rn.2s",
7835 [(set (v2f32 VPR64:$Rd),
7836 (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
7840 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
7841 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
7843 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
7844 def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7845 (outs VPR64:$Rd), (ins VPR128:$Rn),
7846 asmop # "\t$Rd.8b, $Rn.8h",
7849 def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7850 (outs VPR64:$Rd), (ins VPR128:$Rn),
7851 asmop # "\t$Rd.4h, $Rn.4s",
7854 def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7855 (outs VPR64:$Rd), (ins VPR128:$Rn),
7856 asmop # "\t$Rd.2s, $Rn.2d",
7859 let Constraints = "$Rd = $src" in {
7860 def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7861 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7862 asmop # "2\t$Rd.16b, $Rn.8h",
7865 def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7866 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7867 asmop # "2\t$Rd.8h, $Rn.4s",
7870 def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7871 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7872 asmop # "2\t$Rd.4s, $Rn.2d",
7877 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
7878 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
7879 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
7880 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
7882 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
7883 SDPatternOperator Neon_Op> {
7884 def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
7885 (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
7887 def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
7888 (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
7890 def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
7891 (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
7893 def : Pat<(v16i8 (concat_vectors
7895 (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
7896 (!cast<Instruction>(Prefix # 8h16b)
7897 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
7900 def : Pat<(v8i16 (concat_vectors
7902 (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
7903 (!cast<Instruction>(Prefix # 4s8h)
7904 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
7907 def : Pat<(v4i32 (concat_vectors
7909 (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
7910 (!cast<Instruction>(Prefix # 2d4s)
7911 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
7915 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
7916 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
7917 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
7918 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
7920 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
7921 def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7923 (ins VPR64:$Rn, uimm_exact8:$Imm),
7924 asmop # "\t$Rd.8h, $Rn.8b, $Imm",
7927 def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7929 (ins VPR64:$Rn, uimm_exact16:$Imm),
7930 asmop # "\t$Rd.4s, $Rn.4h, $Imm",
7933 def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7935 (ins VPR64:$Rn, uimm_exact32:$Imm),
7936 asmop # "\t$Rd.2d, $Rn.2s, $Imm",
7939 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7941 (ins VPR128:$Rn, uimm_exact8:$Imm),
7942 asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
7945 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7947 (ins VPR128:$Rn, uimm_exact16:$Imm),
7948 asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
7951 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7953 (ins VPR128:$Rn, uimm_exact32:$Imm),
7954 asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
7958 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
7960 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
7961 SDPatternOperator ExtOp, Operand Neon_Imm,
7964 (DesTy (ExtOp (OpTy VPR64:$Rn))),
7966 (i32 Neon_Imm:$Imm))))),
7967 (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
7969 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
7970 SDPatternOperator ExtOp, Operand Neon_Imm,
7971 string suffix, PatFrag GetHigh>
7974 (OpTy (GetHigh VPR128:$Rn)))),
7976 (i32 Neon_Imm:$Imm))))),
7977 (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
7979 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
7980 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
7981 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
7982 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
7983 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
7984 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
7985 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
7987 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
7989 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
7991 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
7993 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
7995 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
7998 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
7999 def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8000 (outs VPR64:$Rd), (ins VPR128:$Rn),
8001 asmop # "\t$Rd.4h, $Rn.4s",
8004 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8005 (outs VPR64:$Rd), (ins VPR128:$Rn),
8006 asmop # "\t$Rd.2s, $Rn.2d",
8009 let Constraints = "$src = $Rd" in {
8010 def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8011 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8012 asmop # "2\t$Rd.8h, $Rn.4s",
8015 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8016 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8017 asmop # "2\t$Rd.4s, $Rn.2d",
8022 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8024 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8025 SDPatternOperator f32_to_f16_Op,
8026 SDPatternOperator f64_to_f32_Op> {
8028 def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8029 (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8031 def : Pat<(v8i16 (concat_vectors
8033 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8034 (!cast<Instruction>(prefix # "4s8h")
8035 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8036 (v4f32 VPR128:$Rn))>;
8038 def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8039 (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8041 def : Pat<(v4f32 (concat_vectors
8043 (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8044 (!cast<Instruction>(prefix # "2d4s")
8045 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8046 (v2f64 VPR128:$Rn))>;
8049 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8051 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8053 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8054 (outs VPR64:$Rd), (ins VPR128:$Rn),
8055 asmop # "\t$Rd.2s, $Rn.2d",
8058 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8059 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8060 asmop # "2\t$Rd.4s, $Rn.2d",
8062 let Constraints = "$src = $Rd";
8065 def : Pat<(v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))),
8066 (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8068 def : Pat<(v4f32 (concat_vectors
8070 (v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))))),
8071 (!cast<Instruction>(prefix # "2d4s")
8072 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8076 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8078 def Neon_High4Float : PatFrag<(ops node:$in),
8079 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8081 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8082 def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8083 (outs VPR128:$Rd), (ins VPR64:$Rn),
8084 asmop # "\t$Rd.4s, $Rn.4h",
8087 def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8088 (outs VPR128:$Rd), (ins VPR64:$Rn),
8089 asmop # "\t$Rd.2d, $Rn.2s",
8092 def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8093 (outs VPR128:$Rd), (ins VPR128:$Rn),
8094 asmop # "2\t$Rd.4s, $Rn.8h",
8097 def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8098 (outs VPR128:$Rd), (ins VPR128:$Rn),
8099 asmop # "2\t$Rd.2d, $Rn.4s",
8103 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8105 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8106 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8107 (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8109 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8111 (v8i16 VPR128:$Rn))))),
8112 (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8114 def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8115 (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8117 def : Pat<(v2f64 (fextend
8118 (v2f32 (Neon_High4Float
8119 (v4f32 VPR128:$Rn))))),
8120 (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8123 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8125 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8126 ValueType ResTy4s, ValueType OpTy4s,
8127 ValueType ResTy2d, ValueType OpTy2d,
8128 ValueType ResTy2s, ValueType OpTy2s,
8129 SDPatternOperator Neon_Op> {
8131 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8132 (outs VPR128:$Rd), (ins VPR128:$Rn),
8133 asmop # "\t$Rd.4s, $Rn.4s",
8134 [(set (ResTy4s VPR128:$Rd),
8135 (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8138 def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8139 (outs VPR128:$Rd), (ins VPR128:$Rn),
8140 asmop # "\t$Rd.2d, $Rn.2d",
8141 [(set (ResTy2d VPR128:$Rd),
8142 (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8145 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8146 (outs VPR64:$Rd), (ins VPR64:$Rn),
8147 asmop # "\t$Rd.2s, $Rn.2s",
8148 [(set (ResTy2s VPR64:$Rd),
8149 (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8153 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8154 bits<5> opcode, SDPatternOperator Neon_Op> {
8155 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8156 v2f64, v2i32, v2f32, Neon_Op>;
8159 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8160 int_aarch64_neon_fcvtns>;
8161 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8162 int_aarch64_neon_fcvtnu>;
8163 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8164 int_aarch64_neon_fcvtps>;
8165 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8166 int_aarch64_neon_fcvtpu>;
8167 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8168 int_aarch64_neon_fcvtms>;
8169 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8170 int_aarch64_neon_fcvtmu>;
8171 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8172 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8173 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8174 int_aarch64_neon_fcvtas>;
8175 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8176 int_aarch64_neon_fcvtau>;
8178 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8179 bits<5> opcode, SDPatternOperator Neon_Op> {
8180 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8181 v2i64, v2f32, v2i32, Neon_Op>;
8184 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8185 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8187 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8188 bits<5> opcode, SDPatternOperator Neon_Op> {
8189 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8190 v2f64, v2f32, v2f32, Neon_Op>;
8193 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8194 int_aarch64_neon_frintn>;
8195 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8196 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8197 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8198 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8199 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8200 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8201 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8202 int_arm_neon_vrecpe>;
8203 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8204 int_arm_neon_vrsqrte>;
8205 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111,
8206 int_aarch64_neon_fsqrt>;
8208 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8209 bits<5> opcode, SDPatternOperator Neon_Op> {
8210 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8211 (outs VPR128:$Rd), (ins VPR128:$Rn),
8212 asmop # "\t$Rd.4s, $Rn.4s",
8213 [(set (v4i32 VPR128:$Rd),
8214 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8217 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8218 (outs VPR64:$Rd), (ins VPR64:$Rn),
8219 asmop # "\t$Rd.2s, $Rn.2s",
8220 [(set (v2i32 VPR64:$Rd),
8221 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8225 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8226 int_arm_neon_vrecpe>;
8227 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8228 int_arm_neon_vrsqrte>;
8231 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8232 string asmop, SDPatternOperator opnode>
8233 : NeonI_Crypto_AES<size, opcode,
8234 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8235 asmop # "\t$Rd.16b, $Rn.16b",
8236 [(set (v16i8 VPR128:$Rd),
8237 (v16i8 (opnode (v16i8 VPR128:$src),
8238 (v16i8 VPR128:$Rn))))],
8240 let Constraints = "$src = $Rd";
8241 let Predicates = [HasNEON, HasCrypto];
8244 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8245 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8247 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8248 string asmop, SDPatternOperator opnode>
8249 : NeonI_Crypto_AES<size, opcode,
8250 (outs VPR128:$Rd), (ins VPR128:$Rn),
8251 asmop # "\t$Rd.16b, $Rn.16b",
8252 [(set (v16i8 VPR128:$Rd),
8253 (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8256 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8257 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8259 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8260 string asmop, SDPatternOperator opnode>
8261 : NeonI_Crypto_SHA<size, opcode,
8262 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8263 asmop # "\t$Rd.4s, $Rn.4s",
8264 [(set (v4i32 VPR128:$Rd),
8265 (v4i32 (opnode (v4i32 VPR128:$src),
8266 (v4i32 VPR128:$Rn))))],
8268 let Constraints = "$src = $Rd";
8269 let Predicates = [HasNEON, HasCrypto];
8272 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8273 int_arm_neon_sha1su1>;
8274 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8275 int_arm_neon_sha256su0>;
8277 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8278 string asmop, SDPatternOperator opnode>
8279 : NeonI_Crypto_SHA<size, opcode,
8280 (outs FPR32:$Rd), (ins FPR32:$Rn),
8281 asmop # "\t$Rd, $Rn",
8282 [(set (v1i32 FPR32:$Rd),
8283 (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8285 let Predicates = [HasNEON, HasCrypto];
8288 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8290 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8291 SDPatternOperator opnode>
8292 : NeonI_Crypto_3VSHA<size, opcode,
8294 (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8295 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8296 [(set (v4i32 VPR128:$Rd),
8297 (v4i32 (opnode (v4i32 VPR128:$src),
8299 (v4i32 VPR128:$Rm))))],
8301 let Constraints = "$src = $Rd";
8302 let Predicates = [HasNEON, HasCrypto];
8305 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8306 int_arm_neon_sha1su0>;
8307 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8308 int_arm_neon_sha256su1>;
8310 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8311 SDPatternOperator opnode>
8312 : NeonI_Crypto_3VSHA<size, opcode,
8314 (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8315 asmop # "\t$Rd, $Rn, $Rm.4s",
8316 [(set (v4i32 FPR128:$Rd),
8317 (v4i32 (opnode (v4i32 FPR128:$src),
8319 (v4i32 VPR128:$Rm))))],
8321 let Constraints = "$src = $Rd";
8322 let Predicates = [HasNEON, HasCrypto];
8325 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8326 int_arm_neon_sha256h>;
8327 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8328 int_arm_neon_sha256h2>;
8330 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8331 SDPatternOperator opnode>
8332 : NeonI_Crypto_3VSHA<size, opcode,
8334 (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8335 asmop # "\t$Rd, $Rn, $Rm.4s",
8336 [(set (v4i32 FPR128:$Rd),
8337 (v4i32 (opnode (v4i32 FPR128:$src),
8339 (v4i32 VPR128:$Rm))))],
8341 let Constraints = "$src = $Rd";
8342 let Predicates = [HasNEON, HasCrypto];
8345 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8346 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8347 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;