1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // (outs Result), (ins Imm, OpCmode)
19 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
21 def Neon_movi : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
23 def Neon_mvni : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
25 // (outs Result), (ins Imm)
26 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
27 [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
29 // (outs Result), (ins LHS, RHS, CondCode)
30 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
31 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
33 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
34 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
35 [SDTCisVec<0>, SDTCisVec<1>]>>;
37 // (outs Result), (ins LHS, RHS)
38 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
39 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
41 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
43 def Neon_sqrshlImm : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
44 def Neon_uqrshlImm : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
46 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
48 def Neon_uzp1 : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
49 def Neon_uzp2 : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
50 def Neon_zip1 : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
51 def Neon_zip2 : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
52 def Neon_trn1 : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
53 def Neon_trn2 : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
55 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
56 def Neon_rev64 : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
57 def Neon_rev32 : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
58 def Neon_rev16 : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
59 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
61 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
62 [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
63 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
64 [SDTCisVec<0>, SDTCisSameAs<0, 1>,
65 SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
67 def SDT_assertext : SDTypeProfile<1, 1,
68 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
69 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
70 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
72 //===----------------------------------------------------------------------===//
73 // Addressing-mode instantiations
74 //===----------------------------------------------------------------------===//
76 multiclass ls_64_pats<dag address, dag Base, dag Offset, ValueType Ty> {
77 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
78 !foreach(decls.pattern, Offset,
79 !subst(OFFSET, dword_uimm12, decls.pattern)),
80 !foreach(decls.pattern, address,
81 !subst(OFFSET, dword_uimm12,
82 !subst(ALIGN, min_align8, decls.pattern))),
86 multiclass ls_128_pats<dag address, dag Base, dag Offset, ValueType Ty> {
87 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
88 !foreach(decls.pattern, Offset,
89 !subst(OFFSET, qword_uimm12, decls.pattern)),
90 !foreach(decls.pattern, address,
91 !subst(OFFSET, qword_uimm12,
92 !subst(ALIGN, min_align16, decls.pattern))),
96 multiclass uimm12_neon_pats<dag address, dag Base, dag Offset> {
97 defm : ls_64_pats<address, Base, Offset, v8i8>;
98 defm : ls_64_pats<address, Base, Offset, v4i16>;
99 defm : ls_64_pats<address, Base, Offset, v2i32>;
100 defm : ls_64_pats<address, Base, Offset, v1i64>;
101 defm : ls_64_pats<address, Base, Offset, v2f32>;
102 defm : ls_64_pats<address, Base, Offset, v1f64>;
104 defm : ls_128_pats<address, Base, Offset, v16i8>;
105 defm : ls_128_pats<address, Base, Offset, v8i16>;
106 defm : ls_128_pats<address, Base, Offset, v4i32>;
107 defm : ls_128_pats<address, Base, Offset, v2i64>;
108 defm : ls_128_pats<address, Base, Offset, v4f32>;
109 defm : ls_128_pats<address, Base, Offset, v2f64>;
112 defm : uimm12_neon_pats<(A64WrapperSmall
113 tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
114 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
116 //===----------------------------------------------------------------------===//
118 //===----------------------------------------------------------------------===//
120 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size, bits<5> opcode,
121 string asmop, SDPatternOperator opnode8B,
122 SDPatternOperator opnode16B,
123 bit Commutable = 0> {
124 let isCommutable = Commutable in {
125 def _8B : NeonI_3VSame<0b0, u, size, opcode,
126 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
127 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
128 [(set (v8i8 VPR64:$Rd),
129 (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
132 def _16B : NeonI_3VSame<0b1, u, size, opcode,
133 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
134 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
135 [(set (v16i8 VPR128:$Rd),
136 (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
142 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
143 string asmop, SDPatternOperator opnode,
144 bit Commutable = 0> {
145 let isCommutable = Commutable in {
146 def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
147 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
148 asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
149 [(set (v4i16 VPR64:$Rd),
150 (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
153 def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
154 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
155 asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
156 [(set (v8i16 VPR128:$Rd),
157 (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
160 def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
161 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
162 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
163 [(set (v2i32 VPR64:$Rd),
164 (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
167 def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
168 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
169 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
170 [(set (v4i32 VPR128:$Rd),
171 (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
175 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
176 string asmop, SDPatternOperator opnode,
178 : NeonI_3VSame_HS_sizes<u, opcode, asmop, opnode, Commutable> {
179 let isCommutable = Commutable in {
180 def _8B : NeonI_3VSame<0b0, u, 0b00, opcode,
181 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
182 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
183 [(set (v8i8 VPR64:$Rd),
184 (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
187 def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
188 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
189 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
190 [(set (v16i8 VPR128:$Rd),
191 (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
196 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
197 string asmop, SDPatternOperator opnode,
199 : NeonI_3VSame_BHS_sizes<u, opcode, asmop, opnode, Commutable> {
200 let isCommutable = Commutable in {
201 def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
202 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
203 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
204 [(set (v2i64 VPR128:$Rd),
205 (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
210 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
211 // but Result types can be integer or floating point types.
212 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
213 string asmop, SDPatternOperator opnode2S,
214 SDPatternOperator opnode4S,
215 SDPatternOperator opnode2D,
216 ValueType ResTy2S, ValueType ResTy4S,
217 ValueType ResTy2D, bit Commutable = 0> {
218 let isCommutable = Commutable in {
219 def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
220 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
221 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
222 [(set (ResTy2S VPR64:$Rd),
223 (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
226 def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
227 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
228 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
229 [(set (ResTy4S VPR128:$Rd),
230 (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
233 def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
234 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
235 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
236 [(set (ResTy2D VPR128:$Rd),
237 (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
242 //===----------------------------------------------------------------------===//
243 // Instruction Definitions
244 //===----------------------------------------------------------------------===//
246 // Vector Arithmetic Instructions
248 // Vector Add (Integer and Floating-Point)
250 defm ADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
251 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
252 v2f32, v4f32, v2f64, 1>;
254 // Vector Sub (Integer and Floating-Point)
256 defm SUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
257 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
258 v2f32, v4f32, v2f64, 0>;
260 // Vector Multiply (Integer and Floating-Point)
262 defm MULvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
263 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
264 v2f32, v4f32, v2f64, 1>;
266 // Vector Multiply (Polynomial)
268 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
269 int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
271 // Vector Multiply-accumulate and Multiply-subtract (Integer)
273 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
274 // two operands constraints.
275 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
276 RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
277 bits<5> opcode, SDPatternOperator opnode>
278 : NeonI_3VSame<q, u, size, opcode,
279 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
280 asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
281 [(set (OpTy VPRC:$Rd),
282 (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
284 let Constraints = "$src = $Rd";
287 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
288 (add node:$Ra, (mul node:$Rn, node:$Rm))>;
290 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
291 (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
294 def MLAvvv_8B: NeonI_3VSame_Constraint_impl<"mla", ".8b", VPR64, v8i8,
295 0b0, 0b0, 0b00, 0b10010, Neon_mla>;
296 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
297 0b1, 0b0, 0b00, 0b10010, Neon_mla>;
298 def MLAvvv_4H: NeonI_3VSame_Constraint_impl<"mla", ".4h", VPR64, v4i16,
299 0b0, 0b0, 0b01, 0b10010, Neon_mla>;
300 def MLAvvv_8H: NeonI_3VSame_Constraint_impl<"mla", ".8h", VPR128, v8i16,
301 0b1, 0b0, 0b01, 0b10010, Neon_mla>;
302 def MLAvvv_2S: NeonI_3VSame_Constraint_impl<"mla", ".2s", VPR64, v2i32,
303 0b0, 0b0, 0b10, 0b10010, Neon_mla>;
304 def MLAvvv_4S: NeonI_3VSame_Constraint_impl<"mla", ".4s", VPR128, v4i32,
305 0b1, 0b0, 0b10, 0b10010, Neon_mla>;
307 def MLSvvv_8B: NeonI_3VSame_Constraint_impl<"mls", ".8b", VPR64, v8i8,
308 0b0, 0b1, 0b00, 0b10010, Neon_mls>;
309 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
310 0b1, 0b1, 0b00, 0b10010, Neon_mls>;
311 def MLSvvv_4H: NeonI_3VSame_Constraint_impl<"mls", ".4h", VPR64, v4i16,
312 0b0, 0b1, 0b01, 0b10010, Neon_mls>;
313 def MLSvvv_8H: NeonI_3VSame_Constraint_impl<"mls", ".8h", VPR128, v8i16,
314 0b1, 0b1, 0b01, 0b10010, Neon_mls>;
315 def MLSvvv_2S: NeonI_3VSame_Constraint_impl<"mls", ".2s", VPR64, v2i32,
316 0b0, 0b1, 0b10, 0b10010, Neon_mls>;
317 def MLSvvv_4S: NeonI_3VSame_Constraint_impl<"mls", ".4s", VPR128, v4i32,
318 0b1, 0b1, 0b10, 0b10010, Neon_mls>;
320 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
322 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
323 (fadd node:$Ra, (fmul_su node:$Rn, node:$Rm))>;
325 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
326 (fsub node:$Ra, (fmul_su node:$Rn, node:$Rm))>;
328 let Predicates = [HasNEON, UseFusedMAC] in {
329 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s", VPR64, v2f32,
330 0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
331 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s", VPR128, v4f32,
332 0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
333 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d", VPR128, v2f64,
334 0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
336 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s", VPR64, v2f32,
337 0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
338 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s", VPR128, v4f32,
339 0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
340 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d", VPR128, v2f64,
341 0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
344 // We're also allowed to match the fma instruction regardless of compile
346 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
347 (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
348 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
349 (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
350 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
351 (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
353 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
354 (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
355 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
356 (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
357 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
358 (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
360 // Vector Divide (Floating-Point)
362 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
363 v2f32, v4f32, v2f64, 0>;
365 // Vector Bitwise Operations
367 // Vector Bitwise AND
369 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
371 // Vector Bitwise Exclusive OR
373 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
377 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
379 // ORR disassembled as MOV if Vn==Vm
381 // Vector Move - register
382 // Alias for ORR if Vn=Vm.
383 // FIXME: This is actually the preferred syntax but TableGen can't deal with
384 // custom printing of aliases.
385 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
386 (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
387 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
388 (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
390 // The MOVI instruction takes two immediate operands. The first is the
391 // immediate encoding, while the second is the cmode. A cmode of 14, or
392 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
393 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
394 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
396 def Neon_not8B : PatFrag<(ops node:$in),
397 (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
398 def Neon_not16B : PatFrag<(ops node:$in),
399 (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
401 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
402 (or node:$Rn, (Neon_not8B node:$Rm))>;
404 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
405 (or node:$Rn, (Neon_not16B node:$Rm))>;
407 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
408 (and node:$Rn, (Neon_not8B node:$Rm))>;
410 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
411 (and node:$Rn, (Neon_not16B node:$Rm))>;
414 // Vector Bitwise OR NOT - register
416 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
417 Neon_orn8B, Neon_orn16B, 0>;
419 // Vector Bitwise Bit Clear (AND NOT) - register
421 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
422 Neon_bic8B, Neon_bic16B, 0>;
424 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
425 SDPatternOperator opnode16B,
427 Instruction INST16B> {
428 def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
429 (INST8B VPR64:$Rn, VPR64:$Rm)>;
430 def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
431 (INST8B VPR64:$Rn, VPR64:$Rm)>;
432 def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
433 (INST8B VPR64:$Rn, VPR64:$Rm)>;
434 def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
435 (INST16B VPR128:$Rn, VPR128:$Rm)>;
436 def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
437 (INST16B VPR128:$Rn, VPR128:$Rm)>;
438 def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
439 (INST16B VPR128:$Rn, VPR128:$Rm)>;
442 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
443 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
444 defm : Neon_bitwise2V_patterns<or, or, ORRvvv_8B, ORRvvv_16B>;
445 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
446 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
447 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
449 // Vector Bitwise Select
450 def BSLvvv_8B : NeonI_3VSame_Constraint_impl<"bsl", ".8b", VPR64, v8i8,
451 0b0, 0b1, 0b01, 0b00011, vselect>;
453 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
454 0b1, 0b1, 0b01, 0b00011, vselect>;
456 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
458 Instruction INST16B> {
459 // Disassociate type from instruction definition
460 def : Pat<(v8i8 (opnode (v8i8 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
461 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
462 def : Pat<(v2i32 (opnode (v2i32 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
463 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
464 def : Pat<(v4i16 (opnode (v4i16 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
465 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
466 def : Pat<(v1i64 (opnode (v1i64 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
467 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
468 def : Pat<(v16i8 (opnode (v16i8 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
469 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
470 def : Pat<(v4i32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
471 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
472 def : Pat<(v8i16 (opnode (v8i16 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
473 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
474 def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
475 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
477 // Allow to match BSL instruction pattern with non-constant operand
478 def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
479 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
480 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
481 def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
482 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
483 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
484 def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
485 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
486 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
487 def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
488 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
489 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
490 def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
491 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
492 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
493 def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
494 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
495 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
496 def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
497 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
498 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
499 def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
500 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
501 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
503 // Allow to match llvm.arm.* intrinsics.
504 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
505 (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
506 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
507 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
508 (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
509 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
510 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
511 (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
512 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
513 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
514 (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
515 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
516 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
517 (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
518 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
519 def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
520 (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
521 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
522 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
523 (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
524 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
525 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
526 (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
527 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
528 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
529 (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
530 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
531 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
532 (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
533 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
534 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
535 (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
536 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
537 def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
538 (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
539 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
542 // Additional patterns for bitwise instruction BSL
543 defm: Neon_bitwise3V_patterns<vselect, BSLvvv_8B, BSLvvv_16B>;
545 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
546 (vselect node:$src, node:$Rn, node:$Rm),
547 [{ (void)N; return false; }]>;
549 // Vector Bitwise Insert if True
551 def BITvvv_8B : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64, v8i8,
552 0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
553 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
554 0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
556 // Vector Bitwise Insert if False
558 def BIFvvv_8B : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64, v8i8,
559 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
560 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
561 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
563 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
565 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
566 (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
567 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
568 (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
570 // Vector Absolute Difference and Accumulate (Unsigned)
571 def UABAvvv_8B : NeonI_3VSame_Constraint_impl<"uaba", ".8b", VPR64, v8i8,
572 0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
573 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
574 0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
575 def UABAvvv_4H : NeonI_3VSame_Constraint_impl<"uaba", ".4h", VPR64, v4i16,
576 0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
577 def UABAvvv_8H : NeonI_3VSame_Constraint_impl<"uaba", ".8h", VPR128, v8i16,
578 0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
579 def UABAvvv_2S : NeonI_3VSame_Constraint_impl<"uaba", ".2s", VPR64, v2i32,
580 0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
581 def UABAvvv_4S : NeonI_3VSame_Constraint_impl<"uaba", ".4s", VPR128, v4i32,
582 0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
584 // Vector Absolute Difference and Accumulate (Signed)
585 def SABAvvv_8B : NeonI_3VSame_Constraint_impl<"saba", ".8b", VPR64, v8i8,
586 0b0, 0b0, 0b00, 0b01111, Neon_saba>;
587 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
588 0b1, 0b0, 0b00, 0b01111, Neon_saba>;
589 def SABAvvv_4H : NeonI_3VSame_Constraint_impl<"saba", ".4h", VPR64, v4i16,
590 0b0, 0b0, 0b01, 0b01111, Neon_saba>;
591 def SABAvvv_8H : NeonI_3VSame_Constraint_impl<"saba", ".8h", VPR128, v8i16,
592 0b1, 0b0, 0b01, 0b01111, Neon_saba>;
593 def SABAvvv_2S : NeonI_3VSame_Constraint_impl<"saba", ".2s", VPR64, v2i32,
594 0b0, 0b0, 0b10, 0b01111, Neon_saba>;
595 def SABAvvv_4S : NeonI_3VSame_Constraint_impl<"saba", ".4s", VPR128, v4i32,
596 0b1, 0b0, 0b10, 0b01111, Neon_saba>;
599 // Vector Absolute Difference (Signed, Unsigned)
600 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
601 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
603 // Vector Absolute Difference (Floating Point)
604 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
605 int_arm_neon_vabds, int_arm_neon_vabds,
606 int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
608 // Vector Reciprocal Step (Floating Point)
609 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
610 int_arm_neon_vrecps, int_arm_neon_vrecps,
612 v2f32, v4f32, v2f64, 0>;
614 // Vector Reciprocal Square Root Step (Floating Point)
615 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
616 int_arm_neon_vrsqrts,
617 int_arm_neon_vrsqrts,
618 int_arm_neon_vrsqrts,
619 v2f32, v4f32, v2f64, 0>;
621 // Vector Comparisons
623 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
624 (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
625 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
626 (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
627 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
628 (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
629 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
630 (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
631 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
632 (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
634 // NeonI_compare_aliases class: swaps register operands to implement
635 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
636 class NeonI_compare_aliases<string asmop, string asmlane,
637 Instruction inst, RegisterOperand VPRC>
638 : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
640 (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
642 // Vector Comparisons (Integer)
644 // Vector Compare Mask Equal (Integer)
645 let isCommutable =1 in {
646 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
649 // Vector Compare Mask Higher or Same (Unsigned Integer)
650 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
652 // Vector Compare Mask Greater Than or Equal (Integer)
653 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
655 // Vector Compare Mask Higher (Unsigned Integer)
656 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
658 // Vector Compare Mask Greater Than (Integer)
659 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
661 // Vector Compare Mask Bitwise Test (Integer)
662 defm CMTSTvvv: NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
664 // Vector Compare Mask Less or Same (Unsigned Integer)
665 // CMLS is alias for CMHS with operands reversed.
666 def CMLSvvv_8B : NeonI_compare_aliases<"cmls", ".8b", CMHSvvv_8B, VPR64>;
667 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
668 def CMLSvvv_4H : NeonI_compare_aliases<"cmls", ".4h", CMHSvvv_4H, VPR64>;
669 def CMLSvvv_8H : NeonI_compare_aliases<"cmls", ".8h", CMHSvvv_8H, VPR128>;
670 def CMLSvvv_2S : NeonI_compare_aliases<"cmls", ".2s", CMHSvvv_2S, VPR64>;
671 def CMLSvvv_4S : NeonI_compare_aliases<"cmls", ".4s", CMHSvvv_4S, VPR128>;
672 def CMLSvvv_2D : NeonI_compare_aliases<"cmls", ".2d", CMHSvvv_2D, VPR128>;
674 // Vector Compare Mask Less Than or Equal (Integer)
675 // CMLE is alias for CMGE with operands reversed.
676 def CMLEvvv_8B : NeonI_compare_aliases<"cmle", ".8b", CMGEvvv_8B, VPR64>;
677 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
678 def CMLEvvv_4H : NeonI_compare_aliases<"cmle", ".4h", CMGEvvv_4H, VPR64>;
679 def CMLEvvv_8H : NeonI_compare_aliases<"cmle", ".8h", CMGEvvv_8H, VPR128>;
680 def CMLEvvv_2S : NeonI_compare_aliases<"cmle", ".2s", CMGEvvv_2S, VPR64>;
681 def CMLEvvv_4S : NeonI_compare_aliases<"cmle", ".4s", CMGEvvv_4S, VPR128>;
682 def CMLEvvv_2D : NeonI_compare_aliases<"cmle", ".2d", CMGEvvv_2D, VPR128>;
684 // Vector Compare Mask Lower (Unsigned Integer)
685 // CMLO is alias for CMHI with operands reversed.
686 def CMLOvvv_8B : NeonI_compare_aliases<"cmlo", ".8b", CMHIvvv_8B, VPR64>;
687 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
688 def CMLOvvv_4H : NeonI_compare_aliases<"cmlo", ".4h", CMHIvvv_4H, VPR64>;
689 def CMLOvvv_8H : NeonI_compare_aliases<"cmlo", ".8h", CMHIvvv_8H, VPR128>;
690 def CMLOvvv_2S : NeonI_compare_aliases<"cmlo", ".2s", CMHIvvv_2S, VPR64>;
691 def CMLOvvv_4S : NeonI_compare_aliases<"cmlo", ".4s", CMHIvvv_4S, VPR128>;
692 def CMLOvvv_2D : NeonI_compare_aliases<"cmlo", ".2d", CMHIvvv_2D, VPR128>;
694 // Vector Compare Mask Less Than (Integer)
695 // CMLT is alias for CMGT with operands reversed.
696 def CMLTvvv_8B : NeonI_compare_aliases<"cmlt", ".8b", CMGTvvv_8B, VPR64>;
697 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
698 def CMLTvvv_4H : NeonI_compare_aliases<"cmlt", ".4h", CMGTvvv_4H, VPR64>;
699 def CMLTvvv_8H : NeonI_compare_aliases<"cmlt", ".8h", CMGTvvv_8H, VPR128>;
700 def CMLTvvv_2S : NeonI_compare_aliases<"cmlt", ".2s", CMGTvvv_2S, VPR64>;
701 def CMLTvvv_4S : NeonI_compare_aliases<"cmlt", ".4s", CMGTvvv_4S, VPR128>;
702 def CMLTvvv_2D : NeonI_compare_aliases<"cmlt", ".2d", CMGTvvv_2D, VPR128>;
705 def neon_uimm0_asmoperand : AsmOperandClass
708 let PredicateMethod = "isUImm<0>";
709 let RenderMethod = "addImmOperands";
712 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
713 let ParserMatchClass = neon_uimm0_asmoperand;
714 let PrintMethod = "printNeonUImm0Operand";
718 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
720 def _8B : NeonI_2VMisc<0b0, u, 0b00, opcode,
721 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
722 asmop # "\t$Rd.8b, $Rn.8b, $Imm",
723 [(set (v8i8 VPR64:$Rd),
724 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
727 def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
728 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
729 asmop # "\t$Rd.16b, $Rn.16b, $Imm",
730 [(set (v16i8 VPR128:$Rd),
731 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
734 def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
735 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
736 asmop # "\t$Rd.4h, $Rn.4h, $Imm",
737 [(set (v4i16 VPR64:$Rd),
738 (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
741 def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
742 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
743 asmop # "\t$Rd.8h, $Rn.8h, $Imm",
744 [(set (v8i16 VPR128:$Rd),
745 (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
748 def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
749 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
750 asmop # "\t$Rd.2s, $Rn.2s, $Imm",
751 [(set (v2i32 VPR64:$Rd),
752 (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
755 def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
756 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
757 asmop # "\t$Rd.4s, $Rn.4s, $Imm",
758 [(set (v4i32 VPR128:$Rd),
759 (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
762 def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
763 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
764 asmop # "\t$Rd.2d, $Rn.2d, $Imm",
765 [(set (v2i64 VPR128:$Rd),
766 (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
770 // Vector Compare Mask Equal to Zero (Integer)
771 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
773 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
774 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
776 // Vector Compare Mask Greater Than Zero (Signed Integer)
777 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
779 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
780 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
782 // Vector Compare Mask Less Than Zero (Signed Integer)
783 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
785 // Vector Comparisons (Floating Point)
787 // Vector Compare Mask Equal (Floating Point)
788 let isCommutable =1 in {
789 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
790 Neon_cmeq, Neon_cmeq,
791 v2i32, v4i32, v2i64, 0>;
794 // Vector Compare Mask Greater Than Or Equal (Floating Point)
795 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
796 Neon_cmge, Neon_cmge,
797 v2i32, v4i32, v2i64, 0>;
799 // Vector Compare Mask Greater Than (Floating Point)
800 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
801 Neon_cmgt, Neon_cmgt,
802 v2i32, v4i32, v2i64, 0>;
804 // Vector Compare Mask Less Than Or Equal (Floating Point)
805 // FCMLE is alias for FCMGE with operands reversed.
806 def FCMLEvvv_2S : NeonI_compare_aliases<"fcmle", ".2s", FCMGEvvv_2S, VPR64>;
807 def FCMLEvvv_4S : NeonI_compare_aliases<"fcmle", ".4s", FCMGEvvv_4S, VPR128>;
808 def FCMLEvvv_2D : NeonI_compare_aliases<"fcmle", ".2d", FCMGEvvv_2D, VPR128>;
810 // Vector Compare Mask Less Than (Floating Point)
811 // FCMLT is alias for FCMGT with operands reversed.
812 def FCMLTvvv_2S : NeonI_compare_aliases<"fcmlt", ".2s", FCMGTvvv_2S, VPR64>;
813 def FCMLTvvv_4S : NeonI_compare_aliases<"fcmlt", ".4s", FCMGTvvv_4S, VPR128>;
814 def FCMLTvvv_2D : NeonI_compare_aliases<"fcmlt", ".2d", FCMGTvvv_2D, VPR128>;
817 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
818 string asmop, CondCode CC>
820 def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
821 (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
822 asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
823 [(set (v2i32 VPR64:$Rd),
824 (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpz32:$FPImm), CC)))],
827 def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
828 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
829 asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
830 [(set (v4i32 VPR128:$Rd),
831 (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
834 def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
835 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
836 asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
837 [(set (v2i64 VPR128:$Rd),
838 (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
842 // Vector Compare Mask Equal to Zero (Floating Point)
843 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
845 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
846 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
848 // Vector Compare Mask Greater Than Zero (Floating Point)
849 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
851 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
852 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
854 // Vector Compare Mask Less Than Zero (Floating Point)
855 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
857 // Vector Absolute Comparisons (Floating Point)
859 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
860 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
861 int_arm_neon_vacged, int_arm_neon_vacgeq,
862 int_aarch64_neon_vacgeq,
863 v2i32, v4i32, v2i64, 0>;
865 // Vector Absolute Compare Mask Greater Than (Floating Point)
866 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
867 int_arm_neon_vacgtd, int_arm_neon_vacgtq,
868 int_aarch64_neon_vacgtq,
869 v2i32, v4i32, v2i64, 0>;
871 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
872 // FACLE is alias for FACGE with operands reversed.
873 def FACLEvvv_2S : NeonI_compare_aliases<"facle", ".2s", FACGEvvv_2S, VPR64>;
874 def FACLEvvv_4S : NeonI_compare_aliases<"facle", ".4s", FACGEvvv_4S, VPR128>;
875 def FACLEvvv_2D : NeonI_compare_aliases<"facle", ".2d", FACGEvvv_2D, VPR128>;
877 // Vector Absolute Compare Mask Less Than (Floating Point)
878 // FACLT is alias for FACGT with operands reversed.
879 def FACLTvvv_2S : NeonI_compare_aliases<"faclt", ".2s", FACGTvvv_2S, VPR64>;
880 def FACLTvvv_4S : NeonI_compare_aliases<"faclt", ".4s", FACGTvvv_4S, VPR128>;
881 def FACLTvvv_2D : NeonI_compare_aliases<"faclt", ".2d", FACGTvvv_2D, VPR128>;
883 // Vector halving add (Integer Signed, Unsigned)
884 defm SHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
885 int_arm_neon_vhadds, 1>;
886 defm UHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
887 int_arm_neon_vhaddu, 1>;
889 // Vector halving sub (Integer Signed, Unsigned)
890 defm SHSUBvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
891 int_arm_neon_vhsubs, 0>;
892 defm UHSUBvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
893 int_arm_neon_vhsubu, 0>;
895 // Vector rouding halving add (Integer Signed, Unsigned)
896 defm SRHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
897 int_arm_neon_vrhadds, 1>;
898 defm URHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
899 int_arm_neon_vrhaddu, 1>;
901 // Vector Saturating add (Integer Signed, Unsigned)
902 defm SQADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
903 int_arm_neon_vqadds, 1>;
904 defm UQADDvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
905 int_arm_neon_vqaddu, 1>;
907 // Vector Saturating sub (Integer Signed, Unsigned)
908 defm SQSUBvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
909 int_arm_neon_vqsubs, 1>;
910 defm UQSUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
911 int_arm_neon_vqsubu, 1>;
913 // Vector Shift Left (Signed and Unsigned Integer)
914 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
915 int_arm_neon_vshifts, 1>;
916 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
917 int_arm_neon_vshiftu, 1>;
919 // Vector Saturating Shift Left (Signed and Unsigned Integer)
920 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
921 int_arm_neon_vqshifts, 1>;
922 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
923 int_arm_neon_vqshiftu, 1>;
925 // Vector Rouding Shift Left (Signed and Unsigned Integer)
926 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
927 int_arm_neon_vrshifts, 1>;
928 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
929 int_arm_neon_vrshiftu, 1>;
931 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
932 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
933 int_arm_neon_vqrshifts, 1>;
934 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
935 int_arm_neon_vqrshiftu, 1>;
937 // Vector Maximum (Signed and Unsigned Integer)
938 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
939 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
941 // Vector Minimum (Signed and Unsigned Integer)
942 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
943 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
945 // Vector Maximum (Floating Point)
946 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
947 int_arm_neon_vmaxs, int_arm_neon_vmaxs,
948 int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
950 // Vector Minimum (Floating Point)
951 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
952 int_arm_neon_vmins, int_arm_neon_vmins,
953 int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
955 // Vector maxNum (Floating Point) - prefer a number over a quiet NaN)
956 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
957 int_aarch64_neon_vmaxnm,
958 int_aarch64_neon_vmaxnm,
959 int_aarch64_neon_vmaxnm,
960 v2f32, v4f32, v2f64, 1>;
962 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
963 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
964 int_aarch64_neon_vminnm,
965 int_aarch64_neon_vminnm,
966 int_aarch64_neon_vminnm,
967 v2f32, v4f32, v2f64, 1>;
969 // Vector Maximum Pairwise (Signed and Unsigned Integer)
970 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
971 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
973 // Vector Minimum Pairwise (Signed and Unsigned Integer)
974 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
975 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
977 // Vector Maximum Pairwise (Floating Point)
978 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
979 int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
980 int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
982 // Vector Minimum Pairwise (Floating Point)
983 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
984 int_arm_neon_vpmins, int_arm_neon_vpmins,
985 int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
987 // Vector maxNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
988 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
989 int_aarch64_neon_vpmaxnm,
990 int_aarch64_neon_vpmaxnm,
991 int_aarch64_neon_vpmaxnm,
992 v2f32, v4f32, v2f64, 1>;
994 // Vector minNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
995 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
996 int_aarch64_neon_vpminnm,
997 int_aarch64_neon_vpminnm,
998 int_aarch64_neon_vpminnm,
999 v2f32, v4f32, v2f64, 1>;
1001 // Vector Addition Pairwise (Integer)
1002 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
1004 // Vector Addition Pairwise (Floating Point)
1005 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
1009 v2f32, v4f32, v2f64, 1>;
1011 // Vector Saturating Doubling Multiply High
1012 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
1013 int_arm_neon_vqdmulh, 1>;
1015 // Vector Saturating Rouding Doubling Multiply High
1016 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
1017 int_arm_neon_vqrdmulh, 1>;
1019 // Vector Multiply Extended (Floating Point)
1020 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
1021 int_aarch64_neon_vmulx,
1022 int_aarch64_neon_vmulx,
1023 int_aarch64_neon_vmulx,
1024 v2f32, v4f32, v2f64, 1>;
1026 // Patterns to match llvm.aarch64.* intrinsic for
1027 // ADDP, SMINP, UMINP, SMAXP, UMAXP having i32 as output
1028 class Neon_VectorPair_v2i32_pattern<SDPatternOperator opnode, Instruction INST>
1029 : Pat<(v1i32 (opnode (v2i32 VPR64:$Rn))),
1031 (v2i32 (INST (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rn))),
1034 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_sminv, SMINPvvv_2S>;
1035 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_uminv, UMINPvvv_2S>;
1036 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_smaxv, SMAXPvvv_2S>;
1037 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_umaxv, UMAXPvvv_2S>;
1038 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_vaddv, ADDP_2S>;
1040 // Vector Immediate Instructions
1042 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
1044 def _asmoperand : AsmOperandClass
1046 let Name = "NeonMovImmShift" # PREFIX;
1047 let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
1048 let PredicateMethod = "isNeonMovImmShift" # PREFIX;
1052 // Definition of vector immediates shift operands
1054 // The selectable use-cases extract the shift operation
1055 // information from the OpCmode fields encoded in the immediate.
1056 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
1057 uint64_t OpCmode = N->getZExtValue();
1059 unsigned ShiftOnesIn;
1061 A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1062 if (!HasShift) return SDValue();
1063 return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1066 // Vector immediates shift operands which accept LSL and MSL
1067 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1068 // or 0, 8 (LSLH) or 8, 16 (MSL).
1069 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1070 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1071 // LSLH restricts shift amount to 0, 8 out of 0, 8, 16, 24
1072 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1074 multiclass neon_mov_imm_shift_operands<string PREFIX,
1075 string HALF, string ISHALF, code pred>
1077 def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1080 "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1082 "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1083 let ParserMatchClass =
1084 !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1088 defm neon_mov_imm_LSL : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1090 unsigned ShiftOnesIn;
1092 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1093 return (HasShift && !ShiftOnesIn);
1096 defm neon_mov_imm_MSL : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1098 unsigned ShiftOnesIn;
1100 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1101 return (HasShift && ShiftOnesIn);
1104 defm neon_mov_imm_LSLH : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1106 unsigned ShiftOnesIn;
1108 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1109 return (HasShift && !ShiftOnesIn);
1112 def neon_uimm1_asmoperand : AsmOperandClass
1115 let PredicateMethod = "isUImm<1>";
1116 let RenderMethod = "addImmOperands";
1119 def neon_uimm2_asmoperand : AsmOperandClass
1122 let PredicateMethod = "isUImm<2>";
1123 let RenderMethod = "addImmOperands";
1126 def neon_uimm8_asmoperand : AsmOperandClass
1129 let PredicateMethod = "isUImm<8>";
1130 let RenderMethod = "addImmOperands";
1133 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1134 let ParserMatchClass = neon_uimm8_asmoperand;
1135 let PrintMethod = "printUImmHexOperand";
1138 def neon_uimm64_mask_asmoperand : AsmOperandClass
1140 let Name = "NeonUImm64Mask";
1141 let PredicateMethod = "isNeonUImm64Mask";
1142 let RenderMethod = "addNeonUImm64MaskOperands";
1145 // MCOperand for 64-bit bytemask with each byte having only the
1146 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1147 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1148 let ParserMatchClass = neon_uimm64_mask_asmoperand;
1149 let PrintMethod = "printNeonUImm64MaskOperand";
1152 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1153 SDPatternOperator opnode>
1155 // shift zeros, per word
1156 def _2S : NeonI_1VModImm<0b0, op,
1158 (ins neon_uimm8:$Imm,
1159 neon_mov_imm_LSL_operand:$Simm),
1160 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1161 [(set (v2i32 VPR64:$Rd),
1162 (v2i32 (opnode (timm:$Imm),
1163 (neon_mov_imm_LSL_operand:$Simm))))],
1166 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1169 def _4S : NeonI_1VModImm<0b1, op,
1171 (ins neon_uimm8:$Imm,
1172 neon_mov_imm_LSL_operand:$Simm),
1173 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1174 [(set (v4i32 VPR128:$Rd),
1175 (v4i32 (opnode (timm:$Imm),
1176 (neon_mov_imm_LSL_operand:$Simm))))],
1179 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1182 // shift zeros, per halfword
1183 def _4H : NeonI_1VModImm<0b0, op,
1185 (ins neon_uimm8:$Imm,
1186 neon_mov_imm_LSLH_operand:$Simm),
1187 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1188 [(set (v4i16 VPR64:$Rd),
1189 (v4i16 (opnode (timm:$Imm),
1190 (neon_mov_imm_LSLH_operand:$Simm))))],
1193 let cmode = {0b1, 0b0, Simm, 0b0};
1196 def _8H : NeonI_1VModImm<0b1, op,
1198 (ins neon_uimm8:$Imm,
1199 neon_mov_imm_LSLH_operand:$Simm),
1200 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1201 [(set (v8i16 VPR128:$Rd),
1202 (v8i16 (opnode (timm:$Imm),
1203 (neon_mov_imm_LSLH_operand:$Simm))))],
1206 let cmode = {0b1, 0b0, Simm, 0b0};
1210 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1211 SDPatternOperator opnode,
1212 SDPatternOperator neonopnode>
1214 let Constraints = "$src = $Rd" in {
1215 // shift zeros, per word
1216 def _2S : NeonI_1VModImm<0b0, op,
1218 (ins VPR64:$src, neon_uimm8:$Imm,
1219 neon_mov_imm_LSL_operand:$Simm),
1220 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1221 [(set (v2i32 VPR64:$Rd),
1222 (v2i32 (opnode (v2i32 VPR64:$src),
1223 (v2i32 (neonopnode timm:$Imm,
1224 neon_mov_imm_LSL_operand:$Simm)))))],
1227 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1230 def _4S : NeonI_1VModImm<0b1, op,
1232 (ins VPR128:$src, neon_uimm8:$Imm,
1233 neon_mov_imm_LSL_operand:$Simm),
1234 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1235 [(set (v4i32 VPR128:$Rd),
1236 (v4i32 (opnode (v4i32 VPR128:$src),
1237 (v4i32 (neonopnode timm:$Imm,
1238 neon_mov_imm_LSL_operand:$Simm)))))],
1241 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1244 // shift zeros, per halfword
1245 def _4H : NeonI_1VModImm<0b0, op,
1247 (ins VPR64:$src, neon_uimm8:$Imm,
1248 neon_mov_imm_LSLH_operand:$Simm),
1249 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1250 [(set (v4i16 VPR64:$Rd),
1251 (v4i16 (opnode (v4i16 VPR64:$src),
1252 (v4i16 (neonopnode timm:$Imm,
1253 neon_mov_imm_LSL_operand:$Simm)))))],
1256 let cmode = {0b1, 0b0, Simm, 0b1};
1259 def _8H : NeonI_1VModImm<0b1, op,
1261 (ins VPR128:$src, neon_uimm8:$Imm,
1262 neon_mov_imm_LSLH_operand:$Simm),
1263 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1264 [(set (v8i16 VPR128:$Rd),
1265 (v8i16 (opnode (v8i16 VPR128:$src),
1266 (v8i16 (neonopnode timm:$Imm,
1267 neon_mov_imm_LSL_operand:$Simm)))))],
1270 let cmode = {0b1, 0b0, Simm, 0b1};
1275 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1276 SDPatternOperator opnode>
1278 // shift ones, per word
1279 def _2S : NeonI_1VModImm<0b0, op,
1281 (ins neon_uimm8:$Imm,
1282 neon_mov_imm_MSL_operand:$Simm),
1283 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1284 [(set (v2i32 VPR64:$Rd),
1285 (v2i32 (opnode (timm:$Imm),
1286 (neon_mov_imm_MSL_operand:$Simm))))],
1289 let cmode = {0b1, 0b1, 0b0, Simm};
1292 def _4S : NeonI_1VModImm<0b1, op,
1294 (ins neon_uimm8:$Imm,
1295 neon_mov_imm_MSL_operand:$Simm),
1296 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1297 [(set (v4i32 VPR128:$Rd),
1298 (v4i32 (opnode (timm:$Imm),
1299 (neon_mov_imm_MSL_operand:$Simm))))],
1302 let cmode = {0b1, 0b1, 0b0, Simm};
1306 // Vector Move Immediate Shifted
1307 let isReMaterializable = 1 in {
1308 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1311 // Vector Move Inverted Immediate Shifted
1312 let isReMaterializable = 1 in {
1313 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1316 // Vector Bitwise Bit Clear (AND NOT) - immediate
1317 let isReMaterializable = 1 in {
1318 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1322 // Vector Bitwise OR - immedidate
1324 let isReMaterializable = 1 in {
1325 defm ORRvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1329 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1330 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1331 // BIC immediate instructions selection requires additional patterns to
1332 // transform Neon_movi operands into BIC immediate operands
1334 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1335 uint64_t OpCmode = N->getZExtValue();
1337 unsigned ShiftOnesIn;
1338 (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1339 // LSLH restricts shift amount to 0, 8 which are encoded as 0 and 1
1340 // Transform encoded shift amount 0 to 1 and 1 to 0.
1341 return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1344 def neon_mov_imm_LSLH_transform_operand
1347 unsigned ShiftOnesIn;
1349 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1350 return (HasShift && !ShiftOnesIn); }],
1351 neon_mov_imm_LSLH_transform_XFORM>;
1353 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0xff, LSL 8)
1354 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0xff)
1355 def : Pat<(v4i16 (and VPR64:$src,
1356 (v4i16 (Neon_movi 255,
1357 neon_mov_imm_LSLH_transform_operand:$Simm)))),
1358 (BICvi_lsl_4H VPR64:$src, 255,
1359 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1361 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0xff, LSL 8)
1362 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0xff)
1363 def : Pat<(v8i16 (and VPR128:$src,
1364 (v8i16 (Neon_movi 255,
1365 neon_mov_imm_LSLH_transform_operand:$Simm)))),
1366 (BICvi_lsl_8H VPR128:$src, 255,
1367 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1369 def : Pat<(v8i8 (and VPR64:$src,
1370 (bitconvert(v4i16 (Neon_movi 255,
1371 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1372 (BICvi_lsl_4H VPR64:$src, 255,
1373 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1374 def : Pat<(v2i32 (and VPR64:$src,
1375 (bitconvert(v4i16 (Neon_movi 255,
1376 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1377 (BICvi_lsl_4H VPR64:$src, 255,
1378 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1379 def : Pat<(v1i64 (and VPR64:$src,
1380 (bitconvert(v4i16 (Neon_movi 255,
1381 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1382 (BICvi_lsl_4H VPR64:$src, 255,
1383 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1385 def : Pat<(v16i8 (and VPR128:$src,
1386 (bitconvert(v8i16 (Neon_movi 255,
1387 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1388 (BICvi_lsl_8H VPR128:$src, 255,
1389 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1390 def : Pat<(v4i32 (and VPR128:$src,
1391 (bitconvert(v8i16 (Neon_movi 255,
1392 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1393 (BICvi_lsl_8H VPR128:$src, 255,
1394 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1395 def : Pat<(v2i64 (and VPR128:$src,
1396 (bitconvert(v8i16 (Neon_movi 255,
1397 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1398 (BICvi_lsl_8H VPR128:$src, 255,
1399 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1401 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1402 SDPatternOperator neonopnode,
1406 Instruction INST4S> {
1407 def : Pat<(v8i8 (opnode VPR64:$src,
1408 (bitconvert(v4i16 (neonopnode timm:$Imm,
1409 neon_mov_imm_LSLH_operand:$Simm))))),
1410 (INST4H VPR64:$src, neon_uimm8:$Imm,
1411 neon_mov_imm_LSLH_operand:$Simm)>;
1412 def : Pat<(v2i32 (opnode VPR64:$src,
1413 (bitconvert(v4i16 (neonopnode timm:$Imm,
1414 neon_mov_imm_LSLH_operand:$Simm))))),
1415 (INST4H VPR64:$src, neon_uimm8:$Imm,
1416 neon_mov_imm_LSLH_operand:$Simm)>;
1417 def : Pat<(v1i64 (opnode VPR64:$src,
1418 (bitconvert(v4i16 (neonopnode timm:$Imm,
1419 neon_mov_imm_LSLH_operand:$Simm))))),
1420 (INST4H VPR64:$src, neon_uimm8:$Imm,
1421 neon_mov_imm_LSLH_operand:$Simm)>;
1423 def : Pat<(v16i8 (opnode VPR128:$src,
1424 (bitconvert(v8i16 (neonopnode timm:$Imm,
1425 neon_mov_imm_LSLH_operand:$Simm))))),
1426 (INST8H VPR128:$src, neon_uimm8:$Imm,
1427 neon_mov_imm_LSLH_operand:$Simm)>;
1428 def : Pat<(v4i32 (opnode VPR128:$src,
1429 (bitconvert(v8i16 (neonopnode timm:$Imm,
1430 neon_mov_imm_LSLH_operand:$Simm))))),
1431 (INST8H VPR128:$src, neon_uimm8:$Imm,
1432 neon_mov_imm_LSLH_operand:$Simm)>;
1433 def : Pat<(v2i64 (opnode VPR128:$src,
1434 (bitconvert(v8i16 (neonopnode timm:$Imm,
1435 neon_mov_imm_LSLH_operand:$Simm))))),
1436 (INST8H VPR128:$src, neon_uimm8:$Imm,
1437 neon_mov_imm_LSLH_operand:$Simm)>;
1439 def : Pat<(v8i8 (opnode VPR64:$src,
1440 (bitconvert(v2i32 (neonopnode timm:$Imm,
1441 neon_mov_imm_LSLH_operand:$Simm))))),
1442 (INST2S VPR64:$src, neon_uimm8:$Imm,
1443 neon_mov_imm_LSLH_operand:$Simm)>;
1444 def : Pat<(v4i16 (opnode VPR64:$src,
1445 (bitconvert(v2i32 (neonopnode timm:$Imm,
1446 neon_mov_imm_LSLH_operand:$Simm))))),
1447 (INST2S VPR64:$src, neon_uimm8:$Imm,
1448 neon_mov_imm_LSLH_operand:$Simm)>;
1449 def : Pat<(v1i64 (opnode VPR64:$src,
1450 (bitconvert(v2i32 (neonopnode timm:$Imm,
1451 neon_mov_imm_LSLH_operand:$Simm))))),
1452 (INST2S VPR64:$src, neon_uimm8:$Imm,
1453 neon_mov_imm_LSLH_operand:$Simm)>;
1455 def : Pat<(v16i8 (opnode VPR128:$src,
1456 (bitconvert(v4i32 (neonopnode timm:$Imm,
1457 neon_mov_imm_LSLH_operand:$Simm))))),
1458 (INST4S VPR128:$src, neon_uimm8:$Imm,
1459 neon_mov_imm_LSLH_operand:$Simm)>;
1460 def : Pat<(v8i16 (opnode VPR128:$src,
1461 (bitconvert(v4i32 (neonopnode timm:$Imm,
1462 neon_mov_imm_LSLH_operand:$Simm))))),
1463 (INST4S VPR128:$src, neon_uimm8:$Imm,
1464 neon_mov_imm_LSLH_operand:$Simm)>;
1465 def : Pat<(v2i64 (opnode VPR128:$src,
1466 (bitconvert(v4i32 (neonopnode timm:$Imm,
1467 neon_mov_imm_LSLH_operand:$Simm))))),
1468 (INST4S VPR128:$src, neon_uimm8:$Imm,
1469 neon_mov_imm_LSLH_operand:$Simm)>;
1472 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1473 defm : Neon_bitwiseVi_patterns<and, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H,
1474 BICvi_lsl_2S, BICvi_lsl_4S>;
1476 // Additional patterns for Vector Bitwise OR - immedidate
1477 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H,
1478 ORRvi_lsl_2S, ORRvi_lsl_4S>;
1481 // Vector Move Immediate Masked
1482 let isReMaterializable = 1 in {
1483 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1486 // Vector Move Inverted Immediate Masked
1487 let isReMaterializable = 1 in {
1488 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1491 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1492 Instruction inst, RegisterOperand VPRC>
1493 : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1494 (inst VPRC:$Rd, neon_uimm8:$Imm, 0), 0b0>;
1496 // Aliases for Vector Move Immediate Shifted
1497 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1498 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1499 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1500 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1502 // Aliases for Vector Move Inverted Immediate Shifted
1503 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1504 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1505 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1506 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1508 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1509 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1510 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1511 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1512 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1514 // Aliases for Vector Bitwise OR - immedidate
1515 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1516 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1517 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1518 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1520 // Vector Move Immediate - per byte
1521 let isReMaterializable = 1 in {
1522 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1523 (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1524 "movi\t$Rd.8b, $Imm",
1525 [(set (v8i8 VPR64:$Rd),
1526 (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1531 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1532 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1533 "movi\t$Rd.16b, $Imm",
1534 [(set (v16i8 VPR128:$Rd),
1535 (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1541 // Vector Move Immediate - bytemask, per double word
1542 let isReMaterializable = 1 in {
1543 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1544 (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1545 "movi\t $Rd.2d, $Imm",
1546 [(set (v2i64 VPR128:$Rd),
1547 (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1553 // Vector Move Immediate - bytemask, one doubleword
1555 let isReMaterializable = 1 in {
1556 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1557 (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1559 [(set (v1i64 FPR64:$Rd),
1560 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1566 // Vector Floating Point Move Immediate
1568 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1569 Operand immOpType, bit q, bit op>
1570 : NeonI_1VModImm<q, op,
1571 (outs VPRC:$Rd), (ins immOpType:$Imm),
1572 "fmov\t$Rd" # asmlane # ", $Imm",
1573 [(set (OpTy VPRC:$Rd),
1574 (OpTy (Neon_fmovi (timm:$Imm))))],
1579 let isReMaterializable = 1 in {
1580 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64, v2f32, fmov32_operand, 0b0, 0b0>;
1581 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1582 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1585 // Vector Shift (Immediate)
1586 // Immediate in [0, 63]
1587 def imm0_63 : Operand<i32> {
1588 let ParserMatchClass = uimm6_asmoperand;
1591 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1595 // 8 immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1596 // 16 immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1597 // 32 immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1598 // 64 immh:immb<6> = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1600 // The shift right immediate amount, in the range 1 to element bits, is computed
1601 // as Offset - UInt(immh:immb). The shift left immediate amount, in the range 0
1602 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1604 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1605 let Name = "ShrImm" # OFFSET;
1606 let RenderMethod = "addImmOperands";
1607 let DiagnosticType = "ShrImm" # OFFSET;
1610 class shr_imm<string OFFSET> : Operand<i32> {
1611 let EncoderMethod = "getShiftRightImm" # OFFSET;
1612 let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1613 let ParserMatchClass =
1614 !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1617 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1618 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1619 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1620 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1622 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1623 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1624 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1625 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1627 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1628 let Name = "ShlImm" # OFFSET;
1629 let RenderMethod = "addImmOperands";
1630 let DiagnosticType = "ShlImm" # OFFSET;
1633 class shl_imm<string OFFSET> : Operand<i32> {
1634 let EncoderMethod = "getShiftLeftImm" # OFFSET;
1635 let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1636 let ParserMatchClass =
1637 !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1640 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1641 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1642 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1643 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1645 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1646 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1647 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1648 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1650 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1651 RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1652 : NeonI_2VShiftImm<q, u, opcode,
1653 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1654 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1655 [(set (Ty VPRC:$Rd),
1656 (Ty (OpNode (Ty VPRC:$Rn),
1657 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1660 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1661 // 64-bit vector types.
1662 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1663 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1666 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1667 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1670 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1671 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1674 // 128-bit vector types.
1675 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1676 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1679 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1680 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1683 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1684 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1687 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1688 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
1692 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1693 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1695 let Inst{22-19} = 0b0001;
1698 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1700 let Inst{22-20} = 0b001;
1703 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1705 let Inst{22-21} = 0b01;
1708 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1710 let Inst{22-19} = 0b0001;
1713 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1715 let Inst{22-20} = 0b001;
1718 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1720 let Inst{22-21} = 0b01;
1723 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1730 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1733 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1734 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1736 def Neon_High16B : PatFrag<(ops node:$in),
1737 (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1738 def Neon_High8H : PatFrag<(ops node:$in),
1739 (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1740 def Neon_High4S : PatFrag<(ops node:$in),
1741 (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1742 def Neon_High2D : PatFrag<(ops node:$in),
1743 (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1744 def Neon_High4float : PatFrag<(ops node:$in),
1745 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1746 def Neon_High2double : PatFrag<(ops node:$in),
1747 (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1749 def Neon_Low16B : PatFrag<(ops node:$in),
1750 (v8i8 (extract_subvector (v16i8 node:$in),
1752 def Neon_Low8H : PatFrag<(ops node:$in),
1753 (v4i16 (extract_subvector (v8i16 node:$in),
1755 def Neon_Low4S : PatFrag<(ops node:$in),
1756 (v2i32 (extract_subvector (v4i32 node:$in),
1758 def Neon_Low2D : PatFrag<(ops node:$in),
1759 (v1i64 (extract_subvector (v2i64 node:$in),
1761 def Neon_Low4float : PatFrag<(ops node:$in),
1762 (v2f32 (extract_subvector (v4f32 node:$in),
1764 def Neon_Low2double : PatFrag<(ops node:$in),
1765 (v1f64 (extract_subvector (v2f64 node:$in),
1768 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1769 string SrcT, ValueType DestTy, ValueType SrcTy,
1770 Operand ImmTy, SDPatternOperator ExtOp>
1771 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1772 (ins VPR64:$Rn, ImmTy:$Imm),
1773 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1774 [(set (DestTy VPR128:$Rd),
1776 (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1777 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1780 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1781 string SrcT, ValueType DestTy, ValueType SrcTy,
1782 int StartIndex, Operand ImmTy,
1783 SDPatternOperator ExtOp, PatFrag getTop>
1784 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1785 (ins VPR128:$Rn, ImmTy:$Imm),
1786 asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1787 [(set (DestTy VPR128:$Rd),
1790 (SrcTy (getTop VPR128:$Rn)))),
1791 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1794 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1796 // 64-bit vector types.
1797 def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1799 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1802 def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1804 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1807 def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1809 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1812 // 128-bit vector types
1813 def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1814 8, shl_imm8, ExtOp, Neon_High16B> {
1815 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1818 def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1819 4, shl_imm16, ExtOp, Neon_High8H> {
1820 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1823 def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1824 2, shl_imm32, ExtOp, Neon_High4S> {
1825 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1828 // Use other patterns to match when the immediate is 0.
1829 def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1830 (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1832 def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1833 (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1835 def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1836 (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1838 def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1839 (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1841 def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1842 (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1844 def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1845 (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1849 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1850 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1852 class NeonI_ext_len_alias<string asmop, string lane, string laneOp,
1853 Instruction inst, RegisterOperand VPRC,
1854 RegisterOperand VPRCOp>
1855 : NeonInstAlias<asmop # "\t$Rd" # lane #", $Rn" # laneOp,
1856 (inst VPRC:$Rd, VPRCOp:$Rn, 0), 0b0>;
1858 // Signed integer lengthen (vector) is alias for SSHLL Vd, Vn, #0
1859 // Signed integer lengthen (vector, second part) is alias for SSHLL2 Vd, Vn, #0
1860 // FIXME: This is actually the preferred syntax but TableGen can't deal with
1861 // custom printing of aliases.
1862 def SXTLvv_8B : NeonI_ext_len_alias<"sxtl", ".8h", ".8b", SSHLLvvi_8B, VPR128, VPR64>;
1863 def SXTLvv_4H : NeonI_ext_len_alias<"sxtl", ".4s", ".4h", SSHLLvvi_4H, VPR128, VPR64>;
1864 def SXTLvv_2S : NeonI_ext_len_alias<"sxtl", ".2d", ".2s", SSHLLvvi_2S, VPR128, VPR64>;
1865 def SXTL2vv_16B : NeonI_ext_len_alias<"sxtl2", ".8h", ".16b", SSHLLvvi_16B, VPR128, VPR128>;
1866 def SXTL2vv_8H : NeonI_ext_len_alias<"sxtl2", ".4s", ".8h", SSHLLvvi_8H, VPR128, VPR128>;
1867 def SXTL2vv_4S : NeonI_ext_len_alias<"sxtl2", ".2d", ".4s", SSHLLvvi_4S, VPR128, VPR128>;
1869 // Unsigned integer lengthen (vector) is alias for USHLL Vd, Vn, #0
1870 // Unsigned integer lengthen (vector, second part) is alias for USHLL2 Vd, Vn, #0
1871 // FIXME: This is actually the preferred syntax but TableGen can't deal with
1872 // custom printing of aliases.
1873 def UXTLvv_8B : NeonI_ext_len_alias<"uxtl", ".8h", ".8b", USHLLvvi_8B, VPR128, VPR64>;
1874 def UXTLvv_4H : NeonI_ext_len_alias<"uxtl", ".4s", ".4h", USHLLvvi_4H, VPR128, VPR64>;
1875 def UXTLvv_2S : NeonI_ext_len_alias<"uxtl", ".2d", ".2s", USHLLvvi_2S, VPR128, VPR64>;
1876 def UXTL2vv_16B : NeonI_ext_len_alias<"uxtl2", ".8h", ".16b", USHLLvvi_16B, VPR128, VPR128>;
1877 def UXTL2vv_8H : NeonI_ext_len_alias<"uxtl2", ".4s", ".8h", USHLLvvi_8H, VPR128, VPR128>;
1878 def UXTL2vv_4S : NeonI_ext_len_alias<"uxtl2", ".2d", ".4s", USHLLvvi_4S, VPR128, VPR128>;
1880 // Rounding/Saturating shift
1881 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1882 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1883 SDPatternOperator OpNode>
1884 : NeonI_2VShiftImm<q, u, opcode,
1885 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1886 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1887 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1888 (i32 ImmTy:$Imm))))],
1891 // shift right (vector by immediate)
1892 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1893 SDPatternOperator OpNode> {
1894 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1896 let Inst{22-19} = 0b0001;
1899 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1901 let Inst{22-20} = 0b001;
1904 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1906 let Inst{22-21} = 0b01;
1909 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1911 let Inst{22-19} = 0b0001;
1914 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1916 let Inst{22-20} = 0b001;
1919 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1921 let Inst{22-21} = 0b01;
1924 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1930 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1931 SDPatternOperator OpNode> {
1932 // 64-bit vector types.
1933 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1935 let Inst{22-19} = 0b0001;
1938 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1940 let Inst{22-20} = 0b001;
1943 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1945 let Inst{22-21} = 0b01;
1948 // 128-bit vector types.
1949 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1951 let Inst{22-19} = 0b0001;
1954 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1956 let Inst{22-20} = 0b001;
1959 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1961 let Inst{22-21} = 0b01;
1964 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1970 // Rounding shift right
1971 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1972 int_aarch64_neon_vsrshr>;
1973 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1974 int_aarch64_neon_vurshr>;
1976 // Saturating shift left unsigned
1977 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1979 // Saturating shift left
1980 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1981 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1983 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1984 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1986 : NeonI_2VShiftImm<q, u, opcode,
1987 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1988 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1989 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1990 (Ty (OpNode (Ty VPRC:$Rn),
1991 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
1993 let Constraints = "$src = $Rd";
1996 // Shift Right accumulate
1997 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1998 def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2000 let Inst{22-19} = 0b0001;
2003 def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2005 let Inst{22-20} = 0b001;
2008 def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2010 let Inst{22-21} = 0b01;
2013 def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2015 let Inst{22-19} = 0b0001;
2018 def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2020 let Inst{22-20} = 0b001;
2023 def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2025 let Inst{22-21} = 0b01;
2028 def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2034 // Shift right and accumulate
2035 defm SSRAvvi : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
2036 defm USRAvvi : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
2038 // Rounding shift accumulate
2039 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
2040 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2041 SDPatternOperator OpNode>
2042 : NeonI_2VShiftImm<q, u, opcode,
2043 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2044 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2045 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
2046 (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
2048 let Constraints = "$src = $Rd";
2051 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
2052 SDPatternOperator OpNode> {
2053 def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2055 let Inst{22-19} = 0b0001;
2058 def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2060 let Inst{22-20} = 0b001;
2063 def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2065 let Inst{22-21} = 0b01;
2068 def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2070 let Inst{22-19} = 0b0001;
2073 def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2075 let Inst{22-20} = 0b001;
2078 def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2080 let Inst{22-21} = 0b01;
2083 def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2089 // Rounding shift right and accumulate
2090 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
2091 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
2093 // Shift insert by immediate
2094 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
2095 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2096 SDPatternOperator OpNode>
2097 : NeonI_2VShiftImm<q, u, opcode,
2098 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2099 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2100 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
2101 (i32 ImmTy:$Imm))))],
2103 let Constraints = "$src = $Rd";
2106 // shift left insert (vector by immediate)
2107 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
2108 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
2109 int_aarch64_neon_vsli> {
2110 let Inst{22-19} = 0b0001;
2113 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
2114 int_aarch64_neon_vsli> {
2115 let Inst{22-20} = 0b001;
2118 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
2119 int_aarch64_neon_vsli> {
2120 let Inst{22-21} = 0b01;
2123 // 128-bit vector types
2124 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
2125 int_aarch64_neon_vsli> {
2126 let Inst{22-19} = 0b0001;
2129 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
2130 int_aarch64_neon_vsli> {
2131 let Inst{22-20} = 0b001;
2134 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
2135 int_aarch64_neon_vsli> {
2136 let Inst{22-21} = 0b01;
2139 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
2140 int_aarch64_neon_vsli> {
2145 // shift right insert (vector by immediate)
2146 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
2147 // 64-bit vector types.
2148 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2149 int_aarch64_neon_vsri> {
2150 let Inst{22-19} = 0b0001;
2153 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2154 int_aarch64_neon_vsri> {
2155 let Inst{22-20} = 0b001;
2158 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2159 int_aarch64_neon_vsri> {
2160 let Inst{22-21} = 0b01;
2163 // 128-bit vector types
2164 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2165 int_aarch64_neon_vsri> {
2166 let Inst{22-19} = 0b0001;
2169 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2170 int_aarch64_neon_vsri> {
2171 let Inst{22-20} = 0b001;
2174 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2175 int_aarch64_neon_vsri> {
2176 let Inst{22-21} = 0b01;
2179 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2180 int_aarch64_neon_vsri> {
2185 // Shift left and insert
2186 defm SLIvvi : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2188 // Shift right and insert
2189 defm SRIvvi : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2191 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2192 string SrcT, Operand ImmTy>
2193 : NeonI_2VShiftImm<q, u, opcode,
2194 (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2195 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2198 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2199 string SrcT, Operand ImmTy>
2200 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2201 (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2202 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2204 let Constraints = "$src = $Rd";
2207 // left long shift by immediate
2208 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2209 def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2210 let Inst{22-19} = 0b0001;
2213 def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2214 let Inst{22-20} = 0b001;
2217 def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2218 let Inst{22-21} = 0b01;
2221 // Shift Narrow High
2222 def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2224 let Inst{22-19} = 0b0001;
2227 def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2229 let Inst{22-20} = 0b001;
2232 def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2234 let Inst{22-21} = 0b01;
2238 // Shift right narrow
2239 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2241 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2242 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2243 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2244 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2245 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2246 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2247 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2248 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2250 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2251 (v2i64 (concat_vectors (v1i64 node:$Rm),
2252 (v1i64 node:$Rn)))>;
2253 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2254 (v8i16 (concat_vectors (v4i16 node:$Rm),
2255 (v4i16 node:$Rn)))>;
2256 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2257 (v4i32 (concat_vectors (v2i32 node:$Rm),
2258 (v2i32 node:$Rn)))>;
2259 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2260 (v4f32 (concat_vectors (v2f32 node:$Rm),
2261 (v2f32 node:$Rn)))>;
2262 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2263 (v2f64 (concat_vectors (v1f64 node:$Rm),
2264 (v1f64 node:$Rn)))>;
2266 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2267 (v8i16 (srl (v8i16 node:$lhs),
2268 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2269 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2270 (v4i32 (srl (v4i32 node:$lhs),
2271 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2272 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2273 (v2i64 (srl (v2i64 node:$lhs),
2274 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2275 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2276 (v8i16 (sra (v8i16 node:$lhs),
2277 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2278 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2279 (v4i32 (sra (v4i32 node:$lhs),
2280 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2281 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2282 (v2i64 (sra (v2i64 node:$lhs),
2283 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2285 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2286 multiclass Neon_shiftNarrow_patterns<string shr> {
2287 def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2288 (i32 shr_imm8:$Imm)))),
2289 (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2290 def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2291 (i32 shr_imm16:$Imm)))),
2292 (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2293 def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2294 (i32 shr_imm32:$Imm)))),
2295 (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2297 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2298 (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2299 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2300 (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2301 VPR128:$Rn, imm:$Imm)>;
2302 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2303 (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2304 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2305 (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2306 VPR128:$Rn, imm:$Imm)>;
2307 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2308 (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2309 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2310 (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2311 VPR128:$Rn, imm:$Imm)>;
2314 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2315 def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2316 (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2317 def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2318 (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2319 def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2320 (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2322 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2323 (v1i64 (bitconvert (v8i8
2324 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2325 (!cast<Instruction>(prefix # "_16B")
2326 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2327 VPR128:$Rn, imm:$Imm)>;
2328 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2329 (v1i64 (bitconvert (v4i16
2330 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2331 (!cast<Instruction>(prefix # "_8H")
2332 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2333 VPR128:$Rn, imm:$Imm)>;
2334 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2335 (v1i64 (bitconvert (v2i32
2336 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2337 (!cast<Instruction>(prefix # "_4S")
2338 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2339 VPR128:$Rn, imm:$Imm)>;
2342 defm : Neon_shiftNarrow_patterns<"lshr">;
2343 defm : Neon_shiftNarrow_patterns<"ashr">;
2345 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2346 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2347 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2348 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2349 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2350 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2351 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2353 // Convert fix-point and float-pointing
2354 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2355 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2356 Operand ImmTy, SDPatternOperator IntOp>
2357 : NeonI_2VShiftImm<q, u, opcode,
2358 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2359 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2360 [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2361 (i32 ImmTy:$Imm))))],
2364 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2365 SDPatternOperator IntOp> {
2366 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2368 let Inst{22-21} = 0b01;
2371 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2373 let Inst{22-21} = 0b01;
2376 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2382 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2383 SDPatternOperator IntOp> {
2384 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2386 let Inst{22-21} = 0b01;
2389 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2391 let Inst{22-21} = 0b01;
2394 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2400 // Convert fixed-point to floating-point
2401 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2402 int_arm_neon_vcvtfxs2fp>;
2403 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2404 int_arm_neon_vcvtfxu2fp>;
2406 // Convert floating-point to fixed-point
2407 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2408 int_arm_neon_vcvtfp2fxs>;
2409 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2410 int_arm_neon_vcvtfp2fxu>;
2412 multiclass Neon_sshll2_0<SDNode ext>
2414 def _v8i8 : PatFrag<(ops node:$Rn),
2415 (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2416 def _v4i16 : PatFrag<(ops node:$Rn),
2417 (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2418 def _v2i32 : PatFrag<(ops node:$Rn),
2419 (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2422 defm NI_sext_high : Neon_sshll2_0<sext>;
2423 defm NI_zext_high : Neon_sshll2_0<zext>;
2426 //===----------------------------------------------------------------------===//
2427 // Multiclasses for NeonI_Across
2428 //===----------------------------------------------------------------------===//
2432 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2433 string asmop, SDPatternOperator opnode>
2435 def _1h8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2436 (outs FPR16:$Rd), (ins VPR64:$Rn),
2437 asmop # "\t$Rd, $Rn.8b",
2438 [(set (v1i16 FPR16:$Rd),
2439 (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2442 def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2443 (outs FPR16:$Rd), (ins VPR128:$Rn),
2444 asmop # "\t$Rd, $Rn.16b",
2445 [(set (v1i16 FPR16:$Rd),
2446 (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2449 def _1s4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2450 (outs FPR32:$Rd), (ins VPR64:$Rn),
2451 asmop # "\t$Rd, $Rn.4h",
2452 [(set (v1i32 FPR32:$Rd),
2453 (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2456 def _1s8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2457 (outs FPR32:$Rd), (ins VPR128:$Rn),
2458 asmop # "\t$Rd, $Rn.8h",
2459 [(set (v1i32 FPR32:$Rd),
2460 (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2463 // _1d2s doesn't exist!
2465 def _1d4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2466 (outs FPR64:$Rd), (ins VPR128:$Rn),
2467 asmop # "\t$Rd, $Rn.4s",
2468 [(set (v1i64 FPR64:$Rd),
2469 (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2473 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2474 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2478 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2479 string asmop, SDPatternOperator opnode>
2481 def _1b8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2482 (outs FPR8:$Rd), (ins VPR64:$Rn),
2483 asmop # "\t$Rd, $Rn.8b",
2484 [(set (v1i8 FPR8:$Rd),
2485 (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2488 def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2489 (outs FPR8:$Rd), (ins VPR128:$Rn),
2490 asmop # "\t$Rd, $Rn.16b",
2491 [(set (v1i8 FPR8:$Rd),
2492 (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2495 def _1h4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2496 (outs FPR16:$Rd), (ins VPR64:$Rn),
2497 asmop # "\t$Rd, $Rn.4h",
2498 [(set (v1i16 FPR16:$Rd),
2499 (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2502 def _1h8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2503 (outs FPR16:$Rd), (ins VPR128:$Rn),
2504 asmop # "\t$Rd, $Rn.8h",
2505 [(set (v1i16 FPR16:$Rd),
2506 (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2509 // _1s2s doesn't exist!
2511 def _1s4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2512 (outs FPR32:$Rd), (ins VPR128:$Rn),
2513 asmop # "\t$Rd, $Rn.4s",
2514 [(set (v1i32 FPR32:$Rd),
2515 (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2519 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2520 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2522 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2523 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2525 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2529 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2530 string asmop, SDPatternOperator opnode> {
2531 def _1s4s: NeonI_2VAcross<0b1, u, size, opcode,
2532 (outs FPR32:$Rd), (ins VPR128:$Rn),
2533 asmop # "\t$Rd, $Rn.4s",
2534 [(set (f32 FPR32:$Rd),
2535 (f32 (opnode (v4f32 VPR128:$Rn))))],
2539 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2540 int_aarch64_neon_vmaxnmv>;
2541 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2542 int_aarch64_neon_vminnmv>;
2544 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2545 int_aarch64_neon_vmaxv>;
2546 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2547 int_aarch64_neon_vminv>;
2549 // The followings are for instruction class (Perm)
2551 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2552 string asmop, RegisterOperand OpVPR, string OpS,
2553 SDPatternOperator opnode, ValueType Ty>
2554 : NeonI_Perm<q, size, opcode,
2555 (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2556 asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2557 [(set (Ty OpVPR:$Rd),
2558 (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2561 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2562 SDPatternOperator opnode> {
2563 def _8b : NeonI_Permute<0b0, 0b00, opcode, asmop,
2564 VPR64, "8b", opnode, v8i8>;
2565 def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2566 VPR128, "16b",opnode, v16i8>;
2567 def _4h : NeonI_Permute<0b0, 0b01, opcode, asmop,
2568 VPR64, "4h", opnode, v4i16>;
2569 def _8h : NeonI_Permute<0b1, 0b01, opcode, asmop,
2570 VPR128, "8h", opnode, v8i16>;
2571 def _2s : NeonI_Permute<0b0, 0b10, opcode, asmop,
2572 VPR64, "2s", opnode, v2i32>;
2573 def _4s : NeonI_Permute<0b1, 0b10, opcode, asmop,
2574 VPR128, "4s", opnode, v4i32>;
2575 def _2d : NeonI_Permute<0b1, 0b11, opcode, asmop,
2576 VPR128, "2d", opnode, v2i64>;
2579 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2580 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2581 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2582 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2583 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2584 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2586 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2587 def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2588 (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2590 def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2591 (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2593 def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2594 (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2597 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2598 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2599 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2600 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2601 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2602 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2604 // The followings are for instruction class (3V Diff)
2606 // normal long/long2 pattern
2607 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2608 string asmop, string ResS, string OpS,
2609 SDPatternOperator opnode, SDPatternOperator ext,
2610 RegisterOperand OpVPR,
2611 ValueType ResTy, ValueType OpTy>
2612 : NeonI_3VDiff<q, u, size, opcode,
2613 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2614 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2615 [(set (ResTy VPR128:$Rd),
2616 (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2617 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2620 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2621 string asmop, SDPatternOperator opnode,
2622 bit Commutable = 0> {
2623 let isCommutable = Commutable in {
2624 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2625 opnode, sext, VPR64, v8i16, v8i8>;
2626 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2627 opnode, sext, VPR64, v4i32, v4i16>;
2628 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2629 opnode, sext, VPR64, v2i64, v2i32>;
2633 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2634 SDPatternOperator opnode, bit Commutable = 0> {
2635 let isCommutable = Commutable in {
2636 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2637 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2638 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2639 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2640 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2641 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2645 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2646 SDPatternOperator opnode, bit Commutable = 0> {
2647 let isCommutable = Commutable in {
2648 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2649 opnode, zext, VPR64, v8i16, v8i8>;
2650 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2651 opnode, zext, VPR64, v4i32, v4i16>;
2652 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2653 opnode, zext, VPR64, v2i64, v2i32>;
2657 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2658 SDPatternOperator opnode, bit Commutable = 0> {
2659 let isCommutable = Commutable in {
2660 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2661 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2662 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2663 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2664 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2665 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2669 defm SADDLvvv : NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2670 defm UADDLvvv : NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2672 defm SADDL2vvv : NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2673 defm UADDL2vvv : NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2675 defm SSUBLvvv : NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2676 defm USUBLvvv : NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2678 defm SSUBL2vvv : NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2679 defm USUBL2vvv : NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2681 // normal wide/wide2 pattern
2682 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2683 string asmop, string ResS, string OpS,
2684 SDPatternOperator opnode, SDPatternOperator ext,
2685 RegisterOperand OpVPR,
2686 ValueType ResTy, ValueType OpTy>
2687 : NeonI_3VDiff<q, u, size, opcode,
2688 (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2689 asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2690 [(set (ResTy VPR128:$Rd),
2691 (ResTy (opnode (ResTy VPR128:$Rn),
2692 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2695 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2696 SDPatternOperator opnode> {
2697 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2698 opnode, sext, VPR64, v8i16, v8i8>;
2699 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2700 opnode, sext, VPR64, v4i32, v4i16>;
2701 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2702 opnode, sext, VPR64, v2i64, v2i32>;
2705 defm SADDWvvv : NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2706 defm SSUBWvvv : NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2708 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2709 SDPatternOperator opnode> {
2710 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2711 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2712 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2713 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2714 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2715 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2718 defm SADDW2vvv : NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2719 defm SSUBW2vvv : NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2721 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2722 SDPatternOperator opnode> {
2723 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2724 opnode, zext, VPR64, v8i16, v8i8>;
2725 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2726 opnode, zext, VPR64, v4i32, v4i16>;
2727 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2728 opnode, zext, VPR64, v2i64, v2i32>;
2731 defm UADDWvvv : NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2732 defm USUBWvvv : NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2734 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2735 SDPatternOperator opnode> {
2736 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2737 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2738 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2739 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2740 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2741 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2744 defm UADDW2vvv : NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2745 defm USUBW2vvv : NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2747 // Get the high half part of the vector element.
2748 multiclass NeonI_get_high {
2749 def _8h : PatFrag<(ops node:$Rn),
2750 (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2751 (v8i16 (Neon_vdup (i32 8)))))))>;
2752 def _4s : PatFrag<(ops node:$Rn),
2753 (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2754 (v4i32 (Neon_vdup (i32 16)))))))>;
2755 def _2d : PatFrag<(ops node:$Rn),
2756 (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2757 (v2i64 (Neon_vdup (i32 32)))))))>;
2760 defm NI_get_hi : NeonI_get_high;
2762 // pattern for addhn/subhn with 2 operands
2763 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2764 string asmop, string ResS, string OpS,
2765 SDPatternOperator opnode, SDPatternOperator get_hi,
2766 ValueType ResTy, ValueType OpTy>
2767 : NeonI_3VDiff<q, u, size, opcode,
2768 (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2769 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2770 [(set (ResTy VPR64:$Rd),
2772 (OpTy (opnode (OpTy VPR128:$Rn),
2773 (OpTy VPR128:$Rm))))))],
2776 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2777 SDPatternOperator opnode, bit Commutable = 0> {
2778 let isCommutable = Commutable in {
2779 def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2780 opnode, NI_get_hi_8h, v8i8, v8i16>;
2781 def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2782 opnode, NI_get_hi_4s, v4i16, v4i32>;
2783 def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2784 opnode, NI_get_hi_2d, v2i32, v2i64>;
2788 defm ADDHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2789 defm SUBHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2791 // pattern for operation with 2 operands
2792 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2793 string asmop, string ResS, string OpS,
2794 SDPatternOperator opnode,
2795 RegisterOperand ResVPR, RegisterOperand OpVPR,
2796 ValueType ResTy, ValueType OpTy>
2797 : NeonI_3VDiff<q, u, size, opcode,
2798 (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2799 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2800 [(set (ResTy ResVPR:$Rd),
2801 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2804 // normal narrow pattern
2805 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2806 SDPatternOperator opnode, bit Commutable = 0> {
2807 let isCommutable = Commutable in {
2808 def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2809 opnode, VPR64, VPR128, v8i8, v8i16>;
2810 def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2811 opnode, VPR64, VPR128, v4i16, v4i32>;
2812 def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2813 opnode, VPR64, VPR128, v2i32, v2i64>;
2817 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2818 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2820 // pattern for acle intrinsic with 3 operands
2821 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2822 string asmop, string ResS, string OpS>
2823 : NeonI_3VDiff<q, u, size, opcode,
2824 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2825 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2827 let Constraints = "$src = $Rd";
2828 let neverHasSideEffects = 1;
2831 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2832 def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2833 def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2834 def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2837 defm ADDHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2838 defm SUBHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2840 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2841 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2843 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2845 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2846 SDPatternOperator coreop>
2847 : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2848 (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2849 (SrcTy VPR128:$Rm)))))),
2850 (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2851 VPR128:$Rn, VPR128:$Rm)>;
2854 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8, v8i16,
2855 BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2856 def : NarrowHighHalfPat<ADDHN2vvv_8h4s, v4i16, v4i32,
2857 BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2858 def : NarrowHighHalfPat<ADDHN2vvv_4s2d, v2i32, v2i64,
2859 BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2862 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8, v8i16,
2863 BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2864 def : NarrowHighHalfPat<SUBHN2vvv_8h4s, v4i16, v4i32,
2865 BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2866 def : NarrowHighHalfPat<SUBHN2vvv_4s2d, v2i32, v2i64,
2867 BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2870 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vraddhn>;
2871 def : NarrowHighHalfPat<RADDHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vraddhn>;
2872 def : NarrowHighHalfPat<RADDHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vraddhn>;
2875 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vrsubhn>;
2876 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vrsubhn>;
2877 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vrsubhn>;
2879 // pattern that need to extend result
2880 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2881 string asmop, string ResS, string OpS,
2882 SDPatternOperator opnode,
2883 RegisterOperand OpVPR,
2884 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2885 : NeonI_3VDiff<q, u, size, opcode,
2886 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2887 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2888 [(set (ResTy VPR128:$Rd),
2889 (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2890 (OpTy OpVPR:$Rm))))))],
2893 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2894 SDPatternOperator opnode, bit Commutable = 0> {
2895 let isCommutable = Commutable in {
2896 def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2897 opnode, VPR64, v8i16, v8i8, v8i8>;
2898 def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2899 opnode, VPR64, v4i32, v4i16, v4i16>;
2900 def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2901 opnode, VPR64, v2i64, v2i32, v2i32>;
2905 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2906 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2908 multiclass NeonI_Op_High<SDPatternOperator op> {
2909 def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2910 (op (v8i8 (Neon_High16B node:$Rn)),
2911 (v8i8 (Neon_High16B node:$Rm)))>;
2912 def _8H : PatFrag<(ops node:$Rn, node:$Rm),
2913 (op (v4i16 (Neon_High8H node:$Rn)),
2914 (v4i16 (Neon_High8H node:$Rm)))>;
2915 def _4S : PatFrag<(ops node:$Rn, node:$Rm),
2916 (op (v2i32 (Neon_High4S node:$Rn)),
2917 (v2i32 (Neon_High4S node:$Rm)))>;
2920 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2921 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2922 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2923 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2924 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2925 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2927 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2928 bit Commutable = 0> {
2929 let isCommutable = Commutable in {
2930 def _8h8b : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2931 !cast<PatFrag>(opnode # "_16B"),
2932 VPR128, v8i16, v16i8, v8i8>;
2933 def _4s4h : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2934 !cast<PatFrag>(opnode # "_8H"),
2935 VPR128, v4i32, v8i16, v4i16>;
2936 def _2d2s : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2937 !cast<PatFrag>(opnode # "_4S"),
2938 VPR128, v2i64, v4i32, v2i32>;
2942 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2943 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2945 // For pattern that need two operators being chained.
2946 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2947 string asmop, string ResS, string OpS,
2948 SDPatternOperator opnode, SDPatternOperator subop,
2949 RegisterOperand OpVPR,
2950 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2951 : NeonI_3VDiff<q, u, size, opcode,
2952 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2953 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2954 [(set (ResTy VPR128:$Rd),
2956 (ResTy VPR128:$src),
2957 (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2958 (OpTy OpVPR:$Rm))))))))],
2960 let Constraints = "$src = $Rd";
2963 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2964 SDPatternOperator opnode, SDPatternOperator subop>{
2965 def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2966 opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2967 def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2968 opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2969 def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2970 opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2973 defm SABALvvv : NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2974 add, int_arm_neon_vabds>;
2975 defm UABALvvv : NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2976 add, int_arm_neon_vabdu>;
2978 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2979 SDPatternOperator opnode, string subop> {
2980 def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2981 opnode, !cast<PatFrag>(subop # "_16B"),
2982 VPR128, v8i16, v16i8, v8i8>;
2983 def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2984 opnode, !cast<PatFrag>(subop # "_8H"),
2985 VPR128, v4i32, v8i16, v4i16>;
2986 def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2987 opnode, !cast<PatFrag>(subop # "_4S"),
2988 VPR128, v2i64, v4i32, v2i32>;
2991 defm SABAL2vvv : NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2993 defm UABAL2vvv : NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2996 // Long pattern with 2 operands
2997 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
2998 SDPatternOperator opnode, bit Commutable = 0> {
2999 let isCommutable = Commutable in {
3000 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3001 opnode, VPR128, VPR64, v8i16, v8i8>;
3002 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3003 opnode, VPR128, VPR64, v4i32, v4i16>;
3004 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3005 opnode, VPR128, VPR64, v2i64, v2i32>;
3009 defm SMULLvvv : NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
3010 defm UMULLvvv : NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
3012 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
3013 string asmop, string ResS, string OpS,
3014 SDPatternOperator opnode,
3015 ValueType ResTy, ValueType OpTy>
3016 : NeonI_3VDiff<q, u, size, opcode,
3017 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3018 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3019 [(set (ResTy VPR128:$Rd),
3020 (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
3023 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
3024 string opnode, bit Commutable = 0> {
3025 let isCommutable = Commutable in {
3026 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3027 !cast<PatFrag>(opnode # "_16B"),
3029 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3030 !cast<PatFrag>(opnode # "_8H"),
3032 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3033 !cast<PatFrag>(opnode # "_4S"),
3038 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
3040 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
3043 // Long pattern with 3 operands
3044 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
3045 string asmop, string ResS, string OpS,
3046 SDPatternOperator opnode,
3047 ValueType ResTy, ValueType OpTy>
3048 : NeonI_3VDiff<q, u, size, opcode,
3049 (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
3050 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3051 [(set (ResTy VPR128:$Rd),
3053 (ResTy VPR128:$src),
3054 (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
3056 let Constraints = "$src = $Rd";
3059 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
3060 SDPatternOperator opnode> {
3061 def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3062 opnode, v8i16, v8i8>;
3063 def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3064 opnode, v4i32, v4i16>;
3065 def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3066 opnode, v2i64, v2i32>;
3069 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3071 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3073 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3075 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3077 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3079 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3081 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3083 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3085 defm SMLALvvv : NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
3086 defm UMLALvvv : NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
3088 defm SMLSLvvv : NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
3089 defm UMLSLvvv : NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
3091 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
3092 string asmop, string ResS, string OpS,
3093 SDPatternOperator subop, SDPatternOperator opnode,
3094 RegisterOperand OpVPR,
3095 ValueType ResTy, ValueType OpTy>
3096 : NeonI_3VDiff<q, u, size, opcode,
3097 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
3098 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3099 [(set (ResTy VPR128:$Rd),
3101 (ResTy VPR128:$src),
3102 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
3104 let Constraints = "$src = $Rd";
3107 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
3108 SDPatternOperator subop, string opnode> {
3109 def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3110 subop, !cast<PatFrag>(opnode # "_16B"),
3111 VPR128, v8i16, v16i8>;
3112 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3113 subop, !cast<PatFrag>(opnode # "_8H"),
3114 VPR128, v4i32, v8i16>;
3115 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3116 subop, !cast<PatFrag>(opnode # "_4S"),
3117 VPR128, v2i64, v4i32>;
3120 defm SMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
3121 add, "NI_smull_hi">;
3122 defm UMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
3123 add, "NI_umull_hi">;
3125 defm SMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
3126 sub, "NI_smull_hi">;
3127 defm UMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
3128 sub, "NI_umull_hi">;
3130 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
3131 SDPatternOperator opnode> {
3132 def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3133 opnode, int_arm_neon_vqdmull,
3134 VPR64, v4i32, v4i16>;
3135 def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3136 opnode, int_arm_neon_vqdmull,
3137 VPR64, v2i64, v2i32>;
3140 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
3141 int_arm_neon_vqadds>;
3142 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
3143 int_arm_neon_vqsubs>;
3145 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
3146 SDPatternOperator opnode, bit Commutable = 0> {
3147 let isCommutable = Commutable in {
3148 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3149 opnode, VPR128, VPR64, v4i32, v4i16>;
3150 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3151 opnode, VPR128, VPR64, v2i64, v2i32>;
3155 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3156 int_arm_neon_vqdmull, 1>;
3158 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3159 string opnode, bit Commutable = 0> {
3160 let isCommutable = Commutable in {
3161 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3162 !cast<PatFrag>(opnode # "_8H"),
3164 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3165 !cast<PatFrag>(opnode # "_4S"),
3170 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3173 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3174 SDPatternOperator opnode> {
3175 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3176 opnode, NI_qdmull_hi_8H,
3177 VPR128, v4i32, v8i16>;
3178 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3179 opnode, NI_qdmull_hi_4S,
3180 VPR128, v2i64, v4i32>;
3183 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3184 int_arm_neon_vqadds>;
3185 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3186 int_arm_neon_vqsubs>;
3188 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3189 SDPatternOperator opnode_8h8b,
3190 SDPatternOperator opnode_1q1d, bit Commutable = 0> {
3191 let isCommutable = Commutable in {
3192 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3193 opnode_8h8b, VPR128, VPR64, v8i16, v8i8>;
3195 def _1q1d : NeonI_3VD_2Op<0b0, u, 0b11, opcode, asmop, "1q", "1d",
3196 opnode_1q1d, VPR128, VPR64, v16i8, v1i64>;
3200 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp,
3201 int_aarch64_neon_vmull_p64, 1>;
3203 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3204 string opnode, bit Commutable = 0> {
3205 let isCommutable = Commutable in {
3206 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3207 !cast<PatFrag>(opnode # "_16B"),
3211 NeonI_3VDiff<0b1, u, 0b11, opcode,
3212 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3213 asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3214 [(set (v16i8 VPR128:$Rd),
3215 (v16i8 (int_aarch64_neon_vmull_p64
3216 (v1i64 (scalar_to_vector
3217 (i64 (vector_extract (v2i64 VPR128:$Rn), 1)))),
3218 (v1i64 (scalar_to_vector
3219 (i64 (vector_extract (v2i64 VPR128:$Rm), 1)))))))],
3224 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3227 // End of implementation for instruction class (3V Diff)
3229 // The followings are vector load/store multiple N-element structure
3230 // (class SIMD lselem).
3232 // ld1: load multiple 1-element structure to 1/2/3/4 registers.
3233 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3234 // The structure consists of a sequence of sets of N values.
3235 // The first element of the structure is placed in the first lane
3236 // of the first first vector, the second element in the first lane
3237 // of the second vector, and so on.
3238 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3239 // the three 64-bit vectors list {BA, DC, FE}.
3240 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3241 // 64-bit vectors list {DA, EB, FC}.
3242 // Store instructions store multiple structure to N registers like load.
3245 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3246 RegisterOperand VecList, string asmop>
3247 : NeonI_LdStMult<q, 1, opcode, size,
3248 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3249 asmop # "\t$Rt, [$Rn]",
3253 let neverHasSideEffects = 1;
3256 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3257 def _8B : NeonI_LDVList<0, opcode, 0b00,
3258 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3260 def _4H : NeonI_LDVList<0, opcode, 0b01,
3261 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3263 def _2S : NeonI_LDVList<0, opcode, 0b10,
3264 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3266 def _16B : NeonI_LDVList<1, opcode, 0b00,
3267 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3269 def _8H : NeonI_LDVList<1, opcode, 0b01,
3270 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3272 def _4S : NeonI_LDVList<1, opcode, 0b10,
3273 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3275 def _2D : NeonI_LDVList<1, opcode, 0b11,
3276 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3279 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3280 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3281 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3283 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3285 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3287 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3289 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3290 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3291 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3293 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3294 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3296 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3297 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3299 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3300 RegisterOperand VecList, string asmop>
3301 : NeonI_LdStMult<q, 0, opcode, size,
3302 (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3303 asmop # "\t$Rt, [$Rn]",
3307 let neverHasSideEffects = 1;
3310 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3311 def _8B : NeonI_STVList<0, opcode, 0b00,
3312 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3314 def _4H : NeonI_STVList<0, opcode, 0b01,
3315 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3317 def _2S : NeonI_STVList<0, opcode, 0b10,
3318 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3320 def _16B : NeonI_STVList<1, opcode, 0b00,
3321 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3323 def _8H : NeonI_STVList<1, opcode, 0b01,
3324 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3326 def _4S : NeonI_STVList<1, opcode, 0b10,
3327 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3329 def _2D : NeonI_STVList<1, opcode, 0b11,
3330 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3333 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3334 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3335 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3337 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3339 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3341 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3343 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3344 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3345 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3347 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3348 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3350 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3351 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3353 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3354 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3356 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3357 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3359 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3360 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3362 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3363 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3365 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3366 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3368 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3369 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3371 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3372 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3373 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3374 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3376 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3377 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3378 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3379 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3381 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3382 (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3383 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3384 (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3386 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3387 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3388 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3389 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3391 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3392 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3393 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3394 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3396 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3397 (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3398 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3399 (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3401 // Match load/store of v1i8/v1i16/v1i32 type to FPR8/FPR16/FPR32 load/store.
3402 // FIXME: for now we have v1i8, v1i16, v1i32 legal types, if they are illegal,
3403 // these patterns are not needed any more.
3404 def : Pat<(v1i8 (load GPR64xsp:$addr)), (LSFP8_LDR $addr, 0)>;
3405 def : Pat<(v1i16 (load GPR64xsp:$addr)), (LSFP16_LDR $addr, 0)>;
3406 def : Pat<(v1i32 (load GPR64xsp:$addr)), (LSFP32_LDR $addr, 0)>;
3408 def : Pat<(store (v1i8 FPR8:$value), GPR64xsp:$addr),
3409 (LSFP8_STR $value, $addr, 0)>;
3410 def : Pat<(store (v1i16 FPR16:$value), GPR64xsp:$addr),
3411 (LSFP16_STR $value, $addr, 0)>;
3412 def : Pat<(store (v1i32 FPR32:$value), GPR64xsp:$addr),
3413 (LSFP32_STR $value, $addr, 0)>;
3416 // End of vector load/store multiple N-element structure(class SIMD lselem)
3418 // The followings are post-index vector load/store multiple N-element
3419 // structure(class SIMD lselem-post)
3420 def exact1_asmoperand : AsmOperandClass {
3421 let Name = "Exact1";
3422 let PredicateMethod = "isExactImm<1>";
3423 let RenderMethod = "addImmOperands";
3425 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3426 let ParserMatchClass = exact1_asmoperand;
3429 def exact2_asmoperand : AsmOperandClass {
3430 let Name = "Exact2";
3431 let PredicateMethod = "isExactImm<2>";
3432 let RenderMethod = "addImmOperands";
3434 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3435 let ParserMatchClass = exact2_asmoperand;
3438 def exact3_asmoperand : AsmOperandClass {
3439 let Name = "Exact3";
3440 let PredicateMethod = "isExactImm<3>";
3441 let RenderMethod = "addImmOperands";
3443 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3444 let ParserMatchClass = exact3_asmoperand;
3447 def exact4_asmoperand : AsmOperandClass {
3448 let Name = "Exact4";
3449 let PredicateMethod = "isExactImm<4>";
3450 let RenderMethod = "addImmOperands";
3452 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3453 let ParserMatchClass = exact4_asmoperand;
3456 def exact6_asmoperand : AsmOperandClass {
3457 let Name = "Exact6";
3458 let PredicateMethod = "isExactImm<6>";
3459 let RenderMethod = "addImmOperands";
3461 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3462 let ParserMatchClass = exact6_asmoperand;
3465 def exact8_asmoperand : AsmOperandClass {
3466 let Name = "Exact8";
3467 let PredicateMethod = "isExactImm<8>";
3468 let RenderMethod = "addImmOperands";
3470 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3471 let ParserMatchClass = exact8_asmoperand;
3474 def exact12_asmoperand : AsmOperandClass {
3475 let Name = "Exact12";
3476 let PredicateMethod = "isExactImm<12>";
3477 let RenderMethod = "addImmOperands";
3479 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3480 let ParserMatchClass = exact12_asmoperand;
3483 def exact16_asmoperand : AsmOperandClass {
3484 let Name = "Exact16";
3485 let PredicateMethod = "isExactImm<16>";
3486 let RenderMethod = "addImmOperands";
3488 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3489 let ParserMatchClass = exact16_asmoperand;
3492 def exact24_asmoperand : AsmOperandClass {
3493 let Name = "Exact24";
3494 let PredicateMethod = "isExactImm<24>";
3495 let RenderMethod = "addImmOperands";
3497 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3498 let ParserMatchClass = exact24_asmoperand;
3501 def exact32_asmoperand : AsmOperandClass {
3502 let Name = "Exact32";
3503 let PredicateMethod = "isExactImm<32>";
3504 let RenderMethod = "addImmOperands";
3506 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3507 let ParserMatchClass = exact32_asmoperand;
3510 def exact48_asmoperand : AsmOperandClass {
3511 let Name = "Exact48";
3512 let PredicateMethod = "isExactImm<48>";
3513 let RenderMethod = "addImmOperands";
3515 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3516 let ParserMatchClass = exact48_asmoperand;
3519 def exact64_asmoperand : AsmOperandClass {
3520 let Name = "Exact64";
3521 let PredicateMethod = "isExactImm<64>";
3522 let RenderMethod = "addImmOperands";
3524 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3525 let ParserMatchClass = exact64_asmoperand;
3528 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3529 RegisterOperand VecList, Operand ImmTy,
3531 let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3532 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3533 def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3534 (outs VecList:$Rt, GPR64xsp:$wb),
3535 (ins GPR64xsp:$Rn, ImmTy:$amt),
3536 asmop # "\t$Rt, [$Rn], $amt",
3542 def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3543 (outs VecList:$Rt, GPR64xsp:$wb),
3544 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3545 asmop # "\t$Rt, [$Rn], $Rm",
3551 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3552 Operand ImmTy2, string asmop> {
3553 defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3554 !cast<RegisterOperand>(List # "8B_operand"),
3557 defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3558 !cast<RegisterOperand>(List # "4H_operand"),
3561 defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3562 !cast<RegisterOperand>(List # "2S_operand"),
3565 defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3566 !cast<RegisterOperand>(List # "16B_operand"),
3569 defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3570 !cast<RegisterOperand>(List # "8H_operand"),
3573 defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3574 !cast<RegisterOperand>(List # "4S_operand"),
3577 defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3578 !cast<RegisterOperand>(List # "2D_operand"),
3582 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3583 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3584 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3587 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3589 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3592 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3594 // Post-index load multiple 1-element structures from N consecutive registers
3596 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3598 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3599 uimm_exact16, "ld1">;
3601 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3603 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3604 uimm_exact24, "ld1">;
3606 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3608 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3609 uimm_exact32, "ld1">;
3611 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3612 RegisterOperand VecList, Operand ImmTy,
3614 let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3615 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3616 def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3617 (outs GPR64xsp:$wb),
3618 (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3619 asmop # "\t$Rt, [$Rn], $amt",
3625 def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3626 (outs GPR64xsp:$wb),
3627 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3628 asmop # "\t$Rt, [$Rn], $Rm",
3634 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3635 Operand ImmTy2, string asmop> {
3636 defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3637 !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3639 defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3640 !cast<RegisterOperand>(List # "4H_operand"),
3643 defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3644 !cast<RegisterOperand>(List # "2S_operand"),
3647 defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3648 !cast<RegisterOperand>(List # "16B_operand"),
3651 defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3652 !cast<RegisterOperand>(List # "8H_operand"),
3655 defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3656 !cast<RegisterOperand>(List # "4S_operand"),
3659 defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3660 !cast<RegisterOperand>(List # "2D_operand"),
3664 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3665 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3666 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3669 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3671 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3674 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3676 // Post-index load multiple 1-element structures from N consecutive registers
3678 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3680 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3681 uimm_exact16, "st1">;
3683 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3685 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3686 uimm_exact24, "st1">;
3688 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3690 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3691 uimm_exact32, "st1">;
3693 // End of post-index vector load/store multiple N-element structure
3694 // (class SIMD lselem-post)
3696 // The followings are vector load/store single N-element structure
3697 // (class SIMD lsone).
3698 def neon_uimm0_bare : Operand<i64>,
3699 ImmLeaf<i64, [{return Imm == 0;}]> {
3700 let ParserMatchClass = neon_uimm0_asmoperand;
3701 let PrintMethod = "printUImmBareOperand";
3704 def neon_uimm1_bare : Operand<i64>,
3705 ImmLeaf<i64, [{return Imm < 2;}]> {
3706 let ParserMatchClass = neon_uimm1_asmoperand;
3707 let PrintMethod = "printUImmBareOperand";
3710 def neon_uimm2_bare : Operand<i64>,
3711 ImmLeaf<i64, [{return Imm < 4;}]> {
3712 let ParserMatchClass = neon_uimm2_asmoperand;
3713 let PrintMethod = "printUImmBareOperand";
3716 def neon_uimm3_bare : Operand<i64>,
3717 ImmLeaf<i64, [{return Imm < 8;}]> {
3718 let ParserMatchClass = uimm3_asmoperand;
3719 let PrintMethod = "printUImmBareOperand";
3722 def neon_uimm4_bare : Operand<i64>,
3723 ImmLeaf<i64, [{return Imm < 16;}]> {
3724 let ParserMatchClass = uimm4_asmoperand;
3725 let PrintMethod = "printUImmBareOperand";
3728 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3729 RegisterOperand VecList, string asmop>
3730 : NeonI_LdOne_Dup<q, r, opcode, size,
3731 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3732 asmop # "\t$Rt, [$Rn]",
3736 let neverHasSideEffects = 1;
3739 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3740 def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3741 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3743 def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3744 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3746 def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3747 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3749 def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3750 !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3752 def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3753 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3755 def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3756 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3758 def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3759 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3761 def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3762 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3765 // Load single 1-element structure to all lanes of 1 register
3766 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3768 // Load single N-element structure to all lanes of N consecutive
3769 // registers (N = 2,3,4)
3770 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3771 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3772 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3775 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3777 : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3778 (VTy (INST GPR64xsp:$Rn))>;
3780 // Match all LD1R instructions
3781 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3783 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3785 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3787 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3789 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3790 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3792 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3793 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3795 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3796 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3798 class LD1R_pattern_v1 <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3800 : Pat<(VTy (scalar_to_vector (DTy (LoadOp GPR64xsp:$Rn)))),
3801 (VTy (INST GPR64xsp:$Rn))>;
3803 def : LD1R_pattern_v1<v1i64, i64, load, LD1R_1D>;
3804 def : LD1R_pattern_v1<v1f64, f64, load, LD1R_1D>;
3806 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3807 RegisterClass RegList> {
3808 defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3809 defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3810 defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3811 defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3814 // Special vector list operand of 128-bit vectors with bare layout.
3815 // i.e. only show ".b", ".h", ".s", ".d"
3816 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3817 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3818 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3819 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3821 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3822 Operand ImmOp, string asmop>
3823 : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3825 (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3826 asmop # "\t$Rt[$lane], [$Rn]",
3830 let neverHasSideEffects = 1;
3831 let hasExtraDefRegAllocReq = 1;
3832 let Constraints = "$src = $Rt";
3835 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3836 def _B : NeonI_LDN_Lane<r, 0b00, op0,
3837 !cast<RegisterOperand>(List # "B_operand"),
3838 neon_uimm4_bare, asmop> {
3839 let Inst{12-10} = lane{2-0};
3840 let Inst{30} = lane{3};
3843 def _H : NeonI_LDN_Lane<r, 0b01, op0,
3844 !cast<RegisterOperand>(List # "H_operand"),
3845 neon_uimm3_bare, asmop> {
3846 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3847 let Inst{30} = lane{2};
3850 def _S : NeonI_LDN_Lane<r, 0b10, op0,
3851 !cast<RegisterOperand>(List # "S_operand"),
3852 neon_uimm2_bare, asmop> {
3853 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3854 let Inst{30} = lane{1};
3857 def _D : NeonI_LDN_Lane<r, 0b10, op0,
3858 !cast<RegisterOperand>(List # "D_operand"),
3859 neon_uimm1_bare, asmop> {
3860 let Inst{12-10} = 0b001;
3861 let Inst{30} = lane{0};
3865 // Load single 1-element structure to one lane of 1 register.
3866 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3868 // Load single N-element structure to one lane of N consecutive registers
3870 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3871 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3872 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3874 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3875 Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3877 def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3878 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3879 (VTy (EXTRACT_SUBREG
3881 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3885 def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3886 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3887 (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3890 // Match all LD1LN instructions
3891 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3892 extloadi8, LD1LN_B>;
3894 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3895 extloadi16, LD1LN_H>;
3897 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3899 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3902 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3904 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3907 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3908 Operand ImmOp, string asmop>
3909 : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3910 (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3911 asmop # "\t$Rt[$lane], [$Rn]",
3915 let neverHasSideEffects = 1;
3916 let hasExtraDefRegAllocReq = 1;
3919 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3920 def _B : NeonI_STN_Lane<r, 0b00, op0,
3921 !cast<RegisterOperand>(List # "B_operand"),
3922 neon_uimm4_bare, asmop> {
3923 let Inst{12-10} = lane{2-0};
3924 let Inst{30} = lane{3};
3927 def _H : NeonI_STN_Lane<r, 0b01, op0,
3928 !cast<RegisterOperand>(List # "H_operand"),
3929 neon_uimm3_bare, asmop> {
3930 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3931 let Inst{30} = lane{2};
3934 def _S : NeonI_STN_Lane<r, 0b10, op0,
3935 !cast<RegisterOperand>(List # "S_operand"),
3936 neon_uimm2_bare, asmop> {
3937 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3938 let Inst{30} = lane{1};
3941 def _D : NeonI_STN_Lane<r, 0b10, op0,
3942 !cast<RegisterOperand>(List # "D_operand"),
3943 neon_uimm1_bare, asmop>{
3944 let Inst{12-10} = 0b001;
3945 let Inst{30} = lane{0};
3949 // Store single 1-element structure from one lane of 1 register.
3950 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3952 // Store single N-element structure from one lane of N consecutive registers
3954 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3955 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3956 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3958 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3959 Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3961 def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3964 (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3967 def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3969 (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3972 // Match all ST1LN instructions
3973 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3974 truncstorei8, ST1LN_B>;
3976 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3977 truncstorei16, ST1LN_H>;
3979 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3981 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3984 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3986 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3989 // End of vector load/store single N-element structure (class SIMD lsone).
3992 // The following are post-index load/store single N-element instructions
3993 // (class SIMD lsone-post)
3995 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3996 RegisterOperand VecList, Operand ImmTy,
3998 let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
3999 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4000 def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4001 (outs VecList:$Rt, GPR64xsp:$wb),
4002 (ins GPR64xsp:$Rn, ImmTy:$amt),
4003 asmop # "\t$Rt, [$Rn], $amt",
4009 def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4010 (outs VecList:$Rt, GPR64xsp:$wb),
4011 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
4012 asmop # "\t$Rt, [$Rn], $Rm",
4018 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
4019 Operand uimm_b, Operand uimm_h,
4020 Operand uimm_s, Operand uimm_d> {
4021 defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
4022 !cast<RegisterOperand>(List # "8B_operand"),
4025 defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
4026 !cast<RegisterOperand>(List # "4H_operand"),
4029 defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
4030 !cast<RegisterOperand>(List # "2S_operand"),
4033 defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
4034 !cast<RegisterOperand>(List # "1D_operand"),
4037 defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
4038 !cast<RegisterOperand>(List # "16B_operand"),
4041 defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
4042 !cast<RegisterOperand>(List # "8H_operand"),
4045 defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
4046 !cast<RegisterOperand>(List # "4S_operand"),
4049 defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
4050 !cast<RegisterOperand>(List # "2D_operand"),
4054 // Post-index load single 1-element structure to all lanes of 1 register
4055 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
4056 uimm_exact2, uimm_exact4, uimm_exact8>;
4058 // Post-index load single N-element structure to all lanes of N consecutive
4059 // registers (N = 2,3,4)
4060 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
4061 uimm_exact4, uimm_exact8, uimm_exact16>;
4062 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
4063 uimm_exact6, uimm_exact12, uimm_exact24>;
4064 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
4065 uimm_exact8, uimm_exact16, uimm_exact32>;
4067 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
4068 Constraints = "$Rn = $wb, $Rt = $src",
4069 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4070 class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4071 Operand ImmTy, Operand ImmOp, string asmop>
4072 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4073 (outs VList:$Rt, GPR64xsp:$wb),
4074 (ins GPR64xsp:$Rn, ImmTy:$amt,
4075 VList:$src, ImmOp:$lane),
4076 asmop # "\t$Rt[$lane], [$Rn], $amt",
4082 class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4083 Operand ImmTy, Operand ImmOp, string asmop>
4084 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4085 (outs VList:$Rt, GPR64xsp:$wb),
4086 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
4087 VList:$src, ImmOp:$lane),
4088 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4093 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4094 Operand uimm_b, Operand uimm_h,
4095 Operand uimm_s, Operand uimm_d> {
4096 def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
4097 !cast<RegisterOperand>(List # "B_operand"),
4098 uimm_b, neon_uimm4_bare, asmop> {
4099 let Inst{12-10} = lane{2-0};
4100 let Inst{30} = lane{3};
4103 def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
4104 !cast<RegisterOperand>(List # "B_operand"),
4105 uimm_b, neon_uimm4_bare, asmop> {
4106 let Inst{12-10} = lane{2-0};
4107 let Inst{30} = lane{3};
4110 def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
4111 !cast<RegisterOperand>(List # "H_operand"),
4112 uimm_h, neon_uimm3_bare, asmop> {
4113 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4114 let Inst{30} = lane{2};
4117 def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
4118 !cast<RegisterOperand>(List # "H_operand"),
4119 uimm_h, neon_uimm3_bare, asmop> {
4120 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4121 let Inst{30} = lane{2};
4124 def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4125 !cast<RegisterOperand>(List # "S_operand"),
4126 uimm_s, neon_uimm2_bare, asmop> {
4127 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4128 let Inst{30} = lane{1};
4131 def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
4132 !cast<RegisterOperand>(List # "S_operand"),
4133 uimm_s, neon_uimm2_bare, asmop> {
4134 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4135 let Inst{30} = lane{1};
4138 def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4139 !cast<RegisterOperand>(List # "D_operand"),
4140 uimm_d, neon_uimm1_bare, asmop> {
4141 let Inst{12-10} = 0b001;
4142 let Inst{30} = lane{0};
4145 def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
4146 !cast<RegisterOperand>(List # "D_operand"),
4147 uimm_d, neon_uimm1_bare, asmop> {
4148 let Inst{12-10} = 0b001;
4149 let Inst{30} = lane{0};
4153 // Post-index load single 1-element structure to one lane of 1 register.
4154 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
4155 uimm_exact2, uimm_exact4, uimm_exact8>;
4157 // Post-index load single N-element structure to one lane of N consecutive
4160 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
4161 uimm_exact4, uimm_exact8, uimm_exact16>;
4162 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
4163 uimm_exact6, uimm_exact12, uimm_exact24>;
4164 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
4165 uimm_exact8, uimm_exact16, uimm_exact32>;
4167 let mayStore = 1, neverHasSideEffects = 1,
4168 hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
4169 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4170 class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4171 Operand ImmTy, Operand ImmOp, string asmop>
4172 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4173 (outs GPR64xsp:$wb),
4174 (ins GPR64xsp:$Rn, ImmTy:$amt,
4175 VList:$Rt, ImmOp:$lane),
4176 asmop # "\t$Rt[$lane], [$Rn], $amt",
4182 class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4183 Operand ImmTy, Operand ImmOp, string asmop>
4184 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4185 (outs GPR64xsp:$wb),
4186 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4188 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4193 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4194 Operand uimm_b, Operand uimm_h,
4195 Operand uimm_s, Operand uimm_d> {
4196 def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4197 !cast<RegisterOperand>(List # "B_operand"),
4198 uimm_b, neon_uimm4_bare, asmop> {
4199 let Inst{12-10} = lane{2-0};
4200 let Inst{30} = lane{3};
4203 def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4204 !cast<RegisterOperand>(List # "B_operand"),
4205 uimm_b, neon_uimm4_bare, asmop> {
4206 let Inst{12-10} = lane{2-0};
4207 let Inst{30} = lane{3};
4210 def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4211 !cast<RegisterOperand>(List # "H_operand"),
4212 uimm_h, neon_uimm3_bare, asmop> {
4213 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4214 let Inst{30} = lane{2};
4217 def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4218 !cast<RegisterOperand>(List # "H_operand"),
4219 uimm_h, neon_uimm3_bare, asmop> {
4220 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4221 let Inst{30} = lane{2};
4224 def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4225 !cast<RegisterOperand>(List # "S_operand"),
4226 uimm_s, neon_uimm2_bare, asmop> {
4227 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4228 let Inst{30} = lane{1};
4231 def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4232 !cast<RegisterOperand>(List # "S_operand"),
4233 uimm_s, neon_uimm2_bare, asmop> {
4234 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4235 let Inst{30} = lane{1};
4238 def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4239 !cast<RegisterOperand>(List # "D_operand"),
4240 uimm_d, neon_uimm1_bare, asmop> {
4241 let Inst{12-10} = 0b001;
4242 let Inst{30} = lane{0};
4245 def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4246 !cast<RegisterOperand>(List # "D_operand"),
4247 uimm_d, neon_uimm1_bare, asmop> {
4248 let Inst{12-10} = 0b001;
4249 let Inst{30} = lane{0};
4253 // Post-index store single 1-element structure from one lane of 1 register.
4254 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4255 uimm_exact2, uimm_exact4, uimm_exact8>;
4257 // Post-index store single N-element structure from one lane of N consecutive
4258 // registers (N = 2,3,4)
4259 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4260 uimm_exact4, uimm_exact8, uimm_exact16>;
4261 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4262 uimm_exact6, uimm_exact12, uimm_exact24>;
4263 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4264 uimm_exact8, uimm_exact16, uimm_exact32>;
4266 // End of post-index load/store single N-element instructions
4267 // (class SIMD lsone-post)
4269 // Neon Scalar instructions implementation
4270 // Scalar Three Same
4272 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4274 : NeonI_Scalar3Same<u, size, opcode,
4275 (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4276 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4280 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4281 : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4283 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4284 bit Commutable = 0> {
4285 let isCommutable = Commutable in {
4286 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4287 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4291 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4292 string asmop, bit Commutable = 0> {
4293 let isCommutable = Commutable in {
4294 def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4295 def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4299 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4300 string asmop, bit Commutable = 0> {
4301 let isCommutable = Commutable in {
4302 def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4303 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4304 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4305 def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4309 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4310 Instruction INSTD> {
4311 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4312 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4315 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4320 : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4321 def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4322 (INSTB FPR8:$Rn, FPR8:$Rm)>;
4323 def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4324 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4325 def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4326 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4329 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4331 Instruction INSTS> {
4332 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4333 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4334 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4335 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4338 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4339 ValueType SResTy, ValueType STy,
4340 Instruction INSTS, ValueType DResTy,
4341 ValueType DTy, Instruction INSTD> {
4342 def : Pat<(SResTy (opnode (STy FPR32:$Rn), (STy FPR32:$Rm))),
4343 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4344 def : Pat<(DResTy (opnode (DTy FPR64:$Rn), (DTy FPR64:$Rm))),
4345 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4348 class Neon_Scalar3Same_cmp_V1_D_size_patterns<CondCode CC,
4350 : Pat<(v1i64 (Neon_cmp (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm), CC)),
4351 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4353 // Scalar Three Different
4355 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4356 RegisterClass FPRCD, RegisterClass FPRCS>
4357 : NeonI_Scalar3Diff<u, size, opcode,
4358 (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4359 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4363 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4364 def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4365 def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4368 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4369 let Constraints = "$Src = $Rd" in {
4370 def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4371 (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4372 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4375 def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4376 (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4377 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4383 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4385 Instruction INSTS> {
4386 def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4387 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4388 def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4389 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4392 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4394 Instruction INSTS> {
4395 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4396 (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4397 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4398 (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4401 // Scalar Two Registers Miscellaneous
4403 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4404 RegisterClass FPRCD, RegisterClass FPRCS>
4405 : NeonI_Scalar2SameMisc<u, size, opcode,
4406 (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4407 !strconcat(asmop, "\t$Rd, $Rn"),
4411 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4413 def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4415 def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4419 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4420 def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4423 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4424 : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4425 def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4426 def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4427 def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4430 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4431 : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4433 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4435 def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4436 def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4437 def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4440 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4441 string asmop, RegisterClass FPRC>
4442 : NeonI_Scalar2SameMisc<u, size, opcode,
4443 (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4444 !strconcat(asmop, "\t$Rd, $Rn"),
4448 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4451 let Constraints = "$Src = $Rd" in {
4452 def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4453 def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4454 def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4455 def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4459 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4461 : Pat<(f32 (opnode (f64 FPR64:$Rn))),
4464 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4466 Instruction INSTD> {
4467 def : Pat<(v1i32 (opnode (f32 FPR32:$Rn))),
4469 def : Pat<(v1i64 (opnode (f64 FPR64:$Rn))),
4473 class Neon_Scalar2SameMisc_vcvt_D_size_patterns<SDPatternOperator opnode,
4475 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4478 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator opnode,
4480 Instruction INSTD> {
4481 def : Pat<(f32 (opnode (v1i32 FPR32:$Rn))),
4483 def : Pat<(f64 (opnode (v1i64 FPR64:$Rn))),
4487 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4489 Instruction INSTD> {
4490 def : Pat<(f32 (opnode (f32 FPR32:$Rn))),
4492 def : Pat<(f64 (opnode (f64 FPR64:$Rn))),
4496 class Neon_Scalar2SameMisc_V1_D_size_patterns<SDPatternOperator opnode,
4498 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4501 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4502 : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4503 (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4504 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4508 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4510 def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4511 (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4512 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4515 def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4516 (outs FPR64:$Rd), (ins FPR64:$Rn, fpz32:$FPImm),
4517 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4522 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4524 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4525 (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4526 (INSTD FPR64:$Rn, 0)>;
4528 class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
4530 : Pat<(v1i64 (Neon_cmpz (v1i64 FPR64:$Rn),
4531 (i32 neon_uimm0:$Imm), CC)),
4532 (INSTD FPR64:$Rn, neon_uimm0:$Imm)>;
4534 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4537 Instruction INSTD> {
4538 def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 fpz32:$FPImm))),
4539 (INSTS FPR32:$Rn, fpz32:$FPImm)>;
4540 def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f32 fpz32:$FPImm))),
4541 (INSTD FPR64:$Rn, fpz32:$FPImm)>;
4542 def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpz32:$FPImm), CC)),
4543 (INSTD FPR64:$Rn, fpz32:$FPImm)>;
4546 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4547 Instruction INSTD> {
4548 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4552 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4557 : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4558 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4560 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4562 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4566 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4567 SDPatternOperator opnode,
4570 Instruction INSTD> {
4571 def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4573 def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4575 def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4580 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4581 SDPatternOperator opnode,
4585 Instruction INSTD> {
4586 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4587 (INSTB FPR8:$Src, FPR8:$Rn)>;
4588 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4589 (INSTH FPR16:$Src, FPR16:$Rn)>;
4590 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4591 (INSTS FPR32:$Src, FPR32:$Rn)>;
4592 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4593 (INSTD FPR64:$Src, FPR64:$Rn)>;
4596 // Scalar Shift By Immediate
4598 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4599 RegisterClass FPRC, Operand ImmTy>
4600 : NeonI_ScalarShiftImm<u, opcode,
4601 (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4602 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4605 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4607 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4609 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4610 let Inst{21-16} = Imm;
4614 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4616 : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4617 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4619 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4620 let Inst{18-16} = Imm;
4622 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4624 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4625 let Inst{19-16} = Imm;
4627 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4629 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4630 let Inst{20-16} = Imm;
4634 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4636 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4638 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4639 let Inst{21-16} = Imm;
4643 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4645 : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4646 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4648 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4649 let Inst{18-16} = Imm;
4651 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4653 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4654 let Inst{19-16} = Imm;
4656 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4658 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4659 let Inst{20-16} = Imm;
4663 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4664 : NeonI_ScalarShiftImm<u, opcode,
4666 (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4667 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4670 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4671 let Inst{21-16} = Imm;
4672 let Constraints = "$Src = $Rd";
4675 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4676 : NeonI_ScalarShiftImm<u, opcode,
4678 (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4679 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4682 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4683 let Inst{21-16} = Imm;
4684 let Constraints = "$Src = $Rd";
4687 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4688 RegisterClass FPRCD, RegisterClass FPRCS,
4690 : NeonI_ScalarShiftImm<u, opcode,
4691 (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4692 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4695 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4697 def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4700 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4701 let Inst{18-16} = Imm;
4703 def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4706 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4707 let Inst{19-16} = Imm;
4709 def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4712 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4713 let Inst{20-16} = Imm;
4717 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4718 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4720 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4721 let Inst{20-16} = Imm;
4723 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4725 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4726 let Inst{21-16} = Imm;
4730 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4731 Instruction INSTD> {
4732 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4733 (INSTD FPR64:$Rn, imm:$Imm)>;
4736 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4737 Instruction INSTD> {
4738 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4739 (INSTD FPR64:$Rn, imm:$Imm)>;
4742 class Neon_ScalarShiftLImm_V1_D_size_patterns<SDPatternOperator opnode,
4744 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4745 (v1i64 (Neon_vdup (i32 shl_imm64:$Imm))))),
4746 (INSTD FPR64:$Rn, imm:$Imm)>;
4748 class Neon_ScalarShiftRImm_V1_D_size_patterns<SDPatternOperator opnode,
4750 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4751 (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4752 (INSTD FPR64:$Rn, imm:$Imm)>;
4754 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4759 : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4760 def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4761 (INSTB FPR8:$Rn, imm:$Imm)>;
4762 def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4763 (INSTH FPR16:$Rn, imm:$Imm)>;
4764 def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4765 (INSTS FPR32:$Rn, imm:$Imm)>;
4768 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4770 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4771 (i32 shl_imm64:$Imm))),
4772 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4774 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4776 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4777 (i32 shr_imm64:$Imm))),
4778 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4780 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4781 SDPatternOperator opnode,
4784 Instruction INSTD> {
4785 def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4786 (INSTH FPR16:$Rn, imm:$Imm)>;
4787 def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4788 (INSTS FPR32:$Rn, imm:$Imm)>;
4789 def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4790 (INSTD FPR64:$Rn, imm:$Imm)>;
4793 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator opnode,
4795 Instruction INSTD> {
4796 def ssi : Pat<(f32 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4797 (INSTS FPR32:$Rn, imm:$Imm)>;
4798 def ddi : Pat<(f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4799 (INSTD FPR64:$Rn, imm:$Imm)>;
4802 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
4804 Instruction INSTD> {
4805 def ssi : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4806 (INSTS FPR32:$Rn, imm:$Imm)>;
4807 def ddi : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4808 (INSTD FPR64:$Rn, imm:$Imm)>;
4811 // Scalar Signed Shift Right (Immediate)
4812 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4813 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4814 // Pattern to match llvm.arm.* intrinsic.
4815 def : Neon_ScalarShiftRImm_V1_D_size_patterns<sra, SSHRddi>;
4817 // Scalar Unsigned Shift Right (Immediate)
4818 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4819 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4820 // Pattern to match llvm.arm.* intrinsic.
4821 def : Neon_ScalarShiftRImm_V1_D_size_patterns<srl, USHRddi>;
4823 // Scalar Signed Rounding Shift Right (Immediate)
4824 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4825 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4827 // Scalar Unigned Rounding Shift Right (Immediate)
4828 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4829 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4831 // Scalar Signed Shift Right and Accumulate (Immediate)
4832 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4833 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4834 <int_aarch64_neon_vsrads_n, SSRA>;
4836 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4837 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4838 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4839 <int_aarch64_neon_vsradu_n, USRA>;
4841 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4842 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4843 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4844 <int_aarch64_neon_vrsrads_n, SRSRA>;
4846 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4847 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4848 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4849 <int_aarch64_neon_vrsradu_n, URSRA>;
4851 // Scalar Shift Left (Immediate)
4852 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4853 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4854 // Pattern to match llvm.arm.* intrinsic.
4855 def : Neon_ScalarShiftLImm_V1_D_size_patterns<shl, SHLddi>;
4857 // Signed Saturating Shift Left (Immediate)
4858 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4859 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4861 SQSHLssi, SQSHLddi>;
4862 // Pattern to match llvm.arm.* intrinsic.
4863 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4865 // Unsigned Saturating Shift Left (Immediate)
4866 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4867 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4869 UQSHLssi, UQSHLddi>;
4870 // Pattern to match llvm.arm.* intrinsic.
4871 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4873 // Signed Saturating Shift Left Unsigned (Immediate)
4874 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4875 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4876 SQSHLUbbi, SQSHLUhhi,
4877 SQSHLUssi, SQSHLUddi>;
4879 // Shift Right And Insert (Immediate)
4880 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4881 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4882 <int_aarch64_neon_vsri, SRI>;
4884 // Shift Left And Insert (Immediate)
4885 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4886 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4887 <int_aarch64_neon_vsli, SLI>;
4889 // Signed Saturating Shift Right Narrow (Immediate)
4890 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4891 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4892 SQSHRNbhi, SQSHRNhsi,
4895 // Unsigned Saturating Shift Right Narrow (Immediate)
4896 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4897 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4898 UQSHRNbhi, UQSHRNhsi,
4901 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4902 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4903 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4904 SQRSHRNbhi, SQRSHRNhsi,
4907 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4908 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4909 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4910 UQRSHRNbhi, UQRSHRNhsi,
4913 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4914 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4915 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4916 SQSHRUNbhi, SQSHRUNhsi,
4919 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4920 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4921 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4922 SQRSHRUNbhi, SQRSHRUNhsi,
4925 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4926 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4927 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxs2fp_n,
4928 SCVTF_Nssi, SCVTF_Nddi>;
4930 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4931 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4932 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxu2fp_n,
4933 UCVTF_Nssi, UCVTF_Nddi>;
4935 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4936 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4937 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxs_n,
4938 FCVTZS_Nssi, FCVTZS_Nddi>;
4940 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4941 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4942 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxu_n,
4943 FCVTZU_Nssi, FCVTZU_Nddi>;
4945 // Patterns For Convert Instructions Between v1f64 and v1i64
4946 class Neon_ScalarShiftImm_cvtf_v1f64_pattern<SDPatternOperator opnode,
4948 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4949 (INST FPR64:$Rn, imm:$Imm)>;
4951 class Neon_ScalarShiftImm_fcvt_v1f64_pattern<SDPatternOperator opnode,
4953 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4954 (INST FPR64:$Rn, imm:$Imm)>;
4956 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxs2fp,
4959 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxu2fp,
4962 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxs,
4965 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxu,
4968 // Scalar Integer Add
4969 let isCommutable = 1 in {
4970 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4973 // Scalar Integer Sub
4974 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4976 // Pattern for Scalar Integer Add and Sub with D register only
4977 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4978 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4980 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4981 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4982 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4983 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4984 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4986 // Scalar Integer Saturating Add (Signed, Unsigned)
4987 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4988 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4990 // Scalar Integer Saturating Sub (Signed, Unsigned)
4991 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4992 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4995 // Patterns to match llvm.aarch64.* intrinsic for
4996 // Scalar Integer Saturating Add, Sub (Signed, Unsigned)
4997 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
4998 SQADDhhh, SQADDsss, SQADDddd>;
4999 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
5000 UQADDhhh, UQADDsss, UQADDddd>;
5001 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
5002 SQSUBhhh, SQSUBsss, SQSUBddd>;
5003 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
5004 UQSUBhhh, UQSUBsss, UQSUBddd>;
5006 // Scalar Integer Saturating Doubling Multiply Half High
5007 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
5009 // Scalar Integer Saturating Rounding Doubling Multiply Half High
5010 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
5012 // Patterns to match llvm.arm.* intrinsic for
5013 // Scalar Integer Saturating Doubling Multiply Half High and
5014 // Scalar Integer Saturating Rounding Doubling Multiply Half High
5015 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
5017 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
5020 // Scalar Floating-point Multiply Extended
5021 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
5023 // Scalar Floating-point Reciprocal Step
5024 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
5025 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrecps, f32, f32,
5026 FRECPSsss, f64, f64, FRECPSddd>;
5027 def : Pat<(v1f64 (int_arm_neon_vrecps (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5028 (FRECPSddd FPR64:$Rn, FPR64:$Rm)>;
5030 // Scalar Floating-point Reciprocal Square Root Step
5031 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
5032 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrsqrts, f32, f32,
5033 FRSQRTSsss, f64, f64, FRSQRTSddd>;
5034 def : Pat<(v1f64 (int_arm_neon_vrsqrts (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5035 (FRSQRTSddd FPR64:$Rn, FPR64:$Rm)>;
5036 def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>;
5038 // Patterns to match llvm.aarch64.* intrinsic for
5039 // Scalar Floating-point Multiply Extended,
5040 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
5042 Instruction INSTD> {
5043 def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
5044 (INSTS FPR32:$Rn, FPR32:$Rm)>;
5045 def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
5046 (INSTD FPR64:$Rn, FPR64:$Rm)>;
5049 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
5050 FMULXsss, FMULXddd>;
5051 def : Pat<(v1f64 (int_aarch64_neon_vmulx (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5052 (FMULXddd FPR64:$Rn, FPR64:$Rm)>;
5054 // Scalar Integer Shift Left (Signed, Unsigned)
5055 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
5056 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
5058 // Patterns to match llvm.arm.* intrinsic for
5059 // Scalar Integer Shift Left (Signed, Unsigned)
5060 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
5061 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
5063 // Patterns to match llvm.aarch64.* intrinsic for
5064 // Scalar Integer Shift Left (Signed, Unsigned)
5065 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
5066 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
5068 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
5069 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
5070 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
5072 // Patterns to match llvm.aarch64.* intrinsic for
5073 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
5074 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
5075 SQSHLhhh, SQSHLsss, SQSHLddd>;
5076 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
5077 UQSHLhhh, UQSHLsss, UQSHLddd>;
5079 // Patterns to match llvm.arm.* intrinsic for
5080 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
5081 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
5082 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
5084 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5085 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
5086 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
5088 // Patterns to match llvm.aarch64.* intrinsic for
5089 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5090 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
5091 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
5093 // Patterns to match llvm.arm.* intrinsic for
5094 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5095 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
5096 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
5098 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5099 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
5100 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
5102 // Patterns to match llvm.aarch64.* intrinsic for
5103 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5104 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
5105 SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
5106 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
5107 UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
5109 // Patterns to match llvm.arm.* intrinsic for
5110 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5111 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
5112 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
5114 // Signed Saturating Doubling Multiply-Add Long
5115 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
5116 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
5117 SQDMLALshh, SQDMLALdss>;
5119 // Signed Saturating Doubling Multiply-Subtract Long
5120 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
5121 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
5122 SQDMLSLshh, SQDMLSLdss>;
5124 // Signed Saturating Doubling Multiply Long
5125 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
5126 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
5127 SQDMULLshh, SQDMULLdss>;
5129 // Scalar Signed Integer Convert To Floating-point
5130 defm SCVTF : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
5131 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fps,
5134 // Scalar Unsigned Integer Convert To Floating-point
5135 defm UCVTF : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
5136 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fpu,
5139 // Scalar Floating-point Converts
5140 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
5141 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
5144 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
5145 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
5146 FCVTNSss, FCVTNSdd>;
5147 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtns, FCVTNSdd>;
5149 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
5150 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
5151 FCVTNUss, FCVTNUdd>;
5152 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtnu, FCVTNUdd>;
5154 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
5155 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
5156 FCVTMSss, FCVTMSdd>;
5157 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtms, FCVTMSdd>;
5159 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
5160 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
5161 FCVTMUss, FCVTMUdd>;
5162 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtmu, FCVTMUdd>;
5164 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
5165 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
5166 FCVTASss, FCVTASdd>;
5167 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtas, FCVTASdd>;
5169 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
5170 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
5171 FCVTAUss, FCVTAUdd>;
5172 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtau, FCVTAUdd>;
5174 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
5175 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
5176 FCVTPSss, FCVTPSdd>;
5177 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtps, FCVTPSdd>;
5179 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
5180 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
5181 FCVTPUss, FCVTPUdd>;
5182 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtpu, FCVTPUdd>;
5184 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
5185 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
5186 FCVTZSss, FCVTZSdd>;
5187 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzs,
5190 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
5191 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
5192 FCVTZUss, FCVTZUdd>;
5193 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzu,
5196 // Patterns For Convert Instructions Between v1f64 and v1i64
5197 class Neon_Scalar2SameMisc_cvtf_v1f64_pattern<SDPatternOperator opnode,
5199 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5201 class Neon_Scalar2SameMisc_fcvt_v1f64_pattern<SDPatternOperator opnode,
5203 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5205 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<sint_to_fp, SCVTFdd>;
5206 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<uint_to_fp, UCVTFdd>;
5208 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_sint, FCVTZSdd>;
5209 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_uint, FCVTZUdd>;
5211 // Scalar Floating-point Reciprocal Estimate
5212 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5213 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpe,
5214 FRECPEss, FRECPEdd>;
5215 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrecpe,
5218 // Scalar Floating-point Reciprocal Exponent
5219 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5220 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5221 FRECPXss, FRECPXdd>;
5223 // Scalar Floating-point Reciprocal Square Root Estimate
5224 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5225 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrsqrte,
5226 FRSQRTEss, FRSQRTEdd>;
5227 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrsqrte,
5230 // Scalar Floating-point Round
5231 class Neon_ScalarFloatRound_pattern<SDPatternOperator opnode, Instruction INST>
5232 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5234 def : Neon_ScalarFloatRound_pattern<fceil, FRINTPdd>;
5235 def : Neon_ScalarFloatRound_pattern<ffloor, FRINTMdd>;
5236 def : Neon_ScalarFloatRound_pattern<ftrunc, FRINTZdd>;
5237 def : Neon_ScalarFloatRound_pattern<frint, FRINTXdd>;
5238 def : Neon_ScalarFloatRound_pattern<fnearbyint, FRINTIdd>;
5239 def : Neon_ScalarFloatRound_pattern<frnd, FRINTAdd>;
5240 def : Neon_ScalarFloatRound_pattern<int_aarch64_neon_frintn, FRINTNdd>;
5242 // Scalar Integer Compare
5244 // Scalar Compare Bitwise Equal
5245 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5246 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5248 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5251 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5252 (INSTD FPR64:$Rn, FPR64:$Rm)>;
5254 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5256 // Scalar Compare Signed Greather Than Or Equal
5257 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5258 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5259 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGEddd, SETGE>;
5261 // Scalar Compare Unsigned Higher Or Same
5262 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5263 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5264 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHSddd, SETUGE>;
5266 // Scalar Compare Unsigned Higher
5267 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5268 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5269 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHIddd, SETUGT>;
5271 // Scalar Compare Signed Greater Than
5272 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5273 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5274 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGTddd, SETGT>;
5276 // Scalar Compare Bitwise Test Bits
5277 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5278 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5279 defm : Neon_Scalar3Same_D_size_patterns<Neon_tst, CMTSTddd>;
5281 // Scalar Compare Bitwise Equal To Zero
5282 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5283 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5285 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETEQ, CMEQddi>;
5287 // Scalar Compare Signed Greather Than Or Equal To Zero
5288 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5289 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5291 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGE, CMGEddi>;
5293 // Scalar Compare Signed Greater Than Zero
5294 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5295 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5297 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGT, CMGTddi>;
5299 // Scalar Compare Signed Less Than Or Equal To Zero
5300 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5301 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5303 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLE, CMLEddi>;
5305 // Scalar Compare Less Than Zero
5306 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5307 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5309 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
5311 // Scalar Floating-point Compare
5313 // Scalar Floating-point Compare Mask Equal
5314 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5315 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fceq, v1i32, f32,
5316 FCMEQsss, v1i64, f64, FCMEQddd>;
5317 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
5319 // Scalar Floating-point Compare Mask Equal To Zero
5320 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5321 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fceq, SETEQ,
5322 FCMEQZssi, FCMEQZddi>;
5324 // Scalar Floating-point Compare Mask Greater Than Or Equal
5325 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5326 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcge, v1i32, f32,
5327 FCMGEsss, v1i64, f64, FCMGEddd>;
5328 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
5330 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5331 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5332 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcge, SETGE,
5333 FCMGEZssi, FCMGEZddi>;
5335 // Scalar Floating-point Compare Mask Greather Than
5336 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5337 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcgt, v1i32, f32,
5338 FCMGTsss, v1i64, f64, FCMGTddd>;
5339 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
5341 // Scalar Floating-point Compare Mask Greather Than Zero
5342 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5343 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcgt, SETGT,
5344 FCMGTZssi, FCMGTZddi>;
5346 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5347 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5348 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fclez, SETLE,
5349 FCMLEZssi, FCMLEZddi>;
5351 // Scalar Floating-point Compare Mask Less Than Zero
5352 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5353 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcltz, SETLT,
5354 FCMLTZssi, FCMLTZddi>;
5356 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5357 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5358 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcage, v1i32, f32,
5359 FACGEsss, v1i64, f64, FACGEddd>;
5360 def : Pat<(v1i64 (int_aarch64_neon_vcage (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5361 (FACGEddd FPR64:$Rn, FPR64:$Rm)>;
5363 // Scalar Floating-point Absolute Compare Mask Greater Than
5364 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5365 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcagt, v1i32, f32,
5366 FACGTsss, v1i64, f64, FACGTddd>;
5367 def : Pat<(v1i64 (int_aarch64_neon_vcagt (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5368 (FACGTddd FPR64:$Rn, FPR64:$Rm)>;
5370 // Scalar Floating-point Absolute Difference
5371 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5372 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vabd, f32, f32,
5373 FABDsss, f64, f64, FABDddd>;
5375 // Scalar Absolute Value
5376 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5377 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5379 // Scalar Signed Saturating Absolute Value
5380 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5381 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5382 SQABSbb, SQABShh, SQABSss, SQABSdd>;
5385 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5386 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5388 // Scalar Signed Saturating Negate
5389 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5390 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5391 SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5393 // Scalar Signed Saturating Accumulated of Unsigned Value
5394 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5395 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5397 SUQADDss, SUQADDdd>;
5399 // Scalar Unsigned Saturating Accumulated of Signed Value
5400 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5401 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5403 USQADDss, USQADDdd>;
5405 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5406 (v1i64 FPR64:$Rn))),
5407 (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5409 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5410 (v1i64 FPR64:$Rn))),
5411 (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5413 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5416 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5417 (SQABSdd FPR64:$Rn)>;
5419 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5420 (SQNEGdd FPR64:$Rn)>;
5422 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5423 (v1i64 FPR64:$Rn))),
5426 // Scalar Signed Saturating Extract Unsigned Narrow
5427 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5428 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5432 // Scalar Signed Saturating Extract Narrow
5433 defm SQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5434 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5438 // Scalar Unsigned Saturating Extract Narrow
5439 defm UQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5440 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5444 // Scalar Reduce Pairwise
5446 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5447 string asmop, bit Commutable = 0> {
5448 let isCommutable = Commutable in {
5449 def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5450 (outs FPR64:$Rd), (ins VPR128:$Rn),
5451 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5457 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5458 string asmop, bit Commutable = 0>
5459 : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5460 let isCommutable = Commutable in {
5461 def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5462 (outs FPR32:$Rd), (ins VPR64:$Rn),
5463 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5469 // Scalar Reduce Addition Pairwise (Integer) with
5470 // Pattern to match llvm.arm.* intrinsic
5471 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5473 // Pattern to match llvm.aarch64.* intrinsic for
5474 // Scalar Reduce Addition Pairwise (Integer)
5475 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5476 (ADDPvv_D_2D VPR128:$Rn)>;
5477 def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
5478 (ADDPvv_D_2D VPR128:$Rn)>;
5480 // Scalar Reduce Addition Pairwise (Floating Point)
5481 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5483 // Scalar Reduce Maximum Pairwise (Floating Point)
5484 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5486 // Scalar Reduce Minimum Pairwise (Floating Point)
5487 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5489 // Scalar Reduce maxNum Pairwise (Floating Point)
5490 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5492 // Scalar Reduce minNum Pairwise (Floating Point)
5493 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5495 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnode,
5497 Instruction INSTD> {
5498 def : Pat<(f32 (opnode (v2f32 VPR64:$Rn))),
5500 def : Pat<(f64 (opnode (v2f64 VPR128:$Rn))),
5501 (INSTD VPR128:$Rn)>;
5504 // Patterns to match llvm.aarch64.* intrinsic for
5505 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5506 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5507 FADDPvv_S_2S, FADDPvv_D_2D>;
5509 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5510 FMAXPvv_S_2S, FMAXPvv_D_2D>;
5512 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5513 FMINPvv_S_2S, FMINPvv_D_2D>;
5515 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5516 FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5518 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5519 FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5521 def : Pat<(f32 (int_aarch64_neon_vpfadd (v4f32 VPR128:$Rn))),
5522 (FADDPvv_S_2S (v2f32
5524 (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
5527 // Scalar by element Arithmetic
5529 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5530 string rmlane, bit u, bit szhi, bit szlo,
5531 RegisterClass ResFPR, RegisterClass OpFPR,
5532 RegisterOperand OpVPR, Operand OpImm>
5533 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5535 (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5536 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5543 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5545 bit u, bit szhi, bit szlo,
5546 RegisterClass ResFPR,
5547 RegisterClass OpFPR,
5548 RegisterOperand OpVPR,
5550 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5552 (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5553 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5556 let Constraints = "$src = $Rd";
5561 // Scalar Floating Point multiply (scalar, by element)
5562 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5563 0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5564 let Inst{11} = Imm{1}; // h
5565 let Inst{21} = Imm{0}; // l
5566 let Inst{20-16} = MRm;
5568 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5569 0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5570 let Inst{11} = Imm{0}; // h
5571 let Inst{21} = 0b0; // l
5572 let Inst{20-16} = MRm;
5575 // Scalar Floating Point multiply extended (scalar, by element)
5576 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5577 0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5578 let Inst{11} = Imm{1}; // h
5579 let Inst{21} = Imm{0}; // l
5580 let Inst{20-16} = MRm;
5582 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5583 0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5584 let Inst{11} = Imm{0}; // h
5585 let Inst{21} = 0b0; // l
5586 let Inst{20-16} = MRm;
5589 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5590 SDPatternOperator opnode,
5592 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5593 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5595 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5596 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5597 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5599 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5600 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5601 (ResTy (INST (ResTy FPRC:$Rn),
5602 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5606 def : Pat<(ResTy (opnode
5607 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5609 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5611 def : Pat<(ResTy (opnode
5612 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5614 (ResTy (INST (ResTy FPRC:$Rn),
5615 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5619 // Patterns for Scalar Floating Point multiply (scalar, by element)
5620 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5621 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5622 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5623 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5625 // Patterns for Scalar Floating Point multiply extended (scalar, by element)
5626 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5627 FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5628 v2f32, v4f32, neon_uimm1_bare>;
5629 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5630 FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5631 v1f64, v2f64, neon_uimm0_bare>;
5633 // Scalar Floating Point fused multiply-add (scalar, by element)
5634 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5635 0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5636 let Inst{11} = Imm{1}; // h
5637 let Inst{21} = Imm{0}; // l
5638 let Inst{20-16} = MRm;
5640 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5641 0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5642 let Inst{11} = Imm{0}; // h
5643 let Inst{21} = 0b0; // l
5644 let Inst{20-16} = MRm;
5647 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5648 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5649 0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5650 let Inst{11} = Imm{1}; // h
5651 let Inst{21} = Imm{0}; // l
5652 let Inst{20-16} = MRm;
5654 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5655 0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5656 let Inst{11} = Imm{0}; // h
5657 let Inst{21} = 0b0; // l
5658 let Inst{20-16} = MRm;
5660 // We are allowed to match the fma instruction regardless of compile options.
5661 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5662 Instruction FMLAI, Instruction FMLSI,
5663 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5664 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5666 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5667 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5669 (ResTy (FMLAI (ResTy FPRC:$Ra),
5670 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5672 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5673 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5675 (ResTy (FMLAI (ResTy FPRC:$Ra),
5677 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5680 // swapped fmla operands
5681 def : Pat<(ResTy (fma
5682 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5685 (ResTy (FMLAI (ResTy FPRC:$Ra),
5686 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5688 def : Pat<(ResTy (fma
5689 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5692 (ResTy (FMLAI (ResTy FPRC:$Ra),
5694 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5698 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5699 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5701 (ResTy (FMLSI (ResTy FPRC:$Ra),
5702 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5704 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5705 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5707 (ResTy (FMLSI (ResTy FPRC:$Ra),
5709 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5712 // swapped fmls operands
5713 def : Pat<(ResTy (fma
5714 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5717 (ResTy (FMLSI (ResTy FPRC:$Ra),
5718 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5720 def : Pat<(ResTy (fma
5721 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5724 (ResTy (FMLSI (ResTy FPRC:$Ra),
5726 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5730 // Scalar Floating Point fused multiply-add and
5731 // multiply-subtract (scalar, by element)
5732 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5733 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5734 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5735 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5736 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5737 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5739 // Scalar Signed saturating doubling multiply long (scalar, by element)
5740 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5741 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5742 let Inst{11} = 0b0; // h
5743 let Inst{21} = Imm{1}; // l
5744 let Inst{20} = Imm{0}; // m
5745 let Inst{19-16} = MRm{3-0};
5747 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5748 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5749 let Inst{11} = Imm{2}; // h
5750 let Inst{21} = Imm{1}; // l
5751 let Inst{20} = Imm{0}; // m
5752 let Inst{19-16} = MRm{3-0};
5754 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5755 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5756 let Inst{11} = 0b0; // h
5757 let Inst{21} = Imm{0}; // l
5758 let Inst{20-16} = MRm;
5760 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5761 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5762 let Inst{11} = Imm{1}; // h
5763 let Inst{21} = Imm{0}; // l
5764 let Inst{20-16} = MRm;
5767 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5768 SDPatternOperator opnode,
5770 ValueType ResTy, RegisterClass FPRC,
5771 ValueType OpVTy, ValueType OpTy,
5772 ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5774 def : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5775 (OpVTy (scalar_to_vector
5776 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5777 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5780 def : Pat<(ResTy (opnode
5781 (OpVTy (scalar_to_vector
5782 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5784 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5788 // Patterns for Scalar Signed saturating doubling
5789 // multiply long (scalar, by element)
5790 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5791 SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5792 i32, VPR64Lo, neon_uimm2_bare>;
5793 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5794 SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5795 i32, VPR128Lo, neon_uimm3_bare>;
5796 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5797 SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5798 i32, VPR64Lo, neon_uimm1_bare>;
5799 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5800 SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5801 i32, VPR128Lo, neon_uimm2_bare>;
5803 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5804 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5805 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5806 let Inst{11} = 0b0; // h
5807 let Inst{21} = Imm{1}; // l
5808 let Inst{20} = Imm{0}; // m
5809 let Inst{19-16} = MRm{3-0};
5811 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5812 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5813 let Inst{11} = Imm{2}; // h
5814 let Inst{21} = Imm{1}; // l
5815 let Inst{20} = Imm{0}; // m
5816 let Inst{19-16} = MRm{3-0};
5818 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5819 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5820 let Inst{11} = 0b0; // h
5821 let Inst{21} = Imm{0}; // l
5822 let Inst{20-16} = MRm;
5824 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5825 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5826 let Inst{11} = Imm{1}; // h
5827 let Inst{21} = Imm{0}; // l
5828 let Inst{20-16} = MRm;
5831 // Scalar Signed saturating doubling
5832 // multiply-subtract long (scalar, by element)
5833 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5834 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5835 let Inst{11} = 0b0; // h
5836 let Inst{21} = Imm{1}; // l
5837 let Inst{20} = Imm{0}; // m
5838 let Inst{19-16} = MRm{3-0};
5840 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5841 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5842 let Inst{11} = Imm{2}; // h
5843 let Inst{21} = Imm{1}; // l
5844 let Inst{20} = Imm{0}; // m
5845 let Inst{19-16} = MRm{3-0};
5847 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5848 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5849 let Inst{11} = 0b0; // h
5850 let Inst{21} = Imm{0}; // l
5851 let Inst{20-16} = MRm;
5853 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5854 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5855 let Inst{11} = Imm{1}; // h
5856 let Inst{21} = Imm{0}; // l
5857 let Inst{20-16} = MRm;
5860 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5861 SDPatternOperator opnode,
5862 SDPatternOperator coreopnode,
5864 ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5866 ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5868 def : Pat<(ResTy (opnode
5869 (ResTy ResFPRC:$Ra),
5870 (ResTy (coreopnode (OpTy FPRC:$Rn),
5871 (OpTy (scalar_to_vector
5872 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5873 (ResTy (INST (ResTy ResFPRC:$Ra),
5874 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5877 def : Pat<(ResTy (opnode
5878 (ResTy ResFPRC:$Ra),
5880 (OpTy (scalar_to_vector
5881 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5882 (OpTy FPRC:$Rn))))),
5883 (ResTy (INST (ResTy ResFPRC:$Ra),
5884 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5887 // Patterns for Scalar Signed saturating
5888 // doubling multiply-add long (scalar, by element)
5889 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5890 int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5891 i32, VPR64Lo, neon_uimm2_bare>;
5892 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5893 int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5894 i32, VPR128Lo, neon_uimm3_bare>;
5895 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5896 int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5897 i32, VPR64Lo, neon_uimm1_bare>;
5898 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5899 int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5900 i32, VPR128Lo, neon_uimm2_bare>;
5902 // Patterns for Scalar Signed saturating
5903 // doubling multiply-sub long (scalar, by element)
5904 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5905 int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5906 i32, VPR64Lo, neon_uimm2_bare>;
5907 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5908 int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5909 i32, VPR128Lo, neon_uimm3_bare>;
5910 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5911 int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5912 i32, VPR64Lo, neon_uimm1_bare>;
5913 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5914 int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5915 i32, VPR128Lo, neon_uimm2_bare>;
5917 // Scalar Signed saturating doubling multiply returning
5918 // high half (scalar, by element)
5919 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5920 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5921 let Inst{11} = 0b0; // h
5922 let Inst{21} = Imm{1}; // l
5923 let Inst{20} = Imm{0}; // m
5924 let Inst{19-16} = MRm{3-0};
5926 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5927 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5928 let Inst{11} = Imm{2}; // h
5929 let Inst{21} = Imm{1}; // l
5930 let Inst{20} = Imm{0}; // m
5931 let Inst{19-16} = MRm{3-0};
5933 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5934 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5935 let Inst{11} = 0b0; // h
5936 let Inst{21} = Imm{0}; // l
5937 let Inst{20-16} = MRm;
5939 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5940 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5941 let Inst{11} = Imm{1}; // h
5942 let Inst{21} = Imm{0}; // l
5943 let Inst{20-16} = MRm;
5946 // Patterns for Scalar Signed saturating doubling multiply returning
5947 // high half (scalar, by element)
5948 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5949 SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5950 i32, VPR64Lo, neon_uimm2_bare>;
5951 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5952 SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5953 i32, VPR128Lo, neon_uimm3_bare>;
5954 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5955 SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5956 i32, VPR64Lo, neon_uimm1_bare>;
5957 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5958 SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5959 i32, VPR128Lo, neon_uimm2_bare>;
5961 // Scalar Signed saturating rounding doubling multiply
5962 // returning high half (scalar, by element)
5963 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5964 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5965 let Inst{11} = 0b0; // h
5966 let Inst{21} = Imm{1}; // l
5967 let Inst{20} = Imm{0}; // m
5968 let Inst{19-16} = MRm{3-0};
5970 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5971 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5972 let Inst{11} = Imm{2}; // h
5973 let Inst{21} = Imm{1}; // l
5974 let Inst{20} = Imm{0}; // m
5975 let Inst{19-16} = MRm{3-0};
5977 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5978 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5979 let Inst{11} = 0b0; // h
5980 let Inst{21} = Imm{0}; // l
5981 let Inst{20-16} = MRm;
5983 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5984 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5985 let Inst{11} = Imm{1}; // h
5986 let Inst{21} = Imm{0}; // l
5987 let Inst{20-16} = MRm;
5990 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5991 SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
5992 VPR64Lo, neon_uimm2_bare>;
5993 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5994 SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
5995 VPR128Lo, neon_uimm3_bare>;
5996 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5997 SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
5998 VPR64Lo, neon_uimm1_bare>;
5999 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6000 SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
6001 VPR128Lo, neon_uimm2_bare>;
6003 // Scalar general arithmetic operation
6004 class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
6006 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
6008 class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
6010 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
6011 (INST FPR64:$Rn, FPR64:$Rm)>;
6013 class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
6015 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
6016 (v1f64 FPR64:$Ra))),
6017 (INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
6019 def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
6020 def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
6021 def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
6022 def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
6023 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
6024 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
6025 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
6026 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
6027 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
6029 def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
6030 def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
6032 def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
6033 def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
6035 // Scalar Copy - DUP element to scalar
6036 class NeonI_Scalar_DUP<string asmop, string asmlane,
6037 RegisterClass ResRC, RegisterOperand VPRC,
6039 : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
6040 asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
6046 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
6047 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6049 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
6050 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6052 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
6053 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6055 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
6056 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6059 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 0)),
6060 (f32 (EXTRACT_SUBREG (v4f32 VPR128:$Rn), sub_32))>;
6061 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 1)),
6062 (f32 (DUPsv_S (v4f32 VPR128:$Rn), 1))>;
6063 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 2)),
6064 (f32 (DUPsv_S (v4f32 VPR128:$Rn), 2))>;
6065 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 3)),
6066 (f32 (DUPsv_S (v4f32 VPR128:$Rn), 3))>;
6068 def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 0)),
6069 (f64 (EXTRACT_SUBREG (v2f64 VPR128:$Rn), sub_64))>;
6070 def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 1)),
6071 (f64 (DUPdv_D (v2f64 VPR128:$Rn), 1))>;
6073 def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 0)),
6074 (f32 (EXTRACT_SUBREG (v2f32 VPR64:$Rn), sub_32))>;
6075 def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 1)),
6076 (f32 (DUPsv_S (v4f32 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6079 def : Pat<(f64 (vector_extract (v1f64 VPR64:$Rn), 0)),
6080 (f64 (EXTRACT_SUBREG (v1f64 VPR64:$Rn), sub_64))>;
6082 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
6083 ValueType ResTy, ValueType OpTy,Operand OpLImm,
6084 ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
6086 def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
6087 (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
6089 def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
6091 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6095 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
6096 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
6097 v8i8, v16i8, neon_uimm3_bare>;
6098 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
6099 v4i16, v8i16, neon_uimm2_bare>;
6100 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
6101 v2i32, v4i32, neon_uimm1_bare>;
6103 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
6104 ValueType OpTy, ValueType ElemTy,
6105 Operand OpImm, ValueType OpNTy,
6106 ValueType ExTy, Operand OpNImm> {
6108 def : Pat<(ResTy (vector_insert (ResTy undef),
6109 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
6110 (neon_uimm0_bare:$Imm))),
6111 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
6113 def : Pat<(ResTy (vector_insert (ResTy undef),
6114 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
6117 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6121 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
6122 ValueType OpTy, ValueType ElemTy,
6123 Operand OpImm, ValueType OpNTy,
6124 ValueType ExTy, Operand OpNImm> {
6126 def : Pat<(ResTy (scalar_to_vector
6127 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
6128 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
6130 def : Pat<(ResTy (scalar_to_vector
6131 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
6133 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6137 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
6139 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
6140 v1i64, v2i64, i64, neon_uimm1_bare,
6141 v1i64, v2i64, neon_uimm0_bare>;
6142 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
6143 v1i32, v4i32, i32, neon_uimm2_bare,
6144 v2i32, v4i32, neon_uimm1_bare>;
6145 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
6146 v1i16, v8i16, i32, neon_uimm3_bare,
6147 v4i16, v8i16, neon_uimm2_bare>;
6148 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
6149 v1i8, v16i8, i32, neon_uimm4_bare,
6150 v8i8, v16i8, neon_uimm3_bare>;
6151 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
6152 v1i64, v2i64, i64, neon_uimm1_bare,
6153 v1i64, v2i64, neon_uimm0_bare>;
6154 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
6155 v1i32, v4i32, i32, neon_uimm2_bare,
6156 v2i32, v4i32, neon_uimm1_bare>;
6157 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
6158 v1i16, v8i16, i32, neon_uimm3_bare,
6159 v4i16, v8i16, neon_uimm2_bare>;
6160 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
6161 v1i8, v16i8, i32, neon_uimm4_bare,
6162 v8i8, v16i8, neon_uimm3_bare>;
6164 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
6165 Instruction DUPI, Operand OpImm,
6166 RegisterClass ResRC> {
6167 def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
6168 (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
6171 // Aliases for Scalar copy - DUP element (scalar)
6172 // FIXME: This is actually the preferred syntax but TableGen can't deal with
6173 // custom printing of aliases.
6174 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
6175 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
6176 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
6177 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
6179 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
6181 def : Pat<(ResTy (GetLow VPR128:$Rn)),
6182 (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
6183 def : Pat<(ResTy (GetHigh VPR128:$Rn)),
6184 (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
6187 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
6188 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
6189 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
6190 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
6191 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
6192 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
6194 //===----------------------------------------------------------------------===//
6195 // Non-Instruction Patterns
6196 //===----------------------------------------------------------------------===//
6198 // 64-bit vector bitcasts...
6200 def : Pat<(v1i64 (bitconvert (v8i8 VPR64:$src))), (v1i64 VPR64:$src)>;
6201 def : Pat<(v2f32 (bitconvert (v8i8 VPR64:$src))), (v2f32 VPR64:$src)>;
6202 def : Pat<(v2i32 (bitconvert (v8i8 VPR64:$src))), (v2i32 VPR64:$src)>;
6203 def : Pat<(v4i16 (bitconvert (v8i8 VPR64:$src))), (v4i16 VPR64:$src)>;
6205 def : Pat<(v1i64 (bitconvert (v4i16 VPR64:$src))), (v1i64 VPR64:$src)>;
6206 def : Pat<(v2i32 (bitconvert (v4i16 VPR64:$src))), (v2i32 VPR64:$src)>;
6207 def : Pat<(v2f32 (bitconvert (v4i16 VPR64:$src))), (v2f32 VPR64:$src)>;
6208 def : Pat<(v8i8 (bitconvert (v4i16 VPR64:$src))), (v8i8 VPR64:$src)>;
6210 def : Pat<(v1i64 (bitconvert (v2i32 VPR64:$src))), (v1i64 VPR64:$src)>;
6211 def : Pat<(v2f32 (bitconvert (v2i32 VPR64:$src))), (v2f32 VPR64:$src)>;
6212 def : Pat<(v4i16 (bitconvert (v2i32 VPR64:$src))), (v4i16 VPR64:$src)>;
6213 def : Pat<(v8i8 (bitconvert (v2i32 VPR64:$src))), (v8i8 VPR64:$src)>;
6215 def : Pat<(v1i64 (bitconvert (v2f32 VPR64:$src))), (v1i64 VPR64:$src)>;
6216 def : Pat<(v2i32 (bitconvert (v2f32 VPR64:$src))), (v2i32 VPR64:$src)>;
6217 def : Pat<(v4i16 (bitconvert (v2f32 VPR64:$src))), (v4i16 VPR64:$src)>;
6218 def : Pat<(v8i8 (bitconvert (v2f32 VPR64:$src))), (v8i8 VPR64:$src)>;
6220 def : Pat<(v2f32 (bitconvert (v1i64 VPR64:$src))), (v2f32 VPR64:$src)>;
6221 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6222 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6223 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6225 def : Pat<(v1i64 (bitconvert (v1f64 VPR64:$src))), (v1i64 VPR64:$src)>;
6226 def : Pat<(v2f32 (bitconvert (v1f64 VPR64:$src))), (v2f32 VPR64:$src)>;
6227 def : Pat<(v2i32 (bitconvert (v1f64 VPR64:$src))), (v2i32 VPR64:$src)>;
6228 def : Pat<(v4i16 (bitconvert (v1f64 VPR64:$src))), (v4i16 VPR64:$src)>;
6229 def : Pat<(v8i8 (bitconvert (v1f64 VPR64:$src))), (v8i8 VPR64:$src)>;
6230 def : Pat<(f64 (bitconvert (v1f64 VPR64:$src))), (f64 VPR64:$src)>;
6232 def : Pat<(v1f64 (bitconvert (v1i64 VPR64:$src))), (v1f64 VPR64:$src)>;
6233 def : Pat<(v1f64 (bitconvert (v2f32 VPR64:$src))), (v1f64 VPR64:$src)>;
6234 def : Pat<(v1f64 (bitconvert (v2i32 VPR64:$src))), (v1f64 VPR64:$src)>;
6235 def : Pat<(v1f64 (bitconvert (v4i16 VPR64:$src))), (v1f64 VPR64:$src)>;
6236 def : Pat<(v1f64 (bitconvert (v8i8 VPR64:$src))), (v1f64 VPR64:$src)>;
6237 def : Pat<(v1f64 (bitconvert (f64 VPR64:$src))), (v1f64 VPR64:$src)>;
6239 // ..and 128-bit vector bitcasts...
6241 def : Pat<(v2f64 (bitconvert (v16i8 VPR128:$src))), (v2f64 VPR128:$src)>;
6242 def : Pat<(v2i64 (bitconvert (v16i8 VPR128:$src))), (v2i64 VPR128:$src)>;
6243 def : Pat<(v4f32 (bitconvert (v16i8 VPR128:$src))), (v4f32 VPR128:$src)>;
6244 def : Pat<(v4i32 (bitconvert (v16i8 VPR128:$src))), (v4i32 VPR128:$src)>;
6245 def : Pat<(v8i16 (bitconvert (v16i8 VPR128:$src))), (v8i16 VPR128:$src)>;
6247 def : Pat<(v2f64 (bitconvert (v8i16 VPR128:$src))), (v2f64 VPR128:$src)>;
6248 def : Pat<(v2i64 (bitconvert (v8i16 VPR128:$src))), (v2i64 VPR128:$src)>;
6249 def : Pat<(v4i32 (bitconvert (v8i16 VPR128:$src))), (v4i32 VPR128:$src)>;
6250 def : Pat<(v4f32 (bitconvert (v8i16 VPR128:$src))), (v4f32 VPR128:$src)>;
6251 def : Pat<(v16i8 (bitconvert (v8i16 VPR128:$src))), (v16i8 VPR128:$src)>;
6253 def : Pat<(v2f64 (bitconvert (v4i32 VPR128:$src))), (v2f64 VPR128:$src)>;
6254 def : Pat<(v2i64 (bitconvert (v4i32 VPR128:$src))), (v2i64 VPR128:$src)>;
6255 def : Pat<(v4f32 (bitconvert (v4i32 VPR128:$src))), (v4f32 VPR128:$src)>;
6256 def : Pat<(v8i16 (bitconvert (v4i32 VPR128:$src))), (v8i16 VPR128:$src)>;
6257 def : Pat<(v16i8 (bitconvert (v4i32 VPR128:$src))), (v16i8 VPR128:$src)>;
6259 def : Pat<(v2f64 (bitconvert (v4f32 VPR128:$src))), (v2f64 VPR128:$src)>;
6260 def : Pat<(v2i64 (bitconvert (v4f32 VPR128:$src))), (v2i64 VPR128:$src)>;
6261 def : Pat<(v4i32 (bitconvert (v4f32 VPR128:$src))), (v4i32 VPR128:$src)>;
6262 def : Pat<(v8i16 (bitconvert (v4f32 VPR128:$src))), (v8i16 VPR128:$src)>;
6263 def : Pat<(v16i8 (bitconvert (v4f32 VPR128:$src))), (v16i8 VPR128:$src)>;
6265 def : Pat<(v2f64 (bitconvert (v2i64 VPR128:$src))), (v2f64 VPR128:$src)>;
6266 def : Pat<(v4f32 (bitconvert (v2i64 VPR128:$src))), (v4f32 VPR128:$src)>;
6267 def : Pat<(v4i32 (bitconvert (v2i64 VPR128:$src))), (v4i32 VPR128:$src)>;
6268 def : Pat<(v8i16 (bitconvert (v2i64 VPR128:$src))), (v8i16 VPR128:$src)>;
6269 def : Pat<(v16i8 (bitconvert (v2i64 VPR128:$src))), (v16i8 VPR128:$src)>;
6271 def : Pat<(v2i64 (bitconvert (v2f64 VPR128:$src))), (v2i64 VPR128:$src)>;
6272 def : Pat<(v4f32 (bitconvert (v2f64 VPR128:$src))), (v4f32 VPR128:$src)>;
6273 def : Pat<(v4i32 (bitconvert (v2f64 VPR128:$src))), (v4i32 VPR128:$src)>;
6274 def : Pat<(v8i16 (bitconvert (v2f64 VPR128:$src))), (v8i16 VPR128:$src)>;
6275 def : Pat<(v16i8 (bitconvert (v2f64 VPR128:$src))), (v16i8 VPR128:$src)>;
6277 // ...and scalar bitcasts...
6278 def : Pat<(f16 (bitconvert (v1i16 FPR16:$src))), (f16 FPR16:$src)>;
6279 def : Pat<(f32 (bitconvert (v1i32 FPR32:$src))), (f32 FPR32:$src)>;
6280 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
6281 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
6283 def : Pat<(i64 (bitconvert (v1i64 FPR64:$src))), (FMOVxd $src)>;
6284 def : Pat<(i64 (bitconvert (v1f64 FPR64:$src))), (FMOVxd $src)>;
6285 def : Pat<(i64 (bitconvert (v2i32 FPR64:$src))), (FMOVxd $src)>;
6286 def : Pat<(i64 (bitconvert (v2f32 FPR64:$src))), (FMOVxd $src)>;
6287 def : Pat<(i64 (bitconvert (v4i16 FPR64:$src))), (FMOVxd $src)>;
6288 def : Pat<(i64 (bitconvert (v8i8 FPR64:$src))), (FMOVxd $src)>;
6290 def : Pat<(i32 (bitconvert (v1i32 FPR32:$src))), (FMOVws $src)>;
6292 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6293 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6294 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6296 def : Pat<(f64 (bitconvert (v8i8 VPR64:$src))), (f64 VPR64:$src)>;
6297 def : Pat<(f64 (bitconvert (v4i16 VPR64:$src))), (f64 VPR64:$src)>;
6298 def : Pat<(f64 (bitconvert (v2i32 VPR64:$src))), (f64 VPR64:$src)>;
6299 def : Pat<(f64 (bitconvert (v2f32 VPR64:$src))), (f64 VPR64:$src)>;
6300 def : Pat<(f64 (bitconvert (v1i64 VPR64:$src))), (f64 VPR64:$src)>;
6302 def : Pat<(f128 (bitconvert (v16i8 VPR128:$src))), (f128 VPR128:$src)>;
6303 def : Pat<(f128 (bitconvert (v8i16 VPR128:$src))), (f128 VPR128:$src)>;
6304 def : Pat<(f128 (bitconvert (v4i32 VPR128:$src))), (f128 VPR128:$src)>;
6305 def : Pat<(f128 (bitconvert (v2i64 VPR128:$src))), (f128 VPR128:$src)>;
6306 def : Pat<(f128 (bitconvert (v4f32 VPR128:$src))), (f128 VPR128:$src)>;
6307 def : Pat<(f128 (bitconvert (v2f64 VPR128:$src))), (f128 VPR128:$src)>;
6309 def : Pat<(v1i16 (bitconvert (f16 FPR16:$src))), (v1i16 FPR16:$src)>;
6310 def : Pat<(v1i32 (bitconvert (f32 FPR32:$src))), (v1i32 FPR32:$src)>;
6311 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6312 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
6314 def : Pat<(v1i64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6315 def : Pat<(v1f64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6316 def : Pat<(v2i32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6317 def : Pat<(v2f32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6318 def : Pat<(v4i16 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6319 def : Pat<(v8i8 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6321 def : Pat<(v1i32 (bitconvert (i32 GPR32:$src))), (FMOVsw $src)>;
6323 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
6324 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
6325 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
6326 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
6327 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6329 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
6330 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
6331 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
6332 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
6333 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
6334 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
6336 // Scalar Three Same
6338 def neon_uimm3 : Operand<i64>,
6339 ImmLeaf<i64, [{return Imm < 8;}]> {
6340 let ParserMatchClass = uimm3_asmoperand;
6341 let PrintMethod = "printUImmHexOperand";
6344 def neon_uimm4 : Operand<i64>,
6345 ImmLeaf<i64, [{return Imm < 16;}]> {
6346 let ParserMatchClass = uimm4_asmoperand;
6347 let PrintMethod = "printUImmHexOperand";
6351 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6352 string OpS, RegisterOperand OpVPR, Operand OpImm>
6353 : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6354 (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6355 asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6356 ", $Rm." # OpS # ", $Index",
6362 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6363 VPR64, neon_uimm3> {
6364 let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6367 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6368 VPR128, neon_uimm4> {
6369 let Inst{14-11} = Index;
6372 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6374 : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6376 (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6378 def : NI_Extract<v8i8, VPR64, EXTvvvi_8b, neon_uimm3>;
6379 def : NI_Extract<v4i16, VPR64, EXTvvvi_8b, neon_uimm3>;
6380 def : NI_Extract<v2i32, VPR64, EXTvvvi_8b, neon_uimm3>;
6381 def : NI_Extract<v1i64, VPR64, EXTvvvi_8b, neon_uimm3>;
6382 def : NI_Extract<v2f32, VPR64, EXTvvvi_8b, neon_uimm3>;
6383 def : NI_Extract<v1f64, VPR64, EXTvvvi_8b, neon_uimm3>;
6384 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6385 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6386 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6387 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6388 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6389 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6392 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6393 string asmop, string OpS, RegisterOperand OpVPR,
6394 RegisterOperand VecList>
6395 : NeonI_TBL<q, op2, len, op,
6396 (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6397 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6401 // The vectors in look up table are always 16b
6402 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6403 def _8b : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6404 !cast<RegisterOperand>(List # "16B_operand")>;
6406 def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6407 !cast<RegisterOperand>(List # "16B_operand")>;
6410 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6411 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6412 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6413 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6415 // Table lookup extention
6416 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6417 string asmop, string OpS, RegisterOperand OpVPR,
6418 RegisterOperand VecList>
6419 : NeonI_TBL<q, op2, len, op,
6420 (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6421 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6424 let Constraints = "$src = $Rd";
6427 // The vectors in look up table are always 16b
6428 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6429 def _8b : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6430 !cast<RegisterOperand>(List # "16B_operand")>;
6432 def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6433 !cast<RegisterOperand>(List # "16B_operand")>;
6436 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6437 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6438 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6439 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6441 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6442 RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6443 : NeonI_copy<0b1, 0b0, 0b0011,
6444 (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6445 asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6446 [(set (ResTy VPR128:$Rd),
6447 (ResTy (vector_insert
6448 (ResTy VPR128:$src),
6453 let Constraints = "$src = $Rd";
6456 //Insert element (vector, from main)
6457 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6459 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6461 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6463 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6465 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6467 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6469 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6471 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6474 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6475 (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6476 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6477 (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6478 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6479 (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6480 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6481 (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6483 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6484 RegisterClass OpGPR, ValueType OpTy,
6485 Operand OpImm, Instruction INS>
6486 : Pat<(ResTy (vector_insert
6490 (ResTy (EXTRACT_SUBREG
6491 (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6492 OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6494 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6495 neon_uimm3_bare, INSbw>;
6496 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6497 neon_uimm2_bare, INShw>;
6498 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6499 neon_uimm1_bare, INSsw>;
6500 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6501 neon_uimm0_bare, INSdx>;
6503 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6504 : NeonI_insert<0b1, 0b1,
6505 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6506 ResImm:$Immd, ResImm:$Immn),
6507 asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6510 let Constraints = "$src = $Rd";
6515 //Insert element (vector, from element)
6516 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6517 let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6518 let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6520 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6521 let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6522 let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6523 // bit 11 is unspecified, but should be set to zero.
6525 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6526 let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6527 let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6528 // bits 11-12 are unspecified, but should be set to zero.
6530 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6531 let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6532 let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6533 // bits 11-13 are unspecified, but should be set to zero.
6536 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6537 (INSELb VPR128:$Rd, VPR128:$Rn,
6538 neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6539 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6540 (INSELh VPR128:$Rd, VPR128:$Rn,
6541 neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6542 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6543 (INSELs VPR128:$Rd, VPR128:$Rn,
6544 neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6545 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6546 (INSELd VPR128:$Rd, VPR128:$Rn,
6547 neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6549 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6550 ValueType MidTy, Operand StImm, Operand NaImm,
6552 def : Pat<(ResTy (vector_insert
6553 (ResTy VPR128:$src),
6554 (MidTy (vector_extract
6558 (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6559 StImm:$Immd, StImm:$Immn)>;
6561 def : Pat <(ResTy (vector_insert
6562 (ResTy VPR128:$src),
6563 (MidTy (vector_extract
6567 (INS (ResTy VPR128:$src),
6568 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6569 StImm:$Immd, NaImm:$Immn)>;
6571 def : Pat <(NaTy (vector_insert
6573 (MidTy (vector_extract
6577 (NaTy (EXTRACT_SUBREG
6579 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6581 NaImm:$Immd, StImm:$Immn)),
6584 def : Pat <(NaTy (vector_insert
6586 (MidTy (vector_extract
6590 (NaTy (EXTRACT_SUBREG
6592 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6593 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6594 NaImm:$Immd, NaImm:$Immn)),
6598 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6599 neon_uimm1_bare, INSELs>;
6600 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6601 neon_uimm0_bare, INSELd>;
6602 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6603 neon_uimm3_bare, INSELb>;
6604 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6605 neon_uimm2_bare, INSELh>;
6606 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6607 neon_uimm1_bare, INSELs>;
6608 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6609 neon_uimm0_bare, INSELd>;
6611 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6613 RegisterClass OpFPR, Operand ResImm,
6614 SubRegIndex SubIndex, Instruction INS> {
6615 def : Pat <(ResTy (vector_insert
6616 (ResTy VPR128:$src),
6619 (INS (ResTy VPR128:$src),
6620 (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6624 def : Pat <(NaTy (vector_insert
6628 (NaTy (EXTRACT_SUBREG
6630 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6631 (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6637 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6639 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6642 class NeonI_SMOV<string asmop, string Res, bit Q,
6643 ValueType OpTy, ValueType eleTy,
6644 Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6645 : NeonI_copy<Q, 0b0, 0b0101,
6646 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6647 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6648 [(set (ResTy ResGPR:$Rd),
6650 (ResTy (vector_extract
6651 (OpTy VPR128:$Rn), (OpImm:$Imm))),
6657 //Signed integer move (main, from element)
6658 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6660 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6662 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6664 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6666 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6668 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6670 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6672 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6674 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6676 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6679 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6680 ValueType eleTy, Operand StImm, Operand NaImm,
6681 Instruction SMOVI> {
6682 def : Pat<(i64 (sext_inreg
6684 (i32 (vector_extract
6685 (StTy VPR128:$Rn), (StImm:$Imm))))),
6687 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6689 def : Pat<(i64 (sext
6690 (i32 (vector_extract
6691 (StTy VPR128:$Rn), (StImm:$Imm))))),
6692 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6694 def : Pat<(i64 (sext_inreg
6695 (i64 (vector_extract
6696 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6698 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6701 def : Pat<(i64 (sext_inreg
6703 (i32 (vector_extract
6704 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6706 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6709 def : Pat<(i64 (sext
6710 (i32 (vector_extract
6711 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6712 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6716 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6717 neon_uimm3_bare, SMOVxb>;
6718 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6719 neon_uimm2_bare, SMOVxh>;
6720 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6721 neon_uimm1_bare, SMOVxs>;
6723 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6724 ValueType eleTy, Operand StImm, Operand NaImm,
6726 : Pat<(i32 (sext_inreg
6727 (i32 (vector_extract
6728 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6730 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6733 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6734 neon_uimm3_bare, SMOVwb>;
6735 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6736 neon_uimm2_bare, SMOVwh>;
6738 class NeonI_UMOV<string asmop, string Res, bit Q,
6739 ValueType OpTy, Operand OpImm,
6740 RegisterClass ResGPR, ValueType ResTy>
6741 : NeonI_copy<Q, 0b0, 0b0111,
6742 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6743 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6744 [(set (ResTy ResGPR:$Rd),
6745 (ResTy (vector_extract
6746 (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6751 //Unsigned integer move (main, from element)
6752 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6754 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6756 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6758 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6760 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6762 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6764 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6766 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6769 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6770 (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6771 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6772 (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6774 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6775 Operand StImm, Operand NaImm,
6777 : Pat<(ResTy (vector_extract
6778 (NaTy VPR64:$Rn), NaImm:$Imm)),
6779 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6782 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6783 neon_uimm3_bare, UMOVwb>;
6784 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6785 neon_uimm2_bare, UMOVwh>;
6786 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6787 neon_uimm1_bare, UMOVws>;
6790 (i32 (vector_extract
6791 (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6793 (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6796 (i32 (vector_extract
6797 (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6799 (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6801 def : Pat<(i64 (zext
6802 (i32 (vector_extract
6803 (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6804 (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6807 (i32 (vector_extract
6808 (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6810 (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6811 neon_uimm3_bare:$Imm)>;
6814 (i32 (vector_extract
6815 (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6817 (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6818 neon_uimm2_bare:$Imm)>;
6820 def : Pat<(i64 (zext
6821 (i32 (vector_extract
6822 (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6823 (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6824 neon_uimm0_bare:$Imm)>;
6826 // Additional copy patterns for scalar types
6827 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6829 (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6831 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6833 (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6835 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6836 (FMOVws FPR32:$Rn)>;
6838 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6839 (FMOVxd FPR64:$Rn)>;
6841 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6844 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6845 (v1i8 (EXTRACT_SUBREG (v16i8
6846 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6849 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6850 (v1i16 (EXTRACT_SUBREG (v8i16
6851 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6854 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6857 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6860 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
6861 (v8i8 (EXTRACT_SUBREG (v16i8
6862 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6865 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
6866 (v4i16 (EXTRACT_SUBREG (v8i16
6867 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6870 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6871 (v2i32 (EXTRACT_SUBREG (v16i8
6872 (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6875 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
6876 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6878 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
6879 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6881 def : Pat<(v4i32 (scalar_to_vector GPR32:$Rn)),
6882 (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6884 def : Pat<(v2i64 (scalar_to_vector GPR64:$Rn)),
6885 (INSdx (v2i64 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6887 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6888 (v2i32 (EXTRACT_SUBREG (v16i8
6889 (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6892 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6893 (v2i32 (EXTRACT_SUBREG (v16i8
6894 (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6897 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6900 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6901 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6902 (f64 FPR64:$src), sub_64)>;
6904 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane, string rnlane,
6905 RegisterOperand ResVPR, Operand OpImm>
6906 : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6907 (ins VPR128:$Rn, OpImm:$Imm),
6908 asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6914 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6916 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6919 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6921 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6924 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6926 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6929 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6931 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6934 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6936 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6939 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6941 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6944 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6946 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6949 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6950 ValueType OpTy,ValueType NaTy,
6951 ValueType ExTy, Operand OpLImm,
6953 def : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6954 (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6956 def : Pat<(ResTy (Neon_vduplane
6957 (NaTy VPR64:$Rn), OpNImm:$Imm)),
6959 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6961 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6962 neon_uimm4_bare, neon_uimm3_bare>;
6963 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6964 neon_uimm4_bare, neon_uimm3_bare>;
6965 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6966 neon_uimm3_bare, neon_uimm2_bare>;
6967 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6968 neon_uimm3_bare, neon_uimm2_bare>;
6969 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6970 neon_uimm2_bare, neon_uimm1_bare>;
6971 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6972 neon_uimm2_bare, neon_uimm1_bare>;
6973 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6974 neon_uimm1_bare, neon_uimm0_bare>;
6975 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6976 neon_uimm2_bare, neon_uimm1_bare>;
6977 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6978 neon_uimm2_bare, neon_uimm1_bare>;
6979 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6980 neon_uimm1_bare, neon_uimm0_bare>;
6982 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6984 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6986 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6988 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6990 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
6992 (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
6995 class NeonI_DUP<bit Q, string asmop, string rdlane,
6996 RegisterOperand ResVPR, ValueType ResTy,
6997 RegisterClass OpGPR, ValueType OpTy>
6998 : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
6999 asmop # "\t$Rd" # rdlane # ", $Rn",
7000 [(set (ResTy ResVPR:$Rd),
7001 (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
7004 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
7005 let Inst{20-16} = 0b00001;
7006 // bits 17-20 are unspecified, but should be set to zero.
7009 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
7010 let Inst{20-16} = 0b00010;
7011 // bits 18-20 are unspecified, but should be set to zero.
7014 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
7015 let Inst{20-16} = 0b00100;
7016 // bits 19-20 are unspecified, but should be set to zero.
7019 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
7020 let Inst{20-16} = 0b01000;
7021 // bit 20 is unspecified, but should be set to zero.
7024 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
7025 let Inst{20-16} = 0b00001;
7026 // bits 17-20 are unspecified, but should be set to zero.
7029 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
7030 let Inst{20-16} = 0b00010;
7031 // bits 18-20 are unspecified, but should be set to zero.
7034 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
7035 let Inst{20-16} = 0b00100;
7036 // bits 19-20 are unspecified, but should be set to zero.
7039 // patterns for CONCAT_VECTORS
7040 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
7041 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
7042 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
7043 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
7045 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7046 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
7049 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
7051 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7055 defm : Concat_Vector_Pattern<v16i8, v8i8>;
7056 defm : Concat_Vector_Pattern<v8i16, v4i16>;
7057 defm : Concat_Vector_Pattern<v4i32, v2i32>;
7058 defm : Concat_Vector_Pattern<v2i64, v1i64>;
7059 defm : Concat_Vector_Pattern<v4f32, v2f32>;
7060 defm : Concat_Vector_Pattern<v2f64, v1f64>;
7062 //patterns for EXTRACT_SUBVECTOR
7063 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
7064 (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7065 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
7066 (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7067 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
7068 (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7069 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
7070 (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7071 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
7072 (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7073 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
7074 (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7076 // The followings are for instruction class (3V Elem)
7080 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
7081 string asmop, string ResS, string OpS, string EleOpS,
7082 Operand OpImm, RegisterOperand ResVPR,
7083 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7084 : NeonI_2VElem<q, u, size, opcode,
7085 (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
7086 EleOpVPR:$Re, OpImm:$Index),
7087 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7088 ", $Re." # EleOpS # "[$Index]",
7094 let Constraints = "$src = $Rd";
7097 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
7098 // vector register class for element is always 128-bit to cover the max index
7099 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7100 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7101 let Inst{11} = {Index{1}};
7102 let Inst{21} = {Index{0}};
7103 let Inst{20-16} = Re;
7106 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7107 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7108 let Inst{11} = {Index{1}};
7109 let Inst{21} = {Index{0}};
7110 let Inst{20-16} = Re;
7113 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7114 def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7115 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7116 let Inst{11} = {Index{2}};
7117 let Inst{21} = {Index{1}};
7118 let Inst{20} = {Index{0}};
7119 let Inst{19-16} = Re{3-0};
7122 def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7123 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7124 let Inst{11} = {Index{2}};
7125 let Inst{21} = {Index{1}};
7126 let Inst{20} = {Index{0}};
7127 let Inst{19-16} = Re{3-0};
7131 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
7132 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
7134 // Pattern for lane in 128-bit vector
7135 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7136 RegisterOperand ResVPR, RegisterOperand OpVPR,
7137 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
7139 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
7140 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7141 (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7143 // Pattern for lane in 64-bit vector
7144 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7145 RegisterOperand ResVPR, RegisterOperand OpVPR,
7146 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
7148 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
7149 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7150 (INST ResVPR:$src, OpVPR:$Rn,
7151 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7153 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
7155 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7156 op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
7158 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7159 op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
7161 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7162 op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7164 def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7165 op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7167 // Index can only be half of the max value for lane in 64-bit vector
7169 def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7170 op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
7172 def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7173 op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7176 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
7177 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
7179 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
7180 string asmop, string ResS, string OpS, string EleOpS,
7181 Operand OpImm, RegisterOperand ResVPR,
7182 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7183 : NeonI_2VElem<q, u, size, opcode,
7184 (outs ResVPR:$Rd), (ins OpVPR:$Rn,
7185 EleOpVPR:$Re, OpImm:$Index),
7186 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7187 ", $Re." # EleOpS # "[$Index]",
7194 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
7195 // vector register class for element is always 128-bit to cover the max index
7196 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7197 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7198 let Inst{11} = {Index{1}};
7199 let Inst{21} = {Index{0}};
7200 let Inst{20-16} = Re;
7203 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7204 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7205 let Inst{11} = {Index{1}};
7206 let Inst{21} = {Index{0}};
7207 let Inst{20-16} = Re;
7210 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7211 def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7212 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7213 let Inst{11} = {Index{2}};
7214 let Inst{21} = {Index{1}};
7215 let Inst{20} = {Index{0}};
7216 let Inst{19-16} = Re{3-0};
7219 def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7220 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7221 let Inst{11} = {Index{2}};
7222 let Inst{21} = {Index{1}};
7223 let Inst{20} = {Index{0}};
7224 let Inst{19-16} = Re{3-0};
7228 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
7229 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
7230 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
7232 // Pattern for lane in 128-bit vector
7233 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7234 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7235 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7236 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7237 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7238 (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7240 // Pattern for lane in 64-bit vector
7241 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7242 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7243 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7244 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7245 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7247 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7249 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
7250 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7251 op, VPR64, VPR128, v2i32, v2i32, v4i32>;
7253 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7254 op, VPR128, VPR128, v4i32, v4i32, v4i32>;
7256 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7257 op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7259 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7260 op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7262 // Index can only be half of the max value for lane in 64-bit vector
7264 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7265 op, VPR64, VPR64, v2i32, v2i32, v2i32>;
7267 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7268 op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7271 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
7272 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
7273 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
7277 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
7278 // vector register class for element is always 128-bit to cover the max index
7279 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7280 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7281 let Inst{11} = {Index{1}};
7282 let Inst{21} = {Index{0}};
7283 let Inst{20-16} = Re;
7286 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7287 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7288 let Inst{11} = {Index{1}};
7289 let Inst{21} = {Index{0}};
7290 let Inst{20-16} = Re;
7293 // _1d2d doesn't exist!
7295 def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7296 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7297 let Inst{11} = {Index{0}};
7299 let Inst{20-16} = Re;
7303 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
7304 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
7306 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
7307 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7308 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
7309 SDPatternOperator coreop>
7310 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7311 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
7313 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
7315 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
7316 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7317 op, VPR64, VPR128, v2f32, v2f32, v4f32>;
7319 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7320 op, VPR128, VPR128, v4f32, v4f32, v4f32>;
7322 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7323 op, VPR128, VPR128, v2f64, v2f64, v2f64>;
7325 // Index can only be half of the max value for lane in 64-bit vector
7327 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7328 op, VPR64, VPR64, v2f32, v2f32, v2f32>;
7330 def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7331 op, VPR128, VPR64, v2f64, v2f64, v1f64,
7332 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7335 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
7336 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
7338 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
7339 (v2f32 VPR64:$Rn))),
7340 (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7342 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
7343 (v4f32 VPR128:$Rn))),
7344 (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7346 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
7347 (v2f64 VPR128:$Rn))),
7348 (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7350 // The followings are patterns using fma
7351 // -ffp-contract=fast generates fma
7353 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7354 // vector register class for element is always 128-bit to cover the max index
7355 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7356 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7357 let Inst{11} = {Index{1}};
7358 let Inst{21} = {Index{0}};
7359 let Inst{20-16} = Re;
7362 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7363 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7364 let Inst{11} = {Index{1}};
7365 let Inst{21} = {Index{0}};
7366 let Inst{20-16} = Re;
7369 // _1d2d doesn't exist!
7371 def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7372 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7373 let Inst{11} = {Index{0}};
7375 let Inst{20-16} = Re;
7379 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7380 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7382 // Pattern for lane in 128-bit vector
7383 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7384 RegisterOperand ResVPR, RegisterOperand OpVPR,
7385 ValueType ResTy, ValueType OpTy,
7386 SDPatternOperator coreop>
7387 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7388 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7389 (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7391 // Pattern for lane 0
7392 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7393 RegisterOperand ResVPR, ValueType ResTy>
7394 : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7395 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7396 (ResTy ResVPR:$src))),
7397 (INST ResVPR:$src, ResVPR:$Rn,
7398 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7400 // Pattern for lane in 64-bit vector
7401 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7402 RegisterOperand ResVPR, RegisterOperand OpVPR,
7403 ValueType ResTy, ValueType OpTy,
7404 SDPatternOperator coreop>
7405 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7406 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7407 (INST ResVPR:$src, ResVPR:$Rn,
7408 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7410 // Pattern for lane in 64-bit vector
7411 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7412 SDPatternOperator op,
7413 RegisterOperand ResVPR, RegisterOperand OpVPR,
7414 ValueType ResTy, ValueType OpTy,
7415 SDPatternOperator coreop>
7416 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7417 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7418 (INST ResVPR:$src, ResVPR:$Rn,
7419 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7422 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7423 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7424 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7425 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7427 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7430 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7431 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7432 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7434 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7437 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7438 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7439 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7441 // Index can only be half of the max value for lane in 64-bit vector
7443 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7444 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7445 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7447 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7448 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7449 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7452 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7454 // Pattern for lane 0
7455 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7456 RegisterOperand ResVPR, ValueType ResTy>
7457 : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7458 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7459 (ResTy ResVPR:$src))),
7460 (INST ResVPR:$src, ResVPR:$Rn,
7461 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7463 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7465 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7466 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7467 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7469 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7470 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7471 BinOpFrag<(Neon_vduplane
7472 (fneg node:$LHS), node:$RHS)>>;
7474 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7477 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7478 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7479 BinOpFrag<(fneg (Neon_vduplane
7480 node:$LHS, node:$RHS))>>;
7482 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7483 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7484 BinOpFrag<(Neon_vduplane
7485 (fneg node:$LHS), node:$RHS)>>;
7487 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7490 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7491 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7492 BinOpFrag<(fneg (Neon_vduplane
7493 node:$LHS, node:$RHS))>>;
7495 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7496 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7497 BinOpFrag<(Neon_vduplane
7498 (fneg node:$LHS), node:$RHS)>>;
7500 // Index can only be half of the max value for lane in 64-bit vector
7502 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7503 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7504 BinOpFrag<(fneg (Neon_vduplane
7505 node:$LHS, node:$RHS))>>;
7507 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7508 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7509 BinOpFrag<(Neon_vduplane
7510 (fneg node:$LHS), node:$RHS)>>;
7512 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7513 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7514 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7516 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7517 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7518 BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7520 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7521 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7522 BinOpFrag<(fneg (Neon_combine_2d
7523 node:$LHS, node:$RHS))>>;
7525 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7526 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7527 BinOpFrag<(Neon_combine_2d
7528 (fneg node:$LHS), (fneg node:$RHS))>>;
7531 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7533 // Variant 3: Long type
7534 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7535 // SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7537 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7538 // vector register class for element is always 128-bit to cover the max index
7539 def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7540 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7541 let Inst{11} = {Index{1}};
7542 let Inst{21} = {Index{0}};
7543 let Inst{20-16} = Re;
7546 def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7547 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7548 let Inst{11} = {Index{1}};
7549 let Inst{21} = {Index{0}};
7550 let Inst{20-16} = Re;
7553 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7554 def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7555 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7556 let Inst{11} = {Index{2}};
7557 let Inst{21} = {Index{1}};
7558 let Inst{20} = {Index{0}};
7559 let Inst{19-16} = Re{3-0};
7562 def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7563 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7564 let Inst{11} = {Index{2}};
7565 let Inst{21} = {Index{1}};
7566 let Inst{20} = {Index{0}};
7567 let Inst{19-16} = Re{3-0};
7571 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7572 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7573 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7574 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7575 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7576 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7578 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7579 // vector register class for element is always 128-bit to cover the max index
7580 def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7581 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7582 let Inst{11} = {Index{1}};
7583 let Inst{21} = {Index{0}};
7584 let Inst{20-16} = Re;
7587 def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7588 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7589 let Inst{11} = {Index{1}};
7590 let Inst{21} = {Index{0}};
7591 let Inst{20-16} = Re;
7594 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7595 def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7596 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7597 let Inst{11} = {Index{2}};
7598 let Inst{21} = {Index{1}};
7599 let Inst{20} = {Index{0}};
7600 let Inst{19-16} = Re{3-0};
7603 def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7604 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7605 let Inst{11} = {Index{2}};
7606 let Inst{21} = {Index{1}};
7607 let Inst{20} = {Index{0}};
7608 let Inst{19-16} = Re{3-0};
7612 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7613 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7614 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7616 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7619 // Pattern for lane in 128-bit vector
7620 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7621 RegisterOperand EleOpVPR, ValueType ResTy,
7622 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7623 SDPatternOperator hiop>
7624 : Pat<(ResTy (op (ResTy VPR128:$src),
7625 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7626 (HalfOpTy (Neon_vduplane
7627 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7628 (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7630 // Pattern for lane in 64-bit vector
7631 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7632 RegisterOperand EleOpVPR, ValueType ResTy,
7633 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7634 SDPatternOperator hiop>
7635 : Pat<(ResTy (op (ResTy VPR128:$src),
7636 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7637 (HalfOpTy (Neon_vduplane
7638 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7639 (INST VPR128:$src, VPR128:$Rn,
7640 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7642 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7643 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7644 SDPatternOperator hiop, Instruction DupInst>
7645 : Pat<(ResTy (op (ResTy VPR128:$src),
7646 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7647 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7648 (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7650 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7651 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7652 op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7654 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7655 op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7657 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7658 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7660 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7661 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7663 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7664 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7666 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7667 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7669 // Index can only be half of the max value for lane in 64-bit vector
7671 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7672 op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7674 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7675 op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7677 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7678 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7680 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7681 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7684 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7685 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7686 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7687 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7689 // Pattern for lane in 128-bit vector
7690 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7691 RegisterOperand EleOpVPR, ValueType ResTy,
7692 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7693 SDPatternOperator hiop>
7695 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7696 (HalfOpTy (Neon_vduplane
7697 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7698 (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7700 // Pattern for lane in 64-bit vector
7701 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7702 RegisterOperand EleOpVPR, ValueType ResTy,
7703 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7704 SDPatternOperator hiop>
7706 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7707 (HalfOpTy (Neon_vduplane
7708 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7710 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7712 // Pattern for fixed lane 0
7713 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7714 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7715 SDPatternOperator hiop, Instruction DupInst>
7717 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7718 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7719 (INST VPR128:$Rn, (DupInst $Re), 0)>;
7721 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7722 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7723 op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7725 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7726 op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7728 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7729 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7731 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7732 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7734 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7735 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7737 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7738 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7740 // Index can only be half of the max value for lane in 64-bit vector
7742 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7743 op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7745 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7746 op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7748 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7749 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7751 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7752 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7755 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7756 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7757 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7759 multiclass NI_qdma<SDPatternOperator op> {
7760 def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7762 (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7764 def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7766 (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7769 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7770 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7772 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7773 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7774 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7775 v4i32, v4i16, v8i16>;
7777 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7778 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7779 v2i64, v2i32, v4i32>;
7781 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7782 !cast<PatFrag>(op # "_4s"), VPR128Lo,
7783 v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7785 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7786 !cast<PatFrag>(op # "_2d"), VPR128,
7787 v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7789 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7790 !cast<PatFrag>(op # "_4s"),
7791 v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7793 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7794 !cast<PatFrag>(op # "_2d"),
7795 v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7797 // Index can only be half of the max value for lane in 64-bit vector
7799 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7800 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7801 v4i32, v4i16, v4i16>;
7803 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7804 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7805 v2i64, v2i32, v2i32>;
7807 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7808 !cast<PatFrag>(op # "_4s"), VPR64Lo,
7809 v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7811 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7812 !cast<PatFrag>(op # "_2d"), VPR64,
7813 v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7816 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7817 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7819 // End of implementation for instruction class (3V Elem)
7821 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7822 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7823 SDPatternOperator Neon_Rev>
7824 : NeonI_2VMisc<Q, U, size, opcode,
7825 (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7826 asmop # "\t$Rd." # Res # ", $Rn." # Res,
7827 [(set (ResTy ResVPR:$Rd),
7828 (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7831 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7833 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7835 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7837 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7839 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7841 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7844 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7845 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7847 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7849 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7851 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7853 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7856 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7858 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7861 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7862 SDPatternOperator Neon_Padd> {
7863 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7864 (outs VPR128:$Rd), (ins VPR128:$Rn),
7865 asmop # "\t$Rd.8h, $Rn.16b",
7866 [(set (v8i16 VPR128:$Rd),
7867 (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7870 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7871 (outs VPR64:$Rd), (ins VPR64:$Rn),
7872 asmop # "\t$Rd.4h, $Rn.8b",
7873 [(set (v4i16 VPR64:$Rd),
7874 (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7877 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7878 (outs VPR128:$Rd), (ins VPR128:$Rn),
7879 asmop # "\t$Rd.4s, $Rn.8h",
7880 [(set (v4i32 VPR128:$Rd),
7881 (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7884 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7885 (outs VPR64:$Rd), (ins VPR64:$Rn),
7886 asmop # "\t$Rd.2s, $Rn.4h",
7887 [(set (v2i32 VPR64:$Rd),
7888 (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7891 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7892 (outs VPR128:$Rd), (ins VPR128:$Rn),
7893 asmop # "\t$Rd.2d, $Rn.4s",
7894 [(set (v2i64 VPR128:$Rd),
7895 (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7898 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7899 (outs VPR64:$Rd), (ins VPR64:$Rn),
7900 asmop # "\t$Rd.1d, $Rn.2s",
7901 [(set (v1i64 VPR64:$Rd),
7902 (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7906 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7907 int_arm_neon_vpaddls>;
7908 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7909 int_arm_neon_vpaddlu>;
7911 def : Pat<(v1i64 (int_aarch64_neon_saddlv (v2i32 VPR64:$Rn))),
7913 def : Pat<(v1i64 (int_aarch64_neon_uaddlv (v2i32 VPR64:$Rn))),
7916 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7917 SDPatternOperator Neon_Padd> {
7918 let Constraints = "$src = $Rd" in {
7919 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7920 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7921 asmop # "\t$Rd.8h, $Rn.16b",
7922 [(set (v8i16 VPR128:$Rd),
7924 (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7927 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7928 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7929 asmop # "\t$Rd.4h, $Rn.8b",
7930 [(set (v4i16 VPR64:$Rd),
7932 (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7935 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7936 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7937 asmop # "\t$Rd.4s, $Rn.8h",
7938 [(set (v4i32 VPR128:$Rd),
7940 (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7943 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7944 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7945 asmop # "\t$Rd.2s, $Rn.4h",
7946 [(set (v2i32 VPR64:$Rd),
7948 (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7951 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7952 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7953 asmop # "\t$Rd.2d, $Rn.4s",
7954 [(set (v2i64 VPR128:$Rd),
7956 (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7959 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7960 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7961 asmop # "\t$Rd.1d, $Rn.2s",
7962 [(set (v1i64 VPR64:$Rd),
7964 (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7969 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7970 int_arm_neon_vpadals>;
7971 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7972 int_arm_neon_vpadalu>;
7974 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7975 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7976 (outs VPR128:$Rd), (ins VPR128:$Rn),
7977 asmop # "\t$Rd.16b, $Rn.16b",
7980 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7981 (outs VPR128:$Rd), (ins VPR128:$Rn),
7982 asmop # "\t$Rd.8h, $Rn.8h",
7985 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7986 (outs VPR128:$Rd), (ins VPR128:$Rn),
7987 asmop # "\t$Rd.4s, $Rn.4s",
7990 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7991 (outs VPR128:$Rd), (ins VPR128:$Rn),
7992 asmop # "\t$Rd.2d, $Rn.2d",
7995 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7996 (outs VPR64:$Rd), (ins VPR64:$Rn),
7997 asmop # "\t$Rd.8b, $Rn.8b",
8000 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8001 (outs VPR64:$Rd), (ins VPR64:$Rn),
8002 asmop # "\t$Rd.4h, $Rn.4h",
8005 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8006 (outs VPR64:$Rd), (ins VPR64:$Rn),
8007 asmop # "\t$Rd.2s, $Rn.2s",
8011 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
8012 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
8013 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
8014 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
8016 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
8017 SDPatternOperator Neon_Op> {
8018 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
8019 (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
8021 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
8022 (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
8024 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
8025 (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
8027 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
8028 (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
8030 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
8031 (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
8033 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
8034 (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
8036 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
8037 (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
8040 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
8041 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
8042 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
8044 def : Pat<(v16i8 (sub
8045 (v16i8 Neon_AllZero),
8046 (v16i8 VPR128:$Rn))),
8047 (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
8048 def : Pat<(v8i8 (sub
8049 (v8i8 Neon_AllZero),
8051 (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
8052 def : Pat<(v8i16 (sub
8053 (v8i16 (bitconvert (v16i8 Neon_AllZero))),
8054 (v8i16 VPR128:$Rn))),
8055 (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
8056 def : Pat<(v4i16 (sub
8057 (v4i16 (bitconvert (v8i8 Neon_AllZero))),
8058 (v4i16 VPR64:$Rn))),
8059 (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
8060 def : Pat<(v4i32 (sub
8061 (v4i32 (bitconvert (v16i8 Neon_AllZero))),
8062 (v4i32 VPR128:$Rn))),
8063 (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
8064 def : Pat<(v2i32 (sub
8065 (v2i32 (bitconvert (v8i8 Neon_AllZero))),
8066 (v2i32 VPR64:$Rn))),
8067 (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
8068 def : Pat<(v2i64 (sub
8069 (v2i64 (bitconvert (v16i8 Neon_AllZero))),
8070 (v2i64 VPR128:$Rn))),
8071 (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
8073 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
8074 let Constraints = "$src = $Rd" in {
8075 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8076 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8077 asmop # "\t$Rd.16b, $Rn.16b",
8080 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8081 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8082 asmop # "\t$Rd.8h, $Rn.8h",
8085 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8086 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8087 asmop # "\t$Rd.4s, $Rn.4s",
8090 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8091 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8092 asmop # "\t$Rd.2d, $Rn.2d",
8095 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8096 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8097 asmop # "\t$Rd.8b, $Rn.8b",
8100 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8101 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8102 asmop # "\t$Rd.4h, $Rn.4h",
8105 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8106 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8107 asmop # "\t$Rd.2s, $Rn.2s",
8112 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
8113 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
8115 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
8116 SDPatternOperator Neon_Op> {
8117 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
8118 (v16i8 (!cast<Instruction>(Prefix # 16b)
8119 (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
8121 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
8122 (v8i16 (!cast<Instruction>(Prefix # 8h)
8123 (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
8125 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
8126 (v4i32 (!cast<Instruction>(Prefix # 4s)
8127 (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
8129 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
8130 (v2i64 (!cast<Instruction>(Prefix # 2d)
8131 (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
8133 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
8134 (v8i8 (!cast<Instruction>(Prefix # 8b)
8135 (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
8137 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
8138 (v4i16 (!cast<Instruction>(Prefix # 4h)
8139 (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
8141 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
8142 (v2i32 (!cast<Instruction>(Prefix # 2s)
8143 (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
8146 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
8147 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
8149 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
8150 SDPatternOperator Neon_Op> {
8151 def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
8152 (outs VPR128:$Rd), (ins VPR128:$Rn),
8153 asmop # "\t$Rd.16b, $Rn.16b",
8154 [(set (v16i8 VPR128:$Rd),
8155 (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
8158 def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
8159 (outs VPR128:$Rd), (ins VPR128:$Rn),
8160 asmop # "\t$Rd.8h, $Rn.8h",
8161 [(set (v8i16 VPR128:$Rd),
8162 (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
8165 def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
8166 (outs VPR128:$Rd), (ins VPR128:$Rn),
8167 asmop # "\t$Rd.4s, $Rn.4s",
8168 [(set (v4i32 VPR128:$Rd),
8169 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8172 def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
8173 (outs VPR64:$Rd), (ins VPR64:$Rn),
8174 asmop # "\t$Rd.8b, $Rn.8b",
8175 [(set (v8i8 VPR64:$Rd),
8176 (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
8179 def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
8180 (outs VPR64:$Rd), (ins VPR64:$Rn),
8181 asmop # "\t$Rd.4h, $Rn.4h",
8182 [(set (v4i16 VPR64:$Rd),
8183 (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
8186 def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
8187 (outs VPR64:$Rd), (ins VPR64:$Rn),
8188 asmop # "\t$Rd.2s, $Rn.2s",
8189 [(set (v2i32 VPR64:$Rd),
8190 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8194 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
8195 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
8197 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
8199 def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
8200 (outs VPR128:$Rd), (ins VPR128:$Rn),
8201 asmop # "\t$Rd.16b, $Rn.16b",
8204 def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
8205 (outs VPR64:$Rd), (ins VPR64:$Rn),
8206 asmop # "\t$Rd.8b, $Rn.8b",
8210 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
8211 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
8212 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
8214 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
8215 (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
8216 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
8217 (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
8219 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
8220 (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
8221 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
8222 (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
8224 def : Pat<(v16i8 (xor
8226 (v16i8 Neon_AllOne))),
8227 (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
8228 def : Pat<(v8i8 (xor
8230 (v8i8 Neon_AllOne))),
8231 (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
8232 def : Pat<(v8i16 (xor
8234 (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
8235 (NOT16b VPR128:$Rn)>;
8236 def : Pat<(v4i16 (xor
8238 (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
8240 def : Pat<(v4i32 (xor
8242 (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
8243 (NOT16b VPR128:$Rn)>;
8244 def : Pat<(v2i32 (xor
8246 (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
8248 def : Pat<(v2i64 (xor
8250 (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
8251 (NOT16b VPR128:$Rn)>;
8253 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
8254 (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
8255 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
8256 (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
8258 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
8259 SDPatternOperator Neon_Op> {
8260 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8261 (outs VPR128:$Rd), (ins VPR128:$Rn),
8262 asmop # "\t$Rd.4s, $Rn.4s",
8263 [(set (v4f32 VPR128:$Rd),
8264 (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
8267 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8268 (outs VPR128:$Rd), (ins VPR128:$Rn),
8269 asmop # "\t$Rd.2d, $Rn.2d",
8270 [(set (v2f64 VPR128:$Rd),
8271 (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
8274 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8275 (outs VPR64:$Rd), (ins VPR64:$Rn),
8276 asmop # "\t$Rd.2s, $Rn.2s",
8277 [(set (v2f32 VPR64:$Rd),
8278 (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
8282 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
8283 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
8285 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
8286 def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8287 (outs VPR64:$Rd), (ins VPR128:$Rn),
8288 asmop # "\t$Rd.8b, $Rn.8h",
8291 def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8292 (outs VPR64:$Rd), (ins VPR128:$Rn),
8293 asmop # "\t$Rd.4h, $Rn.4s",
8296 def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8297 (outs VPR64:$Rd), (ins VPR128:$Rn),
8298 asmop # "\t$Rd.2s, $Rn.2d",
8301 let Constraints = "$Rd = $src" in {
8302 def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8303 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8304 asmop # "2\t$Rd.16b, $Rn.8h",
8307 def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8308 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8309 asmop # "2\t$Rd.8h, $Rn.4s",
8312 def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8313 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8314 asmop # "2\t$Rd.4s, $Rn.2d",
8319 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
8320 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
8321 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
8322 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
8324 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
8325 SDPatternOperator Neon_Op> {
8326 def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8327 (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8329 def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8330 (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8332 def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8333 (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8335 def : Pat<(v16i8 (concat_vectors
8337 (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8338 (!cast<Instruction>(Prefix # 8h16b)
8339 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8342 def : Pat<(v8i16 (concat_vectors
8344 (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8345 (!cast<Instruction>(Prefix # 4s8h)
8346 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8349 def : Pat<(v4i32 (concat_vectors
8351 (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8352 (!cast<Instruction>(Prefix # 2d4s)
8353 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8357 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8358 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8359 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8360 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8362 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8363 let DecoderMethod = "DecodeSHLLInstruction" in {
8364 def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8366 (ins VPR64:$Rn, uimm_exact8:$Imm),
8367 asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8370 def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8372 (ins VPR64:$Rn, uimm_exact16:$Imm),
8373 asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8376 def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8378 (ins VPR64:$Rn, uimm_exact32:$Imm),
8379 asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8382 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8384 (ins VPR128:$Rn, uimm_exact8:$Imm),
8385 asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8388 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8390 (ins VPR128:$Rn, uimm_exact16:$Imm),
8391 asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8394 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8396 (ins VPR128:$Rn, uimm_exact32:$Imm),
8397 asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8402 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8404 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8405 SDPatternOperator ExtOp, Operand Neon_Imm,
8408 (DesTy (ExtOp (OpTy VPR64:$Rn))),
8410 (i32 Neon_Imm:$Imm))))),
8411 (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8413 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8414 SDPatternOperator ExtOp, Operand Neon_Imm,
8415 string suffix, PatFrag GetHigh>
8418 (OpTy (GetHigh VPR128:$Rn)))),
8420 (i32 Neon_Imm:$Imm))))),
8421 (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8423 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8424 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8425 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8426 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8427 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8428 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8429 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8431 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8433 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8435 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8437 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8439 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8442 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8443 def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8444 (outs VPR64:$Rd), (ins VPR128:$Rn),
8445 asmop # "\t$Rd.4h, $Rn.4s",
8448 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8449 (outs VPR64:$Rd), (ins VPR128:$Rn),
8450 asmop # "\t$Rd.2s, $Rn.2d",
8453 let Constraints = "$src = $Rd" in {
8454 def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8455 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8456 asmop # "2\t$Rd.8h, $Rn.4s",
8459 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8460 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8461 asmop # "2\t$Rd.4s, $Rn.2d",
8466 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8468 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8469 SDPatternOperator f32_to_f16_Op,
8470 SDPatternOperator f64_to_f32_Op> {
8472 def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8473 (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8475 def : Pat<(v8i16 (concat_vectors
8477 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8478 (!cast<Instruction>(prefix # "4s8h")
8479 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8480 (v4f32 VPR128:$Rn))>;
8482 def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8483 (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8485 def : Pat<(v4f32 (concat_vectors
8487 (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8488 (!cast<Instruction>(prefix # "2d4s")
8489 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8490 (v2f64 VPR128:$Rn))>;
8493 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8495 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8497 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8498 (outs VPR64:$Rd), (ins VPR128:$Rn),
8499 asmop # "\t$Rd.2s, $Rn.2d",
8502 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8503 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8504 asmop # "2\t$Rd.4s, $Rn.2d",
8506 let Constraints = "$src = $Rd";
8509 def : Pat<(v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))),
8510 (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8512 def : Pat<(v4f32 (concat_vectors
8514 (v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))))),
8515 (!cast<Instruction>(prefix # "2d4s")
8516 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8520 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8522 def Neon_High4Float : PatFrag<(ops node:$in),
8523 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8525 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8526 def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8527 (outs VPR128:$Rd), (ins VPR64:$Rn),
8528 asmop # "\t$Rd.4s, $Rn.4h",
8531 def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8532 (outs VPR128:$Rd), (ins VPR64:$Rn),
8533 asmop # "\t$Rd.2d, $Rn.2s",
8536 def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8537 (outs VPR128:$Rd), (ins VPR128:$Rn),
8538 asmop # "2\t$Rd.4s, $Rn.8h",
8541 def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8542 (outs VPR128:$Rd), (ins VPR128:$Rn),
8543 asmop # "2\t$Rd.2d, $Rn.4s",
8547 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8549 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8550 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8551 (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8553 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8555 (v8i16 VPR128:$Rn))))),
8556 (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8558 def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8559 (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8561 def : Pat<(v2f64 (fextend
8562 (v2f32 (Neon_High4Float
8563 (v4f32 VPR128:$Rn))))),
8564 (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8567 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8569 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8570 ValueType ResTy4s, ValueType OpTy4s,
8571 ValueType ResTy2d, ValueType OpTy2d,
8572 ValueType ResTy2s, ValueType OpTy2s,
8573 SDPatternOperator Neon_Op> {
8575 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8576 (outs VPR128:$Rd), (ins VPR128:$Rn),
8577 asmop # "\t$Rd.4s, $Rn.4s",
8578 [(set (ResTy4s VPR128:$Rd),
8579 (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8582 def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8583 (outs VPR128:$Rd), (ins VPR128:$Rn),
8584 asmop # "\t$Rd.2d, $Rn.2d",
8585 [(set (ResTy2d VPR128:$Rd),
8586 (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8589 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8590 (outs VPR64:$Rd), (ins VPR64:$Rn),
8591 asmop # "\t$Rd.2s, $Rn.2s",
8592 [(set (ResTy2s VPR64:$Rd),
8593 (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8597 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8598 bits<5> opcode, SDPatternOperator Neon_Op> {
8599 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8600 v2f64, v2i32, v2f32, Neon_Op>;
8603 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8604 int_arm_neon_vcvtns>;
8605 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8606 int_arm_neon_vcvtnu>;
8607 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8608 int_arm_neon_vcvtps>;
8609 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8610 int_arm_neon_vcvtpu>;
8611 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8612 int_arm_neon_vcvtms>;
8613 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8614 int_arm_neon_vcvtmu>;
8615 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8616 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8617 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8618 int_arm_neon_vcvtas>;
8619 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8620 int_arm_neon_vcvtau>;
8622 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8623 bits<5> opcode, SDPatternOperator Neon_Op> {
8624 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8625 v2i64, v2f32, v2i32, Neon_Op>;
8628 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8629 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8631 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8632 bits<5> opcode, SDPatternOperator Neon_Op> {
8633 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8634 v2f64, v2f32, v2f32, Neon_Op>;
8637 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8638 int_aarch64_neon_frintn>;
8639 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8640 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8641 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8642 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8643 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8644 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8645 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8646 int_arm_neon_vrecpe>;
8647 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8648 int_arm_neon_vrsqrte>;
8649 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
8651 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8652 bits<5> opcode, SDPatternOperator Neon_Op> {
8653 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8654 (outs VPR128:$Rd), (ins VPR128:$Rn),
8655 asmop # "\t$Rd.4s, $Rn.4s",
8656 [(set (v4i32 VPR128:$Rd),
8657 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8660 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8661 (outs VPR64:$Rd), (ins VPR64:$Rn),
8662 asmop # "\t$Rd.2s, $Rn.2s",
8663 [(set (v2i32 VPR64:$Rd),
8664 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8668 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8669 int_arm_neon_vrecpe>;
8670 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8671 int_arm_neon_vrsqrte>;
8674 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8675 string asmop, SDPatternOperator opnode>
8676 : NeonI_Crypto_AES<size, opcode,
8677 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8678 asmop # "\t$Rd.16b, $Rn.16b",
8679 [(set (v16i8 VPR128:$Rd),
8680 (v16i8 (opnode (v16i8 VPR128:$src),
8681 (v16i8 VPR128:$Rn))))],
8683 let Constraints = "$src = $Rd";
8684 let Predicates = [HasNEON, HasCrypto];
8687 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8688 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8690 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8691 string asmop, SDPatternOperator opnode>
8692 : NeonI_Crypto_AES<size, opcode,
8693 (outs VPR128:$Rd), (ins VPR128:$Rn),
8694 asmop # "\t$Rd.16b, $Rn.16b",
8695 [(set (v16i8 VPR128:$Rd),
8696 (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8699 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8700 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8702 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8703 string asmop, SDPatternOperator opnode>
8704 : NeonI_Crypto_SHA<size, opcode,
8705 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8706 asmop # "\t$Rd.4s, $Rn.4s",
8707 [(set (v4i32 VPR128:$Rd),
8708 (v4i32 (opnode (v4i32 VPR128:$src),
8709 (v4i32 VPR128:$Rn))))],
8711 let Constraints = "$src = $Rd";
8712 let Predicates = [HasNEON, HasCrypto];
8715 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8716 int_arm_neon_sha1su1>;
8717 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8718 int_arm_neon_sha256su0>;
8720 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8721 string asmop, SDPatternOperator opnode>
8722 : NeonI_Crypto_SHA<size, opcode,
8723 (outs FPR32:$Rd), (ins FPR32:$Rn),
8724 asmop # "\t$Rd, $Rn",
8725 [(set (v1i32 FPR32:$Rd),
8726 (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8728 let Predicates = [HasNEON, HasCrypto];
8731 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8733 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8734 SDPatternOperator opnode>
8735 : NeonI_Crypto_3VSHA<size, opcode,
8737 (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8738 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8739 [(set (v4i32 VPR128:$Rd),
8740 (v4i32 (opnode (v4i32 VPR128:$src),
8742 (v4i32 VPR128:$Rm))))],
8744 let Constraints = "$src = $Rd";
8745 let Predicates = [HasNEON, HasCrypto];
8748 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8749 int_arm_neon_sha1su0>;
8750 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8751 int_arm_neon_sha256su1>;
8753 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8754 SDPatternOperator opnode>
8755 : NeonI_Crypto_3VSHA<size, opcode,
8757 (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8758 asmop # "\t$Rd, $Rn, $Rm.4s",
8759 [(set (v4i32 FPR128:$Rd),
8760 (v4i32 (opnode (v4i32 FPR128:$src),
8762 (v4i32 VPR128:$Rm))))],
8764 let Constraints = "$src = $Rd";
8765 let Predicates = [HasNEON, HasCrypto];
8768 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8769 int_arm_neon_sha256h>;
8770 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8771 int_arm_neon_sha256h2>;
8773 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8774 SDPatternOperator opnode>
8775 : NeonI_Crypto_3VSHA<size, opcode,
8777 (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8778 asmop # "\t$Rd, $Rn, $Rm.4s",
8779 [(set (v4i32 FPR128:$Rd),
8780 (v4i32 (opnode (v4i32 FPR128:$src),
8782 (v4i32 VPR128:$Rm))))],
8784 let Constraints = "$src = $Rd";
8785 let Predicates = [HasNEON, HasCrypto];
8788 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8789 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8790 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8792 // Additional patterns to match shl to USHL.
8793 def : Pat<(v8i8 (shl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8794 (USHLvvv_8B $Rn, $Rm)>;
8795 def : Pat<(v4i16 (shl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8796 (USHLvvv_4H $Rn, $Rm)>;
8797 def : Pat<(v2i32 (shl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8798 (USHLvvv_2S $Rn, $Rm)>;
8799 def : Pat<(v1i64 (shl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8800 (USHLddd $Rn, $Rm)>;
8801 def : Pat<(v16i8 (shl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8802 (USHLvvv_16B $Rn, $Rm)>;
8803 def : Pat<(v8i16 (shl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8804 (USHLvvv_8H $Rn, $Rm)>;
8805 def : Pat<(v4i32 (shl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8806 (USHLvvv_4S $Rn, $Rm)>;
8807 def : Pat<(v2i64 (shl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8808 (USHLvvv_2D $Rn, $Rm)>;
8810 // Additional patterns to match sra, srl.
8811 // For a vector right shift by vector, the shift amounts of SSHL/USHL are
8812 // negative. Negate the vector of shift amount first.
8813 def : Pat<(v8i8 (srl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8814 (USHLvvv_8B $Rn, (NEG8b $Rm))>;
8815 def : Pat<(v4i16 (srl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8816 (USHLvvv_4H $Rn, (NEG4h $Rm))>;
8817 def : Pat<(v2i32 (srl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8818 (USHLvvv_2S $Rn, (NEG2s $Rm))>;
8819 def : Pat<(v1i64 (srl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8820 (USHLddd $Rn, (NEGdd $Rm))>;
8821 def : Pat<(v16i8 (srl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8822 (USHLvvv_16B $Rn, (NEG16b $Rm))>;
8823 def : Pat<(v8i16 (srl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8824 (USHLvvv_8H $Rn, (NEG8h $Rm))>;
8825 def : Pat<(v4i32 (srl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8826 (USHLvvv_4S $Rn, (NEG4s $Rm))>;
8827 def : Pat<(v2i64 (srl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8828 (USHLvvv_2D $Rn, (NEG2d $Rm))>;
8830 def : Pat<(v8i8 (sra (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8831 (SSHLvvv_8B $Rn, (NEG8b $Rm))>;
8832 def : Pat<(v4i16 (sra (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8833 (SSHLvvv_4H $Rn, (NEG4h $Rm))>;
8834 def : Pat<(v2i32 (sra (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8835 (SSHLvvv_2S $Rn, (NEG2s $Rm))>;
8836 def : Pat<(v1i64 (sra (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8837 (SSHLddd $Rn, (NEGdd $Rm))>;
8838 def : Pat<(v16i8 (sra (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8839 (SSHLvvv_16B $Rn, (NEG16b $Rm))>;
8840 def : Pat<(v8i16 (sra (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8841 (SSHLvvv_8H $Rn, (NEG8h $Rm))>;
8842 def : Pat<(v4i32 (sra (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8843 (SSHLvvv_4S $Rn, (NEG4s $Rm))>;
8844 def : Pat<(v2i64 (sra (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8845 (SSHLvvv_2D $Rn, (NEG2d $Rm))>;
8848 // Patterns for handling half-precision values
8851 // Convert f16 value coming in as i16 value to f32
8852 def : Pat<(f32 (f16_to_f32 (i32 (and (i32 GPR32:$Rn), 65535)))),
8853 (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8854 def : Pat<(f32 (f16_to_f32 (i32 (assertzext GPR32:$Rn)))),
8855 (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8857 def : Pat<(f32 (f16_to_f32 (i32 (assertzext (i32 (
8858 f32_to_f16 (f32 FPR32:$Rn))))))),
8861 // Patterns for vector extract of half-precision FP value in i16 storage type
8862 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8863 (v4i16 VPR64:$Rn), neon_uimm2_bare:$Imm)), 65535)))),
8864 (FCVTsh (f16 (DUPhv_H
8865 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8866 neon_uimm2_bare:$Imm)))>;
8868 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8869 (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)), 65535)))),
8870 (FCVTsh (f16 (DUPhv_H (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)))>;
8872 // Patterns for vector insert of half-precision FP value 0 in i16 storage type
8873 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8874 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8875 (neon_uimm3_bare:$Imm))),
8876 (v8i16 (INSELh (v8i16 VPR128:$Rn),
8877 (v8i16 (SUBREG_TO_REG (i64 0),
8878 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8880 neon_uimm3_bare:$Imm, 0))>;
8882 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8883 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8884 (neon_uimm2_bare:$Imm))),
8885 (v4i16 (EXTRACT_SUBREG
8887 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8888 (v8i16 (SUBREG_TO_REG (i64 0),
8889 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8891 neon_uimm2_bare:$Imm, 0)),
8894 // Patterns for vector insert of half-precision FP value in i16 storage type
8895 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8896 (i32 (assertsext (i32 (fp_to_sint
8897 (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8898 (neon_uimm3_bare:$Imm))),
8899 (v8i16 (INSELh (v8i16 VPR128:$Rn),
8900 (v8i16 (SUBREG_TO_REG (i64 0),
8901 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8903 neon_uimm3_bare:$Imm, 0))>;
8905 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8906 (i32 (assertsext (i32 (fp_to_sint
8907 (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8908 (neon_uimm2_bare:$Imm))),
8909 (v4i16 (EXTRACT_SUBREG
8911 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8912 (v8i16 (SUBREG_TO_REG (i64 0),
8913 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8915 neon_uimm2_bare:$Imm, 0)),
8918 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8919 (i32 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8920 (neon_uimm3_bare:$Imm1))),
8921 (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8922 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8924 // Patterns for vector copy of half-precision FP value in i16 storage type
8925 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8926 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8927 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8929 (neon_uimm3_bare:$Imm1))),
8930 (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8931 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8933 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8934 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8935 (vector_extract (v4i16 VPR64:$src), neon_uimm3_bare:$Imm2)),
8937 (neon_uimm3_bare:$Imm1))),
8938 (v4i16 (EXTRACT_SUBREG
8940 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8941 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
8942 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2)),