lib/Target/AArch64/AArch64InstrNEON.td

   1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the AArch64 NEON instruction set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // NEON-specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17 def Neon_bsl       : SDNode<"AArch64ISD::NEON_BSL", SDTypeProfile<1, 3,
  18                       [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
  19                       SDTCisSameAs<0, 3>]>>;
  20
  21 // (outs Result), (ins Imm, OpCmode)
  22 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
  23
  24 def Neon_movi     : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
  25
  26 def Neon_mvni     : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
  27
  28 // (outs Result), (ins Imm)
  29 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
  30                         [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
  31
  32 // (outs Result), (ins LHS, RHS, CondCode)
  33 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
  34                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  35
  36 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
  37 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
  38                  [SDTCisVec<0>,  SDTCisVec<1>]>>;
  39
  40 // (outs Result), (ins LHS, RHS)
  41 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
  42                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  43
  44 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  45                                      SDTCisVT<2, i32>]>;
  46 def Neon_sqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
  47 def Neon_uqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
  48
  49 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  50                                SDTCisSameAs<0, 2>]>;
  51 def Neon_uzp1    : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
  52 def Neon_uzp2    : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
  53 def Neon_zip1    : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
  54 def Neon_zip2    : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
  55 def Neon_trn1    : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
  56 def Neon_trn2    : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
  57
  58 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
  59 def Neon_rev64    : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
  60 def Neon_rev32    : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
  61 def Neon_rev16    : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
  62 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
  63                        [SDTCisVec<0>]>>;
  64 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
  65                            [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
  66 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
  67                            [SDTCisVec<0>,  SDTCisSameAs<0, 1>,
  68                            SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
  69
  70 //===----------------------------------------------------------------------===//
  71 // Multiclasses
  72 //===----------------------------------------------------------------------===//
  73
  74 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size,  bits<5> opcode,
  75                                 string asmop, SDPatternOperator opnode8B,
  76                                 SDPatternOperator opnode16B,
  77                                 bit Commutable = 0> {
  78   let isCommutable = Commutable in {
  79     def _8B :  NeonI_3VSame<0b0, u, size, opcode,
  80                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  81                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
  82                [(set (v8i8 VPR64:$Rd),
  83                   (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
  84                NoItinerary>;
  85
  86     def _16B : NeonI_3VSame<0b1, u, size, opcode,
  87                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
  88                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
  89                [(set (v16i8 VPR128:$Rd),
  90                   (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
  91                NoItinerary>;
  92   }
  93
  94 }
  95
  96 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
  97                                   string asmop, SDPatternOperator opnode,
  98                                   bit Commutable = 0> {
  99   let isCommutable = Commutable in {
 100     def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
 101               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 102               asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
 103               [(set (v4i16 VPR64:$Rd),
 104                  (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
 105               NoItinerary>;
 106
 107     def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
 108               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 109               asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
 110               [(set (v8i16 VPR128:$Rd),
 111                  (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
 112               NoItinerary>;
 113
 114     def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
 115               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 116               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 117               [(set (v2i32 VPR64:$Rd),
 118                  (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
 119               NoItinerary>;
 120
 121     def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
 122               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 123               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 124               [(set (v4i32 VPR128:$Rd),
 125                  (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
 126               NoItinerary>;
 127   }
 128 }
 129 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
 130                                   string asmop, SDPatternOperator opnode,
 131                                   bit Commutable = 0>
 132    : NeonI_3VSame_HS_sizes<u, opcode,  asmop, opnode, Commutable> {
 133   let isCommutable = Commutable in {
 134     def _8B :  NeonI_3VSame<0b0, u, 0b00, opcode,
 135                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 136                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 137                [(set (v8i8 VPR64:$Rd),
 138                   (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 139                NoItinerary>;
 140
 141     def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
 142                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 143                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 144                [(set (v16i8 VPR128:$Rd),
 145                   (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 146                NoItinerary>;
 147   }
 148 }
 149
 150 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
 151                                    string asmop, SDPatternOperator opnode,
 152                                    bit Commutable = 0>
 153    : NeonI_3VSame_BHS_sizes<u, opcode,  asmop, opnode, Commutable> {
 154   let isCommutable = Commutable in {
 155     def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
 156               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 157               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 158               [(set (v2i64 VPR128:$Rd),
 159                  (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
 160               NoItinerary>;
 161   }
 162 }
 163
 164 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
 165 // but Result types can be integer or floating point types.
 166 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
 167                                  string asmop, SDPatternOperator opnode2S,
 168                                  SDPatternOperator opnode4S,
 169                                  SDPatternOperator opnode2D,
 170                                  ValueType ResTy2S, ValueType ResTy4S,
 171                                  ValueType ResTy2D, bit Commutable = 0> {
 172   let isCommutable = Commutable in {
 173     def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
 174               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 175               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 176               [(set (ResTy2S VPR64:$Rd),
 177                  (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
 178               NoItinerary>;
 179
 180     def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
 181               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 182               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 183               [(set (ResTy4S VPR128:$Rd),
 184                  (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
 185               NoItinerary>;
 186
 187     def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
 188               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 189               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 190               [(set (ResTy2D VPR128:$Rd),
 191                  (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
 192                NoItinerary>;
 193   }
 194 }
 195
 196 //===----------------------------------------------------------------------===//
 197 // Instruction Definitions
 198 //===----------------------------------------------------------------------===//
 199
 200 // Vector Arithmetic Instructions
 201
 202 // Vector Add (Integer and Floating-Point)
 203
 204 defm ADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
 205 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
 206                                      v2f32, v4f32, v2f64, 1>;
 207
 208 // Vector Sub (Integer and Floating-Point)
 209
 210 defm SUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
 211 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
 212                                      v2f32, v4f32, v2f64, 0>;
 213
 214 // Vector Multiply (Integer and Floating-Point)
 215
 216 defm MULvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
 217 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
 218                                      v2f32, v4f32, v2f64, 1>;
 219
 220 // Vector Multiply (Polynomial)
 221
 222 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
 223                                     int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
 224
 225 // Vector Multiply-accumulate and Multiply-subtract (Integer)
 226
 227 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
 228 // two operands constraints.
 229 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
 230   RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
 231   bits<5> opcode, SDPatternOperator opnode>
 232   : NeonI_3VSame<q, u, size, opcode,
 233     (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
 234     asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
 235     [(set (OpTy VPRC:$Rd),
 236        (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
 237     NoItinerary> {
 238   let Constraints = "$src = $Rd";
 239 }
 240
 241 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 242                        (add node:$Ra, (mul node:$Rn, node:$Rm))>;
 243
 244 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 245                        (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
 246
 247
 248 def MLAvvv_8B:  NeonI_3VSame_Constraint_impl<"mla", ".8b",  VPR64,  v8i8,
 249                                              0b0, 0b0, 0b00, 0b10010, Neon_mla>;
 250 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
 251                                              0b1, 0b0, 0b00, 0b10010, Neon_mla>;
 252 def MLAvvv_4H:  NeonI_3VSame_Constraint_impl<"mla", ".4h",  VPR64,  v4i16,
 253                                              0b0, 0b0, 0b01, 0b10010, Neon_mla>;
 254 def MLAvvv_8H:  NeonI_3VSame_Constraint_impl<"mla", ".8h",  VPR128, v8i16,
 255                                              0b1, 0b0, 0b01, 0b10010, Neon_mla>;
 256 def MLAvvv_2S:  NeonI_3VSame_Constraint_impl<"mla", ".2s",  VPR64,  v2i32,
 257                                              0b0, 0b0, 0b10, 0b10010, Neon_mla>;
 258 def MLAvvv_4S:  NeonI_3VSame_Constraint_impl<"mla", ".4s",  VPR128, v4i32,
 259                                              0b1, 0b0, 0b10, 0b10010, Neon_mla>;
 260
 261 def MLSvvv_8B:  NeonI_3VSame_Constraint_impl<"mls", ".8b",  VPR64,  v8i8,
 262                                              0b0, 0b1, 0b00, 0b10010, Neon_mls>;
 263 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
 264                                              0b1, 0b1, 0b00, 0b10010, Neon_mls>;
 265 def MLSvvv_4H:  NeonI_3VSame_Constraint_impl<"mls", ".4h",  VPR64,  v4i16,
 266                                              0b0, 0b1, 0b01, 0b10010, Neon_mls>;
 267 def MLSvvv_8H:  NeonI_3VSame_Constraint_impl<"mls", ".8h",  VPR128, v8i16,
 268                                              0b1, 0b1, 0b01, 0b10010, Neon_mls>;
 269 def MLSvvv_2S:  NeonI_3VSame_Constraint_impl<"mls", ".2s",  VPR64,  v2i32,
 270                                              0b0, 0b1, 0b10, 0b10010, Neon_mls>;
 271 def MLSvvv_4S:  NeonI_3VSame_Constraint_impl<"mls", ".4s",  VPR128, v4i32,
 272                                              0b1, 0b1, 0b10, 0b10010, Neon_mls>;
 273
 274 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
 275
 276 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 277                         (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
 278
 279 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 280                         (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
 281
 282 let Predicates = [HasNEON, UseFusedMAC] in {
 283 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s",  VPR64,  v2f32,
 284                                              0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
 285 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s",  VPR128, v4f32,
 286                                              0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
 287 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d",  VPR128, v2f64,
 288                                              0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
 289
 290 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s",  VPR64,  v2f32,
 291                                               0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
 292 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s",  VPR128, v4f32,
 293                                              0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
 294 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d",  VPR128, v2f64,
 295                                              0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
 296 }
 297
 298 // We're also allowed to match the fma instruction regardless of compile
 299 // options.
 300 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
 301           (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 302 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 303           (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 304 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 305           (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 306
 307 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
 308           (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 309 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 310           (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 311 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 312           (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 313
 314 // Vector Divide (Floating-Point)
 315
 316 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
 317                                      v2f32, v4f32, v2f64, 0>;
 318
 319 // Vector Bitwise Operations
 320
 321 // Vector Bitwise AND
 322
 323 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
 324
 325 // Vector Bitwise Exclusive OR
 326
 327 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
 328
 329 // Vector Bitwise OR
 330
 331 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
 332
 333 // ORR disassembled as MOV if Vn==Vm
 334
 335 // Vector Move - register
 336 // Alias for ORR if Vn=Vm.
 337 // FIXME: This is actually the preferred syntax but TableGen can't deal with
 338 // custom printing of aliases.
 339 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
 340                     (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
 341 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
 342                     (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
 343
 344 // The MOVI instruction takes two immediate operands.  The first is the
 345 // immediate encoding, while the second is the cmode.  A cmode of 14, or
 346 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
 347 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
 348 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
 349
 350 def Neon_not8B  : PatFrag<(ops node:$in),
 351                           (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
 352 def Neon_not16B : PatFrag<(ops node:$in),
 353                           (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
 354
 355 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
 356                          (or node:$Rn, (Neon_not8B node:$Rm))>;
 357
 358 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
 359                           (or node:$Rn, (Neon_not16B node:$Rm))>;
 360
 361 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
 362                          (and node:$Rn, (Neon_not8B node:$Rm))>;
 363
 364 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
 365                           (and node:$Rn, (Neon_not16B node:$Rm))>;
 366
 367
 368 // Vector Bitwise OR NOT - register
 369
 370 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
 371                                    Neon_orn8B, Neon_orn16B, 0>;
 372
 373 // Vector Bitwise Bit Clear (AND NOT) - register
 374
 375 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
 376                                    Neon_bic8B, Neon_bic16B, 0>;
 377
 378 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
 379                                    SDPatternOperator opnode16B,
 380                                    Instruction INST8B,
 381                                    Instruction INST16B> {
 382   def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 383             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 384   def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 385             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 386   def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 387             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 388   def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 389             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 390   def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 391             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 392   def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 393             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 394 }
 395
 396 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
 397 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
 398 defm : Neon_bitwise2V_patterns<or,  or,  ORRvvv_8B, ORRvvv_16B>;
 399 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
 400 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
 401 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
 402
 403 //   Vector Bitwise Select
 404 def BSLvvv_8B  : NeonI_3VSame_Constraint_impl<"bsl", ".8b",  VPR64, v8i8,
 405                                               0b0, 0b1, 0b01, 0b00011, Neon_bsl>;
 406
 407 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
 408                                               0b1, 0b1, 0b01, 0b00011, Neon_bsl>;
 409
 410 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
 411                                    Instruction INST8B,
 412                                    Instruction INST16B> {
 413   // Disassociate type from instruction definition
 414   def : Pat<(v2i32 (opnode VPR64:$src,VPR64:$Rn, VPR64:$Rm)),
 415             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 416   def : Pat<(v4i16 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 417             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 418   def : Pat<(v1i64 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 419             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 420   def : Pat<(v4i32 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 421             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 422   def : Pat<(v8i16 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 423             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 424   def : Pat<(v2i64 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 425             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 426
 427   // Allow to match BSL instruction pattern with non-constant operand
 428   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
 429                     (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 430           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 431   def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
 432                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 433           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 434   def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
 435                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 436           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 437   def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
 438                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 439           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 440   def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
 441                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 442           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 443   def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
 444                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 445           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 446   def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
 447                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 448           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 449   def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
 450                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 451           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 452
 453   // Allow to match llvm.arm.* intrinsics.
 454   def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
 455                     (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
 456             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 457   def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
 458                     (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
 459             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 460   def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
 461                     (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
 462             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 463   def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
 464                     (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
 465             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 466   def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
 467                     (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
 468             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 469   def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
 470                     (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
 471             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 472   def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
 473                     (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
 474             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 475   def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
 476                     (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
 477             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 478   def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
 479                     (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
 480             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 481   def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
 482                     (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
 483             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 484   def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
 485                     (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
 486             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 487   def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
 488                     (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
 489             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 490 }
 491
 492 // Additional patterns for bitwise instruction BSL
 493 defm: Neon_bitwise3V_patterns<Neon_bsl, BSLvvv_8B, BSLvvv_16B>;
 494
 495 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
 496                            (Neon_bsl node:$src, node:$Rn, node:$Rm),
 497                            [{ (void)N; return false; }]>;
 498
 499 // Vector Bitwise Insert if True
 500
 501 def BITvvv_8B  : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64,   v8i8,
 502                    0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 503 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
 504                    0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 505
 506 // Vector Bitwise Insert if False
 507
 508 def BIFvvv_8B  : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64,  v8i8,
 509                                 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 510 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
 511                                 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 512
 513 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
 514
 515 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 516                        (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
 517 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 518                        (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
 519
 520 // Vector Absolute Difference and Accumulate (Unsigned)
 521 def UABAvvv_8B :  NeonI_3VSame_Constraint_impl<"uaba", ".8b",  VPR64,  v8i8,
 522                     0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
 523 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
 524                     0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
 525 def UABAvvv_4H :  NeonI_3VSame_Constraint_impl<"uaba", ".4h",  VPR64,  v4i16,
 526                     0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
 527 def UABAvvv_8H :  NeonI_3VSame_Constraint_impl<"uaba", ".8h",  VPR128, v8i16,
 528                     0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
 529 def UABAvvv_2S :  NeonI_3VSame_Constraint_impl<"uaba", ".2s",  VPR64,  v2i32,
 530                     0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
 531 def UABAvvv_4S :  NeonI_3VSame_Constraint_impl<"uaba", ".4s",  VPR128, v4i32,
 532                     0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
 533
 534 // Vector Absolute Difference and Accumulate (Signed)
 535 def SABAvvv_8B :  NeonI_3VSame_Constraint_impl<"saba", ".8b",  VPR64,  v8i8,
 536                     0b0, 0b0, 0b00, 0b01111, Neon_saba>;
 537 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
 538                     0b1, 0b0, 0b00, 0b01111, Neon_saba>;
 539 def SABAvvv_4H :  NeonI_3VSame_Constraint_impl<"saba", ".4h",  VPR64,  v4i16,
 540                     0b0, 0b0, 0b01, 0b01111, Neon_saba>;
 541 def SABAvvv_8H :  NeonI_3VSame_Constraint_impl<"saba", ".8h",  VPR128, v8i16,
 542                     0b1, 0b0, 0b01, 0b01111, Neon_saba>;
 543 def SABAvvv_2S :  NeonI_3VSame_Constraint_impl<"saba", ".2s",  VPR64,  v2i32,
 544                     0b0, 0b0, 0b10, 0b01111, Neon_saba>;
 545 def SABAvvv_4S :  NeonI_3VSame_Constraint_impl<"saba", ".4s",  VPR128, v4i32,
 546                     0b1, 0b0, 0b10, 0b01111, Neon_saba>;
 547
 548
 549 // Vector Absolute Difference (Signed, Unsigned)
 550 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
 551 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
 552
 553 // Vector Absolute Difference (Floating Point)
 554 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
 555                                     int_arm_neon_vabds, int_arm_neon_vabds,
 556                                     int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
 557
 558 // Vector Reciprocal Step (Floating Point)
 559 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
 560                                        int_arm_neon_vrecps, int_arm_neon_vrecps,
 561                                        int_arm_neon_vrecps,
 562                                        v2f32, v4f32, v2f64, 0>;
 563
 564 // Vector Reciprocal Square Root Step (Floating Point)
 565 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
 566                                         int_arm_neon_vrsqrts,
 567                                         int_arm_neon_vrsqrts,
 568                                         int_arm_neon_vrsqrts,
 569                                         v2f32, v4f32, v2f64, 0>;
 570
 571 // Vector Comparisons
 572
 573 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
 574                         (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
 575 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
 576                          (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
 577 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
 578                         (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
 579 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
 580                         (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
 581 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
 582                         (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
 583
 584 // NeonI_compare_aliases class: swaps register operands to implement
 585 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
 586 class NeonI_compare_aliases<string asmop, string asmlane,
 587                             Instruction inst, RegisterOperand VPRC>
 588   : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
 589                     ", $Rm" # asmlane,
 590                   (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
 591
 592 // Vector Comparisons (Integer)
 593
 594 // Vector Compare Mask Equal (Integer)
 595 let isCommutable =1 in {
 596 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
 597 }
 598
 599 // Vector Compare Mask Higher or Same (Unsigned Integer)
 600 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
 601
 602 // Vector Compare Mask Greater Than or Equal (Integer)
 603 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
 604
 605 // Vector Compare Mask Higher (Unsigned Integer)
 606 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
 607
 608 // Vector Compare Mask Greater Than (Integer)
 609 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
 610
 611 // Vector Compare Mask Bitwise Test (Integer)
 612 defm CMTSTvvv:  NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
 613
 614 // Vector Compare Mask Less or Same (Unsigned Integer)
 615 // CMLS is alias for CMHS with operands reversed.
 616 def CMLSvvv_8B  : NeonI_compare_aliases<"cmls", ".8b",  CMHSvvv_8B,  VPR64>;
 617 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
 618 def CMLSvvv_4H  : NeonI_compare_aliases<"cmls", ".4h",  CMHSvvv_4H,  VPR64>;
 619 def CMLSvvv_8H  : NeonI_compare_aliases<"cmls", ".8h",  CMHSvvv_8H,  VPR128>;
 620 def CMLSvvv_2S  : NeonI_compare_aliases<"cmls", ".2s",  CMHSvvv_2S,  VPR64>;
 621 def CMLSvvv_4S  : NeonI_compare_aliases<"cmls", ".4s",  CMHSvvv_4S,  VPR128>;
 622 def CMLSvvv_2D  : NeonI_compare_aliases<"cmls", ".2d",  CMHSvvv_2D,  VPR128>;
 623
 624 // Vector Compare Mask Less Than or Equal (Integer)
 625 // CMLE is alias for CMGE with operands reversed.
 626 def CMLEvvv_8B  : NeonI_compare_aliases<"cmle", ".8b",  CMGEvvv_8B,  VPR64>;
 627 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
 628 def CMLEvvv_4H  : NeonI_compare_aliases<"cmle", ".4h",  CMGEvvv_4H,  VPR64>;
 629 def CMLEvvv_8H  : NeonI_compare_aliases<"cmle", ".8h",  CMGEvvv_8H,  VPR128>;
 630 def CMLEvvv_2S  : NeonI_compare_aliases<"cmle", ".2s",  CMGEvvv_2S,  VPR64>;
 631 def CMLEvvv_4S  : NeonI_compare_aliases<"cmle", ".4s",  CMGEvvv_4S,  VPR128>;
 632 def CMLEvvv_2D  : NeonI_compare_aliases<"cmle", ".2d",  CMGEvvv_2D,  VPR128>;
 633
 634 // Vector Compare Mask Lower (Unsigned Integer)
 635 // CMLO is alias for CMHI with operands reversed.
 636 def CMLOvvv_8B  : NeonI_compare_aliases<"cmlo", ".8b",  CMHIvvv_8B,  VPR64>;
 637 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
 638 def CMLOvvv_4H  : NeonI_compare_aliases<"cmlo", ".4h",  CMHIvvv_4H,  VPR64>;
 639 def CMLOvvv_8H  : NeonI_compare_aliases<"cmlo", ".8h",  CMHIvvv_8H,  VPR128>;
 640 def CMLOvvv_2S  : NeonI_compare_aliases<"cmlo", ".2s",  CMHIvvv_2S,  VPR64>;
 641 def CMLOvvv_4S  : NeonI_compare_aliases<"cmlo", ".4s",  CMHIvvv_4S,  VPR128>;
 642 def CMLOvvv_2D  : NeonI_compare_aliases<"cmlo", ".2d",  CMHIvvv_2D,  VPR128>;
 643
 644 // Vector Compare Mask Less Than (Integer)
 645 // CMLT is alias for CMGT with operands reversed.
 646 def CMLTvvv_8B  : NeonI_compare_aliases<"cmlt", ".8b",  CMGTvvv_8B,  VPR64>;
 647 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
 648 def CMLTvvv_4H  : NeonI_compare_aliases<"cmlt", ".4h",  CMGTvvv_4H,  VPR64>;
 649 def CMLTvvv_8H  : NeonI_compare_aliases<"cmlt", ".8h",  CMGTvvv_8H,  VPR128>;
 650 def CMLTvvv_2S  : NeonI_compare_aliases<"cmlt", ".2s",  CMGTvvv_2S,  VPR64>;
 651 def CMLTvvv_4S  : NeonI_compare_aliases<"cmlt", ".4s",  CMGTvvv_4S,  VPR128>;
 652 def CMLTvvv_2D  : NeonI_compare_aliases<"cmlt", ".2d",  CMGTvvv_2D,  VPR128>;
 653
 654
 655 def neon_uimm0_asmoperand : AsmOperandClass
 656 {
 657   let Name = "UImm0";
 658   let PredicateMethod = "isUImm<0>";
 659   let RenderMethod = "addImmOperands";
 660 }
 661
 662 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
 663   let ParserMatchClass = neon_uimm0_asmoperand;
 664   let PrintMethod = "printNeonUImm0Operand";
 665
 666 }
 667
 668 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
 669 {
 670   def _8B :  NeonI_2VMisc<0b0, u, 0b00, opcode,
 671              (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 672              asmop # "\t$Rd.8b, $Rn.8b, $Imm",
 673              [(set (v8i8 VPR64:$Rd),
 674                 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 675              NoItinerary>;
 676
 677   def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
 678              (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 679              asmop # "\t$Rd.16b, $Rn.16b, $Imm",
 680              [(set (v16i8 VPR128:$Rd),
 681                 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 682              NoItinerary>;
 683
 684   def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
 685             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 686             asmop # "\t$Rd.4h, $Rn.4h, $Imm",
 687             [(set (v4i16 VPR64:$Rd),
 688                (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 689             NoItinerary>;
 690
 691   def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
 692             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 693             asmop # "\t$Rd.8h, $Rn.8h, $Imm",
 694             [(set (v8i16 VPR128:$Rd),
 695                (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 696             NoItinerary>;
 697
 698   def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
 699             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 700             asmop # "\t$Rd.2s, $Rn.2s, $Imm",
 701             [(set (v2i32 VPR64:$Rd),
 702                (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 703             NoItinerary>;
 704
 705   def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
 706             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 707             asmop # "\t$Rd.4s, $Rn.4s, $Imm",
 708             [(set (v4i32 VPR128:$Rd),
 709                (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 710             NoItinerary>;
 711
 712   def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
 713             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 714             asmop # "\t$Rd.2d, $Rn.2d, $Imm",
 715             [(set (v2i64 VPR128:$Rd),
 716                (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 717             NoItinerary>;
 718 }
 719
 720 // Vector Compare Mask Equal to Zero (Integer)
 721 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
 722
 723 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
 724 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
 725
 726 // Vector Compare Mask Greater Than Zero (Signed Integer)
 727 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
 728
 729 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
 730 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
 731
 732 // Vector Compare Mask Less Than Zero (Signed Integer)
 733 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
 734
 735 // Vector Comparisons (Floating Point)
 736
 737 // Vector Compare Mask Equal (Floating Point)
 738 let isCommutable =1 in {
 739 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
 740                                       Neon_cmeq, Neon_cmeq,
 741                                       v2i32, v4i32, v2i64, 0>;
 742 }
 743
 744 // Vector Compare Mask Greater Than Or Equal (Floating Point)
 745 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
 746                                       Neon_cmge, Neon_cmge,
 747                                       v2i32, v4i32, v2i64, 0>;
 748
 749 // Vector Compare Mask Greater Than (Floating Point)
 750 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
 751                                       Neon_cmgt, Neon_cmgt,
 752                                       v2i32, v4i32, v2i64, 0>;
 753
 754 // Vector Compare Mask Less Than Or Equal (Floating Point)
 755 // FCMLE is alias for FCMGE with operands reversed.
 756 def FCMLEvvv_2S  : NeonI_compare_aliases<"fcmle", ".2s",  FCMGEvvv_2S,  VPR64>;
 757 def FCMLEvvv_4S  : NeonI_compare_aliases<"fcmle", ".4s",  FCMGEvvv_4S,  VPR128>;
 758 def FCMLEvvv_2D  : NeonI_compare_aliases<"fcmle", ".2d",  FCMGEvvv_2D,  VPR128>;
 759
 760 // Vector Compare Mask Less Than (Floating Point)
 761 // FCMLT is alias for FCMGT with operands reversed.
 762 def FCMLTvvv_2S  : NeonI_compare_aliases<"fcmlt", ".2s",  FCMGTvvv_2S,  VPR64>;
 763 def FCMLTvvv_4S  : NeonI_compare_aliases<"fcmlt", ".4s",  FCMGTvvv_4S,  VPR128>;
 764 def FCMLTvvv_2D  : NeonI_compare_aliases<"fcmlt", ".2d",  FCMGTvvv_2D,  VPR128>;
 765
 766
 767 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
 768                               string asmop, CondCode CC>
 769 {
 770   def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
 771             (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
 772             asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
 773             [(set (v2i32 VPR64:$Rd),
 774                (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpimm:$FPImm), CC)))],
 775             NoItinerary>;
 776
 777   def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
 778             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 779             asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
 780             [(set (v4i32 VPR128:$Rd),
 781                (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
 782             NoItinerary>;
 783
 784   def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
 785             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 786             asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
 787             [(set (v2i64 VPR128:$Rd),
 788                (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
 789             NoItinerary>;
 790 }
 791
 792 // Vector Compare Mask Equal to Zero (Floating Point)
 793 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
 794
 795 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
 796 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
 797
 798 // Vector Compare Mask Greater Than Zero (Floating Point)
 799 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
 800
 801 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
 802 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
 803
 804 // Vector Compare Mask Less Than Zero (Floating Point)
 805 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
 806
 807 // Vector Absolute Comparisons (Floating Point)
 808
 809 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
 810 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
 811                                       int_arm_neon_vacged, int_arm_neon_vacgeq,
 812                                       int_aarch64_neon_vacgeq,
 813                                       v2i32, v4i32, v2i64, 0>;
 814
 815 // Vector Absolute Compare Mask Greater Than (Floating Point)
 816 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
 817                                       int_arm_neon_vacgtd, int_arm_neon_vacgtq,
 818                                       int_aarch64_neon_vacgtq,
 819                                       v2i32, v4i32, v2i64, 0>;
 820
 821 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
 822 // FACLE is alias for FACGE with operands reversed.
 823 def FACLEvvv_2S  : NeonI_compare_aliases<"facle", ".2s",  FACGEvvv_2S,  VPR64>;
 824 def FACLEvvv_4S  : NeonI_compare_aliases<"facle", ".4s",  FACGEvvv_4S,  VPR128>;
 825 def FACLEvvv_2D  : NeonI_compare_aliases<"facle", ".2d",  FACGEvvv_2D,  VPR128>;
 826
 827 // Vector Absolute Compare Mask Less Than (Floating Point)
 828 // FACLT is alias for FACGT with operands reversed.
 829 def FACLTvvv_2S  : NeonI_compare_aliases<"faclt", ".2s",  FACGTvvv_2S,  VPR64>;
 830 def FACLTvvv_4S  : NeonI_compare_aliases<"faclt", ".4s",  FACGTvvv_4S,  VPR128>;
 831 def FACLTvvv_2D  : NeonI_compare_aliases<"faclt", ".2d",  FACGTvvv_2D,  VPR128>;
 832
 833 // Vector halving add (Integer Signed, Unsigned)
 834 defm SHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
 835                                         int_arm_neon_vhadds, 1>;
 836 defm UHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
 837                                         int_arm_neon_vhaddu, 1>;
 838
 839 // Vector halving sub (Integer Signed, Unsigned)
 840 defm SHSUBvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
 841                                         int_arm_neon_vhsubs, 0>;
 842 defm UHSUBvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
 843                                         int_arm_neon_vhsubu, 0>;
 844
 845 // Vector rouding halving add (Integer Signed, Unsigned)
 846 defm SRHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
 847                                          int_arm_neon_vrhadds, 1>;
 848 defm URHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
 849                                          int_arm_neon_vrhaddu, 1>;
 850
 851 // Vector Saturating add (Integer Signed, Unsigned)
 852 defm SQADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
 853                    int_arm_neon_vqadds, 1>;
 854 defm UQADDvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
 855                    int_arm_neon_vqaddu, 1>;
 856
 857 // Vector Saturating sub (Integer Signed, Unsigned)
 858 defm SQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
 859                    int_arm_neon_vqsubs, 1>;
 860 defm UQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
 861                    int_arm_neon_vqsubu, 1>;
 862
 863 // Vector Shift Left (Signed and Unsigned Integer)
 864 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
 865                  int_arm_neon_vshifts, 1>;
 866 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
 867                  int_arm_neon_vshiftu, 1>;
 868
 869 // Vector Saturating Shift Left (Signed and Unsigned Integer)
 870 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
 871                   int_arm_neon_vqshifts, 1>;
 872 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
 873                   int_arm_neon_vqshiftu, 1>;
 874
 875 // Vector Rouding Shift Left (Signed and Unsigned Integer)
 876 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
 877                   int_arm_neon_vrshifts, 1>;
 878 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
 879                   int_arm_neon_vrshiftu, 1>;
 880
 881 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
 882 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
 883                    int_arm_neon_vqrshifts, 1>;
 884 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
 885                    int_arm_neon_vqrshiftu, 1>;
 886
 887 // Vector Maximum (Signed and Unsigned Integer)
 888 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
 889 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
 890
 891 // Vector Minimum (Signed and Unsigned Integer)
 892 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
 893 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
 894
 895 // Vector Maximum (Floating Point)
 896 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
 897                                      int_arm_neon_vmaxs, int_arm_neon_vmaxs,
 898                                      int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
 899
 900 // Vector Minimum (Floating Point)
 901 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
 902                                      int_arm_neon_vmins, int_arm_neon_vmins,
 903                                      int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
 904
 905 // Vector maxNum (Floating Point) -  prefer a number over a quiet NaN)
 906 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
 907                                        int_aarch64_neon_vmaxnm,
 908                                        int_aarch64_neon_vmaxnm,
 909                                        int_aarch64_neon_vmaxnm,
 910                                        v2f32, v4f32, v2f64, 1>;
 911
 912 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
 913 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
 914                                        int_aarch64_neon_vminnm,
 915                                        int_aarch64_neon_vminnm,
 916                                        int_aarch64_neon_vminnm,
 917                                        v2f32, v4f32, v2f64, 1>;
 918
 919 // Vector Maximum Pairwise (Signed and Unsigned Integer)
 920 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
 921 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
 922
 923 // Vector Minimum Pairwise (Signed and Unsigned Integer)
 924 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
 925 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
 926
 927 // Vector Maximum Pairwise (Floating Point)
 928 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
 929                                      int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
 930                                      int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
 931
 932 // Vector Minimum Pairwise (Floating Point)
 933 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
 934                                      int_arm_neon_vpmins, int_arm_neon_vpmins,
 935                                      int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
 936
 937 // Vector maxNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 938 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
 939                                        int_aarch64_neon_vpmaxnm,
 940                                        int_aarch64_neon_vpmaxnm,
 941                                        int_aarch64_neon_vpmaxnm,
 942                                        v2f32, v4f32, v2f64, 1>;
 943
 944 // Vector minNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 945 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
 946                                        int_aarch64_neon_vpminnm,
 947                                        int_aarch64_neon_vpminnm,
 948                                        int_aarch64_neon_vpminnm,
 949                                        v2f32, v4f32, v2f64, 1>;
 950
 951 // Vector Addition Pairwise (Integer)
 952 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
 953
 954 // Vector Addition Pairwise (Floating Point)
 955 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
 956                                        int_arm_neon_vpadd,
 957                                        int_arm_neon_vpadd,
 958                                        int_arm_neon_vpadd,
 959                                        v2f32, v4f32, v2f64, 1>;
 960
 961 // Vector Saturating Doubling Multiply High
 962 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
 963                     int_arm_neon_vqdmulh, 1>;
 964
 965 // Vector Saturating Rouding Doubling Multiply High
 966 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
 967                      int_arm_neon_vqrdmulh, 1>;
 968
 969 // Vector Multiply Extended (Floating Point)
 970 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
 971                                       int_aarch64_neon_vmulx,
 972                                       int_aarch64_neon_vmulx,
 973                                       int_aarch64_neon_vmulx,
 974                                       v2f32, v4f32, v2f64, 1>;
 975
 976 // Vector Immediate Instructions
 977
 978 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
 979 {
 980   def _asmoperand : AsmOperandClass
 981     {
 982       let Name = "NeonMovImmShift" # PREFIX;
 983       let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
 984       let PredicateMethod = "isNeonMovImmShift" # PREFIX;
 985     }
 986 }
 987
 988 // Definition of vector immediates shift operands
 989
 990 // The selectable use-cases extract the shift operation
 991 // information from the OpCmode fields encoded in the immediate.
 992 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
 993   uint64_t OpCmode = N->getZExtValue();
 994   unsigned ShiftImm;
 995   unsigned ShiftOnesIn;
 996   unsigned HasShift =
 997     A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
 998   if (!HasShift) return SDValue();
 999   return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1000 }]>;
1001
1002 // Vector immediates shift operands which accept LSL and MSL
1003 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1004 // or 0, 8 (LSLH) or 8, 16 (MSL).
1005 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1006 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1007 // LSLH restricts shift amount to  0, 8 out of 0, 8, 16, 24
1008 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1009
1010 multiclass neon_mov_imm_shift_operands<string PREFIX,
1011                                        string HALF, string ISHALF, code pred>
1012 {
1013    def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1014     {
1015       let PrintMethod =
1016         "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1017       let DecoderMethod =
1018         "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1019       let ParserMatchClass =
1020         !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1021     }
1022 }
1023
1024 defm neon_mov_imm_LSL  : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1025   unsigned ShiftImm;
1026   unsigned ShiftOnesIn;
1027   unsigned HasShift =
1028     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1029   return (HasShift && !ShiftOnesIn);
1030 }]>;
1031
1032 defm neon_mov_imm_MSL  : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1033   unsigned ShiftImm;
1034   unsigned ShiftOnesIn;
1035   unsigned HasShift =
1036     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1037   return (HasShift && ShiftOnesIn);
1038 }]>;
1039
1040 defm neon_mov_imm_LSLH  : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1041   unsigned ShiftImm;
1042   unsigned ShiftOnesIn;
1043   unsigned HasShift =
1044     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1045   return (HasShift && !ShiftOnesIn);
1046 }]>;
1047
1048 def neon_uimm1_asmoperand : AsmOperandClass
1049 {
1050   let Name = "UImm1";
1051   let PredicateMethod = "isUImm<1>";
1052   let RenderMethod = "addImmOperands";
1053 }
1054
1055 def neon_uimm2_asmoperand : AsmOperandClass
1056 {
1057   let Name = "UImm2";
1058   let PredicateMethod = "isUImm<2>";
1059   let RenderMethod = "addImmOperands";
1060 }
1061
1062 def neon_uimm8_asmoperand : AsmOperandClass
1063 {
1064   let Name = "UImm8";
1065   let PredicateMethod = "isUImm<8>";
1066   let RenderMethod = "addImmOperands";
1067 }
1068
1069 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1070   let ParserMatchClass = neon_uimm8_asmoperand;
1071   let PrintMethod = "printUImmHexOperand";
1072 }
1073
1074 def neon_uimm64_mask_asmoperand : AsmOperandClass
1075 {
1076   let Name = "NeonUImm64Mask";
1077   let PredicateMethod = "isNeonUImm64Mask";
1078   let RenderMethod = "addNeonUImm64MaskOperands";
1079 }
1080
1081 // MCOperand for 64-bit bytemask with each byte having only the
1082 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1083 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1084   let ParserMatchClass = neon_uimm64_mask_asmoperand;
1085   let PrintMethod = "printNeonUImm64MaskOperand";
1086 }
1087
1088 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1089                                    SDPatternOperator opnode>
1090 {
1091     // shift zeros, per word
1092     def _2S  : NeonI_1VModImm<0b0, op,
1093                               (outs VPR64:$Rd),
1094                               (ins neon_uimm8:$Imm,
1095                                 neon_mov_imm_LSL_operand:$Simm),
1096                               !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1097                               [(set (v2i32 VPR64:$Rd),
1098                                  (v2i32 (opnode (timm:$Imm),
1099                                    (neon_mov_imm_LSL_operand:$Simm))))],
1100                               NoItinerary> {
1101        bits<2> Simm;
1102        let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1103      }
1104
1105     def _4S  : NeonI_1VModImm<0b1, op,
1106                               (outs VPR128:$Rd),
1107                               (ins neon_uimm8:$Imm,
1108                                 neon_mov_imm_LSL_operand:$Simm),
1109                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1110                               [(set (v4i32 VPR128:$Rd),
1111                                  (v4i32 (opnode (timm:$Imm),
1112                                    (neon_mov_imm_LSL_operand:$Simm))))],
1113                               NoItinerary> {
1114       bits<2> Simm;
1115       let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1116     }
1117
1118     // shift zeros, per halfword
1119     def _4H  : NeonI_1VModImm<0b0, op,
1120                               (outs VPR64:$Rd),
1121                               (ins neon_uimm8:$Imm,
1122                                 neon_mov_imm_LSLH_operand:$Simm),
1123                               !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1124                               [(set (v4i16 VPR64:$Rd),
1125                                  (v4i16 (opnode (timm:$Imm),
1126                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1127                               NoItinerary> {
1128       bit  Simm;
1129       let cmode = {0b1, 0b0, Simm, 0b0};
1130     }
1131
1132     def _8H  : NeonI_1VModImm<0b1, op,
1133                               (outs VPR128:$Rd),
1134                               (ins neon_uimm8:$Imm,
1135                                 neon_mov_imm_LSLH_operand:$Simm),
1136                               !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1137                               [(set (v8i16 VPR128:$Rd),
1138                                  (v8i16 (opnode (timm:$Imm),
1139                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1140                               NoItinerary> {
1141       bit Simm;
1142       let cmode = {0b1, 0b0, Simm, 0b0};
1143      }
1144 }
1145
1146 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1147                                                    SDPatternOperator opnode,
1148                                                    SDPatternOperator neonopnode>
1149 {
1150   let Constraints = "$src = $Rd" in {
1151     // shift zeros, per word
1152     def _2S  : NeonI_1VModImm<0b0, op,
1153                  (outs VPR64:$Rd),
1154                  (ins VPR64:$src, neon_uimm8:$Imm,
1155                    neon_mov_imm_LSL_operand:$Simm),
1156                  !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1157                  [(set (v2i32 VPR64:$Rd),
1158                     (v2i32 (opnode (v2i32 VPR64:$src),
1159                       (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1160                         neon_mov_imm_LSL_operand:$Simm)))))))],
1161                  NoItinerary> {
1162       bits<2> Simm;
1163       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1164     }
1165
1166     def _4S  : NeonI_1VModImm<0b1, op,
1167                  (outs VPR128:$Rd),
1168                  (ins VPR128:$src, neon_uimm8:$Imm,
1169                    neon_mov_imm_LSL_operand:$Simm),
1170                  !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1171                  [(set (v4i32 VPR128:$Rd),
1172                     (v4i32 (opnode (v4i32 VPR128:$src),
1173                       (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1174                         neon_mov_imm_LSL_operand:$Simm)))))))],
1175                  NoItinerary> {
1176       bits<2> Simm;
1177       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1178     }
1179
1180     // shift zeros, per halfword
1181     def _4H  : NeonI_1VModImm<0b0, op,
1182                  (outs VPR64:$Rd),
1183                  (ins VPR64:$src, neon_uimm8:$Imm,
1184                    neon_mov_imm_LSLH_operand:$Simm),
1185                  !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1186                  [(set (v4i16 VPR64:$Rd),
1187                     (v4i16 (opnode (v4i16 VPR64:$src),
1188                        (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1189                           neon_mov_imm_LSL_operand:$Simm)))))))],
1190                  NoItinerary> {
1191       bit  Simm;
1192       let cmode = {0b1, 0b0, Simm, 0b1};
1193     }
1194
1195     def _8H  : NeonI_1VModImm<0b1, op,
1196                  (outs VPR128:$Rd),
1197                  (ins VPR128:$src, neon_uimm8:$Imm,
1198                    neon_mov_imm_LSLH_operand:$Simm),
1199                  !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1200                  [(set (v8i16 VPR128:$Rd),
1201                     (v8i16 (opnode (v8i16 VPR128:$src),
1202                       (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1203                         neon_mov_imm_LSL_operand:$Simm)))))))],
1204                  NoItinerary> {
1205       bit Simm;
1206       let cmode = {0b1, 0b0, Simm, 0b1};
1207     }
1208   }
1209 }
1210
1211 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1212                                    SDPatternOperator opnode>
1213 {
1214     // shift ones, per word
1215     def _2S  : NeonI_1VModImm<0b0, op,
1216                              (outs VPR64:$Rd),
1217                              (ins neon_uimm8:$Imm,
1218                                neon_mov_imm_MSL_operand:$Simm),
1219                              !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1220                               [(set (v2i32 VPR64:$Rd),
1221                                  (v2i32 (opnode (timm:$Imm),
1222                                    (neon_mov_imm_MSL_operand:$Simm))))],
1223                              NoItinerary> {
1224        bit Simm;
1225        let cmode = {0b1, 0b1, 0b0, Simm};
1226      }
1227
1228    def _4S  : NeonI_1VModImm<0b1, op,
1229                               (outs VPR128:$Rd),
1230                               (ins neon_uimm8:$Imm,
1231                                 neon_mov_imm_MSL_operand:$Simm),
1232                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1233                               [(set (v4i32 VPR128:$Rd),
1234                                  (v4i32 (opnode (timm:$Imm),
1235                                    (neon_mov_imm_MSL_operand:$Simm))))],
1236                               NoItinerary> {
1237      bit Simm;
1238      let cmode = {0b1, 0b1, 0b0, Simm};
1239    }
1240 }
1241
1242 // Vector Move Immediate Shifted
1243 let isReMaterializable = 1 in {
1244 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1245 }
1246
1247 // Vector Move Inverted Immediate Shifted
1248 let isReMaterializable = 1 in {
1249 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1250 }
1251
1252 // Vector Bitwise Bit Clear (AND NOT) - immediate
1253 let isReMaterializable = 1 in {
1254 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1255                                                          and, Neon_mvni>;
1256 }
1257
1258 // Vector Bitwise OR - immedidate
1259
1260 let isReMaterializable = 1 in {
1261 defm ORRvi_lsl   : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1262                                                            or, Neon_movi>;
1263 }
1264
1265 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1266 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1267 // BIC immediate instructions selection requires additional patterns to
1268 // transform Neon_movi operands into BIC immediate operands
1269
1270 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1271   uint64_t OpCmode = N->getZExtValue();
1272   unsigned ShiftImm;
1273   unsigned ShiftOnesIn;
1274   (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1275   // LSLH restricts shift amount to  0, 8 which are encoded as 0 and 1
1276   // Transform encoded shift amount 0 to 1 and 1 to 0.
1277   return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1278 }]>;
1279
1280 def neon_mov_imm_LSLH_transform_operand
1281   : ImmLeaf<i32, [{
1282     unsigned ShiftImm;
1283     unsigned ShiftOnesIn;
1284     unsigned HasShift =
1285       A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1286     return (HasShift && !ShiftOnesIn); }],
1287   neon_mov_imm_LSLH_transform_XFORM>;
1288
1289 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1290 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1291 def : Pat<(v4i16 (and VPR64:$src,
1292             (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1293           (BICvi_lsl_4H VPR64:$src, 0,
1294             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1295
1296 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1297 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1298 def : Pat<(v8i16 (and VPR128:$src,
1299             (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1300           (BICvi_lsl_8H VPR128:$src, 0,
1301             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1302
1303
1304 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1305                                    SDPatternOperator neonopnode,
1306                                    Instruction INST4H,
1307                                    Instruction INST8H> {
1308   def : Pat<(v8i8 (opnode VPR64:$src,
1309                     (bitconvert(v4i16 (neonopnode timm:$Imm,
1310                       neon_mov_imm_LSLH_operand:$Simm))))),
1311             (INST4H VPR64:$src, neon_uimm8:$Imm,
1312               neon_mov_imm_LSLH_operand:$Simm)>;
1313   def : Pat<(v1i64 (opnode VPR64:$src,
1314                   (bitconvert(v4i16 (neonopnode timm:$Imm,
1315                     neon_mov_imm_LSLH_operand:$Simm))))),
1316           (INST4H VPR64:$src, neon_uimm8:$Imm,
1317             neon_mov_imm_LSLH_operand:$Simm)>;
1318
1319   def : Pat<(v16i8 (opnode VPR128:$src,
1320                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1321                      neon_mov_imm_LSLH_operand:$Simm))))),
1322           (INST8H VPR128:$src, neon_uimm8:$Imm,
1323             neon_mov_imm_LSLH_operand:$Simm)>;
1324   def : Pat<(v4i32 (opnode VPR128:$src,
1325                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1326                      neon_mov_imm_LSLH_operand:$Simm))))),
1327           (INST8H VPR128:$src, neon_uimm8:$Imm,
1328             neon_mov_imm_LSLH_operand:$Simm)>;
1329   def : Pat<(v2i64 (opnode VPR128:$src,
1330                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1331                      neon_mov_imm_LSLH_operand:$Simm))))),
1332           (INST8H VPR128:$src, neon_uimm8:$Imm,
1333             neon_mov_imm_LSLH_operand:$Simm)>;
1334 }
1335
1336 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1337 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1338
1339 // Additional patterns for Vector Bitwise OR - immedidate
1340 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1341
1342
1343 // Vector Move Immediate Masked
1344 let isReMaterializable = 1 in {
1345 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1346 }
1347
1348 // Vector Move Inverted Immediate Masked
1349 let isReMaterializable = 1 in {
1350 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1351 }
1352
1353 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1354                                 Instruction inst, RegisterOperand VPRC>
1355   : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1356                         (inst VPRC:$Rd, neon_uimm8:$Imm,  0), 0b0>;
1357
1358 // Aliases for Vector Move Immediate Shifted
1359 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1360 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1361 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1362 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1363
1364 // Aliases for Vector Move Inverted Immediate Shifted
1365 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1366 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1367 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1368 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1369
1370 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1371 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1372 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1373 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1374 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1375
1376 // Aliases for Vector Bitwise OR - immedidate
1377 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1378 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1379 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1380 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1381
1382 //  Vector Move Immediate - per byte
1383 let isReMaterializable = 1 in {
1384 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1385                                (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1386                                "movi\t$Rd.8b, $Imm",
1387                                [(set (v8i8 VPR64:$Rd),
1388                                   (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1389                                 NoItinerary> {
1390   let cmode = 0b1110;
1391 }
1392
1393 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1394                                 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1395                                 "movi\t$Rd.16b, $Imm",
1396                                 [(set (v16i8 VPR128:$Rd),
1397                                    (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1398                                  NoItinerary> {
1399   let cmode = 0b1110;
1400 }
1401 }
1402
1403 // Vector Move Immediate - bytemask, per double word
1404 let isReMaterializable = 1 in {
1405 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1406                                (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1407                                "movi\t $Rd.2d, $Imm",
1408                                [(set (v2i64 VPR128:$Rd),
1409                                   (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1410                                NoItinerary> {
1411   let cmode = 0b1110;
1412 }
1413 }
1414
1415 // Vector Move Immediate - bytemask, one doubleword
1416
1417 let isReMaterializable = 1 in {
1418 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1419                            (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1420                            "movi\t $Rd, $Imm",
1421                            [(set (f64 FPR64:$Rd),
1422                               (f64 (bitconvert
1423                                 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))))],
1424                            NoItinerary> {
1425   let cmode = 0b1110;
1426 }
1427 }
1428
1429 // Vector Floating Point Move Immediate
1430
1431 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1432                       Operand immOpType, bit q, bit op>
1433   : NeonI_1VModImm<q, op,
1434                    (outs VPRC:$Rd), (ins immOpType:$Imm),
1435                    "fmov\t$Rd" # asmlane # ", $Imm",
1436                    [(set (OpTy VPRC:$Rd),
1437                       (OpTy (Neon_fmovi (timm:$Imm))))],
1438                    NoItinerary> {
1439      let cmode = 0b1111;
1440    }
1441
1442 let isReMaterializable = 1 in {
1443 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64,  v2f32, fmov32_operand, 0b0, 0b0>;
1444 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1445 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1446 }
1447
1448 // Vector Shift (Immediate)
1449 // Immediate in [0, 63]
1450 def imm0_63 : Operand<i32> {
1451   let ParserMatchClass = uimm6_asmoperand;
1452 }
1453
1454 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1455 // as follows:
1456 //
1457 //    Offset    Encoding
1458 //     8        immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1459 //     16       immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1460 //     32       immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1461 //     64       immh:immb<6>   = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1462 //
1463 // The shift right immediate amount, in the range 1 to element bits, is computed
1464 // as Offset - UInt(immh:immb).  The shift left immediate amount, in the range 0
1465 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1466
1467 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1468   let Name = "ShrImm" # OFFSET;
1469   let RenderMethod = "addImmOperands";
1470   let DiagnosticType = "ShrImm" # OFFSET;
1471 }
1472
1473 class shr_imm<string OFFSET> : Operand<i32> {
1474   let EncoderMethod = "getShiftRightImm" # OFFSET;
1475   let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1476   let ParserMatchClass =
1477     !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1478 }
1479
1480 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1481 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1482 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1483 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1484
1485 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1486 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1487 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1488 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1489
1490 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1491   let Name = "ShlImm" # OFFSET;
1492   let RenderMethod = "addImmOperands";
1493   let DiagnosticType = "ShlImm" # OFFSET;
1494 }
1495
1496 class shl_imm<string OFFSET> : Operand<i32> {
1497   let EncoderMethod = "getShiftLeftImm" # OFFSET;
1498   let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1499   let ParserMatchClass =
1500     !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1501 }
1502
1503 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1504 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1505 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1506 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1507
1508 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1509 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1510 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1511 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1512
1513 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1514                RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1515   : NeonI_2VShiftImm<q, u, opcode,
1516                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1517                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1518                      [(set (Ty VPRC:$Rd),
1519                         (Ty (OpNode (Ty VPRC:$Rn),
1520                           (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1521                      NoItinerary>;
1522
1523 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1524   // 64-bit vector types.
1525   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1526     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1527   }
1528
1529   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1530     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1531   }
1532
1533   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1534     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1535   }
1536
1537   // 128-bit vector types.
1538   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1539     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1540   }
1541
1542   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1543     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1544   }
1545
1546   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1547     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1548   }
1549
1550   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1551     let Inst{22} = 0b1;        // immh:immb = 1xxxxxx
1552   }
1553 }
1554
1555 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1556   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1557                      OpNode> {
1558     let Inst{22-19} = 0b0001;
1559   }
1560
1561   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1562                      OpNode> {
1563     let Inst{22-20} = 0b001;
1564   }
1565
1566   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1567                      OpNode> {
1568      let Inst{22-21} = 0b01;
1569   }
1570
1571   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1572                       OpNode> {
1573                       let Inst{22-19} = 0b0001;
1574                     }
1575
1576   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1577                      OpNode> {
1578                      let Inst{22-20} = 0b001;
1579                     }
1580
1581   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1582                      OpNode> {
1583                       let Inst{22-21} = 0b01;
1584                     }
1585
1586   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1587                      OpNode> {
1588                       let Inst{22} = 0b1;
1589                     }
1590 }
1591
1592 // Shift left
1593 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1594
1595 // Shift right
1596 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1597 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1598
1599 def Neon_High16B : PatFrag<(ops node:$in),
1600                            (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1601 def Neon_High8H  : PatFrag<(ops node:$in),
1602                            (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1603 def Neon_High4S  : PatFrag<(ops node:$in),
1604                            (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1605 def Neon_High2D  : PatFrag<(ops node:$in),
1606                            (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1607 def Neon_High4float : PatFrag<(ops node:$in),
1608                                (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1609 def Neon_High2double : PatFrag<(ops node:$in),
1610                                (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1611
1612 def Neon_Low16B : PatFrag<(ops node:$in),
1613                           (v8i8 (extract_subvector (v16i8 node:$in),
1614                                                    (iPTR 0)))>;
1615 def Neon_Low8H : PatFrag<(ops node:$in),
1616                          (v4i16 (extract_subvector (v8i16 node:$in),
1617                                                    (iPTR 0)))>;
1618 def Neon_Low4S : PatFrag<(ops node:$in),
1619                          (v2i32 (extract_subvector (v4i32 node:$in),
1620                                                    (iPTR 0)))>;
1621 def Neon_Low2D : PatFrag<(ops node:$in),
1622                          (v1i64 (extract_subvector (v2i64 node:$in),
1623                                                    (iPTR 0)))>;
1624 def Neon_Low4float : PatFrag<(ops node:$in),
1625                              (v2f32 (extract_subvector (v4f32 node:$in),
1626                                                        (iPTR 0)))>;
1627 def Neon_Low2double : PatFrag<(ops node:$in),
1628                               (v1f64 (extract_subvector (v2f64 node:$in),
1629                                                         (iPTR 0)))>;
1630
1631 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1632                    string SrcT, ValueType DestTy, ValueType SrcTy,
1633                    Operand ImmTy, SDPatternOperator ExtOp>
1634   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1635                      (ins VPR64:$Rn, ImmTy:$Imm),
1636                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1637                      [(set (DestTy VPR128:$Rd),
1638                         (DestTy (shl
1639                           (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1640                             (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1641                      NoItinerary>;
1642
1643 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1644                        string SrcT, ValueType DestTy, ValueType SrcTy,
1645                        int StartIndex, Operand ImmTy,
1646                        SDPatternOperator ExtOp, PatFrag getTop>
1647   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1648                      (ins VPR128:$Rn, ImmTy:$Imm),
1649                      asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1650                      [(set (DestTy VPR128:$Rd),
1651                         (DestTy (shl
1652                           (DestTy (ExtOp
1653                             (SrcTy (getTop VPR128:$Rn)))),
1654                               (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1655                      NoItinerary>;
1656
1657 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1658                          SDNode ExtOp> {
1659   // 64-bit vector types.
1660   def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1661                          shl_imm8, ExtOp> {
1662     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1663   }
1664
1665   def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1666                          shl_imm16, ExtOp> {
1667     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1668   }
1669
1670   def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1671                          shl_imm32, ExtOp> {
1672     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1673   }
1674
1675   // 128-bit vector types
1676   def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1677                               8, shl_imm8, ExtOp, Neon_High16B> {
1678     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1679   }
1680
1681   def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1682                              4, shl_imm16, ExtOp, Neon_High8H> {
1683     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1684   }
1685
1686   def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1687                              2, shl_imm32, ExtOp, Neon_High4S> {
1688     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1689   }
1690
1691   // Use other patterns to match when the immediate is 0.
1692   def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1693             (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1694
1695   def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1696             (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1697
1698   def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1699             (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1700
1701   def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1702             (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1703
1704   def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1705             (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1706
1707   def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1708             (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1709 }
1710
1711 // Shift left long
1712 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1713 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1714
1715 // Rounding/Saturating shift
1716 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1717                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1718                   SDPatternOperator OpNode>
1719   : NeonI_2VShiftImm<q, u, opcode,
1720                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1721                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1722                      [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1723                         (i32 ImmTy:$Imm))))],
1724                      NoItinerary>;
1725
1726 // shift right (vector by immediate)
1727 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1728                            SDPatternOperator OpNode> {
1729   def _8B  : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1730                          OpNode> {
1731     let Inst{22-19} = 0b0001;
1732   }
1733
1734   def _4H  : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1735                          OpNode> {
1736     let Inst{22-20} = 0b001;
1737   }
1738
1739   def _2S  : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1740                          OpNode> {
1741     let Inst{22-21} = 0b01;
1742   }
1743
1744   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1745                          OpNode> {
1746     let Inst{22-19} = 0b0001;
1747   }
1748
1749   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1750                         OpNode> {
1751     let Inst{22-20} = 0b001;
1752   }
1753
1754   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1755                         OpNode> {
1756     let Inst{22-21} = 0b01;
1757   }
1758
1759   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1760                         OpNode> {
1761     let Inst{22} = 0b1;
1762   }
1763 }
1764
1765 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1766                           SDPatternOperator OpNode> {
1767   // 64-bit vector types.
1768   def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1769                         OpNode> {
1770     let Inst{22-19} = 0b0001;
1771   }
1772
1773   def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1774                         OpNode> {
1775     let Inst{22-20} = 0b001;
1776   }
1777
1778   def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1779                         OpNode> {
1780     let Inst{22-21} = 0b01;
1781   }
1782
1783   // 128-bit vector types.
1784   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1785                          OpNode> {
1786     let Inst{22-19} = 0b0001;
1787   }
1788
1789   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1790                         OpNode> {
1791     let Inst{22-20} = 0b001;
1792   }
1793
1794   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1795                         OpNode> {
1796     let Inst{22-21} = 0b01;
1797   }
1798
1799   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1800                         OpNode> {
1801     let Inst{22} = 0b1;
1802   }
1803 }
1804
1805 // Rounding shift right
1806 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1807                                 int_aarch64_neon_vsrshr>;
1808 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1809                                 int_aarch64_neon_vurshr>;
1810
1811 // Saturating shift left unsigned
1812 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1813
1814 // Saturating shift left
1815 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1816 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1817
1818 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1819                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1820                   SDNode OpNode>
1821   : NeonI_2VShiftImm<q, u, opcode,
1822            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1823            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1824            [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1825               (Ty (OpNode (Ty VPRC:$Rn),
1826                 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
1827            NoItinerary> {
1828   let Constraints = "$src = $Rd";
1829 }
1830
1831 // Shift Right accumulate
1832 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1833   def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1834                         OpNode> {
1835     let Inst{22-19} = 0b0001;
1836   }
1837
1838   def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1839                         OpNode> {
1840     let Inst{22-20} = 0b001;
1841   }
1842
1843   def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1844                         OpNode> {
1845     let Inst{22-21} = 0b01;
1846   }
1847
1848   def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1849                          OpNode> {
1850     let Inst{22-19} = 0b0001;
1851   }
1852
1853   def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1854                         OpNode> {
1855     let Inst{22-20} = 0b001;
1856   }
1857
1858   def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1859                         OpNode> {
1860     let Inst{22-21} = 0b01;
1861   }
1862
1863   def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1864                         OpNode> {
1865     let Inst{22} = 0b1;
1866   }
1867 }
1868
1869 // Shift right and accumulate
1870 defm SSRAvvi    : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1871 defm USRAvvi    : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1872
1873 // Rounding shift accumulate
1874 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1875                     RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1876                     SDPatternOperator OpNode>
1877   : NeonI_2VShiftImm<q, u, opcode,
1878                      (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1879                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1880                      [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1881                         (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
1882                      NoItinerary> {
1883   let Constraints = "$src = $Rd";
1884 }
1885
1886 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1887                              SDPatternOperator OpNode> {
1888   def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1889                           OpNode> {
1890     let Inst{22-19} = 0b0001;
1891   }
1892
1893   def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1894                           OpNode> {
1895     let Inst{22-20} = 0b001;
1896   }
1897
1898   def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1899                           OpNode> {
1900     let Inst{22-21} = 0b01;
1901   }
1902
1903   def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1904                            OpNode> {
1905     let Inst{22-19} = 0b0001;
1906   }
1907
1908   def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1909                           OpNode> {
1910     let Inst{22-20} = 0b001;
1911   }
1912
1913   def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1914                           OpNode> {
1915     let Inst{22-21} = 0b01;
1916   }
1917
1918   def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1919                           OpNode> {
1920     let Inst{22} = 0b1;
1921   }
1922 }
1923
1924 // Rounding shift right and accumulate
1925 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1926 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1927
1928 // Shift insert by immediate
1929 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1930                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1931                   SDPatternOperator OpNode>
1932     : NeonI_2VShiftImm<q, u, opcode,
1933            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1934            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1935            [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1936              (i32 ImmTy:$Imm))))],
1937            NoItinerary> {
1938   let Constraints = "$src = $Rd";
1939 }
1940
1941 // shift left insert (vector by immediate)
1942 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1943   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1944                         int_aarch64_neon_vsli> {
1945     let Inst{22-19} = 0b0001;
1946   }
1947
1948   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1949                         int_aarch64_neon_vsli> {
1950     let Inst{22-20} = 0b001;
1951   }
1952
1953   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1954                         int_aarch64_neon_vsli> {
1955     let Inst{22-21} = 0b01;
1956   }
1957
1958     // 128-bit vector types
1959   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1960                          int_aarch64_neon_vsli> {
1961     let Inst{22-19} = 0b0001;
1962   }
1963
1964   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1965                         int_aarch64_neon_vsli> {
1966     let Inst{22-20} = 0b001;
1967   }
1968
1969   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1970                         int_aarch64_neon_vsli> {
1971     let Inst{22-21} = 0b01;
1972   }
1973
1974   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1975                         int_aarch64_neon_vsli> {
1976     let Inst{22} = 0b1;
1977   }
1978 }
1979
1980 // shift right insert (vector by immediate)
1981 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
1982     // 64-bit vector types.
1983   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1984                         int_aarch64_neon_vsri> {
1985     let Inst{22-19} = 0b0001;
1986   }
1987
1988   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1989                         int_aarch64_neon_vsri> {
1990     let Inst{22-20} = 0b001;
1991   }
1992
1993   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1994                         int_aarch64_neon_vsri> {
1995     let Inst{22-21} = 0b01;
1996   }
1997
1998     // 128-bit vector types
1999   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2000                          int_aarch64_neon_vsri> {
2001     let Inst{22-19} = 0b0001;
2002   }
2003
2004   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2005                         int_aarch64_neon_vsri> {
2006     let Inst{22-20} = 0b001;
2007   }
2008
2009   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2010                         int_aarch64_neon_vsri> {
2011     let Inst{22-21} = 0b01;
2012   }
2013
2014   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2015                         int_aarch64_neon_vsri> {
2016     let Inst{22} = 0b1;
2017   }
2018 }
2019
2020 // Shift left and insert
2021 defm SLIvvi   : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2022
2023 // Shift right and insert
2024 defm SRIvvi   : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2025
2026 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2027                     string SrcT, Operand ImmTy>
2028   : NeonI_2VShiftImm<q, u, opcode,
2029                      (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2030                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2031                      [], NoItinerary>;
2032
2033 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2034                        string SrcT, Operand ImmTy>
2035   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2036                      (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2037                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2038                      [], NoItinerary> {
2039   let Constraints = "$src = $Rd";
2040 }
2041
2042 // left long shift by immediate
2043 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2044   def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2045     let Inst{22-19} = 0b0001;
2046   }
2047
2048   def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2049     let Inst{22-20} = 0b001;
2050   }
2051
2052   def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2053     let Inst{22-21} = 0b01;
2054   }
2055
2056   // Shift Narrow High
2057   def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2058                               shr_imm8> {
2059     let Inst{22-19} = 0b0001;
2060   }
2061
2062   def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2063                              shr_imm16> {
2064     let Inst{22-20} = 0b001;
2065   }
2066
2067   def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2068                              shr_imm32> {
2069     let Inst{22-21} = 0b01;
2070   }
2071 }
2072
2073 // Shift right narrow
2074 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2075
2076 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2077 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2078 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2079 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2080 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2081 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2082 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2083 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2084
2085 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2086                               (v2i64 (concat_vectors (v1i64 node:$Rm),
2087                                                      (v1i64 node:$Rn)))>;
2088 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2089                               (v8i16 (concat_vectors (v4i16 node:$Rm),
2090                                                      (v4i16 node:$Rn)))>;
2091 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2092                               (v4i32 (concat_vectors (v2i32 node:$Rm),
2093                                                      (v2i32 node:$Rn)))>;
2094 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2095                               (v4f32 (concat_vectors (v2f32 node:$Rm),
2096                                                      (v2f32 node:$Rn)))>;
2097 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2098                               (v2f64 (concat_vectors (v1f64 node:$Rm),
2099                                                      (v1f64 node:$Rn)))>;
2100
2101 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2102                              (v8i16 (srl (v8i16 node:$lhs),
2103                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2104 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2105                              (v4i32 (srl (v4i32 node:$lhs),
2106                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2107 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2108                              (v2i64 (srl (v2i64 node:$lhs),
2109                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2110 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2111                              (v8i16 (sra (v8i16 node:$lhs),
2112                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2113 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2114                              (v4i32 (sra (v4i32 node:$lhs),
2115                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2116 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2117                              (v2i64 (sra (v2i64 node:$lhs),
2118                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2119
2120 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2121 multiclass Neon_shiftNarrow_patterns<string shr> {
2122   def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2123               (i32 shr_imm8:$Imm)))),
2124             (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2125   def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2126               (i32 shr_imm16:$Imm)))),
2127             (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2128   def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2129               (i32 shr_imm32:$Imm)))),
2130             (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2131
2132   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2133               (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2134                 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2135             (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2136                          VPR128:$Rn, imm:$Imm)>;
2137   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2138               (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2139                 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2140             (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2141                         VPR128:$Rn, imm:$Imm)>;
2142   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2143               (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2144                 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2145             (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2146                         VPR128:$Rn, imm:$Imm)>;
2147 }
2148
2149 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2150   def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2151             (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2152   def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2153             (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2154   def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2155             (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2156
2157   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2158                 (v1i64 (bitconvert (v8i8
2159                     (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2160             (!cast<Instruction>(prefix # "_16B")
2161                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2162                 VPR128:$Rn, imm:$Imm)>;
2163   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2164                 (v1i64 (bitconvert (v4i16
2165                     (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2166             (!cast<Instruction>(prefix # "_8H")
2167                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2168                 VPR128:$Rn, imm:$Imm)>;
2169   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2170                 (v1i64 (bitconvert (v2i32
2171                     (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2172             (!cast<Instruction>(prefix # "_4S")
2173                   (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2174                   VPR128:$Rn, imm:$Imm)>;
2175 }
2176
2177 defm : Neon_shiftNarrow_patterns<"lshr">;
2178 defm : Neon_shiftNarrow_patterns<"ashr">;
2179
2180 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2181 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2182 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2183 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2184 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2185 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2186 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2187
2188 // Convert fix-point and float-pointing
2189 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2190                 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2191                 Operand ImmTy, SDPatternOperator IntOp>
2192   : NeonI_2VShiftImm<q, u, opcode,
2193                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2194                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2195                      [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2196                        (i32 ImmTy:$Imm))))],
2197                      NoItinerary>;
2198
2199 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2200                               SDPatternOperator IntOp> {
2201   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2202                       shr_imm32, IntOp> {
2203     let Inst{22-21} = 0b01;
2204   }
2205
2206   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2207                       shr_imm32, IntOp> {
2208     let Inst{22-21} = 0b01;
2209   }
2210
2211   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2212                       shr_imm64, IntOp> {
2213     let Inst{22} = 0b1;
2214   }
2215 }
2216
2217 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2218                               SDPatternOperator IntOp> {
2219   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2220                       shr_imm32, IntOp> {
2221     let Inst{22-21} = 0b01;
2222   }
2223
2224   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2225                       shr_imm32, IntOp> {
2226     let Inst{22-21} = 0b01;
2227   }
2228
2229   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2230                       shr_imm64, IntOp> {
2231     let Inst{22} = 0b1;
2232   }
2233 }
2234
2235 // Convert fixed-point to floating-point
2236 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2237                                    int_arm_neon_vcvtfxs2fp>;
2238 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2239                                    int_arm_neon_vcvtfxu2fp>;
2240
2241 // Convert floating-point to fixed-point
2242 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2243                                    int_arm_neon_vcvtfp2fxs>;
2244 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2245                                    int_arm_neon_vcvtfp2fxu>;
2246
2247 multiclass Neon_sshll2_0<SDNode ext>
2248 {
2249   def _v8i8  : PatFrag<(ops node:$Rn),
2250                        (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2251   def _v4i16 : PatFrag<(ops node:$Rn),
2252                        (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2253   def _v2i32 : PatFrag<(ops node:$Rn),
2254                        (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2255 }
2256
2257 defm NI_sext_high : Neon_sshll2_0<sext>;
2258 defm NI_zext_high : Neon_sshll2_0<zext>;
2259
2260
2261 //===----------------------------------------------------------------------===//
2262 // Multiclasses for NeonI_Across
2263 //===----------------------------------------------------------------------===//
2264
2265 // Variant 1
2266
2267 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2268                             string asmop, SDPatternOperator opnode>
2269 {
2270     def _1h8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2271                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2272                 asmop # "\t$Rd, $Rn.8b",
2273                 [(set (v1i16 FPR16:$Rd),
2274                     (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2275                 NoItinerary>;
2276
2277     def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2278                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2279                 asmop # "\t$Rd, $Rn.16b",
2280                 [(set (v1i16 FPR16:$Rd),
2281                     (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2282                 NoItinerary>;
2283
2284     def _1s4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2285                 (outs FPR32:$Rd), (ins VPR64:$Rn),
2286                 asmop # "\t$Rd, $Rn.4h",
2287                 [(set (v1i32 FPR32:$Rd),
2288                     (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2289                 NoItinerary>;
2290
2291     def _1s8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2292                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2293                 asmop # "\t$Rd, $Rn.8h",
2294                 [(set (v1i32 FPR32:$Rd),
2295                     (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2296                 NoItinerary>;
2297
2298     // _1d2s doesn't exist!
2299
2300     def _1d4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2301                 (outs FPR64:$Rd), (ins VPR128:$Rn),
2302                 asmop # "\t$Rd, $Rn.4s",
2303                 [(set (v1i64 FPR64:$Rd),
2304                     (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2305                 NoItinerary>;
2306 }
2307
2308 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2309 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2310
2311 // Variant 2
2312
2313 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2314                             string asmop, SDPatternOperator opnode>
2315 {
2316     def _1b8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2317                 (outs FPR8:$Rd), (ins VPR64:$Rn),
2318                 asmop # "\t$Rd, $Rn.8b",
2319                 [(set (v1i8 FPR8:$Rd),
2320                     (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2321                 NoItinerary>;
2322
2323     def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2324                 (outs FPR8:$Rd), (ins VPR128:$Rn),
2325                 asmop # "\t$Rd, $Rn.16b",
2326                 [(set (v1i8 FPR8:$Rd),
2327                     (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2328                 NoItinerary>;
2329
2330     def _1h4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2331                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2332                 asmop # "\t$Rd, $Rn.4h",
2333                 [(set (v1i16 FPR16:$Rd),
2334                     (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2335                 NoItinerary>;
2336
2337     def _1h8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2338                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2339                 asmop # "\t$Rd, $Rn.8h",
2340                 [(set (v1i16 FPR16:$Rd),
2341                     (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2342                 NoItinerary>;
2343
2344     // _1s2s doesn't exist!
2345
2346     def _1s4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2347                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2348                 asmop # "\t$Rd, $Rn.4s",
2349                 [(set (v1i32 FPR32:$Rd),
2350                     (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2351                 NoItinerary>;
2352 }
2353
2354 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2355 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2356
2357 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2358 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2359
2360 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2361
2362 // Variant 3
2363
2364 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2365                             string asmop, SDPatternOperator opnode> {
2366     def _1s4s:  NeonI_2VAcross<0b1, u, size, opcode,
2367                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2368                 asmop # "\t$Rd, $Rn.4s",
2369                 [(set (v1f32 FPR32:$Rd),
2370                     (v1f32 (opnode (v4f32 VPR128:$Rn))))],
2371                 NoItinerary>;
2372 }
2373
2374 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2375                                 int_aarch64_neon_vmaxnmv>;
2376 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2377                                 int_aarch64_neon_vminnmv>;
2378
2379 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2380                               int_aarch64_neon_vmaxv>;
2381 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2382                               int_aarch64_neon_vminv>;
2383
2384 // The followings are for instruction class (Perm)
2385
2386 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2387                     string asmop, RegisterOperand OpVPR, string OpS,
2388                     SDPatternOperator opnode, ValueType Ty>
2389   : NeonI_Perm<q, size, opcode,
2390                (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2391                asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2392                [(set (Ty OpVPR:$Rd),
2393                   (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2394                NoItinerary>;
2395
2396 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2397                           SDPatternOperator opnode> {
2398   def _8b  : NeonI_Permute<0b0, 0b00, opcode, asmop,
2399                            VPR64, "8b", opnode, v8i8>;
2400   def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2401                            VPR128, "16b",opnode, v16i8>;
2402   def _4h  : NeonI_Permute<0b0, 0b01, opcode, asmop,
2403                            VPR64, "4h", opnode, v4i16>;
2404   def _8h  : NeonI_Permute<0b1, 0b01, opcode, asmop,
2405                            VPR128, "8h", opnode, v8i16>;
2406   def _2s  : NeonI_Permute<0b0, 0b10, opcode, asmop,
2407                            VPR64, "2s", opnode, v2i32>;
2408   def _4s  : NeonI_Permute<0b1, 0b10, opcode, asmop,
2409                            VPR128, "4s", opnode, v4i32>;
2410   def _2d  : NeonI_Permute<0b1, 0b11, opcode, asmop,
2411                            VPR128, "2d", opnode, v2i64>;
2412 }
2413
2414 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2415 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2416 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2417 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2418 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2419 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2420
2421 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2422   def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2423             (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2424
2425   def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2426             (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2427
2428   def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2429             (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2430 }
2431
2432 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2433 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2434 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2435 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2436 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2437 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2438
2439 // The followings are for instruction class (3V Diff)
2440
2441 // normal long/long2 pattern
2442 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2443                  string asmop, string ResS, string OpS,
2444                  SDPatternOperator opnode, SDPatternOperator ext,
2445                  RegisterOperand OpVPR,
2446                  ValueType ResTy, ValueType OpTy>
2447   : NeonI_3VDiff<q, u, size, opcode,
2448                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2449                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2450                  [(set (ResTy VPR128:$Rd),
2451                     (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2452                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2453                  NoItinerary>;
2454
2455 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2456                         string asmop, SDPatternOperator opnode,
2457                         bit Commutable = 0> {
2458   let isCommutable = Commutable in {
2459     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2460                            opnode, sext, VPR64, v8i16, v8i8>;
2461     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2462                            opnode, sext, VPR64, v4i32, v4i16>;
2463     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2464                            opnode, sext, VPR64, v2i64, v2i32>;
2465   }
2466 }
2467
2468 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2469                          SDPatternOperator opnode, bit Commutable = 0> {
2470   let isCommutable = Commutable in {
2471     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2472                             opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2473     def _4s8h  : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2474                             opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2475     def _2d4s  : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2476                             opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2477   }
2478 }
2479
2480 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2481                         SDPatternOperator opnode, bit Commutable = 0> {
2482   let isCommutable = Commutable in {
2483     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2484                            opnode, zext, VPR64, v8i16, v8i8>;
2485     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2486                            opnode, zext, VPR64, v4i32, v4i16>;
2487     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2488                            opnode, zext, VPR64, v2i64, v2i32>;
2489   }
2490 }
2491
2492 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2493                          SDPatternOperator opnode, bit Commutable = 0> {
2494   let isCommutable = Commutable in {
2495     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2496                             opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2497     def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2498                            opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2499     def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2500                            opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2501   }
2502 }
2503
2504 defm SADDLvvv :  NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2505 defm UADDLvvv :  NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2506
2507 defm SADDL2vvv :  NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2508 defm UADDL2vvv :  NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2509
2510 defm SSUBLvvv :  NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2511 defm USUBLvvv :  NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2512
2513 defm SSUBL2vvv :  NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2514 defm USUBL2vvv :  NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2515
2516 // normal wide/wide2 pattern
2517 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2518                  string asmop, string ResS, string OpS,
2519                  SDPatternOperator opnode, SDPatternOperator ext,
2520                  RegisterOperand OpVPR,
2521                  ValueType ResTy, ValueType OpTy>
2522   : NeonI_3VDiff<q, u, size, opcode,
2523                  (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2524                  asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2525                  [(set (ResTy VPR128:$Rd),
2526                     (ResTy (opnode (ResTy VPR128:$Rn),
2527                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2528                  NoItinerary>;
2529
2530 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2531                         SDPatternOperator opnode> {
2532   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2533                          opnode, sext, VPR64, v8i16, v8i8>;
2534   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2535                          opnode, sext, VPR64, v4i32, v4i16>;
2536   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2537                          opnode, sext, VPR64, v2i64, v2i32>;
2538 }
2539
2540 defm SADDWvvv :  NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2541 defm SSUBWvvv :  NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2542
2543 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2544                          SDPatternOperator opnode> {
2545   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2546                           opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2547   def _4s8h  : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2548                           opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2549   def _2d4s  : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2550                           opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2551 }
2552
2553 defm SADDW2vvv :  NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2554 defm SSUBW2vvv :  NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2555
2556 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2557                         SDPatternOperator opnode> {
2558   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2559                          opnode, zext, VPR64, v8i16, v8i8>;
2560   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2561                          opnode, zext, VPR64, v4i32, v4i16>;
2562   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2563                          opnode, zext, VPR64, v2i64, v2i32>;
2564 }
2565
2566 defm UADDWvvv :  NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2567 defm USUBWvvv :  NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2568
2569 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2570                          SDPatternOperator opnode> {
2571   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2572                           opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2573   def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2574                          opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2575   def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2576                          opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2577 }
2578
2579 defm UADDW2vvv :  NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2580 defm USUBW2vvv :  NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2581
2582 // Get the high half part of the vector element.
2583 multiclass NeonI_get_high {
2584   def _8h : PatFrag<(ops node:$Rn),
2585                     (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2586                                              (v8i16 (Neon_vdup (i32 8)))))))>;
2587   def _4s : PatFrag<(ops node:$Rn),
2588                     (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2589                                               (v4i32 (Neon_vdup (i32 16)))))))>;
2590   def _2d : PatFrag<(ops node:$Rn),
2591                     (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2592                                               (v2i64 (Neon_vdup (i32 32)))))))>;
2593 }
2594
2595 defm NI_get_hi : NeonI_get_high;
2596
2597 // pattern for addhn/subhn with 2 operands
2598 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2599                            string asmop, string ResS, string OpS,
2600                            SDPatternOperator opnode, SDPatternOperator get_hi,
2601                            ValueType ResTy, ValueType OpTy>
2602   : NeonI_3VDiff<q, u, size, opcode,
2603                  (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2604                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2605                  [(set (ResTy VPR64:$Rd),
2606                     (ResTy (get_hi
2607                       (OpTy (opnode (OpTy VPR128:$Rn),
2608                                     (OpTy VPR128:$Rm))))))],
2609                  NoItinerary>;
2610
2611 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2612                                 SDPatternOperator opnode, bit Commutable = 0> {
2613   let isCommutable = Commutable in {
2614     def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2615                                      opnode, NI_get_hi_8h, v8i8, v8i16>;
2616     def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2617                                      opnode, NI_get_hi_4s, v4i16, v4i32>;
2618     def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2619                                      opnode, NI_get_hi_2d, v2i32, v2i64>;
2620   }
2621 }
2622
2623 defm ADDHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2624 defm SUBHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2625
2626 // pattern for operation with 2 operands
2627 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2628                     string asmop, string ResS, string OpS,
2629                     SDPatternOperator opnode,
2630                     RegisterOperand ResVPR, RegisterOperand OpVPR,
2631                     ValueType ResTy, ValueType OpTy>
2632   : NeonI_3VDiff<q, u, size, opcode,
2633                  (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2634                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2635                  [(set (ResTy ResVPR:$Rd),
2636                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2637                  NoItinerary>;
2638
2639 // normal narrow pattern
2640 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2641                           SDPatternOperator opnode, bit Commutable = 0> {
2642   let isCommutable = Commutable in {
2643     def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2644                               opnode, VPR64, VPR128, v8i8, v8i16>;
2645     def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2646                               opnode, VPR64, VPR128, v4i16, v4i32>;
2647     def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2648                               opnode, VPR64, VPR128, v2i32, v2i64>;
2649   }
2650 }
2651
2652 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2653 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2654
2655 // pattern for acle intrinsic with 3 operands
2656 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2657                      string asmop, string ResS, string OpS>
2658   : NeonI_3VDiff<q, u, size, opcode,
2659                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2660                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2661                  [], NoItinerary> {
2662   let Constraints = "$src = $Rd";
2663   let neverHasSideEffects = 1;
2664 }
2665
2666 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2667   def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2668   def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2669   def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2670 }
2671
2672 defm ADDHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2673 defm SUBHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2674
2675 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2676 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2677
2678 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2679 // part.
2680 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2681                         SDPatternOperator coreop>
2682   : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2683                       (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2684                                                         (SrcTy VPR128:$Rm)))))),
2685         (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2686               VPR128:$Rn, VPR128:$Rm)>;
2687
2688 // addhn2 patterns
2689 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8,  v8i16,
2690           BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2691 def : NarrowHighHalfPat<ADDHN2vvv_8h4s,  v4i16, v4i32,
2692           BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2693 def : NarrowHighHalfPat<ADDHN2vvv_4s2d,  v2i32, v2i64,
2694           BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2695
2696 // subhn2 patterns
2697 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8,  v8i16,
2698           BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2699 def : NarrowHighHalfPat<SUBHN2vvv_8h4s,  v4i16, v4i32,
2700           BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2701 def : NarrowHighHalfPat<SUBHN2vvv_4s2d,  v2i32, v2i64,
2702           BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2703
2704 // raddhn2 patterns
2705 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vraddhn>;
2706 def : NarrowHighHalfPat<RADDHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vraddhn>;
2707 def : NarrowHighHalfPat<RADDHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vraddhn>;
2708
2709 // rsubhn2 patterns
2710 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vrsubhn>;
2711 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vrsubhn>;
2712 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vrsubhn>;
2713
2714 // pattern that need to extend result
2715 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2716                      string asmop, string ResS, string OpS,
2717                      SDPatternOperator opnode,
2718                      RegisterOperand OpVPR,
2719                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2720   : NeonI_3VDiff<q, u, size, opcode,
2721                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2722                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2723                  [(set (ResTy VPR128:$Rd),
2724                     (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2725                                                 (OpTy OpVPR:$Rm))))))],
2726                  NoItinerary>;
2727
2728 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2729                            SDPatternOperator opnode, bit Commutable = 0> {
2730   let isCommutable = Commutable in {
2731     def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2732                                opnode, VPR64, v8i16, v8i8, v8i8>;
2733     def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2734                                opnode, VPR64, v4i32, v4i16, v4i16>;
2735     def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2736                                opnode, VPR64, v2i64, v2i32, v2i32>;
2737   }
2738 }
2739
2740 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2741 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2742
2743 multiclass NeonI_Op_High<SDPatternOperator op> {
2744   def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2745                      (op (v8i8 (Neon_High16B node:$Rn)),
2746                          (v8i8 (Neon_High16B node:$Rm)))>;
2747   def _8H  : PatFrag<(ops node:$Rn, node:$Rm),
2748                      (op (v4i16 (Neon_High8H node:$Rn)),
2749                          (v4i16 (Neon_High8H node:$Rm)))>;
2750   def _4S  : PatFrag<(ops node:$Rn, node:$Rm),
2751                      (op (v2i32 (Neon_High4S node:$Rn)),
2752                          (v2i32 (Neon_High4S node:$Rm)))>;
2753 }
2754
2755 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2756 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2757 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2758 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2759 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2760 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2761
2762 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2763                             bit Commutable = 0> {
2764   let isCommutable = Commutable in {
2765     def _8h8b  : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2766                                 !cast<PatFrag>(opnode # "_16B"),
2767                                 VPR128, v8i16, v16i8, v8i8>;
2768     def _4s4h  : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2769                                 !cast<PatFrag>(opnode # "_8H"),
2770                                 VPR128, v4i32, v8i16, v4i16>;
2771     def _2d2s  : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2772                                 !cast<PatFrag>(opnode # "_4S"),
2773                                 VPR128, v2i64, v4i32, v2i32>;
2774   }
2775 }
2776
2777 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2778 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2779
2780 // For pattern that need two operators being chained.
2781 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2782                      string asmop, string ResS, string OpS,
2783                      SDPatternOperator opnode, SDPatternOperator subop,
2784                      RegisterOperand OpVPR,
2785                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2786   : NeonI_3VDiff<q, u, size, opcode,
2787                  (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2788                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2789                  [(set (ResTy VPR128:$Rd),
2790                     (ResTy (opnode
2791                       (ResTy VPR128:$src),
2792                       (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2793                                                  (OpTy OpVPR:$Rm))))))))],
2794                  NoItinerary> {
2795   let Constraints = "$src = $Rd";
2796 }
2797
2798 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2799                              SDPatternOperator opnode, SDPatternOperator subop>{
2800   def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2801                              opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2802   def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2803                              opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2804   def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2805                              opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2806 }
2807
2808 defm SABALvvv :  NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2809                                    add, int_arm_neon_vabds>;
2810 defm UABALvvv :  NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2811                                    add, int_arm_neon_vabdu>;
2812
2813 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2814                               SDPatternOperator opnode, string subop> {
2815   def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2816                              opnode, !cast<PatFrag>(subop # "_16B"),
2817                              VPR128, v8i16, v16i8, v8i8>;
2818   def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2819                              opnode, !cast<PatFrag>(subop # "_8H"),
2820                              VPR128, v4i32, v8i16, v4i16>;
2821   def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2822                              opnode, !cast<PatFrag>(subop # "_4S"),
2823                              VPR128, v2i64, v4i32, v2i32>;
2824 }
2825
2826 defm SABAL2vvv :  NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2827                                      "NI_sabdl_hi">;
2828 defm UABAL2vvv :  NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2829                                      "NI_uabdl_hi">;
2830
2831 // Long pattern with 2 operands
2832 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
2833                           SDPatternOperator opnode, bit Commutable = 0> {
2834   let isCommutable = Commutable in {
2835     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2836                               opnode, VPR128, VPR64, v8i16, v8i8>;
2837     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2838                               opnode, VPR128, VPR64, v4i32, v4i16>;
2839     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2840                               opnode, VPR128, VPR64, v2i64, v2i32>;
2841   }
2842 }
2843
2844 defm SMULLvvv :  NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
2845 defm UMULLvvv :  NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
2846
2847 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
2848                            string asmop, string ResS, string OpS,
2849                            SDPatternOperator opnode,
2850                            ValueType ResTy, ValueType OpTy>
2851   : NeonI_3VDiff<q, u, size, opcode,
2852                  (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2853                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2854                  [(set (ResTy VPR128:$Rd),
2855                     (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
2856                  NoItinerary>;
2857
2858 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
2859                                    string opnode, bit Commutable = 0> {
2860   let isCommutable = Commutable in {
2861     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2862                                       !cast<PatFrag>(opnode # "_16B"),
2863                                       v8i16, v16i8>;
2864     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2865                                      !cast<PatFrag>(opnode # "_8H"),
2866                                      v4i32, v8i16>;
2867     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2868                                      !cast<PatFrag>(opnode # "_4S"),
2869                                      v2i64, v4i32>;
2870   }
2871 }
2872
2873 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
2874                                          "NI_smull_hi", 1>;
2875 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
2876                                          "NI_umull_hi", 1>;
2877
2878 // Long pattern with 3 operands
2879 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2880                      string asmop, string ResS, string OpS,
2881                      SDPatternOperator opnode,
2882                      ValueType ResTy, ValueType OpTy>
2883   : NeonI_3VDiff<q, u, size, opcode,
2884                  (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
2885                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2886                  [(set (ResTy VPR128:$Rd),
2887                     (ResTy (opnode
2888                       (ResTy VPR128:$src),
2889                       (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
2890                NoItinerary> {
2891   let Constraints = "$src = $Rd";
2892 }
2893
2894 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
2895                              SDPatternOperator opnode> {
2896   def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2897                              opnode, v8i16, v8i8>;
2898   def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2899                              opnode, v4i32, v4i16>;
2900   def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2901                              opnode, v2i64, v2i32>;
2902 }
2903
2904 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2905                          (add node:$Rd,
2906                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2907
2908 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2909                          (add node:$Rd,
2910                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2911
2912 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2913                          (sub node:$Rd,
2914                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2915
2916 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2917                          (sub node:$Rd,
2918                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2919
2920 defm SMLALvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
2921 defm UMLALvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
2922
2923 defm SMLSLvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
2924 defm UMLSLvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
2925
2926 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
2927                            string asmop, string ResS, string OpS,
2928                            SDPatternOperator subop, SDPatternOperator opnode,
2929                            RegisterOperand OpVPR,
2930                            ValueType ResTy, ValueType OpTy>
2931   : NeonI_3VDiff<q, u, size, opcode,
2932                (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2933                asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2934                [(set (ResTy VPR128:$Rd),
2935                   (ResTy (subop
2936                     (ResTy VPR128:$src),
2937                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
2938                NoItinerary> {
2939   let Constraints = "$src = $Rd";
2940 }
2941
2942 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
2943                                    SDPatternOperator subop, string opnode> {
2944   def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2945                                     subop, !cast<PatFrag>(opnode # "_16B"),
2946                                     VPR128, v8i16, v16i8>;
2947   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2948                                    subop, !cast<PatFrag>(opnode # "_8H"),
2949                                    VPR128, v4i32, v8i16>;
2950   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2951                                    subop, !cast<PatFrag>(opnode # "_4S"),
2952                                    VPR128, v2i64, v4i32>;
2953 }
2954
2955 defm SMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
2956                                           add, "NI_smull_hi">;
2957 defm UMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
2958                                           add, "NI_umull_hi">;
2959
2960 defm SMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
2961                                           sub, "NI_smull_hi">;
2962 defm UMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
2963                                           sub, "NI_umull_hi">;
2964
2965 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
2966                                     SDPatternOperator opnode> {
2967   def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2968                                    opnode, int_arm_neon_vqdmull,
2969                                    VPR64, v4i32, v4i16>;
2970   def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2971                                    opnode, int_arm_neon_vqdmull,
2972                                    VPR64, v2i64, v2i32>;
2973 }
2974
2975 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
2976                                            int_arm_neon_vqadds>;
2977 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
2978                                            int_arm_neon_vqsubs>;
2979
2980 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
2981                          SDPatternOperator opnode, bit Commutable = 0> {
2982   let isCommutable = Commutable in {
2983     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2984                               opnode, VPR128, VPR64, v4i32, v4i16>;
2985     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2986                               opnode, VPR128, VPR64, v2i64, v2i32>;
2987   }
2988 }
2989
2990 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
2991                                 int_arm_neon_vqdmull, 1>;
2992
2993 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
2994                                    string opnode, bit Commutable = 0> {
2995   let isCommutable = Commutable in {
2996     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2997                                      !cast<PatFrag>(opnode # "_8H"),
2998                                      v4i32, v8i16>;
2999     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3000                                      !cast<PatFrag>(opnode # "_4S"),
3001                                      v2i64, v4i32>;
3002   }
3003 }
3004
3005 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3006                                            "NI_qdmull_hi", 1>;
3007
3008 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3009                                      SDPatternOperator opnode> {
3010   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3011                                    opnode, NI_qdmull_hi_8H,
3012                                    VPR128, v4i32, v8i16>;
3013   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3014                                    opnode, NI_qdmull_hi_4S,
3015                                    VPR128, v2i64, v4i32>;
3016 }
3017
3018 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3019                                              int_arm_neon_vqadds>;
3020 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3021                                              int_arm_neon_vqsubs>;
3022
3023 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3024                          SDPatternOperator opnode, bit Commutable = 0> {
3025   let isCommutable = Commutable in {
3026     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3027                               opnode, VPR128, VPR64, v8i16, v8i8>;
3028
3029     def _1q1d : NeonI_3VDiff<0b0, u, 0b11, opcode,
3030                              (outs VPR128:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
3031                              asmop # "\t$Rd.1q, $Rn.1d, $Rm.1d",
3032                              [], NoItinerary>;
3033   }
3034 }
3035
3036 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp, 1>;
3037
3038 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3039                                    string opnode, bit Commutable = 0> {
3040   let isCommutable = Commutable in {
3041     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3042                                       !cast<PatFrag>(opnode # "_16B"),
3043                                       v8i16, v16i8>;
3044
3045     def _1q2d : NeonI_3VDiff<0b1, u, 0b11, opcode,
3046                              (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3047                              asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3048                              [], NoItinerary>;
3049   }
3050 }
3051
3052 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3053                                          1>;
3054
3055 // End of implementation for instruction class (3V Diff)
3056
3057 // The followings are vector load/store multiple N-element structure
3058 // (class SIMD lselem).
3059
3060 // ld1:         load multiple 1-element structure to 1/2/3/4 registers.
3061 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3062 //              The structure consists of a sequence of sets of N values.
3063 //              The first element of the structure is placed in the first lane
3064 //              of the first first vector, the second element in the first lane
3065 //              of the second vector, and so on.
3066 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3067 // the three 64-bit vectors list {BA, DC, FE}.
3068 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3069 // 64-bit vectors list {DA, EB, FC}.
3070 // Store instructions store multiple structure to N registers like load.
3071
3072
3073 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3074                     RegisterOperand VecList, string asmop>
3075   : NeonI_LdStMult<q, 1, opcode, size,
3076                  (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3077                  asmop # "\t$Rt, [$Rn]",
3078                  [],
3079                  NoItinerary> {
3080   let mayLoad = 1;
3081   let neverHasSideEffects = 1;
3082 }
3083
3084 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3085   def _8B : NeonI_LDVList<0, opcode, 0b00,
3086                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3087
3088   def _4H : NeonI_LDVList<0, opcode, 0b01,
3089                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3090
3091   def _2S : NeonI_LDVList<0, opcode, 0b10,
3092                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3093
3094   def _16B : NeonI_LDVList<1, opcode, 0b00,
3095                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3096
3097   def _8H : NeonI_LDVList<1, opcode, 0b01,
3098                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3099
3100   def _4S : NeonI_LDVList<1, opcode, 0b10,
3101                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3102
3103   def _2D : NeonI_LDVList<1, opcode, 0b11,
3104                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3105 }
3106
3107 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3108 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3109 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3110
3111 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3112
3113 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3114
3115 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3116
3117 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3118 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3119 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3120
3121 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3122 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3123
3124 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3125 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3126
3127 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3128                     RegisterOperand VecList, string asmop>
3129   : NeonI_LdStMult<q, 0, opcode, size,
3130                  (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3131                  asmop # "\t$Rt, [$Rn]",
3132                  [],
3133                  NoItinerary> {
3134   let mayStore = 1;
3135   let neverHasSideEffects = 1;
3136 }
3137
3138 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3139   def _8B : NeonI_STVList<0, opcode, 0b00,
3140                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3141
3142   def _4H : NeonI_STVList<0, opcode, 0b01,
3143                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3144
3145   def _2S : NeonI_STVList<0, opcode, 0b10,
3146                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3147
3148   def _16B : NeonI_STVList<1, opcode, 0b00,
3149                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3150
3151   def _8H : NeonI_STVList<1, opcode, 0b01,
3152                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3153
3154   def _4S : NeonI_STVList<1, opcode, 0b10,
3155                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3156
3157   def _2D : NeonI_STVList<1, opcode, 0b11,
3158                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3159 }
3160
3161 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3162 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3163 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3164
3165 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3166
3167 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3168
3169 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3170
3171 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3172 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3173 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3174
3175 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3176 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3177
3178 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3179 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3180
3181 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3182 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3183
3184 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3185 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3186
3187 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3188 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3189
3190 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3191 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3192
3193 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3194 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3195
3196 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3197 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3198
3199 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3200           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3201 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3202           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3203
3204 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3205           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3206 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3207           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3208
3209 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3210           (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3211 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3212           (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3213
3214 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3215           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3216 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3217           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3218
3219 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3220           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3221 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3222           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3223
3224 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3225           (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3226 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3227           (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3228
3229 // End of vector load/store multiple N-element structure(class SIMD lselem)
3230
3231 // The followings are post-index vector load/store multiple N-element
3232 // structure(class SIMD lselem-post)
3233 def exact1_asmoperand : AsmOperandClass {
3234   let Name = "Exact1";
3235   let PredicateMethod = "isExactImm<1>";
3236   let RenderMethod = "addImmOperands";
3237 }
3238 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3239   let ParserMatchClass = exact1_asmoperand;
3240 }
3241
3242 def exact2_asmoperand : AsmOperandClass {
3243   let Name = "Exact2";
3244   let PredicateMethod = "isExactImm<2>";
3245   let RenderMethod = "addImmOperands";
3246 }
3247 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3248   let ParserMatchClass = exact2_asmoperand;
3249 }
3250
3251 def exact3_asmoperand : AsmOperandClass {
3252   let Name = "Exact3";
3253   let PredicateMethod = "isExactImm<3>";
3254   let RenderMethod = "addImmOperands";
3255 }
3256 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3257   let ParserMatchClass = exact3_asmoperand;
3258 }
3259
3260 def exact4_asmoperand : AsmOperandClass {
3261   let Name = "Exact4";
3262   let PredicateMethod = "isExactImm<4>";
3263   let RenderMethod = "addImmOperands";
3264 }
3265 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3266   let ParserMatchClass = exact4_asmoperand;
3267 }
3268
3269 def exact6_asmoperand : AsmOperandClass {
3270   let Name = "Exact6";
3271   let PredicateMethod = "isExactImm<6>";
3272   let RenderMethod = "addImmOperands";
3273 }
3274 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3275   let ParserMatchClass = exact6_asmoperand;
3276 }
3277
3278 def exact8_asmoperand : AsmOperandClass {
3279   let Name = "Exact8";
3280   let PredicateMethod = "isExactImm<8>";
3281   let RenderMethod = "addImmOperands";
3282 }
3283 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3284   let ParserMatchClass = exact8_asmoperand;
3285 }
3286
3287 def exact12_asmoperand : AsmOperandClass {
3288   let Name = "Exact12";
3289   let PredicateMethod = "isExactImm<12>";
3290   let RenderMethod = "addImmOperands";
3291 }
3292 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3293   let ParserMatchClass = exact12_asmoperand;
3294 }
3295
3296 def exact16_asmoperand : AsmOperandClass {
3297   let Name = "Exact16";
3298   let PredicateMethod = "isExactImm<16>";
3299   let RenderMethod = "addImmOperands";
3300 }
3301 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3302   let ParserMatchClass = exact16_asmoperand;
3303 }
3304
3305 def exact24_asmoperand : AsmOperandClass {
3306   let Name = "Exact24";
3307   let PredicateMethod = "isExactImm<24>";
3308   let RenderMethod = "addImmOperands";
3309 }
3310 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3311   let ParserMatchClass = exact24_asmoperand;
3312 }
3313
3314 def exact32_asmoperand : AsmOperandClass {
3315   let Name = "Exact32";
3316   let PredicateMethod = "isExactImm<32>";
3317   let RenderMethod = "addImmOperands";
3318 }
3319 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3320   let ParserMatchClass = exact32_asmoperand;
3321 }
3322
3323 def exact48_asmoperand : AsmOperandClass {
3324   let Name = "Exact48";
3325   let PredicateMethod = "isExactImm<48>";
3326   let RenderMethod = "addImmOperands";
3327 }
3328 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3329   let ParserMatchClass = exact48_asmoperand;
3330 }
3331
3332 def exact64_asmoperand : AsmOperandClass {
3333   let Name = "Exact64";
3334   let PredicateMethod = "isExactImm<64>";
3335   let RenderMethod = "addImmOperands";
3336 }
3337 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3338   let ParserMatchClass = exact64_asmoperand;
3339 }
3340
3341 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3342                            RegisterOperand VecList, Operand ImmTy,
3343                            string asmop> {
3344   let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3345       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3346     def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3347                      (outs VecList:$Rt, GPR64xsp:$wb),
3348                      (ins GPR64xsp:$Rn, ImmTy:$amt),
3349                      asmop # "\t$Rt, [$Rn], $amt",
3350                      [],
3351                      NoItinerary> {
3352       let Rm = 0b11111;
3353     }
3354
3355     def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3356                         (outs VecList:$Rt, GPR64xsp:$wb),
3357                         (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3358                         asmop # "\t$Rt, [$Rn], $Rm",
3359                         [],
3360                         NoItinerary>;
3361   }
3362 }
3363
3364 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3365     Operand ImmTy2, string asmop> {
3366   defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3367                               !cast<RegisterOperand>(List # "8B_operand"),
3368                               ImmTy, asmop>;
3369
3370   defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3371                               !cast<RegisterOperand>(List # "4H_operand"),
3372                               ImmTy, asmop>;
3373
3374   defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3375                               !cast<RegisterOperand>(List # "2S_operand"),
3376                               ImmTy, asmop>;
3377
3378   defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3379                                !cast<RegisterOperand>(List # "16B_operand"),
3380                                ImmTy2, asmop>;
3381
3382   defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3383                               !cast<RegisterOperand>(List # "8H_operand"),
3384                               ImmTy2, asmop>;
3385
3386   defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3387                               !cast<RegisterOperand>(List # "4S_operand"),
3388                               ImmTy2, asmop>;
3389
3390   defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3391                               !cast<RegisterOperand>(List # "2D_operand"),
3392                               ImmTy2, asmop>;
3393 }
3394
3395 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3396 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3397 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3398                                  "ld1">;
3399
3400 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3401
3402 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3403                              "ld3">;
3404
3405 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3406
3407 // Post-index load multiple 1-element structures from N consecutive registers
3408 // (N = 2,3,4)
3409 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3410                                "ld1">;
3411 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3412                                    uimm_exact16, "ld1">;
3413
3414 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3415                                "ld1">;
3416 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3417                                    uimm_exact24, "ld1">;
3418
3419 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3420                                 "ld1">;
3421 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3422                                    uimm_exact32, "ld1">;
3423
3424 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3425                             RegisterOperand VecList, Operand ImmTy,
3426                             string asmop> {
3427   let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3428       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3429     def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3430                      (outs GPR64xsp:$wb),
3431                      (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3432                      asmop # "\t$Rt, [$Rn], $amt",
3433                      [],
3434                      NoItinerary> {
3435       let Rm = 0b11111;
3436     }
3437
3438     def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3439                       (outs GPR64xsp:$wb),
3440                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3441                       asmop # "\t$Rt, [$Rn], $Rm",
3442                       [],
3443                       NoItinerary>;
3444   }
3445 }
3446
3447 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3448                            Operand ImmTy2, string asmop> {
3449   defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3450                  !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3451
3452   defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3453                               !cast<RegisterOperand>(List # "4H_operand"),
3454                               ImmTy, asmop>;
3455
3456   defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3457                               !cast<RegisterOperand>(List # "2S_operand"),
3458                               ImmTy, asmop>;
3459
3460   defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3461                                !cast<RegisterOperand>(List # "16B_operand"),
3462                                ImmTy2, asmop>;
3463
3464   defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3465                               !cast<RegisterOperand>(List # "8H_operand"),
3466                               ImmTy2, asmop>;
3467
3468   defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3469                               !cast<RegisterOperand>(List # "4S_operand"),
3470                               ImmTy2, asmop>;
3471
3472   defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3473                               !cast<RegisterOperand>(List # "2D_operand"),
3474                               ImmTy2, asmop>;
3475 }
3476
3477 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3478 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3479 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3480                                  "st1">;
3481
3482 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3483
3484 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3485                              "st3">;
3486
3487 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3488
3489 // Post-index load multiple 1-element structures from N consecutive registers
3490 // (N = 2,3,4)
3491 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3492                                "st1">;
3493 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3494                                    uimm_exact16, "st1">;
3495
3496 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3497                                "st1">;
3498 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3499                                    uimm_exact24, "st1">;
3500
3501 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3502                                "st1">;
3503 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3504                                    uimm_exact32, "st1">;
3505
3506 // End of post-index vector load/store multiple N-element structure
3507 // (class SIMD lselem-post)
3508
3509 // The followings are vector load/store single N-element structure
3510 // (class SIMD lsone).
3511 def neon_uimm0_bare : Operand<i64>,
3512                         ImmLeaf<i64, [{return Imm == 0;}]> {
3513   let ParserMatchClass = neon_uimm0_asmoperand;
3514   let PrintMethod = "printUImmBareOperand";
3515 }
3516
3517 def neon_uimm1_bare : Operand<i64>,
3518                         ImmLeaf<i64, [{return Imm < 2;}]> {
3519   let ParserMatchClass = neon_uimm1_asmoperand;
3520   let PrintMethod = "printUImmBareOperand";
3521 }
3522
3523 def neon_uimm2_bare : Operand<i64>,
3524                         ImmLeaf<i64, [{return Imm < 4;}]> {
3525   let ParserMatchClass = neon_uimm2_asmoperand;
3526   let PrintMethod = "printUImmBareOperand";
3527 }
3528
3529 def neon_uimm3_bare : Operand<i64>,
3530                         ImmLeaf<i64, [{return Imm < 8;}]> {
3531   let ParserMatchClass = uimm3_asmoperand;
3532   let PrintMethod = "printUImmBareOperand";
3533 }
3534
3535 def neon_uimm4_bare : Operand<i64>,
3536                         ImmLeaf<i64, [{return Imm < 16;}]> {
3537   let ParserMatchClass = uimm4_asmoperand;
3538   let PrintMethod = "printUImmBareOperand";
3539 }
3540
3541 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3542                     RegisterOperand VecList, string asmop>
3543     : NeonI_LdOne_Dup<q, r, opcode, size,
3544                       (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3545                       asmop # "\t$Rt, [$Rn]",
3546                       [],
3547                       NoItinerary> {
3548   let mayLoad = 1;
3549   let neverHasSideEffects = 1;
3550 }
3551
3552 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3553   def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3554                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3555
3556   def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3557                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3558
3559   def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3560                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3561
3562   def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3563                           !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3564
3565   def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3566                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3567
3568   def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3569                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3570
3571   def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3572                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3573
3574   def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3575                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3576 }
3577
3578 // Load single 1-element structure to all lanes of 1 register
3579 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3580
3581 // Load single N-element structure to all lanes of N consecutive
3582 // registers (N = 2,3,4)
3583 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3584 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3585 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3586
3587
3588 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3589                     Instruction INST>
3590     : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3591           (VTy (INST GPR64xsp:$Rn))>;
3592
3593 // Match all LD1R instructions
3594 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3595
3596 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3597
3598 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3599
3600 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3601
3602 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3603 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3604
3605 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3606 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3607
3608 def : LD1R_pattern<v1i64, i64, load, LD1R_1D>;
3609 def : LD1R_pattern<v1f64, f64, load, LD1R_1D>;
3610
3611 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3612 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3613
3614
3615 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3616                                 RegisterClass RegList> {
3617   defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3618   defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3619   defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3620   defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3621 }
3622
3623 // Special vector list operand of 128-bit vectors with bare layout.
3624 // i.e. only show ".b", ".h", ".s", ".d"
3625 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3626 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3627 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3628 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3629
3630 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3631                      Operand ImmOp, string asmop>
3632     : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3633                          (outs VList:$Rt),
3634                          (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3635                          asmop # "\t$Rt[$lane], [$Rn]",
3636                          [],
3637                          NoItinerary> {
3638   let mayLoad = 1;
3639   let neverHasSideEffects = 1;
3640   let hasExtraDefRegAllocReq = 1;
3641   let Constraints = "$src = $Rt";
3642 }
3643
3644 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3645   def _B : NeonI_LDN_Lane<r, 0b00, op0,
3646                           !cast<RegisterOperand>(List # "B_operand"),
3647                           neon_uimm4_bare, asmop> {
3648     let Inst{12-10} = lane{2-0};
3649     let Inst{30} = lane{3};
3650   }
3651
3652   def _H : NeonI_LDN_Lane<r, 0b01, op0,
3653                           !cast<RegisterOperand>(List # "H_operand"),
3654                           neon_uimm3_bare, asmop> {
3655     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3656     let Inst{30} = lane{2};
3657   }
3658
3659   def _S : NeonI_LDN_Lane<r, 0b10, op0,
3660                           !cast<RegisterOperand>(List # "S_operand"),
3661                           neon_uimm2_bare, asmop> {
3662     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3663     let Inst{30} = lane{1};
3664   }
3665
3666   def _D : NeonI_LDN_Lane<r, 0b10, op0,
3667                           !cast<RegisterOperand>(List # "D_operand"),
3668                           neon_uimm1_bare, asmop> {
3669     let Inst{12-10} = 0b001;
3670     let Inst{30} = lane{0};
3671   }
3672 }
3673
3674 // Load single 1-element structure to one lane of 1 register.
3675 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3676
3677 // Load single N-element structure to one lane of N consecutive registers
3678 // (N = 2,3,4)
3679 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3680 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3681 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3682
3683 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3684                           Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3685                           Instruction INST> {
3686   def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3687                      (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3688             (VTy (EXTRACT_SUBREG
3689                      (INST GPR64xsp:$Rn,
3690                            (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3691                            ImmOp:$lane),
3692                      sub_64))>;
3693
3694   def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3695                       (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3696             (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3697 }
3698
3699 // Match all LD1LN instructions
3700 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3701                       extloadi8, LD1LN_B>;
3702
3703 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3704                       extloadi16, LD1LN_H>;
3705
3706 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3707                       load, LD1LN_S>;
3708 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3709                       load, LD1LN_S>;
3710
3711 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3712                       load, LD1LN_D>;
3713 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3714                       load, LD1LN_D>;
3715
3716 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3717                      Operand ImmOp, string asmop>
3718     : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3719                          (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3720                          asmop # "\t$Rt[$lane], [$Rn]",
3721                          [],
3722                          NoItinerary> {
3723   let mayStore = 1;
3724   let neverHasSideEffects = 1;
3725   let hasExtraDefRegAllocReq = 1;
3726 }
3727
3728 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3729   def _B : NeonI_STN_Lane<r, 0b00, op0,
3730                           !cast<RegisterOperand>(List # "B_operand"),
3731                           neon_uimm4_bare, asmop> {
3732     let Inst{12-10} = lane{2-0};
3733     let Inst{30} = lane{3};
3734   }
3735
3736   def _H : NeonI_STN_Lane<r, 0b01, op0,
3737                           !cast<RegisterOperand>(List # "H_operand"),
3738                           neon_uimm3_bare, asmop> {
3739     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3740     let Inst{30} = lane{2};
3741   }
3742
3743   def _S : NeonI_STN_Lane<r, 0b10, op0,
3744                           !cast<RegisterOperand>(List # "S_operand"),
3745                            neon_uimm2_bare, asmop> {
3746     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3747     let Inst{30} = lane{1};
3748   }
3749
3750   def _D : NeonI_STN_Lane<r, 0b10, op0,
3751                           !cast<RegisterOperand>(List # "D_operand"),
3752                           neon_uimm1_bare, asmop>{
3753     let Inst{12-10} = 0b001;
3754     let Inst{30} = lane{0};
3755   }
3756 }
3757
3758 // Store single 1-element structure from one lane of 1 register.
3759 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3760
3761 // Store single N-element structure from one lane of N consecutive registers
3762 // (N = 2,3,4)
3763 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3764 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3765 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3766
3767 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3768                           Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3769                           Instruction INST> {
3770   def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3771                      GPR64xsp:$Rn),
3772             (INST GPR64xsp:$Rn,
3773                   (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3774                   ImmOp:$lane)>;
3775
3776   def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3777                      GPR64xsp:$Rn),
3778             (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3779 }
3780
3781 // Match all ST1LN instructions
3782 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3783                       truncstorei8, ST1LN_B>;
3784
3785 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3786                       truncstorei16, ST1LN_H>;
3787
3788 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3789                       store, ST1LN_S>;
3790 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3791                       store, ST1LN_S>;
3792
3793 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3794                       store, ST1LN_D>;
3795 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3796                       store, ST1LN_D>;
3797
3798 // End of vector load/store single N-element structure (class SIMD lsone).
3799
3800
3801 // The following are post-index load/store single N-element instructions
3802 // (class SIMD lsone-post)
3803
3804 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3805                             RegisterOperand VecList, Operand ImmTy,
3806                             string asmop> {
3807   let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
3808   DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3809     def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3810                       (outs VecList:$Rt, GPR64xsp:$wb),
3811                       (ins GPR64xsp:$Rn, ImmTy:$amt),
3812                       asmop # "\t$Rt, [$Rn], $amt",
3813                       [],
3814                       NoItinerary> {
3815                         let Rm = 0b11111;
3816                       }
3817
3818     def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3819                       (outs VecList:$Rt, GPR64xsp:$wb),
3820                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3821                       asmop # "\t$Rt, [$Rn], $Rm",
3822                       [],
3823                       NoItinerary>;
3824   }
3825 }
3826
3827 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
3828                          Operand uimm_b, Operand uimm_h,
3829                          Operand uimm_s, Operand uimm_d> {
3830   defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
3831                               !cast<RegisterOperand>(List # "8B_operand"),
3832                               uimm_b, asmop>;
3833
3834   defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
3835                               !cast<RegisterOperand>(List # "4H_operand"),
3836                               uimm_h, asmop>;
3837
3838   defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
3839                               !cast<RegisterOperand>(List # "2S_operand"),
3840                               uimm_s, asmop>;
3841
3842   defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
3843                               !cast<RegisterOperand>(List # "1D_operand"),
3844                               uimm_d, asmop>;
3845
3846   defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
3847                                !cast<RegisterOperand>(List # "16B_operand"),
3848                                uimm_b, asmop>;
3849
3850   defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
3851                               !cast<RegisterOperand>(List # "8H_operand"),
3852                               uimm_h, asmop>;
3853
3854   defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
3855                               !cast<RegisterOperand>(List # "4S_operand"),
3856                               uimm_s, asmop>;
3857
3858   defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
3859                               !cast<RegisterOperand>(List # "2D_operand"),
3860                               uimm_d, asmop>;
3861 }
3862
3863 // Post-index load single 1-element structure to all lanes of 1 register
3864 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
3865                              uimm_exact2, uimm_exact4, uimm_exact8>;
3866
3867 // Post-index load single N-element structure to all lanes of N consecutive
3868 // registers (N = 2,3,4)
3869 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
3870                              uimm_exact4, uimm_exact8, uimm_exact16>;
3871 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
3872                              uimm_exact6, uimm_exact12, uimm_exact24>;
3873 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
3874                              uimm_exact8, uimm_exact16, uimm_exact32>;
3875
3876 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
3877     Constraints = "$Rn = $wb, $Rt = $src",
3878     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3879   class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3880                                 Operand ImmTy, Operand ImmOp, string asmop>
3881       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3882                                 (outs VList:$Rt, GPR64xsp:$wb),
3883                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
3884                                     VList:$src, ImmOp:$lane),
3885                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
3886                                 [],
3887                                 NoItinerary> {
3888     let Rm = 0b11111;
3889   }
3890
3891   class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3892                                  Operand ImmTy, Operand ImmOp, string asmop>
3893       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3894                                 (outs VList:$Rt, GPR64xsp:$wb),
3895                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
3896                                     VList:$src, ImmOp:$lane),
3897                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
3898                                 [],
3899                                 NoItinerary>;
3900 }
3901
3902 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
3903                            Operand uimm_b, Operand uimm_h,
3904                            Operand uimm_s, Operand uimm_d> {
3905   def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
3906                                !cast<RegisterOperand>(List # "B_operand"),
3907                                uimm_b, neon_uimm4_bare, asmop> {
3908     let Inst{12-10} = lane{2-0};
3909     let Inst{30} = lane{3};
3910   }
3911
3912   def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
3913                                    !cast<RegisterOperand>(List # "B_operand"),
3914                                    uimm_b, neon_uimm4_bare, asmop> {
3915     let Inst{12-10} = lane{2-0};
3916     let Inst{30} = lane{3};
3917   }
3918
3919   def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
3920                                !cast<RegisterOperand>(List # "H_operand"),
3921                                uimm_h, neon_uimm3_bare, asmop> {
3922     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3923     let Inst{30} = lane{2};
3924   }
3925
3926   def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
3927                                    !cast<RegisterOperand>(List # "H_operand"),
3928                                    uimm_h, neon_uimm3_bare, asmop> {
3929     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3930     let Inst{30} = lane{2};
3931   }
3932
3933   def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3934                                !cast<RegisterOperand>(List # "S_operand"),
3935                                uimm_s, neon_uimm2_bare, asmop> {
3936     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3937     let Inst{30} = lane{1};
3938   }
3939
3940   def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
3941                                    !cast<RegisterOperand>(List # "S_operand"),
3942                                    uimm_s, neon_uimm2_bare, asmop> {
3943     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3944     let Inst{30} = lane{1};
3945   }
3946
3947   def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3948                                !cast<RegisterOperand>(List # "D_operand"),
3949                                uimm_d, neon_uimm1_bare, asmop> {
3950     let Inst{12-10} = 0b001;
3951     let Inst{30} = lane{0};
3952   }
3953
3954   def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
3955                                    !cast<RegisterOperand>(List # "D_operand"),
3956                                    uimm_d, neon_uimm1_bare, asmop> {
3957     let Inst{12-10} = 0b001;
3958     let Inst{30} = lane{0};
3959   }
3960 }
3961
3962 // Post-index load single 1-element structure to one lane of 1 register.
3963 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
3964                                 uimm_exact2, uimm_exact4, uimm_exact8>;
3965
3966 // Post-index load single N-element structure to one lane of N consecutive
3967 // registers
3968 // (N = 2,3,4)
3969 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
3970                                 uimm_exact4, uimm_exact8, uimm_exact16>;
3971 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
3972                                 uimm_exact6, uimm_exact12, uimm_exact24>;
3973 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
3974                                 uimm_exact8, uimm_exact16, uimm_exact32>;
3975
3976 let mayStore = 1, neverHasSideEffects = 1,
3977     hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
3978     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3979   class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3980                       Operand ImmTy, Operand ImmOp, string asmop>
3981       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
3982                                 (outs GPR64xsp:$wb),
3983                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
3984                                     VList:$Rt, ImmOp:$lane),
3985                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
3986                                 [],
3987                                 NoItinerary> {
3988     let Rm = 0b11111;
3989   }
3990
3991   class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3992                        Operand ImmTy, Operand ImmOp, string asmop>
3993       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
3994                                 (outs GPR64xsp:$wb),
3995                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
3996                                     ImmOp:$lane),
3997                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
3998                                 [],
3999                                 NoItinerary>;
4000 }
4001
4002 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4003                            Operand uimm_b, Operand uimm_h,
4004                            Operand uimm_s, Operand uimm_d> {
4005   def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4006                                !cast<RegisterOperand>(List # "B_operand"),
4007                                uimm_b, neon_uimm4_bare, asmop> {
4008     let Inst{12-10} = lane{2-0};
4009     let Inst{30} = lane{3};
4010   }
4011
4012   def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4013                                    !cast<RegisterOperand>(List # "B_operand"),
4014                                    uimm_b, neon_uimm4_bare, asmop> {
4015     let Inst{12-10} = lane{2-0};
4016     let Inst{30} = lane{3};
4017   }
4018
4019   def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4020                                !cast<RegisterOperand>(List # "H_operand"),
4021                                uimm_h, neon_uimm3_bare, asmop> {
4022     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4023     let Inst{30} = lane{2};
4024   }
4025
4026   def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4027                                    !cast<RegisterOperand>(List # "H_operand"),
4028                                    uimm_h, neon_uimm3_bare, asmop> {
4029     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4030     let Inst{30} = lane{2};
4031   }
4032
4033   def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4034                                !cast<RegisterOperand>(List # "S_operand"),
4035                                uimm_s, neon_uimm2_bare, asmop> {
4036     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4037     let Inst{30} = lane{1};
4038   }
4039
4040   def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4041                                    !cast<RegisterOperand>(List # "S_operand"),
4042                                    uimm_s, neon_uimm2_bare, asmop> {
4043     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4044     let Inst{30} = lane{1};
4045   }
4046
4047   def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4048                                !cast<RegisterOperand>(List # "D_operand"),
4049                                uimm_d, neon_uimm1_bare, asmop> {
4050     let Inst{12-10} = 0b001;
4051     let Inst{30} = lane{0};
4052   }
4053
4054   def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4055                                    !cast<RegisterOperand>(List # "D_operand"),
4056                                    uimm_d, neon_uimm1_bare, asmop> {
4057     let Inst{12-10} = 0b001;
4058     let Inst{30} = lane{0};
4059   }
4060 }
4061
4062 // Post-index store single 1-element structure from one lane of 1 register.
4063 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4064                                 uimm_exact2, uimm_exact4, uimm_exact8>;
4065
4066 // Post-index store single N-element structure from one lane of N consecutive
4067 // registers (N = 2,3,4)
4068 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4069                                 uimm_exact4, uimm_exact8, uimm_exact16>;
4070 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4071                                 uimm_exact6, uimm_exact12, uimm_exact24>;
4072 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4073                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4074
4075 // End of post-index load/store single N-element instructions
4076 // (class SIMD lsone-post)
4077
4078 // Neon Scalar instructions implementation
4079 // Scalar Three Same
4080
4081 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4082                              RegisterClass FPRC>
4083   : NeonI_Scalar3Same<u, size, opcode,
4084                       (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4085                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4086                       [],
4087                       NoItinerary>;
4088
4089 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4090   : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4091
4092 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4093                                       bit Commutable = 0> {
4094   let isCommutable = Commutable in {
4095     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4096     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4097   }
4098 }
4099
4100 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4101                                       string asmop, bit Commutable = 0> {
4102   let isCommutable = Commutable in {
4103     def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4104     def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4105   }
4106 }
4107
4108 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4109                                         string asmop, bit Commutable = 0> {
4110   let isCommutable = Commutable in {
4111     def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4112     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4113     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4114     def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4115   }
4116 }
4117
4118 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4119                                             Instruction INSTD> {
4120   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4121             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4122 }
4123
4124 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4125                                                Instruction INSTB,
4126                                                Instruction INSTH,
4127                                                Instruction INSTS,
4128                                                Instruction INSTD>
4129   : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4130   def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4131            (INSTB FPR8:$Rn, FPR8:$Rm)>;
4132
4133   def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4134            (INSTH FPR16:$Rn, FPR16:$Rm)>;
4135
4136   def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4137            (INSTS FPR32:$Rn, FPR32:$Rm)>;
4138 }
4139
4140 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
4141                                            Instruction INSTD>
4142   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4143         (INSTD FPR64:$Rn, FPR64:$Rm)>;
4144
4145 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4146                                              Instruction INSTH,
4147                                              Instruction INSTS> {
4148   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4149             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4150   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4151             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4152 }
4153
4154 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4155                                              Instruction INSTS,
4156                                              Instruction INSTD> {
4157   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4158             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4159   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4160             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4161 }
4162
4163 multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
4164                                                  Instruction INSTS,
4165                                                  Instruction INSTD> {
4166   def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4167             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4168   def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4169             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4170 }
4171
4172 // Scalar Three Different
4173
4174 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4175                              RegisterClass FPRCD, RegisterClass FPRCS>
4176   : NeonI_Scalar3Diff<u, size, opcode,
4177                       (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4178                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4179                       [],
4180                       NoItinerary>;
4181
4182 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4183   def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4184   def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4185 }
4186
4187 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4188   let Constraints = "$Src = $Rd" in {
4189     def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4190                        (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4191                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4192                        [],
4193                        NoItinerary>;
4194     def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4195                        (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4196                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4197                        [],
4198                        NoItinerary>;
4199   }
4200 }
4201
4202 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4203                                              Instruction INSTH,
4204                                              Instruction INSTS> {
4205   def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4206             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4207   def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4208             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4209 }
4210
4211 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4212                                              Instruction INSTH,
4213                                              Instruction INSTS> {
4214   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4215             (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4216   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4217             (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4218 }
4219
4220 // Scalar Two Registers Miscellaneous
4221
4222 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4223                              RegisterClass FPRCD, RegisterClass FPRCS>
4224   : NeonI_Scalar2SameMisc<u, size, opcode,
4225                           (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4226                           !strconcat(asmop, "\t$Rd, $Rn"),
4227                           [],
4228                           NoItinerary>;
4229
4230 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4231                                          string asmop> {
4232   def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4233                                       FPR32>;
4234   def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4235                                       FPR64>;
4236 }
4237
4238 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4239   def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4240 }
4241
4242 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4243   : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4244   def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4245   def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4246   def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4247 }
4248
4249 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4250   : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4251
4252 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4253                                                  string asmop> {
4254   def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4255   def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4256   def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4257 }
4258
4259 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4260                                        string asmop, RegisterClass FPRC>
4261   : NeonI_Scalar2SameMisc<u, size, opcode,
4262                           (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4263                           !strconcat(asmop, "\t$Rd, $Rn"),
4264                           [],
4265                           NoItinerary>;
4266
4267 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4268                                                  string asmop> {
4269
4270   let Constraints = "$Src = $Rd" in {
4271     def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4272     def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4273     def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4274     def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4275   }
4276 }
4277
4278 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4279                                                   Instruction INSTD>
4280   : Pat<(v1f32 (opnode (v1f64 FPR64:$Rn))),
4281         (INSTD FPR64:$Rn)>;
4282
4283 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4284                                                       Instruction INSTS,
4285                                                       Instruction INSTD> {
4286   def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn))),
4287             (INSTS FPR32:$Rn)>;
4288   def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4289             (INSTD FPR64:$Rn)>;
4290 }
4291
4292 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator Sopnode,
4293                                                      SDPatternOperator Dopnode,
4294                                                      Instruction INSTS,
4295                                                      Instruction INSTD> {
4296   def : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn))),
4297             (INSTS FPR32:$Rn)>;
4298   def : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn))),
4299             (INSTD FPR64:$Rn)>;
4300 }
4301
4302 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4303                                                  Instruction INSTS,
4304                                                  Instruction INSTD> {
4305   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn))),
4306             (INSTS FPR32:$Rn)>;
4307   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4308             (INSTD FPR64:$Rn)>;
4309 }
4310
4311 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4312   : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4313                           (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4314                           !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4315                           [],
4316                           NoItinerary>;
4317
4318 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4319                                               string asmop> {
4320   def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4321                            (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4322                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4323                            [],
4324                            NoItinerary>;
4325   def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4326                            (outs FPR64:$Rd), (ins FPR64:$Rn, fpz64movi:$FPImm),
4327                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4328                            [],
4329                            NoItinerary>;
4330 }
4331
4332 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4333                                                 Instruction INSTD>
4334   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4335                        (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4336         (INSTD FPR64:$Rn, 0)>;
4337
4338 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4339                                                       Instruction INSTS,
4340                                                       Instruction INSTD> {
4341   def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
4342                            (v1f32 (scalar_to_vector (f32 fpimm:$FPImm))))),
4343             (INSTS FPR32:$Rn, fpimm:$FPImm)>;
4344   def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
4345                            (v1f64 (bitconvert (v8i8 Neon_AllZero))))),
4346             (INSTD FPR64:$Rn, 0)>;
4347 }
4348
4349 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4350                                                 Instruction INSTD> {
4351   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4352             (INSTD FPR64:$Rn)>;
4353 }
4354
4355 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4356                                                    Instruction INSTB,
4357                                                    Instruction INSTH,
4358                                                    Instruction INSTS,
4359                                                    Instruction INSTD>
4360   : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4361   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4362             (INSTB FPR8:$Rn)>;
4363   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4364             (INSTH FPR16:$Rn)>;
4365   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4366             (INSTS FPR32:$Rn)>;
4367 }
4368
4369 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4370                                                        SDPatternOperator opnode,
4371                                                        Instruction INSTH,
4372                                                        Instruction INSTS,
4373                                                        Instruction INSTD> {
4374   def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4375             (INSTH FPR16:$Rn)>;
4376   def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4377             (INSTS FPR32:$Rn)>;
4378   def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4379             (INSTD FPR64:$Rn)>;
4380
4381 }
4382
4383 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4384                                                        SDPatternOperator opnode,
4385                                                        Instruction INSTB,
4386                                                        Instruction INSTH,
4387                                                        Instruction INSTS,
4388                                                        Instruction INSTD> {
4389   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4390             (INSTB FPR8:$Src, FPR8:$Rn)>;
4391   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4392             (INSTH FPR16:$Src, FPR16:$Rn)>;
4393   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4394             (INSTS FPR32:$Src, FPR32:$Rn)>;
4395   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4396             (INSTD FPR64:$Src, FPR64:$Rn)>;
4397 }
4398
4399 // Scalar Shift By Immediate
4400
4401 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4402                                 RegisterClass FPRC, Operand ImmTy>
4403   : NeonI_ScalarShiftImm<u, opcode,
4404                          (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4405                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4406                          [], NoItinerary>;
4407
4408 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4409                                             string asmop> {
4410   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4411     bits<6> Imm;
4412     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4413     let Inst{21-16} = Imm;
4414   }
4415 }
4416
4417 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4418                                                string asmop>
4419   : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4420   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4421     bits<3> Imm;
4422     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4423     let Inst{18-16} = Imm;
4424   }
4425   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4426     bits<4> Imm;
4427     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4428     let Inst{19-16} = Imm;
4429   }
4430   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4431     bits<5> Imm;
4432     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4433     let Inst{20-16} = Imm;
4434   }
4435 }
4436
4437 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4438                                             string asmop> {
4439   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4440     bits<6> Imm;
4441     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4442     let Inst{21-16} = Imm;
4443   }
4444 }
4445
4446 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4447                                               string asmop>
4448   : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4449   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4450     bits<3> Imm;
4451     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4452     let Inst{18-16} = Imm;
4453   }
4454   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4455     bits<4> Imm;
4456     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4457     let Inst{19-16} = Imm;
4458   }
4459   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4460     bits<5> Imm;
4461     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4462     let Inst{20-16} = Imm;
4463   }
4464 }
4465
4466 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4467   : NeonI_ScalarShiftImm<u, opcode,
4468                          (outs FPR64:$Rd),
4469                          (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4470                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4471                          [], NoItinerary> {
4472     bits<6> Imm;
4473     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4474     let Inst{21-16} = Imm;
4475     let Constraints = "$Src = $Rd";
4476 }
4477
4478 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4479   : NeonI_ScalarShiftImm<u, opcode,
4480                          (outs FPR64:$Rd),
4481                          (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4482                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4483                          [], NoItinerary> {
4484     bits<6> Imm;
4485     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4486     let Inst{21-16} = Imm;
4487     let Constraints = "$Src = $Rd";
4488 }
4489
4490 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4491                                        RegisterClass FPRCD, RegisterClass FPRCS,
4492                                        Operand ImmTy>
4493   : NeonI_ScalarShiftImm<u, opcode,
4494                          (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4495                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4496                          [], NoItinerary>;
4497
4498 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4499                                                 string asmop> {
4500   def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4501                                              shr_imm8> {
4502     bits<3> Imm;
4503     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4504     let Inst{18-16} = Imm;
4505   }
4506   def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4507                                              shr_imm16> {
4508     bits<4> Imm;
4509     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4510     let Inst{19-16} = Imm;
4511   }
4512   def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4513                                              shr_imm32> {
4514     bits<5> Imm;
4515     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4516     let Inst{20-16} = Imm;
4517   }
4518 }
4519
4520 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4521   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4522     bits<5> Imm;
4523     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4524     let Inst{20-16} = Imm;
4525   }
4526   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4527     bits<6> Imm;
4528     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4529     let Inst{21-16} = Imm;
4530   }
4531 }
4532
4533 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4534                                                Instruction INSTD> {
4535   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4536                 (INSTD FPR64:$Rn, imm:$Imm)>;
4537 }
4538
4539 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4540                                                Instruction INSTD> {
4541   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4542                 (INSTD FPR64:$Rn, imm:$Imm)>;
4543 }
4544
4545 class Neon_ScalarShiftImm_arm_D_size_patterns<SDPatternOperator opnode,
4546                                               Instruction INSTD>
4547   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4548             (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4549         (INSTD FPR64:$Rn, imm:$Imm)>;
4550
4551 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4552                                                    Instruction INSTB,
4553                                                    Instruction INSTH,
4554                                                    Instruction INSTS,
4555                                                    Instruction INSTD>
4556   : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4557   def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4558                 (INSTB FPR8:$Rn, imm:$Imm)>;
4559   def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4560                 (INSTH FPR16:$Rn, imm:$Imm)>;
4561   def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4562                 (INSTS FPR32:$Rn, imm:$Imm)>;
4563 }
4564
4565 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4566                                                 Instruction INSTD>
4567   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4568             (i32 shl_imm64:$Imm))),
4569         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4570
4571 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4572                                                 Instruction INSTD>
4573   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4574             (i32 shr_imm64:$Imm))),
4575         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4576
4577 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4578                                                        SDPatternOperator opnode,
4579                                                        Instruction INSTH,
4580                                                        Instruction INSTS,
4581                                                        Instruction INSTD> {
4582   def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4583                 (INSTH FPR16:$Rn, imm:$Imm)>;
4584   def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4585                 (INSTS FPR32:$Rn, imm:$Imm)>;
4586   def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4587                 (INSTD FPR64:$Rn, imm:$Imm)>;
4588 }
4589
4590 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator Sopnode,
4591                                                       SDPatternOperator Dopnode,
4592                                                       Instruction INSTS,
4593                                                       Instruction INSTD> {
4594   def ssi : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4595                 (INSTS FPR32:$Rn, imm:$Imm)>;
4596   def ddi : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4597                 (INSTD FPR64:$Rn, imm:$Imm)>;
4598 }
4599
4600 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator Sopnode,
4601                                                       SDPatternOperator Dopnode,
4602                                                       Instruction INSTS,
4603                                                       Instruction INSTD> {
4604   def ssi : Pat<(v1i32 (Sopnode (v1f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4605                 (INSTS FPR32:$Rn, imm:$Imm)>;
4606   def ddi : Pat<(v1i64 (Dopnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4607                 (INSTD FPR64:$Rn, imm:$Imm)>;
4608 }
4609
4610 // Scalar Signed Shift Right (Immediate)
4611 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4612 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4613 // Pattern to match llvm.arm.* intrinsic.
4614 def : Neon_ScalarShiftImm_arm_D_size_patterns<sra, SSHRddi>;
4615
4616 // Scalar Unsigned Shift Right (Immediate)
4617 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4618 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4619 // Pattern to match llvm.arm.* intrinsic.
4620 def : Neon_ScalarShiftImm_arm_D_size_patterns<srl, USHRddi>;
4621
4622 // Scalar Signed Rounding Shift Right (Immediate)
4623 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4624 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4625
4626 // Scalar Unigned Rounding Shift Right (Immediate)
4627 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4628 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4629
4630 // Scalar Signed Shift Right and Accumulate (Immediate)
4631 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4632 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4633           <int_aarch64_neon_vsrads_n, SSRA>;
4634
4635 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4636 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4637 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4638           <int_aarch64_neon_vsradu_n, USRA>;
4639
4640 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4641 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4642 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4643           <int_aarch64_neon_vrsrads_n, SRSRA>;
4644
4645 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4646 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4647 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4648           <int_aarch64_neon_vrsradu_n, URSRA>;
4649
4650 // Scalar Shift Left (Immediate)
4651 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4652 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4653 // Pattern to match llvm.arm.* intrinsic.
4654 def : Neon_ScalarShiftImm_arm_D_size_patterns<shl, SHLddi>;
4655
4656 // Signed Saturating Shift Left (Immediate)
4657 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4658 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4659                                                SQSHLbbi, SQSHLhhi,
4660                                                SQSHLssi, SQSHLddi>;
4661 // Pattern to match llvm.arm.* intrinsic.
4662 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4663
4664 // Unsigned Saturating Shift Left (Immediate)
4665 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4666 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4667                                                UQSHLbbi, UQSHLhhi,
4668                                                UQSHLssi, UQSHLddi>;
4669 // Pattern to match llvm.arm.* intrinsic.
4670 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4671
4672 // Signed Saturating Shift Left Unsigned (Immediate)
4673 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4674 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4675                                                SQSHLUbbi, SQSHLUhhi,
4676                                                SQSHLUssi, SQSHLUddi>;
4677
4678 // Shift Right And Insert (Immediate)
4679 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4680 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4681           <int_aarch64_neon_vsri, SRI>;
4682
4683 // Shift Left And Insert (Immediate)
4684 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4685 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4686           <int_aarch64_neon_vsli, SLI>;
4687
4688 // Signed Saturating Shift Right Narrow (Immediate)
4689 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4690 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4691                                                     SQSHRNbhi, SQSHRNhsi,
4692                                                     SQSHRNsdi>;
4693
4694 // Unsigned Saturating Shift Right Narrow (Immediate)
4695 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4696 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4697                                                     UQSHRNbhi, UQSHRNhsi,
4698                                                     UQSHRNsdi>;
4699
4700 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4701 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4702 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4703                                                     SQRSHRNbhi, SQRSHRNhsi,
4704                                                     SQRSHRNsdi>;
4705
4706 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4707 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4708 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4709                                                     UQRSHRNbhi, UQRSHRNhsi,
4710                                                     UQRSHRNsdi>;
4711
4712 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4713 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4714 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4715                                                     SQSHRUNbhi, SQSHRUNhsi,
4716                                                     SQSHRUNsdi>;
4717
4718 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4719 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4720 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4721                                                     SQRSHRUNbhi, SQRSHRUNhsi,
4722                                                     SQRSHRUNsdi>;
4723
4724 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4725 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4726 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_s32,
4727                                                   int_aarch64_neon_vcvtf64_n_s64,
4728                                                   SCVTF_Nssi, SCVTF_Nddi>;
4729
4730 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4731 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4732 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_u32,
4733                                                   int_aarch64_neon_vcvtf64_n_u64,
4734                                                   UCVTF_Nssi, UCVTF_Nddi>;
4735
4736 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4737 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4738 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_s32_f32,
4739                                                   int_aarch64_neon_vcvtd_n_s64_f64,
4740                                                   FCVTZS_Nssi, FCVTZS_Nddi>;
4741
4742 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4743 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4744 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_u32_f32,
4745                                                   int_aarch64_neon_vcvtd_n_u64_f64,
4746                                                   FCVTZU_Nssi, FCVTZU_Nddi>;
4747
4748 // Scalar Integer Add
4749 let isCommutable = 1 in {
4750 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4751 }
4752
4753 // Scalar Integer Sub
4754 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4755
4756 // Pattern for Scalar Integer Add and Sub with D register only
4757 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4758 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4759
4760 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4761 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4762 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4763 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4764 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4765
4766 // Scalar Integer Saturating Add (Signed, Unsigned)
4767 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4768 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4769
4770 // Scalar Integer Saturating Sub (Signed, Unsigned)
4771 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4772 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4773
4774
4775 // Patterns to match llvm.aarch64.* intrinsic for
4776 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
4777 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
4778                                            SQADDhhh, SQADDsss, SQADDddd>;
4779 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
4780                                            UQADDhhh, UQADDsss, UQADDddd>;
4781 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
4782                                            SQSUBhhh, SQSUBsss, SQSUBddd>;
4783 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
4784                                            UQSUBhhh, UQSUBsss, UQSUBddd>;
4785
4786 // Scalar Integer Saturating Doubling Multiply Half High
4787 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
4788
4789 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4790 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
4791
4792 // Patterns to match llvm.arm.* intrinsic for
4793 // Scalar Integer Saturating Doubling Multiply Half High and
4794 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4795 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
4796                                                                SQDMULHsss>;
4797 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
4798                                                                 SQRDMULHsss>;
4799
4800 // Scalar Floating-point Multiply Extended
4801 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
4802
4803 // Scalar Floating-point Reciprocal Step
4804 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
4805
4806 // Scalar Floating-point Reciprocal Square Root Step
4807 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
4808
4809 // Patterns to match llvm.arm.* intrinsic for
4810 // Scalar Floating-point Reciprocal Step and
4811 // Scalar Floating-point Reciprocal Square Root Step
4812 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss,
4813                                                               FRECPSddd>;
4814 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
4815                                                                FRSQRTSddd>;
4816
4817 // Patterns to match llvm.aarch64.* intrinsic for
4818 // Scalar Floating-point Multiply Extended,
4819 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
4820                                                   Instruction INSTS,
4821                                                   Instruction INSTD> {
4822   def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4823             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4824   def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4825             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4826 }
4827
4828 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
4829                                               FMULXsss,FMULXddd>;
4830
4831 // Scalar Integer Shift Left (Signed, Unsigned)
4832 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
4833 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
4834
4835 // Patterns to match llvm.arm.* intrinsic for
4836 // Scalar Integer Shift Left (Signed, Unsigned)
4837 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
4838 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
4839
4840 // Patterns to match llvm.aarch64.* intrinsic for
4841 // Scalar Integer Shift Left (Signed, Unsigned)
4842 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
4843 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
4844
4845 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
4846 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
4847 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
4848
4849 // Patterns to match llvm.aarch64.* intrinsic for
4850 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4851 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
4852                                            SQSHLhhh, SQSHLsss, SQSHLddd>;
4853 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
4854                                            UQSHLhhh, UQSHLsss, UQSHLddd>;
4855
4856 // Patterns to match llvm.arm.* intrinsic for
4857 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4858 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
4859 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
4860
4861 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4862 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
4863 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
4864
4865 // Patterns to match llvm.aarch64.* intrinsic for
4866 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4867 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
4868 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
4869
4870 // Patterns to match llvm.arm.* intrinsic for
4871 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4872 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
4873 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
4874
4875 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4876 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
4877 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
4878
4879 // Patterns to match llvm.aarch64.* intrinsic for
4880 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4881 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
4882                                            SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
4883 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
4884                                            UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
4885
4886 // Patterns to match llvm.arm.* intrinsic for
4887 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4888 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
4889 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
4890
4891 // Signed Saturating Doubling Multiply-Add Long
4892 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
4893 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
4894                                             SQDMLALshh, SQDMLALdss>;
4895
4896 // Signed Saturating Doubling Multiply-Subtract Long
4897 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
4898 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
4899                                             SQDMLSLshh, SQDMLSLdss>;
4900
4901 // Signed Saturating Doubling Multiply Long
4902 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
4903 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
4904                                          SQDMULLshh, SQDMULLdss>;
4905
4906 // Scalar Signed Integer Convert To Floating-point
4907 defm SCVTF  : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
4908 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,
4909                                                  int_aarch64_neon_vcvtf64_s64,
4910                                                  SCVTFss, SCVTFdd>;
4911
4912 // Scalar Unsigned Integer Convert To Floating-point
4913 defm UCVTF  : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
4914 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_u32,
4915                                                  int_aarch64_neon_vcvtf64_u64,
4916                                                  UCVTFss, UCVTFdd>;
4917
4918 // Scalar Floating-point Converts
4919 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
4920 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
4921                                                   FCVTXN>;
4922
4923 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
4924 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
4925                                                   FCVTNSss, FCVTNSdd>;
4926
4927 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
4928 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
4929                                                   FCVTNUss, FCVTNUdd>;
4930
4931 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
4932 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
4933                                                   FCVTMSss, FCVTMSdd>;
4934
4935 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
4936 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
4937                                                   FCVTMUss, FCVTMUdd>;
4938
4939 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
4940 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
4941                                                   FCVTASss, FCVTASdd>;
4942
4943 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
4944 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
4945                                                   FCVTAUss, FCVTAUdd>;
4946
4947 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
4948 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
4949                                                   FCVTPSss, FCVTPSdd>;
4950
4951 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
4952 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
4953                                                   FCVTPUss, FCVTPUdd>;
4954
4955 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
4956 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
4957                                                   FCVTZSss, FCVTZSdd>;
4958
4959 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
4960 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
4961                                                   FCVTZUss, FCVTZUdd>;
4962
4963 // Scalar Floating-point Reciprocal Estimate
4964 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
4965 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrecpe,
4966                                              FRECPEss, FRECPEdd>;
4967
4968 // Scalar Floating-point Reciprocal Exponent
4969 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
4970 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
4971                                              FRECPXss, FRECPXdd>;
4972
4973 // Scalar Floating-point Reciprocal Square Root Estimate
4974 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
4975 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrsqrte,
4976                                              FRSQRTEss, FRSQRTEdd>;
4977
4978 // Scalar Integer Compare
4979
4980 // Scalar Compare Bitwise Equal
4981 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
4982 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
4983
4984 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
4985                                               Instruction INSTD,
4986                                               CondCode CC>
4987   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
4988         (INSTD FPR64:$Rn, FPR64:$Rm)>;
4989
4990 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
4991
4992 // Scalar Compare Signed Greather Than Or Equal
4993 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
4994 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
4995
4996 // Scalar Compare Unsigned Higher Or Same
4997 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
4998 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
4999
5000 // Scalar Compare Unsigned Higher
5001 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5002 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5003
5004 // Scalar Compare Signed Greater Than
5005 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5006 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5007
5008 // Scalar Compare Bitwise Test Bits
5009 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5010 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5011 def : Neon_Scalar3Same_cmp_D_size_patterns<Neon_tst, CMTSTddd>;
5012
5013 // Scalar Compare Bitwise Equal To Zero
5014 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5015 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5016                                                 CMEQddi>;
5017
5018 // Scalar Compare Signed Greather Than Or Equal To Zero
5019 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5020 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5021                                                 CMGEddi>;
5022
5023 // Scalar Compare Signed Greater Than Zero
5024 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5025 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5026                                                 CMGTddi>;
5027
5028 // Scalar Compare Signed Less Than Or Equal To Zero
5029 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5030 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5031                                                 CMLEddi>;
5032
5033 // Scalar Compare Less Than Zero
5034 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5035 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5036                                                 CMLTddi>;
5037
5038 // Scalar Floating-point Compare
5039
5040 // Scalar Floating-point Compare Mask Equal
5041 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5042 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vceq,
5043                                              FCMEQsss, FCMEQddd>;
5044
5045 // Scalar Floating-point Compare Mask Equal To Zero
5046 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5047 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
5048                                                   FCMEQZssi, FCMEQZddi>;
5049
5050 // Scalar Floating-point Compare Mask Greater Than Or Equal
5051 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5052 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcge,
5053                                              FCMGEsss, FCMGEddd>;
5054
5055 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5056 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5057 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcge,
5058                                                   FCMGEZssi, FCMGEZddi>;
5059
5060 // Scalar Floating-point Compare Mask Greather Than
5061 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5062 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcgt,
5063                                              FCMGTsss, FCMGTddd>;
5064
5065 // Scalar Floating-point Compare Mask Greather Than Zero
5066 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5067 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcgt,
5068                                                   FCMGTZssi, FCMGTZddi>;
5069
5070 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5071 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5072 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vclez,
5073                                                   FCMLEZssi, FCMLEZddi>;
5074
5075 // Scalar Floating-point Compare Mask Less Than Zero
5076 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5077 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcltz,
5078                                                   FCMLTZssi, FCMLTZddi>;
5079
5080 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5081 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5082 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcage,
5083                                              FACGEsss, FACGEddd>;
5084
5085 // Scalar Floating-point Absolute Compare Mask Greater Than
5086 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5087 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcagt,
5088                                              FACGTsss, FACGTddd>;
5089
5090 // Scakar Floating-point Absolute Difference
5091 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5092 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vabd,
5093                                          FABDsss, FABDddd>;
5094
5095 // Scalar Absolute Value
5096 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5097 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5098
5099 // Scalar Signed Saturating Absolute Value
5100 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5101 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5102                                                SQABSbb, SQABShh, SQABSss, SQABSdd>;
5103
5104 // Scalar Negate
5105 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5106 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5107
5108 // Scalar Signed Saturating Negate
5109 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5110 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5111                                                SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5112
5113 // Scalar Signed Saturating Accumulated of Unsigned Value
5114 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5115 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5116                                                      SUQADDbb, SUQADDhh,
5117                                                      SUQADDss, SUQADDdd>;
5118
5119 // Scalar Unsigned Saturating Accumulated of Signed Value
5120 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5121 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5122                                                      USQADDbb, USQADDhh,
5123                                                      USQADDss, USQADDdd>;
5124
5125 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5126                                           (v1i64 FPR64:$Rn))),
5127           (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5128
5129 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5130                                           (v1i64 FPR64:$Rn))),
5131           (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5132
5133 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5134           (ABSdd FPR64:$Rn)>;
5135
5136 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5137           (SQABSdd FPR64:$Rn)>;
5138
5139 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5140           (SQNEGdd FPR64:$Rn)>;
5141
5142 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5143                       (v1i64 FPR64:$Rn))),
5144           (NEGdd FPR64:$Rn)>;
5145
5146 // Scalar Signed Saturating Extract Unsigned Narrow
5147 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5148 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5149                                                      SQXTUNbh, SQXTUNhs,
5150                                                      SQXTUNsd>;
5151
5152 // Scalar Signed Saturating Extract Narrow
5153 defm SQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5154 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5155                                                      SQXTNbh, SQXTNhs,
5156                                                      SQXTNsd>;
5157
5158 // Scalar Unsigned Saturating Extract Narrow
5159 defm UQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5160 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5161                                                      UQXTNbh, UQXTNhs,
5162                                                      UQXTNsd>;
5163
5164 // Scalar Reduce Pairwise
5165
5166 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5167                                      string asmop, bit Commutable = 0> {
5168   let isCommutable = Commutable in {
5169     def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5170                                 (outs FPR64:$Rd), (ins VPR128:$Rn),
5171                                 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5172                                 [],
5173                                 NoItinerary>;
5174   }
5175 }
5176
5177 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5178                                      string asmop, bit Commutable = 0>
5179   : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5180   let isCommutable = Commutable in {
5181     def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5182                                 (outs FPR32:$Rd), (ins VPR64:$Rn),
5183                                 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5184                                 [],
5185                                 NoItinerary>;
5186   }
5187 }
5188
5189 // Scalar Reduce Addition Pairwise (Integer) with
5190 // Pattern to match llvm.arm.* intrinsic
5191 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5192
5193 // Pattern to match llvm.aarch64.* intrinsic for
5194 // Scalar Reduce Addition Pairwise (Integer)
5195 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5196           (ADDPvv_D_2D VPR128:$Rn)>;
5197
5198 // Scalar Reduce Addition Pairwise (Floating Point)
5199 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5200
5201 // Scalar Reduce Maximum Pairwise (Floating Point)
5202 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5203
5204 // Scalar Reduce Minimum Pairwise (Floating Point)
5205 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5206
5207 // Scalar Reduce maxNum Pairwise (Floating Point)
5208 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5209
5210 // Scalar Reduce minNum Pairwise (Floating Point)
5211 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5212
5213 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnodeS,
5214                                             SDPatternOperator opnodeD,
5215                                             Instruction INSTS,
5216                                             Instruction INSTD> {
5217   def : Pat<(v1f32 (opnodeS (v2f32 VPR64:$Rn))),
5218             (INSTS VPR64:$Rn)>;
5219   def : Pat<(v1f64 (opnodeD (v2f64 VPR128:$Rn))),
5220             (INSTD VPR128:$Rn)>;
5221 }
5222
5223 // Patterns to match llvm.aarch64.* intrinsic for
5224 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5225 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5226   int_aarch64_neon_vpfaddq, FADDPvv_S_2S, FADDPvv_D_2D>;
5227
5228 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5229   int_aarch64_neon_vpmaxq, FMAXPvv_S_2S, FMAXPvv_D_2D>;
5230
5231 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5232   int_aarch64_neon_vpminq, FMINPvv_S_2S, FMINPvv_D_2D>;
5233
5234 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5235   int_aarch64_neon_vpfmaxnmq, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5236
5237 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5238   int_aarch64_neon_vpfminnmq, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5239
5240
5241 // Scalar by element Arithmetic
5242
5243 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5244                                     string rmlane, bit u, bit szhi, bit szlo,
5245                                     RegisterClass ResFPR, RegisterClass OpFPR,
5246                                     RegisterOperand OpVPR, Operand OpImm>
5247   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5248                              (outs ResFPR:$Rd),
5249                              (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5250                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5251                              [],
5252                              NoItinerary> {
5253   bits<3> Imm;
5254   bits<5> MRm;
5255 }
5256
5257 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5258                                                     string rmlane,
5259                                                     bit u, bit szhi, bit szlo,
5260                                                     RegisterClass ResFPR,
5261                                                     RegisterClass OpFPR,
5262                                                     RegisterOperand OpVPR,
5263                                                     Operand OpImm>
5264   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5265                              (outs ResFPR:$Rd),
5266                              (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5267                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5268                              [],
5269                              NoItinerary> {
5270   let Constraints = "$src = $Rd";
5271   bits<3> Imm;
5272   bits<5> MRm;
5273 }
5274
5275 // Scalar Floating Point  multiply (scalar, by element)
5276 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5277   0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5278   let Inst{11} = Imm{1}; // h
5279   let Inst{21} = Imm{0}; // l
5280   let Inst{20-16} = MRm;
5281 }
5282 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5283   0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5284   let Inst{11} = Imm{0}; // h
5285   let Inst{21} = 0b0;    // l
5286   let Inst{20-16} = MRm;
5287 }
5288
5289 // Scalar Floating Point  multiply extended (scalar, by element)
5290 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5291   0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5292   let Inst{11} = Imm{1}; // h
5293   let Inst{21} = Imm{0}; // l
5294   let Inst{20-16} = MRm;
5295 }
5296 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5297   0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5298   let Inst{11} = Imm{0}; // h
5299   let Inst{21} = 0b0;    // l
5300   let Inst{20-16} = MRm;
5301 }
5302
5303 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5304   SDPatternOperator opnode,
5305   Instruction INST,
5306   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5307   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5308
5309   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5310                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5311              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5312
5313   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5314                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5315              (ResTy (INST (ResTy FPRC:$Rn),
5316                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5317                OpNImm:$Imm))>;
5318
5319   // swapped operands
5320   def  : Pat<(ResTy (opnode
5321                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5322                (ResTy FPRC:$Rn))),
5323              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5324
5325   def  : Pat<(ResTy (opnode
5326                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5327                (ResTy FPRC:$Rn))),
5328              (ResTy (INST (ResTy FPRC:$Rn),
5329                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5330                OpNImm:$Imm))>;
5331 }
5332
5333 // Patterns for Scalar Floating Point  multiply (scalar, by element)
5334 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5335   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5336 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5337   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5338
5339 // Patterns for Scalar Floating Point  multiply extended (scalar, by element)
5340 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5341   FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5342   v2f32, v4f32, neon_uimm1_bare>;
5343 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5344   FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5345   v1f64, v2f64, neon_uimm0_bare>;
5346
5347
5348 // Scalar Floating Point fused multiply-add (scalar, by element)
5349 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5350   0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5351   let Inst{11} = Imm{1}; // h
5352   let Inst{21} = Imm{0}; // l
5353   let Inst{20-16} = MRm;
5354 }
5355 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5356   0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5357   let Inst{11} = Imm{0}; // h
5358   let Inst{21} = 0b0;    // l
5359   let Inst{20-16} = MRm;
5360 }
5361
5362 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5363 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5364   0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5365   let Inst{11} = Imm{1}; // h
5366   let Inst{21} = Imm{0}; // l
5367   let Inst{20-16} = MRm;
5368 }
5369 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5370   0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5371   let Inst{11} = Imm{0}; // h
5372   let Inst{21} = 0b0;    // l
5373   let Inst{20-16} = MRm;
5374 }
5375 // We are allowed to match the fma instruction regardless of compile options.
5376 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5377   Instruction FMLAI, Instruction FMLSI,
5378   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5379   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5380   // fmla
5381   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5382                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5383                (ResTy FPRC:$Ra))),
5384              (ResTy (FMLAI (ResTy FPRC:$Ra),
5385                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5386
5387   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5388                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5389                (ResTy FPRC:$Ra))),
5390              (ResTy (FMLAI (ResTy FPRC:$Ra),
5391                (ResTy FPRC:$Rn),
5392                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5393                OpNImm:$Imm))>;
5394
5395   // swapped fmla operands
5396   def  : Pat<(ResTy (fma
5397                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5398                (ResTy FPRC:$Rn),
5399                (ResTy FPRC:$Ra))),
5400              (ResTy (FMLAI (ResTy FPRC:$Ra),
5401                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5402
5403   def  : Pat<(ResTy (fma
5404                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5405                (ResTy FPRC:$Rn),
5406                (ResTy FPRC:$Ra))),
5407              (ResTy (FMLAI (ResTy FPRC:$Ra),
5408                (ResTy FPRC:$Rn),
5409                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5410                OpNImm:$Imm))>;
5411
5412   // fmls
5413   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5414                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5415                (ResTy FPRC:$Ra))),
5416              (ResTy (FMLSI (ResTy FPRC:$Ra),
5417                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5418
5419   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5420                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5421                (ResTy FPRC:$Ra))),
5422              (ResTy (FMLSI (ResTy FPRC:$Ra),
5423                (ResTy FPRC:$Rn),
5424                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5425                OpNImm:$Imm))>;
5426
5427   // swapped fmls operands
5428   def  : Pat<(ResTy (fma
5429                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5430                (ResTy FPRC:$Rn),
5431                (ResTy FPRC:$Ra))),
5432              (ResTy (FMLSI (ResTy FPRC:$Ra),
5433                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5434
5435   def  : Pat<(ResTy (fma
5436                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5437                (ResTy FPRC:$Rn),
5438                (ResTy FPRC:$Ra))),
5439              (ResTy (FMLSI (ResTy FPRC:$Ra),
5440                (ResTy FPRC:$Rn),
5441                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5442                OpNImm:$Imm))>;
5443 }
5444
5445 // Scalar Floating Point fused multiply-add and
5446 // multiply-subtract (scalar, by element)
5447 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5448   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5449 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5450   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5451 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5452   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5453
5454 // Scalar Signed saturating doubling multiply long (scalar, by element)
5455 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5456   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5457   let Inst{11} = 0b0; // h
5458   let Inst{21} = Imm{1}; // l
5459   let Inst{20} = Imm{0}; // m
5460   let Inst{19-16} = MRm{3-0};
5461 }
5462 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5463   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5464   let Inst{11} = Imm{2}; // h
5465   let Inst{21} = Imm{1}; // l
5466   let Inst{20} = Imm{0}; // m
5467   let Inst{19-16} = MRm{3-0};
5468 }
5469 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5470   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5471   let Inst{11} = 0b0;    // h
5472   let Inst{21} = Imm{0}; // l
5473   let Inst{20-16} = MRm;
5474 }
5475 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5476   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5477   let Inst{11} = Imm{1};    // h
5478   let Inst{21} = Imm{0};    // l
5479   let Inst{20-16} = MRm;
5480 }
5481
5482 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5483   SDPatternOperator opnode,
5484   Instruction INST,
5485   ValueType ResTy, RegisterClass FPRC,
5486   ValueType OpVTy, ValueType OpTy,
5487   ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5488
5489   def  : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5490                (OpVTy (scalar_to_vector
5491                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5492              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5493
5494   //swapped operands
5495   def  : Pat<(ResTy (opnode
5496                (OpVTy (scalar_to_vector
5497                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5498                  (OpVTy FPRC:$Rn))),
5499              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5500 }
5501
5502
5503 // Patterns for Scalar Signed saturating doubling
5504 // multiply long (scalar, by element)
5505 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5506   SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5507   i32, VPR64Lo, neon_uimm2_bare>;
5508 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5509   SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5510   i32, VPR128Lo, neon_uimm3_bare>;
5511 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5512   SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5513   i32, VPR64Lo, neon_uimm1_bare>;
5514 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5515   SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5516   i32, VPR128Lo, neon_uimm2_bare>;
5517
5518 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5519 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5520   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5521   let Inst{11} = 0b0; // h
5522   let Inst{21} = Imm{1}; // l
5523   let Inst{20} = Imm{0}; // m
5524   let Inst{19-16} = MRm{3-0};
5525 }
5526 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5527   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5528   let Inst{11} = Imm{2}; // h
5529   let Inst{21} = Imm{1}; // l
5530   let Inst{20} = Imm{0}; // m
5531   let Inst{19-16} = MRm{3-0};
5532 }
5533 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5534   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5535   let Inst{11} = 0b0;    // h
5536   let Inst{21} = Imm{0}; // l
5537   let Inst{20-16} = MRm;
5538 }
5539 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5540   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5541   let Inst{11} = Imm{1};    // h
5542   let Inst{21} = Imm{0};    // l
5543   let Inst{20-16} = MRm;
5544 }
5545
5546 // Scalar Signed saturating doubling
5547 // multiply-subtract long (scalar, by element)
5548 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5549   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5550   let Inst{11} = 0b0; // h
5551   let Inst{21} = Imm{1}; // l
5552   let Inst{20} = Imm{0}; // m
5553   let Inst{19-16} = MRm{3-0};
5554 }
5555 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5556   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5557   let Inst{11} = Imm{2}; // h
5558   let Inst{21} = Imm{1}; // l
5559   let Inst{20} = Imm{0}; // m
5560   let Inst{19-16} = MRm{3-0};
5561 }
5562 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5563   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5564   let Inst{11} = 0b0;    // h
5565   let Inst{21} = Imm{0}; // l
5566   let Inst{20-16} = MRm;
5567 }
5568 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5569   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5570   let Inst{11} = Imm{1};    // h
5571   let Inst{21} = Imm{0};    // l
5572   let Inst{20-16} = MRm;
5573 }
5574
5575 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5576   SDPatternOperator opnode,
5577   SDPatternOperator coreopnode,
5578   Instruction INST,
5579   ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5580   ValueType OpTy,
5581   ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5582
5583   def  : Pat<(ResTy (opnode
5584                (ResTy ResFPRC:$Ra),
5585                (ResTy (coreopnode (OpTy FPRC:$Rn),
5586                  (OpTy (scalar_to_vector
5587                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5588              (ResTy (INST (ResTy ResFPRC:$Ra),
5589                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5590
5591   // swapped operands
5592   def  : Pat<(ResTy (opnode
5593                (ResTy ResFPRC:$Ra),
5594                (ResTy (coreopnode
5595                  (OpTy (scalar_to_vector
5596                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5597                  (OpTy FPRC:$Rn))))),
5598              (ResTy (INST (ResTy ResFPRC:$Ra),
5599                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5600 }
5601
5602 // Patterns for Scalar Signed saturating
5603 // doubling multiply-add long (scalar, by element)
5604 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5605   int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5606   i32, VPR64Lo, neon_uimm2_bare>;
5607 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5608   int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5609   i32, VPR128Lo, neon_uimm3_bare>;
5610 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5611   int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5612   i32, VPR64Lo, neon_uimm1_bare>;
5613 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5614   int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5615   i32, VPR128Lo, neon_uimm2_bare>;
5616
5617 // Patterns for Scalar Signed saturating
5618 // doubling multiply-sub long (scalar, by element)
5619 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5620   int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5621   i32, VPR64Lo, neon_uimm2_bare>;
5622 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5623   int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5624   i32, VPR128Lo, neon_uimm3_bare>;
5625 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5626   int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5627   i32, VPR64Lo, neon_uimm1_bare>;
5628 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5629   int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5630   i32, VPR128Lo, neon_uimm2_bare>;
5631
5632
5633 // Scalar Signed saturating doubling multiply returning
5634 // high half (scalar, by element)
5635 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5636   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5637   let Inst{11} = 0b0; // h
5638   let Inst{21} = Imm{1}; // l
5639   let Inst{20} = Imm{0}; // m
5640   let Inst{19-16} = MRm{3-0};
5641 }
5642 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5643   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5644   let Inst{11} = Imm{2}; // h
5645   let Inst{21} = Imm{1}; // l
5646   let Inst{20} = Imm{0}; // m
5647   let Inst{19-16} = MRm{3-0};
5648 }
5649 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5650   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5651   let Inst{11} = 0b0;    // h
5652   let Inst{21} = Imm{0}; // l
5653   let Inst{20-16} = MRm;
5654 }
5655 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5656   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5657   let Inst{11} = Imm{1};    // h
5658   let Inst{21} = Imm{0};    // l
5659   let Inst{20-16} = MRm;
5660 }
5661
5662 // Patterns for Scalar Signed saturating doubling multiply returning
5663 // high half (scalar, by element)
5664 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5665   SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5666   i32, VPR64Lo, neon_uimm2_bare>;
5667 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5668   SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5669   i32, VPR128Lo, neon_uimm3_bare>;
5670 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5671   SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5672   i32, VPR64Lo, neon_uimm1_bare>;
5673 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5674   SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5675   i32, VPR128Lo, neon_uimm2_bare>;
5676
5677 // Scalar Signed saturating rounding doubling multiply
5678 // returning high half (scalar, by element)
5679 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5680   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5681   let Inst{11} = 0b0; // h
5682   let Inst{21} = Imm{1}; // l
5683   let Inst{20} = Imm{0}; // m
5684   let Inst{19-16} = MRm{3-0};
5685 }
5686 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5687   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5688   let Inst{11} = Imm{2}; // h
5689   let Inst{21} = Imm{1}; // l
5690   let Inst{20} = Imm{0}; // m
5691   let Inst{19-16} = MRm{3-0};
5692 }
5693 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5694   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5695   let Inst{11} = 0b0;    // h
5696   let Inst{21} = Imm{0}; // l
5697   let Inst{20-16} = MRm;
5698 }
5699 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5700   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5701   let Inst{11} = Imm{1};    // h
5702   let Inst{21} = Imm{0};    // l
5703   let Inst{20-16} = MRm;
5704 }
5705
5706 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5707   SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
5708   VPR64Lo, neon_uimm2_bare>;
5709 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5710   SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
5711   VPR128Lo, neon_uimm3_bare>;
5712 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5713   SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
5714   VPR64Lo, neon_uimm1_bare>;
5715 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5716   SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
5717   VPR128Lo, neon_uimm2_bare>;
5718
5719 // Scalar Copy - DUP element to scalar
5720 class NeonI_Scalar_DUP<string asmop, string asmlane,
5721                        RegisterClass ResRC, RegisterOperand VPRC,
5722                        Operand OpImm>
5723   : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
5724                      asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
5725                      [],
5726                      NoItinerary> {
5727   bits<4> Imm;
5728 }
5729
5730 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
5731   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5732 }
5733 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
5734   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5735 }
5736 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
5737   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5738 }
5739 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
5740   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5741 }
5742
5743 multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
5744   ValueType OpTy, Operand OpImm,
5745   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5746   def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5747             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5748
5749   def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5750             (ResTy (DUPI
5751               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5752                 OpNImm:$Imm))>;
5753 }
5754
5755 // Patterns for vector extract of FP data using scalar DUP instructions
5756 defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
5757   v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5758 defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64,
5759   v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5760
5761 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
5762   ValueType ResTy, ValueType OpTy,Operand OpLImm,
5763   ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
5764
5765   def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
5766             (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
5767
5768   def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
5769             (ResTy (DUPI
5770               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5771                 OpNImm:$Imm))>;
5772 }
5773
5774 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
5775 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
5776                                         v8i8, v16i8, neon_uimm3_bare>;
5777 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
5778                                         v4i16, v8i16, neon_uimm2_bare>;
5779 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
5780                                         v2i32, v4i32, neon_uimm1_bare>;
5781
5782 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
5783                                           ValueType OpTy, ValueType ElemTy,
5784                                           Operand OpImm, ValueType OpNTy,
5785                                           ValueType ExTy, Operand OpNImm> {
5786
5787   def : Pat<(ResTy (vector_insert (ResTy undef),
5788               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5789               (neon_uimm0_bare:$Imm))),
5790             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5791
5792   def : Pat<(ResTy (vector_insert (ResTy undef),
5793               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5794               (OpNImm:$Imm))),
5795             (ResTy (DUPI
5796               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5797               OpNImm:$Imm))>;
5798 }
5799
5800 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
5801                                           ValueType OpTy, ValueType ElemTy,
5802                                           Operand OpImm, ValueType OpNTy,
5803                                           ValueType ExTy, Operand OpNImm> {
5804
5805   def : Pat<(ResTy (scalar_to_vector
5806               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
5807             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5808
5809   def : Pat<(ResTy (scalar_to_vector
5810               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
5811             (ResTy (DUPI
5812               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5813               OpNImm:$Imm))>;
5814 }
5815
5816 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
5817 // instructions.
5818 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5819   v1i64, v2i64, i64, neon_uimm1_bare,
5820   v1i64, v2i64, neon_uimm0_bare>;
5821 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
5822   v1i32, v4i32, i32, neon_uimm2_bare,
5823   v2i32, v4i32, neon_uimm1_bare>;
5824 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
5825   v1i16, v8i16, i32, neon_uimm3_bare,
5826   v4i16, v8i16, neon_uimm2_bare>;
5827 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
5828   v1i8, v16i8, i32, neon_uimm4_bare,
5829   v8i8, v16i8, neon_uimm3_bare>;
5830 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5831   v1f64, v2f64, f64, neon_uimm1_bare,
5832   v1f64, v2f64, neon_uimm0_bare>;
5833 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
5834   v1f32, v4f32, f32, neon_uimm2_bare,
5835   v2f32, v4f32, neon_uimm1_bare>;
5836 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
5837   v1i64, v2i64, i64, neon_uimm1_bare,
5838   v1i64, v2i64, neon_uimm0_bare>;
5839 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
5840   v1i32, v4i32, i32, neon_uimm2_bare,
5841   v2i32, v4i32, neon_uimm1_bare>;
5842 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
5843   v1i16, v8i16, i32, neon_uimm3_bare,
5844   v4i16, v8i16, neon_uimm2_bare>;
5845 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
5846   v1i8, v16i8, i32, neon_uimm4_bare,
5847   v8i8, v16i8, neon_uimm3_bare>;
5848 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
5849   v1f64, v2f64, f64, neon_uimm1_bare,
5850   v1f64, v2f64, neon_uimm0_bare>;
5851 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
5852   v1f32, v4f32, f32, neon_uimm2_bare,
5853   v2f32, v4f32, neon_uimm1_bare>;
5854
5855 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
5856                                   Instruction DUPI, Operand OpImm,
5857                                   RegisterClass ResRC> {
5858   def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
5859           (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
5860 }
5861
5862 // Aliases for Scalar copy - DUP element (scalar)
5863 // FIXME: This is actually the preferred syntax but TableGen can't deal with
5864 // custom printing of aliases.
5865 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
5866 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
5867 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
5868 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
5869
5870 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
5871                       ValueType OpTy> {
5872   def : Pat<(ResTy (GetLow VPR128:$Rn)),
5873             (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
5874   def : Pat<(ResTy (GetHigh VPR128:$Rn)),
5875             (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
5876 }
5877
5878 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
5879 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
5880 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
5881 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
5882 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
5883 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
5884
5885 //===----------------------------------------------------------------------===//
5886 // Non-Instruction Patterns
5887 //===----------------------------------------------------------------------===//
5888
5889 // 64-bit vector bitcasts...
5890
5891 def : Pat<(v1i64 (bitconvert (v8i8  VPR64:$src))), (v1i64 VPR64:$src)>;
5892 def : Pat<(v2f32 (bitconvert (v8i8  VPR64:$src))), (v2f32 VPR64:$src)>;
5893 def : Pat<(v2i32 (bitconvert (v8i8  VPR64:$src))), (v2i32 VPR64:$src)>;
5894 def : Pat<(v4i16 (bitconvert (v8i8  VPR64:$src))), (v4i16 VPR64:$src)>;
5895
5896 def : Pat<(v1i64 (bitconvert (v4i16  VPR64:$src))), (v1i64 VPR64:$src)>;
5897 def : Pat<(v2i32 (bitconvert (v4i16  VPR64:$src))), (v2i32 VPR64:$src)>;
5898 def : Pat<(v2f32 (bitconvert (v4i16  VPR64:$src))), (v2f32 VPR64:$src)>;
5899 def : Pat<(v8i8  (bitconvert (v4i16  VPR64:$src))), (v8i8 VPR64:$src)>;
5900
5901 def : Pat<(v1i64 (bitconvert (v2i32  VPR64:$src))), (v1i64 VPR64:$src)>;
5902 def : Pat<(v2f32 (bitconvert (v2i32  VPR64:$src))), (v2f32 VPR64:$src)>;
5903 def : Pat<(v4i16 (bitconvert (v2i32  VPR64:$src))), (v4i16 VPR64:$src)>;
5904 def : Pat<(v8i8  (bitconvert (v2i32  VPR64:$src))), (v8i8 VPR64:$src)>;
5905
5906 def : Pat<(v1i64 (bitconvert (v2f32  VPR64:$src))), (v1i64 VPR64:$src)>;
5907 def : Pat<(v2i32 (bitconvert (v2f32  VPR64:$src))), (v2i32 VPR64:$src)>;
5908 def : Pat<(v4i16 (bitconvert (v2f32  VPR64:$src))), (v4i16 VPR64:$src)>;
5909 def : Pat<(v8i8  (bitconvert (v2f32  VPR64:$src))), (v8i8 VPR64:$src)>;
5910
5911 def : Pat<(v2f32 (bitconvert (v1i64  VPR64:$src))), (v2f32 VPR64:$src)>;
5912 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
5913 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
5914 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
5915
5916 // ..and 128-bit vector bitcasts...
5917
5918 def : Pat<(v2f64 (bitconvert (v16i8  VPR128:$src))), (v2f64 VPR128:$src)>;
5919 def : Pat<(v2i64 (bitconvert (v16i8  VPR128:$src))), (v2i64 VPR128:$src)>;
5920 def : Pat<(v4f32 (bitconvert (v16i8  VPR128:$src))), (v4f32 VPR128:$src)>;
5921 def : Pat<(v4i32 (bitconvert (v16i8  VPR128:$src))), (v4i32 VPR128:$src)>;
5922 def : Pat<(v8i16 (bitconvert (v16i8  VPR128:$src))), (v8i16 VPR128:$src)>;
5923
5924 def : Pat<(v2f64 (bitconvert (v8i16  VPR128:$src))), (v2f64 VPR128:$src)>;
5925 def : Pat<(v2i64 (bitconvert (v8i16  VPR128:$src))), (v2i64 VPR128:$src)>;
5926 def : Pat<(v4i32 (bitconvert (v8i16  VPR128:$src))), (v4i32 VPR128:$src)>;
5927 def : Pat<(v4f32 (bitconvert (v8i16  VPR128:$src))), (v4f32 VPR128:$src)>;
5928 def : Pat<(v16i8 (bitconvert (v8i16  VPR128:$src))), (v16i8 VPR128:$src)>;
5929
5930 def : Pat<(v2f64 (bitconvert (v4i32  VPR128:$src))), (v2f64 VPR128:$src)>;
5931 def : Pat<(v2i64 (bitconvert (v4i32  VPR128:$src))), (v2i64 VPR128:$src)>;
5932 def : Pat<(v4f32 (bitconvert (v4i32  VPR128:$src))), (v4f32 VPR128:$src)>;
5933 def : Pat<(v8i16 (bitconvert (v4i32  VPR128:$src))), (v8i16 VPR128:$src)>;
5934 def : Pat<(v16i8 (bitconvert (v4i32  VPR128:$src))), (v16i8 VPR128:$src)>;
5935
5936 def : Pat<(v2f64 (bitconvert (v4f32  VPR128:$src))), (v2f64 VPR128:$src)>;
5937 def : Pat<(v2i64 (bitconvert (v4f32  VPR128:$src))), (v2i64 VPR128:$src)>;
5938 def : Pat<(v4i32 (bitconvert (v4f32  VPR128:$src))), (v4i32 VPR128:$src)>;
5939 def : Pat<(v8i16 (bitconvert (v4f32  VPR128:$src))), (v8i16 VPR128:$src)>;
5940 def : Pat<(v16i8 (bitconvert (v4f32  VPR128:$src))), (v16i8 VPR128:$src)>;
5941
5942 def : Pat<(v2f64 (bitconvert (v2i64  VPR128:$src))), (v2f64 VPR128:$src)>;
5943 def : Pat<(v4f32 (bitconvert (v2i64  VPR128:$src))), (v4f32 VPR128:$src)>;
5944 def : Pat<(v4i32 (bitconvert (v2i64  VPR128:$src))), (v4i32 VPR128:$src)>;
5945 def : Pat<(v8i16 (bitconvert (v2i64  VPR128:$src))), (v8i16 VPR128:$src)>;
5946 def : Pat<(v16i8 (bitconvert (v2i64  VPR128:$src))), (v16i8 VPR128:$src)>;
5947
5948 def : Pat<(v2i64 (bitconvert (v2f64  VPR128:$src))), (v2i64 VPR128:$src)>;
5949 def : Pat<(v4f32 (bitconvert (v2f64  VPR128:$src))), (v4f32 VPR128:$src)>;
5950 def : Pat<(v4i32 (bitconvert (v2f64  VPR128:$src))), (v4i32 VPR128:$src)>;
5951 def : Pat<(v8i16 (bitconvert (v2f64  VPR128:$src))), (v8i16 VPR128:$src)>;
5952 def : Pat<(v16i8 (bitconvert (v2f64  VPR128:$src))), (v16i8 VPR128:$src)>;
5953
5954
5955 // ...and scalar bitcasts...
5956 def : Pat<(f16 (bitconvert (v1i16  FPR16:$src))), (f16 FPR16:$src)>;
5957 def : Pat<(f32 (bitconvert (v1i32  FPR32:$src))), (f32 FPR32:$src)>;
5958 def : Pat<(f64 (bitconvert (v1i64  FPR64:$src))), (f64 FPR64:$src)>;
5959 def : Pat<(f32 (bitconvert (v1f32  FPR32:$src))), (f32 FPR32:$src)>;
5960 def : Pat<(f64 (bitconvert (v1f64  FPR64:$src))), (f64 FPR64:$src)>;
5961
5962 def : Pat<(i64 (bitconvert (v1i64  FPR64:$src))), (FMOVxd $src)>;
5963 def : Pat<(i64 (bitconvert (v1f64  FPR64:$src))), (FMOVxd $src)>;
5964 def : Pat<(i64 (bitconvert (v2i32  FPR64:$src))), (FMOVxd $src)>;
5965 def : Pat<(i64 (bitconvert (v2f32  FPR64:$src))), (FMOVxd $src)>;
5966 def : Pat<(i64 (bitconvert (v4i16  FPR64:$src))), (FMOVxd $src)>;
5967 def : Pat<(i64 (bitconvert (v8i8  FPR64:$src))), (FMOVxd $src)>;
5968
5969 def : Pat<(i32 (bitconvert (v1i32  FPR32:$src))), (FMOVws $src)>;
5970
5971 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
5972 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
5973 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
5974
5975 def : Pat<(f64   (bitconvert (v8i8  VPR64:$src))), (f64 VPR64:$src)>;
5976 def : Pat<(f64   (bitconvert (v4i16  VPR64:$src))), (f64 VPR64:$src)>;
5977 def : Pat<(f64   (bitconvert (v2i32  VPR64:$src))), (f64 VPR64:$src)>;
5978 def : Pat<(f64   (bitconvert (v2f32  VPR64:$src))), (f64 VPR64:$src)>;
5979 def : Pat<(f64   (bitconvert (v1i64  VPR64:$src))), (f64 VPR64:$src)>;
5980
5981 def : Pat<(f128  (bitconvert (v16i8  VPR128:$src))), (f128 VPR128:$src)>;
5982 def : Pat<(f128  (bitconvert (v8i16  VPR128:$src))), (f128 VPR128:$src)>;
5983 def : Pat<(f128  (bitconvert (v4i32  VPR128:$src))), (f128 VPR128:$src)>;
5984 def : Pat<(f128  (bitconvert (v2i64  VPR128:$src))), (f128 VPR128:$src)>;
5985 def : Pat<(f128  (bitconvert (v4f32  VPR128:$src))), (f128 VPR128:$src)>;
5986 def : Pat<(f128  (bitconvert (v2f64  VPR128:$src))), (f128 VPR128:$src)>;
5987
5988 def : Pat<(v1i16 (bitconvert (f16  FPR16:$src))), (v1i16 FPR16:$src)>;
5989 def : Pat<(v1i32 (bitconvert (f32  FPR32:$src))), (v1i32 FPR32:$src)>;
5990 def : Pat<(v1i64 (bitconvert (f64  FPR64:$src))), (v1i64 FPR64:$src)>;
5991 def : Pat<(v1f32 (bitconvert (f32  FPR32:$src))), (v1f32 FPR32:$src)>;
5992 def : Pat<(v1f64 (bitconvert (f64  FPR64:$src))), (v1f64 FPR64:$src)>;
5993
5994 def : Pat<(v1i64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
5995 def : Pat<(v1f64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
5996 def : Pat<(v2i32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
5997 def : Pat<(v2f32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
5998 def : Pat<(v4i16 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
5999 def : Pat<(v8i8 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6000
6001 def : Pat<(v1i32 (bitconvert (i32  GPR32:$src))), (FMOVsw $src)>;
6002
6003 def : Pat<(v8i8   (bitconvert (f64   FPR64:$src))), (v8i8 FPR64:$src)>;
6004 def : Pat<(v4i16  (bitconvert (f64   FPR64:$src))), (v4i16 FPR64:$src)>;
6005 def : Pat<(v2i32  (bitconvert (f64   FPR64:$src))), (v2i32 FPR64:$src)>;
6006 def : Pat<(v2f32  (bitconvert (f64   FPR64:$src))), (v2f32 FPR64:$src)>;
6007 def : Pat<(v1i64  (bitconvert (f64   FPR64:$src))), (v1i64 FPR64:$src)>;
6008
6009 def : Pat<(v16i8  (bitconvert (f128   FPR128:$src))), (v16i8 FPR128:$src)>;
6010 def : Pat<(v8i16  (bitconvert (f128   FPR128:$src))), (v8i16 FPR128:$src)>;
6011 def : Pat<(v4i32  (bitconvert (f128   FPR128:$src))), (v4i32 FPR128:$src)>;
6012 def : Pat<(v2i64  (bitconvert (f128   FPR128:$src))), (v2i64 FPR128:$src)>;
6013 def : Pat<(v4f32  (bitconvert (f128   FPR128:$src))), (v4f32 FPR128:$src)>;
6014 def : Pat<(v2f64  (bitconvert (f128   FPR128:$src))), (v2f64 FPR128:$src)>;
6015
6016 // Scalar Three Same
6017
6018 def neon_uimm3 : Operand<i64>,
6019                    ImmLeaf<i64, [{return Imm < 8;}]> {
6020   let ParserMatchClass = uimm3_asmoperand;
6021   let PrintMethod = "printUImmHexOperand";
6022 }
6023
6024 def neon_uimm4 : Operand<i64>,
6025                    ImmLeaf<i64, [{return Imm < 16;}]> {
6026   let ParserMatchClass = uimm4_asmoperand;
6027   let PrintMethod = "printUImmHexOperand";
6028 }
6029
6030 // Bitwise Extract
6031 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6032                     string OpS, RegisterOperand OpVPR, Operand OpImm>
6033   : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6034                      (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6035                      asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6036                      ", $Rm." # OpS # ", $Index",
6037                      [],
6038                      NoItinerary>{
6039   bits<4> Index;
6040 }
6041
6042 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6043                                VPR64, neon_uimm3> {
6044   let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6045 }
6046
6047 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6048                                VPR128, neon_uimm4> {
6049   let Inst{14-11} = Index;
6050 }
6051
6052 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6053                  Operand OpImm>
6054   : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6055                                  (i64 OpImm:$Imm))),
6056               (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6057
6058 def : NI_Extract<v8i8,  VPR64,  EXTvvvi_8b,  neon_uimm3>;
6059 def : NI_Extract<v4i16, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6060 def : NI_Extract<v2i32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6061 def : NI_Extract<v1i64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6062 def : NI_Extract<v2f32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6063 def : NI_Extract<v1f64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6064 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6065 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6066 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6067 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6068 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6069 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6070
6071 // Table lookup
6072 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6073              string asmop, string OpS, RegisterOperand OpVPR,
6074              RegisterOperand VecList>
6075   : NeonI_TBL<q, op2, len, op,
6076               (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6077               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6078               [],
6079               NoItinerary>;
6080
6081 // The vectors in look up table are always 16b
6082 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6083   def _8b  : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6084                     !cast<RegisterOperand>(List # "16B_operand")>;
6085
6086   def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6087                     !cast<RegisterOperand>(List # "16B_operand")>;
6088 }
6089
6090 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6091 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6092 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6093 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6094
6095 // Table lookup extention
6096 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6097              string asmop, string OpS, RegisterOperand OpVPR,
6098              RegisterOperand VecList>
6099   : NeonI_TBL<q, op2, len, op,
6100               (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6101               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6102               [],
6103               NoItinerary> {
6104   let Constraints = "$src = $Rd";
6105 }
6106
6107 // The vectors in look up table are always 16b
6108 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6109   def _8b  : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6110                     !cast<RegisterOperand>(List # "16B_operand")>;
6111
6112   def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6113                     !cast<RegisterOperand>(List # "16B_operand")>;
6114 }
6115
6116 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6117 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6118 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6119 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6120
6121 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6122                      RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6123   : NeonI_copy<0b1, 0b0, 0b0011,
6124                (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6125                asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6126                [(set (ResTy VPR128:$Rd),
6127                  (ResTy (vector_insert
6128                    (ResTy VPR128:$src),
6129                    (OpTy OpGPR:$Rn),
6130                    (OpImm:$Imm))))],
6131                NoItinerary> {
6132   bits<4> Imm;
6133   let Constraints = "$src = $Rd";
6134 }
6135
6136 //Insert element (vector, from main)
6137 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6138                            neon_uimm4_bare> {
6139   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6140 }
6141 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6142                            neon_uimm3_bare> {
6143   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6144 }
6145 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6146                            neon_uimm2_bare> {
6147   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6148 }
6149 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6150                            neon_uimm1_bare> {
6151   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6152 }
6153
6154 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6155                     (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6156 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6157                     (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6158 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6159                     (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6160 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6161                     (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6162
6163 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6164                              RegisterClass OpGPR, ValueType OpTy,
6165                              Operand OpImm, Instruction INS>
6166   : Pat<(ResTy (vector_insert
6167               (ResTy VPR64:$src),
6168               (OpTy OpGPR:$Rn),
6169               (OpImm:$Imm))),
6170         (ResTy (EXTRACT_SUBREG
6171           (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6172             OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6173
6174 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6175                                           neon_uimm3_bare, INSbw>;
6176 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6177                                           neon_uimm2_bare, INShw>;
6178 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6179                                           neon_uimm1_bare, INSsw>;
6180 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6181                                           neon_uimm0_bare, INSdx>;
6182
6183 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6184   : NeonI_insert<0b1, 0b1,
6185                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6186                  ResImm:$Immd, ResImm:$Immn),
6187                  asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6188                  [],
6189                  NoItinerary> {
6190   let Constraints = "$src = $Rd";
6191   bits<4> Immd;
6192   bits<4> Immn;
6193 }
6194
6195 //Insert element (vector, from element)
6196 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6197   let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6198   let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6199 }
6200 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6201   let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6202   let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6203   // bit 11 is unspecified, but should be set to zero.
6204 }
6205 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6206   let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6207   let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6208   // bits 11-12 are unspecified, but should be set to zero.
6209 }
6210 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6211   let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6212   let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6213   // bits 11-13 are unspecified, but should be set to zero.
6214 }
6215
6216 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6217                     (INSELb VPR128:$Rd, VPR128:$Rn,
6218                       neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6219 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6220                     (INSELh VPR128:$Rd, VPR128:$Rn,
6221                       neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6222 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6223                     (INSELs VPR128:$Rd, VPR128:$Rn,
6224                       neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6225 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6226                     (INSELd VPR128:$Rd, VPR128:$Rn,
6227                       neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6228
6229 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6230                                 ValueType MidTy, Operand StImm, Operand NaImm,
6231                                 Instruction INS> {
6232 def : Pat<(ResTy (vector_insert
6233             (ResTy VPR128:$src),
6234             (MidTy (vector_extract
6235               (ResTy VPR128:$Rn),
6236               (StImm:$Immn))),
6237             (StImm:$Immd))),
6238           (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6239               StImm:$Immd, StImm:$Immn)>;
6240
6241 def : Pat <(ResTy (vector_insert
6242              (ResTy VPR128:$src),
6243              (MidTy (vector_extract
6244                (NaTy VPR64:$Rn),
6245                (NaImm:$Immn))),
6246              (StImm:$Immd))),
6247            (INS (ResTy VPR128:$src),
6248              (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6249              StImm:$Immd, NaImm:$Immn)>;
6250
6251 def : Pat <(NaTy (vector_insert
6252              (NaTy VPR64:$src),
6253              (MidTy (vector_extract
6254                (ResTy VPR128:$Rn),
6255                (StImm:$Immn))),
6256              (NaImm:$Immd))),
6257            (NaTy (EXTRACT_SUBREG
6258              (ResTy (INS
6259                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6260                (ResTy VPR128:$Rn),
6261                NaImm:$Immd, StImm:$Immn)),
6262              sub_64))>;
6263
6264 def : Pat <(NaTy (vector_insert
6265              (NaTy VPR64:$src),
6266              (MidTy (vector_extract
6267                (NaTy VPR64:$Rn),
6268                (NaImm:$Immn))),
6269              (NaImm:$Immd))),
6270            (NaTy (EXTRACT_SUBREG
6271              (ResTy (INS
6272                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6273                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6274                NaImm:$Immd, NaImm:$Immn)),
6275              sub_64))>;
6276 }
6277
6278 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6279                             neon_uimm1_bare, INSELs>;
6280 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6281                             neon_uimm0_bare, INSELd>;
6282 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6283                             neon_uimm3_bare, INSELb>;
6284 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6285                             neon_uimm2_bare, INSELh>;
6286 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6287                             neon_uimm1_bare, INSELs>;
6288 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6289                             neon_uimm0_bare, INSELd>;
6290
6291 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6292                                       ValueType MidTy,
6293                                       RegisterClass OpFPR, Operand ResImm,
6294                                       SubRegIndex SubIndex, Instruction INS> {
6295 def : Pat <(ResTy (vector_insert
6296              (ResTy VPR128:$src),
6297              (MidTy OpFPR:$Rn),
6298              (ResImm:$Imm))),
6299            (INS (ResTy VPR128:$src),
6300              (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6301              ResImm:$Imm,
6302              (i64 0))>;
6303
6304 def : Pat <(NaTy (vector_insert
6305              (NaTy VPR64:$src),
6306              (MidTy OpFPR:$Rn),
6307              (ResImm:$Imm))),
6308            (NaTy (EXTRACT_SUBREG
6309              (ResTy (INS
6310                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6311                (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6312                ResImm:$Imm,
6313                (i64 0))),
6314              sub_64))>;
6315 }
6316
6317 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6318                                   sub_32, INSELs>;
6319 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6320                                   sub_64, INSELd>;
6321
6322 class NeonI_SMOV<string asmop, string Res, bit Q,
6323                  ValueType OpTy, ValueType eleTy,
6324                  Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6325   : NeonI_copy<Q, 0b0, 0b0101,
6326                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6327                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6328                [(set (ResTy ResGPR:$Rd),
6329                  (ResTy (sext_inreg
6330                    (ResTy (vector_extract
6331                      (OpTy VPR128:$Rn), (OpImm:$Imm))),
6332                    eleTy)))],
6333                NoItinerary> {
6334   bits<4> Imm;
6335 }
6336
6337 //Signed integer move (main, from element)
6338 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6339                         GPR32, i32> {
6340   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6341 }
6342 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6343                         GPR32, i32> {
6344   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6345 }
6346 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6347                         GPR64, i64> {
6348   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6349 }
6350 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6351                         GPR64, i64> {
6352   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6353 }
6354 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6355                         GPR64, i64> {
6356   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6357 }
6358
6359 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6360                                ValueType eleTy, Operand StImm,  Operand NaImm,
6361                                Instruction SMOVI> {
6362   def : Pat<(i64 (sext_inreg
6363               (i64 (anyext
6364                 (i32 (vector_extract
6365                   (StTy VPR128:$Rn), (StImm:$Imm))))),
6366               eleTy)),
6367             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6368
6369   def : Pat<(i64 (sext
6370               (i32 (vector_extract
6371                 (StTy VPR128:$Rn), (StImm:$Imm))))),
6372             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6373
6374   def : Pat<(i64 (sext_inreg
6375               (i64 (vector_extract
6376                 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6377               eleTy)),
6378             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6379               NaImm:$Imm)>;
6380
6381   def : Pat<(i64 (sext_inreg
6382               (i64 (anyext
6383                 (i32 (vector_extract
6384                   (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6385               eleTy)),
6386             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6387               NaImm:$Imm)>;
6388
6389   def : Pat<(i64 (sext
6390               (i32 (vector_extract
6391                 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6392             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6393               NaImm:$Imm)>;
6394 }
6395
6396 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6397                           neon_uimm3_bare, SMOVxb>;
6398 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6399                           neon_uimm2_bare, SMOVxh>;
6400 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6401                           neon_uimm1_bare, SMOVxs>;
6402
6403 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6404                           ValueType eleTy, Operand StImm,  Operand NaImm,
6405                           Instruction SMOVI>
6406   : Pat<(i32 (sext_inreg
6407           (i32 (vector_extract
6408             (NaTy VPR64:$Rn), (NaImm:$Imm))),
6409           eleTy)),
6410         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6411           NaImm:$Imm)>;
6412
6413 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6414                          neon_uimm3_bare, SMOVwb>;
6415 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6416                          neon_uimm2_bare, SMOVwh>;
6417
6418 class NeonI_UMOV<string asmop, string Res, bit Q,
6419                  ValueType OpTy, Operand OpImm,
6420                  RegisterClass ResGPR, ValueType ResTy>
6421   : NeonI_copy<Q, 0b0, 0b0111,
6422                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6423                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6424                [(set (ResTy ResGPR:$Rd),
6425                   (ResTy (vector_extract
6426                     (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6427                NoItinerary> {
6428   bits<4> Imm;
6429 }
6430
6431 //Unsigned integer move (main, from element)
6432 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6433                          GPR32, i32> {
6434   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6435 }
6436 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6437                          GPR32, i32> {
6438   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6439 }
6440 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6441                          GPR32, i32> {
6442   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6443 }
6444 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6445                          GPR64, i64> {
6446   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6447 }
6448
6449 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6450                     (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6451 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6452                     (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6453
6454 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6455                          Operand StImm,  Operand NaImm,
6456                          Instruction SMOVI>
6457   : Pat<(ResTy (vector_extract
6458           (NaTy VPR64:$Rn), NaImm:$Imm)),
6459         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6460           NaImm:$Imm)>;
6461
6462 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6463                         neon_uimm3_bare, UMOVwb>;
6464 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6465                         neon_uimm2_bare, UMOVwh>;
6466 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6467                         neon_uimm1_bare, UMOVws>;
6468
6469 def : Pat<(i32 (and
6470             (i32 (vector_extract
6471               (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6472             255)),
6473           (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6474
6475 def : Pat<(i32 (and
6476             (i32 (vector_extract
6477               (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6478             65535)),
6479           (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6480
6481 def : Pat<(i64 (zext
6482             (i32 (vector_extract
6483               (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6484           (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6485
6486 def : Pat<(i32 (and
6487             (i32 (vector_extract
6488               (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6489             255)),
6490           (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6491             neon_uimm3_bare:$Imm)>;
6492
6493 def : Pat<(i32 (and
6494             (i32 (vector_extract
6495               (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6496             65535)),
6497           (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6498             neon_uimm2_bare:$Imm)>;
6499
6500 def : Pat<(i64 (zext
6501             (i32 (vector_extract
6502               (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6503           (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6504             neon_uimm0_bare:$Imm)>;
6505
6506 // Additional copy patterns for scalar types
6507 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6508           (UMOVwb (v16i8
6509             (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6510
6511 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6512           (UMOVwh (v8i16
6513             (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6514
6515 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6516           (FMOVws FPR32:$Rn)>;
6517
6518 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6519           (FMOVxd FPR64:$Rn)>;
6520
6521 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6522           (f64 FPR64:$Rn)>;
6523
6524 def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
6525           (f32 FPR32:$Rn)>;
6526
6527 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6528           (v1i8 (EXTRACT_SUBREG (v16i8
6529             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6530             sub_8))>;
6531
6532 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6533           (v1i16 (EXTRACT_SUBREG (v8i16
6534             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6535             sub_16))>;
6536
6537 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6538           (FMOVsw $src)>;
6539
6540 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6541           (FMOVdx $src)>;
6542
6543 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
6544           (v1f32 FPR32:$Rn)>;
6545 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6546           (v1f64 FPR64:$Rn)>;
6547
6548 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
6549           (FMOVdd $src)>;
6550
6551 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6552           (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6553                          (f64 FPR64:$src), sub_64)>;
6554
6555 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane,  string rnlane,
6556                     RegisterOperand ResVPR, Operand OpImm>
6557   : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6558                (ins VPR128:$Rn, OpImm:$Imm),
6559                asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6560                [],
6561                NoItinerary> {
6562   bits<4> Imm;
6563 }
6564
6565 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6566                               neon_uimm4_bare> {
6567   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6568 }
6569
6570 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6571                               neon_uimm3_bare> {
6572   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6573 }
6574
6575 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6576                               neon_uimm2_bare> {
6577   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6578 }
6579
6580 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6581                               neon_uimm1_bare> {
6582   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6583 }
6584
6585 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6586                               neon_uimm4_bare> {
6587   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6588 }
6589
6590 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6591                               neon_uimm3_bare> {
6592   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6593 }
6594
6595 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6596                               neon_uimm2_bare> {
6597   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6598 }
6599
6600 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6601                                        ValueType OpTy,ValueType NaTy,
6602                                        ValueType ExTy, Operand OpLImm,
6603                                        Operand OpNImm> {
6604 def  : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6605         (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6606
6607 def : Pat<(ResTy (Neon_vduplane
6608             (NaTy VPR64:$Rn), OpNImm:$Imm)),
6609           (ResTy (DUPELT
6610             (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6611 }
6612 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6613                              neon_uimm4_bare, neon_uimm3_bare>;
6614 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6615                              neon_uimm4_bare, neon_uimm3_bare>;
6616 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6617                              neon_uimm3_bare, neon_uimm2_bare>;
6618 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6619                              neon_uimm3_bare, neon_uimm2_bare>;
6620 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6621                              neon_uimm2_bare, neon_uimm1_bare>;
6622 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6623                              neon_uimm2_bare, neon_uimm1_bare>;
6624 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6625                              neon_uimm1_bare, neon_uimm0_bare>;
6626 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6627                              neon_uimm2_bare, neon_uimm1_bare>;
6628 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6629                              neon_uimm2_bare, neon_uimm1_bare>;
6630 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6631                              neon_uimm1_bare, neon_uimm0_bare>;
6632
6633 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6634           (v2f32 (DUPELT2s
6635             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6636             (i64 0)))>;
6637 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6638           (v4f32 (DUPELT4s
6639             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6640             (i64 0)))>;
6641 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
6642           (v2f64 (DUPELT2d
6643             (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
6644             (i64 0)))>;
6645
6646 class NeonI_DUP<bit Q, string asmop, string rdlane,
6647                 RegisterOperand ResVPR, ValueType ResTy,
6648                 RegisterClass OpGPR, ValueType OpTy>
6649   : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
6650                asmop # "\t$Rd" # rdlane # ", $Rn",
6651                [(set (ResTy ResVPR:$Rd),
6652                  (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
6653                NoItinerary>;
6654
6655 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
6656   let Inst{20-16} = 0b00001;
6657   // bits 17-20 are unspecified, but should be set to zero.
6658 }
6659
6660 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
6661   let Inst{20-16} = 0b00010;
6662   // bits 18-20 are unspecified, but should be set to zero.
6663 }
6664
6665 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
6666   let Inst{20-16} = 0b00100;
6667   // bits 19-20 are unspecified, but should be set to zero.
6668 }
6669
6670 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
6671   let Inst{20-16} = 0b01000;
6672   // bit 20 is unspecified, but should be set to zero.
6673 }
6674
6675 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
6676   let Inst{20-16} = 0b00001;
6677   // bits 17-20 are unspecified, but should be set to zero.
6678 }
6679
6680 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
6681   let Inst{20-16} = 0b00010;
6682   // bits 18-20 are unspecified, but should be set to zero.
6683 }
6684
6685 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
6686   let Inst{20-16} = 0b00100;
6687   // bits 19-20 are unspecified, but should be set to zero.
6688 }
6689
6690 // patterns for CONCAT_VECTORS
6691 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
6692 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
6693           (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
6694 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
6695           (INSELd
6696             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6697             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
6698             (i64 1),
6699             (i64 0))>;
6700 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
6701           (DUPELT2d
6702             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6703             (i64 0))> ;
6704 }
6705
6706 defm : Concat_Vector_Pattern<v16i8, v8i8>;
6707 defm : Concat_Vector_Pattern<v8i16, v4i16>;
6708 defm : Concat_Vector_Pattern<v4i32, v2i32>;
6709 defm : Concat_Vector_Pattern<v2i64, v1i64>;
6710 defm : Concat_Vector_Pattern<v4f32, v2f32>;
6711 defm : Concat_Vector_Pattern<v2f64, v1f64>;
6712
6713 //patterns for EXTRACT_SUBVECTOR
6714 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
6715           (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6716 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
6717           (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6718 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
6719           (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6720 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
6721           (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6722 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
6723           (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6724 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
6725           (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6726
6727 // The followings are for instruction class (3V Elem)
6728
6729 // Variant 1
6730
6731 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
6732              string asmop, string ResS, string OpS, string EleOpS,
6733              Operand OpImm, RegisterOperand ResVPR,
6734              RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6735   : NeonI_2VElem<q, u, size, opcode,
6736                  (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
6737                                          EleOpVPR:$Re, OpImm:$Index),
6738                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6739                  ", $Re." # EleOpS # "[$Index]",
6740                  [],
6741                  NoItinerary> {
6742   bits<3> Index;
6743   bits<5> Re;
6744
6745   let Constraints = "$src = $Rd";
6746 }
6747
6748 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
6749   // vector register class for element is always 128-bit to cover the max index
6750   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6751                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
6752     let Inst{11} = {Index{1}};
6753     let Inst{21} = {Index{0}};
6754     let Inst{20-16} = Re;
6755   }
6756
6757   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6758                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
6759     let Inst{11} = {Index{1}};
6760     let Inst{21} = {Index{0}};
6761     let Inst{20-16} = Re;
6762   }
6763
6764   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6765   def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6766                      neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6767     let Inst{11} = {Index{2}};
6768     let Inst{21} = {Index{1}};
6769     let Inst{20} = {Index{0}};
6770     let Inst{19-16} = Re{3-0};
6771   }
6772
6773   def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6774                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6775     let Inst{11} = {Index{2}};
6776     let Inst{21} = {Index{1}};
6777     let Inst{20} = {Index{0}};
6778     let Inst{19-16} = Re{3-0};
6779   }
6780 }
6781
6782 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
6783 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
6784
6785 // Pattern for lane in 128-bit vector
6786 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6787                    RegisterOperand ResVPR, RegisterOperand OpVPR,
6788                    RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6789                    ValueType EleOpTy>
6790   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6791           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6792         (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6793
6794 // Pattern for lane in 64-bit vector
6795 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6796                   RegisterOperand ResVPR, RegisterOperand OpVPR,
6797                   RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6798                   ValueType EleOpTy>
6799   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6800           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6801         (INST ResVPR:$src, OpVPR:$Rn,
6802           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6803
6804 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
6805 {
6806   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6807                      op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
6808
6809   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6810                      op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
6811
6812   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6813                      op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
6814
6815   def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6816                      op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
6817
6818   // Index can only be half of the max value for lane in 64-bit vector
6819
6820   def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6821                     op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
6822
6823   def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6824                     op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
6825 }
6826
6827 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
6828 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
6829
6830 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
6831                  string asmop, string ResS, string OpS, string EleOpS,
6832                  Operand OpImm, RegisterOperand ResVPR,
6833                  RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6834   : NeonI_2VElem<q, u, size, opcode,
6835                  (outs ResVPR:$Rd), (ins OpVPR:$Rn,
6836                                          EleOpVPR:$Re, OpImm:$Index),
6837                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6838                  ", $Re." # EleOpS # "[$Index]",
6839                  [],
6840                  NoItinerary> {
6841   bits<3> Index;
6842   bits<5> Re;
6843 }
6844
6845 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
6846   // vector register class for element is always 128-bit to cover the max index
6847   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6848                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
6849     let Inst{11} = {Index{1}};
6850     let Inst{21} = {Index{0}};
6851     let Inst{20-16} = Re;
6852   }
6853
6854   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6855                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
6856     let Inst{11} = {Index{1}};
6857     let Inst{21} = {Index{0}};
6858     let Inst{20-16} = Re;
6859   }
6860
6861   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6862   def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6863                          neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6864     let Inst{11} = {Index{2}};
6865     let Inst{21} = {Index{1}};
6866     let Inst{20} = {Index{0}};
6867     let Inst{19-16} = Re{3-0};
6868   }
6869
6870   def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6871                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6872     let Inst{11} = {Index{2}};
6873     let Inst{21} = {Index{1}};
6874     let Inst{20} = {Index{0}};
6875     let Inst{19-16} = Re{3-0};
6876   }
6877 }
6878
6879 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
6880 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
6881 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
6882
6883 // Pattern for lane in 128-bit vector
6884 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6885                        RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6886                        ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
6887   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6888           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6889         (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6890
6891 // Pattern for lane in 64-bit vector
6892 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6893                       RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6894                       ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
6895   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6896           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6897         (INST OpVPR:$Rn,
6898           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6899
6900 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
6901   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6902                          op, VPR64, VPR128, v2i32, v2i32, v4i32>;
6903
6904   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6905                          op, VPR128, VPR128, v4i32, v4i32, v4i32>;
6906
6907   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6908                          op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
6909
6910   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6911                          op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
6912
6913   // Index can only be half of the max value for lane in 64-bit vector
6914
6915   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6916                         op, VPR64, VPR64, v2i32, v2i32, v2i32>;
6917
6918   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6919                         op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
6920 }
6921
6922 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
6923 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
6924 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
6925
6926 // Variant 2
6927
6928 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
6929   // vector register class for element is always 128-bit to cover the max index
6930   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6931                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
6932     let Inst{11} = {Index{1}};
6933     let Inst{21} = {Index{0}};
6934     let Inst{20-16} = Re;
6935   }
6936
6937   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6938                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
6939     let Inst{11} = {Index{1}};
6940     let Inst{21} = {Index{0}};
6941     let Inst{20-16} = Re;
6942   }
6943
6944   // _1d2d doesn't exist!
6945
6946   def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
6947                          neon_uimm1_bare, VPR128, VPR128, VPR128> {
6948     let Inst{11} = {Index{0}};
6949     let Inst{21} = 0b0;
6950     let Inst{20-16} = Re;
6951   }
6952 }
6953
6954 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
6955 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
6956
6957 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
6958                          RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6959                          ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
6960                          SDPatternOperator coreop>
6961   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6962           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
6963         (INST OpVPR:$Rn,
6964           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
6965
6966 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
6967   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6968                          op, VPR64, VPR128, v2f32, v2f32, v4f32>;
6969
6970   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6971                          op, VPR128, VPR128, v4f32, v4f32, v4f32>;
6972
6973   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
6974                          op, VPR128, VPR128, v2f64, v2f64, v2f64>;
6975
6976   // Index can only be half of the max value for lane in 64-bit vector
6977
6978   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6979                         op, VPR64, VPR64, v2f32, v2f32, v2f32>;
6980
6981   def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
6982                            op, VPR128, VPR64, v2f64, v2f64, v1f64,
6983                            BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
6984 }
6985
6986 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
6987 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
6988
6989 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
6990                        (v2f32 VPR64:$Rn))),
6991           (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
6992
6993 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
6994                        (v4f32 VPR128:$Rn))),
6995           (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
6996
6997 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
6998                        (v2f64 VPR128:$Rn))),
6999           (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7000
7001 // The followings are patterns using fma
7002 // -ffp-contract=fast generates fma
7003
7004 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7005   // vector register class for element is always 128-bit to cover the max index
7006   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7007                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
7008     let Inst{11} = {Index{1}};
7009     let Inst{21} = {Index{0}};
7010     let Inst{20-16} = Re;
7011   }
7012
7013   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7014                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7015     let Inst{11} = {Index{1}};
7016     let Inst{21} = {Index{0}};
7017     let Inst{20-16} = Re;
7018   }
7019
7020   // _1d2d doesn't exist!
7021
7022   def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7023                      neon_uimm1_bare, VPR128, VPR128, VPR128> {
7024     let Inst{11} = {Index{0}};
7025     let Inst{21} = 0b0;
7026     let Inst{20-16} = Re;
7027   }
7028 }
7029
7030 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7031 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7032
7033 // Pattern for lane in 128-bit vector
7034 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7035                        RegisterOperand ResVPR, RegisterOperand OpVPR,
7036                        ValueType ResTy, ValueType OpTy,
7037                        SDPatternOperator coreop>
7038   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7039                    (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
7040         (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7041
7042 // Pattern for lane 0
7043 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7044                       RegisterOperand ResVPR, ValueType ResTy>
7045   : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7046                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7047                    (ResTy ResVPR:$src))),
7048         (INST ResVPR:$src, ResVPR:$Rn,
7049               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7050
7051 // Pattern for lane in 64-bit vector
7052 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7053                       RegisterOperand ResVPR, RegisterOperand OpVPR,
7054                       ValueType ResTy, ValueType OpTy,
7055                       SDPatternOperator coreop>
7056   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7057                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7058         (INST ResVPR:$src, ResVPR:$Rn,
7059           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7060
7061 // Pattern for lane in 64-bit vector
7062 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7063                            SDPatternOperator op,
7064                            RegisterOperand ResVPR, RegisterOperand OpVPR,
7065                            ValueType ResTy, ValueType OpTy,
7066                            SDPatternOperator coreop>
7067   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7068                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7069         (INST ResVPR:$src, ResVPR:$Rn,
7070           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7071
7072
7073 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7074   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7075                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7076                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7077
7078   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7079                         op, VPR64, v2f32>;
7080
7081   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7082                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7083                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7084
7085   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7086                         op, VPR128, v4f32>;
7087
7088   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7089                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7090                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7091
7092   // Index can only be half of the max value for lane in 64-bit vector
7093
7094   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7095                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7096                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7097
7098   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7099                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7100                              BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7101 }
7102
7103 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7104
7105 // Pattern for lane 0
7106 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7107                       RegisterOperand ResVPR, ValueType ResTy>
7108   : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7109                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7110                    (ResTy ResVPR:$src))),
7111         (INST ResVPR:$src, ResVPR:$Rn,
7112               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7113
7114 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7115 {
7116   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7117                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7118                          BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7119
7120   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7121                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7122                          BinOpFrag<(Neon_vduplane
7123                                      (fneg node:$LHS), node:$RHS)>>;
7124
7125   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7126                         op, VPR64, v2f32>;
7127
7128   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7129                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7130                          BinOpFrag<(fneg (Neon_vduplane
7131                                      node:$LHS, node:$RHS))>>;
7132
7133   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7134                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7135                          BinOpFrag<(Neon_vduplane
7136                                      (fneg node:$LHS), node:$RHS)>>;
7137
7138   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7139                         op, VPR128, v4f32>;
7140
7141   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7142                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7143                          BinOpFrag<(fneg (Neon_vduplane
7144                                      node:$LHS, node:$RHS))>>;
7145
7146   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7147                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7148                          BinOpFrag<(Neon_vduplane
7149                                      (fneg node:$LHS), node:$RHS)>>;
7150
7151   // Index can only be half of the max value for lane in 64-bit vector
7152
7153   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7154                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7155                         BinOpFrag<(fneg (Neon_vduplane
7156                                     node:$LHS, node:$RHS))>>;
7157
7158   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7159                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7160                         BinOpFrag<(Neon_vduplane
7161                                     (fneg node:$LHS), node:$RHS)>>;
7162
7163   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7164                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7165                         BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7166
7167   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7168                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7169                         BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7170
7171   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7172                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7173                              BinOpFrag<(fneg (Neon_combine_2d
7174                                          node:$LHS, node:$RHS))>>;
7175
7176   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7177                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7178                              BinOpFrag<(Neon_combine_2d
7179                                          (fneg node:$LHS), (fneg node:$RHS))>>;
7180 }
7181
7182 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7183
7184 // Variant 3: Long type
7185 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7186 //      SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7187
7188 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7189   // vector register class for element is always 128-bit to cover the max index
7190   def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7191                      neon_uimm2_bare, VPR128, VPR64, VPR128> {
7192     let Inst{11} = {Index{1}};
7193     let Inst{21} = {Index{0}};
7194     let Inst{20-16} = Re;
7195   }
7196
7197   def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7198                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7199     let Inst{11} = {Index{1}};
7200     let Inst{21} = {Index{0}};
7201     let Inst{20-16} = Re;
7202   }
7203
7204   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7205   def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7206                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7207     let Inst{11} = {Index{2}};
7208     let Inst{21} = {Index{1}};
7209     let Inst{20} = {Index{0}};
7210     let Inst{19-16} = Re{3-0};
7211   }
7212
7213   def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7214                      neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7215     let Inst{11} = {Index{2}};
7216     let Inst{21} = {Index{1}};
7217     let Inst{20} = {Index{0}};
7218     let Inst{19-16} = Re{3-0};
7219   }
7220 }
7221
7222 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7223 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7224 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7225 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7226 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7227 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7228
7229 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7230   // vector register class for element is always 128-bit to cover the max index
7231   def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7232                          neon_uimm2_bare, VPR128, VPR64, VPR128> {
7233     let Inst{11} = {Index{1}};
7234     let Inst{21} = {Index{0}};
7235     let Inst{20-16} = Re;
7236   }
7237
7238   def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7239                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7240     let Inst{11} = {Index{1}};
7241     let Inst{21} = {Index{0}};
7242     let Inst{20-16} = Re;
7243   }
7244
7245   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7246   def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7247                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7248     let Inst{11} = {Index{2}};
7249     let Inst{21} = {Index{1}};
7250     let Inst{20} = {Index{0}};
7251     let Inst{19-16} = Re{3-0};
7252   }
7253
7254   def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7255                          neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7256     let Inst{11} = {Index{2}};
7257     let Inst{21} = {Index{1}};
7258     let Inst{20} = {Index{0}};
7259     let Inst{19-16} = Re{3-0};
7260   }
7261 }
7262
7263 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7264 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7265 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7266
7267 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7268           (FMOVdd $src)>;
7269 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$src))),
7270           (FMOVss $src)>;
7271
7272 // Pattern for lane in 128-bit vector
7273 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7274                      RegisterOperand EleOpVPR, ValueType ResTy,
7275                      ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7276                      SDPatternOperator hiop>
7277   : Pat<(ResTy (op (ResTy VPR128:$src),
7278           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7279           (HalfOpTy (Neon_vduplane
7280                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7281         (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7282
7283 // Pattern for lane in 64-bit vector
7284 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7285                     RegisterOperand EleOpVPR, ValueType ResTy,
7286                     ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7287                     SDPatternOperator hiop>
7288   : Pat<(ResTy (op (ResTy VPR128:$src),
7289           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7290           (HalfOpTy (Neon_vduplane
7291                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7292         (INST VPR128:$src, VPR128:$Rn,
7293           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7294
7295 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7296                      ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7297                      SDPatternOperator hiop, Instruction DupInst>
7298   : Pat<(ResTy (op (ResTy VPR128:$src),
7299           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7300           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7301         (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7302
7303 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7304   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7305                      op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7306
7307   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7308                      op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7309
7310   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7311                        op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7312
7313   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7314                        op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7315
7316   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7317                        op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7318
7319   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7320                        op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7321
7322   // Index can only be half of the max value for lane in 64-bit vector
7323
7324   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7325                     op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7326
7327   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7328                     op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7329
7330   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7331                       op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7332
7333   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7334                       op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7335 }
7336
7337 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7338 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7339 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7340 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7341
7342 // Pattern for lane in 128-bit vector
7343 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7344                          RegisterOperand EleOpVPR, ValueType ResTy,
7345                          ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7346                          SDPatternOperator hiop>
7347   : Pat<(ResTy (op
7348           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7349           (HalfOpTy (Neon_vduplane
7350                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7351         (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7352
7353 // Pattern for lane in 64-bit vector
7354 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7355                         RegisterOperand EleOpVPR, ValueType ResTy,
7356                         ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7357                         SDPatternOperator hiop>
7358   : Pat<(ResTy (op
7359           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7360           (HalfOpTy (Neon_vduplane
7361                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7362         (INST VPR128:$Rn,
7363           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7364
7365 // Pattern for fixed lane 0
7366 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7367                          ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7368                          SDPatternOperator hiop, Instruction DupInst>
7369   : Pat<(ResTy (op
7370           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7371           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7372         (INST VPR128:$Rn, (DupInst $Re), 0)>;
7373
7374 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7375   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7376                          op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7377
7378   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7379                          op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7380
7381   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7382                          op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7383
7384   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7385                            op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7386
7387   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7388                            op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7389
7390   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7391                            op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7392
7393   // Index can only be half of the max value for lane in 64-bit vector
7394
7395   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7396                         op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7397
7398   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7399                         op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7400
7401   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7402                           op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7403
7404   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7405                           op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7406 }
7407
7408 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7409 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7410 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7411
7412 multiclass NI_qdma<SDPatternOperator op> {
7413   def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7414                     (op node:$Ra,
7415                       (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7416
7417   def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7418                     (op node:$Ra,
7419                       (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7420 }
7421
7422 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7423 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7424
7425 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7426   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7427                      !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7428                      v4i32, v4i16, v8i16>;
7429
7430   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7431                      !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7432                      v2i64, v2i32, v4i32>;
7433
7434   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7435                        !cast<PatFrag>(op # "_4s"), VPR128Lo,
7436                        v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7437
7438   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7439                        !cast<PatFrag>(op # "_2d"), VPR128,
7440                        v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7441
7442   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7443                        !cast<PatFrag>(op # "_4s"),
7444                        v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7445
7446   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7447                        !cast<PatFrag>(op # "_2d"),
7448                        v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7449
7450   // Index can only be half of the max value for lane in 64-bit vector
7451
7452   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7453                     !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7454                     v4i32, v4i16, v4i16>;
7455
7456   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7457                     !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7458                     v2i64, v2i32, v2i32>;
7459
7460   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7461                       !cast<PatFrag>(op # "_4s"), VPR64Lo,
7462                       v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7463
7464   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7465                       !cast<PatFrag>(op # "_2d"), VPR64,
7466                       v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7467 }
7468
7469 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7470 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7471
7472 // End of implementation for instruction class (3V Elem)
7473
7474 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7475                 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7476                 SDPatternOperator Neon_Rev>
7477   : NeonI_2VMisc<Q, U, size, opcode,
7478                (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7479                asmop # "\t$Rd." # Res # ", $Rn." # Res,
7480                [(set (ResTy ResVPR:$Rd),
7481                   (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7482                NoItinerary> ;
7483
7484 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7485                           v16i8, Neon_rev64>;
7486 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7487                          v8i16, Neon_rev64>;
7488 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7489                          v4i32, Neon_rev64>;
7490 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7491                          v8i8, Neon_rev64>;
7492 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7493                          v4i16, Neon_rev64>;
7494 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7495                          v2i32, Neon_rev64>;
7496
7497 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7498 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7499
7500 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7501                           v16i8, Neon_rev32>;
7502 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7503                           v8i16, Neon_rev32>;
7504 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7505                          v8i8, Neon_rev32>;
7506 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7507                          v4i16, Neon_rev32>;
7508
7509 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7510                           v16i8, Neon_rev16>;
7511 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7512                          v8i8, Neon_rev16>;
7513
7514 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7515                              SDPatternOperator Neon_Padd> {
7516   def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7517                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7518                            asmop # "\t$Rd.8h, $Rn.16b",
7519                            [(set (v8i16 VPR128:$Rd),
7520                               (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7521                            NoItinerary>;
7522
7523   def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7524                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7525                           asmop # "\t$Rd.4h, $Rn.8b",
7526                           [(set (v4i16 VPR64:$Rd),
7527                              (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7528                           NoItinerary>;
7529
7530   def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7531                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7532                            asmop # "\t$Rd.4s, $Rn.8h",
7533                            [(set (v4i32 VPR128:$Rd),
7534                               (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7535                            NoItinerary>;
7536
7537   def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7538                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7539                           asmop # "\t$Rd.2s, $Rn.4h",
7540                           [(set (v2i32 VPR64:$Rd),
7541                              (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7542                           NoItinerary>;
7543
7544   def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7545                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7546                            asmop # "\t$Rd.2d, $Rn.4s",
7547                            [(set (v2i64 VPR128:$Rd),
7548                               (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7549                            NoItinerary>;
7550
7551   def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7552                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7553                           asmop # "\t$Rd.1d, $Rn.2s",
7554                           [(set (v1i64 VPR64:$Rd),
7555                              (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7556                           NoItinerary>;
7557 }
7558
7559 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7560                                 int_arm_neon_vpaddls>;
7561 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7562                                 int_arm_neon_vpaddlu>;
7563
7564 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7565                              SDPatternOperator Neon_Padd> {
7566   let Constraints = "$src = $Rd" in {
7567     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7568                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7569                              asmop # "\t$Rd.8h, $Rn.16b",
7570                              [(set (v8i16 VPR128:$Rd),
7571                                 (v8i16 (Neon_Padd
7572                                   (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7573                              NoItinerary>;
7574
7575     def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7576                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7577                             asmop # "\t$Rd.4h, $Rn.8b",
7578                             [(set (v4i16 VPR64:$Rd),
7579                                (v4i16 (Neon_Padd
7580                                  (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7581                             NoItinerary>;
7582
7583     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7584                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7585                             asmop # "\t$Rd.4s, $Rn.8h",
7586                             [(set (v4i32 VPR128:$Rd),
7587                                (v4i32 (Neon_Padd
7588                                  (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7589                             NoItinerary>;
7590
7591     def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7592                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7593                             asmop # "\t$Rd.2s, $Rn.4h",
7594                             [(set (v2i32 VPR64:$Rd),
7595                                (v2i32 (Neon_Padd
7596                                  (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7597                             NoItinerary>;
7598
7599     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7600                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7601                             asmop # "\t$Rd.2d, $Rn.4s",
7602                             [(set (v2i64 VPR128:$Rd),
7603                                (v2i64 (Neon_Padd
7604                                  (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7605                             NoItinerary>;
7606
7607     def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7608                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7609                             asmop # "\t$Rd.1d, $Rn.2s",
7610                             [(set (v1i64 VPR64:$Rd),
7611                                (v1i64 (Neon_Padd
7612                                  (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7613                             NoItinerary>;
7614   }
7615 }
7616
7617 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7618                                    int_arm_neon_vpadals>;
7619 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7620                                    int_arm_neon_vpadalu>;
7621
7622 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7623   def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7624                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7625                          asmop # "\t$Rd.16b, $Rn.16b",
7626                          [], NoItinerary>;
7627
7628   def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7629                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7630                         asmop # "\t$Rd.8h, $Rn.8h",
7631                         [], NoItinerary>;
7632
7633   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7634                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7635                         asmop # "\t$Rd.4s, $Rn.4s",
7636                         [], NoItinerary>;
7637
7638   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7639                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7640                         asmop # "\t$Rd.2d, $Rn.2d",
7641                         [], NoItinerary>;
7642
7643   def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7644                          (outs VPR64:$Rd), (ins VPR64:$Rn),
7645                          asmop # "\t$Rd.8b, $Rn.8b",
7646                          [], NoItinerary>;
7647
7648   def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7649                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7650                         asmop # "\t$Rd.4h, $Rn.4h",
7651                         [], NoItinerary>;
7652
7653   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7654                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7655                         asmop # "\t$Rd.2s, $Rn.2s",
7656                         [], NoItinerary>;
7657 }
7658
7659 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
7660 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
7661 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
7662 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
7663
7664 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
7665                                           SDPatternOperator Neon_Op> {
7666   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
7667             (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
7668
7669   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
7670             (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
7671
7672   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
7673             (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
7674
7675   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
7676             (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
7677
7678   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
7679             (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
7680
7681   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
7682             (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
7683
7684   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
7685             (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
7686 }
7687
7688 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
7689 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
7690 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
7691
7692 def : Pat<(v16i8 (sub
7693             (v16i8 Neon_AllZero),
7694             (v16i8 VPR128:$Rn))),
7695           (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
7696 def : Pat<(v8i8 (sub
7697             (v8i8 Neon_AllZero),
7698             (v8i8 VPR64:$Rn))),
7699           (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
7700 def : Pat<(v8i16 (sub
7701             (v8i16 (bitconvert (v16i8 Neon_AllZero))),
7702             (v8i16 VPR128:$Rn))),
7703           (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
7704 def : Pat<(v4i16 (sub
7705             (v4i16 (bitconvert (v8i8 Neon_AllZero))),
7706             (v4i16 VPR64:$Rn))),
7707           (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
7708 def : Pat<(v4i32 (sub
7709             (v4i32 (bitconvert (v16i8 Neon_AllZero))),
7710             (v4i32 VPR128:$Rn))),
7711           (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
7712 def : Pat<(v2i32 (sub
7713             (v2i32 (bitconvert (v8i8 Neon_AllZero))),
7714             (v2i32 VPR64:$Rn))),
7715           (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
7716 def : Pat<(v2i64 (sub
7717             (v2i64 (bitconvert (v16i8 Neon_AllZero))),
7718             (v2i64 VPR128:$Rn))),
7719           (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
7720
7721 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
7722   let Constraints = "$src = $Rd" in {
7723     def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7724                            (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7725                            asmop # "\t$Rd.16b, $Rn.16b",
7726                            [], NoItinerary>;
7727
7728     def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7729                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7730                           asmop # "\t$Rd.8h, $Rn.8h",
7731                           [], NoItinerary>;
7732
7733     def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7734                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7735                           asmop # "\t$Rd.4s, $Rn.4s",
7736                           [], NoItinerary>;
7737
7738     def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7739                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7740                           asmop # "\t$Rd.2d, $Rn.2d",
7741                           [], NoItinerary>;
7742
7743     def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7744                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7745                           asmop # "\t$Rd.8b, $Rn.8b",
7746                           [], NoItinerary>;
7747
7748     def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7749                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7750                           asmop # "\t$Rd.4h, $Rn.4h",
7751                           [], NoItinerary>;
7752
7753     def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7754                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7755                           asmop # "\t$Rd.2s, $Rn.2s",
7756                           [], NoItinerary>;
7757   }
7758 }
7759
7760 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
7761 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
7762
7763 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
7764                                            SDPatternOperator Neon_Op> {
7765   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
7766             (v16i8 (!cast<Instruction>(Prefix # 16b)
7767               (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
7768
7769   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
7770             (v8i16 (!cast<Instruction>(Prefix # 8h)
7771               (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
7772
7773   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
7774             (v4i32 (!cast<Instruction>(Prefix # 4s)
7775               (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
7776
7777   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
7778             (v2i64 (!cast<Instruction>(Prefix # 2d)
7779               (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
7780
7781   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
7782             (v8i8 (!cast<Instruction>(Prefix # 8b)
7783               (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
7784
7785   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
7786             (v4i16 (!cast<Instruction>(Prefix # 4h)
7787               (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
7788
7789   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
7790             (v2i32 (!cast<Instruction>(Prefix # 2s)
7791               (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
7792 }
7793
7794 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
7795 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
7796
7797 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
7798                           SDPatternOperator Neon_Op> {
7799   def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
7800                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7801                          asmop # "\t$Rd.16b, $Rn.16b",
7802                          [(set (v16i8 VPR128:$Rd),
7803                             (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
7804                          NoItinerary>;
7805
7806   def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
7807                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7808                         asmop # "\t$Rd.8h, $Rn.8h",
7809                         [(set (v8i16 VPR128:$Rd),
7810                            (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
7811                         NoItinerary>;
7812
7813   def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
7814                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7815                         asmop # "\t$Rd.4s, $Rn.4s",
7816                         [(set (v4i32 VPR128:$Rd),
7817                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
7818                         NoItinerary>;
7819
7820   def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
7821                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7822                         asmop # "\t$Rd.8b, $Rn.8b",
7823                         [(set (v8i8 VPR64:$Rd),
7824                            (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
7825                         NoItinerary>;
7826
7827   def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
7828                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7829                         asmop # "\t$Rd.4h, $Rn.4h",
7830                         [(set (v4i16 VPR64:$Rd),
7831                            (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
7832                         NoItinerary>;
7833
7834   def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
7835                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7836                         asmop # "\t$Rd.2s, $Rn.2s",
7837                         [(set (v2i32 VPR64:$Rd),
7838                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
7839                         NoItinerary>;
7840 }
7841
7842 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
7843 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
7844
7845 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
7846                               bits<5> Opcode> {
7847   def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
7848                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7849                          asmop # "\t$Rd.16b, $Rn.16b",
7850                          [], NoItinerary>;
7851
7852   def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
7853                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7854                         asmop # "\t$Rd.8b, $Rn.8b",
7855                         [], NoItinerary>;
7856 }
7857
7858 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
7859 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
7860 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
7861
7862 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
7863                     (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
7864 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
7865                     (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
7866
7867 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
7868           (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
7869 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
7870           (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
7871
7872 def : Pat<(v16i8 (xor
7873             (v16i8 VPR128:$Rn),
7874             (v16i8 Neon_AllOne))),
7875           (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
7876 def : Pat<(v8i8 (xor
7877             (v8i8 VPR64:$Rn),
7878             (v8i8 Neon_AllOne))),
7879           (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
7880 def : Pat<(v8i16 (xor
7881             (v8i16 VPR128:$Rn),
7882             (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
7883           (NOT16b VPR128:$Rn)>;
7884 def : Pat<(v4i16 (xor
7885             (v4i16 VPR64:$Rn),
7886             (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
7887           (NOT8b VPR64:$Rn)>;
7888 def : Pat<(v4i32 (xor
7889             (v4i32 VPR128:$Rn),
7890             (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
7891           (NOT16b VPR128:$Rn)>;
7892 def : Pat<(v2i32 (xor
7893             (v2i32 VPR64:$Rn),
7894             (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
7895           (NOT8b VPR64:$Rn)>;
7896 def : Pat<(v2i64 (xor
7897             (v2i64 VPR128:$Rn),
7898             (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
7899           (NOT16b VPR128:$Rn)>;
7900
7901 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
7902           (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
7903 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
7904           (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
7905
7906 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
7907                                 SDPatternOperator Neon_Op> {
7908   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7909                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7910                         asmop # "\t$Rd.4s, $Rn.4s",
7911                         [(set (v4f32 VPR128:$Rd),
7912                            (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
7913                         NoItinerary>;
7914
7915   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7916                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7917                         asmop # "\t$Rd.2d, $Rn.2d",
7918                         [(set (v2f64 VPR128:$Rd),
7919                            (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
7920                         NoItinerary>;
7921
7922   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7923                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7924                         asmop # "\t$Rd.2s, $Rn.2s",
7925                         [(set (v2f32 VPR64:$Rd),
7926                            (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
7927                         NoItinerary>;
7928 }
7929
7930 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
7931 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
7932
7933 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
7934   def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7935                           (outs VPR64:$Rd), (ins VPR128:$Rn),
7936                           asmop # "\t$Rd.8b, $Rn.8h",
7937                           [], NoItinerary>;
7938
7939   def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7940                           (outs VPR64:$Rd), (ins VPR128:$Rn),
7941                           asmop # "\t$Rd.4h, $Rn.4s",
7942                           [], NoItinerary>;
7943
7944   def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7945                           (outs VPR64:$Rd), (ins VPR128:$Rn),
7946                           asmop # "\t$Rd.2s, $Rn.2d",
7947                           [], NoItinerary>;
7948
7949   let Constraints = "$Rd = $src" in {
7950     def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7951                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7952                              asmop # "2\t$Rd.16b, $Rn.8h",
7953                              [], NoItinerary>;
7954
7955     def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7956                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7957                             asmop # "2\t$Rd.8h, $Rn.4s",
7958                             [], NoItinerary>;
7959
7960     def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7961                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7962                             asmop # "2\t$Rd.4s, $Rn.2d",
7963                             [], NoItinerary>;
7964   }
7965 }
7966
7967 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
7968 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
7969 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
7970 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
7971
7972 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
7973                                         SDPatternOperator Neon_Op> {
7974   def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
7975             (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
7976
7977   def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
7978             (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
7979
7980   def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
7981             (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
7982
7983   def : Pat<(v16i8 (concat_vectors
7984               (v8i8 VPR64:$src),
7985               (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
7986             (!cast<Instruction>(Prefix # 8h16b)
7987               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
7988               VPR128:$Rn)>;
7989
7990   def : Pat<(v8i16 (concat_vectors
7991               (v4i16 VPR64:$src),
7992               (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
7993             (!cast<Instruction>(Prefix # 4s8h)
7994               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
7995               VPR128:$Rn)>;
7996
7997   def : Pat<(v4i32 (concat_vectors
7998               (v2i32 VPR64:$src),
7999               (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8000             (!cast<Instruction>(Prefix # 2d4s)
8001               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8002               VPR128:$Rn)>;
8003 }
8004
8005 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8006 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8007 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8008 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8009
8010 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8011   let DecoderMethod = "DecodeSHLLInstruction" in {
8012     def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8013                             (outs VPR128:$Rd),
8014                             (ins VPR64:$Rn, uimm_exact8:$Imm),
8015                             asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8016                             [], NoItinerary>;
8017
8018     def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8019                             (outs VPR128:$Rd),
8020                             (ins VPR64:$Rn, uimm_exact16:$Imm),
8021                             asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8022                             [], NoItinerary>;
8023
8024     def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8025                             (outs VPR128:$Rd),
8026                             (ins VPR64:$Rn, uimm_exact32:$Imm),
8027                             asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8028                             [], NoItinerary>;
8029
8030     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8031                             (outs VPR128:$Rd),
8032                             (ins VPR128:$Rn, uimm_exact8:$Imm),
8033                             asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8034                             [], NoItinerary>;
8035
8036     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8037                             (outs VPR128:$Rd),
8038                             (ins VPR128:$Rn, uimm_exact16:$Imm),
8039                             asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8040                             [], NoItinerary>;
8041
8042     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8043                             (outs VPR128:$Rd),
8044                             (ins VPR128:$Rn, uimm_exact32:$Imm),
8045                             asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8046                             [], NoItinerary>;
8047   }
8048 }
8049
8050 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8051
8052 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8053                           SDPatternOperator ExtOp, Operand Neon_Imm,
8054                           string suffix>
8055   : Pat<(DesTy (shl
8056           (DesTy (ExtOp (OpTy VPR64:$Rn))),
8057             (DesTy (Neon_vdup
8058               (i32 Neon_Imm:$Imm))))),
8059         (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8060
8061 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8062                                SDPatternOperator ExtOp, Operand Neon_Imm,
8063                                string suffix, PatFrag GetHigh>
8064   : Pat<(DesTy (shl
8065           (DesTy (ExtOp
8066             (OpTy (GetHigh VPR128:$Rn)))),
8067               (DesTy (Neon_vdup
8068                 (i32 Neon_Imm:$Imm))))),
8069         (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8070
8071 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8072 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8073 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8074 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8075 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8076 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8077 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8078                                Neon_High16B>;
8079 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8080                                Neon_High16B>;
8081 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8082                                Neon_High8H>;
8083 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8084                                Neon_High8H>;
8085 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8086                                Neon_High4S>;
8087 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8088                                Neon_High4S>;
8089
8090 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8091   def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8092                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8093                           asmop # "\t$Rd.4h, $Rn.4s",
8094                           [], NoItinerary>;
8095
8096   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8097                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8098                           asmop # "\t$Rd.2s, $Rn.2d",
8099                           [], NoItinerary>;
8100
8101   let Constraints = "$src = $Rd" in {
8102     def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8103                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8104                             asmop # "2\t$Rd.8h, $Rn.4s",
8105                             [], NoItinerary>;
8106
8107     def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8108                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8109                             asmop # "2\t$Rd.4s, $Rn.2d",
8110                             [], NoItinerary>;
8111   }
8112 }
8113
8114 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8115
8116 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8117                                        SDPatternOperator f32_to_f16_Op,
8118                                        SDPatternOperator f64_to_f32_Op> {
8119
8120   def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8121               (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8122
8123   def : Pat<(v8i16 (concat_vectors
8124                 (v4i16 VPR64:$src),
8125                 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8126                   (!cast<Instruction>(prefix # "4s8h")
8127                     (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8128                     (v4f32 VPR128:$Rn))>;
8129
8130   def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8131             (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8132
8133   def : Pat<(v4f32 (concat_vectors
8134               (v2f32 VPR64:$src),
8135               (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8136                 (!cast<Instruction>(prefix # "2d4s")
8137                   (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8138                   (v2f64 VPR128:$Rn))>;
8139 }
8140
8141 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8142
8143 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8144                                  bits<5> opcode> {
8145   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8146                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8147                           asmop # "\t$Rd.2s, $Rn.2d",
8148                           [], NoItinerary>;
8149
8150   def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8151                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8152                           asmop # "2\t$Rd.4s, $Rn.2d",
8153                           [], NoItinerary> {
8154     let Constraints = "$src = $Rd";
8155   }
8156
8157   def : Pat<(v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))),
8158             (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8159
8160   def : Pat<(v4f32 (concat_vectors
8161               (v2f32 VPR64:$src),
8162               (v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))))),
8163             (!cast<Instruction>(prefix # "2d4s")
8164                (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8165                VPR128:$Rn)>;
8166 }
8167
8168 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8169
8170 def Neon_High4Float : PatFrag<(ops node:$in),
8171                               (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8172
8173 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8174   def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8175                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8176                           asmop # "\t$Rd.4s, $Rn.4h",
8177                           [], NoItinerary>;
8178
8179   def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8180                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8181                           asmop # "\t$Rd.2d, $Rn.2s",
8182                           [], NoItinerary>;
8183
8184   def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8185                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8186                           asmop # "2\t$Rd.4s, $Rn.8h",
8187                           [], NoItinerary>;
8188
8189   def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8190                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8191                           asmop # "2\t$Rd.2d, $Rn.4s",
8192                           [], NoItinerary>;
8193 }
8194
8195 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8196
8197 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8198   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8199             (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8200
8201   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8202               (v4i16 (Neon_High8H
8203                 (v8i16 VPR128:$Rn))))),
8204             (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8205
8206   def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8207             (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8208
8209   def : Pat<(v2f64 (fextend
8210               (v2f32 (Neon_High4Float
8211                 (v4f32 VPR128:$Rn))))),
8212             (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8213 }
8214
8215 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8216
8217 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8218                                 ValueType ResTy4s, ValueType OpTy4s,
8219                                 ValueType ResTy2d, ValueType OpTy2d,
8220                                 ValueType ResTy2s, ValueType OpTy2s,
8221                                 SDPatternOperator Neon_Op> {
8222
8223   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8224                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8225                         asmop # "\t$Rd.4s, $Rn.4s",
8226                         [(set (ResTy4s VPR128:$Rd),
8227                            (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8228                         NoItinerary>;
8229
8230   def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8231                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8232                         asmop # "\t$Rd.2d, $Rn.2d",
8233                         [(set (ResTy2d VPR128:$Rd),
8234                            (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8235                         NoItinerary>;
8236
8237   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8238                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8239                         asmop # "\t$Rd.2s, $Rn.2s",
8240                         [(set (ResTy2s VPR64:$Rd),
8241                            (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8242                         NoItinerary>;
8243 }
8244
8245 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8246                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8247   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8248                                 v2f64, v2i32, v2f32, Neon_Op>;
8249 }
8250
8251 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8252                                      int_aarch64_neon_fcvtns>;
8253 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8254                                      int_aarch64_neon_fcvtnu>;
8255 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8256                                      int_aarch64_neon_fcvtps>;
8257 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8258                                      int_aarch64_neon_fcvtpu>;
8259 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8260                                      int_aarch64_neon_fcvtms>;
8261 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8262                                      int_aarch64_neon_fcvtmu>;
8263 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8264 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8265 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8266                                      int_aarch64_neon_fcvtas>;
8267 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8268                                      int_aarch64_neon_fcvtau>;
8269
8270 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8271                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8272   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8273                                 v2i64, v2f32, v2i32, Neon_Op>;
8274 }
8275
8276 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8277 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8278
8279 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8280                                  bits<5> opcode, SDPatternOperator Neon_Op> {
8281   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8282                                 v2f64, v2f32, v2f32, Neon_Op>;
8283 }
8284
8285 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8286                                      int_aarch64_neon_frintn>;
8287 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8288 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8289 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8290 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8291 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8292 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8293 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8294                                     int_arm_neon_vrecpe>;
8295 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8296                                      int_arm_neon_vrsqrte>;
8297 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111,
8298                                    int_aarch64_neon_fsqrt>;
8299
8300 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8301                                bits<5> opcode, SDPatternOperator Neon_Op> {
8302   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8303                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8304                         asmop # "\t$Rd.4s, $Rn.4s",
8305                         [(set (v4i32 VPR128:$Rd),
8306                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8307                         NoItinerary>;
8308
8309   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8310                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8311                         asmop # "\t$Rd.2s, $Rn.2s",
8312                         [(set (v2i32 VPR64:$Rd),
8313                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8314                         NoItinerary>;
8315 }
8316
8317 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8318                                   int_arm_neon_vrecpe>;
8319 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8320                                    int_arm_neon_vrsqrte>;
8321
8322 // Crypto Class
8323 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8324                          string asmop, SDPatternOperator opnode>
8325   : NeonI_Crypto_AES<size, opcode,
8326                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8327                      asmop # "\t$Rd.16b, $Rn.16b",
8328                      [(set (v16i8 VPR128:$Rd),
8329                         (v16i8 (opnode (v16i8 VPR128:$src),
8330                                        (v16i8 VPR128:$Rn))))],
8331                      NoItinerary>{
8332   let Constraints = "$src = $Rd";
8333   let Predicates = [HasNEON, HasCrypto];
8334 }
8335
8336 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8337 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8338
8339 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8340                       string asmop, SDPatternOperator opnode>
8341   : NeonI_Crypto_AES<size, opcode,
8342                      (outs VPR128:$Rd), (ins VPR128:$Rn),
8343                      asmop # "\t$Rd.16b, $Rn.16b",
8344                      [(set (v16i8 VPR128:$Rd),
8345                         (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8346                      NoItinerary>;
8347
8348 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8349 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8350
8351 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8352                          string asmop, SDPatternOperator opnode>
8353   : NeonI_Crypto_SHA<size, opcode,
8354                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8355                      asmop # "\t$Rd.4s, $Rn.4s",
8356                      [(set (v4i32 VPR128:$Rd),
8357                         (v4i32 (opnode (v4i32 VPR128:$src),
8358                                        (v4i32 VPR128:$Rn))))],
8359                      NoItinerary> {
8360   let Constraints = "$src = $Rd";
8361   let Predicates = [HasNEON, HasCrypto];
8362 }
8363
8364 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8365                                  int_arm_neon_sha1su1>;
8366 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8367                                    int_arm_neon_sha256su0>;
8368
8369 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8370                          string asmop, SDPatternOperator opnode>
8371   : NeonI_Crypto_SHA<size, opcode,
8372                      (outs FPR32:$Rd), (ins FPR32:$Rn),
8373                      asmop # "\t$Rd, $Rn",
8374                      [(set (v1i32 FPR32:$Rd),
8375                         (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8376                      NoItinerary> {
8377   let Predicates = [HasNEON, HasCrypto];
8378 }
8379
8380 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8381
8382 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8383                            SDPatternOperator opnode>
8384   : NeonI_Crypto_3VSHA<size, opcode,
8385                        (outs VPR128:$Rd),
8386                        (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8387                        asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8388                        [(set (v4i32 VPR128:$Rd),
8389                           (v4i32 (opnode (v4i32 VPR128:$src),
8390                                          (v4i32 VPR128:$Rn),
8391                                          (v4i32 VPR128:$Rm))))],
8392                        NoItinerary> {
8393   let Constraints = "$src = $Rd";
8394   let Predicates = [HasNEON, HasCrypto];
8395 }
8396
8397 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8398                                    int_arm_neon_sha1su0>;
8399 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8400                                      int_arm_neon_sha256su1>;
8401
8402 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8403                            SDPatternOperator opnode>
8404   : NeonI_Crypto_3VSHA<size, opcode,
8405                        (outs FPR128:$Rd),
8406                        (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8407                        asmop # "\t$Rd, $Rn, $Rm.4s",
8408                        [(set (v4i32 FPR128:$Rd),
8409                           (v4i32 (opnode (v4i32 FPR128:$src),
8410                                          (v4i32 FPR128:$Rn),
8411                                          (v4i32 VPR128:$Rm))))],
8412                        NoItinerary> {
8413   let Constraints = "$src = $Rd";
8414   let Predicates = [HasNEON, HasCrypto];
8415 }
8416
8417 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8418                                    int_arm_neon_sha256h>;
8419 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8420                                     int_arm_neon_sha256h2>;
8421
8422 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8423                            SDPatternOperator opnode>
8424   : NeonI_Crypto_3VSHA<size, opcode,
8425                        (outs FPR128:$Rd),
8426                        (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8427                        asmop # "\t$Rd, $Rn, $Rm.4s",
8428                        [(set (v4i32 FPR128:$Rd),
8429                           (v4i32 (opnode (v4i32 FPR128:$src),
8430                                          (v1i32 FPR32:$Rn),
8431                                          (v4i32 VPR128:$Rm))))],
8432                        NoItinerary> {
8433   let Constraints = "$src = $Rd";
8434   let Predicates = [HasNEON, HasCrypto];
8435 }
8436
8437 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8438 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8439 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8440