1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
17 def Neon_bsl : SDNode<"AArch64ISD::NEON_BSL", SDTypeProfile<1, 3,
18 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
19 SDTCisSameAs<0, 3>]>>;
21 // (outs Result), (ins Imm, OpCmode)
22 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
24 def Neon_movi : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
26 def Neon_mvni : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
28 // (outs Result), (ins Imm)
29 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
30 [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
32 // (outs Result), (ins LHS, RHS, CondCode)
33 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
34 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
36 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
37 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
38 [SDTCisVec<0>, SDTCisVec<1>]>>;
40 // (outs Result), (ins LHS, RHS)
41 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
42 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
44 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
46 def Neon_sqrshlImm : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
47 def Neon_uqrshlImm : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
49 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
51 def Neon_uzp1 : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
52 def Neon_uzp2 : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
53 def Neon_zip1 : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
54 def Neon_zip2 : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
55 def Neon_trn1 : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
56 def Neon_trn2 : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
58 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
59 def Neon_rev64 : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
60 def Neon_rev32 : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
61 def Neon_rev16 : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
62 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
64 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
65 [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
66 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
67 [SDTCisVec<0>, SDTCisSameAs<0, 1>,
68 SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
70 //===----------------------------------------------------------------------===//
72 //===----------------------------------------------------------------------===//
74 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size, bits<5> opcode,
75 string asmop, SDPatternOperator opnode8B,
76 SDPatternOperator opnode16B,
78 let isCommutable = Commutable in {
79 def _8B : NeonI_3VSame<0b0, u, size, opcode,
80 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
81 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
82 [(set (v8i8 VPR64:$Rd),
83 (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
86 def _16B : NeonI_3VSame<0b1, u, size, opcode,
87 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
88 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
89 [(set (v16i8 VPR128:$Rd),
90 (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
96 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
97 string asmop, SDPatternOperator opnode,
99 let isCommutable = Commutable in {
100 def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
101 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
102 asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
103 [(set (v4i16 VPR64:$Rd),
104 (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
107 def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
108 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
109 asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
110 [(set (v8i16 VPR128:$Rd),
111 (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
114 def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
115 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
116 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
117 [(set (v2i32 VPR64:$Rd),
118 (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
121 def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
122 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
123 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
124 [(set (v4i32 VPR128:$Rd),
125 (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
129 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
130 string asmop, SDPatternOperator opnode,
132 : NeonI_3VSame_HS_sizes<u, opcode, asmop, opnode, Commutable> {
133 let isCommutable = Commutable in {
134 def _8B : NeonI_3VSame<0b0, u, 0b00, opcode,
135 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
136 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
137 [(set (v8i8 VPR64:$Rd),
138 (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
141 def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
142 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
143 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
144 [(set (v16i8 VPR128:$Rd),
145 (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
150 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
151 string asmop, SDPatternOperator opnode,
153 : NeonI_3VSame_BHS_sizes<u, opcode, asmop, opnode, Commutable> {
154 let isCommutable = Commutable in {
155 def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
156 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
157 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
158 [(set (v2i64 VPR128:$Rd),
159 (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
164 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
165 // but Result types can be integer or floating point types.
166 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
167 string asmop, SDPatternOperator opnode2S,
168 SDPatternOperator opnode4S,
169 SDPatternOperator opnode2D,
170 ValueType ResTy2S, ValueType ResTy4S,
171 ValueType ResTy2D, bit Commutable = 0> {
172 let isCommutable = Commutable in {
173 def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
174 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
175 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
176 [(set (ResTy2S VPR64:$Rd),
177 (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
180 def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
181 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
182 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
183 [(set (ResTy4S VPR128:$Rd),
184 (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
187 def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
188 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
189 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
190 [(set (ResTy2D VPR128:$Rd),
191 (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
196 //===----------------------------------------------------------------------===//
197 // Instruction Definitions
198 //===----------------------------------------------------------------------===//
200 // Vector Arithmetic Instructions
202 // Vector Add (Integer and Floating-Point)
204 defm ADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
205 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
206 v2f32, v4f32, v2f64, 1>;
208 // Vector Sub (Integer and Floating-Point)
210 defm SUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
211 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
212 v2f32, v4f32, v2f64, 0>;
214 // Vector Multiply (Integer and Floating-Point)
216 defm MULvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
217 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
218 v2f32, v4f32, v2f64, 1>;
220 // Vector Multiply (Polynomial)
222 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
223 int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
225 // Vector Multiply-accumulate and Multiply-subtract (Integer)
227 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
228 // two operands constraints.
229 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
230 RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
231 bits<5> opcode, SDPatternOperator opnode>
232 : NeonI_3VSame<q, u, size, opcode,
233 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
234 asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
235 [(set (OpTy VPRC:$Rd),
236 (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
238 let Constraints = "$src = $Rd";
241 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
242 (add node:$Ra, (mul node:$Rn, node:$Rm))>;
244 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
245 (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
248 def MLAvvv_8B: NeonI_3VSame_Constraint_impl<"mla", ".8b", VPR64, v8i8,
249 0b0, 0b0, 0b00, 0b10010, Neon_mla>;
250 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
251 0b1, 0b0, 0b00, 0b10010, Neon_mla>;
252 def MLAvvv_4H: NeonI_3VSame_Constraint_impl<"mla", ".4h", VPR64, v4i16,
253 0b0, 0b0, 0b01, 0b10010, Neon_mla>;
254 def MLAvvv_8H: NeonI_3VSame_Constraint_impl<"mla", ".8h", VPR128, v8i16,
255 0b1, 0b0, 0b01, 0b10010, Neon_mla>;
256 def MLAvvv_2S: NeonI_3VSame_Constraint_impl<"mla", ".2s", VPR64, v2i32,
257 0b0, 0b0, 0b10, 0b10010, Neon_mla>;
258 def MLAvvv_4S: NeonI_3VSame_Constraint_impl<"mla", ".4s", VPR128, v4i32,
259 0b1, 0b0, 0b10, 0b10010, Neon_mla>;
261 def MLSvvv_8B: NeonI_3VSame_Constraint_impl<"mls", ".8b", VPR64, v8i8,
262 0b0, 0b1, 0b00, 0b10010, Neon_mls>;
263 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
264 0b1, 0b1, 0b00, 0b10010, Neon_mls>;
265 def MLSvvv_4H: NeonI_3VSame_Constraint_impl<"mls", ".4h", VPR64, v4i16,
266 0b0, 0b1, 0b01, 0b10010, Neon_mls>;
267 def MLSvvv_8H: NeonI_3VSame_Constraint_impl<"mls", ".8h", VPR128, v8i16,
268 0b1, 0b1, 0b01, 0b10010, Neon_mls>;
269 def MLSvvv_2S: NeonI_3VSame_Constraint_impl<"mls", ".2s", VPR64, v2i32,
270 0b0, 0b1, 0b10, 0b10010, Neon_mls>;
271 def MLSvvv_4S: NeonI_3VSame_Constraint_impl<"mls", ".4s", VPR128, v4i32,
272 0b1, 0b1, 0b10, 0b10010, Neon_mls>;
274 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
276 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
277 (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
279 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
280 (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
282 let Predicates = [HasNEON, UseFusedMAC] in {
283 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s", VPR64, v2f32,
284 0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
285 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s", VPR128, v4f32,
286 0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
287 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d", VPR128, v2f64,
288 0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
290 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s", VPR64, v2f32,
291 0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
292 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s", VPR128, v4f32,
293 0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
294 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d", VPR128, v2f64,
295 0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
298 // We're also allowed to match the fma instruction regardless of compile
300 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
301 (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
302 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
303 (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
304 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
305 (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
307 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
308 (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
309 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
310 (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
311 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
312 (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
314 // Vector Divide (Floating-Point)
316 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
317 v2f32, v4f32, v2f64, 0>;
319 // Vector Bitwise Operations
321 // Vector Bitwise AND
323 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
325 // Vector Bitwise Exclusive OR
327 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
331 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
333 // ORR disassembled as MOV if Vn==Vm
335 // Vector Move - register
336 // Alias for ORR if Vn=Vm.
337 // FIXME: This is actually the preferred syntax but TableGen can't deal with
338 // custom printing of aliases.
339 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
340 (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
341 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
342 (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
344 // The MOVI instruction takes two immediate operands. The first is the
345 // immediate encoding, while the second is the cmode. A cmode of 14, or
346 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
347 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
348 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
350 def Neon_not8B : PatFrag<(ops node:$in),
351 (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
352 def Neon_not16B : PatFrag<(ops node:$in),
353 (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
355 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
356 (or node:$Rn, (Neon_not8B node:$Rm))>;
358 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
359 (or node:$Rn, (Neon_not16B node:$Rm))>;
361 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
362 (and node:$Rn, (Neon_not8B node:$Rm))>;
364 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
365 (and node:$Rn, (Neon_not16B node:$Rm))>;
368 // Vector Bitwise OR NOT - register
370 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
371 Neon_orn8B, Neon_orn16B, 0>;
373 // Vector Bitwise Bit Clear (AND NOT) - register
375 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
376 Neon_bic8B, Neon_bic16B, 0>;
378 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
379 SDPatternOperator opnode16B,
381 Instruction INST16B> {
382 def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
383 (INST8B VPR64:$Rn, VPR64:$Rm)>;
384 def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
385 (INST8B VPR64:$Rn, VPR64:$Rm)>;
386 def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
387 (INST8B VPR64:$Rn, VPR64:$Rm)>;
388 def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
389 (INST16B VPR128:$Rn, VPR128:$Rm)>;
390 def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
391 (INST16B VPR128:$Rn, VPR128:$Rm)>;
392 def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
393 (INST16B VPR128:$Rn, VPR128:$Rm)>;
396 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
397 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
398 defm : Neon_bitwise2V_patterns<or, or, ORRvvv_8B, ORRvvv_16B>;
399 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
400 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
401 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
403 // Vector Bitwise Select
404 def BSLvvv_8B : NeonI_3VSame_Constraint_impl<"bsl", ".8b", VPR64, v8i8,
405 0b0, 0b1, 0b01, 0b00011, Neon_bsl>;
407 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
408 0b1, 0b1, 0b01, 0b00011, Neon_bsl>;
410 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
412 Instruction INST16B> {
413 // Disassociate type from instruction definition
414 def : Pat<(v2i32 (opnode VPR64:$src,VPR64:$Rn, VPR64:$Rm)),
415 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
416 def : Pat<(v4i16 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
417 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
418 def : Pat<(v1i64 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
419 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
420 def : Pat<(v4i32 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
421 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
422 def : Pat<(v8i16 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
423 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
424 def : Pat<(v2i64 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
425 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
427 // Allow to match BSL instruction pattern with non-constant operand
428 def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
429 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
430 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
431 def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
432 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
433 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
434 def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
435 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
436 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
437 def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
438 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
439 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
440 def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
441 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
442 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
443 def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
444 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
445 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
446 def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
447 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
448 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
449 def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
450 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
451 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
453 // Allow to match llvm.arm.* intrinsics.
454 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
455 (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
456 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
457 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
458 (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
459 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
460 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
461 (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
462 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
463 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
464 (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
465 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
466 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
467 (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
468 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
469 def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
470 (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
471 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
472 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
473 (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
474 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
475 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
476 (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
477 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
478 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
479 (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
480 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
481 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
482 (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
483 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
484 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
485 (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
486 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
487 def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
488 (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
489 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
492 // Additional patterns for bitwise instruction BSL
493 defm: Neon_bitwise3V_patterns<Neon_bsl, BSLvvv_8B, BSLvvv_16B>;
495 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
496 (Neon_bsl node:$src, node:$Rn, node:$Rm),
497 [{ (void)N; return false; }]>;
499 // Vector Bitwise Insert if True
501 def BITvvv_8B : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64, v8i8,
502 0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
503 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
504 0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
506 // Vector Bitwise Insert if False
508 def BIFvvv_8B : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64, v8i8,
509 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
510 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
511 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
513 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
515 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
516 (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
517 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
518 (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
520 // Vector Absolute Difference and Accumulate (Unsigned)
521 def UABAvvv_8B : NeonI_3VSame_Constraint_impl<"uaba", ".8b", VPR64, v8i8,
522 0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
523 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
524 0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
525 def UABAvvv_4H : NeonI_3VSame_Constraint_impl<"uaba", ".4h", VPR64, v4i16,
526 0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
527 def UABAvvv_8H : NeonI_3VSame_Constraint_impl<"uaba", ".8h", VPR128, v8i16,
528 0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
529 def UABAvvv_2S : NeonI_3VSame_Constraint_impl<"uaba", ".2s", VPR64, v2i32,
530 0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
531 def UABAvvv_4S : NeonI_3VSame_Constraint_impl<"uaba", ".4s", VPR128, v4i32,
532 0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
534 // Vector Absolute Difference and Accumulate (Signed)
535 def SABAvvv_8B : NeonI_3VSame_Constraint_impl<"saba", ".8b", VPR64, v8i8,
536 0b0, 0b0, 0b00, 0b01111, Neon_saba>;
537 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
538 0b1, 0b0, 0b00, 0b01111, Neon_saba>;
539 def SABAvvv_4H : NeonI_3VSame_Constraint_impl<"saba", ".4h", VPR64, v4i16,
540 0b0, 0b0, 0b01, 0b01111, Neon_saba>;
541 def SABAvvv_8H : NeonI_3VSame_Constraint_impl<"saba", ".8h", VPR128, v8i16,
542 0b1, 0b0, 0b01, 0b01111, Neon_saba>;
543 def SABAvvv_2S : NeonI_3VSame_Constraint_impl<"saba", ".2s", VPR64, v2i32,
544 0b0, 0b0, 0b10, 0b01111, Neon_saba>;
545 def SABAvvv_4S : NeonI_3VSame_Constraint_impl<"saba", ".4s", VPR128, v4i32,
546 0b1, 0b0, 0b10, 0b01111, Neon_saba>;
549 // Vector Absolute Difference (Signed, Unsigned)
550 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
551 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
553 // Vector Absolute Difference (Floating Point)
554 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
555 int_arm_neon_vabds, int_arm_neon_vabds,
556 int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
558 // Vector Reciprocal Step (Floating Point)
559 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
560 int_arm_neon_vrecps, int_arm_neon_vrecps,
562 v2f32, v4f32, v2f64, 0>;
564 // Vector Reciprocal Square Root Step (Floating Point)
565 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
566 int_arm_neon_vrsqrts,
567 int_arm_neon_vrsqrts,
568 int_arm_neon_vrsqrts,
569 v2f32, v4f32, v2f64, 0>;
571 // Vector Comparisons
573 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
574 (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
575 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
576 (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
577 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
578 (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
579 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
580 (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
581 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
582 (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
584 // NeonI_compare_aliases class: swaps register operands to implement
585 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
586 class NeonI_compare_aliases<string asmop, string asmlane,
587 Instruction inst, RegisterOperand VPRC>
588 : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
590 (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
592 // Vector Comparisons (Integer)
594 // Vector Compare Mask Equal (Integer)
595 let isCommutable =1 in {
596 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
599 // Vector Compare Mask Higher or Same (Unsigned Integer)
600 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
602 // Vector Compare Mask Greater Than or Equal (Integer)
603 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
605 // Vector Compare Mask Higher (Unsigned Integer)
606 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
608 // Vector Compare Mask Greater Than (Integer)
609 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
611 // Vector Compare Mask Bitwise Test (Integer)
612 defm CMTSTvvv: NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
614 // Vector Compare Mask Less or Same (Unsigned Integer)
615 // CMLS is alias for CMHS with operands reversed.
616 def CMLSvvv_8B : NeonI_compare_aliases<"cmls", ".8b", CMHSvvv_8B, VPR64>;
617 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
618 def CMLSvvv_4H : NeonI_compare_aliases<"cmls", ".4h", CMHSvvv_4H, VPR64>;
619 def CMLSvvv_8H : NeonI_compare_aliases<"cmls", ".8h", CMHSvvv_8H, VPR128>;
620 def CMLSvvv_2S : NeonI_compare_aliases<"cmls", ".2s", CMHSvvv_2S, VPR64>;
621 def CMLSvvv_4S : NeonI_compare_aliases<"cmls", ".4s", CMHSvvv_4S, VPR128>;
622 def CMLSvvv_2D : NeonI_compare_aliases<"cmls", ".2d", CMHSvvv_2D, VPR128>;
624 // Vector Compare Mask Less Than or Equal (Integer)
625 // CMLE is alias for CMGE with operands reversed.
626 def CMLEvvv_8B : NeonI_compare_aliases<"cmle", ".8b", CMGEvvv_8B, VPR64>;
627 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
628 def CMLEvvv_4H : NeonI_compare_aliases<"cmle", ".4h", CMGEvvv_4H, VPR64>;
629 def CMLEvvv_8H : NeonI_compare_aliases<"cmle", ".8h", CMGEvvv_8H, VPR128>;
630 def CMLEvvv_2S : NeonI_compare_aliases<"cmle", ".2s", CMGEvvv_2S, VPR64>;
631 def CMLEvvv_4S : NeonI_compare_aliases<"cmle", ".4s", CMGEvvv_4S, VPR128>;
632 def CMLEvvv_2D : NeonI_compare_aliases<"cmle", ".2d", CMGEvvv_2D, VPR128>;
634 // Vector Compare Mask Lower (Unsigned Integer)
635 // CMLO is alias for CMHI with operands reversed.
636 def CMLOvvv_8B : NeonI_compare_aliases<"cmlo", ".8b", CMHIvvv_8B, VPR64>;
637 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
638 def CMLOvvv_4H : NeonI_compare_aliases<"cmlo", ".4h", CMHIvvv_4H, VPR64>;
639 def CMLOvvv_8H : NeonI_compare_aliases<"cmlo", ".8h", CMHIvvv_8H, VPR128>;
640 def CMLOvvv_2S : NeonI_compare_aliases<"cmlo", ".2s", CMHIvvv_2S, VPR64>;
641 def CMLOvvv_4S : NeonI_compare_aliases<"cmlo", ".4s", CMHIvvv_4S, VPR128>;
642 def CMLOvvv_2D : NeonI_compare_aliases<"cmlo", ".2d", CMHIvvv_2D, VPR128>;
644 // Vector Compare Mask Less Than (Integer)
645 // CMLT is alias for CMGT with operands reversed.
646 def CMLTvvv_8B : NeonI_compare_aliases<"cmlt", ".8b", CMGTvvv_8B, VPR64>;
647 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
648 def CMLTvvv_4H : NeonI_compare_aliases<"cmlt", ".4h", CMGTvvv_4H, VPR64>;
649 def CMLTvvv_8H : NeonI_compare_aliases<"cmlt", ".8h", CMGTvvv_8H, VPR128>;
650 def CMLTvvv_2S : NeonI_compare_aliases<"cmlt", ".2s", CMGTvvv_2S, VPR64>;
651 def CMLTvvv_4S : NeonI_compare_aliases<"cmlt", ".4s", CMGTvvv_4S, VPR128>;
652 def CMLTvvv_2D : NeonI_compare_aliases<"cmlt", ".2d", CMGTvvv_2D, VPR128>;
655 def neon_uimm0_asmoperand : AsmOperandClass
658 let PredicateMethod = "isUImm<0>";
659 let RenderMethod = "addImmOperands";
662 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
663 let ParserMatchClass = neon_uimm0_asmoperand;
664 let PrintMethod = "printNeonUImm0Operand";
668 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
670 def _8B : NeonI_2VMisc<0b0, u, 0b00, opcode,
671 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
672 asmop # "\t$Rd.8b, $Rn.8b, $Imm",
673 [(set (v8i8 VPR64:$Rd),
674 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
677 def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
678 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
679 asmop # "\t$Rd.16b, $Rn.16b, $Imm",
680 [(set (v16i8 VPR128:$Rd),
681 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
684 def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
685 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
686 asmop # "\t$Rd.4h, $Rn.4h, $Imm",
687 [(set (v4i16 VPR64:$Rd),
688 (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
691 def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
692 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
693 asmop # "\t$Rd.8h, $Rn.8h, $Imm",
694 [(set (v8i16 VPR128:$Rd),
695 (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
698 def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
699 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
700 asmop # "\t$Rd.2s, $Rn.2s, $Imm",
701 [(set (v2i32 VPR64:$Rd),
702 (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
705 def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
706 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
707 asmop # "\t$Rd.4s, $Rn.4s, $Imm",
708 [(set (v4i32 VPR128:$Rd),
709 (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
712 def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
713 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
714 asmop # "\t$Rd.2d, $Rn.2d, $Imm",
715 [(set (v2i64 VPR128:$Rd),
716 (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
720 // Vector Compare Mask Equal to Zero (Integer)
721 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
723 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
724 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
726 // Vector Compare Mask Greater Than Zero (Signed Integer)
727 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
729 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
730 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
732 // Vector Compare Mask Less Than Zero (Signed Integer)
733 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
735 // Vector Comparisons (Floating Point)
737 // Vector Compare Mask Equal (Floating Point)
738 let isCommutable =1 in {
739 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
740 Neon_cmeq, Neon_cmeq,
741 v2i32, v4i32, v2i64, 0>;
744 // Vector Compare Mask Greater Than Or Equal (Floating Point)
745 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
746 Neon_cmge, Neon_cmge,
747 v2i32, v4i32, v2i64, 0>;
749 // Vector Compare Mask Greater Than (Floating Point)
750 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
751 Neon_cmgt, Neon_cmgt,
752 v2i32, v4i32, v2i64, 0>;
754 // Vector Compare Mask Less Than Or Equal (Floating Point)
755 // FCMLE is alias for FCMGE with operands reversed.
756 def FCMLEvvv_2S : NeonI_compare_aliases<"fcmle", ".2s", FCMGEvvv_2S, VPR64>;
757 def FCMLEvvv_4S : NeonI_compare_aliases<"fcmle", ".4s", FCMGEvvv_4S, VPR128>;
758 def FCMLEvvv_2D : NeonI_compare_aliases<"fcmle", ".2d", FCMGEvvv_2D, VPR128>;
760 // Vector Compare Mask Less Than (Floating Point)
761 // FCMLT is alias for FCMGT with operands reversed.
762 def FCMLTvvv_2S : NeonI_compare_aliases<"fcmlt", ".2s", FCMGTvvv_2S, VPR64>;
763 def FCMLTvvv_4S : NeonI_compare_aliases<"fcmlt", ".4s", FCMGTvvv_4S, VPR128>;
764 def FCMLTvvv_2D : NeonI_compare_aliases<"fcmlt", ".2d", FCMGTvvv_2D, VPR128>;
767 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
768 string asmop, CondCode CC>
770 def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
771 (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
772 asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
773 [(set (v2i32 VPR64:$Rd),
774 (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpimm:$FPImm), CC)))],
777 def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
778 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
779 asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
780 [(set (v4i32 VPR128:$Rd),
781 (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
784 def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
785 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
786 asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
787 [(set (v2i64 VPR128:$Rd),
788 (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
792 // Vector Compare Mask Equal to Zero (Floating Point)
793 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
795 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
796 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
798 // Vector Compare Mask Greater Than Zero (Floating Point)
799 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
801 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
802 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
804 // Vector Compare Mask Less Than Zero (Floating Point)
805 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
807 // Vector Absolute Comparisons (Floating Point)
809 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
810 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
811 int_arm_neon_vacged, int_arm_neon_vacgeq,
812 int_aarch64_neon_vacgeq,
813 v2i32, v4i32, v2i64, 0>;
815 // Vector Absolute Compare Mask Greater Than (Floating Point)
816 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
817 int_arm_neon_vacgtd, int_arm_neon_vacgtq,
818 int_aarch64_neon_vacgtq,
819 v2i32, v4i32, v2i64, 0>;
821 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
822 // FACLE is alias for FACGE with operands reversed.
823 def FACLEvvv_2S : NeonI_compare_aliases<"facle", ".2s", FACGEvvv_2S, VPR64>;
824 def FACLEvvv_4S : NeonI_compare_aliases<"facle", ".4s", FACGEvvv_4S, VPR128>;
825 def FACLEvvv_2D : NeonI_compare_aliases<"facle", ".2d", FACGEvvv_2D, VPR128>;
827 // Vector Absolute Compare Mask Less Than (Floating Point)
828 // FACLT is alias for FACGT with operands reversed.
829 def FACLTvvv_2S : NeonI_compare_aliases<"faclt", ".2s", FACGTvvv_2S, VPR64>;
830 def FACLTvvv_4S : NeonI_compare_aliases<"faclt", ".4s", FACGTvvv_4S, VPR128>;
831 def FACLTvvv_2D : NeonI_compare_aliases<"faclt", ".2d", FACGTvvv_2D, VPR128>;
833 // Vector halving add (Integer Signed, Unsigned)
834 defm SHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
835 int_arm_neon_vhadds, 1>;
836 defm UHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
837 int_arm_neon_vhaddu, 1>;
839 // Vector halving sub (Integer Signed, Unsigned)
840 defm SHSUBvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
841 int_arm_neon_vhsubs, 0>;
842 defm UHSUBvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
843 int_arm_neon_vhsubu, 0>;
845 // Vector rouding halving add (Integer Signed, Unsigned)
846 defm SRHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
847 int_arm_neon_vrhadds, 1>;
848 defm URHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
849 int_arm_neon_vrhaddu, 1>;
851 // Vector Saturating add (Integer Signed, Unsigned)
852 defm SQADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
853 int_arm_neon_vqadds, 1>;
854 defm UQADDvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
855 int_arm_neon_vqaddu, 1>;
857 // Vector Saturating sub (Integer Signed, Unsigned)
858 defm SQSUBvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
859 int_arm_neon_vqsubs, 1>;
860 defm UQSUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
861 int_arm_neon_vqsubu, 1>;
863 // Vector Shift Left (Signed and Unsigned Integer)
864 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
865 int_arm_neon_vshifts, 1>;
866 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
867 int_arm_neon_vshiftu, 1>;
869 // Vector Saturating Shift Left (Signed and Unsigned Integer)
870 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
871 int_arm_neon_vqshifts, 1>;
872 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
873 int_arm_neon_vqshiftu, 1>;
875 // Vector Rouding Shift Left (Signed and Unsigned Integer)
876 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
877 int_arm_neon_vrshifts, 1>;
878 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
879 int_arm_neon_vrshiftu, 1>;
881 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
882 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
883 int_arm_neon_vqrshifts, 1>;
884 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
885 int_arm_neon_vqrshiftu, 1>;
887 // Vector Maximum (Signed and Unsigned Integer)
888 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
889 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
891 // Vector Minimum (Signed and Unsigned Integer)
892 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
893 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
895 // Vector Maximum (Floating Point)
896 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
897 int_arm_neon_vmaxs, int_arm_neon_vmaxs,
898 int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
900 // Vector Minimum (Floating Point)
901 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
902 int_arm_neon_vmins, int_arm_neon_vmins,
903 int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
905 // Vector maxNum (Floating Point) - prefer a number over a quiet NaN)
906 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
907 int_aarch64_neon_vmaxnm,
908 int_aarch64_neon_vmaxnm,
909 int_aarch64_neon_vmaxnm,
910 v2f32, v4f32, v2f64, 1>;
912 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
913 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
914 int_aarch64_neon_vminnm,
915 int_aarch64_neon_vminnm,
916 int_aarch64_neon_vminnm,
917 v2f32, v4f32, v2f64, 1>;
919 // Vector Maximum Pairwise (Signed and Unsigned Integer)
920 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
921 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
923 // Vector Minimum Pairwise (Signed and Unsigned Integer)
924 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
925 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
927 // Vector Maximum Pairwise (Floating Point)
928 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
929 int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
930 int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
932 // Vector Minimum Pairwise (Floating Point)
933 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
934 int_arm_neon_vpmins, int_arm_neon_vpmins,
935 int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
937 // Vector maxNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
938 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
939 int_aarch64_neon_vpmaxnm,
940 int_aarch64_neon_vpmaxnm,
941 int_aarch64_neon_vpmaxnm,
942 v2f32, v4f32, v2f64, 1>;
944 // Vector minNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
945 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
946 int_aarch64_neon_vpminnm,
947 int_aarch64_neon_vpminnm,
948 int_aarch64_neon_vpminnm,
949 v2f32, v4f32, v2f64, 1>;
951 // Vector Addition Pairwise (Integer)
952 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
954 // Vector Addition Pairwise (Floating Point)
955 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
959 v2f32, v4f32, v2f64, 1>;
961 // Vector Saturating Doubling Multiply High
962 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
963 int_arm_neon_vqdmulh, 1>;
965 // Vector Saturating Rouding Doubling Multiply High
966 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
967 int_arm_neon_vqrdmulh, 1>;
969 // Vector Multiply Extended (Floating Point)
970 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
971 int_aarch64_neon_vmulx,
972 int_aarch64_neon_vmulx,
973 int_aarch64_neon_vmulx,
974 v2f32, v4f32, v2f64, 1>;
976 // Vector Immediate Instructions
978 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
980 def _asmoperand : AsmOperandClass
982 let Name = "NeonMovImmShift" # PREFIX;
983 let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
984 let PredicateMethod = "isNeonMovImmShift" # PREFIX;
988 // Definition of vector immediates shift operands
990 // The selectable use-cases extract the shift operation
991 // information from the OpCmode fields encoded in the immediate.
992 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
993 uint64_t OpCmode = N->getZExtValue();
995 unsigned ShiftOnesIn;
997 A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
998 if (!HasShift) return SDValue();
999 return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1002 // Vector immediates shift operands which accept LSL and MSL
1003 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1004 // or 0, 8 (LSLH) or 8, 16 (MSL).
1005 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1006 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1007 // LSLH restricts shift amount to 0, 8 out of 0, 8, 16, 24
1008 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1010 multiclass neon_mov_imm_shift_operands<string PREFIX,
1011 string HALF, string ISHALF, code pred>
1013 def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1016 "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1018 "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1019 let ParserMatchClass =
1020 !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1024 defm neon_mov_imm_LSL : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1026 unsigned ShiftOnesIn;
1028 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1029 return (HasShift && !ShiftOnesIn);
1032 defm neon_mov_imm_MSL : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1034 unsigned ShiftOnesIn;
1036 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1037 return (HasShift && ShiftOnesIn);
1040 defm neon_mov_imm_LSLH : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1042 unsigned ShiftOnesIn;
1044 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1045 return (HasShift && !ShiftOnesIn);
1048 def neon_uimm1_asmoperand : AsmOperandClass
1051 let PredicateMethod = "isUImm<1>";
1052 let RenderMethod = "addImmOperands";
1055 def neon_uimm2_asmoperand : AsmOperandClass
1058 let PredicateMethod = "isUImm<2>";
1059 let RenderMethod = "addImmOperands";
1062 def neon_uimm8_asmoperand : AsmOperandClass
1065 let PredicateMethod = "isUImm<8>";
1066 let RenderMethod = "addImmOperands";
1069 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1070 let ParserMatchClass = neon_uimm8_asmoperand;
1071 let PrintMethod = "printUImmHexOperand";
1074 def neon_uimm64_mask_asmoperand : AsmOperandClass
1076 let Name = "NeonUImm64Mask";
1077 let PredicateMethod = "isNeonUImm64Mask";
1078 let RenderMethod = "addNeonUImm64MaskOperands";
1081 // MCOperand for 64-bit bytemask with each byte having only the
1082 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1083 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1084 let ParserMatchClass = neon_uimm64_mask_asmoperand;
1085 let PrintMethod = "printNeonUImm64MaskOperand";
1088 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1089 SDPatternOperator opnode>
1091 // shift zeros, per word
1092 def _2S : NeonI_1VModImm<0b0, op,
1094 (ins neon_uimm8:$Imm,
1095 neon_mov_imm_LSL_operand:$Simm),
1096 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1097 [(set (v2i32 VPR64:$Rd),
1098 (v2i32 (opnode (timm:$Imm),
1099 (neon_mov_imm_LSL_operand:$Simm))))],
1102 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1105 def _4S : NeonI_1VModImm<0b1, op,
1107 (ins neon_uimm8:$Imm,
1108 neon_mov_imm_LSL_operand:$Simm),
1109 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1110 [(set (v4i32 VPR128:$Rd),
1111 (v4i32 (opnode (timm:$Imm),
1112 (neon_mov_imm_LSL_operand:$Simm))))],
1115 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1118 // shift zeros, per halfword
1119 def _4H : NeonI_1VModImm<0b0, op,
1121 (ins neon_uimm8:$Imm,
1122 neon_mov_imm_LSLH_operand:$Simm),
1123 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1124 [(set (v4i16 VPR64:$Rd),
1125 (v4i16 (opnode (timm:$Imm),
1126 (neon_mov_imm_LSLH_operand:$Simm))))],
1129 let cmode = {0b1, 0b0, Simm, 0b0};
1132 def _8H : NeonI_1VModImm<0b1, op,
1134 (ins neon_uimm8:$Imm,
1135 neon_mov_imm_LSLH_operand:$Simm),
1136 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1137 [(set (v8i16 VPR128:$Rd),
1138 (v8i16 (opnode (timm:$Imm),
1139 (neon_mov_imm_LSLH_operand:$Simm))))],
1142 let cmode = {0b1, 0b0, Simm, 0b0};
1146 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1147 SDPatternOperator opnode,
1148 SDPatternOperator neonopnode>
1150 let Constraints = "$src = $Rd" in {
1151 // shift zeros, per word
1152 def _2S : NeonI_1VModImm<0b0, op,
1154 (ins VPR64:$src, neon_uimm8:$Imm,
1155 neon_mov_imm_LSL_operand:$Simm),
1156 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1157 [(set (v2i32 VPR64:$Rd),
1158 (v2i32 (opnode (v2i32 VPR64:$src),
1159 (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1160 neon_mov_imm_LSL_operand:$Simm)))))))],
1163 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1166 def _4S : NeonI_1VModImm<0b1, op,
1168 (ins VPR128:$src, neon_uimm8:$Imm,
1169 neon_mov_imm_LSL_operand:$Simm),
1170 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1171 [(set (v4i32 VPR128:$Rd),
1172 (v4i32 (opnode (v4i32 VPR128:$src),
1173 (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1174 neon_mov_imm_LSL_operand:$Simm)))))))],
1177 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1180 // shift zeros, per halfword
1181 def _4H : NeonI_1VModImm<0b0, op,
1183 (ins VPR64:$src, neon_uimm8:$Imm,
1184 neon_mov_imm_LSLH_operand:$Simm),
1185 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1186 [(set (v4i16 VPR64:$Rd),
1187 (v4i16 (opnode (v4i16 VPR64:$src),
1188 (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1189 neon_mov_imm_LSL_operand:$Simm)))))))],
1192 let cmode = {0b1, 0b0, Simm, 0b1};
1195 def _8H : NeonI_1VModImm<0b1, op,
1197 (ins VPR128:$src, neon_uimm8:$Imm,
1198 neon_mov_imm_LSLH_operand:$Simm),
1199 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1200 [(set (v8i16 VPR128:$Rd),
1201 (v8i16 (opnode (v8i16 VPR128:$src),
1202 (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1203 neon_mov_imm_LSL_operand:$Simm)))))))],
1206 let cmode = {0b1, 0b0, Simm, 0b1};
1211 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1212 SDPatternOperator opnode>
1214 // shift ones, per word
1215 def _2S : NeonI_1VModImm<0b0, op,
1217 (ins neon_uimm8:$Imm,
1218 neon_mov_imm_MSL_operand:$Simm),
1219 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1220 [(set (v2i32 VPR64:$Rd),
1221 (v2i32 (opnode (timm:$Imm),
1222 (neon_mov_imm_MSL_operand:$Simm))))],
1225 let cmode = {0b1, 0b1, 0b0, Simm};
1228 def _4S : NeonI_1VModImm<0b1, op,
1230 (ins neon_uimm8:$Imm,
1231 neon_mov_imm_MSL_operand:$Simm),
1232 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1233 [(set (v4i32 VPR128:$Rd),
1234 (v4i32 (opnode (timm:$Imm),
1235 (neon_mov_imm_MSL_operand:$Simm))))],
1238 let cmode = {0b1, 0b1, 0b0, Simm};
1242 // Vector Move Immediate Shifted
1243 let isReMaterializable = 1 in {
1244 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1247 // Vector Move Inverted Immediate Shifted
1248 let isReMaterializable = 1 in {
1249 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1252 // Vector Bitwise Bit Clear (AND NOT) - immediate
1253 let isReMaterializable = 1 in {
1254 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1258 // Vector Bitwise OR - immedidate
1260 let isReMaterializable = 1 in {
1261 defm ORRvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1265 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1266 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1267 // BIC immediate instructions selection requires additional patterns to
1268 // transform Neon_movi operands into BIC immediate operands
1270 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1271 uint64_t OpCmode = N->getZExtValue();
1273 unsigned ShiftOnesIn;
1274 (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1275 // LSLH restricts shift amount to 0, 8 which are encoded as 0 and 1
1276 // Transform encoded shift amount 0 to 1 and 1 to 0.
1277 return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1280 def neon_mov_imm_LSLH_transform_operand
1283 unsigned ShiftOnesIn;
1285 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1286 return (HasShift && !ShiftOnesIn); }],
1287 neon_mov_imm_LSLH_transform_XFORM>;
1289 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1290 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1291 def : Pat<(v4i16 (and VPR64:$src,
1292 (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1293 (BICvi_lsl_4H VPR64:$src, 0,
1294 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1296 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1297 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1298 def : Pat<(v8i16 (and VPR128:$src,
1299 (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1300 (BICvi_lsl_8H VPR128:$src, 0,
1301 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1304 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1305 SDPatternOperator neonopnode,
1307 Instruction INST8H> {
1308 def : Pat<(v8i8 (opnode VPR64:$src,
1309 (bitconvert(v4i16 (neonopnode timm:$Imm,
1310 neon_mov_imm_LSLH_operand:$Simm))))),
1311 (INST4H VPR64:$src, neon_uimm8:$Imm,
1312 neon_mov_imm_LSLH_operand:$Simm)>;
1313 def : Pat<(v1i64 (opnode VPR64:$src,
1314 (bitconvert(v4i16 (neonopnode timm:$Imm,
1315 neon_mov_imm_LSLH_operand:$Simm))))),
1316 (INST4H VPR64:$src, neon_uimm8:$Imm,
1317 neon_mov_imm_LSLH_operand:$Simm)>;
1319 def : Pat<(v16i8 (opnode VPR128:$src,
1320 (bitconvert(v8i16 (neonopnode timm:$Imm,
1321 neon_mov_imm_LSLH_operand:$Simm))))),
1322 (INST8H VPR128:$src, neon_uimm8:$Imm,
1323 neon_mov_imm_LSLH_operand:$Simm)>;
1324 def : Pat<(v4i32 (opnode VPR128:$src,
1325 (bitconvert(v8i16 (neonopnode timm:$Imm,
1326 neon_mov_imm_LSLH_operand:$Simm))))),
1327 (INST8H VPR128:$src, neon_uimm8:$Imm,
1328 neon_mov_imm_LSLH_operand:$Simm)>;
1329 def : Pat<(v2i64 (opnode VPR128:$src,
1330 (bitconvert(v8i16 (neonopnode timm:$Imm,
1331 neon_mov_imm_LSLH_operand:$Simm))))),
1332 (INST8H VPR128:$src, neon_uimm8:$Imm,
1333 neon_mov_imm_LSLH_operand:$Simm)>;
1336 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1337 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1339 // Additional patterns for Vector Bitwise OR - immedidate
1340 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1343 // Vector Move Immediate Masked
1344 let isReMaterializable = 1 in {
1345 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1348 // Vector Move Inverted Immediate Masked
1349 let isReMaterializable = 1 in {
1350 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1353 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1354 Instruction inst, RegisterOperand VPRC>
1355 : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1356 (inst VPRC:$Rd, neon_uimm8:$Imm, 0), 0b0>;
1358 // Aliases for Vector Move Immediate Shifted
1359 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1360 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1361 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1362 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1364 // Aliases for Vector Move Inverted Immediate Shifted
1365 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1366 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1367 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1368 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1370 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1371 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1372 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1373 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1374 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1376 // Aliases for Vector Bitwise OR - immedidate
1377 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1378 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1379 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1380 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1382 // Vector Move Immediate - per byte
1383 let isReMaterializable = 1 in {
1384 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1385 (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1386 "movi\t$Rd.8b, $Imm",
1387 [(set (v8i8 VPR64:$Rd),
1388 (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1393 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1394 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1395 "movi\t$Rd.16b, $Imm",
1396 [(set (v16i8 VPR128:$Rd),
1397 (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1403 // Vector Move Immediate - bytemask, per double word
1404 let isReMaterializable = 1 in {
1405 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1406 (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1407 "movi\t $Rd.2d, $Imm",
1408 [(set (v2i64 VPR128:$Rd),
1409 (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1415 // Vector Move Immediate - bytemask, one doubleword
1417 let isReMaterializable = 1 in {
1418 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1419 (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1421 [(set (f64 FPR64:$Rd),
1423 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))))],
1429 // Vector Floating Point Move Immediate
1431 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1432 Operand immOpType, bit q, bit op>
1433 : NeonI_1VModImm<q, op,
1434 (outs VPRC:$Rd), (ins immOpType:$Imm),
1435 "fmov\t$Rd" # asmlane # ", $Imm",
1436 [(set (OpTy VPRC:$Rd),
1437 (OpTy (Neon_fmovi (timm:$Imm))))],
1442 let isReMaterializable = 1 in {
1443 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64, v2f32, fmov32_operand, 0b0, 0b0>;
1444 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1445 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1448 // Vector Shift (Immediate)
1449 // Immediate in [0, 63]
1450 def imm0_63 : Operand<i32> {
1451 let ParserMatchClass = uimm6_asmoperand;
1454 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1458 // 8 immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1459 // 16 immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1460 // 32 immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1461 // 64 immh:immb<6> = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1463 // The shift right immediate amount, in the range 1 to element bits, is computed
1464 // as Offset - UInt(immh:immb). The shift left immediate amount, in the range 0
1465 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1467 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1468 let Name = "ShrImm" # OFFSET;
1469 let RenderMethod = "addImmOperands";
1470 let DiagnosticType = "ShrImm" # OFFSET;
1473 class shr_imm<string OFFSET> : Operand<i32> {
1474 let EncoderMethod = "getShiftRightImm" # OFFSET;
1475 let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1476 let ParserMatchClass =
1477 !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1480 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1481 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1482 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1483 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1485 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1486 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1487 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1488 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1490 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1491 let Name = "ShlImm" # OFFSET;
1492 let RenderMethod = "addImmOperands";
1493 let DiagnosticType = "ShlImm" # OFFSET;
1496 class shl_imm<string OFFSET> : Operand<i32> {
1497 let EncoderMethod = "getShiftLeftImm" # OFFSET;
1498 let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1499 let ParserMatchClass =
1500 !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1503 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1504 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1505 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1506 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1508 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1509 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1510 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1511 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1513 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1514 RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1515 : NeonI_2VShiftImm<q, u, opcode,
1516 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1517 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1518 [(set (Ty VPRC:$Rd),
1519 (Ty (OpNode (Ty VPRC:$Rn),
1520 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1523 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1524 // 64-bit vector types.
1525 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1526 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1529 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1530 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1533 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1534 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1537 // 128-bit vector types.
1538 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1539 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1542 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1543 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1546 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1547 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1550 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1551 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
1555 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1556 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1558 let Inst{22-19} = 0b0001;
1561 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1563 let Inst{22-20} = 0b001;
1566 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1568 let Inst{22-21} = 0b01;
1571 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1573 let Inst{22-19} = 0b0001;
1576 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1578 let Inst{22-20} = 0b001;
1581 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1583 let Inst{22-21} = 0b01;
1586 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1593 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1596 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1597 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1599 def Neon_High16B : PatFrag<(ops node:$in),
1600 (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1601 def Neon_High8H : PatFrag<(ops node:$in),
1602 (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1603 def Neon_High4S : PatFrag<(ops node:$in),
1604 (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1605 def Neon_High2D : PatFrag<(ops node:$in),
1606 (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1607 def Neon_High4float : PatFrag<(ops node:$in),
1608 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1609 def Neon_High2double : PatFrag<(ops node:$in),
1610 (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1612 def Neon_Low16B : PatFrag<(ops node:$in),
1613 (v8i8 (extract_subvector (v16i8 node:$in),
1615 def Neon_Low8H : PatFrag<(ops node:$in),
1616 (v4i16 (extract_subvector (v8i16 node:$in),
1618 def Neon_Low4S : PatFrag<(ops node:$in),
1619 (v2i32 (extract_subvector (v4i32 node:$in),
1621 def Neon_Low2D : PatFrag<(ops node:$in),
1622 (v1i64 (extract_subvector (v2i64 node:$in),
1624 def Neon_Low4float : PatFrag<(ops node:$in),
1625 (v2f32 (extract_subvector (v4f32 node:$in),
1627 def Neon_Low2double : PatFrag<(ops node:$in),
1628 (v1f64 (extract_subvector (v2f64 node:$in),
1631 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1632 string SrcT, ValueType DestTy, ValueType SrcTy,
1633 Operand ImmTy, SDPatternOperator ExtOp>
1634 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1635 (ins VPR64:$Rn, ImmTy:$Imm),
1636 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1637 [(set (DestTy VPR128:$Rd),
1639 (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1640 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1643 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1644 string SrcT, ValueType DestTy, ValueType SrcTy,
1645 int StartIndex, Operand ImmTy,
1646 SDPatternOperator ExtOp, PatFrag getTop>
1647 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1648 (ins VPR128:$Rn, ImmTy:$Imm),
1649 asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1650 [(set (DestTy VPR128:$Rd),
1653 (SrcTy (getTop VPR128:$Rn)))),
1654 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1657 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1659 // 64-bit vector types.
1660 def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1662 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1665 def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1667 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1670 def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1672 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1675 // 128-bit vector types
1676 def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1677 8, shl_imm8, ExtOp, Neon_High16B> {
1678 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1681 def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1682 4, shl_imm16, ExtOp, Neon_High8H> {
1683 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1686 def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1687 2, shl_imm32, ExtOp, Neon_High4S> {
1688 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1691 // Use other patterns to match when the immediate is 0.
1692 def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1693 (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1695 def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1696 (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1698 def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1699 (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1701 def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1702 (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1704 def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1705 (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1707 def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1708 (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1712 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1713 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1715 // Rounding/Saturating shift
1716 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1717 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1718 SDPatternOperator OpNode>
1719 : NeonI_2VShiftImm<q, u, opcode,
1720 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1721 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1722 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1723 (i32 ImmTy:$Imm))))],
1726 // shift right (vector by immediate)
1727 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1728 SDPatternOperator OpNode> {
1729 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1731 let Inst{22-19} = 0b0001;
1734 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1736 let Inst{22-20} = 0b001;
1739 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1741 let Inst{22-21} = 0b01;
1744 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1746 let Inst{22-19} = 0b0001;
1749 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1751 let Inst{22-20} = 0b001;
1754 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1756 let Inst{22-21} = 0b01;
1759 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1765 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1766 SDPatternOperator OpNode> {
1767 // 64-bit vector types.
1768 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1770 let Inst{22-19} = 0b0001;
1773 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1775 let Inst{22-20} = 0b001;
1778 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1780 let Inst{22-21} = 0b01;
1783 // 128-bit vector types.
1784 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1786 let Inst{22-19} = 0b0001;
1789 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1791 let Inst{22-20} = 0b001;
1794 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1796 let Inst{22-21} = 0b01;
1799 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1805 // Rounding shift right
1806 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1807 int_aarch64_neon_vsrshr>;
1808 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1809 int_aarch64_neon_vurshr>;
1811 // Saturating shift left unsigned
1812 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1814 // Saturating shift left
1815 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1816 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1818 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1819 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1821 : NeonI_2VShiftImm<q, u, opcode,
1822 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1823 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1824 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1825 (Ty (OpNode (Ty VPRC:$Rn),
1826 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
1828 let Constraints = "$src = $Rd";
1831 // Shift Right accumulate
1832 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1833 def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1835 let Inst{22-19} = 0b0001;
1838 def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1840 let Inst{22-20} = 0b001;
1843 def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1845 let Inst{22-21} = 0b01;
1848 def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1850 let Inst{22-19} = 0b0001;
1853 def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1855 let Inst{22-20} = 0b001;
1858 def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1860 let Inst{22-21} = 0b01;
1863 def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1869 // Shift right and accumulate
1870 defm SSRAvvi : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1871 defm USRAvvi : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1873 // Rounding shift accumulate
1874 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1875 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1876 SDPatternOperator OpNode>
1877 : NeonI_2VShiftImm<q, u, opcode,
1878 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1879 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1880 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1881 (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
1883 let Constraints = "$src = $Rd";
1886 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1887 SDPatternOperator OpNode> {
1888 def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1890 let Inst{22-19} = 0b0001;
1893 def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1895 let Inst{22-20} = 0b001;
1898 def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1900 let Inst{22-21} = 0b01;
1903 def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1905 let Inst{22-19} = 0b0001;
1908 def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1910 let Inst{22-20} = 0b001;
1913 def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1915 let Inst{22-21} = 0b01;
1918 def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1924 // Rounding shift right and accumulate
1925 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1926 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1928 // Shift insert by immediate
1929 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1930 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1931 SDPatternOperator OpNode>
1932 : NeonI_2VShiftImm<q, u, opcode,
1933 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1934 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1935 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1936 (i32 ImmTy:$Imm))))],
1938 let Constraints = "$src = $Rd";
1941 // shift left insert (vector by immediate)
1942 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1943 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1944 int_aarch64_neon_vsli> {
1945 let Inst{22-19} = 0b0001;
1948 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1949 int_aarch64_neon_vsli> {
1950 let Inst{22-20} = 0b001;
1953 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1954 int_aarch64_neon_vsli> {
1955 let Inst{22-21} = 0b01;
1958 // 128-bit vector types
1959 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1960 int_aarch64_neon_vsli> {
1961 let Inst{22-19} = 0b0001;
1964 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1965 int_aarch64_neon_vsli> {
1966 let Inst{22-20} = 0b001;
1969 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1970 int_aarch64_neon_vsli> {
1971 let Inst{22-21} = 0b01;
1974 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1975 int_aarch64_neon_vsli> {
1980 // shift right insert (vector by immediate)
1981 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
1982 // 64-bit vector types.
1983 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1984 int_aarch64_neon_vsri> {
1985 let Inst{22-19} = 0b0001;
1988 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1989 int_aarch64_neon_vsri> {
1990 let Inst{22-20} = 0b001;
1993 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1994 int_aarch64_neon_vsri> {
1995 let Inst{22-21} = 0b01;
1998 // 128-bit vector types
1999 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2000 int_aarch64_neon_vsri> {
2001 let Inst{22-19} = 0b0001;
2004 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2005 int_aarch64_neon_vsri> {
2006 let Inst{22-20} = 0b001;
2009 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2010 int_aarch64_neon_vsri> {
2011 let Inst{22-21} = 0b01;
2014 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2015 int_aarch64_neon_vsri> {
2020 // Shift left and insert
2021 defm SLIvvi : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2023 // Shift right and insert
2024 defm SRIvvi : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2026 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2027 string SrcT, Operand ImmTy>
2028 : NeonI_2VShiftImm<q, u, opcode,
2029 (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2030 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2033 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2034 string SrcT, Operand ImmTy>
2035 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2036 (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2037 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2039 let Constraints = "$src = $Rd";
2042 // left long shift by immediate
2043 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2044 def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2045 let Inst{22-19} = 0b0001;
2048 def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2049 let Inst{22-20} = 0b001;
2052 def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2053 let Inst{22-21} = 0b01;
2056 // Shift Narrow High
2057 def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2059 let Inst{22-19} = 0b0001;
2062 def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2064 let Inst{22-20} = 0b001;
2067 def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2069 let Inst{22-21} = 0b01;
2073 // Shift right narrow
2074 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2076 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2077 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2078 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2079 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2080 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2081 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2082 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2083 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2085 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2086 (v2i64 (concat_vectors (v1i64 node:$Rm),
2087 (v1i64 node:$Rn)))>;
2088 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2089 (v8i16 (concat_vectors (v4i16 node:$Rm),
2090 (v4i16 node:$Rn)))>;
2091 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2092 (v4i32 (concat_vectors (v2i32 node:$Rm),
2093 (v2i32 node:$Rn)))>;
2094 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2095 (v4f32 (concat_vectors (v2f32 node:$Rm),
2096 (v2f32 node:$Rn)))>;
2097 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2098 (v2f64 (concat_vectors (v1f64 node:$Rm),
2099 (v1f64 node:$Rn)))>;
2101 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2102 (v8i16 (srl (v8i16 node:$lhs),
2103 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2104 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2105 (v4i32 (srl (v4i32 node:$lhs),
2106 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2107 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2108 (v2i64 (srl (v2i64 node:$lhs),
2109 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2110 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2111 (v8i16 (sra (v8i16 node:$lhs),
2112 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2113 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2114 (v4i32 (sra (v4i32 node:$lhs),
2115 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2116 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2117 (v2i64 (sra (v2i64 node:$lhs),
2118 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2120 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2121 multiclass Neon_shiftNarrow_patterns<string shr> {
2122 def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2123 (i32 shr_imm8:$Imm)))),
2124 (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2125 def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2126 (i32 shr_imm16:$Imm)))),
2127 (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2128 def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2129 (i32 shr_imm32:$Imm)))),
2130 (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2132 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2133 (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2134 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2135 (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2136 VPR128:$Rn, imm:$Imm)>;
2137 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2138 (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2139 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2140 (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2141 VPR128:$Rn, imm:$Imm)>;
2142 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2143 (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2144 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2145 (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2146 VPR128:$Rn, imm:$Imm)>;
2149 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2150 def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2151 (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2152 def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2153 (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2154 def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2155 (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2157 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2158 (v1i64 (bitconvert (v8i8
2159 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2160 (!cast<Instruction>(prefix # "_16B")
2161 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2162 VPR128:$Rn, imm:$Imm)>;
2163 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2164 (v1i64 (bitconvert (v4i16
2165 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2166 (!cast<Instruction>(prefix # "_8H")
2167 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2168 VPR128:$Rn, imm:$Imm)>;
2169 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2170 (v1i64 (bitconvert (v2i32
2171 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2172 (!cast<Instruction>(prefix # "_4S")
2173 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2174 VPR128:$Rn, imm:$Imm)>;
2177 defm : Neon_shiftNarrow_patterns<"lshr">;
2178 defm : Neon_shiftNarrow_patterns<"ashr">;
2180 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2181 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2182 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2183 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2184 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2185 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2186 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2188 // Convert fix-point and float-pointing
2189 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2190 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2191 Operand ImmTy, SDPatternOperator IntOp>
2192 : NeonI_2VShiftImm<q, u, opcode,
2193 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2194 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2195 [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2196 (i32 ImmTy:$Imm))))],
2199 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2200 SDPatternOperator IntOp> {
2201 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2203 let Inst{22-21} = 0b01;
2206 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2208 let Inst{22-21} = 0b01;
2211 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2217 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2218 SDPatternOperator IntOp> {
2219 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2221 let Inst{22-21} = 0b01;
2224 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2226 let Inst{22-21} = 0b01;
2229 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2235 // Convert fixed-point to floating-point
2236 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2237 int_arm_neon_vcvtfxs2fp>;
2238 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2239 int_arm_neon_vcvtfxu2fp>;
2241 // Convert floating-point to fixed-point
2242 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2243 int_arm_neon_vcvtfp2fxs>;
2244 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2245 int_arm_neon_vcvtfp2fxu>;
2247 multiclass Neon_sshll2_0<SDNode ext>
2249 def _v8i8 : PatFrag<(ops node:$Rn),
2250 (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2251 def _v4i16 : PatFrag<(ops node:$Rn),
2252 (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2253 def _v2i32 : PatFrag<(ops node:$Rn),
2254 (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2257 defm NI_sext_high : Neon_sshll2_0<sext>;
2258 defm NI_zext_high : Neon_sshll2_0<zext>;
2261 //===----------------------------------------------------------------------===//
2262 // Multiclasses for NeonI_Across
2263 //===----------------------------------------------------------------------===//
2267 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2268 string asmop, SDPatternOperator opnode>
2270 def _1h8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2271 (outs FPR16:$Rd), (ins VPR64:$Rn),
2272 asmop # "\t$Rd, $Rn.8b",
2273 [(set (v1i16 FPR16:$Rd),
2274 (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2277 def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2278 (outs FPR16:$Rd), (ins VPR128:$Rn),
2279 asmop # "\t$Rd, $Rn.16b",
2280 [(set (v1i16 FPR16:$Rd),
2281 (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2284 def _1s4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2285 (outs FPR32:$Rd), (ins VPR64:$Rn),
2286 asmop # "\t$Rd, $Rn.4h",
2287 [(set (v1i32 FPR32:$Rd),
2288 (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2291 def _1s8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2292 (outs FPR32:$Rd), (ins VPR128:$Rn),
2293 asmop # "\t$Rd, $Rn.8h",
2294 [(set (v1i32 FPR32:$Rd),
2295 (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2298 // _1d2s doesn't exist!
2300 def _1d4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2301 (outs FPR64:$Rd), (ins VPR128:$Rn),
2302 asmop # "\t$Rd, $Rn.4s",
2303 [(set (v1i64 FPR64:$Rd),
2304 (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2308 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2309 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2313 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2314 string asmop, SDPatternOperator opnode>
2316 def _1b8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2317 (outs FPR8:$Rd), (ins VPR64:$Rn),
2318 asmop # "\t$Rd, $Rn.8b",
2319 [(set (v1i8 FPR8:$Rd),
2320 (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2323 def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2324 (outs FPR8:$Rd), (ins VPR128:$Rn),
2325 asmop # "\t$Rd, $Rn.16b",
2326 [(set (v1i8 FPR8:$Rd),
2327 (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2330 def _1h4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2331 (outs FPR16:$Rd), (ins VPR64:$Rn),
2332 asmop # "\t$Rd, $Rn.4h",
2333 [(set (v1i16 FPR16:$Rd),
2334 (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2337 def _1h8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2338 (outs FPR16:$Rd), (ins VPR128:$Rn),
2339 asmop # "\t$Rd, $Rn.8h",
2340 [(set (v1i16 FPR16:$Rd),
2341 (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2344 // _1s2s doesn't exist!
2346 def _1s4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2347 (outs FPR32:$Rd), (ins VPR128:$Rn),
2348 asmop # "\t$Rd, $Rn.4s",
2349 [(set (v1i32 FPR32:$Rd),
2350 (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2354 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2355 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2357 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2358 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2360 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2364 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2365 string asmop, SDPatternOperator opnode> {
2366 def _1s4s: NeonI_2VAcross<0b1, u, size, opcode,
2367 (outs FPR32:$Rd), (ins VPR128:$Rn),
2368 asmop # "\t$Rd, $Rn.4s",
2369 [(set (v1f32 FPR32:$Rd),
2370 (v1f32 (opnode (v4f32 VPR128:$Rn))))],
2374 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2375 int_aarch64_neon_vmaxnmv>;
2376 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2377 int_aarch64_neon_vminnmv>;
2379 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2380 int_aarch64_neon_vmaxv>;
2381 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2382 int_aarch64_neon_vminv>;
2384 // The followings are for instruction class (Perm)
2386 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2387 string asmop, RegisterOperand OpVPR, string OpS,
2388 SDPatternOperator opnode, ValueType Ty>
2389 : NeonI_Perm<q, size, opcode,
2390 (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2391 asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2392 [(set (Ty OpVPR:$Rd),
2393 (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2396 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2397 SDPatternOperator opnode> {
2398 def _8b : NeonI_Permute<0b0, 0b00, opcode, asmop,
2399 VPR64, "8b", opnode, v8i8>;
2400 def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2401 VPR128, "16b",opnode, v16i8>;
2402 def _4h : NeonI_Permute<0b0, 0b01, opcode, asmop,
2403 VPR64, "4h", opnode, v4i16>;
2404 def _8h : NeonI_Permute<0b1, 0b01, opcode, asmop,
2405 VPR128, "8h", opnode, v8i16>;
2406 def _2s : NeonI_Permute<0b0, 0b10, opcode, asmop,
2407 VPR64, "2s", opnode, v2i32>;
2408 def _4s : NeonI_Permute<0b1, 0b10, opcode, asmop,
2409 VPR128, "4s", opnode, v4i32>;
2410 def _2d : NeonI_Permute<0b1, 0b11, opcode, asmop,
2411 VPR128, "2d", opnode, v2i64>;
2414 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2415 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2416 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2417 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2418 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2419 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2421 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2422 def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2423 (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2425 def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2426 (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2428 def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2429 (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2432 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2433 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2434 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2435 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2436 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2437 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2439 // The followings are for instruction class (3V Diff)
2441 // normal long/long2 pattern
2442 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2443 string asmop, string ResS, string OpS,
2444 SDPatternOperator opnode, SDPatternOperator ext,
2445 RegisterOperand OpVPR,
2446 ValueType ResTy, ValueType OpTy>
2447 : NeonI_3VDiff<q, u, size, opcode,
2448 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2449 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2450 [(set (ResTy VPR128:$Rd),
2451 (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2452 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2455 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2456 string asmop, SDPatternOperator opnode,
2457 bit Commutable = 0> {
2458 let isCommutable = Commutable in {
2459 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2460 opnode, sext, VPR64, v8i16, v8i8>;
2461 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2462 opnode, sext, VPR64, v4i32, v4i16>;
2463 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2464 opnode, sext, VPR64, v2i64, v2i32>;
2468 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2469 SDPatternOperator opnode, bit Commutable = 0> {
2470 let isCommutable = Commutable in {
2471 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2472 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2473 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2474 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2475 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2476 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2480 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2481 SDPatternOperator opnode, bit Commutable = 0> {
2482 let isCommutable = Commutable in {
2483 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2484 opnode, zext, VPR64, v8i16, v8i8>;
2485 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2486 opnode, zext, VPR64, v4i32, v4i16>;
2487 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2488 opnode, zext, VPR64, v2i64, v2i32>;
2492 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2493 SDPatternOperator opnode, bit Commutable = 0> {
2494 let isCommutable = Commutable in {
2495 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2496 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2497 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2498 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2499 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2500 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2504 defm SADDLvvv : NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2505 defm UADDLvvv : NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2507 defm SADDL2vvv : NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2508 defm UADDL2vvv : NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2510 defm SSUBLvvv : NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2511 defm USUBLvvv : NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2513 defm SSUBL2vvv : NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2514 defm USUBL2vvv : NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2516 // normal wide/wide2 pattern
2517 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2518 string asmop, string ResS, string OpS,
2519 SDPatternOperator opnode, SDPatternOperator ext,
2520 RegisterOperand OpVPR,
2521 ValueType ResTy, ValueType OpTy>
2522 : NeonI_3VDiff<q, u, size, opcode,
2523 (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2524 asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2525 [(set (ResTy VPR128:$Rd),
2526 (ResTy (opnode (ResTy VPR128:$Rn),
2527 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2530 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2531 SDPatternOperator opnode> {
2532 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2533 opnode, sext, VPR64, v8i16, v8i8>;
2534 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2535 opnode, sext, VPR64, v4i32, v4i16>;
2536 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2537 opnode, sext, VPR64, v2i64, v2i32>;
2540 defm SADDWvvv : NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2541 defm SSUBWvvv : NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2543 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2544 SDPatternOperator opnode> {
2545 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2546 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2547 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2548 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2549 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2550 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2553 defm SADDW2vvv : NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2554 defm SSUBW2vvv : NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2556 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2557 SDPatternOperator opnode> {
2558 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2559 opnode, zext, VPR64, v8i16, v8i8>;
2560 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2561 opnode, zext, VPR64, v4i32, v4i16>;
2562 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2563 opnode, zext, VPR64, v2i64, v2i32>;
2566 defm UADDWvvv : NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2567 defm USUBWvvv : NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2569 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2570 SDPatternOperator opnode> {
2571 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2572 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2573 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2574 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2575 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2576 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2579 defm UADDW2vvv : NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2580 defm USUBW2vvv : NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2582 // Get the high half part of the vector element.
2583 multiclass NeonI_get_high {
2584 def _8h : PatFrag<(ops node:$Rn),
2585 (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2586 (v8i16 (Neon_vdup (i32 8)))))))>;
2587 def _4s : PatFrag<(ops node:$Rn),
2588 (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2589 (v4i32 (Neon_vdup (i32 16)))))))>;
2590 def _2d : PatFrag<(ops node:$Rn),
2591 (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2592 (v2i64 (Neon_vdup (i32 32)))))))>;
2595 defm NI_get_hi : NeonI_get_high;
2597 // pattern for addhn/subhn with 2 operands
2598 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2599 string asmop, string ResS, string OpS,
2600 SDPatternOperator opnode, SDPatternOperator get_hi,
2601 ValueType ResTy, ValueType OpTy>
2602 : NeonI_3VDiff<q, u, size, opcode,
2603 (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2604 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2605 [(set (ResTy VPR64:$Rd),
2607 (OpTy (opnode (OpTy VPR128:$Rn),
2608 (OpTy VPR128:$Rm))))))],
2611 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2612 SDPatternOperator opnode, bit Commutable = 0> {
2613 let isCommutable = Commutable in {
2614 def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2615 opnode, NI_get_hi_8h, v8i8, v8i16>;
2616 def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2617 opnode, NI_get_hi_4s, v4i16, v4i32>;
2618 def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2619 opnode, NI_get_hi_2d, v2i32, v2i64>;
2623 defm ADDHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2624 defm SUBHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2626 // pattern for operation with 2 operands
2627 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2628 string asmop, string ResS, string OpS,
2629 SDPatternOperator opnode,
2630 RegisterOperand ResVPR, RegisterOperand OpVPR,
2631 ValueType ResTy, ValueType OpTy>
2632 : NeonI_3VDiff<q, u, size, opcode,
2633 (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2634 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2635 [(set (ResTy ResVPR:$Rd),
2636 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2639 // normal narrow pattern
2640 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2641 SDPatternOperator opnode, bit Commutable = 0> {
2642 let isCommutable = Commutable in {
2643 def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2644 opnode, VPR64, VPR128, v8i8, v8i16>;
2645 def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2646 opnode, VPR64, VPR128, v4i16, v4i32>;
2647 def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2648 opnode, VPR64, VPR128, v2i32, v2i64>;
2652 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2653 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2655 // pattern for acle intrinsic with 3 operands
2656 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2657 string asmop, string ResS, string OpS>
2658 : NeonI_3VDiff<q, u, size, opcode,
2659 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2660 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2662 let Constraints = "$src = $Rd";
2663 let neverHasSideEffects = 1;
2666 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2667 def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2668 def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2669 def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2672 defm ADDHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2673 defm SUBHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2675 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2676 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2678 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2680 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2681 SDPatternOperator coreop>
2682 : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2683 (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2684 (SrcTy VPR128:$Rm)))))),
2685 (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2686 VPR128:$Rn, VPR128:$Rm)>;
2689 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8, v8i16,
2690 BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2691 def : NarrowHighHalfPat<ADDHN2vvv_8h4s, v4i16, v4i32,
2692 BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2693 def : NarrowHighHalfPat<ADDHN2vvv_4s2d, v2i32, v2i64,
2694 BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2697 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8, v8i16,
2698 BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2699 def : NarrowHighHalfPat<SUBHN2vvv_8h4s, v4i16, v4i32,
2700 BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2701 def : NarrowHighHalfPat<SUBHN2vvv_4s2d, v2i32, v2i64,
2702 BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2705 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vraddhn>;
2706 def : NarrowHighHalfPat<RADDHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vraddhn>;
2707 def : NarrowHighHalfPat<RADDHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vraddhn>;
2710 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vrsubhn>;
2711 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vrsubhn>;
2712 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vrsubhn>;
2714 // pattern that need to extend result
2715 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2716 string asmop, string ResS, string OpS,
2717 SDPatternOperator opnode,
2718 RegisterOperand OpVPR,
2719 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2720 : NeonI_3VDiff<q, u, size, opcode,
2721 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2722 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2723 [(set (ResTy VPR128:$Rd),
2724 (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2725 (OpTy OpVPR:$Rm))))))],
2728 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2729 SDPatternOperator opnode, bit Commutable = 0> {
2730 let isCommutable = Commutable in {
2731 def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2732 opnode, VPR64, v8i16, v8i8, v8i8>;
2733 def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2734 opnode, VPR64, v4i32, v4i16, v4i16>;
2735 def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2736 opnode, VPR64, v2i64, v2i32, v2i32>;
2740 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2741 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2743 multiclass NeonI_Op_High<SDPatternOperator op> {
2744 def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2745 (op (v8i8 (Neon_High16B node:$Rn)),
2746 (v8i8 (Neon_High16B node:$Rm)))>;
2747 def _8H : PatFrag<(ops node:$Rn, node:$Rm),
2748 (op (v4i16 (Neon_High8H node:$Rn)),
2749 (v4i16 (Neon_High8H node:$Rm)))>;
2750 def _4S : PatFrag<(ops node:$Rn, node:$Rm),
2751 (op (v2i32 (Neon_High4S node:$Rn)),
2752 (v2i32 (Neon_High4S node:$Rm)))>;
2755 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2756 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2757 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2758 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2759 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2760 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2762 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2763 bit Commutable = 0> {
2764 let isCommutable = Commutable in {
2765 def _8h8b : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2766 !cast<PatFrag>(opnode # "_16B"),
2767 VPR128, v8i16, v16i8, v8i8>;
2768 def _4s4h : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2769 !cast<PatFrag>(opnode # "_8H"),
2770 VPR128, v4i32, v8i16, v4i16>;
2771 def _2d2s : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2772 !cast<PatFrag>(opnode # "_4S"),
2773 VPR128, v2i64, v4i32, v2i32>;
2777 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2778 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2780 // For pattern that need two operators being chained.
2781 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2782 string asmop, string ResS, string OpS,
2783 SDPatternOperator opnode, SDPatternOperator subop,
2784 RegisterOperand OpVPR,
2785 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2786 : NeonI_3VDiff<q, u, size, opcode,
2787 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2788 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2789 [(set (ResTy VPR128:$Rd),
2791 (ResTy VPR128:$src),
2792 (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2793 (OpTy OpVPR:$Rm))))))))],
2795 let Constraints = "$src = $Rd";
2798 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2799 SDPatternOperator opnode, SDPatternOperator subop>{
2800 def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2801 opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2802 def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2803 opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2804 def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2805 opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2808 defm SABALvvv : NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2809 add, int_arm_neon_vabds>;
2810 defm UABALvvv : NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2811 add, int_arm_neon_vabdu>;
2813 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2814 SDPatternOperator opnode, string subop> {
2815 def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2816 opnode, !cast<PatFrag>(subop # "_16B"),
2817 VPR128, v8i16, v16i8, v8i8>;
2818 def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2819 opnode, !cast<PatFrag>(subop # "_8H"),
2820 VPR128, v4i32, v8i16, v4i16>;
2821 def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2822 opnode, !cast<PatFrag>(subop # "_4S"),
2823 VPR128, v2i64, v4i32, v2i32>;
2826 defm SABAL2vvv : NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2828 defm UABAL2vvv : NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2831 // Long pattern with 2 operands
2832 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
2833 SDPatternOperator opnode, bit Commutable = 0> {
2834 let isCommutable = Commutable in {
2835 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2836 opnode, VPR128, VPR64, v8i16, v8i8>;
2837 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2838 opnode, VPR128, VPR64, v4i32, v4i16>;
2839 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2840 opnode, VPR128, VPR64, v2i64, v2i32>;
2844 defm SMULLvvv : NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
2845 defm UMULLvvv : NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
2847 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
2848 string asmop, string ResS, string OpS,
2849 SDPatternOperator opnode,
2850 ValueType ResTy, ValueType OpTy>
2851 : NeonI_3VDiff<q, u, size, opcode,
2852 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2853 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2854 [(set (ResTy VPR128:$Rd),
2855 (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
2858 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
2859 string opnode, bit Commutable = 0> {
2860 let isCommutable = Commutable in {
2861 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2862 !cast<PatFrag>(opnode # "_16B"),
2864 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2865 !cast<PatFrag>(opnode # "_8H"),
2867 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2868 !cast<PatFrag>(opnode # "_4S"),
2873 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
2875 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
2878 // Long pattern with 3 operands
2879 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2880 string asmop, string ResS, string OpS,
2881 SDPatternOperator opnode,
2882 ValueType ResTy, ValueType OpTy>
2883 : NeonI_3VDiff<q, u, size, opcode,
2884 (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
2885 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2886 [(set (ResTy VPR128:$Rd),
2888 (ResTy VPR128:$src),
2889 (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
2891 let Constraints = "$src = $Rd";
2894 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
2895 SDPatternOperator opnode> {
2896 def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2897 opnode, v8i16, v8i8>;
2898 def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2899 opnode, v4i32, v4i16>;
2900 def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2901 opnode, v2i64, v2i32>;
2904 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2906 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2908 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2910 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2912 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2914 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2916 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2918 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2920 defm SMLALvvv : NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
2921 defm UMLALvvv : NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
2923 defm SMLSLvvv : NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
2924 defm UMLSLvvv : NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
2926 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
2927 string asmop, string ResS, string OpS,
2928 SDPatternOperator subop, SDPatternOperator opnode,
2929 RegisterOperand OpVPR,
2930 ValueType ResTy, ValueType OpTy>
2931 : NeonI_3VDiff<q, u, size, opcode,
2932 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2933 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2934 [(set (ResTy VPR128:$Rd),
2936 (ResTy VPR128:$src),
2937 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
2939 let Constraints = "$src = $Rd";
2942 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
2943 SDPatternOperator subop, string opnode> {
2944 def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2945 subop, !cast<PatFrag>(opnode # "_16B"),
2946 VPR128, v8i16, v16i8>;
2947 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2948 subop, !cast<PatFrag>(opnode # "_8H"),
2949 VPR128, v4i32, v8i16>;
2950 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2951 subop, !cast<PatFrag>(opnode # "_4S"),
2952 VPR128, v2i64, v4i32>;
2955 defm SMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
2956 add, "NI_smull_hi">;
2957 defm UMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
2958 add, "NI_umull_hi">;
2960 defm SMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
2961 sub, "NI_smull_hi">;
2962 defm UMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
2963 sub, "NI_umull_hi">;
2965 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
2966 SDPatternOperator opnode> {
2967 def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2968 opnode, int_arm_neon_vqdmull,
2969 VPR64, v4i32, v4i16>;
2970 def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2971 opnode, int_arm_neon_vqdmull,
2972 VPR64, v2i64, v2i32>;
2975 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
2976 int_arm_neon_vqadds>;
2977 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
2978 int_arm_neon_vqsubs>;
2980 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
2981 SDPatternOperator opnode, bit Commutable = 0> {
2982 let isCommutable = Commutable in {
2983 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2984 opnode, VPR128, VPR64, v4i32, v4i16>;
2985 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2986 opnode, VPR128, VPR64, v2i64, v2i32>;
2990 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
2991 int_arm_neon_vqdmull, 1>;
2993 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
2994 string opnode, bit Commutable = 0> {
2995 let isCommutable = Commutable in {
2996 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2997 !cast<PatFrag>(opnode # "_8H"),
2999 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3000 !cast<PatFrag>(opnode # "_4S"),
3005 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3008 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3009 SDPatternOperator opnode> {
3010 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3011 opnode, NI_qdmull_hi_8H,
3012 VPR128, v4i32, v8i16>;
3013 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3014 opnode, NI_qdmull_hi_4S,
3015 VPR128, v2i64, v4i32>;
3018 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3019 int_arm_neon_vqadds>;
3020 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3021 int_arm_neon_vqsubs>;
3023 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3024 SDPatternOperator opnode, bit Commutable = 0> {
3025 let isCommutable = Commutable in {
3026 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3027 opnode, VPR128, VPR64, v8i16, v8i8>;
3029 def _1q1d : NeonI_3VDiff<0b0, u, 0b11, opcode,
3030 (outs VPR128:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
3031 asmop # "\t$Rd.1q, $Rn.1d, $Rm.1d",
3036 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp, 1>;
3038 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3039 string opnode, bit Commutable = 0> {
3040 let isCommutable = Commutable in {
3041 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3042 !cast<PatFrag>(opnode # "_16B"),
3045 def _1q2d : NeonI_3VDiff<0b1, u, 0b11, opcode,
3046 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3047 asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3052 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3055 // End of implementation for instruction class (3V Diff)
3057 // The followings are vector load/store multiple N-element structure
3058 // (class SIMD lselem).
3060 // ld1: load multiple 1-element structure to 1/2/3/4 registers.
3061 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3062 // The structure consists of a sequence of sets of N values.
3063 // The first element of the structure is placed in the first lane
3064 // of the first first vector, the second element in the first lane
3065 // of the second vector, and so on.
3066 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3067 // the three 64-bit vectors list {BA, DC, FE}.
3068 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3069 // 64-bit vectors list {DA, EB, FC}.
3070 // Store instructions store multiple structure to N registers like load.
3073 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3074 RegisterOperand VecList, string asmop>
3075 : NeonI_LdStMult<q, 1, opcode, size,
3076 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3077 asmop # "\t$Rt, [$Rn]",
3081 let neverHasSideEffects = 1;
3084 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3085 def _8B : NeonI_LDVList<0, opcode, 0b00,
3086 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3088 def _4H : NeonI_LDVList<0, opcode, 0b01,
3089 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3091 def _2S : NeonI_LDVList<0, opcode, 0b10,
3092 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3094 def _16B : NeonI_LDVList<1, opcode, 0b00,
3095 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3097 def _8H : NeonI_LDVList<1, opcode, 0b01,
3098 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3100 def _4S : NeonI_LDVList<1, opcode, 0b10,
3101 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3103 def _2D : NeonI_LDVList<1, opcode, 0b11,
3104 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3107 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3108 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3109 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3111 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3113 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3115 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3117 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3118 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3119 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3121 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3122 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3124 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3125 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3127 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3128 RegisterOperand VecList, string asmop>
3129 : NeonI_LdStMult<q, 0, opcode, size,
3130 (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3131 asmop # "\t$Rt, [$Rn]",
3135 let neverHasSideEffects = 1;
3138 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3139 def _8B : NeonI_STVList<0, opcode, 0b00,
3140 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3142 def _4H : NeonI_STVList<0, opcode, 0b01,
3143 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3145 def _2S : NeonI_STVList<0, opcode, 0b10,
3146 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3148 def _16B : NeonI_STVList<1, opcode, 0b00,
3149 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3151 def _8H : NeonI_STVList<1, opcode, 0b01,
3152 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3154 def _4S : NeonI_STVList<1, opcode, 0b10,
3155 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3157 def _2D : NeonI_STVList<1, opcode, 0b11,
3158 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3161 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3162 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3163 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3165 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3167 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3169 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3171 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3172 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3173 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3175 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3176 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3178 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3179 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3181 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3182 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3184 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3185 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3187 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3188 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3190 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3191 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3193 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3194 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3196 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3197 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3199 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3200 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3201 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3202 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3204 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3205 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3206 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3207 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3209 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3210 (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3211 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3212 (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3214 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3215 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3216 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3217 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3219 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3220 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3221 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3222 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3224 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3225 (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3226 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3227 (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3229 // End of vector load/store multiple N-element structure(class SIMD lselem)
3231 // The followings are post-index vector load/store multiple N-element
3232 // structure(class SIMD lselem-post)
3233 def exact1_asmoperand : AsmOperandClass {
3234 let Name = "Exact1";
3235 let PredicateMethod = "isExactImm<1>";
3236 let RenderMethod = "addImmOperands";
3238 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3239 let ParserMatchClass = exact1_asmoperand;
3242 def exact2_asmoperand : AsmOperandClass {
3243 let Name = "Exact2";
3244 let PredicateMethod = "isExactImm<2>";
3245 let RenderMethod = "addImmOperands";
3247 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3248 let ParserMatchClass = exact2_asmoperand;
3251 def exact3_asmoperand : AsmOperandClass {
3252 let Name = "Exact3";
3253 let PredicateMethod = "isExactImm<3>";
3254 let RenderMethod = "addImmOperands";
3256 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3257 let ParserMatchClass = exact3_asmoperand;
3260 def exact4_asmoperand : AsmOperandClass {
3261 let Name = "Exact4";
3262 let PredicateMethod = "isExactImm<4>";
3263 let RenderMethod = "addImmOperands";
3265 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3266 let ParserMatchClass = exact4_asmoperand;
3269 def exact6_asmoperand : AsmOperandClass {
3270 let Name = "Exact6";
3271 let PredicateMethod = "isExactImm<6>";
3272 let RenderMethod = "addImmOperands";
3274 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3275 let ParserMatchClass = exact6_asmoperand;
3278 def exact8_asmoperand : AsmOperandClass {
3279 let Name = "Exact8";
3280 let PredicateMethod = "isExactImm<8>";
3281 let RenderMethod = "addImmOperands";
3283 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3284 let ParserMatchClass = exact8_asmoperand;
3287 def exact12_asmoperand : AsmOperandClass {
3288 let Name = "Exact12";
3289 let PredicateMethod = "isExactImm<12>";
3290 let RenderMethod = "addImmOperands";
3292 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3293 let ParserMatchClass = exact12_asmoperand;
3296 def exact16_asmoperand : AsmOperandClass {
3297 let Name = "Exact16";
3298 let PredicateMethod = "isExactImm<16>";
3299 let RenderMethod = "addImmOperands";
3301 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3302 let ParserMatchClass = exact16_asmoperand;
3305 def exact24_asmoperand : AsmOperandClass {
3306 let Name = "Exact24";
3307 let PredicateMethod = "isExactImm<24>";
3308 let RenderMethod = "addImmOperands";
3310 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3311 let ParserMatchClass = exact24_asmoperand;
3314 def exact32_asmoperand : AsmOperandClass {
3315 let Name = "Exact32";
3316 let PredicateMethod = "isExactImm<32>";
3317 let RenderMethod = "addImmOperands";
3319 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3320 let ParserMatchClass = exact32_asmoperand;
3323 def exact48_asmoperand : AsmOperandClass {
3324 let Name = "Exact48";
3325 let PredicateMethod = "isExactImm<48>";
3326 let RenderMethod = "addImmOperands";
3328 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3329 let ParserMatchClass = exact48_asmoperand;
3332 def exact64_asmoperand : AsmOperandClass {
3333 let Name = "Exact64";
3334 let PredicateMethod = "isExactImm<64>";
3335 let RenderMethod = "addImmOperands";
3337 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3338 let ParserMatchClass = exact64_asmoperand;
3341 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3342 RegisterOperand VecList, Operand ImmTy,
3344 let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3345 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3346 def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3347 (outs VecList:$Rt, GPR64xsp:$wb),
3348 (ins GPR64xsp:$Rn, ImmTy:$amt),
3349 asmop # "\t$Rt, [$Rn], $amt",
3355 def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3356 (outs VecList:$Rt, GPR64xsp:$wb),
3357 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3358 asmop # "\t$Rt, [$Rn], $Rm",
3364 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3365 Operand ImmTy2, string asmop> {
3366 defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3367 !cast<RegisterOperand>(List # "8B_operand"),
3370 defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3371 !cast<RegisterOperand>(List # "4H_operand"),
3374 defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3375 !cast<RegisterOperand>(List # "2S_operand"),
3378 defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3379 !cast<RegisterOperand>(List # "16B_operand"),
3382 defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3383 !cast<RegisterOperand>(List # "8H_operand"),
3386 defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3387 !cast<RegisterOperand>(List # "4S_operand"),
3390 defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3391 !cast<RegisterOperand>(List # "2D_operand"),
3395 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3396 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3397 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3400 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3402 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3405 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3407 // Post-index load multiple 1-element structures from N consecutive registers
3409 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3411 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3412 uimm_exact16, "ld1">;
3414 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3416 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3417 uimm_exact24, "ld1">;
3419 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3421 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3422 uimm_exact32, "ld1">;
3424 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3425 RegisterOperand VecList, Operand ImmTy,
3427 let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3428 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3429 def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3430 (outs GPR64xsp:$wb),
3431 (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3432 asmop # "\t$Rt, [$Rn], $amt",
3438 def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3439 (outs GPR64xsp:$wb),
3440 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3441 asmop # "\t$Rt, [$Rn], $Rm",
3447 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3448 Operand ImmTy2, string asmop> {
3449 defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3450 !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3452 defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3453 !cast<RegisterOperand>(List # "4H_operand"),
3456 defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3457 !cast<RegisterOperand>(List # "2S_operand"),
3460 defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3461 !cast<RegisterOperand>(List # "16B_operand"),
3464 defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3465 !cast<RegisterOperand>(List # "8H_operand"),
3468 defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3469 !cast<RegisterOperand>(List # "4S_operand"),
3472 defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3473 !cast<RegisterOperand>(List # "2D_operand"),
3477 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3478 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3479 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3482 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3484 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3487 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3489 // Post-index load multiple 1-element structures from N consecutive registers
3491 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3493 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3494 uimm_exact16, "st1">;
3496 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3498 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3499 uimm_exact24, "st1">;
3501 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3503 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3504 uimm_exact32, "st1">;
3506 // End of post-index vector load/store multiple N-element structure
3507 // (class SIMD lselem-post)
3509 // The followings are vector load/store single N-element structure
3510 // (class SIMD lsone).
3511 def neon_uimm0_bare : Operand<i64>,
3512 ImmLeaf<i64, [{return Imm == 0;}]> {
3513 let ParserMatchClass = neon_uimm0_asmoperand;
3514 let PrintMethod = "printUImmBareOperand";
3517 def neon_uimm1_bare : Operand<i64>,
3518 ImmLeaf<i64, [{return Imm < 2;}]> {
3519 let ParserMatchClass = neon_uimm1_asmoperand;
3520 let PrintMethod = "printUImmBareOperand";
3523 def neon_uimm2_bare : Operand<i64>,
3524 ImmLeaf<i64, [{return Imm < 4;}]> {
3525 let ParserMatchClass = neon_uimm2_asmoperand;
3526 let PrintMethod = "printUImmBareOperand";
3529 def neon_uimm3_bare : Operand<i64>,
3530 ImmLeaf<i64, [{return Imm < 8;}]> {
3531 let ParserMatchClass = uimm3_asmoperand;
3532 let PrintMethod = "printUImmBareOperand";
3535 def neon_uimm4_bare : Operand<i64>,
3536 ImmLeaf<i64, [{return Imm < 16;}]> {
3537 let ParserMatchClass = uimm4_asmoperand;
3538 let PrintMethod = "printUImmBareOperand";
3541 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3542 RegisterOperand VecList, string asmop>
3543 : NeonI_LdOne_Dup<q, r, opcode, size,
3544 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3545 asmop # "\t$Rt, [$Rn]",
3549 let neverHasSideEffects = 1;
3552 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3553 def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3554 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3556 def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3557 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3559 def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3560 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3562 def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3563 !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3565 def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3566 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3568 def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3569 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3571 def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3572 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3574 def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3575 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3578 // Load single 1-element structure to all lanes of 1 register
3579 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3581 // Load single N-element structure to all lanes of N consecutive
3582 // registers (N = 2,3,4)
3583 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3584 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3585 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3588 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3590 : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3591 (VTy (INST GPR64xsp:$Rn))>;
3593 // Match all LD1R instructions
3594 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3596 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3598 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3600 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3602 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3603 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3605 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3606 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3608 def : LD1R_pattern<v1i64, i64, load, LD1R_1D>;
3609 def : LD1R_pattern<v1f64, f64, load, LD1R_1D>;
3611 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3612 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3615 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3616 RegisterClass RegList> {
3617 defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3618 defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3619 defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3620 defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3623 // Special vector list operand of 128-bit vectors with bare layout.
3624 // i.e. only show ".b", ".h", ".s", ".d"
3625 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3626 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3627 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3628 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3630 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3631 Operand ImmOp, string asmop>
3632 : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3634 (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3635 asmop # "\t$Rt[$lane], [$Rn]",
3639 let neverHasSideEffects = 1;
3640 let hasExtraDefRegAllocReq = 1;
3641 let Constraints = "$src = $Rt";
3644 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3645 def _B : NeonI_LDN_Lane<r, 0b00, op0,
3646 !cast<RegisterOperand>(List # "B_operand"),
3647 neon_uimm4_bare, asmop> {
3648 let Inst{12-10} = lane{2-0};
3649 let Inst{30} = lane{3};
3652 def _H : NeonI_LDN_Lane<r, 0b01, op0,
3653 !cast<RegisterOperand>(List # "H_operand"),
3654 neon_uimm3_bare, asmop> {
3655 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3656 let Inst{30} = lane{2};
3659 def _S : NeonI_LDN_Lane<r, 0b10, op0,
3660 !cast<RegisterOperand>(List # "S_operand"),
3661 neon_uimm2_bare, asmop> {
3662 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3663 let Inst{30} = lane{1};
3666 def _D : NeonI_LDN_Lane<r, 0b10, op0,
3667 !cast<RegisterOperand>(List # "D_operand"),
3668 neon_uimm1_bare, asmop> {
3669 let Inst{12-10} = 0b001;
3670 let Inst{30} = lane{0};
3674 // Load single 1-element structure to one lane of 1 register.
3675 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3677 // Load single N-element structure to one lane of N consecutive registers
3679 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3680 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3681 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3683 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3684 Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3686 def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3687 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3688 (VTy (EXTRACT_SUBREG
3690 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3694 def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3695 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3696 (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3699 // Match all LD1LN instructions
3700 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3701 extloadi8, LD1LN_B>;
3703 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3704 extloadi16, LD1LN_H>;
3706 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3708 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3711 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3713 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3716 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3717 Operand ImmOp, string asmop>
3718 : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3719 (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3720 asmop # "\t$Rt[$lane], [$Rn]",
3724 let neverHasSideEffects = 1;
3725 let hasExtraDefRegAllocReq = 1;
3728 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3729 def _B : NeonI_STN_Lane<r, 0b00, op0,
3730 !cast<RegisterOperand>(List # "B_operand"),
3731 neon_uimm4_bare, asmop> {
3732 let Inst{12-10} = lane{2-0};
3733 let Inst{30} = lane{3};
3736 def _H : NeonI_STN_Lane<r, 0b01, op0,
3737 !cast<RegisterOperand>(List # "H_operand"),
3738 neon_uimm3_bare, asmop> {
3739 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3740 let Inst{30} = lane{2};
3743 def _S : NeonI_STN_Lane<r, 0b10, op0,
3744 !cast<RegisterOperand>(List # "S_operand"),
3745 neon_uimm2_bare, asmop> {
3746 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3747 let Inst{30} = lane{1};
3750 def _D : NeonI_STN_Lane<r, 0b10, op0,
3751 !cast<RegisterOperand>(List # "D_operand"),
3752 neon_uimm1_bare, asmop>{
3753 let Inst{12-10} = 0b001;
3754 let Inst{30} = lane{0};
3758 // Store single 1-element structure from one lane of 1 register.
3759 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3761 // Store single N-element structure from one lane of N consecutive registers
3763 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3764 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3765 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3767 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3768 Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3770 def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3773 (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3776 def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3778 (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3781 // Match all ST1LN instructions
3782 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3783 truncstorei8, ST1LN_B>;
3785 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3786 truncstorei16, ST1LN_H>;
3788 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3790 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3793 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3795 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3798 // End of vector load/store single N-element structure (class SIMD lsone).
3801 // The following are post-index load/store single N-element instructions
3802 // (class SIMD lsone-post)
3804 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3805 RegisterOperand VecList, Operand ImmTy,
3807 let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
3808 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3809 def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3810 (outs VecList:$Rt, GPR64xsp:$wb),
3811 (ins GPR64xsp:$Rn, ImmTy:$amt),
3812 asmop # "\t$Rt, [$Rn], $amt",
3818 def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3819 (outs VecList:$Rt, GPR64xsp:$wb),
3820 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3821 asmop # "\t$Rt, [$Rn], $Rm",
3827 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
3828 Operand uimm_b, Operand uimm_h,
3829 Operand uimm_s, Operand uimm_d> {
3830 defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
3831 !cast<RegisterOperand>(List # "8B_operand"),
3834 defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
3835 !cast<RegisterOperand>(List # "4H_operand"),
3838 defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
3839 !cast<RegisterOperand>(List # "2S_operand"),
3842 defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
3843 !cast<RegisterOperand>(List # "1D_operand"),
3846 defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
3847 !cast<RegisterOperand>(List # "16B_operand"),
3850 defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
3851 !cast<RegisterOperand>(List # "8H_operand"),
3854 defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
3855 !cast<RegisterOperand>(List # "4S_operand"),
3858 defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
3859 !cast<RegisterOperand>(List # "2D_operand"),
3863 // Post-index load single 1-element structure to all lanes of 1 register
3864 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
3865 uimm_exact2, uimm_exact4, uimm_exact8>;
3867 // Post-index load single N-element structure to all lanes of N consecutive
3868 // registers (N = 2,3,4)
3869 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
3870 uimm_exact4, uimm_exact8, uimm_exact16>;
3871 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
3872 uimm_exact6, uimm_exact12, uimm_exact24>;
3873 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
3874 uimm_exact8, uimm_exact16, uimm_exact32>;
3876 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
3877 Constraints = "$Rn = $wb, $Rt = $src",
3878 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3879 class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3880 Operand ImmTy, Operand ImmOp, string asmop>
3881 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3882 (outs VList:$Rt, GPR64xsp:$wb),
3883 (ins GPR64xsp:$Rn, ImmTy:$amt,
3884 VList:$src, ImmOp:$lane),
3885 asmop # "\t$Rt[$lane], [$Rn], $amt",
3891 class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3892 Operand ImmTy, Operand ImmOp, string asmop>
3893 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3894 (outs VList:$Rt, GPR64xsp:$wb),
3895 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
3896 VList:$src, ImmOp:$lane),
3897 asmop # "\t$Rt[$lane], [$Rn], $Rm",
3902 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
3903 Operand uimm_b, Operand uimm_h,
3904 Operand uimm_s, Operand uimm_d> {
3905 def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
3906 !cast<RegisterOperand>(List # "B_operand"),
3907 uimm_b, neon_uimm4_bare, asmop> {
3908 let Inst{12-10} = lane{2-0};
3909 let Inst{30} = lane{3};
3912 def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
3913 !cast<RegisterOperand>(List # "B_operand"),
3914 uimm_b, neon_uimm4_bare, asmop> {
3915 let Inst{12-10} = lane{2-0};
3916 let Inst{30} = lane{3};
3919 def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
3920 !cast<RegisterOperand>(List # "H_operand"),
3921 uimm_h, neon_uimm3_bare, asmop> {
3922 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3923 let Inst{30} = lane{2};
3926 def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
3927 !cast<RegisterOperand>(List # "H_operand"),
3928 uimm_h, neon_uimm3_bare, asmop> {
3929 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3930 let Inst{30} = lane{2};
3933 def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3934 !cast<RegisterOperand>(List # "S_operand"),
3935 uimm_s, neon_uimm2_bare, asmop> {
3936 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3937 let Inst{30} = lane{1};
3940 def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
3941 !cast<RegisterOperand>(List # "S_operand"),
3942 uimm_s, neon_uimm2_bare, asmop> {
3943 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3944 let Inst{30} = lane{1};
3947 def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3948 !cast<RegisterOperand>(List # "D_operand"),
3949 uimm_d, neon_uimm1_bare, asmop> {
3950 let Inst{12-10} = 0b001;
3951 let Inst{30} = lane{0};
3954 def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
3955 !cast<RegisterOperand>(List # "D_operand"),
3956 uimm_d, neon_uimm1_bare, asmop> {
3957 let Inst{12-10} = 0b001;
3958 let Inst{30} = lane{0};
3962 // Post-index load single 1-element structure to one lane of 1 register.
3963 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
3964 uimm_exact2, uimm_exact4, uimm_exact8>;
3966 // Post-index load single N-element structure to one lane of N consecutive
3969 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
3970 uimm_exact4, uimm_exact8, uimm_exact16>;
3971 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
3972 uimm_exact6, uimm_exact12, uimm_exact24>;
3973 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
3974 uimm_exact8, uimm_exact16, uimm_exact32>;
3976 let mayStore = 1, neverHasSideEffects = 1,
3977 hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
3978 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3979 class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3980 Operand ImmTy, Operand ImmOp, string asmop>
3981 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
3982 (outs GPR64xsp:$wb),
3983 (ins GPR64xsp:$Rn, ImmTy:$amt,
3984 VList:$Rt, ImmOp:$lane),
3985 asmop # "\t$Rt[$lane], [$Rn], $amt",
3991 class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3992 Operand ImmTy, Operand ImmOp, string asmop>
3993 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
3994 (outs GPR64xsp:$wb),
3995 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
3997 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4002 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4003 Operand uimm_b, Operand uimm_h,
4004 Operand uimm_s, Operand uimm_d> {
4005 def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4006 !cast<RegisterOperand>(List # "B_operand"),
4007 uimm_b, neon_uimm4_bare, asmop> {
4008 let Inst{12-10} = lane{2-0};
4009 let Inst{30} = lane{3};
4012 def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4013 !cast<RegisterOperand>(List # "B_operand"),
4014 uimm_b, neon_uimm4_bare, asmop> {
4015 let Inst{12-10} = lane{2-0};
4016 let Inst{30} = lane{3};
4019 def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4020 !cast<RegisterOperand>(List # "H_operand"),
4021 uimm_h, neon_uimm3_bare, asmop> {
4022 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4023 let Inst{30} = lane{2};
4026 def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4027 !cast<RegisterOperand>(List # "H_operand"),
4028 uimm_h, neon_uimm3_bare, asmop> {
4029 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4030 let Inst{30} = lane{2};
4033 def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4034 !cast<RegisterOperand>(List # "S_operand"),
4035 uimm_s, neon_uimm2_bare, asmop> {
4036 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4037 let Inst{30} = lane{1};
4040 def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4041 !cast<RegisterOperand>(List # "S_operand"),
4042 uimm_s, neon_uimm2_bare, asmop> {
4043 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4044 let Inst{30} = lane{1};
4047 def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4048 !cast<RegisterOperand>(List # "D_operand"),
4049 uimm_d, neon_uimm1_bare, asmop> {
4050 let Inst{12-10} = 0b001;
4051 let Inst{30} = lane{0};
4054 def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4055 !cast<RegisterOperand>(List # "D_operand"),
4056 uimm_d, neon_uimm1_bare, asmop> {
4057 let Inst{12-10} = 0b001;
4058 let Inst{30} = lane{0};
4062 // Post-index store single 1-element structure from one lane of 1 register.
4063 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4064 uimm_exact2, uimm_exact4, uimm_exact8>;
4066 // Post-index store single N-element structure from one lane of N consecutive
4067 // registers (N = 2,3,4)
4068 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4069 uimm_exact4, uimm_exact8, uimm_exact16>;
4070 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4071 uimm_exact6, uimm_exact12, uimm_exact24>;
4072 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4073 uimm_exact8, uimm_exact16, uimm_exact32>;
4075 // End of post-index load/store single N-element instructions
4076 // (class SIMD lsone-post)
4078 // Neon Scalar instructions implementation
4079 // Scalar Three Same
4081 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4083 : NeonI_Scalar3Same<u, size, opcode,
4084 (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4085 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4089 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4090 : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4092 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4093 bit Commutable = 0> {
4094 let isCommutable = Commutable in {
4095 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4096 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4100 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4101 string asmop, bit Commutable = 0> {
4102 let isCommutable = Commutable in {
4103 def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4104 def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4108 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4109 string asmop, bit Commutable = 0> {
4110 let isCommutable = Commutable in {
4111 def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4112 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4113 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4114 def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4118 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4119 Instruction INSTD> {
4120 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4121 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4124 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4129 : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4130 def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4131 (INSTB FPR8:$Rn, FPR8:$Rm)>;
4133 def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4134 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4136 def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4137 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4140 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
4142 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4143 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4145 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4147 Instruction INSTS> {
4148 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4149 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4150 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4151 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4154 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4156 Instruction INSTD> {
4157 def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4158 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4159 def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4160 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4163 multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
4165 Instruction INSTD> {
4166 def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4167 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4168 def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4169 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4172 class Neon_Scalar3Same_cmp_V1_D_size_patterns<CondCode CC,
4174 : Pat<(v1i64 (Neon_cmp (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm), CC)),
4175 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4177 // Scalar Three Different
4179 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4180 RegisterClass FPRCD, RegisterClass FPRCS>
4181 : NeonI_Scalar3Diff<u, size, opcode,
4182 (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4183 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4187 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4188 def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4189 def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4192 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4193 let Constraints = "$Src = $Rd" in {
4194 def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4195 (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4196 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4199 def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4200 (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4201 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4207 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4209 Instruction INSTS> {
4210 def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4211 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4212 def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4213 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4216 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4218 Instruction INSTS> {
4219 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4220 (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4221 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4222 (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4225 // Scalar Two Registers Miscellaneous
4227 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4228 RegisterClass FPRCD, RegisterClass FPRCS>
4229 : NeonI_Scalar2SameMisc<u, size, opcode,
4230 (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4231 !strconcat(asmop, "\t$Rd, $Rn"),
4235 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4237 def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4239 def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4243 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4244 def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4247 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4248 : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4249 def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4250 def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4251 def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4254 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4255 : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4257 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4259 def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4260 def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4261 def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4264 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4265 string asmop, RegisterClass FPRC>
4266 : NeonI_Scalar2SameMisc<u, size, opcode,
4267 (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4268 !strconcat(asmop, "\t$Rd, $Rn"),
4272 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4275 let Constraints = "$Src = $Rd" in {
4276 def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4277 def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4278 def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4279 def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4283 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4285 : Pat<(v1f32 (opnode (v1f64 FPR64:$Rn))),
4288 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4290 Instruction INSTD> {
4291 def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn))),
4293 def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4297 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator Sopnode,
4298 SDPatternOperator Dopnode,
4300 Instruction INSTD> {
4301 def : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn))),
4303 def : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn))),
4307 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4309 Instruction INSTD> {
4310 def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn))),
4312 def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4316 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4317 : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4318 (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4319 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4323 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4325 def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4326 (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4327 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4330 def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4331 (outs FPR64:$Rd), (ins FPR64:$Rn, fpz32:$FPImm),
4332 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4337 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4339 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4340 (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4341 (INSTD FPR64:$Rn, 0)>;
4343 class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
4345 : Pat<(v1i64 (Neon_cmpz (v1i64 FPR64:$Rn),
4346 (i32 neon_uimm0:$Imm), CC)),
4347 (INSTD FPR64:$Rn, neon_uimm0:$Imm)>;
4349 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4351 Instruction INSTD> {
4352 def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
4353 (v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),
4354 (INSTS FPR32:$Rn, fpz32:$FPImm)>;
4355 def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
4356 (v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),
4357 (INSTD FPR64:$Rn, fpz32:$FPImm)>;
4360 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4361 Instruction INSTD> {
4362 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4366 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4371 : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4372 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4374 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4376 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4380 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4381 SDPatternOperator opnode,
4384 Instruction INSTD> {
4385 def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4387 def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4389 def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4394 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4395 SDPatternOperator opnode,
4399 Instruction INSTD> {
4400 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4401 (INSTB FPR8:$Src, FPR8:$Rn)>;
4402 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4403 (INSTH FPR16:$Src, FPR16:$Rn)>;
4404 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4405 (INSTS FPR32:$Src, FPR32:$Rn)>;
4406 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4407 (INSTD FPR64:$Src, FPR64:$Rn)>;
4410 // Scalar Shift By Immediate
4412 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4413 RegisterClass FPRC, Operand ImmTy>
4414 : NeonI_ScalarShiftImm<u, opcode,
4415 (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4416 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4419 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4421 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4423 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4424 let Inst{21-16} = Imm;
4428 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4430 : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4431 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4433 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4434 let Inst{18-16} = Imm;
4436 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4438 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4439 let Inst{19-16} = Imm;
4441 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4443 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4444 let Inst{20-16} = Imm;
4448 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4450 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4452 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4453 let Inst{21-16} = Imm;
4457 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4459 : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4460 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4462 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4463 let Inst{18-16} = Imm;
4465 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4467 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4468 let Inst{19-16} = Imm;
4470 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4472 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4473 let Inst{20-16} = Imm;
4477 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4478 : NeonI_ScalarShiftImm<u, opcode,
4480 (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4481 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4484 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4485 let Inst{21-16} = Imm;
4486 let Constraints = "$Src = $Rd";
4489 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4490 : NeonI_ScalarShiftImm<u, opcode,
4492 (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4493 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4496 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4497 let Inst{21-16} = Imm;
4498 let Constraints = "$Src = $Rd";
4501 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4502 RegisterClass FPRCD, RegisterClass FPRCS,
4504 : NeonI_ScalarShiftImm<u, opcode,
4505 (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4506 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4509 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4511 def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4514 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4515 let Inst{18-16} = Imm;
4517 def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4520 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4521 let Inst{19-16} = Imm;
4523 def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4526 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4527 let Inst{20-16} = Imm;
4531 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4532 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4534 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4535 let Inst{20-16} = Imm;
4537 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4539 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4540 let Inst{21-16} = Imm;
4544 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4545 Instruction INSTD> {
4546 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4547 (INSTD FPR64:$Rn, imm:$Imm)>;
4550 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4551 Instruction INSTD> {
4552 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4553 (INSTD FPR64:$Rn, imm:$Imm)>;
4556 class Neon_ScalarShiftImm_arm_D_size_patterns<SDPatternOperator opnode,
4558 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4559 (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4560 (INSTD FPR64:$Rn, imm:$Imm)>;
4562 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4567 : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4568 def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4569 (INSTB FPR8:$Rn, imm:$Imm)>;
4570 def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4571 (INSTH FPR16:$Rn, imm:$Imm)>;
4572 def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4573 (INSTS FPR32:$Rn, imm:$Imm)>;
4576 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4578 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4579 (i32 shl_imm64:$Imm))),
4580 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4582 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4584 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4585 (i32 shr_imm64:$Imm))),
4586 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4588 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4589 SDPatternOperator opnode,
4592 Instruction INSTD> {
4593 def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4594 (INSTH FPR16:$Rn, imm:$Imm)>;
4595 def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4596 (INSTS FPR32:$Rn, imm:$Imm)>;
4597 def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4598 (INSTD FPR64:$Rn, imm:$Imm)>;
4601 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator Sopnode,
4602 SDPatternOperator Dopnode,
4604 Instruction INSTD> {
4605 def ssi : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4606 (INSTS FPR32:$Rn, imm:$Imm)>;
4607 def ddi : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4608 (INSTD FPR64:$Rn, imm:$Imm)>;
4611 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator Sopnode,
4612 SDPatternOperator Dopnode,
4614 Instruction INSTD> {
4615 def ssi : Pat<(v1i32 (Sopnode (v1f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4616 (INSTS FPR32:$Rn, imm:$Imm)>;
4617 def ddi : Pat<(v1i64 (Dopnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4618 (INSTD FPR64:$Rn, imm:$Imm)>;
4621 // Scalar Signed Shift Right (Immediate)
4622 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4623 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4624 // Pattern to match llvm.arm.* intrinsic.
4625 def : Neon_ScalarShiftImm_arm_D_size_patterns<sra, SSHRddi>;
4627 // Scalar Unsigned Shift Right (Immediate)
4628 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4629 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4630 // Pattern to match llvm.arm.* intrinsic.
4631 def : Neon_ScalarShiftImm_arm_D_size_patterns<srl, USHRddi>;
4633 // Scalar Signed Rounding Shift Right (Immediate)
4634 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4635 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4637 // Scalar Unigned Rounding Shift Right (Immediate)
4638 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4639 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4641 // Scalar Signed Shift Right and Accumulate (Immediate)
4642 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4643 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4644 <int_aarch64_neon_vsrads_n, SSRA>;
4646 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4647 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4648 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4649 <int_aarch64_neon_vsradu_n, USRA>;
4651 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4652 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4653 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4654 <int_aarch64_neon_vrsrads_n, SRSRA>;
4656 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4657 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4658 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4659 <int_aarch64_neon_vrsradu_n, URSRA>;
4661 // Scalar Shift Left (Immediate)
4662 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4663 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4664 // Pattern to match llvm.arm.* intrinsic.
4665 def : Neon_ScalarShiftImm_arm_D_size_patterns<shl, SHLddi>;
4667 // Signed Saturating Shift Left (Immediate)
4668 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4669 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4671 SQSHLssi, SQSHLddi>;
4672 // Pattern to match llvm.arm.* intrinsic.
4673 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4675 // Unsigned Saturating Shift Left (Immediate)
4676 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4677 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4679 UQSHLssi, UQSHLddi>;
4680 // Pattern to match llvm.arm.* intrinsic.
4681 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4683 // Signed Saturating Shift Left Unsigned (Immediate)
4684 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4685 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4686 SQSHLUbbi, SQSHLUhhi,
4687 SQSHLUssi, SQSHLUddi>;
4689 // Shift Right And Insert (Immediate)
4690 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4691 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4692 <int_aarch64_neon_vsri, SRI>;
4694 // Shift Left And Insert (Immediate)
4695 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4696 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4697 <int_aarch64_neon_vsli, SLI>;
4699 // Signed Saturating Shift Right Narrow (Immediate)
4700 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4701 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4702 SQSHRNbhi, SQSHRNhsi,
4705 // Unsigned Saturating Shift Right Narrow (Immediate)
4706 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4707 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4708 UQSHRNbhi, UQSHRNhsi,
4711 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4712 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4713 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4714 SQRSHRNbhi, SQRSHRNhsi,
4717 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4718 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4719 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4720 UQRSHRNbhi, UQRSHRNhsi,
4723 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4724 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4725 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4726 SQSHRUNbhi, SQSHRUNhsi,
4729 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4730 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4731 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4732 SQRSHRUNbhi, SQRSHRUNhsi,
4735 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4736 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4737 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_s32,
4738 int_aarch64_neon_vcvtf64_n_s64,
4739 SCVTF_Nssi, SCVTF_Nddi>;
4741 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4742 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4743 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_u32,
4744 int_aarch64_neon_vcvtf64_n_u64,
4745 UCVTF_Nssi, UCVTF_Nddi>;
4747 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4748 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4749 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_s32_f32,
4750 int_aarch64_neon_vcvtd_n_s64_f64,
4751 FCVTZS_Nssi, FCVTZS_Nddi>;
4753 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4754 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4755 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_u32_f32,
4756 int_aarch64_neon_vcvtd_n_u64_f64,
4757 FCVTZU_Nssi, FCVTZU_Nddi>;
4759 // Patterns For Convert Instructions Between v1f64 and v1i64
4760 class Neon_ScalarShiftImm_cvtf_v1f64_pattern<SDPatternOperator opnode,
4762 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4763 (INST FPR64:$Rn, imm:$Imm)>;
4765 class Neon_ScalarShiftImm_fcvt_v1f64_pattern<SDPatternOperator opnode,
4767 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4768 (INST FPR64:$Rn, imm:$Imm)>;
4770 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxs2fp,
4773 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxu2fp,
4776 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxs,
4779 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxu,
4782 // Scalar Integer Add
4783 let isCommutable = 1 in {
4784 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4787 // Scalar Integer Sub
4788 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4790 // Pattern for Scalar Integer Add and Sub with D register only
4791 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4792 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4794 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4795 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4796 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4797 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4798 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4800 // Scalar Integer Saturating Add (Signed, Unsigned)
4801 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4802 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4804 // Scalar Integer Saturating Sub (Signed, Unsigned)
4805 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4806 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4809 // Patterns to match llvm.aarch64.* intrinsic for
4810 // Scalar Integer Saturating Add, Sub (Signed, Unsigned)
4811 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
4812 SQADDhhh, SQADDsss, SQADDddd>;
4813 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
4814 UQADDhhh, UQADDsss, UQADDddd>;
4815 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
4816 SQSUBhhh, SQSUBsss, SQSUBddd>;
4817 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
4818 UQSUBhhh, UQSUBsss, UQSUBddd>;
4820 // Scalar Integer Saturating Doubling Multiply Half High
4821 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
4823 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4824 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
4826 // Patterns to match llvm.arm.* intrinsic for
4827 // Scalar Integer Saturating Doubling Multiply Half High and
4828 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4829 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
4831 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
4834 // Scalar Floating-point Multiply Extended
4835 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
4837 // Scalar Floating-point Reciprocal Step
4838 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
4840 // Scalar Floating-point Reciprocal Square Root Step
4841 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
4843 // Patterns to match llvm.arm.* intrinsic for
4844 // Scalar Floating-point Reciprocal Step and
4845 // Scalar Floating-point Reciprocal Square Root Step
4846 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss,
4848 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
4851 def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>;
4853 // Patterns to match llvm.aarch64.* intrinsic for
4854 // Scalar Floating-point Multiply Extended,
4855 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
4857 Instruction INSTD> {
4858 def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4859 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4860 def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4861 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4864 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
4867 // Scalar Integer Shift Left (Signed, Unsigned)
4868 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
4869 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
4871 // Patterns to match llvm.arm.* intrinsic for
4872 // Scalar Integer Shift Left (Signed, Unsigned)
4873 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
4874 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
4876 // Patterns to match llvm.aarch64.* intrinsic for
4877 // Scalar Integer Shift Left (Signed, Unsigned)
4878 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
4879 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
4881 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
4882 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
4883 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
4885 // Patterns to match llvm.aarch64.* intrinsic for
4886 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
4887 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
4888 SQSHLhhh, SQSHLsss, SQSHLddd>;
4889 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
4890 UQSHLhhh, UQSHLsss, UQSHLddd>;
4892 // Patterns to match llvm.arm.* intrinsic for
4893 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
4894 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
4895 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
4897 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4898 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
4899 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
4901 // Patterns to match llvm.aarch64.* intrinsic for
4902 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4903 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
4904 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
4906 // Patterns to match llvm.arm.* intrinsic for
4907 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4908 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
4909 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
4911 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4912 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
4913 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
4915 // Patterns to match llvm.aarch64.* intrinsic for
4916 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4917 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
4918 SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
4919 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
4920 UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
4922 // Patterns to match llvm.arm.* intrinsic for
4923 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4924 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
4925 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
4927 // Signed Saturating Doubling Multiply-Add Long
4928 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
4929 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
4930 SQDMLALshh, SQDMLALdss>;
4932 // Signed Saturating Doubling Multiply-Subtract Long
4933 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
4934 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
4935 SQDMLSLshh, SQDMLSLdss>;
4937 // Signed Saturating Doubling Multiply Long
4938 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
4939 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
4940 SQDMULLshh, SQDMULLdss>;
4942 // Scalar Signed Integer Convert To Floating-point
4943 defm SCVTF : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
4944 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,
4945 int_aarch64_neon_vcvtf64_s64,
4948 // Scalar Unsigned Integer Convert To Floating-point
4949 defm UCVTF : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
4950 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_u32,
4951 int_aarch64_neon_vcvtf64_u64,
4954 // Scalar Floating-point Converts
4955 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
4956 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
4959 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
4960 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
4961 FCVTNSss, FCVTNSdd>;
4963 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
4964 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
4965 FCVTNUss, FCVTNUdd>;
4967 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
4968 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
4969 FCVTMSss, FCVTMSdd>;
4971 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
4972 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
4973 FCVTMUss, FCVTMUdd>;
4975 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
4976 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
4977 FCVTASss, FCVTASdd>;
4979 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
4980 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
4981 FCVTAUss, FCVTAUdd>;
4983 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
4984 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
4985 FCVTPSss, FCVTPSdd>;
4987 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
4988 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
4989 FCVTPUss, FCVTPUdd>;
4991 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
4992 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
4993 FCVTZSss, FCVTZSdd>;
4995 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
4996 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
4997 FCVTZUss, FCVTZUdd>;
4999 // Patterns For Convert Instructions Between v1f64 and v1i64
5000 class Neon_Scalar2SameMisc_cvtf_v1f64_pattern<SDPatternOperator opnode,
5002 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5004 class Neon_Scalar2SameMisc_fcvt_v1f64_pattern<SDPatternOperator opnode,
5006 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5008 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<sint_to_fp, SCVTFdd>;
5009 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<uint_to_fp, UCVTFdd>;
5011 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_sint, FCVTZSdd>;
5012 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_uint, FCVTZUdd>;
5014 // Scalar Floating-point Reciprocal Estimate
5015 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5016 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrecpe,
5017 FRECPEss, FRECPEdd>;
5019 // Scalar Floating-point Reciprocal Exponent
5020 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5021 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5022 FRECPXss, FRECPXdd>;
5024 // Scalar Floating-point Reciprocal Square Root Estimate
5025 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5026 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrsqrte,
5027 FRSQRTEss, FRSQRTEdd>;
5029 // Scalar Floating-point Round
5030 class Neon_ScalarFloatRound_pattern<SDPatternOperator opnode, Instruction INST>
5031 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5033 def : Neon_ScalarFloatRound_pattern<fceil, FRINTPdd>;
5034 def : Neon_ScalarFloatRound_pattern<ffloor, FRINTMdd>;
5035 def : Neon_ScalarFloatRound_pattern<ftrunc, FRINTZdd>;
5036 def : Neon_ScalarFloatRound_pattern<frint, FRINTXdd>;
5037 def : Neon_ScalarFloatRound_pattern<fnearbyint, FRINTIdd>;
5038 def : Neon_ScalarFloatRound_pattern<frnd, FRINTAdd>;
5039 def : Neon_ScalarFloatRound_pattern<int_aarch64_neon_frintn, FRINTNdd>;
5041 // Scalar Integer Compare
5043 // Scalar Compare Bitwise Equal
5044 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5045 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5047 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5050 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5051 (INSTD FPR64:$Rn, FPR64:$Rm)>;
5053 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5055 // Scalar Compare Signed Greather Than Or Equal
5056 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5057 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5058 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGEddd, SETGE>;
5060 // Scalar Compare Unsigned Higher Or Same
5061 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5062 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5063 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHSddd, SETUGE>;
5065 // Scalar Compare Unsigned Higher
5066 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5067 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5068 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHIddd, SETUGT>;
5070 // Scalar Compare Signed Greater Than
5071 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5072 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5073 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGTddd, SETGT>;
5075 // Scalar Compare Bitwise Test Bits
5076 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5077 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5078 def : Neon_Scalar3Same_cmp_D_size_patterns<Neon_tst, CMTSTddd>;
5080 // Scalar Compare Bitwise Equal To Zero
5081 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5082 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5084 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETEQ, CMEQddi>;
5086 // Scalar Compare Signed Greather Than Or Equal To Zero
5087 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5088 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5090 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGE, CMGEddi>;
5092 // Scalar Compare Signed Greater Than Zero
5093 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5094 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5096 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGT, CMGTddi>;
5098 // Scalar Compare Signed Less Than Or Equal To Zero
5099 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5100 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5102 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLE, CMLEddi>;
5104 // Scalar Compare Less Than Zero
5105 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5106 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5108 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
5110 // Scalar Floating-point Compare
5112 // Scalar Floating-point Compare Mask Equal
5113 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5114 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vceq,
5115 FCMEQsss, FCMEQddd>;
5116 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
5118 // Scalar Floating-point Compare Mask Equal To Zero
5119 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5120 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
5121 FCMEQZssi, FCMEQZddi>;
5122 def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpz32:$FPImm), SETEQ)),
5123 (FCMEQZddi FPR64:$Rn, fpz32:$FPImm)>;
5125 // Scalar Floating-point Compare Mask Greater Than Or Equal
5126 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5127 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcge,
5128 FCMGEsss, FCMGEddd>;
5129 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
5131 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5132 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5133 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcge,
5134 FCMGEZssi, FCMGEZddi>;
5136 // Scalar Floating-point Compare Mask Greather Than
5137 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5138 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcgt,
5139 FCMGTsss, FCMGTddd>;
5140 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
5142 // Scalar Floating-point Compare Mask Greather Than Zero
5143 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5144 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcgt,
5145 FCMGTZssi, FCMGTZddi>;
5147 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5148 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5149 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vclez,
5150 FCMLEZssi, FCMLEZddi>;
5152 // Scalar Floating-point Compare Mask Less Than Zero
5153 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5154 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcltz,
5155 FCMLTZssi, FCMLTZddi>;
5157 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5158 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5159 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcage,
5160 FACGEsss, FACGEddd>;
5162 // Scalar Floating-point Absolute Compare Mask Greater Than
5163 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5164 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcagt,
5165 FACGTsss, FACGTddd>;
5167 // Scakar Floating-point Absolute Difference
5168 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5169 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vabd,
5172 // Scalar Absolute Value
5173 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5174 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5176 // Scalar Signed Saturating Absolute Value
5177 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5178 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5179 SQABSbb, SQABShh, SQABSss, SQABSdd>;
5182 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5183 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5185 // Scalar Signed Saturating Negate
5186 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5187 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5188 SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5190 // Scalar Signed Saturating Accumulated of Unsigned Value
5191 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5192 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5194 SUQADDss, SUQADDdd>;
5196 // Scalar Unsigned Saturating Accumulated of Signed Value
5197 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5198 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5200 USQADDss, USQADDdd>;
5202 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5203 (v1i64 FPR64:$Rn))),
5204 (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5206 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5207 (v1i64 FPR64:$Rn))),
5208 (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5210 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5213 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5214 (SQABSdd FPR64:$Rn)>;
5216 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5217 (SQNEGdd FPR64:$Rn)>;
5219 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5220 (v1i64 FPR64:$Rn))),
5223 // Scalar Signed Saturating Extract Unsigned Narrow
5224 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5225 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5229 // Scalar Signed Saturating Extract Narrow
5230 defm SQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5231 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5235 // Scalar Unsigned Saturating Extract Narrow
5236 defm UQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5237 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5241 // Scalar Reduce Pairwise
5243 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5244 string asmop, bit Commutable = 0> {
5245 let isCommutable = Commutable in {
5246 def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5247 (outs FPR64:$Rd), (ins VPR128:$Rn),
5248 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5254 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5255 string asmop, bit Commutable = 0>
5256 : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5257 let isCommutable = Commutable in {
5258 def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5259 (outs FPR32:$Rd), (ins VPR64:$Rn),
5260 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5266 // Scalar Reduce Addition Pairwise (Integer) with
5267 // Pattern to match llvm.arm.* intrinsic
5268 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5270 // Pattern to match llvm.aarch64.* intrinsic for
5271 // Scalar Reduce Addition Pairwise (Integer)
5272 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5273 (ADDPvv_D_2D VPR128:$Rn)>;
5274 def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
5275 (ADDPvv_D_2D VPR128:$Rn)>;
5277 // Scalar Reduce Addition Pairwise (Floating Point)
5278 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5280 // Scalar Reduce Maximum Pairwise (Floating Point)
5281 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5283 // Scalar Reduce Minimum Pairwise (Floating Point)
5284 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5286 // Scalar Reduce maxNum Pairwise (Floating Point)
5287 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5289 // Scalar Reduce minNum Pairwise (Floating Point)
5290 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5292 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnodeS,
5293 SDPatternOperator opnodeD,
5295 Instruction INSTD> {
5296 def : Pat<(v1f32 (opnodeS (v2f32 VPR64:$Rn))),
5298 def : Pat<(v1f64 (opnodeD (v2f64 VPR128:$Rn))),
5299 (INSTD VPR128:$Rn)>;
5302 // Patterns to match llvm.aarch64.* intrinsic for
5303 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5304 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5305 int_aarch64_neon_vpfaddq, FADDPvv_S_2S, FADDPvv_D_2D>;
5307 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5308 int_aarch64_neon_vpmaxq, FMAXPvv_S_2S, FMAXPvv_D_2D>;
5310 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5311 int_aarch64_neon_vpminq, FMINPvv_S_2S, FMINPvv_D_2D>;
5313 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5314 int_aarch64_neon_vpfmaxnmq, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5316 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5317 int_aarch64_neon_vpfminnmq, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5319 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vaddv,
5320 int_aarch64_neon_vaddv, FADDPvv_S_2S, FADDPvv_D_2D>;
5322 def : Pat<(v1f32 (int_aarch64_neon_vaddv (v4f32 VPR128:$Rn))),
5323 (FADDPvv_S_2S (v2f32
5325 (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
5328 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vmaxv,
5329 int_aarch64_neon_vmaxv, FMAXPvv_S_2S, FMAXPvv_D_2D>;
5331 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vminv,
5332 int_aarch64_neon_vminv, FMINPvv_S_2S, FMINPvv_D_2D>;
5334 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vmaxnmv,
5335 int_aarch64_neon_vmaxnmv, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5337 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vminnmv,
5338 int_aarch64_neon_vminnmv, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5340 // Scalar by element Arithmetic
5342 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5343 string rmlane, bit u, bit szhi, bit szlo,
5344 RegisterClass ResFPR, RegisterClass OpFPR,
5345 RegisterOperand OpVPR, Operand OpImm>
5346 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5348 (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5349 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5356 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5358 bit u, bit szhi, bit szlo,
5359 RegisterClass ResFPR,
5360 RegisterClass OpFPR,
5361 RegisterOperand OpVPR,
5363 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5365 (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5366 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5369 let Constraints = "$src = $Rd";
5374 // Scalar Floating Point multiply (scalar, by element)
5375 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5376 0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5377 let Inst{11} = Imm{1}; // h
5378 let Inst{21} = Imm{0}; // l
5379 let Inst{20-16} = MRm;
5381 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5382 0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5383 let Inst{11} = Imm{0}; // h
5384 let Inst{21} = 0b0; // l
5385 let Inst{20-16} = MRm;
5388 // Scalar Floating Point multiply extended (scalar, by element)
5389 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5390 0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5391 let Inst{11} = Imm{1}; // h
5392 let Inst{21} = Imm{0}; // l
5393 let Inst{20-16} = MRm;
5395 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5396 0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5397 let Inst{11} = Imm{0}; // h
5398 let Inst{21} = 0b0; // l
5399 let Inst{20-16} = MRm;
5402 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5403 SDPatternOperator opnode,
5405 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5406 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5408 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5409 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5410 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5412 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5413 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5414 (ResTy (INST (ResTy FPRC:$Rn),
5415 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5419 def : Pat<(ResTy (opnode
5420 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5422 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5424 def : Pat<(ResTy (opnode
5425 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5427 (ResTy (INST (ResTy FPRC:$Rn),
5428 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5432 // Patterns for Scalar Floating Point multiply (scalar, by element)
5433 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5434 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5435 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5436 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5438 // Patterns for Scalar Floating Point multiply extended (scalar, by element)
5439 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5440 FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5441 v2f32, v4f32, neon_uimm1_bare>;
5442 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5443 FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5444 v1f64, v2f64, neon_uimm0_bare>;
5447 // Scalar Floating Point fused multiply-add (scalar, by element)
5448 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5449 0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5450 let Inst{11} = Imm{1}; // h
5451 let Inst{21} = Imm{0}; // l
5452 let Inst{20-16} = MRm;
5454 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5455 0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5456 let Inst{11} = Imm{0}; // h
5457 let Inst{21} = 0b0; // l
5458 let Inst{20-16} = MRm;
5461 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5462 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5463 0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5464 let Inst{11} = Imm{1}; // h
5465 let Inst{21} = Imm{0}; // l
5466 let Inst{20-16} = MRm;
5468 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5469 0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5470 let Inst{11} = Imm{0}; // h
5471 let Inst{21} = 0b0; // l
5472 let Inst{20-16} = MRm;
5474 // We are allowed to match the fma instruction regardless of compile options.
5475 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5476 Instruction FMLAI, Instruction FMLSI,
5477 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5478 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5480 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5481 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5483 (ResTy (FMLAI (ResTy FPRC:$Ra),
5484 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5486 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5487 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5489 (ResTy (FMLAI (ResTy FPRC:$Ra),
5491 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5494 // swapped fmla operands
5495 def : Pat<(ResTy (fma
5496 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5499 (ResTy (FMLAI (ResTy FPRC:$Ra),
5500 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5502 def : Pat<(ResTy (fma
5503 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5506 (ResTy (FMLAI (ResTy FPRC:$Ra),
5508 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5512 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5513 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5515 (ResTy (FMLSI (ResTy FPRC:$Ra),
5516 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5518 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5519 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5521 (ResTy (FMLSI (ResTy FPRC:$Ra),
5523 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5526 // swapped fmls operands
5527 def : Pat<(ResTy (fma
5528 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5531 (ResTy (FMLSI (ResTy FPRC:$Ra),
5532 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5534 def : Pat<(ResTy (fma
5535 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5538 (ResTy (FMLSI (ResTy FPRC:$Ra),
5540 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5544 // Scalar Floating Point fused multiply-add and
5545 // multiply-subtract (scalar, by element)
5546 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5547 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5548 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5549 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5550 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5551 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5553 // Scalar Signed saturating doubling multiply long (scalar, by element)
5554 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5555 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5556 let Inst{11} = 0b0; // h
5557 let Inst{21} = Imm{1}; // l
5558 let Inst{20} = Imm{0}; // m
5559 let Inst{19-16} = MRm{3-0};
5561 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5562 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5563 let Inst{11} = Imm{2}; // h
5564 let Inst{21} = Imm{1}; // l
5565 let Inst{20} = Imm{0}; // m
5566 let Inst{19-16} = MRm{3-0};
5568 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5569 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5570 let Inst{11} = 0b0; // h
5571 let Inst{21} = Imm{0}; // l
5572 let Inst{20-16} = MRm;
5574 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5575 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5576 let Inst{11} = Imm{1}; // h
5577 let Inst{21} = Imm{0}; // l
5578 let Inst{20-16} = MRm;
5581 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5582 SDPatternOperator opnode,
5584 ValueType ResTy, RegisterClass FPRC,
5585 ValueType OpVTy, ValueType OpTy,
5586 ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5588 def : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5589 (OpVTy (scalar_to_vector
5590 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5591 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5594 def : Pat<(ResTy (opnode
5595 (OpVTy (scalar_to_vector
5596 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5598 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5602 // Patterns for Scalar Signed saturating doubling
5603 // multiply long (scalar, by element)
5604 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5605 SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5606 i32, VPR64Lo, neon_uimm2_bare>;
5607 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5608 SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5609 i32, VPR128Lo, neon_uimm3_bare>;
5610 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5611 SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5612 i32, VPR64Lo, neon_uimm1_bare>;
5613 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5614 SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5615 i32, VPR128Lo, neon_uimm2_bare>;
5617 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5618 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5619 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5620 let Inst{11} = 0b0; // h
5621 let Inst{21} = Imm{1}; // l
5622 let Inst{20} = Imm{0}; // m
5623 let Inst{19-16} = MRm{3-0};
5625 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5626 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5627 let Inst{11} = Imm{2}; // h
5628 let Inst{21} = Imm{1}; // l
5629 let Inst{20} = Imm{0}; // m
5630 let Inst{19-16} = MRm{3-0};
5632 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5633 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5634 let Inst{11} = 0b0; // h
5635 let Inst{21} = Imm{0}; // l
5636 let Inst{20-16} = MRm;
5638 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5639 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5640 let Inst{11} = Imm{1}; // h
5641 let Inst{21} = Imm{0}; // l
5642 let Inst{20-16} = MRm;
5645 // Scalar Signed saturating doubling
5646 // multiply-subtract long (scalar, by element)
5647 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5648 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5649 let Inst{11} = 0b0; // h
5650 let Inst{21} = Imm{1}; // l
5651 let Inst{20} = Imm{0}; // m
5652 let Inst{19-16} = MRm{3-0};
5654 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5655 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5656 let Inst{11} = Imm{2}; // h
5657 let Inst{21} = Imm{1}; // l
5658 let Inst{20} = Imm{0}; // m
5659 let Inst{19-16} = MRm{3-0};
5661 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5662 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5663 let Inst{11} = 0b0; // h
5664 let Inst{21} = Imm{0}; // l
5665 let Inst{20-16} = MRm;
5667 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5668 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5669 let Inst{11} = Imm{1}; // h
5670 let Inst{21} = Imm{0}; // l
5671 let Inst{20-16} = MRm;
5674 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5675 SDPatternOperator opnode,
5676 SDPatternOperator coreopnode,
5678 ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5680 ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5682 def : Pat<(ResTy (opnode
5683 (ResTy ResFPRC:$Ra),
5684 (ResTy (coreopnode (OpTy FPRC:$Rn),
5685 (OpTy (scalar_to_vector
5686 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5687 (ResTy (INST (ResTy ResFPRC:$Ra),
5688 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5691 def : Pat<(ResTy (opnode
5692 (ResTy ResFPRC:$Ra),
5694 (OpTy (scalar_to_vector
5695 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5696 (OpTy FPRC:$Rn))))),
5697 (ResTy (INST (ResTy ResFPRC:$Ra),
5698 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5701 // Patterns for Scalar Signed saturating
5702 // doubling multiply-add long (scalar, by element)
5703 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5704 int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5705 i32, VPR64Lo, neon_uimm2_bare>;
5706 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5707 int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5708 i32, VPR128Lo, neon_uimm3_bare>;
5709 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5710 int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5711 i32, VPR64Lo, neon_uimm1_bare>;
5712 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5713 int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5714 i32, VPR128Lo, neon_uimm2_bare>;
5716 // Patterns for Scalar Signed saturating
5717 // doubling multiply-sub long (scalar, by element)
5718 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5719 int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5720 i32, VPR64Lo, neon_uimm2_bare>;
5721 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5722 int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5723 i32, VPR128Lo, neon_uimm3_bare>;
5724 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5725 int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5726 i32, VPR64Lo, neon_uimm1_bare>;
5727 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5728 int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5729 i32, VPR128Lo, neon_uimm2_bare>;
5731 // Scalar general arithmetic operation
5732 class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
5734 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5736 class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
5738 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5739 (INST FPR64:$Rn, FPR64:$Rm)>;
5741 class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
5743 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
5744 (v1f64 FPR64:$Ra))),
5745 (INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
5747 def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
5748 def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
5749 def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
5750 def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
5751 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
5752 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
5753 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
5754 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
5755 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
5757 def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
5758 def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
5760 def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
5761 def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
5763 // Scalar Signed saturating doubling multiply returning
5764 // high half (scalar, by element)
5765 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5766 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5767 let Inst{11} = 0b0; // h
5768 let Inst{21} = Imm{1}; // l
5769 let Inst{20} = Imm{0}; // m
5770 let Inst{19-16} = MRm{3-0};
5772 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5773 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5774 let Inst{11} = Imm{2}; // h
5775 let Inst{21} = Imm{1}; // l
5776 let Inst{20} = Imm{0}; // m
5777 let Inst{19-16} = MRm{3-0};
5779 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5780 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5781 let Inst{11} = 0b0; // h
5782 let Inst{21} = Imm{0}; // l
5783 let Inst{20-16} = MRm;
5785 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5786 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5787 let Inst{11} = Imm{1}; // h
5788 let Inst{21} = Imm{0}; // l
5789 let Inst{20-16} = MRm;
5792 // Patterns for Scalar Signed saturating doubling multiply returning
5793 // high half (scalar, by element)
5794 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5795 SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5796 i32, VPR64Lo, neon_uimm2_bare>;
5797 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5798 SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5799 i32, VPR128Lo, neon_uimm3_bare>;
5800 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5801 SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5802 i32, VPR64Lo, neon_uimm1_bare>;
5803 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5804 SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5805 i32, VPR128Lo, neon_uimm2_bare>;
5807 // Scalar Signed saturating rounding doubling multiply
5808 // returning high half (scalar, by element)
5809 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5810 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5811 let Inst{11} = 0b0; // h
5812 let Inst{21} = Imm{1}; // l
5813 let Inst{20} = Imm{0}; // m
5814 let Inst{19-16} = MRm{3-0};
5816 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5817 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5818 let Inst{11} = Imm{2}; // h
5819 let Inst{21} = Imm{1}; // l
5820 let Inst{20} = Imm{0}; // m
5821 let Inst{19-16} = MRm{3-0};
5823 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5824 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5825 let Inst{11} = 0b0; // h
5826 let Inst{21} = Imm{0}; // l
5827 let Inst{20-16} = MRm;
5829 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5830 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5831 let Inst{11} = Imm{1}; // h
5832 let Inst{21} = Imm{0}; // l
5833 let Inst{20-16} = MRm;
5836 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5837 SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
5838 VPR64Lo, neon_uimm2_bare>;
5839 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5840 SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
5841 VPR128Lo, neon_uimm3_bare>;
5842 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5843 SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
5844 VPR64Lo, neon_uimm1_bare>;
5845 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5846 SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
5847 VPR128Lo, neon_uimm2_bare>;
5849 // Scalar Copy - DUP element to scalar
5850 class NeonI_Scalar_DUP<string asmop, string asmlane,
5851 RegisterClass ResRC, RegisterOperand VPRC,
5853 : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
5854 asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
5860 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
5861 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5863 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
5864 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5866 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
5867 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5869 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
5870 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5873 multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
5874 ValueType OpTy, Operand OpImm,
5875 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5876 def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5877 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5879 def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5881 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5885 // Patterns for vector extract of FP data using scalar DUP instructions
5886 defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
5887 v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5888 defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64,
5889 v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5891 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
5892 ValueType ResTy, ValueType OpTy,Operand OpLImm,
5893 ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
5895 def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
5896 (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
5898 def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
5900 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5904 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
5905 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
5906 v8i8, v16i8, neon_uimm3_bare>;
5907 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
5908 v4i16, v8i16, neon_uimm2_bare>;
5909 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
5910 v2i32, v4i32, neon_uimm1_bare>;
5912 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
5913 ValueType OpTy, ValueType ElemTy,
5914 Operand OpImm, ValueType OpNTy,
5915 ValueType ExTy, Operand OpNImm> {
5917 def : Pat<(ResTy (vector_insert (ResTy undef),
5918 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5919 (neon_uimm0_bare:$Imm))),
5920 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5922 def : Pat<(ResTy (vector_insert (ResTy undef),
5923 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5926 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5930 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
5931 ValueType OpTy, ValueType ElemTy,
5932 Operand OpImm, ValueType OpNTy,
5933 ValueType ExTy, Operand OpNImm> {
5935 def : Pat<(ResTy (scalar_to_vector
5936 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
5937 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5939 def : Pat<(ResTy (scalar_to_vector
5940 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
5942 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5946 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
5948 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5949 v1i64, v2i64, i64, neon_uimm1_bare,
5950 v1i64, v2i64, neon_uimm0_bare>;
5951 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
5952 v1i32, v4i32, i32, neon_uimm2_bare,
5953 v2i32, v4i32, neon_uimm1_bare>;
5954 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
5955 v1i16, v8i16, i32, neon_uimm3_bare,
5956 v4i16, v8i16, neon_uimm2_bare>;
5957 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
5958 v1i8, v16i8, i32, neon_uimm4_bare,
5959 v8i8, v16i8, neon_uimm3_bare>;
5960 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5961 v1f64, v2f64, f64, neon_uimm1_bare,
5962 v1f64, v2f64, neon_uimm0_bare>;
5963 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
5964 v1f32, v4f32, f32, neon_uimm2_bare,
5965 v2f32, v4f32, neon_uimm1_bare>;
5966 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
5967 v1i64, v2i64, i64, neon_uimm1_bare,
5968 v1i64, v2i64, neon_uimm0_bare>;
5969 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
5970 v1i32, v4i32, i32, neon_uimm2_bare,
5971 v2i32, v4i32, neon_uimm1_bare>;
5972 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
5973 v1i16, v8i16, i32, neon_uimm3_bare,
5974 v4i16, v8i16, neon_uimm2_bare>;
5975 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
5976 v1i8, v16i8, i32, neon_uimm4_bare,
5977 v8i8, v16i8, neon_uimm3_bare>;
5978 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
5979 v1f64, v2f64, f64, neon_uimm1_bare,
5980 v1f64, v2f64, neon_uimm0_bare>;
5981 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
5982 v1f32, v4f32, f32, neon_uimm2_bare,
5983 v2f32, v4f32, neon_uimm1_bare>;
5985 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
5986 Instruction DUPI, Operand OpImm,
5987 RegisterClass ResRC> {
5988 def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
5989 (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
5992 // Aliases for Scalar copy - DUP element (scalar)
5993 // FIXME: This is actually the preferred syntax but TableGen can't deal with
5994 // custom printing of aliases.
5995 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
5996 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
5997 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
5998 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
6000 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
6002 def : Pat<(ResTy (GetLow VPR128:$Rn)),
6003 (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
6004 def : Pat<(ResTy (GetHigh VPR128:$Rn)),
6005 (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
6008 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
6009 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
6010 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
6011 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
6012 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
6013 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
6015 //===----------------------------------------------------------------------===//
6016 // Non-Instruction Patterns
6017 //===----------------------------------------------------------------------===//
6019 // 64-bit vector bitcasts...
6021 def : Pat<(v1i64 (bitconvert (v8i8 VPR64:$src))), (v1i64 VPR64:$src)>;
6022 def : Pat<(v2f32 (bitconvert (v8i8 VPR64:$src))), (v2f32 VPR64:$src)>;
6023 def : Pat<(v2i32 (bitconvert (v8i8 VPR64:$src))), (v2i32 VPR64:$src)>;
6024 def : Pat<(v4i16 (bitconvert (v8i8 VPR64:$src))), (v4i16 VPR64:$src)>;
6026 def : Pat<(v1i64 (bitconvert (v4i16 VPR64:$src))), (v1i64 VPR64:$src)>;
6027 def : Pat<(v2i32 (bitconvert (v4i16 VPR64:$src))), (v2i32 VPR64:$src)>;
6028 def : Pat<(v2f32 (bitconvert (v4i16 VPR64:$src))), (v2f32 VPR64:$src)>;
6029 def : Pat<(v8i8 (bitconvert (v4i16 VPR64:$src))), (v8i8 VPR64:$src)>;
6031 def : Pat<(v1i64 (bitconvert (v2i32 VPR64:$src))), (v1i64 VPR64:$src)>;
6032 def : Pat<(v2f32 (bitconvert (v2i32 VPR64:$src))), (v2f32 VPR64:$src)>;
6033 def : Pat<(v4i16 (bitconvert (v2i32 VPR64:$src))), (v4i16 VPR64:$src)>;
6034 def : Pat<(v8i8 (bitconvert (v2i32 VPR64:$src))), (v8i8 VPR64:$src)>;
6036 def : Pat<(v1i64 (bitconvert (v2f32 VPR64:$src))), (v1i64 VPR64:$src)>;
6037 def : Pat<(v2i32 (bitconvert (v2f32 VPR64:$src))), (v2i32 VPR64:$src)>;
6038 def : Pat<(v4i16 (bitconvert (v2f32 VPR64:$src))), (v4i16 VPR64:$src)>;
6039 def : Pat<(v8i8 (bitconvert (v2f32 VPR64:$src))), (v8i8 VPR64:$src)>;
6041 def : Pat<(v2f32 (bitconvert (v1i64 VPR64:$src))), (v2f32 VPR64:$src)>;
6042 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6043 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6044 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6046 // ..and 128-bit vector bitcasts...
6048 def : Pat<(v2f64 (bitconvert (v16i8 VPR128:$src))), (v2f64 VPR128:$src)>;
6049 def : Pat<(v2i64 (bitconvert (v16i8 VPR128:$src))), (v2i64 VPR128:$src)>;
6050 def : Pat<(v4f32 (bitconvert (v16i8 VPR128:$src))), (v4f32 VPR128:$src)>;
6051 def : Pat<(v4i32 (bitconvert (v16i8 VPR128:$src))), (v4i32 VPR128:$src)>;
6052 def : Pat<(v8i16 (bitconvert (v16i8 VPR128:$src))), (v8i16 VPR128:$src)>;
6054 def : Pat<(v2f64 (bitconvert (v8i16 VPR128:$src))), (v2f64 VPR128:$src)>;
6055 def : Pat<(v2i64 (bitconvert (v8i16 VPR128:$src))), (v2i64 VPR128:$src)>;
6056 def : Pat<(v4i32 (bitconvert (v8i16 VPR128:$src))), (v4i32 VPR128:$src)>;
6057 def : Pat<(v4f32 (bitconvert (v8i16 VPR128:$src))), (v4f32 VPR128:$src)>;
6058 def : Pat<(v16i8 (bitconvert (v8i16 VPR128:$src))), (v16i8 VPR128:$src)>;
6060 def : Pat<(v2f64 (bitconvert (v4i32 VPR128:$src))), (v2f64 VPR128:$src)>;
6061 def : Pat<(v2i64 (bitconvert (v4i32 VPR128:$src))), (v2i64 VPR128:$src)>;
6062 def : Pat<(v4f32 (bitconvert (v4i32 VPR128:$src))), (v4f32 VPR128:$src)>;
6063 def : Pat<(v8i16 (bitconvert (v4i32 VPR128:$src))), (v8i16 VPR128:$src)>;
6064 def : Pat<(v16i8 (bitconvert (v4i32 VPR128:$src))), (v16i8 VPR128:$src)>;
6066 def : Pat<(v2f64 (bitconvert (v4f32 VPR128:$src))), (v2f64 VPR128:$src)>;
6067 def : Pat<(v2i64 (bitconvert (v4f32 VPR128:$src))), (v2i64 VPR128:$src)>;
6068 def : Pat<(v4i32 (bitconvert (v4f32 VPR128:$src))), (v4i32 VPR128:$src)>;
6069 def : Pat<(v8i16 (bitconvert (v4f32 VPR128:$src))), (v8i16 VPR128:$src)>;
6070 def : Pat<(v16i8 (bitconvert (v4f32 VPR128:$src))), (v16i8 VPR128:$src)>;
6072 def : Pat<(v2f64 (bitconvert (v2i64 VPR128:$src))), (v2f64 VPR128:$src)>;
6073 def : Pat<(v4f32 (bitconvert (v2i64 VPR128:$src))), (v4f32 VPR128:$src)>;
6074 def : Pat<(v4i32 (bitconvert (v2i64 VPR128:$src))), (v4i32 VPR128:$src)>;
6075 def : Pat<(v8i16 (bitconvert (v2i64 VPR128:$src))), (v8i16 VPR128:$src)>;
6076 def : Pat<(v16i8 (bitconvert (v2i64 VPR128:$src))), (v16i8 VPR128:$src)>;
6078 def : Pat<(v2i64 (bitconvert (v2f64 VPR128:$src))), (v2i64 VPR128:$src)>;
6079 def : Pat<(v4f32 (bitconvert (v2f64 VPR128:$src))), (v4f32 VPR128:$src)>;
6080 def : Pat<(v4i32 (bitconvert (v2f64 VPR128:$src))), (v4i32 VPR128:$src)>;
6081 def : Pat<(v8i16 (bitconvert (v2f64 VPR128:$src))), (v8i16 VPR128:$src)>;
6082 def : Pat<(v16i8 (bitconvert (v2f64 VPR128:$src))), (v16i8 VPR128:$src)>;
6085 // ...and scalar bitcasts...
6086 def : Pat<(f16 (bitconvert (v1i16 FPR16:$src))), (f16 FPR16:$src)>;
6087 def : Pat<(f32 (bitconvert (v1i32 FPR32:$src))), (f32 FPR32:$src)>;
6088 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
6089 def : Pat<(f32 (bitconvert (v1f32 FPR32:$src))), (f32 FPR32:$src)>;
6090 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
6092 def : Pat<(i64 (bitconvert (v1i64 FPR64:$src))), (FMOVxd $src)>;
6093 def : Pat<(i64 (bitconvert (v1f64 FPR64:$src))), (FMOVxd $src)>;
6094 def : Pat<(i64 (bitconvert (v2i32 FPR64:$src))), (FMOVxd $src)>;
6095 def : Pat<(i64 (bitconvert (v2f32 FPR64:$src))), (FMOVxd $src)>;
6096 def : Pat<(i64 (bitconvert (v4i16 FPR64:$src))), (FMOVxd $src)>;
6097 def : Pat<(i64 (bitconvert (v8i8 FPR64:$src))), (FMOVxd $src)>;
6099 def : Pat<(i32 (bitconvert (v1i32 FPR32:$src))), (FMOVws $src)>;
6101 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6102 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6103 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6105 def : Pat<(f64 (bitconvert (v8i8 VPR64:$src))), (f64 VPR64:$src)>;
6106 def : Pat<(f64 (bitconvert (v4i16 VPR64:$src))), (f64 VPR64:$src)>;
6107 def : Pat<(f64 (bitconvert (v2i32 VPR64:$src))), (f64 VPR64:$src)>;
6108 def : Pat<(f64 (bitconvert (v2f32 VPR64:$src))), (f64 VPR64:$src)>;
6109 def : Pat<(f64 (bitconvert (v1i64 VPR64:$src))), (f64 VPR64:$src)>;
6111 def : Pat<(f128 (bitconvert (v16i8 VPR128:$src))), (f128 VPR128:$src)>;
6112 def : Pat<(f128 (bitconvert (v8i16 VPR128:$src))), (f128 VPR128:$src)>;
6113 def : Pat<(f128 (bitconvert (v4i32 VPR128:$src))), (f128 VPR128:$src)>;
6114 def : Pat<(f128 (bitconvert (v2i64 VPR128:$src))), (f128 VPR128:$src)>;
6115 def : Pat<(f128 (bitconvert (v4f32 VPR128:$src))), (f128 VPR128:$src)>;
6116 def : Pat<(f128 (bitconvert (v2f64 VPR128:$src))), (f128 VPR128:$src)>;
6118 def : Pat<(v1i16 (bitconvert (f16 FPR16:$src))), (v1i16 FPR16:$src)>;
6119 def : Pat<(v1i32 (bitconvert (f32 FPR32:$src))), (v1i32 FPR32:$src)>;
6120 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6121 def : Pat<(v1f32 (bitconvert (f32 FPR32:$src))), (v1f32 FPR32:$src)>;
6122 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
6124 def : Pat<(v1i64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6125 def : Pat<(v1f64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6126 def : Pat<(v2i32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6127 def : Pat<(v2f32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6128 def : Pat<(v4i16 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6129 def : Pat<(v8i8 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6131 def : Pat<(v1i32 (bitconvert (i32 GPR32:$src))), (FMOVsw $src)>;
6133 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
6134 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
6135 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
6136 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
6137 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6139 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
6140 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
6141 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
6142 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
6143 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
6144 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
6146 // Scalar Three Same
6148 def neon_uimm3 : Operand<i64>,
6149 ImmLeaf<i64, [{return Imm < 8;}]> {
6150 let ParserMatchClass = uimm3_asmoperand;
6151 let PrintMethod = "printUImmHexOperand";
6154 def neon_uimm4 : Operand<i64>,
6155 ImmLeaf<i64, [{return Imm < 16;}]> {
6156 let ParserMatchClass = uimm4_asmoperand;
6157 let PrintMethod = "printUImmHexOperand";
6161 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6162 string OpS, RegisterOperand OpVPR, Operand OpImm>
6163 : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6164 (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6165 asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6166 ", $Rm." # OpS # ", $Index",
6172 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6173 VPR64, neon_uimm3> {
6174 let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6177 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6178 VPR128, neon_uimm4> {
6179 let Inst{14-11} = Index;
6182 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6184 : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6186 (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6188 def : NI_Extract<v8i8, VPR64, EXTvvvi_8b, neon_uimm3>;
6189 def : NI_Extract<v4i16, VPR64, EXTvvvi_8b, neon_uimm3>;
6190 def : NI_Extract<v2i32, VPR64, EXTvvvi_8b, neon_uimm3>;
6191 def : NI_Extract<v1i64, VPR64, EXTvvvi_8b, neon_uimm3>;
6192 def : NI_Extract<v2f32, VPR64, EXTvvvi_8b, neon_uimm3>;
6193 def : NI_Extract<v1f64, VPR64, EXTvvvi_8b, neon_uimm3>;
6194 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6195 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6196 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6197 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6198 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6199 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6202 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6203 string asmop, string OpS, RegisterOperand OpVPR,
6204 RegisterOperand VecList>
6205 : NeonI_TBL<q, op2, len, op,
6206 (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6207 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6211 // The vectors in look up table are always 16b
6212 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6213 def _8b : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6214 !cast<RegisterOperand>(List # "16B_operand")>;
6216 def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6217 !cast<RegisterOperand>(List # "16B_operand")>;
6220 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6221 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6222 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6223 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6225 // Table lookup extention
6226 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6227 string asmop, string OpS, RegisterOperand OpVPR,
6228 RegisterOperand VecList>
6229 : NeonI_TBL<q, op2, len, op,
6230 (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6231 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6234 let Constraints = "$src = $Rd";
6237 // The vectors in look up table are always 16b
6238 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6239 def _8b : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6240 !cast<RegisterOperand>(List # "16B_operand")>;
6242 def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6243 !cast<RegisterOperand>(List # "16B_operand")>;
6246 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6247 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6248 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6249 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6251 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6252 RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6253 : NeonI_copy<0b1, 0b0, 0b0011,
6254 (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6255 asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6256 [(set (ResTy VPR128:$Rd),
6257 (ResTy (vector_insert
6258 (ResTy VPR128:$src),
6263 let Constraints = "$src = $Rd";
6266 //Insert element (vector, from main)
6267 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6269 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6271 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6273 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6275 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6277 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6279 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6281 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6284 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6285 (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6286 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6287 (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6288 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6289 (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6290 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6291 (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6293 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6294 RegisterClass OpGPR, ValueType OpTy,
6295 Operand OpImm, Instruction INS>
6296 : Pat<(ResTy (vector_insert
6300 (ResTy (EXTRACT_SUBREG
6301 (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6302 OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6304 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6305 neon_uimm3_bare, INSbw>;
6306 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6307 neon_uimm2_bare, INShw>;
6308 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6309 neon_uimm1_bare, INSsw>;
6310 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6311 neon_uimm0_bare, INSdx>;
6313 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6314 : NeonI_insert<0b1, 0b1,
6315 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6316 ResImm:$Immd, ResImm:$Immn),
6317 asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6320 let Constraints = "$src = $Rd";
6325 //Insert element (vector, from element)
6326 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6327 let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6328 let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6330 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6331 let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6332 let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6333 // bit 11 is unspecified, but should be set to zero.
6335 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6336 let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6337 let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6338 // bits 11-12 are unspecified, but should be set to zero.
6340 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6341 let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6342 let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6343 // bits 11-13 are unspecified, but should be set to zero.
6346 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6347 (INSELb VPR128:$Rd, VPR128:$Rn,
6348 neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6349 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6350 (INSELh VPR128:$Rd, VPR128:$Rn,
6351 neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6352 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6353 (INSELs VPR128:$Rd, VPR128:$Rn,
6354 neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6355 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6356 (INSELd VPR128:$Rd, VPR128:$Rn,
6357 neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6359 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6360 ValueType MidTy, Operand StImm, Operand NaImm,
6362 def : Pat<(ResTy (vector_insert
6363 (ResTy VPR128:$src),
6364 (MidTy (vector_extract
6368 (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6369 StImm:$Immd, StImm:$Immn)>;
6371 def : Pat <(ResTy (vector_insert
6372 (ResTy VPR128:$src),
6373 (MidTy (vector_extract
6377 (INS (ResTy VPR128:$src),
6378 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6379 StImm:$Immd, NaImm:$Immn)>;
6381 def : Pat <(NaTy (vector_insert
6383 (MidTy (vector_extract
6387 (NaTy (EXTRACT_SUBREG
6389 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6391 NaImm:$Immd, StImm:$Immn)),
6394 def : Pat <(NaTy (vector_insert
6396 (MidTy (vector_extract
6400 (NaTy (EXTRACT_SUBREG
6402 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6403 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6404 NaImm:$Immd, NaImm:$Immn)),
6408 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6409 neon_uimm1_bare, INSELs>;
6410 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6411 neon_uimm0_bare, INSELd>;
6412 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6413 neon_uimm3_bare, INSELb>;
6414 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6415 neon_uimm2_bare, INSELh>;
6416 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6417 neon_uimm1_bare, INSELs>;
6418 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6419 neon_uimm0_bare, INSELd>;
6421 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6423 RegisterClass OpFPR, Operand ResImm,
6424 SubRegIndex SubIndex, Instruction INS> {
6425 def : Pat <(ResTy (vector_insert
6426 (ResTy VPR128:$src),
6429 (INS (ResTy VPR128:$src),
6430 (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6434 def : Pat <(NaTy (vector_insert
6438 (NaTy (EXTRACT_SUBREG
6440 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6441 (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6447 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6449 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6452 class NeonI_SMOV<string asmop, string Res, bit Q,
6453 ValueType OpTy, ValueType eleTy,
6454 Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6455 : NeonI_copy<Q, 0b0, 0b0101,
6456 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6457 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6458 [(set (ResTy ResGPR:$Rd),
6460 (ResTy (vector_extract
6461 (OpTy VPR128:$Rn), (OpImm:$Imm))),
6467 //Signed integer move (main, from element)
6468 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6470 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6472 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6474 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6476 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6478 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6480 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6482 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6484 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6486 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6489 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6490 ValueType eleTy, Operand StImm, Operand NaImm,
6491 Instruction SMOVI> {
6492 def : Pat<(i64 (sext_inreg
6494 (i32 (vector_extract
6495 (StTy VPR128:$Rn), (StImm:$Imm))))),
6497 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6499 def : Pat<(i64 (sext
6500 (i32 (vector_extract
6501 (StTy VPR128:$Rn), (StImm:$Imm))))),
6502 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6504 def : Pat<(i64 (sext_inreg
6505 (i64 (vector_extract
6506 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6508 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6511 def : Pat<(i64 (sext_inreg
6513 (i32 (vector_extract
6514 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6516 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6519 def : Pat<(i64 (sext
6520 (i32 (vector_extract
6521 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6522 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6526 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6527 neon_uimm3_bare, SMOVxb>;
6528 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6529 neon_uimm2_bare, SMOVxh>;
6530 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6531 neon_uimm1_bare, SMOVxs>;
6533 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6534 ValueType eleTy, Operand StImm, Operand NaImm,
6536 : Pat<(i32 (sext_inreg
6537 (i32 (vector_extract
6538 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6540 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6543 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6544 neon_uimm3_bare, SMOVwb>;
6545 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6546 neon_uimm2_bare, SMOVwh>;
6548 class NeonI_UMOV<string asmop, string Res, bit Q,
6549 ValueType OpTy, Operand OpImm,
6550 RegisterClass ResGPR, ValueType ResTy>
6551 : NeonI_copy<Q, 0b0, 0b0111,
6552 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6553 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6554 [(set (ResTy ResGPR:$Rd),
6555 (ResTy (vector_extract
6556 (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6561 //Unsigned integer move (main, from element)
6562 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6564 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6566 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6568 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6570 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6572 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6574 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6576 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6579 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6580 (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6581 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6582 (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6584 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6585 Operand StImm, Operand NaImm,
6587 : Pat<(ResTy (vector_extract
6588 (NaTy VPR64:$Rn), NaImm:$Imm)),
6589 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6592 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6593 neon_uimm3_bare, UMOVwb>;
6594 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6595 neon_uimm2_bare, UMOVwh>;
6596 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6597 neon_uimm1_bare, UMOVws>;
6600 (i32 (vector_extract
6601 (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6603 (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6606 (i32 (vector_extract
6607 (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6609 (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6611 def : Pat<(i64 (zext
6612 (i32 (vector_extract
6613 (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6614 (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6617 (i32 (vector_extract
6618 (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6620 (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6621 neon_uimm3_bare:$Imm)>;
6624 (i32 (vector_extract
6625 (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6627 (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6628 neon_uimm2_bare:$Imm)>;
6630 def : Pat<(i64 (zext
6631 (i32 (vector_extract
6632 (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6633 (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6634 neon_uimm0_bare:$Imm)>;
6636 // Additional copy patterns for scalar types
6637 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6639 (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6641 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6643 (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6645 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6646 (FMOVws FPR32:$Rn)>;
6648 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6649 (FMOVxd FPR64:$Rn)>;
6651 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6654 def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
6657 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6658 (v1i8 (EXTRACT_SUBREG (v16i8
6659 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6662 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6663 (v1i16 (EXTRACT_SUBREG (v8i16
6664 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6667 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6670 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6673 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
6675 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6678 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
6681 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6682 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6683 (f64 FPR64:$src), sub_64)>;
6685 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane, string rnlane,
6686 RegisterOperand ResVPR, Operand OpImm>
6687 : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6688 (ins VPR128:$Rn, OpImm:$Imm),
6689 asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6695 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6697 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6700 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6702 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6705 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6707 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6710 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6712 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6715 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6717 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6720 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6722 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6725 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6727 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6730 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6731 ValueType OpTy,ValueType NaTy,
6732 ValueType ExTy, Operand OpLImm,
6734 def : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6735 (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6737 def : Pat<(ResTy (Neon_vduplane
6738 (NaTy VPR64:$Rn), OpNImm:$Imm)),
6740 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6742 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6743 neon_uimm4_bare, neon_uimm3_bare>;
6744 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6745 neon_uimm4_bare, neon_uimm3_bare>;
6746 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6747 neon_uimm3_bare, neon_uimm2_bare>;
6748 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6749 neon_uimm3_bare, neon_uimm2_bare>;
6750 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6751 neon_uimm2_bare, neon_uimm1_bare>;
6752 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6753 neon_uimm2_bare, neon_uimm1_bare>;
6754 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6755 neon_uimm1_bare, neon_uimm0_bare>;
6756 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6757 neon_uimm2_bare, neon_uimm1_bare>;
6758 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6759 neon_uimm2_bare, neon_uimm1_bare>;
6760 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6761 neon_uimm1_bare, neon_uimm0_bare>;
6763 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6765 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6767 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6769 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6771 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
6773 (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
6776 class NeonI_DUP<bit Q, string asmop, string rdlane,
6777 RegisterOperand ResVPR, ValueType ResTy,
6778 RegisterClass OpGPR, ValueType OpTy>
6779 : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
6780 asmop # "\t$Rd" # rdlane # ", $Rn",
6781 [(set (ResTy ResVPR:$Rd),
6782 (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
6785 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
6786 let Inst{20-16} = 0b00001;
6787 // bits 17-20 are unspecified, but should be set to zero.
6790 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
6791 let Inst{20-16} = 0b00010;
6792 // bits 18-20 are unspecified, but should be set to zero.
6795 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
6796 let Inst{20-16} = 0b00100;
6797 // bits 19-20 are unspecified, but should be set to zero.
6800 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
6801 let Inst{20-16} = 0b01000;
6802 // bit 20 is unspecified, but should be set to zero.
6805 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
6806 let Inst{20-16} = 0b00001;
6807 // bits 17-20 are unspecified, but should be set to zero.
6810 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
6811 let Inst{20-16} = 0b00010;
6812 // bits 18-20 are unspecified, but should be set to zero.
6815 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
6816 let Inst{20-16} = 0b00100;
6817 // bits 19-20 are unspecified, but should be set to zero.
6820 // patterns for CONCAT_VECTORS
6821 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
6822 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
6823 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
6824 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
6826 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6827 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
6830 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
6832 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6836 defm : Concat_Vector_Pattern<v16i8, v8i8>;
6837 defm : Concat_Vector_Pattern<v8i16, v4i16>;
6838 defm : Concat_Vector_Pattern<v4i32, v2i32>;
6839 defm : Concat_Vector_Pattern<v2i64, v1i64>;
6840 defm : Concat_Vector_Pattern<v4f32, v2f32>;
6841 defm : Concat_Vector_Pattern<v2f64, v1f64>;
6843 //patterns for EXTRACT_SUBVECTOR
6844 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
6845 (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6846 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
6847 (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6848 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
6849 (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6850 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
6851 (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6852 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
6853 (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6854 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
6855 (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6857 // The followings are for instruction class (3V Elem)
6861 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
6862 string asmop, string ResS, string OpS, string EleOpS,
6863 Operand OpImm, RegisterOperand ResVPR,
6864 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6865 : NeonI_2VElem<q, u, size, opcode,
6866 (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
6867 EleOpVPR:$Re, OpImm:$Index),
6868 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6869 ", $Re." # EleOpS # "[$Index]",
6875 let Constraints = "$src = $Rd";
6878 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
6879 // vector register class for element is always 128-bit to cover the max index
6880 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6881 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6882 let Inst{11} = {Index{1}};
6883 let Inst{21} = {Index{0}};
6884 let Inst{20-16} = Re;
6887 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6888 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6889 let Inst{11} = {Index{1}};
6890 let Inst{21} = {Index{0}};
6891 let Inst{20-16} = Re;
6894 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6895 def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6896 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6897 let Inst{11} = {Index{2}};
6898 let Inst{21} = {Index{1}};
6899 let Inst{20} = {Index{0}};
6900 let Inst{19-16} = Re{3-0};
6903 def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6904 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6905 let Inst{11} = {Index{2}};
6906 let Inst{21} = {Index{1}};
6907 let Inst{20} = {Index{0}};
6908 let Inst{19-16} = Re{3-0};
6912 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
6913 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
6915 // Pattern for lane in 128-bit vector
6916 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6917 RegisterOperand ResVPR, RegisterOperand OpVPR,
6918 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6920 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6921 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6922 (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6924 // Pattern for lane in 64-bit vector
6925 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6926 RegisterOperand ResVPR, RegisterOperand OpVPR,
6927 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6929 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6930 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6931 (INST ResVPR:$src, OpVPR:$Rn,
6932 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6934 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
6936 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6937 op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
6939 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6940 op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
6942 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6943 op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
6945 def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6946 op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
6948 // Index can only be half of the max value for lane in 64-bit vector
6950 def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6951 op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
6953 def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6954 op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
6957 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
6958 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
6960 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
6961 string asmop, string ResS, string OpS, string EleOpS,
6962 Operand OpImm, RegisterOperand ResVPR,
6963 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6964 : NeonI_2VElem<q, u, size, opcode,
6965 (outs ResVPR:$Rd), (ins OpVPR:$Rn,
6966 EleOpVPR:$Re, OpImm:$Index),
6967 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6968 ", $Re." # EleOpS # "[$Index]",
6975 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
6976 // vector register class for element is always 128-bit to cover the max index
6977 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6978 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6979 let Inst{11} = {Index{1}};
6980 let Inst{21} = {Index{0}};
6981 let Inst{20-16} = Re;
6984 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6985 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6986 let Inst{11} = {Index{1}};
6987 let Inst{21} = {Index{0}};
6988 let Inst{20-16} = Re;
6991 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6992 def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6993 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6994 let Inst{11} = {Index{2}};
6995 let Inst{21} = {Index{1}};
6996 let Inst{20} = {Index{0}};
6997 let Inst{19-16} = Re{3-0};
7000 def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7001 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7002 let Inst{11} = {Index{2}};
7003 let Inst{21} = {Index{1}};
7004 let Inst{20} = {Index{0}};
7005 let Inst{19-16} = Re{3-0};
7009 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
7010 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
7011 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
7013 // Pattern for lane in 128-bit vector
7014 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7015 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7016 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7017 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7018 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7019 (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7021 // Pattern for lane in 64-bit vector
7022 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7023 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7024 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7025 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7026 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7028 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7030 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
7031 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7032 op, VPR64, VPR128, v2i32, v2i32, v4i32>;
7034 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7035 op, VPR128, VPR128, v4i32, v4i32, v4i32>;
7037 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7038 op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7040 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7041 op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7043 // Index can only be half of the max value for lane in 64-bit vector
7045 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7046 op, VPR64, VPR64, v2i32, v2i32, v2i32>;
7048 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7049 op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7052 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
7053 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
7054 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
7058 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
7059 // vector register class for element is always 128-bit to cover the max index
7060 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7061 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7062 let Inst{11} = {Index{1}};
7063 let Inst{21} = {Index{0}};
7064 let Inst{20-16} = Re;
7067 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7068 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7069 let Inst{11} = {Index{1}};
7070 let Inst{21} = {Index{0}};
7071 let Inst{20-16} = Re;
7074 // _1d2d doesn't exist!
7076 def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7077 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7078 let Inst{11} = {Index{0}};
7080 let Inst{20-16} = Re;
7084 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
7085 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
7087 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
7088 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7089 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
7090 SDPatternOperator coreop>
7091 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7092 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
7094 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
7096 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
7097 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7098 op, VPR64, VPR128, v2f32, v2f32, v4f32>;
7100 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7101 op, VPR128, VPR128, v4f32, v4f32, v4f32>;
7103 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7104 op, VPR128, VPR128, v2f64, v2f64, v2f64>;
7106 // Index can only be half of the max value for lane in 64-bit vector
7108 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7109 op, VPR64, VPR64, v2f32, v2f32, v2f32>;
7111 def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7112 op, VPR128, VPR64, v2f64, v2f64, v1f64,
7113 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7116 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
7117 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
7119 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
7120 (v2f32 VPR64:$Rn))),
7121 (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7123 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
7124 (v4f32 VPR128:$Rn))),
7125 (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7127 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
7128 (v2f64 VPR128:$Rn))),
7129 (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7131 // The followings are patterns using fma
7132 // -ffp-contract=fast generates fma
7134 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7135 // vector register class for element is always 128-bit to cover the max index
7136 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7137 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7138 let Inst{11} = {Index{1}};
7139 let Inst{21} = {Index{0}};
7140 let Inst{20-16} = Re;
7143 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7144 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7145 let Inst{11} = {Index{1}};
7146 let Inst{21} = {Index{0}};
7147 let Inst{20-16} = Re;
7150 // _1d2d doesn't exist!
7152 def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7153 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7154 let Inst{11} = {Index{0}};
7156 let Inst{20-16} = Re;
7160 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7161 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7163 // Pattern for lane in 128-bit vector
7164 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7165 RegisterOperand ResVPR, RegisterOperand OpVPR,
7166 ValueType ResTy, ValueType OpTy,
7167 SDPatternOperator coreop>
7168 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7169 (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
7170 (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7172 // Pattern for lane 0
7173 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7174 RegisterOperand ResVPR, ValueType ResTy>
7175 : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7176 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7177 (ResTy ResVPR:$src))),
7178 (INST ResVPR:$src, ResVPR:$Rn,
7179 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7181 // Pattern for lane in 64-bit vector
7182 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7183 RegisterOperand ResVPR, RegisterOperand OpVPR,
7184 ValueType ResTy, ValueType OpTy,
7185 SDPatternOperator coreop>
7186 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7187 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7188 (INST ResVPR:$src, ResVPR:$Rn,
7189 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7191 // Pattern for lane in 64-bit vector
7192 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7193 SDPatternOperator op,
7194 RegisterOperand ResVPR, RegisterOperand OpVPR,
7195 ValueType ResTy, ValueType OpTy,
7196 SDPatternOperator coreop>
7197 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7198 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7199 (INST ResVPR:$src, ResVPR:$Rn,
7200 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7203 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7204 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7205 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7206 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7208 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7211 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7212 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7213 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7215 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7218 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7219 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7220 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7222 // Index can only be half of the max value for lane in 64-bit vector
7224 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7225 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7226 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7228 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7229 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7230 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7233 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7235 // Pattern for lane 0
7236 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7237 RegisterOperand ResVPR, ValueType ResTy>
7238 : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7239 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7240 (ResTy ResVPR:$src))),
7241 (INST ResVPR:$src, ResVPR:$Rn,
7242 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7244 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7246 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7247 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7248 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7250 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7251 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7252 BinOpFrag<(Neon_vduplane
7253 (fneg node:$LHS), node:$RHS)>>;
7255 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7258 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7259 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7260 BinOpFrag<(fneg (Neon_vduplane
7261 node:$LHS, node:$RHS))>>;
7263 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7264 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7265 BinOpFrag<(Neon_vduplane
7266 (fneg node:$LHS), node:$RHS)>>;
7268 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7271 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7272 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7273 BinOpFrag<(fneg (Neon_vduplane
7274 node:$LHS, node:$RHS))>>;
7276 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7277 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7278 BinOpFrag<(Neon_vduplane
7279 (fneg node:$LHS), node:$RHS)>>;
7281 // Index can only be half of the max value for lane in 64-bit vector
7283 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7284 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7285 BinOpFrag<(fneg (Neon_vduplane
7286 node:$LHS, node:$RHS))>>;
7288 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7289 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7290 BinOpFrag<(Neon_vduplane
7291 (fneg node:$LHS), node:$RHS)>>;
7293 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7294 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7295 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7297 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7298 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7299 BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7301 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7302 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7303 BinOpFrag<(fneg (Neon_combine_2d
7304 node:$LHS, node:$RHS))>>;
7306 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7307 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7308 BinOpFrag<(Neon_combine_2d
7309 (fneg node:$LHS), (fneg node:$RHS))>>;
7312 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7314 // Variant 3: Long type
7315 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7316 // SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7318 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7319 // vector register class for element is always 128-bit to cover the max index
7320 def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7321 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7322 let Inst{11} = {Index{1}};
7323 let Inst{21} = {Index{0}};
7324 let Inst{20-16} = Re;
7327 def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7328 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7329 let Inst{11} = {Index{1}};
7330 let Inst{21} = {Index{0}};
7331 let Inst{20-16} = Re;
7334 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7335 def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7336 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7337 let Inst{11} = {Index{2}};
7338 let Inst{21} = {Index{1}};
7339 let Inst{20} = {Index{0}};
7340 let Inst{19-16} = Re{3-0};
7343 def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7344 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7345 let Inst{11} = {Index{2}};
7346 let Inst{21} = {Index{1}};
7347 let Inst{20} = {Index{0}};
7348 let Inst{19-16} = Re{3-0};
7352 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7353 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7354 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7355 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7356 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7357 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7359 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7360 // vector register class for element is always 128-bit to cover the max index
7361 def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7362 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7363 let Inst{11} = {Index{1}};
7364 let Inst{21} = {Index{0}};
7365 let Inst{20-16} = Re;
7368 def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7369 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7370 let Inst{11} = {Index{1}};
7371 let Inst{21} = {Index{0}};
7372 let Inst{20-16} = Re;
7375 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7376 def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7377 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7378 let Inst{11} = {Index{2}};
7379 let Inst{21} = {Index{1}};
7380 let Inst{20} = {Index{0}};
7381 let Inst{19-16} = Re{3-0};
7384 def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7385 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7386 let Inst{11} = {Index{2}};
7387 let Inst{21} = {Index{1}};
7388 let Inst{20} = {Index{0}};
7389 let Inst{19-16} = Re{3-0};
7393 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7394 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7395 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7397 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7399 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$src))),
7402 // Pattern for lane in 128-bit vector
7403 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7404 RegisterOperand EleOpVPR, ValueType ResTy,
7405 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7406 SDPatternOperator hiop>
7407 : Pat<(ResTy (op (ResTy VPR128:$src),
7408 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7409 (HalfOpTy (Neon_vduplane
7410 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7411 (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7413 // Pattern for lane in 64-bit vector
7414 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7415 RegisterOperand EleOpVPR, ValueType ResTy,
7416 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7417 SDPatternOperator hiop>
7418 : Pat<(ResTy (op (ResTy VPR128:$src),
7419 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7420 (HalfOpTy (Neon_vduplane
7421 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7422 (INST VPR128:$src, VPR128:$Rn,
7423 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7425 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7426 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7427 SDPatternOperator hiop, Instruction DupInst>
7428 : Pat<(ResTy (op (ResTy VPR128:$src),
7429 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7430 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7431 (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7433 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7434 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7435 op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7437 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7438 op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7440 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7441 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7443 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7444 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7446 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7447 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7449 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7450 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7452 // Index can only be half of the max value for lane in 64-bit vector
7454 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7455 op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7457 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7458 op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7460 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7461 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7463 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7464 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7467 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7468 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7469 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7470 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7472 // Pattern for lane in 128-bit vector
7473 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7474 RegisterOperand EleOpVPR, ValueType ResTy,
7475 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7476 SDPatternOperator hiop>
7478 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7479 (HalfOpTy (Neon_vduplane
7480 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7481 (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7483 // Pattern for lane in 64-bit vector
7484 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7485 RegisterOperand EleOpVPR, ValueType ResTy,
7486 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7487 SDPatternOperator hiop>
7489 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7490 (HalfOpTy (Neon_vduplane
7491 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7493 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7495 // Pattern for fixed lane 0
7496 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7497 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7498 SDPatternOperator hiop, Instruction DupInst>
7500 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7501 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7502 (INST VPR128:$Rn, (DupInst $Re), 0)>;
7504 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7505 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7506 op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7508 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7509 op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7511 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7512 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7514 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7515 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7517 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7518 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7520 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7521 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7523 // Index can only be half of the max value for lane in 64-bit vector
7525 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7526 op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7528 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7529 op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7531 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7532 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7534 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7535 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7538 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7539 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7540 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7542 multiclass NI_qdma<SDPatternOperator op> {
7543 def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7545 (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7547 def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7549 (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7552 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7553 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7555 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7556 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7557 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7558 v4i32, v4i16, v8i16>;
7560 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7561 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7562 v2i64, v2i32, v4i32>;
7564 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7565 !cast<PatFrag>(op # "_4s"), VPR128Lo,
7566 v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7568 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7569 !cast<PatFrag>(op # "_2d"), VPR128,
7570 v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7572 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7573 !cast<PatFrag>(op # "_4s"),
7574 v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7576 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7577 !cast<PatFrag>(op # "_2d"),
7578 v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7580 // Index can only be half of the max value for lane in 64-bit vector
7582 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7583 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7584 v4i32, v4i16, v4i16>;
7586 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7587 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7588 v2i64, v2i32, v2i32>;
7590 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7591 !cast<PatFrag>(op # "_4s"), VPR64Lo,
7592 v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7594 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7595 !cast<PatFrag>(op # "_2d"), VPR64,
7596 v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7599 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7600 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7602 // End of implementation for instruction class (3V Elem)
7604 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7605 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7606 SDPatternOperator Neon_Rev>
7607 : NeonI_2VMisc<Q, U, size, opcode,
7608 (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7609 asmop # "\t$Rd." # Res # ", $Rn." # Res,
7610 [(set (ResTy ResVPR:$Rd),
7611 (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7614 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7616 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7618 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7620 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7622 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7624 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7627 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7628 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7630 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7632 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7634 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7636 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7639 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7641 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7644 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7645 SDPatternOperator Neon_Padd> {
7646 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7647 (outs VPR128:$Rd), (ins VPR128:$Rn),
7648 asmop # "\t$Rd.8h, $Rn.16b",
7649 [(set (v8i16 VPR128:$Rd),
7650 (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7653 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7654 (outs VPR64:$Rd), (ins VPR64:$Rn),
7655 asmop # "\t$Rd.4h, $Rn.8b",
7656 [(set (v4i16 VPR64:$Rd),
7657 (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7660 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7661 (outs VPR128:$Rd), (ins VPR128:$Rn),
7662 asmop # "\t$Rd.4s, $Rn.8h",
7663 [(set (v4i32 VPR128:$Rd),
7664 (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7667 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7668 (outs VPR64:$Rd), (ins VPR64:$Rn),
7669 asmop # "\t$Rd.2s, $Rn.4h",
7670 [(set (v2i32 VPR64:$Rd),
7671 (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7674 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7675 (outs VPR128:$Rd), (ins VPR128:$Rn),
7676 asmop # "\t$Rd.2d, $Rn.4s",
7677 [(set (v2i64 VPR128:$Rd),
7678 (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7681 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7682 (outs VPR64:$Rd), (ins VPR64:$Rn),
7683 asmop # "\t$Rd.1d, $Rn.2s",
7684 [(set (v1i64 VPR64:$Rd),
7685 (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7689 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7690 int_arm_neon_vpaddls>;
7691 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7692 int_arm_neon_vpaddlu>;
7694 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7695 SDPatternOperator Neon_Padd> {
7696 let Constraints = "$src = $Rd" in {
7697 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7698 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7699 asmop # "\t$Rd.8h, $Rn.16b",
7700 [(set (v8i16 VPR128:$Rd),
7702 (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7705 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7706 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7707 asmop # "\t$Rd.4h, $Rn.8b",
7708 [(set (v4i16 VPR64:$Rd),
7710 (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7713 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7714 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7715 asmop # "\t$Rd.4s, $Rn.8h",
7716 [(set (v4i32 VPR128:$Rd),
7718 (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7721 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7722 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7723 asmop # "\t$Rd.2s, $Rn.4h",
7724 [(set (v2i32 VPR64:$Rd),
7726 (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7729 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7730 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7731 asmop # "\t$Rd.2d, $Rn.4s",
7732 [(set (v2i64 VPR128:$Rd),
7734 (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7737 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7738 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7739 asmop # "\t$Rd.1d, $Rn.2s",
7740 [(set (v1i64 VPR64:$Rd),
7742 (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7747 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7748 int_arm_neon_vpadals>;
7749 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7750 int_arm_neon_vpadalu>;
7752 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7753 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7754 (outs VPR128:$Rd), (ins VPR128:$Rn),
7755 asmop # "\t$Rd.16b, $Rn.16b",
7758 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7759 (outs VPR128:$Rd), (ins VPR128:$Rn),
7760 asmop # "\t$Rd.8h, $Rn.8h",
7763 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7764 (outs VPR128:$Rd), (ins VPR128:$Rn),
7765 asmop # "\t$Rd.4s, $Rn.4s",
7768 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7769 (outs VPR128:$Rd), (ins VPR128:$Rn),
7770 asmop # "\t$Rd.2d, $Rn.2d",
7773 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7774 (outs VPR64:$Rd), (ins VPR64:$Rn),
7775 asmop # "\t$Rd.8b, $Rn.8b",
7778 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7779 (outs VPR64:$Rd), (ins VPR64:$Rn),
7780 asmop # "\t$Rd.4h, $Rn.4h",
7783 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7784 (outs VPR64:$Rd), (ins VPR64:$Rn),
7785 asmop # "\t$Rd.2s, $Rn.2s",
7789 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
7790 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
7791 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
7792 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
7794 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
7795 SDPatternOperator Neon_Op> {
7796 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
7797 (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
7799 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
7800 (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
7802 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
7803 (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
7805 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
7806 (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
7808 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
7809 (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
7811 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
7812 (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
7814 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
7815 (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
7818 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
7819 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
7820 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
7822 def : Pat<(v16i8 (sub
7823 (v16i8 Neon_AllZero),
7824 (v16i8 VPR128:$Rn))),
7825 (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
7826 def : Pat<(v8i8 (sub
7827 (v8i8 Neon_AllZero),
7829 (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
7830 def : Pat<(v8i16 (sub
7831 (v8i16 (bitconvert (v16i8 Neon_AllZero))),
7832 (v8i16 VPR128:$Rn))),
7833 (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
7834 def : Pat<(v4i16 (sub
7835 (v4i16 (bitconvert (v8i8 Neon_AllZero))),
7836 (v4i16 VPR64:$Rn))),
7837 (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
7838 def : Pat<(v4i32 (sub
7839 (v4i32 (bitconvert (v16i8 Neon_AllZero))),
7840 (v4i32 VPR128:$Rn))),
7841 (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
7842 def : Pat<(v2i32 (sub
7843 (v2i32 (bitconvert (v8i8 Neon_AllZero))),
7844 (v2i32 VPR64:$Rn))),
7845 (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
7846 def : Pat<(v2i64 (sub
7847 (v2i64 (bitconvert (v16i8 Neon_AllZero))),
7848 (v2i64 VPR128:$Rn))),
7849 (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
7851 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
7852 let Constraints = "$src = $Rd" in {
7853 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7854 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7855 asmop # "\t$Rd.16b, $Rn.16b",
7858 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7859 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7860 asmop # "\t$Rd.8h, $Rn.8h",
7863 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7864 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7865 asmop # "\t$Rd.4s, $Rn.4s",
7868 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7869 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7870 asmop # "\t$Rd.2d, $Rn.2d",
7873 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7874 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7875 asmop # "\t$Rd.8b, $Rn.8b",
7878 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7879 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7880 asmop # "\t$Rd.4h, $Rn.4h",
7883 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7884 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7885 asmop # "\t$Rd.2s, $Rn.2s",
7890 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
7891 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
7893 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
7894 SDPatternOperator Neon_Op> {
7895 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
7896 (v16i8 (!cast<Instruction>(Prefix # 16b)
7897 (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
7899 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
7900 (v8i16 (!cast<Instruction>(Prefix # 8h)
7901 (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
7903 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
7904 (v4i32 (!cast<Instruction>(Prefix # 4s)
7905 (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
7907 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
7908 (v2i64 (!cast<Instruction>(Prefix # 2d)
7909 (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
7911 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
7912 (v8i8 (!cast<Instruction>(Prefix # 8b)
7913 (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
7915 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
7916 (v4i16 (!cast<Instruction>(Prefix # 4h)
7917 (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
7919 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
7920 (v2i32 (!cast<Instruction>(Prefix # 2s)
7921 (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
7924 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
7925 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
7927 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
7928 SDPatternOperator Neon_Op> {
7929 def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
7930 (outs VPR128:$Rd), (ins VPR128:$Rn),
7931 asmop # "\t$Rd.16b, $Rn.16b",
7932 [(set (v16i8 VPR128:$Rd),
7933 (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
7936 def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
7937 (outs VPR128:$Rd), (ins VPR128:$Rn),
7938 asmop # "\t$Rd.8h, $Rn.8h",
7939 [(set (v8i16 VPR128:$Rd),
7940 (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
7943 def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
7944 (outs VPR128:$Rd), (ins VPR128:$Rn),
7945 asmop # "\t$Rd.4s, $Rn.4s",
7946 [(set (v4i32 VPR128:$Rd),
7947 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
7950 def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
7951 (outs VPR64:$Rd), (ins VPR64:$Rn),
7952 asmop # "\t$Rd.8b, $Rn.8b",
7953 [(set (v8i8 VPR64:$Rd),
7954 (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
7957 def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
7958 (outs VPR64:$Rd), (ins VPR64:$Rn),
7959 asmop # "\t$Rd.4h, $Rn.4h",
7960 [(set (v4i16 VPR64:$Rd),
7961 (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
7964 def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
7965 (outs VPR64:$Rd), (ins VPR64:$Rn),
7966 asmop # "\t$Rd.2s, $Rn.2s",
7967 [(set (v2i32 VPR64:$Rd),
7968 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
7972 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
7973 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
7975 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
7977 def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
7978 (outs VPR128:$Rd), (ins VPR128:$Rn),
7979 asmop # "\t$Rd.16b, $Rn.16b",
7982 def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
7983 (outs VPR64:$Rd), (ins VPR64:$Rn),
7984 asmop # "\t$Rd.8b, $Rn.8b",
7988 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
7989 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
7990 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
7992 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
7993 (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
7994 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
7995 (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
7997 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
7998 (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
7999 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
8000 (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
8002 def : Pat<(v16i8 (xor
8004 (v16i8 Neon_AllOne))),
8005 (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
8006 def : Pat<(v8i8 (xor
8008 (v8i8 Neon_AllOne))),
8009 (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
8010 def : Pat<(v8i16 (xor
8012 (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
8013 (NOT16b VPR128:$Rn)>;
8014 def : Pat<(v4i16 (xor
8016 (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
8018 def : Pat<(v4i32 (xor
8020 (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
8021 (NOT16b VPR128:$Rn)>;
8022 def : Pat<(v2i32 (xor
8024 (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
8026 def : Pat<(v2i64 (xor
8028 (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
8029 (NOT16b VPR128:$Rn)>;
8031 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
8032 (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
8033 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
8034 (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
8036 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
8037 SDPatternOperator Neon_Op> {
8038 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8039 (outs VPR128:$Rd), (ins VPR128:$Rn),
8040 asmop # "\t$Rd.4s, $Rn.4s",
8041 [(set (v4f32 VPR128:$Rd),
8042 (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
8045 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8046 (outs VPR128:$Rd), (ins VPR128:$Rn),
8047 asmop # "\t$Rd.2d, $Rn.2d",
8048 [(set (v2f64 VPR128:$Rd),
8049 (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
8052 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8053 (outs VPR64:$Rd), (ins VPR64:$Rn),
8054 asmop # "\t$Rd.2s, $Rn.2s",
8055 [(set (v2f32 VPR64:$Rd),
8056 (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
8060 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
8061 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
8063 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
8064 def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8065 (outs VPR64:$Rd), (ins VPR128:$Rn),
8066 asmop # "\t$Rd.8b, $Rn.8h",
8069 def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8070 (outs VPR64:$Rd), (ins VPR128:$Rn),
8071 asmop # "\t$Rd.4h, $Rn.4s",
8074 def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8075 (outs VPR64:$Rd), (ins VPR128:$Rn),
8076 asmop # "\t$Rd.2s, $Rn.2d",
8079 let Constraints = "$Rd = $src" in {
8080 def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8081 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8082 asmop # "2\t$Rd.16b, $Rn.8h",
8085 def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8086 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8087 asmop # "2\t$Rd.8h, $Rn.4s",
8090 def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8091 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8092 asmop # "2\t$Rd.4s, $Rn.2d",
8097 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
8098 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
8099 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
8100 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
8102 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
8103 SDPatternOperator Neon_Op> {
8104 def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8105 (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8107 def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8108 (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8110 def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8111 (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8113 def : Pat<(v16i8 (concat_vectors
8115 (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8116 (!cast<Instruction>(Prefix # 8h16b)
8117 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8120 def : Pat<(v8i16 (concat_vectors
8122 (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8123 (!cast<Instruction>(Prefix # 4s8h)
8124 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8127 def : Pat<(v4i32 (concat_vectors
8129 (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8130 (!cast<Instruction>(Prefix # 2d4s)
8131 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8135 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8136 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8137 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8138 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8140 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8141 let DecoderMethod = "DecodeSHLLInstruction" in {
8142 def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8144 (ins VPR64:$Rn, uimm_exact8:$Imm),
8145 asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8148 def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8150 (ins VPR64:$Rn, uimm_exact16:$Imm),
8151 asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8154 def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8156 (ins VPR64:$Rn, uimm_exact32:$Imm),
8157 asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8160 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8162 (ins VPR128:$Rn, uimm_exact8:$Imm),
8163 asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8166 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8168 (ins VPR128:$Rn, uimm_exact16:$Imm),
8169 asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8172 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8174 (ins VPR128:$Rn, uimm_exact32:$Imm),
8175 asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8180 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8182 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8183 SDPatternOperator ExtOp, Operand Neon_Imm,
8186 (DesTy (ExtOp (OpTy VPR64:$Rn))),
8188 (i32 Neon_Imm:$Imm))))),
8189 (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8191 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8192 SDPatternOperator ExtOp, Operand Neon_Imm,
8193 string suffix, PatFrag GetHigh>
8196 (OpTy (GetHigh VPR128:$Rn)))),
8198 (i32 Neon_Imm:$Imm))))),
8199 (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8201 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8202 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8203 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8204 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8205 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8206 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8207 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8209 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8211 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8213 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8215 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8217 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8220 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8221 def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8222 (outs VPR64:$Rd), (ins VPR128:$Rn),
8223 asmop # "\t$Rd.4h, $Rn.4s",
8226 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8227 (outs VPR64:$Rd), (ins VPR128:$Rn),
8228 asmop # "\t$Rd.2s, $Rn.2d",
8231 let Constraints = "$src = $Rd" in {
8232 def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8233 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8234 asmop # "2\t$Rd.8h, $Rn.4s",
8237 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8238 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8239 asmop # "2\t$Rd.4s, $Rn.2d",
8244 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8246 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8247 SDPatternOperator f32_to_f16_Op,
8248 SDPatternOperator f64_to_f32_Op> {
8250 def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8251 (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8253 def : Pat<(v8i16 (concat_vectors
8255 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8256 (!cast<Instruction>(prefix # "4s8h")
8257 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8258 (v4f32 VPR128:$Rn))>;
8260 def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8261 (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8263 def : Pat<(v4f32 (concat_vectors
8265 (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8266 (!cast<Instruction>(prefix # "2d4s")
8267 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8268 (v2f64 VPR128:$Rn))>;
8271 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8273 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8275 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8276 (outs VPR64:$Rd), (ins VPR128:$Rn),
8277 asmop # "\t$Rd.2s, $Rn.2d",
8280 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8281 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8282 asmop # "2\t$Rd.4s, $Rn.2d",
8284 let Constraints = "$src = $Rd";
8287 def : Pat<(v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))),
8288 (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8290 def : Pat<(v4f32 (concat_vectors
8292 (v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))))),
8293 (!cast<Instruction>(prefix # "2d4s")
8294 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8298 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8300 def Neon_High4Float : PatFrag<(ops node:$in),
8301 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8303 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8304 def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8305 (outs VPR128:$Rd), (ins VPR64:$Rn),
8306 asmop # "\t$Rd.4s, $Rn.4h",
8309 def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8310 (outs VPR128:$Rd), (ins VPR64:$Rn),
8311 asmop # "\t$Rd.2d, $Rn.2s",
8314 def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8315 (outs VPR128:$Rd), (ins VPR128:$Rn),
8316 asmop # "2\t$Rd.4s, $Rn.8h",
8319 def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8320 (outs VPR128:$Rd), (ins VPR128:$Rn),
8321 asmop # "2\t$Rd.2d, $Rn.4s",
8325 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8327 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8328 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8329 (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8331 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8333 (v8i16 VPR128:$Rn))))),
8334 (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8336 def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8337 (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8339 def : Pat<(v2f64 (fextend
8340 (v2f32 (Neon_High4Float
8341 (v4f32 VPR128:$Rn))))),
8342 (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8345 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8347 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8348 ValueType ResTy4s, ValueType OpTy4s,
8349 ValueType ResTy2d, ValueType OpTy2d,
8350 ValueType ResTy2s, ValueType OpTy2s,
8351 SDPatternOperator Neon_Op> {
8353 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8354 (outs VPR128:$Rd), (ins VPR128:$Rn),
8355 asmop # "\t$Rd.4s, $Rn.4s",
8356 [(set (ResTy4s VPR128:$Rd),
8357 (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8360 def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8361 (outs VPR128:$Rd), (ins VPR128:$Rn),
8362 asmop # "\t$Rd.2d, $Rn.2d",
8363 [(set (ResTy2d VPR128:$Rd),
8364 (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8367 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8368 (outs VPR64:$Rd), (ins VPR64:$Rn),
8369 asmop # "\t$Rd.2s, $Rn.2s",
8370 [(set (ResTy2s VPR64:$Rd),
8371 (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8375 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8376 bits<5> opcode, SDPatternOperator Neon_Op> {
8377 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8378 v2f64, v2i32, v2f32, Neon_Op>;
8381 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8382 int_aarch64_neon_fcvtns>;
8383 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8384 int_aarch64_neon_fcvtnu>;
8385 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8386 int_aarch64_neon_fcvtps>;
8387 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8388 int_aarch64_neon_fcvtpu>;
8389 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8390 int_aarch64_neon_fcvtms>;
8391 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8392 int_aarch64_neon_fcvtmu>;
8393 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8394 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8395 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8396 int_aarch64_neon_fcvtas>;
8397 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8398 int_aarch64_neon_fcvtau>;
8400 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8401 bits<5> opcode, SDPatternOperator Neon_Op> {
8402 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8403 v2i64, v2f32, v2i32, Neon_Op>;
8406 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8407 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8409 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8410 bits<5> opcode, SDPatternOperator Neon_Op> {
8411 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8412 v2f64, v2f32, v2f32, Neon_Op>;
8415 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8416 int_aarch64_neon_frintn>;
8417 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8418 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8419 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8420 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8421 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8422 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8423 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8424 int_arm_neon_vrecpe>;
8425 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8426 int_arm_neon_vrsqrte>;
8427 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
8429 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8430 bits<5> opcode, SDPatternOperator Neon_Op> {
8431 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8432 (outs VPR128:$Rd), (ins VPR128:$Rn),
8433 asmop # "\t$Rd.4s, $Rn.4s",
8434 [(set (v4i32 VPR128:$Rd),
8435 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8438 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8439 (outs VPR64:$Rd), (ins VPR64:$Rn),
8440 asmop # "\t$Rd.2s, $Rn.2s",
8441 [(set (v2i32 VPR64:$Rd),
8442 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8446 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8447 int_arm_neon_vrecpe>;
8448 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8449 int_arm_neon_vrsqrte>;
8452 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8453 string asmop, SDPatternOperator opnode>
8454 : NeonI_Crypto_AES<size, opcode,
8455 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8456 asmop # "\t$Rd.16b, $Rn.16b",
8457 [(set (v16i8 VPR128:$Rd),
8458 (v16i8 (opnode (v16i8 VPR128:$src),
8459 (v16i8 VPR128:$Rn))))],
8461 let Constraints = "$src = $Rd";
8462 let Predicates = [HasNEON, HasCrypto];
8465 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8466 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8468 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8469 string asmop, SDPatternOperator opnode>
8470 : NeonI_Crypto_AES<size, opcode,
8471 (outs VPR128:$Rd), (ins VPR128:$Rn),
8472 asmop # "\t$Rd.16b, $Rn.16b",
8473 [(set (v16i8 VPR128:$Rd),
8474 (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8477 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8478 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8480 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8481 string asmop, SDPatternOperator opnode>
8482 : NeonI_Crypto_SHA<size, opcode,
8483 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8484 asmop # "\t$Rd.4s, $Rn.4s",
8485 [(set (v4i32 VPR128:$Rd),
8486 (v4i32 (opnode (v4i32 VPR128:$src),
8487 (v4i32 VPR128:$Rn))))],
8489 let Constraints = "$src = $Rd";
8490 let Predicates = [HasNEON, HasCrypto];
8493 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8494 int_arm_neon_sha1su1>;
8495 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8496 int_arm_neon_sha256su0>;
8498 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8499 string asmop, SDPatternOperator opnode>
8500 : NeonI_Crypto_SHA<size, opcode,
8501 (outs FPR32:$Rd), (ins FPR32:$Rn),
8502 asmop # "\t$Rd, $Rn",
8503 [(set (v1i32 FPR32:$Rd),
8504 (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8506 let Predicates = [HasNEON, HasCrypto];
8509 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8511 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8512 SDPatternOperator opnode>
8513 : NeonI_Crypto_3VSHA<size, opcode,
8515 (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8516 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8517 [(set (v4i32 VPR128:$Rd),
8518 (v4i32 (opnode (v4i32 VPR128:$src),
8520 (v4i32 VPR128:$Rm))))],
8522 let Constraints = "$src = $Rd";
8523 let Predicates = [HasNEON, HasCrypto];
8526 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8527 int_arm_neon_sha1su0>;
8528 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8529 int_arm_neon_sha256su1>;
8531 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8532 SDPatternOperator opnode>
8533 : NeonI_Crypto_3VSHA<size, opcode,
8535 (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8536 asmop # "\t$Rd, $Rn, $Rm.4s",
8537 [(set (v4i32 FPR128:$Rd),
8538 (v4i32 (opnode (v4i32 FPR128:$src),
8540 (v4i32 VPR128:$Rm))))],
8542 let Constraints = "$src = $Rd";
8543 let Predicates = [HasNEON, HasCrypto];
8546 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8547 int_arm_neon_sha256h>;
8548 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8549 int_arm_neon_sha256h2>;
8551 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8552 SDPatternOperator opnode>
8553 : NeonI_Crypto_3VSHA<size, opcode,
8555 (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8556 asmop # "\t$Rd, $Rn, $Rm.4s",
8557 [(set (v4i32 FPR128:$Rd),
8558 (v4i32 (opnode (v4i32 FPR128:$src),
8560 (v4i32 VPR128:$Rm))))],
8562 let Constraints = "$src = $Rd";
8563 let Predicates = [HasNEON, HasCrypto];
8566 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8567 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8568 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;