1 //===-- AArch64MCInstLower.cpp - Convert AArch64 MachineInstr to an MCInst -==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower AArch64 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "AArch64AsmPrinter.h"
16 #include "AArch64TargetMachine.h"
17 #include "MCTargetDesc/AArch64MCExpr.h"
18 #include "Utils/AArch64BaseInfo.h"
19 #include "llvm/ADT/SmallString.h"
20 #include "llvm/CodeGen/AsmPrinter.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/Target/Mangler.h"
31 AArch64AsmPrinter::lowerSymbolOperand(const MachineOperand &MO,
32 const MCSymbol *Sym) const {
33 const MCExpr *Expr = 0;
35 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, OutContext);
37 switch (MO.getTargetFlags()) {
38 case AArch64II::MO_GOT:
39 Expr = AArch64MCExpr::CreateGOT(Expr, OutContext);
41 case AArch64II::MO_GOT_LO12:
42 Expr = AArch64MCExpr::CreateGOTLo12(Expr, OutContext);
44 case AArch64II::MO_LO12:
45 Expr = AArch64MCExpr::CreateLo12(Expr, OutContext);
47 case AArch64II::MO_DTPREL_G1:
48 Expr = AArch64MCExpr::CreateDTPREL_G1(Expr, OutContext);
50 case AArch64II::MO_DTPREL_G0_NC:
51 Expr = AArch64MCExpr::CreateDTPREL_G0_NC(Expr, OutContext);
53 case AArch64II::MO_GOTTPREL:
54 Expr = AArch64MCExpr::CreateGOTTPREL(Expr, OutContext);
56 case AArch64II::MO_GOTTPREL_LO12:
57 Expr = AArch64MCExpr::CreateGOTTPRELLo12(Expr, OutContext);
59 case AArch64II::MO_TLSDESC:
60 Expr = AArch64MCExpr::CreateTLSDesc(Expr, OutContext);
62 case AArch64II::MO_TLSDESC_LO12:
63 Expr = AArch64MCExpr::CreateTLSDescLo12(Expr, OutContext);
65 case AArch64II::MO_TPREL_G1:
66 Expr = AArch64MCExpr::CreateTPREL_G1(Expr, OutContext);
68 case AArch64II::MO_TPREL_G0_NC:
69 Expr = AArch64MCExpr::CreateTPREL_G0_NC(Expr, OutContext);
71 case AArch64II::MO_ABS_G3:
72 Expr = AArch64MCExpr::CreateABS_G3(Expr, OutContext);
74 case AArch64II::MO_ABS_G2_NC:
75 Expr = AArch64MCExpr::CreateABS_G2_NC(Expr, OutContext);
77 case AArch64II::MO_ABS_G1_NC:
78 Expr = AArch64MCExpr::CreateABS_G1_NC(Expr, OutContext);
80 case AArch64II::MO_ABS_G0_NC:
81 Expr = AArch64MCExpr::CreateABS_G0_NC(Expr, OutContext);
83 case AArch64II::MO_NO_FLAG:
84 // Expr is already correct
87 llvm_unreachable("Unexpected MachineOperand flag");
90 if (!MO.isJTI() && MO.getOffset())
91 Expr = MCBinaryExpr::CreateAdd(Expr,
92 MCConstantExpr::Create(MO.getOffset(),
96 return MCOperand::CreateExpr(Expr);
99 bool AArch64AsmPrinter::lowerOperand(const MachineOperand &MO,
100 MCOperand &MCOp) const {
101 switch (MO.getType()) {
102 default: llvm_unreachable("unknown operand type");
103 case MachineOperand::MO_Register:
106 assert(!MO.getSubReg() && "Subregs should be eliminated!");
107 MCOp = MCOperand::CreateReg(MO.getReg());
109 case MachineOperand::MO_Immediate:
110 MCOp = MCOperand::CreateImm(MO.getImm());
112 case MachineOperand::MO_BlockAddress:
113 MCOp = lowerSymbolOperand(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
115 case MachineOperand::MO_ExternalSymbol:
116 MCOp = lowerSymbolOperand(MO, GetExternalSymbolSymbol(MO.getSymbolName()));
118 case MachineOperand::MO_GlobalAddress:
119 MCOp = lowerSymbolOperand(MO, Mang->getSymbol(MO.getGlobal()));
121 case MachineOperand::MO_MachineBasicBlock:
122 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
123 MO.getMBB()->getSymbol(), OutContext));
125 case MachineOperand::MO_JumpTableIndex:
126 MCOp = lowerSymbolOperand(MO, GetJTISymbol(MO.getIndex()));
128 case MachineOperand::MO_ConstantPoolIndex:
129 MCOp = lowerSymbolOperand(MO, GetCPISymbol(MO.getIndex()));
131 case MachineOperand::MO_RegisterMask:
132 // Ignore call clobbers
140 void llvm::LowerAArch64MachineInstrToMCInst(const MachineInstr *MI,
142 AArch64AsmPrinter &AP) {
143 OutMI.setOpcode(MI->getOpcode());
145 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
146 const MachineOperand &MO = MI->getOperand(i);
149 if (AP.lowerOperand(MO, MCOp))
150 OutMI.addOperand(MCOp);