1 //===-- AArch64PBQPRegAlloc.cpp - AArch64 specific PBQP constraints -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file contains the AArch64 / Cortex-A57 specific register allocation
10 // constraints for use by the PBQP register allocator.
12 // It is essentially a transcription of what is contained in
13 // AArch64A57FPLoadBalancing, which tries to use a balanced
14 // mix of odd and even D-registers when performing a critical sequence of
15 // independent, non-quadword FP/ASIMD floating-point multiply-accumulates.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "aarch64-pbqp"
21 #include "AArch64PBQPRegAlloc.h"
22 #include "AArch64RegisterInfo.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/RegAllocPBQP.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
37 bool isFPReg(unsigned reg) {
38 return AArch64::FPR32RegClass.contains(reg) ||
39 AArch64::FPR64RegClass.contains(reg) ||
40 AArch64::FPR128RegClass.contains(reg);
44 bool isOdd(unsigned reg) {
47 llvm_unreachable("Register is not from the expected class !");
150 bool haveSameParity(unsigned reg1, unsigned reg2) {
151 assert(isFPReg(reg1) && "Expecting an FP register for reg1");
152 assert(isFPReg(reg2) && "Expecting an FP register for reg2");
154 return isOdd(reg1) == isOdd(reg2);
159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd,
164 LiveIntervals &LIs = G.getMetadata().LIS;
166 if (TRI->isPhysicalRegister(Rd) || TRI->isPhysicalRegister(Ra)) {
167 DEBUG(dbgs() << "Rd is a physical reg:" << TRI->isPhysicalRegister(Rd)
169 DEBUG(dbgs() << "Ra is a physical reg:" << TRI->isPhysicalRegister(Ra)
174 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
175 PBQPRAGraph::NodeId node2 = G.getMetadata().getNodeIdForVReg(Ra);
177 const PBQPRAGraph::NodeMetadata::AllowedRegVector *vRdAllowed =
178 &G.getNodeMetadata(node1).getAllowedRegs();
179 const PBQPRAGraph::NodeMetadata::AllowedRegVector *vRaAllowed =
180 &G.getNodeMetadata(node2).getAllowedRegs();
182 PBQPRAGraph::EdgeId edge = G.findEdge(node1, node2);
184 // The edge does not exist. Create one with the appropriate interference
186 if (edge == G.invalidEdgeId()) {
187 const LiveInterval &ld = LIs.getInterval(Rd);
188 const LiveInterval &la = LIs.getInterval(Ra);
189 bool livesOverlap = ld.overlaps(la);
191 PBQPRAGraph::RawMatrix costs(vRdAllowed->size() + 1,
192 vRaAllowed->size() + 1, 0);
193 for (unsigned i = 0, ie = vRdAllowed->size(); i != ie; ++i) {
194 unsigned pRd = (*vRdAllowed)[i];
195 for (unsigned j = 0, je = vRaAllowed->size(); j != je; ++j) {
196 unsigned pRa = (*vRaAllowed)[j];
197 if (livesOverlap && TRI->regsOverlap(pRd, pRa))
198 costs[i + 1][j + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
200 costs[i + 1][j + 1] = haveSameParity(pRd, pRa) ? 0.0 : 1.0;
203 G.addEdge(node1, node2, std::move(costs));
207 if (G.getEdgeNode1Id(edge) == node2) {
208 std::swap(node1, node2);
209 std::swap(vRdAllowed, vRaAllowed);
212 // Enforce minCost(sameParity(RaClass)) > maxCost(otherParity(RdClass))
213 PBQPRAGraph::RawMatrix costs(G.getEdgeCosts(edge));
214 for (unsigned i = 0, ie = vRdAllowed->size(); i != ie; ++i) {
215 unsigned pRd = (*vRdAllowed)[i];
217 // Get the maximum cost (excluding unallocatable reg) for same parity
219 PBQP::PBQPNum sameParityMax = std::numeric_limits<PBQP::PBQPNum>::min();
220 for (unsigned j = 0, je = vRaAllowed->size(); j != je; ++j) {
221 unsigned pRa = (*vRaAllowed)[j];
222 if (haveSameParity(pRd, pRa))
223 if (costs[i + 1][j + 1] !=
224 std::numeric_limits<PBQP::PBQPNum>::infinity() &&
225 costs[i + 1][j + 1] > sameParityMax)
226 sameParityMax = costs[i + 1][j + 1];
229 // Ensure all registers with a different parity have a higher cost
230 // than sameParityMax
231 for (unsigned j = 0, je = vRaAllowed->size(); j != je; ++j) {
232 unsigned pRa = (*vRaAllowed)[j];
233 if (!haveSameParity(pRd, pRa))
234 if (sameParityMax > costs[i + 1][j + 1])
235 costs[i + 1][j + 1] = sameParityMax + 1.0;
238 G.updateEdgeCosts(edge, std::move(costs));
243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd,
245 LiveIntervals &LIs = G.getMetadata().LIS;
247 // Do some Chain management
248 if (Chains.count(Ra)) {
250 DEBUG(dbgs() << "Moving acc chain from " << PrintReg(Ra, TRI) << " to "
251 << PrintReg(Rd, TRI) << '\n';);
256 DEBUG(dbgs() << "Creating new acc chain for " << PrintReg(Rd, TRI)
261 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
263 const LiveInterval &ld = LIs.getInterval(Rd);
264 for (auto r : Chains) {
269 const LiveInterval &lr = LIs.getInterval(r);
270 if (ld.overlaps(lr)) {
271 const PBQPRAGraph::NodeMetadata::AllowedRegVector *vRdAllowed =
272 &G.getNodeMetadata(node1).getAllowedRegs();
274 PBQPRAGraph::NodeId node2 = G.getMetadata().getNodeIdForVReg(r);
275 const PBQPRAGraph::NodeMetadata::AllowedRegVector *vRrAllowed =
276 &G.getNodeMetadata(node2).getAllowedRegs();
278 PBQPRAGraph::EdgeId edge = G.findEdge(node1, node2);
279 assert(edge != G.invalidEdgeId() &&
280 "PBQP error ! The edge should exist !");
282 DEBUG(dbgs() << "Refining constraint !\n";);
284 if (G.getEdgeNode1Id(edge) == node2) {
285 std::swap(node1, node2);
286 std::swap(vRdAllowed, vRrAllowed);
289 // Enforce that cost is higher with all other Chains of the same parity
290 PBQP::Matrix costs(G.getEdgeCosts(edge));
291 for (unsigned i = 0, ie = vRdAllowed->size(); i != ie; ++i) {
292 unsigned pRd = (*vRdAllowed)[i];
294 // Get the maximum cost (excluding unallocatable reg) for all other
296 PBQP::PBQPNum sameParityMax = std::numeric_limits<PBQP::PBQPNum>::min();
297 for (unsigned j = 0, je = vRrAllowed->size(); j != je; ++j) {
298 unsigned pRa = (*vRrAllowed)[j];
299 if (!haveSameParity(pRd, pRa))
300 if (costs[i + 1][j + 1] !=
301 std::numeric_limits<PBQP::PBQPNum>::infinity() &&
302 costs[i + 1][j + 1] > sameParityMax)
303 sameParityMax = costs[i + 1][j + 1];
306 // Ensure all registers with same parity have a higher cost
307 // than sameParityMax
308 for (unsigned j = 0, je = vRrAllowed->size(); j != je; ++j) {
309 unsigned pRa = (*vRrAllowed)[j];
310 if (haveSameParity(pRd, pRa))
311 if (sameParityMax > costs[i + 1][j + 1])
312 costs[i + 1][j + 1] = sameParityMax + 1.0;
315 G.updateEdgeCosts(edge, std::move(costs));
320 static bool regJustKilledBefore(const LiveIntervals &LIs, unsigned reg,
321 const MachineInstr &MI) {
322 LiveInterval LI = LIs.getInterval(reg);
323 SlotIndex SI = LIs.getInstructionIndex(&MI);
324 return LI.expiredAt(SI);
327 void A57ChainingConstraint::apply(PBQPRAGraph &G) {
328 const MachineFunction &MF = G.getMetadata().MF;
329 LiveIntervals &LIs = G.getMetadata().LIS;
331 TRI = MF.getSubtarget().getRegisterInfo();
334 for (const auto &MBB: MF) {
335 Chains.clear(); // FIXME: really needed ? Could not work at MF level ?
337 for (const auto &MI: MBB) {
339 // Forget Chains which have expired
340 for (auto r : Chains) {
341 SmallVector<unsigned, 8> toDel;
342 if(regJustKilledBefore(LIs, r, MI)) {
343 DEBUG(dbgs() << "Killing chain " << PrintReg(r, TRI) << " at ";
348 while (!toDel.empty()) {
349 Chains.remove(toDel.back());
354 switch (MI.getOpcode()) {
355 case AArch64::FMSUBSrrr:
356 case AArch64::FMADDSrrr:
357 case AArch64::FNMSUBSrrr:
358 case AArch64::FNMADDSrrr:
359 case AArch64::FMSUBDrrr:
360 case AArch64::FMADDDrrr:
361 case AArch64::FNMSUBDrrr:
362 case AArch64::FNMADDDrrr: {
363 unsigned Rd = MI.getOperand(0).getReg();
364 unsigned Ra = MI.getOperand(3).getReg();
366 if (addIntraChainConstraint(G, Rd, Ra))
367 addInterChainConstraint(G, Rd, Ra);
371 case AArch64::FMLAv2f32:
372 case AArch64::FMLSv2f32: {
373 unsigned Rd = MI.getOperand(0).getReg();
374 addInterChainConstraint(G, Rd, Rd);