1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64Subtarget.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/Target/TargetFrameLowering.h"
30 #include "llvm/Target/TargetOptions.h"
34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
38 ReserveX18("aarch64-reserve-x18", cl::Hidden,
39 cl::desc("Reserve X18, making it unavailable as GPR"));
41 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
42 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
45 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
46 assert(MF && "Invalid MachineFunction pointer.");
47 if (MF->getFunction()->getCallingConv() == CallingConv::GHC)
48 // GHC set of callee saved regs is empty as all those regs are
49 // used for passing STG regs around
50 return CSR_AArch64_NoRegs_SaveList;
51 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
52 return CSR_AArch64_AllRegs_SaveList;
54 return CSR_AArch64_AAPCS_SaveList;
58 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
59 CallingConv::ID CC) const {
60 if (CC == CallingConv::GHC)
61 // This is academic becase all GHC calls are (supposed to be) tail calls
62 return CSR_AArch64_NoRegs_RegMask;
63 if (CC == CallingConv::AnyReg)
64 return CSR_AArch64_AllRegs_RegMask;
66 return CSR_AArch64_AAPCS_RegMask;
69 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
71 return CSR_AArch64_TLS_Darwin_RegMask;
73 assert(TT.isOSBinFormatELF() && "only expect Darwin or ELF TLS");
74 return CSR_AArch64_TLS_ELF_RegMask;
78 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
79 CallingConv::ID CC) const {
80 // This should return a register mask that is the same as that returned by
81 // getCallPreservedMask but that additionally preserves the register used for
82 // the first i64 argument (which must also be the register used to return a
83 // single i64 return value)
85 // In case that the calling convention does not use the same register for
86 // both, the function should return NULL (does not currently apply)
87 assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
88 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
92 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
93 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
95 // FIXME: avoid re-calculating this every time.
96 BitVector Reserved(getNumRegs());
97 Reserved.set(AArch64::SP);
98 Reserved.set(AArch64::XZR);
99 Reserved.set(AArch64::WSP);
100 Reserved.set(AArch64::WZR);
102 if (TFI->hasFP(MF) || TT.isOSDarwin()) {
103 Reserved.set(AArch64::FP);
104 Reserved.set(AArch64::W29);
107 if (TT.isOSDarwin() || ReserveX18) {
108 Reserved.set(AArch64::X18); // Platform register
109 Reserved.set(AArch64::W18);
112 if (hasBasePointer(MF)) {
113 Reserved.set(AArch64::X19);
114 Reserved.set(AArch64::W19);
120 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
121 unsigned Reg) const {
122 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
134 return TT.isOSDarwin() || ReserveX18;
137 return TFI->hasFP(MF) || TT.isOSDarwin();
140 return hasBasePointer(MF);
146 const TargetRegisterClass *
147 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
148 unsigned Kind) const {
149 return &AArch64::GPR64RegClass;
152 const TargetRegisterClass *
153 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
154 if (RC == &AArch64::CCRRegClass)
155 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
159 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
161 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
162 const MachineFrameInfo *MFI = MF.getFrameInfo();
164 // In the presence of variable sized objects, if the fixed stack size is
165 // large enough that referencing from the FP won't result in things being
166 // in range relatively often, we can use a base pointer to allow access
167 // from the other direction like the SP normally works.
168 // Furthermore, if both variable sized objects are present, and the
169 // stack needs to be dynamically re-aligned, the base pointer is the only
170 // reliable way to reference the locals.
171 if (MFI->hasVarSizedObjects()) {
172 if (needsStackRealignment(MF))
174 // Conservatively estimate whether the negative offset from the frame
175 // pointer will be sufficient to reach. If a function has a smallish
176 // frame, it's less likely to have lots of spills and callee saved
177 // space, so it's all more likely to be within range of the frame pointer.
178 // If it's wrong, we'll materialize the constant and still get to the
179 // object; it's just suboptimal. Negative offsets use the unscaled
180 // load/store instructions, which have a 9-bit signed immediate.
181 if (MFI->getLocalFrameSize() < 256)
189 bool AArch64RegisterInfo::canRealignStack(const MachineFunction &MF) const {
191 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
197 // FIXME: share this with other backends with identical implementation?
199 AArch64RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
200 const MachineFrameInfo *MFI = MF.getFrameInfo();
201 const Function *F = MF.getFunction();
202 unsigned StackAlign = MF.getTarget()
203 .getSubtargetImpl(*MF.getFunction())
205 ->getStackAlignment();
206 bool requiresRealignment =
207 ((MFI->getMaxAlignment() > StackAlign) ||
208 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
209 Attribute::StackAlignment));
211 return requiresRealignment && canRealignStack(MF);
215 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
216 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
218 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
221 bool AArch64RegisterInfo::requiresRegisterScavenging(
222 const MachineFunction &MF) const {
226 bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
227 const MachineFunction &MF) const {
232 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
233 const MachineFrameInfo *MFI = MF.getFrameInfo();
234 // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
235 // to the stack pointer, so only put the emergency spill slot next to the
236 // FP when there's no better way to access it (SP or base pointer).
237 return MFI->hasVarSizedObjects() && !hasBasePointer(MF);
240 bool AArch64RegisterInfo::requiresFrameIndexScavenging(
241 const MachineFunction &MF) const {
246 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
247 const MachineFrameInfo *MFI = MF.getFrameInfo();
248 // Only consider eliminating leaf frames.
249 if (MFI->hasCalls() || (MF.getTarget().Options.DisableFramePointerElim(MF) &&
250 MFI->adjustsStack()))
252 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
255 /// needsFrameBaseReg - Returns true if the instruction's frame index
256 /// reference would be better served by a base register other than FP
257 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
258 /// references it should create new base registers for.
259 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
260 int64_t Offset) const {
261 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
262 assert(i < MI->getNumOperands() &&
263 "Instr doesn't have FrameIndex operand!");
265 // It's the load/store FI references that cause issues, as it can be difficult
266 // to materialize the offset if it won't fit in the literal field. Estimate
267 // based on the size of the local frame and some conservative assumptions
268 // about the rest of the stack frame (note, this is pre-regalloc, so
269 // we don't know everything for certain yet) whether this offset is likely
270 // to be out of range of the immediate. Return true if so.
272 // We only generate virtual base registers for loads and stores, so
273 // return false for everything else.
274 if (!MI->mayLoad() && !MI->mayStore())
277 // Without a virtual base register, if the function has variable sized
278 // objects, all fixed-size local references will be via the frame pointer,
279 // Approximate the offset and see if it's legal for the instruction.
280 // Note that the incoming offset is based on the SP value at function entry,
281 // so it'll be negative.
282 MachineFunction &MF = *MI->getParent()->getParent();
283 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
284 MachineFrameInfo *MFI = MF.getFrameInfo();
286 // Estimate an offset from the frame pointer.
287 // Conservatively assume all GPR callee-saved registers get pushed.
288 // FP, LR, X19-X28, D8-D15. 64-bits each.
289 int64_t FPOffset = Offset - 16 * 20;
290 // Estimate an offset from the stack pointer.
291 // The incoming offset is relating to the SP at the start of the function,
292 // but when we access the local it'll be relative to the SP after local
293 // allocation, so adjust our SP-relative offset by that allocation size.
294 Offset += MFI->getLocalFrameSize();
295 // Assume that we'll have at least some spill slots allocated.
296 // FIXME: This is a total SWAG number. We should run some statistics
297 // and pick a real one.
298 Offset += 128; // 128 bytes of spill slots
300 // If there is a frame pointer, try using it.
301 // The FP is only available if there is no dynamic realignment. We
302 // don't know for sure yet whether we'll need that, so we guess based
303 // on whether there are any local variables that would trigger it.
304 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
307 // If we can reference via the stack pointer or base pointer, try that.
308 // FIXME: This (and the code that resolves the references) can be improved
309 // to only disallow SP relative references in the live range of
310 // the VLA(s). In practice, it's unclear how much difference that
311 // would make, but it may be worth doing.
312 if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
315 // The offset likely isn't legal; we want to allocate a virtual base register.
319 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
321 int64_t Offset) const {
322 assert(Offset <= INT_MAX && "Offset too big to fit in int.");
323 assert(MI && "Unable to get the legal offset for nil instruction.");
324 int SaveOffset = Offset;
325 return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
328 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
329 /// at the beginning of the basic block.
330 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
333 int64_t Offset) const {
334 MachineBasicBlock::iterator Ins = MBB->begin();
335 DebugLoc DL; // Defaults to "unknown"
336 if (Ins != MBB->end())
337 DL = Ins->getDebugLoc();
338 const MachineFunction &MF = *MBB->getParent();
339 const AArch64InstrInfo *TII =
340 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
341 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
342 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
343 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
344 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
346 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
347 .addFrameIndex(FrameIdx)
352 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
353 int64_t Offset) const {
354 int Off = Offset; // ARM doesn't need the general 64-bit offsets
357 while (!MI.getOperand(i).isFI()) {
359 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
361 const MachineFunction *MF = MI.getParent()->getParent();
362 const AArch64InstrInfo *TII =
363 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
364 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
365 assert(Done && "Unable to resolve frame index!");
369 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
370 int SPAdj, unsigned FIOperandNum,
371 RegScavenger *RS) const {
372 assert(SPAdj == 0 && "Unexpected");
374 MachineInstr &MI = *II;
375 MachineBasicBlock &MBB = *MI.getParent();
376 MachineFunction &MF = *MBB.getParent();
377 const AArch64InstrInfo *TII =
378 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
379 const AArch64FrameLowering *TFI = static_cast<const AArch64FrameLowering *>(
380 MF.getSubtarget().getFrameLowering());
382 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
386 // Special handling of dbg_value, stackmap and patchpoint instructions.
387 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
388 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
389 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
391 Offset += MI.getOperand(FIOperandNum + 1).getImm();
392 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
393 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
397 // Modify MI as necessary to handle as much of 'Offset' as possible
398 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
399 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
402 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
403 "Emergency spill slot is out of reach");
405 // If we get here, the immediate doesn't fit into the instruction. We folded
406 // as much as possible above. Handle the rest, providing a register that is
408 unsigned ScratchReg =
409 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
410 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
411 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
416 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
417 MachineFunction &MF) const {
418 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
420 switch (RC->getID()) {
423 case AArch64::GPR32RegClassID:
424 case AArch64::GPR32spRegClassID:
425 case AArch64::GPR32allRegClassID:
426 case AArch64::GPR64spRegClassID:
427 case AArch64::GPR64allRegClassID:
428 case AArch64::GPR64RegClassID:
429 case AArch64::GPR32commonRegClassID:
430 case AArch64::GPR64commonRegClassID:
431 return 32 - 1 // XZR/SP
432 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
433 - (TT.isOSDarwin() || ReserveX18) // X18 reserved as platform register
434 - hasBasePointer(MF); // X19
435 case AArch64::FPR8RegClassID:
436 case AArch64::FPR16RegClassID:
437 case AArch64::FPR32RegClassID:
438 case AArch64::FPR64RegClassID:
439 case AArch64::FPR128RegClassID:
442 case AArch64::DDRegClassID:
443 case AArch64::DDDRegClassID:
444 case AArch64::DDDDRegClassID:
445 case AArch64::QQRegClassID:
446 case AArch64::QQQRegClassID:
447 case AArch64::QQQQRegClassID:
450 case AArch64::FPR128_loRegClassID: