1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64Subtarget.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/Target/TargetFrameLowering.h"
30 #include "llvm/Target/TargetOptions.h"
34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
37 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
38 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
41 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
42 assert(MF && "Invalid MachineFunction pointer.");
43 if (MF->getFunction()->getCallingConv() == CallingConv::GHC)
44 // GHC set of callee saved regs is empty as all those regs are
45 // used for passing STG regs around
46 return CSR_AArch64_NoRegs_SaveList;
47 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
48 return CSR_AArch64_AllRegs_SaveList;
50 return CSR_AArch64_AAPCS_SaveList;
54 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
55 CallingConv::ID CC) const {
56 if (CC == CallingConv::GHC)
57 // This is academic becase all GHC calls are (supposed to be) tail calls
58 return CSR_AArch64_NoRegs_RegMask;
59 if (CC == CallingConv::AnyReg)
60 return CSR_AArch64_AllRegs_RegMask;
62 return CSR_AArch64_AAPCS_RegMask;
65 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
67 return CSR_AArch64_TLS_Darwin_RegMask;
69 assert(TT.isOSBinFormatELF() && "only expect Darwin or ELF TLS");
70 return CSR_AArch64_TLS_ELF_RegMask;
74 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
75 CallingConv::ID CC) const {
76 // This should return a register mask that is the same as that returned by
77 // getCallPreservedMask but that additionally preserves the register used for
78 // the first i64 argument (which must also be the register used to return a
79 // single i64 return value)
81 // In case that the calling convention does not use the same register for
82 // both, the function should return NULL (does not currently apply)
83 assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
84 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
88 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
89 const AArch64FrameLowering *TFI = getFrameLowering(MF);
91 // FIXME: avoid re-calculating this every time.
92 BitVector Reserved(getNumRegs());
93 Reserved.set(AArch64::SP);
94 Reserved.set(AArch64::XZR);
95 Reserved.set(AArch64::WSP);
96 Reserved.set(AArch64::WZR);
98 if (TFI->hasFP(MF) || TT.isOSDarwin()) {
99 Reserved.set(AArch64::FP);
100 Reserved.set(AArch64::W29);
103 if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved()) {
104 Reserved.set(AArch64::X18); // Platform register
105 Reserved.set(AArch64::W18);
108 if (hasBasePointer(MF)) {
109 Reserved.set(AArch64::X19);
110 Reserved.set(AArch64::W19);
116 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
117 unsigned Reg) const {
118 const AArch64FrameLowering *TFI = getFrameLowering(MF);
130 return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
133 return TFI->hasFP(MF) || TT.isOSDarwin();
136 return hasBasePointer(MF);
142 const TargetRegisterClass *
143 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
144 unsigned Kind) const {
145 return &AArch64::GPR64RegClass;
148 const TargetRegisterClass *
149 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
150 if (RC == &AArch64::CCRRegClass)
151 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
155 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
157 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
158 const MachineFrameInfo *MFI = MF.getFrameInfo();
160 // In the presence of variable sized objects, if the fixed stack size is
161 // large enough that referencing from the FP won't result in things being
162 // in range relatively often, we can use a base pointer to allow access
163 // from the other direction like the SP normally works.
164 // Furthermore, if both variable sized objects are present, and the
165 // stack needs to be dynamically re-aligned, the base pointer is the only
166 // reliable way to reference the locals.
167 if (MFI->hasVarSizedObjects()) {
168 if (needsStackRealignment(MF))
170 // Conservatively estimate whether the negative offset from the frame
171 // pointer will be sufficient to reach. If a function has a smallish
172 // frame, it's less likely to have lots of spills and callee saved
173 // space, so it's all more likely to be within range of the frame pointer.
174 // If it's wrong, we'll materialize the constant and still get to the
175 // object; it's just suboptimal. Negative offsets use the unscaled
176 // load/store instructions, which have a 9-bit signed immediate.
177 if (MFI->getLocalFrameSize() < 256)
186 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
187 const AArch64FrameLowering *TFI = getFrameLowering(MF);
188 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
191 bool AArch64RegisterInfo::requiresRegisterScavenging(
192 const MachineFunction &MF) const {
196 bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
197 const MachineFunction &MF) const {
202 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
203 const MachineFrameInfo *MFI = MF.getFrameInfo();
204 // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
205 // to the stack pointer, so only put the emergency spill slot next to the
206 // FP when there's no better way to access it (SP or base pointer).
207 return MFI->hasVarSizedObjects() && !hasBasePointer(MF);
210 bool AArch64RegisterInfo::requiresFrameIndexScavenging(
211 const MachineFunction &MF) const {
216 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
217 const MachineFrameInfo *MFI = MF.getFrameInfo();
218 // Only consider eliminating leaf frames.
219 if (MFI->hasCalls() || (MF.getTarget().Options.DisableFramePointerElim(MF) &&
220 MFI->adjustsStack()))
222 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
225 /// needsFrameBaseReg - Returns true if the instruction's frame index
226 /// reference would be better served by a base register other than FP
227 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
228 /// references it should create new base registers for.
229 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
230 int64_t Offset) const {
231 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
232 assert(i < MI->getNumOperands() &&
233 "Instr doesn't have FrameIndex operand!");
235 // It's the load/store FI references that cause issues, as it can be difficult
236 // to materialize the offset if it won't fit in the literal field. Estimate
237 // based on the size of the local frame and some conservative assumptions
238 // about the rest of the stack frame (note, this is pre-regalloc, so
239 // we don't know everything for certain yet) whether this offset is likely
240 // to be out of range of the immediate. Return true if so.
242 // We only generate virtual base registers for loads and stores, so
243 // return false for everything else.
244 if (!MI->mayLoad() && !MI->mayStore())
247 // Without a virtual base register, if the function has variable sized
248 // objects, all fixed-size local references will be via the frame pointer,
249 // Approximate the offset and see if it's legal for the instruction.
250 // Note that the incoming offset is based on the SP value at function entry,
251 // so it'll be negative.
252 MachineFunction &MF = *MI->getParent()->getParent();
253 const AArch64FrameLowering *TFI = getFrameLowering(MF);
254 MachineFrameInfo *MFI = MF.getFrameInfo();
256 // Estimate an offset from the frame pointer.
257 // Conservatively assume all GPR callee-saved registers get pushed.
258 // FP, LR, X19-X28, D8-D15. 64-bits each.
259 int64_t FPOffset = Offset - 16 * 20;
260 // Estimate an offset from the stack pointer.
261 // The incoming offset is relating to the SP at the start of the function,
262 // but when we access the local it'll be relative to the SP after local
263 // allocation, so adjust our SP-relative offset by that allocation size.
264 Offset += MFI->getLocalFrameSize();
265 // Assume that we'll have at least some spill slots allocated.
266 // FIXME: This is a total SWAG number. We should run some statistics
267 // and pick a real one.
268 Offset += 128; // 128 bytes of spill slots
270 // If there is a frame pointer, try using it.
271 // The FP is only available if there is no dynamic realignment. We
272 // don't know for sure yet whether we'll need that, so we guess based
273 // on whether there are any local variables that would trigger it.
274 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
277 // If we can reference via the stack pointer or base pointer, try that.
278 // FIXME: This (and the code that resolves the references) can be improved
279 // to only disallow SP relative references in the live range of
280 // the VLA(s). In practice, it's unclear how much difference that
281 // would make, but it may be worth doing.
282 if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
285 // The offset likely isn't legal; we want to allocate a virtual base register.
289 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
291 int64_t Offset) const {
292 assert(Offset <= INT_MAX && "Offset too big to fit in int.");
293 assert(MI && "Unable to get the legal offset for nil instruction.");
294 int SaveOffset = Offset;
295 return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
298 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
299 /// at the beginning of the basic block.
300 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
303 int64_t Offset) const {
304 MachineBasicBlock::iterator Ins = MBB->begin();
305 DebugLoc DL; // Defaults to "unknown"
306 if (Ins != MBB->end())
307 DL = Ins->getDebugLoc();
308 const MachineFunction &MF = *MBB->getParent();
309 const AArch64InstrInfo *TII =
310 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
311 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
312 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
313 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
314 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
316 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
317 .addFrameIndex(FrameIdx)
322 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
323 int64_t Offset) const {
324 int Off = Offset; // ARM doesn't need the general 64-bit offsets
327 while (!MI.getOperand(i).isFI()) {
329 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
331 const MachineFunction *MF = MI.getParent()->getParent();
332 const AArch64InstrInfo *TII =
333 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
334 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
335 assert(Done && "Unable to resolve frame index!");
339 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
340 int SPAdj, unsigned FIOperandNum,
341 RegScavenger *RS) const {
342 assert(SPAdj == 0 && "Unexpected");
344 MachineInstr &MI = *II;
345 MachineBasicBlock &MBB = *MI.getParent();
346 MachineFunction &MF = *MBB.getParent();
347 const AArch64InstrInfo *TII =
348 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
349 const AArch64FrameLowering *TFI = getFrameLowering(MF);
351 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
355 // Special handling of dbg_value, stackmap and patchpoint instructions.
356 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
357 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
358 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
360 Offset += MI.getOperand(FIOperandNum + 1).getImm();
361 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
362 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
366 // Modify MI as necessary to handle as much of 'Offset' as possible
367 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
368 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
371 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
372 "Emergency spill slot is out of reach");
374 // If we get here, the immediate doesn't fit into the instruction. We folded
375 // as much as possible above. Handle the rest, providing a register that is
377 unsigned ScratchReg =
378 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
379 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
380 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
385 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
386 MachineFunction &MF) const {
387 const AArch64FrameLowering *TFI = getFrameLowering(MF);
389 switch (RC->getID()) {
392 case AArch64::GPR32RegClassID:
393 case AArch64::GPR32spRegClassID:
394 case AArch64::GPR32allRegClassID:
395 case AArch64::GPR64spRegClassID:
396 case AArch64::GPR64allRegClassID:
397 case AArch64::GPR64RegClassID:
398 case AArch64::GPR32commonRegClassID:
399 case AArch64::GPR64commonRegClassID:
400 return 32 - 1 // XZR/SP
401 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
402 - MF.getSubtarget<AArch64Subtarget>()
403 .isX18Reserved() // X18 reserved as platform register
404 - hasBasePointer(MF); // X19
405 case AArch64::FPR8RegClassID:
406 case AArch64::FPR16RegClassID:
407 case AArch64::FPR32RegClassID:
408 case AArch64::FPR64RegClassID:
409 case AArch64::FPR128RegClassID:
412 case AArch64::DDRegClassID:
413 case AArch64::DDDRegClassID:
414 case AArch64::DDDDRegClassID:
415 case AArch64::QQRegClassID:
416 case AArch64::QQQRegClassID:
417 case AArch64::QQQQRegClassID:
420 case AArch64::FPR128_loRegClassID: