1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #include "AArch64RegisterInfo.h"
17 #include "AArch64FrameLowering.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64TargetMachine.h"
20 #include "MCTargetDesc/AArch64MCTargetDesc.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/ADT/BitVector.h"
27 #define GET_REGINFO_TARGET_DESC
28 #include "AArch64GenRegisterInfo.inc"
32 AArch64RegisterInfo::AArch64RegisterInfo(const AArch64InstrInfo &tii,
33 const AArch64Subtarget &sti)
34 : AArch64GenRegisterInfo(AArch64::X30), TII(tii) {
38 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
39 return CSR_PCS_SaveList;
43 AArch64RegisterInfo::getCallPreservedMask(CallingConv::ID) const {
44 return CSR_PCS_RegMask;
47 const uint32_t *AArch64RegisterInfo::getTLSDescCallPreservedMask() const {
48 return TLSDesc_RegMask;
51 const TargetRegisterClass *
52 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
53 if (RC == &AArch64::FlagClassRegClass)
54 return &AArch64::GPR64RegClass;
62 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
63 BitVector Reserved(getNumRegs());
64 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
66 Reserved.set(AArch64::XSP);
67 Reserved.set(AArch64::WSP);
69 Reserved.set(AArch64::XZR);
70 Reserved.set(AArch64::WZR);
73 Reserved.set(AArch64::X29);
74 Reserved.set(AArch64::W29);
81 AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI,
83 unsigned FIOperandNum,
84 RegScavenger *RS) const {
85 assert(SPAdj == 0 && "Cannot deal with nonzero SPAdj yet");
86 MachineInstr &MI = *MBBI;
87 MachineBasicBlock &MBB = *MI.getParent();
88 MachineFunction &MF = *MBB.getParent();
89 MachineFrameInfo *MFI = MF.getFrameInfo();
90 const AArch64FrameLowering *TFI =
91 static_cast<const AArch64FrameLowering *>(MF.getTarget().getFrameLowering());
93 // In order to work out the base and offset for addressing, the FrameLowering
94 // code needs to know (sometimes) whether the instruction is storing/loading a
95 // callee-saved register, or whether it's a more generic
96 // operation. Fortunately the frame indices are used *only* for that purpose
97 // and are contiguous, so we can check here.
98 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
103 MinCSFI = CSI[0].getFrameIdx();
104 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
107 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
108 bool IsCalleeSaveOp = FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI;
112 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj,
115 Offset += MI.getOperand(FIOperandNum + 1).getImm();
117 // DBG_VALUE instructions have no real restrictions so they can be handled
119 if (MI.isDebugValue()) {
120 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/ false);
121 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
125 int MinOffset, MaxOffset, OffsetScale;
126 if (MI.getOpcode() == AArch64::ADDxxi_lsl0_s) {
131 // Load/store of a stack object
132 TII.getAddressConstraints(MI, OffsetScale, MinOffset, MaxOffset);
135 // The frame lowering has told us a base and offset it thinks we should use to
136 // access this variable, but it's still up to us to make sure the values are
137 // legal for the instruction in question.
138 if (Offset % OffsetScale != 0 || Offset < MinOffset || Offset > MaxOffset) {
140 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
141 emitRegUpdate(MBB, MBBI, MBBI->getDebugLoc(), TII,
142 BaseReg, FrameReg, BaseReg, Offset);
147 // Negative offsets are expected if we address from FP, but for
148 // now this checks nothing has gone horribly wrong.
149 assert(Offset >= 0 && "Unexpected negative offset from SP");
151 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, true);
152 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset / OffsetScale);
156 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
157 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
166 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
167 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
168 const AArch64FrameLowering *AFI
169 = static_cast<const AArch64FrameLowering*>(TFI);
170 return AFI->useFPForAddressing(MF);