1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64Subtarget.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/Target/TargetFrameLowering.h"
30 #include "llvm/Target/TargetOptions.h"
34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
37 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
38 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
41 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
42 assert(MF && "Invalid MachineFunction pointer.");
43 if (MF->getFunction()->getCallingConv() == CallingConv::GHC)
44 // GHC set of callee saved regs is empty as all those regs are
45 // used for passing STG regs around
46 return CSR_AArch64_NoRegs_SaveList;
47 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
48 return CSR_AArch64_AllRegs_SaveList;
49 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS)
50 return CSR_AArch64_CXX_TLS_Darwin_SaveList;
52 return CSR_AArch64_AAPCS_SaveList;
56 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
57 CallingConv::ID CC) const {
58 if (CC == CallingConv::GHC)
59 // This is academic becase all GHC calls are (supposed to be) tail calls
60 return CSR_AArch64_NoRegs_RegMask;
61 if (CC == CallingConv::AnyReg)
62 return CSR_AArch64_AllRegs_RegMask;
63 if (CC == CallingConv::CXX_FAST_TLS)
64 return CSR_AArch64_CXX_TLS_Darwin_RegMask;
66 return CSR_AArch64_AAPCS_RegMask;
69 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
71 return CSR_AArch64_TLS_Darwin_RegMask;
73 assert(TT.isOSBinFormatELF() && "only expect Darwin or ELF TLS");
74 return CSR_AArch64_TLS_ELF_RegMask;
78 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
79 CallingConv::ID CC) const {
80 // This should return a register mask that is the same as that returned by
81 // getCallPreservedMask but that additionally preserves the register used for
82 // the first i64 argument (which must also be the register used to return a
83 // single i64 return value)
85 // In case that the calling convention does not use the same register for
86 // both, the function should return NULL (does not currently apply)
87 assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
88 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
92 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
93 const AArch64FrameLowering *TFI = getFrameLowering(MF);
95 // FIXME: avoid re-calculating this every time.
96 BitVector Reserved(getNumRegs());
97 Reserved.set(AArch64::SP);
98 Reserved.set(AArch64::XZR);
99 Reserved.set(AArch64::WSP);
100 Reserved.set(AArch64::WZR);
102 if (TFI->hasFP(MF) || TT.isOSDarwin()) {
103 Reserved.set(AArch64::FP);
104 Reserved.set(AArch64::W29);
107 if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved()) {
108 Reserved.set(AArch64::X18); // Platform register
109 Reserved.set(AArch64::W18);
112 if (hasBasePointer(MF)) {
113 Reserved.set(AArch64::X19);
114 Reserved.set(AArch64::W19);
120 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
121 unsigned Reg) const {
122 const AArch64FrameLowering *TFI = getFrameLowering(MF);
134 return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
137 return TFI->hasFP(MF) || TT.isOSDarwin();
140 return hasBasePointer(MF);
146 const TargetRegisterClass *
147 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
148 unsigned Kind) const {
149 return &AArch64::GPR64RegClass;
152 const TargetRegisterClass *
153 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
154 if (RC == &AArch64::CCRRegClass)
155 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
159 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
161 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
162 const MachineFrameInfo *MFI = MF.getFrameInfo();
164 // In the presence of variable sized objects, if the fixed stack size is
165 // large enough that referencing from the FP won't result in things being
166 // in range relatively often, we can use a base pointer to allow access
167 // from the other direction like the SP normally works.
168 // Furthermore, if both variable sized objects are present, and the
169 // stack needs to be dynamically re-aligned, the base pointer is the only
170 // reliable way to reference the locals.
171 if (MFI->hasVarSizedObjects()) {
172 if (needsStackRealignment(MF))
174 // Conservatively estimate whether the negative offset from the frame
175 // pointer will be sufficient to reach. If a function has a smallish
176 // frame, it's less likely to have lots of spills and callee saved
177 // space, so it's all more likely to be within range of the frame pointer.
178 // If it's wrong, we'll materialize the constant and still get to the
179 // object; it's just suboptimal. Negative offsets use the unscaled
180 // load/store instructions, which have a 9-bit signed immediate.
181 if (MFI->getLocalFrameSize() < 256)
190 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
191 const AArch64FrameLowering *TFI = getFrameLowering(MF);
192 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
195 bool AArch64RegisterInfo::requiresRegisterScavenging(
196 const MachineFunction &MF) const {
200 bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
201 const MachineFunction &MF) const {
206 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
207 const MachineFrameInfo *MFI = MF.getFrameInfo();
208 // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
209 // to the stack pointer, so only put the emergency spill slot next to the
210 // FP when there's no better way to access it (SP or base pointer).
211 return MFI->hasVarSizedObjects() && !hasBasePointer(MF);
214 bool AArch64RegisterInfo::requiresFrameIndexScavenging(
215 const MachineFunction &MF) const {
220 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
221 const MachineFrameInfo *MFI = MF.getFrameInfo();
222 // Only consider eliminating leaf frames.
223 if (MFI->hasCalls() || (MF.getTarget().Options.DisableFramePointerElim(MF) &&
224 MFI->adjustsStack()))
226 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
229 /// needsFrameBaseReg - Returns true if the instruction's frame index
230 /// reference would be better served by a base register other than FP
231 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
232 /// references it should create new base registers for.
233 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
234 int64_t Offset) const {
235 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
236 assert(i < MI->getNumOperands() &&
237 "Instr doesn't have FrameIndex operand!");
239 // It's the load/store FI references that cause issues, as it can be difficult
240 // to materialize the offset if it won't fit in the literal field. Estimate
241 // based on the size of the local frame and some conservative assumptions
242 // about the rest of the stack frame (note, this is pre-regalloc, so
243 // we don't know everything for certain yet) whether this offset is likely
244 // to be out of range of the immediate. Return true if so.
246 // We only generate virtual base registers for loads and stores, so
247 // return false for everything else.
248 if (!MI->mayLoad() && !MI->mayStore())
251 // Without a virtual base register, if the function has variable sized
252 // objects, all fixed-size local references will be via the frame pointer,
253 // Approximate the offset and see if it's legal for the instruction.
254 // Note that the incoming offset is based on the SP value at function entry,
255 // so it'll be negative.
256 MachineFunction &MF = *MI->getParent()->getParent();
257 const AArch64FrameLowering *TFI = getFrameLowering(MF);
258 MachineFrameInfo *MFI = MF.getFrameInfo();
260 // Estimate an offset from the frame pointer.
261 // Conservatively assume all GPR callee-saved registers get pushed.
262 // FP, LR, X19-X28, D8-D15. 64-bits each.
263 int64_t FPOffset = Offset - 16 * 20;
264 // Estimate an offset from the stack pointer.
265 // The incoming offset is relating to the SP at the start of the function,
266 // but when we access the local it'll be relative to the SP after local
267 // allocation, so adjust our SP-relative offset by that allocation size.
268 Offset += MFI->getLocalFrameSize();
269 // Assume that we'll have at least some spill slots allocated.
270 // FIXME: This is a total SWAG number. We should run some statistics
271 // and pick a real one.
272 Offset += 128; // 128 bytes of spill slots
274 // If there is a frame pointer, try using it.
275 // The FP is only available if there is no dynamic realignment. We
276 // don't know for sure yet whether we'll need that, so we guess based
277 // on whether there are any local variables that would trigger it.
278 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
281 // If we can reference via the stack pointer or base pointer, try that.
282 // FIXME: This (and the code that resolves the references) can be improved
283 // to only disallow SP relative references in the live range of
284 // the VLA(s). In practice, it's unclear how much difference that
285 // would make, but it may be worth doing.
286 if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
289 // The offset likely isn't legal; we want to allocate a virtual base register.
293 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
295 int64_t Offset) const {
296 assert(Offset <= INT_MAX && "Offset too big to fit in int.");
297 assert(MI && "Unable to get the legal offset for nil instruction.");
298 int SaveOffset = Offset;
299 return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
302 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
303 /// at the beginning of the basic block.
304 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
307 int64_t Offset) const {
308 MachineBasicBlock::iterator Ins = MBB->begin();
309 DebugLoc DL; // Defaults to "unknown"
310 if (Ins != MBB->end())
311 DL = Ins->getDebugLoc();
312 const MachineFunction &MF = *MBB->getParent();
313 const AArch64InstrInfo *TII =
314 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
315 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
316 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
317 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
318 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
320 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
321 .addFrameIndex(FrameIdx)
326 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
327 int64_t Offset) const {
328 int Off = Offset; // ARM doesn't need the general 64-bit offsets
331 while (!MI.getOperand(i).isFI()) {
333 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
335 const MachineFunction *MF = MI.getParent()->getParent();
336 const AArch64InstrInfo *TII =
337 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
338 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
339 assert(Done && "Unable to resolve frame index!");
343 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
344 int SPAdj, unsigned FIOperandNum,
345 RegScavenger *RS) const {
346 assert(SPAdj == 0 && "Unexpected");
348 MachineInstr &MI = *II;
349 MachineBasicBlock &MBB = *MI.getParent();
350 MachineFunction &MF = *MBB.getParent();
351 const AArch64InstrInfo *TII =
352 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
353 const AArch64FrameLowering *TFI = getFrameLowering(MF);
355 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
359 // Special handling of dbg_value, stackmap and patchpoint instructions.
360 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
361 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
362 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
364 Offset += MI.getOperand(FIOperandNum + 1).getImm();
365 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
366 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
370 // Modify MI as necessary to handle as much of 'Offset' as possible
371 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
372 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
375 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
376 "Emergency spill slot is out of reach");
378 // If we get here, the immediate doesn't fit into the instruction. We folded
379 // as much as possible above. Handle the rest, providing a register that is
381 unsigned ScratchReg =
382 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
383 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
384 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
389 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
390 MachineFunction &MF) const {
391 const AArch64FrameLowering *TFI = getFrameLowering(MF);
393 switch (RC->getID()) {
396 case AArch64::GPR32RegClassID:
397 case AArch64::GPR32spRegClassID:
398 case AArch64::GPR32allRegClassID:
399 case AArch64::GPR64spRegClassID:
400 case AArch64::GPR64allRegClassID:
401 case AArch64::GPR64RegClassID:
402 case AArch64::GPR32commonRegClassID:
403 case AArch64::GPR64commonRegClassID:
404 return 32 - 1 // XZR/SP
405 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
406 - MF.getSubtarget<AArch64Subtarget>()
407 .isX18Reserved() // X18 reserved as platform register
408 - hasBasePointer(MF); // X19
409 case AArch64::FPR8RegClassID:
410 case AArch64::FPR16RegClassID:
411 case AArch64::FPR32RegClassID:
412 case AArch64::FPR64RegClassID:
413 case AArch64::FPR128RegClassID:
416 case AArch64::DDRegClassID:
417 case AArch64::DDDRegClassID:
418 case AArch64::DDDDRegClassID:
419 case AArch64::QQRegClassID:
420 case AArch64::QQQRegClassID:
421 case AArch64::QQQQRegClassID:
424 case AArch64::FPR128_loRegClassID: