1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64MachineFunctionInfo.h"
18 #include "AArch64TargetMachine.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/ADT/BitVector.h"
26 #define GET_REGINFO_TARGET_DESC
27 #include "AArch64GenRegisterInfo.inc"
31 AArch64RegisterInfo::AArch64RegisterInfo(const AArch64InstrInfo &tii,
32 const AArch64Subtarget &sti)
33 : AArch64GenRegisterInfo(AArch64::X30), TII(tii) {
37 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
38 return CSR_PCS_SaveList;
42 AArch64RegisterInfo::getCallPreservedMask(CallingConv::ID) const {
43 return CSR_PCS_RegMask;
46 const uint32_t *AArch64RegisterInfo::getTLSDescCallPreservedMask() const {
47 return TLSDesc_RegMask;
50 const TargetRegisterClass *
51 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
52 if (RC == &AArch64::FlagClassRegClass)
53 return &AArch64::GPR64RegClass;
61 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
62 BitVector Reserved(getNumRegs());
63 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
65 Reserved.set(AArch64::XSP);
66 Reserved.set(AArch64::WSP);
68 Reserved.set(AArch64::XZR);
69 Reserved.set(AArch64::WZR);
72 Reserved.set(AArch64::X29);
73 Reserved.set(AArch64::W29);
80 AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI,
81 int SPAdj, RegScavenger *RS) const {
82 assert(SPAdj == 0 && "Cannot deal with nonzero SPAdj yet");
83 MachineInstr &MI = *MBBI;
84 MachineBasicBlock &MBB = *MI.getParent();
85 MachineFunction &MF = *MBB.getParent();
86 MachineFrameInfo *MFI = MF.getFrameInfo();
87 const AArch64FrameLowering *TFI =
88 static_cast<const AArch64FrameLowering *>(MF.getTarget().getFrameLowering());
91 while (!MI.getOperand(i).isFI()) {
93 assert(i < MI.getNumOperands() && "Instr doesn't have a FrameIndex Operand");
96 // In order to work out the base and offset for addressing, the FrameLowering
97 // code needs to know (sometimes) whether the instruction is storing/loading a
98 // callee-saved register, or whether it's a more generic
99 // operation. Fortunately the frame indices are used *only* for that purpose
100 // and are contiguous, so we can check here.
101 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
106 MinCSFI = CSI[0].getFrameIdx();
107 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
110 int FrameIndex = MI.getOperand(i).getIndex();
111 bool IsCalleeSaveOp = FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI;
115 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj,
118 Offset += MI.getOperand(i+1).getImm();
120 // DBG_VALUE instructions have no real restrictions so they can be handled
122 if (MI.isDebugValue()) {
123 MI.getOperand(i).ChangeToRegister(FrameReg, /*isDef=*/ false);
124 MI.getOperand(i+1).ChangeToImmediate(Offset);
128 int MinOffset, MaxOffset, OffsetScale;
129 if (MI.getOpcode() == AArch64::ADDxxi_lsl0_s) {
134 // Load/store of a stack object
135 TII.getAddressConstraints(MI, OffsetScale, MinOffset, MaxOffset);
138 // The frame lowering has told us a base and offset it thinks we should use to
139 // access this variable, but it's still up to us to make sure the values are
140 // legal for the instruction in question.
141 if (Offset % OffsetScale != 0 || Offset < MinOffset || Offset > MaxOffset) {
143 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
144 emitRegUpdate(MBB, MBBI, MBBI->getDebugLoc(), TII,
145 BaseReg, FrameReg, BaseReg, Offset);
150 // Negative offsets are expected if we address from FP, but for
151 // now this checks nothing has gone horribly wrong.
152 assert(Offset >= 0 && "Unexpected negative offset from SP");
154 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, true);
155 MI.getOperand(i+1).ChangeToImmediate(Offset / OffsetScale);
159 AArch64RegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
160 MachineBasicBlock &MBB,
161 MachineBasicBlock::iterator MI) const {
162 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
163 DebugLoc dl = MI->getDebugLoc();
164 int Opcode = MI->getOpcode();
165 bool IsDestroy = Opcode == TII.getCallFrameDestroyOpcode();
166 uint64_t CalleePopAmount = IsDestroy ? MI->getOperand(1).getImm() : 0;
168 if (!TFI->hasReservedCallFrame(MF)) {
169 unsigned Align = TFI->getStackAlignment();
171 uint64_t Amount = MI->getOperand(0).getImm();
172 Amount = (Amount + Align - 1)/Align * Align;
173 if (!IsDestroy) Amount = -Amount;
175 // N.b. if CalleePopAmount is valid but zero (i.e. callee would pop, but it
176 // doesn't have to pop anything), then the first operand will be zero too so
177 // this adjustment is a no-op.
178 if (CalleePopAmount == 0) {
179 // FIXME: in-function stack adjustment for calls is limited to 12-bits
180 // because there's no guaranteed temporary register available. Mostly call
181 // frames will be allocated at the start of a function so this is OK, but
182 // it is a limitation that needs dealing with.
183 assert(abs(Amount) < 0xfff && "call frame too large");
184 emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, Amount);
186 } else if (CalleePopAmount != 0) {
187 // If the calling convention demands that the callee pops arguments from the
188 // stack, we want to add it back if we have a reserved call frame.
189 assert(CalleePopAmount < 0xfff && "call frame too large");
190 emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, -CalleePopAmount);
197 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
198 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
207 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
208 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
209 const AArch64FrameLowering *AFI = static_cast<const AArch64FrameLowering*>(TFI);
210 return AFI->useFPForAddressing(MF);