1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64Subtarget.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/Target/TargetFrameLowering.h"
30 #include "llvm/Target/TargetOptions.h"
34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
37 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
38 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
41 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
42 assert(MF && "Invalid MachineFunction pointer.");
43 if (MF->getFunction()->getCallingConv() == CallingConv::GHC)
44 // GHC set of callee saved regs is empty as all those regs are
45 // used for passing STG regs around
46 return CSR_AArch64_NoRegs_SaveList;
47 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
48 return CSR_AArch64_AllRegs_SaveList;
50 return CSR_AArch64_AAPCS_SaveList;
54 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
55 CallingConv::ID CC) const {
56 if (CC == CallingConv::GHC)
57 // This is academic becase all GHC calls are (supposed to be) tail calls
58 return CSR_AArch64_NoRegs_RegMask;
59 if (CC == CallingConv::AnyReg)
60 return CSR_AArch64_AllRegs_RegMask;
62 return CSR_AArch64_AAPCS_RegMask;
65 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
67 return CSR_AArch64_TLS_Darwin_RegMask;
69 assert(TT.isOSBinFormatELF() && "only expect Darwin or ELF TLS");
70 return CSR_AArch64_TLS_ELF_RegMask;
74 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
75 CallingConv::ID CC) const {
76 // This should return a register mask that is the same as that returned by
77 // getCallPreservedMask but that additionally preserves the register used for
78 // the first i64 argument (which must also be the register used to return a
79 // single i64 return value)
81 // In case that the calling convention does not use the same register for
82 // both, the function should return NULL (does not currently apply)
83 assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
84 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
88 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
89 const AArch64FrameLowering *TFI = getFrameLowering(MF);
91 // FIXME: avoid re-calculating this every time.
92 BitVector Reserved(getNumRegs());
93 Reserved.set(AArch64::SP);
94 Reserved.set(AArch64::XZR);
95 Reserved.set(AArch64::WSP);
96 Reserved.set(AArch64::WZR);
98 if (TFI->hasFP(MF) || TT.isOSDarwin()) {
99 Reserved.set(AArch64::FP);
100 Reserved.set(AArch64::W29);
103 if (TT.isOSDarwin() || MF.getSubtarget<AArch64Subtarget>().isX18Reserved()) {
104 Reserved.set(AArch64::X18); // Platform register
105 Reserved.set(AArch64::W18);
108 if (hasBasePointer(MF)) {
109 Reserved.set(AArch64::X19);
110 Reserved.set(AArch64::W19);
116 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
117 unsigned Reg) const {
118 const AArch64FrameLowering *TFI = getFrameLowering(MF);
130 return TT.isOSDarwin() ||
131 MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
134 return TFI->hasFP(MF) || TT.isOSDarwin();
137 return hasBasePointer(MF);
143 const TargetRegisterClass *
144 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
145 unsigned Kind) const {
146 return &AArch64::GPR64RegClass;
149 const TargetRegisterClass *
150 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
151 if (RC == &AArch64::CCRRegClass)
152 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
156 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
158 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
159 const MachineFrameInfo *MFI = MF.getFrameInfo();
161 // In the presence of variable sized objects, if the fixed stack size is
162 // large enough that referencing from the FP won't result in things being
163 // in range relatively often, we can use a base pointer to allow access
164 // from the other direction like the SP normally works.
165 // Furthermore, if both variable sized objects are present, and the
166 // stack needs to be dynamically re-aligned, the base pointer is the only
167 // reliable way to reference the locals.
168 if (MFI->hasVarSizedObjects()) {
169 if (needsStackRealignment(MF))
171 // Conservatively estimate whether the negative offset from the frame
172 // pointer will be sufficient to reach. If a function has a smallish
173 // frame, it's less likely to have lots of spills and callee saved
174 // space, so it's all more likely to be within range of the frame pointer.
175 // If it's wrong, we'll materialize the constant and still get to the
176 // object; it's just suboptimal. Negative offsets use the unscaled
177 // load/store instructions, which have a 9-bit signed immediate.
178 if (MFI->getLocalFrameSize() < 256)
187 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
188 const AArch64FrameLowering *TFI = getFrameLowering(MF);
189 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
192 bool AArch64RegisterInfo::requiresRegisterScavenging(
193 const MachineFunction &MF) const {
197 bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
198 const MachineFunction &MF) const {
203 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
204 const MachineFrameInfo *MFI = MF.getFrameInfo();
205 // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
206 // to the stack pointer, so only put the emergency spill slot next to the
207 // FP when there's no better way to access it (SP or base pointer).
208 return MFI->hasVarSizedObjects() && !hasBasePointer(MF);
211 bool AArch64RegisterInfo::requiresFrameIndexScavenging(
212 const MachineFunction &MF) const {
217 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
218 const MachineFrameInfo *MFI = MF.getFrameInfo();
219 // Only consider eliminating leaf frames.
220 if (MFI->hasCalls() || (MF.getTarget().Options.DisableFramePointerElim(MF) &&
221 MFI->adjustsStack()))
223 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
226 /// needsFrameBaseReg - Returns true if the instruction's frame index
227 /// reference would be better served by a base register other than FP
228 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
229 /// references it should create new base registers for.
230 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
231 int64_t Offset) const {
232 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
233 assert(i < MI->getNumOperands() &&
234 "Instr doesn't have FrameIndex operand!");
236 // It's the load/store FI references that cause issues, as it can be difficult
237 // to materialize the offset if it won't fit in the literal field. Estimate
238 // based on the size of the local frame and some conservative assumptions
239 // about the rest of the stack frame (note, this is pre-regalloc, so
240 // we don't know everything for certain yet) whether this offset is likely
241 // to be out of range of the immediate. Return true if so.
243 // We only generate virtual base registers for loads and stores, so
244 // return false for everything else.
245 if (!MI->mayLoad() && !MI->mayStore())
248 // Without a virtual base register, if the function has variable sized
249 // objects, all fixed-size local references will be via the frame pointer,
250 // Approximate the offset and see if it's legal for the instruction.
251 // Note that the incoming offset is based on the SP value at function entry,
252 // so it'll be negative.
253 MachineFunction &MF = *MI->getParent()->getParent();
254 const AArch64FrameLowering *TFI = getFrameLowering(MF);
255 MachineFrameInfo *MFI = MF.getFrameInfo();
257 // Estimate an offset from the frame pointer.
258 // Conservatively assume all GPR callee-saved registers get pushed.
259 // FP, LR, X19-X28, D8-D15. 64-bits each.
260 int64_t FPOffset = Offset - 16 * 20;
261 // Estimate an offset from the stack pointer.
262 // The incoming offset is relating to the SP at the start of the function,
263 // but when we access the local it'll be relative to the SP after local
264 // allocation, so adjust our SP-relative offset by that allocation size.
265 Offset += MFI->getLocalFrameSize();
266 // Assume that we'll have at least some spill slots allocated.
267 // FIXME: This is a total SWAG number. We should run some statistics
268 // and pick a real one.
269 Offset += 128; // 128 bytes of spill slots
271 // If there is a frame pointer, try using it.
272 // The FP is only available if there is no dynamic realignment. We
273 // don't know for sure yet whether we'll need that, so we guess based
274 // on whether there are any local variables that would trigger it.
275 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
278 // If we can reference via the stack pointer or base pointer, try that.
279 // FIXME: This (and the code that resolves the references) can be improved
280 // to only disallow SP relative references in the live range of
281 // the VLA(s). In practice, it's unclear how much difference that
282 // would make, but it may be worth doing.
283 if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
286 // The offset likely isn't legal; we want to allocate a virtual base register.
290 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
292 int64_t Offset) const {
293 assert(Offset <= INT_MAX && "Offset too big to fit in int.");
294 assert(MI && "Unable to get the legal offset for nil instruction.");
295 int SaveOffset = Offset;
296 return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
299 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
300 /// at the beginning of the basic block.
301 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
304 int64_t Offset) const {
305 MachineBasicBlock::iterator Ins = MBB->begin();
306 DebugLoc DL; // Defaults to "unknown"
307 if (Ins != MBB->end())
308 DL = Ins->getDebugLoc();
309 const MachineFunction &MF = *MBB->getParent();
310 const AArch64InstrInfo *TII =
311 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
312 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
313 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
314 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
315 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
317 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
318 .addFrameIndex(FrameIdx)
323 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
324 int64_t Offset) const {
325 int Off = Offset; // ARM doesn't need the general 64-bit offsets
328 while (!MI.getOperand(i).isFI()) {
330 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
332 const MachineFunction *MF = MI.getParent()->getParent();
333 const AArch64InstrInfo *TII =
334 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
335 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
336 assert(Done && "Unable to resolve frame index!");
340 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
341 int SPAdj, unsigned FIOperandNum,
342 RegScavenger *RS) const {
343 assert(SPAdj == 0 && "Unexpected");
345 MachineInstr &MI = *II;
346 MachineBasicBlock &MBB = *MI.getParent();
347 MachineFunction &MF = *MBB.getParent();
348 const AArch64InstrInfo *TII =
349 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
350 const AArch64FrameLowering *TFI = getFrameLowering(MF);
352 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
356 // Special handling of dbg_value, stackmap and patchpoint instructions.
357 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
358 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
359 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
361 Offset += MI.getOperand(FIOperandNum + 1).getImm();
362 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
363 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
367 // Modify MI as necessary to handle as much of 'Offset' as possible
368 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
369 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
372 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
373 "Emergency spill slot is out of reach");
375 // If we get here, the immediate doesn't fit into the instruction. We folded
376 // as much as possible above. Handle the rest, providing a register that is
378 unsigned ScratchReg =
379 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
380 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
381 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
386 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
387 MachineFunction &MF) const {
388 const AArch64FrameLowering *TFI = getFrameLowering(MF);
390 switch (RC->getID()) {
393 case AArch64::GPR32RegClassID:
394 case AArch64::GPR32spRegClassID:
395 case AArch64::GPR32allRegClassID:
396 case AArch64::GPR64spRegClassID:
397 case AArch64::GPR64allRegClassID:
398 case AArch64::GPR64RegClassID:
399 case AArch64::GPR32commonRegClassID:
400 case AArch64::GPR64commonRegClassID:
401 return 32 - 1 // XZR/SP
402 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
403 - (TT.isOSDarwin() ||
404 MF.getSubtarget<AArch64Subtarget>()
405 .isX18Reserved()) // X18 reserved as platform register
406 - hasBasePointer(MF); // X19
407 case AArch64::FPR8RegClassID:
408 case AArch64::FPR16RegClassID:
409 case AArch64::FPR32RegClassID:
410 case AArch64::FPR64RegClassID:
411 case AArch64::FPR128RegClassID:
414 case AArch64::DDRegClassID:
415 case AArch64::DDDRegClassID:
416 case AArch64::DDDDRegClassID:
417 case AArch64::QQRegClassID:
418 case AArch64::QQQRegClassID:
419 case AArch64::QQQQRegClassID:
422 case AArch64::FPR128_loRegClassID: