1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
17 #define GET_REGINFO_HEADER
18 #include "AArch64GenRegisterInfo.inc"
22 class MachineFunction;
24 class TargetRegisterClass;
27 struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
32 AArch64RegisterInfo(const Triple &TT);
34 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
36 /// Code Generation virtual methods...
37 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
38 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
39 CallingConv::ID) const override;
41 unsigned getCSRFirstUseCost() const override {
42 // The cost will be compared against BlockFrequency where entry has the
43 // value of 1 << 14. A value of 5 will choose to spill or split really
44 // cold path instead of using a callee-saved register.
48 // Calls involved in thread-local variable lookup save more registers than
49 // normal calls, so they need a different mask to represent this.
50 const uint32_t *getTLSCallPreservedMask() const;
52 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
53 /// case that 'returned' is on an i64 first argument if the calling convention
54 /// is one that can (partially) model this attribute with a preserved mask
55 /// (i.e. it is a calling convention that uses the same register for the first
56 /// i64 argument and an i64 return value)
58 /// Should return NULL in the case that the calling convention does not have
60 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
61 CallingConv::ID) const;
63 BitVector getReservedRegs(const MachineFunction &MF) const override;
64 const TargetRegisterClass *
65 getPointerRegClass(const MachineFunction &MF,
66 unsigned Kind = 0) const override;
67 const TargetRegisterClass *
68 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
70 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
71 bool useFPForScavengingIndex(const MachineFunction &MF) const override;
72 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
74 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
75 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
76 int64_t Offset) const override;
77 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
79 int64_t Offset) const override;
80 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
81 int64_t Offset) const override;
82 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
83 unsigned FIOperandNum,
84 RegScavenger *RS = nullptr) const override;
85 bool cannotEliminateFrame(const MachineFunction &MF) const;
87 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
88 bool hasBasePointer(const MachineFunction &MF) const;
89 unsigned getBaseRegister() const;
91 // Debug information queries.
92 unsigned getFrameRegister(const MachineFunction &MF) const override;
94 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
95 MachineFunction &MF) const override;
96 // Base pointer (stack realignment) support.
97 bool canRealignStack(const MachineFunction &MF) const;
98 bool needsStackRealignment(const MachineFunction &MF) const override;
101 } // end namespace llvm