1 //===- AArch64RegisterInfo.td - ARM Register defs ----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains declarations that describe the AArch64 register file
12 //===----------------------------------------------------------------------===//
14 let Namespace = "AArch64" in {
15 def sub_128 : SubRegIndex<128>;
16 def sub_64 : SubRegIndex<64>;
17 def sub_32 : SubRegIndex<32>;
18 def sub_16 : SubRegIndex<16>;
19 def sub_8 : SubRegIndex<8>;
21 // Note: Code depends on these having consecutive numbers.
22 def qqsub : SubRegIndex<256, 256>;
24 def qsub_0 : SubRegIndex<128>;
25 def qsub_1 : SubRegIndex<128, 128>;
26 def qsub_2 : ComposedSubRegIndex<qqsub, qsub_0>;
27 def qsub_3 : ComposedSubRegIndex<qqsub, qsub_1>;
29 def dsub_0 : SubRegIndex<64>;
30 def dsub_1 : SubRegIndex<64, 64>;
31 def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>;
32 def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>;
35 // Registers are identified with 5-bit ID numbers.
36 class AArch64Reg<bits<16> enc, string n> : Register<n> {
38 let Namespace = "AArch64";
41 class AArch64RegWithSubs<bits<16> enc, string n, list<Register> subregs = [],
42 list<SubRegIndex> inds = []>
43 : AArch64Reg<enc, n> {
44 let SubRegs = subregs;
45 let SubRegIndices = inds;
48 //===----------------------------------------------------------------------===//
49 // Integer registers: w0-w30, wzr, wsp, x0-x30, xzr, sp
50 //===----------------------------------------------------------------------===//
52 foreach Index = 0-30 in {
53 def W#Index : AArch64Reg< Index, "w"#Index>, DwarfRegNum<[Index]>;
56 def WSP : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>;
57 def WZR : AArch64Reg<31, "wzr">;
59 // Could be combined with previous loop, but this way leaves w and x registers
60 // consecutive as LLVM register numbers, which makes for easier debugging.
61 foreach Index = 0-30 in {
62 def X#Index : AArch64RegWithSubs<Index, "x"#Index,
63 [!cast<Register>("W"#Index)], [sub_32]>,
67 def XSP : AArch64RegWithSubs<31, "sp", [WSP], [sub_32]>, DwarfRegNum<[31]>;
68 def XZR : AArch64RegWithSubs<31, "xzr", [WZR], [sub_32]>;
70 // Most instructions treat register 31 as zero for reads and a black-hole for
73 // Note that the order of registers is important for the Disassembler here:
74 // tablegen uses it to form MCRegisterClass::getRegister, which we assume can
75 // take an encoding value.
76 def GPR32 : RegisterClass<"AArch64", [i32], 32,
77 (add (sequence "W%u", 0, 30), WZR)> {
80 def GPR64 : RegisterClass<"AArch64", [i64], 64,
81 (add (sequence "X%u", 0, 30), XZR)> {
84 def GPR32nowzr : RegisterClass<"AArch64", [i32], 32,
85 (sequence "W%u", 0, 30)> {
88 def GPR64noxzr : RegisterClass<"AArch64", [i64], 64,
89 (sequence "X%u", 0, 30)> {
92 // For tail calls, we can't use callee-saved registers or the structure-return
93 // register, as they are supposed to be live across function calls and may be
94 // clobbered by the epilogue.
95 def tcGPR64 : RegisterClass<"AArch64", [i64], 64,
96 (add (sequence "X%u", 0, 7),
97 (sequence "X%u", 9, 18))> {
101 // Certain addressing-useful instructions accept sp directly. Again the order of
102 // registers is important to the Disassembler.
103 def GPR32wsp : RegisterClass<"AArch64", [i32], 32,
104 (add (sequence "W%u", 0, 30), WSP)> {
107 def GPR64xsp : RegisterClass<"AArch64", [i64], 64,
108 (add (sequence "X%u", 0, 30), XSP)> {
111 // Some aliases *only* apply to SP (e.g. MOV uses different encoding for SP and
112 // non-SP variants). We can't use a bare register in those patterns because
113 // TableGen doesn't like it, so we need a class containing just stack registers
114 def Rxsp : RegisterClass<"AArch64", [i64], 64,
118 def Rwsp : RegisterClass<"AArch64", [i32], 32,
122 //===----------------------------------------------------------------------===//
123 // Scalar registers in the vector unit:
124 // b0-b31, h0-h31, s0-s31, d0-d31, q0-q31
125 //===----------------------------------------------------------------------===//
127 foreach Index = 0-31 in {
128 def B # Index : AArch64Reg< Index, "b" # Index>,
129 DwarfRegNum<[!add(Index, 64)]>;
131 def H # Index : AArch64RegWithSubs<Index, "h" # Index,
132 [!cast<Register>("B" # Index)], [sub_8]>,
133 DwarfRegNum<[!add(Index, 64)]>;
135 def S # Index : AArch64RegWithSubs<Index, "s" # Index,
136 [!cast<Register>("H" # Index)], [sub_16]>,
137 DwarfRegNum<[!add(Index, 64)]>;
139 def D # Index : AArch64RegWithSubs<Index, "d" # Index,
140 [!cast<Register>("S" # Index)], [sub_32]>,
141 DwarfRegNum<[!add(Index, 64)]>;
143 def Q # Index : AArch64RegWithSubs<Index, "q" # Index,
144 [!cast<Register>("D" # Index)], [sub_64]>,
145 DwarfRegNum<[!add(Index, 64)]>;
149 def FPR8 : RegisterClass<"AArch64", [v1i8], 8,
150 (sequence "B%u", 0, 31)> {
153 def FPR16 : RegisterClass<"AArch64", [f16, v1i16], 16,
154 (sequence "H%u", 0, 31)> {
157 def FPR32 : RegisterClass<"AArch64", [f32, v1i32], 32,
158 (sequence "S%u", 0, 31)> {
161 def FPR64 : RegisterClass<"AArch64",
162 [f64, v2f32, v2i32, v4i16, v8i8, v1i64, v1f64],
163 64, (sequence "D%u", 0, 31)>;
165 def FPR128 : RegisterClass<"AArch64",
166 [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
167 128, (sequence "Q%u", 0, 31)>;
169 def FPR64Lo : RegisterClass<"AArch64",
170 [f64, v2f32, v2i32, v4i16, v8i8, v1i64, v1f64],
171 64, (sequence "D%u", 0, 15)>;
173 def FPR128Lo : RegisterClass<"AArch64",
174 [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
175 128, (sequence "Q%u", 0, 15)>;
177 //===----------------------------------------------------------------------===//
179 //===----------------------------------------------------------------------===//
181 def VPR64AsmOperand : AsmOperandClass {
183 let PredicateMethod = "isReg";
184 let RenderMethod = "addRegOperands";
187 def VPR64 : RegisterOperand<FPR64, "printVPRRegister">;
189 def VPR128 : RegisterOperand<FPR128, "printVPRRegister">;
191 def VPR64Lo : RegisterOperand<FPR64Lo, "printVPRRegister">;
193 def VPR128Lo : RegisterOperand<FPR128Lo, "printVPRRegister">;
196 def NZCV : Register<"nzcv"> {
197 let Namespace = "AArch64";
200 def FlagClass : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
202 let isAllocatable = 0;
205 //===----------------------------------------------------------------------===//
206 // Consecutive vector registers
207 //===----------------------------------------------------------------------===//
208 // 2 Consecutive 64-bit registers: D0_D1, D1_D2, ..., D31_D0
209 def Tuples2D : RegisterTuples<[dsub_0, dsub_1],
210 [(rotl FPR64, 0), (rotl FPR64, 1)]>;
212 // 3 Consecutive 64-bit registers: D0_D1_D2, ..., D31_D0_D1
213 def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2],
214 [(rotl FPR64, 0), (rotl FPR64, 1),
217 // 4 Consecutive 64-bit registers: D0_D1_D2_D3, ..., D31_D0_D1_D2
218 def Tuples4D : RegisterTuples<[dsub_0, dsub_1, dsub_2, dsub_3],
219 [(rotl FPR64, 0), (rotl FPR64, 1),
220 (rotl FPR64, 2), (rotl FPR64, 3)]>;
222 // 2 Consecutive 128-bit registers: Q0_Q1, Q1_Q2, ..., Q30_Q31
223 def Tuples2Q : RegisterTuples<[qsub_0, qsub_1],
224 [(rotl FPR128, 0), (rotl FPR128, 1)]>;
226 // 3 Consecutive 128-bit registers: Q0_Q1_Q2, ..., Q31_Q0_Q1
227 def Tuples3Q : RegisterTuples<[qsub_0, qsub_1, qsub_2],
228 [(rotl FPR128, 0), (rotl FPR128, 1),
231 // 4 Consecutive 128-bit registers: Q0_Q1_Q2_Q3, ..., Q31_Q0_Q1_Q2
232 def Tuples4Q : RegisterTuples<[qsub_0, qsub_1, qsub_2, qsub_3],
233 [(rotl FPR128, 0), (rotl FPR128, 1),
234 (rotl FPR128, 2), (rotl FPR128, 3)]>;
236 // The followings are super register classes to model 2/3/4 consecutive
237 // 64-bit/128-bit registers.
239 def DPair : RegisterClass<"AArch64", [v2i64], 64, (add Tuples2D)>;
241 def DTriple : RegisterClass<"AArch64", [untyped], 64, (add Tuples3D)> {
242 let Size = 192; // 3 x 64 bits, we have no predefined type of that size.
245 def DQuad : RegisterClass<"AArch64", [v4i64], 64, (add Tuples4D)>;
247 def QPair : RegisterClass<"AArch64", [v4i64], 128, (add Tuples2Q)>;
249 def QTriple : RegisterClass<"AArch64", [untyped], 128, (add Tuples3Q)> {
250 let Size = 384; // 3 x 128 bits, we have no predefined type of that size.
253 def QQuad : RegisterClass<"AArch64", [v8i64], 128, (add Tuples4Q)>;
256 // The followings are vector list operands
257 multiclass VectorList_operands<string PREFIX, string LAYOUT, int Count,
258 RegisterClass RegList> {
259 def _asmoperand : AsmOperandClass {
260 let Name = PREFIX # LAYOUT # Count;
261 let RenderMethod = "addVectorListOperands";
262 let PredicateMethod =
263 "isVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">";
264 let ParserMethod = "ParseVectorList";
267 def _operand : RegisterOperand<RegList,
268 "printVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">"> {
269 let ParserMatchClass =
270 !cast<AsmOperandClass>(PREFIX # LAYOUT # "_asmoperand");
274 multiclass VectorList_BHSD<string PREFIX, int Count, RegisterClass DRegList,
275 RegisterClass QRegList> {
276 defm 8B : VectorList_operands<PREFIX, "8B", Count, DRegList>;
277 defm 4H : VectorList_operands<PREFIX, "4H", Count, DRegList>;
278 defm 2S : VectorList_operands<PREFIX, "2S", Count, DRegList>;
279 defm 1D : VectorList_operands<PREFIX, "1D", Count, DRegList>;
280 defm 16B : VectorList_operands<PREFIX, "16B", Count, QRegList>;
281 defm 8H : VectorList_operands<PREFIX, "8H", Count, QRegList>;
282 defm 4S : VectorList_operands<PREFIX, "4S", Count, QRegList>;
283 defm 2D : VectorList_operands<PREFIX, "2D", Count, QRegList>;
286 // Vector list operand with 1/2/3/4 registers: VOne8B_operand,..., VQuad2D_operand
287 defm VOne : VectorList_BHSD<"VOne", 1, FPR64, FPR128>;
288 defm VPair : VectorList_BHSD<"VPair", 2, DPair, QPair>;
289 defm VTriple : VectorList_BHSD<"VTriple", 3, DTriple, QTriple>;
290 defm VQuad : VectorList_BHSD<"VQuad", 4, DQuad, QQuad>;