1 //=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
11 // below is to define a generic SchedWriteRes for every combination of
12 // latency and microOps. The naming conventions is to use a prefix, one field
13 // for latency, and one or more microOp count/type designators.
16 // MicroOp Count/Types: #(B|I|M|L|S|X|W|V)
18 // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
19 // 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes.
21 //===----------------------------------------------------------------------===//
23 //===----------------------------------------------------------------------===//
24 // Define Generic 1 micro-op types
26 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
27 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
28 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
29 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
30 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
31 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
32 let ResourceCycles = [18]; }
33 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
34 let ResourceCycles = [19]; }
35 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
36 def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
37 def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
38 def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }
39 def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
40 let ResourceCycles = [32]; }
41 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
42 let ResourceCycles = [35]; }
43 def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
44 def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
45 def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
46 def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }
47 def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; }
48 def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
49 def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
50 def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }
51 def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
54 //===----------------------------------------------------------------------===//
55 // Define Generic 2 micro-op types
57 def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
60 let ResourceCycles = [32, 32];
62 def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
67 def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV,
72 def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL,
77 def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
81 def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
85 def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> {
89 def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
93 def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
97 def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI,
102 def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
106 def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
110 def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,
115 def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
119 def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB,
124 def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI,
129 def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB,
134 def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> {
138 def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
142 def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
145 let ResourceCycles = [18, 18];
147 def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
152 def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI,
157 def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS,
162 def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
166 def A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI,
171 def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
177 //===----------------------------------------------------------------------===//
178 // Define Generic 3 micro-op types
180 def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
184 def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI,
185 A57UnitS, A57UnitS]> {
189 def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI,
195 def A57Write_3cyc_1M_2S : SchedWriteRes<[A57UnitM,
196 A57UnitS, A57UnitS]> {
200 def A57Write_3cyc_3S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS]> {
204 def A57Write_3cyc_2S_1V : SchedWriteRes<[A57UnitS, A57UnitS,
209 def A57Write_5cyc_1I_2L : SchedWriteRes<[A57UnitI,
210 A57UnitL, A57UnitL]> {
214 def A57Write_6cyc_1I_2L : SchedWriteRes<[A57UnitI,
215 A57UnitL, A57UnitL]> {
219 def A57Write_6cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
223 def A57Write_7cyc_3L : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL]> {
227 def A57Write_8cyc_1I_1L_1V : SchedWriteRes<[A57UnitI,
233 def A57Write_8cyc_1L_2V : SchedWriteRes<[A57UnitL,
234 A57UnitV, A57UnitV]> {
238 def A57Write_8cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
242 def A57Write_9cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
248 //===----------------------------------------------------------------------===//
249 // Define Generic 4 micro-op types
251 def A57Write_2cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI,
252 A57UnitS, A57UnitS]> {
256 def A57Write_3cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI,
257 A57UnitS, A57UnitS]> {
261 def A57Write_3cyc_1I_3S : SchedWriteRes<[A57UnitI,
262 A57UnitS, A57UnitS, A57UnitS]> {
266 def A57Write_3cyc_1I_2S_1V : SchedWriteRes<[A57UnitI,
272 def A57Write_4cyc_4S : SchedWriteRes<[A57UnitS, A57UnitS,
273 A57UnitS, A57UnitS]> {
277 def A57Write_7cyc_1I_3L : SchedWriteRes<[A57UnitI,
278 A57UnitL, A57UnitL, A57UnitL]> {
282 def A57Write_5cyc_2I_2L : SchedWriteRes<[A57UnitI, A57UnitI,
283 A57UnitL, A57UnitL]> {
287 def A57Write_8cyc_1I_1L_2V : SchedWriteRes<[A57UnitI,
289 A57UnitV, A57UnitV]> {
293 def A57Write_8cyc_4L : SchedWriteRes<[A57UnitL, A57UnitL,
294 A57UnitL, A57UnitL]> {
298 def A57Write_9cyc_2L_2V : SchedWriteRes<[A57UnitL, A57UnitL,
299 A57UnitV, A57UnitV]> {
303 def A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL,
304 A57UnitV, A57UnitV, A57UnitV]> {
308 def A57Write_12cyc_4V : SchedWriteRes<[A57UnitV, A57UnitV,
309 A57UnitV, A57UnitV]> {
315 //===----------------------------------------------------------------------===//
316 // Define Generic 5 micro-op types
318 def A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
319 A57UnitV, A57UnitV]> {
323 def A57Write_8cyc_1I_4L : SchedWriteRes<[A57UnitI,
325 A57UnitL, A57UnitL]> {
329 def A57Write_4cyc_1I_4S : SchedWriteRes<[A57UnitI,
331 A57UnitS, A57UnitS]> {
335 def A57Write_9cyc_1I_2L_2V : SchedWriteRes<[A57UnitI,
337 A57UnitV, A57UnitV]> {
341 def A57Write_9cyc_1I_1L_3V : SchedWriteRes<[A57UnitI,
343 A57UnitV, A57UnitV, A57UnitV]> {
347 def A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL,
348 A57UnitV, A57UnitV, A57UnitV]> {
352 def A57Write_9cyc_5V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
353 A57UnitV, A57UnitV]> {
359 //===----------------------------------------------------------------------===//
360 // Define Generic 6 micro-op types
362 def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI,
363 A57UnitS, A57UnitS, A57UnitS,
364 A57UnitV, A57UnitV]> {
368 def A57Write_4cyc_2I_4S : SchedWriteRes<[A57UnitI, A57UnitI,
370 A57UnitS, A57UnitS]> {
374 def A57Write_4cyc_4S_2V : SchedWriteRes<[A57UnitS, A57UnitS,
376 A57UnitV, A57UnitV]> {
380 def A57Write_6cyc_6S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
381 A57UnitS, A57UnitS, A57UnitS]> {
385 def A57Write_9cyc_1I_2L_3V : SchedWriteRes<[A57UnitI,
387 A57UnitV, A57UnitV, A57UnitV]> {
391 def A57Write_9cyc_1I_1L_4V : SchedWriteRes<[A57UnitI,
394 A57UnitV, A57UnitV]> {
398 def A57Write_9cyc_2L_4V : SchedWriteRes<[A57UnitL, A57UnitL,
400 A57UnitV, A57UnitV]> {
406 //===----------------------------------------------------------------------===//
407 // Define Generic 7 micro-op types
409 def A57Write_10cyc_3L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL,
411 A57UnitV, A57UnitV]> {
415 def A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI,
418 A57UnitV, A57UnitV]> {
422 def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI,
423 A57UnitS, A57UnitS, A57UnitS,
424 A57UnitS, A57UnitS, A57UnitS]> {
428 def A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI,
431 A57UnitV, A57UnitV]> {
435 def A57Write_12cyc_7V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
437 A57UnitV, A57UnitV]> {
443 //===----------------------------------------------------------------------===//
444 // Define Generic 8 micro-op types
446 def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI,
447 A57UnitL, A57UnitL, A57UnitL,
449 A57UnitV, A57UnitV]> {
453 def A57Write_11cyc_4L_4V : SchedWriteRes<[A57UnitL, A57UnitL,
456 A57UnitV, A57UnitV]> {
460 def A57Write_8cyc_8S : SchedWriteRes<[A57UnitS, A57UnitS,
463 A57UnitS, A57UnitS]> {
469 //===----------------------------------------------------------------------===//
470 // Define Generic 9 micro-op types
472 def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI,
476 A57UnitS, A57UnitS]> {
480 def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI,
484 A57UnitV, A57UnitV]> {
488 def A57Write_15cyc_9V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
489 A57UnitV, A57UnitV, A57UnitV,
490 A57UnitV, A57UnitV, A57UnitV]> {
496 //===----------------------------------------------------------------------===//
497 // Define Generic 10 micro-op types
499 def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
500 A57UnitS, A57UnitS, A57UnitS,
502 A57UnitV, A57UnitV]> {
504 let NumMicroOps = 10;
508 //===----------------------------------------------------------------------===//
509 // Define Generic 11 micro-op types
511 def A57Write_6cyc_1I_6S_4V : SchedWriteRes<[A57UnitI,
512 A57UnitS, A57UnitS, A57UnitS,
513 A57UnitS, A57UnitS, A57UnitS,
515 A57UnitV, A57UnitV]> {
517 let NumMicroOps = 11;
521 //===----------------------------------------------------------------------===//
522 // Define Generic 12 micro-op types
524 def A57Write_8cyc_8S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS,
525 A57UnitS, A57UnitS, A57UnitS, A57UnitS,
527 A57UnitV, A57UnitV]> {
529 let NumMicroOps = 12;
532 //===----------------------------------------------------------------------===//
533 // Define Generic 13 micro-op types
535 def A57Write_8cyc_1I_8S_4V : SchedWriteRes<[A57UnitI,
536 A57UnitS, A57UnitS, A57UnitS,
537 A57UnitS, A57UnitS, A57UnitS,
540 A57UnitV, A57UnitV]> {
542 let NumMicroOps = 13;