1 //=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
11 // below is to define a generic SchedWriteRes for every combination of
12 // latency and microOps. The naming conventions is to use a prefix, one field
13 // for latency, and one or more microOp count/type designators.
16 // MicroOp Count/Types: #(B|I|M|L|S|X|W|V)
18 // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
19 // 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes.
21 //===----------------------------------------------------------------------===//
23 //===----------------------------------------------------------------------===//
24 // Define Generic 1 micro-op types
26 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
27 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
28 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
29 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
30 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
31 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18; }
32 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19; }
33 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
34 def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
35 def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
36 def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }
37 def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32; }
38 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35; }
39 def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
40 def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
41 def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
42 def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }
43 def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; }
44 def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
45 def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
46 def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }
47 def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
50 //===----------------------------------------------------------------------===//
51 // Define Generic 2 micro-op types
53 def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
57 def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
62 def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV,
67 def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL,
72 def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
76 def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
80 def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> {
84 def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
88 def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
92 def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI,
97 def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
101 def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
105 def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,
110 def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
114 def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB,
119 def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI,
124 def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB,
129 def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> {
133 def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
137 def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
141 def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
146 def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI,
151 def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS,
156 def A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI,
161 def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
167 //===----------------------------------------------------------------------===//
168 // Define Generic 3 micro-op types
170 def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
174 def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI,
175 A57UnitS, A57UnitS]> {
179 def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI,
185 def A57Write_3cyc_1M_2S : SchedWriteRes<[A57UnitM,
186 A57UnitS, A57UnitS]> {
190 def A57Write_3cyc_3S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS]> {
194 def A57Write_3cyc_2S_1V : SchedWriteRes<[A57UnitS, A57UnitS,
199 def A57Write_5cyc_1I_2L : SchedWriteRes<[A57UnitI,
200 A57UnitL, A57UnitL]> {
204 def A57Write_6cyc_1I_2L : SchedWriteRes<[A57UnitI,
205 A57UnitL, A57UnitL]> {
209 def A57Write_6cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
213 def A57Write_7cyc_3L : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL]> {
217 def A57Write_8cyc_1I_1L_1V : SchedWriteRes<[A57UnitI,
223 def A57Write_8cyc_1L_2V : SchedWriteRes<[A57UnitL,
224 A57UnitV, A57UnitV]> {
228 def A57Write_8cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
232 def A57Write_9cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
238 //===----------------------------------------------------------------------===//
239 // Define Generic 4 micro-op types
241 def A57Write_2cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI,
242 A57UnitS, A57UnitS]> {
246 def A57Write_3cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI,
247 A57UnitS, A57UnitS]> {
251 def A57Write_3cyc_1I_3S : SchedWriteRes<[A57UnitI,
252 A57UnitS, A57UnitS, A57UnitS]> {
256 def A57Write_3cyc_1I_2S_1V : SchedWriteRes<[A57UnitI,
262 def A57Write_4cyc_4S : SchedWriteRes<[A57UnitS, A57UnitS,
263 A57UnitS, A57UnitS]> {
267 def A57Write_7cyc_1I_3L : SchedWriteRes<[A57UnitI,
268 A57UnitL, A57UnitL, A57UnitL]> {
272 def A57Write_5cyc_2I_2L : SchedWriteRes<[A57UnitI, A57UnitI,
273 A57UnitL, A57UnitL]> {
277 def A57Write_8cyc_1I_1L_2V : SchedWriteRes<[A57UnitI,
279 A57UnitV, A57UnitV]> {
283 def A57Write_8cyc_4L : SchedWriteRes<[A57UnitL, A57UnitL,
284 A57UnitL, A57UnitL]> {
288 def A57Write_9cyc_2L_2V : SchedWriteRes<[A57UnitL, A57UnitL,
289 A57UnitV, A57UnitV]> {
293 def A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL,
294 A57UnitV, A57UnitV, A57UnitV]> {
300 //===----------------------------------------------------------------------===//
301 // Define Generic 5 micro-op types
303 def A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
304 A57UnitV, A57UnitV]> {
308 def A57Write_8cyc_1I_4L : SchedWriteRes<[A57UnitI,
310 A57UnitL, A57UnitL]> {
314 def A57Write_4cyc_1I_4S : SchedWriteRes<[A57UnitI,
316 A57UnitS, A57UnitS]> {
320 def A57Write_9cyc_1I_2L_2V : SchedWriteRes<[A57UnitI,
322 A57UnitV, A57UnitV]> {
326 def A57Write_9cyc_1I_1L_3V : SchedWriteRes<[A57UnitI,
328 A57UnitV, A57UnitV, A57UnitV]> {
332 def A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL,
333 A57UnitV, A57UnitV, A57UnitV]> {
339 //===----------------------------------------------------------------------===//
340 // Define Generic 6 micro-op types
342 def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI,
343 A57UnitS, A57UnitS, A57UnitS,
344 A57UnitV, A57UnitV]> {
348 def A57Write_4cyc_2I_4S : SchedWriteRes<[A57UnitI, A57UnitI,
350 A57UnitS, A57UnitS]> {
354 def A57Write_4cyc_4S_2V : SchedWriteRes<[A57UnitS, A57UnitS,
356 A57UnitV, A57UnitV]> {
360 def A57Write_6cyc_6S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
361 A57UnitS, A57UnitS, A57UnitS]> {
365 def A57Write_9cyc_1I_2L_3V : SchedWriteRes<[A57UnitI,
367 A57UnitV, A57UnitV, A57UnitV]> {
371 def A57Write_9cyc_1I_1L_4V : SchedWriteRes<[A57UnitI,
374 A57UnitV, A57UnitV]> {
378 def A57Write_9cyc_2L_4V : SchedWriteRes<[A57UnitL, A57UnitL,
380 A57UnitV, A57UnitV]> {
386 //===----------------------------------------------------------------------===//
387 // Define Generic 7 micro-op types
389 def A57Write_10cyc_3L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL,
391 A57UnitV, A57UnitV]> {
395 def A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI,
398 A57UnitV, A57UnitV]> {
402 def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI,
403 A57UnitS, A57UnitS, A57UnitS,
404 A57UnitS, A57UnitS, A57UnitS]> {
408 def A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI,
411 A57UnitV, A57UnitV]> {
417 //===----------------------------------------------------------------------===//
418 // Define Generic 8 micro-op types
420 def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI,
421 A57UnitL, A57UnitL, A57UnitL,
423 A57UnitV, A57UnitV]> {
427 def A57Write_11cyc_4L_4V : SchedWriteRes<[A57UnitL, A57UnitL,
430 A57UnitV, A57UnitV]> {
434 def A57Write_8cyc_8S : SchedWriteRes<[A57UnitS, A57UnitS,
437 A57UnitS, A57UnitS]> {
443 //===----------------------------------------------------------------------===//
444 // Define Generic 9 micro-op types
446 def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI,
450 A57UnitS, A57UnitS]> {
454 def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI,
458 A57UnitV, A57UnitV]> {
464 //===----------------------------------------------------------------------===//
465 // Define Generic 10 micro-op types
467 def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
468 A57UnitS, A57UnitS, A57UnitS,
470 A57UnitV, A57UnitV]> {
472 let NumMicroOps = 10;
476 //===----------------------------------------------------------------------===//
477 // Define Generic 11 micro-op types
479 def A57Write_6cyc_1I_6S_4V : SchedWriteRes<[A57UnitI,
480 A57UnitS, A57UnitS, A57UnitS,
481 A57UnitS, A57UnitS, A57UnitS,
483 A57UnitV, A57UnitV]> {
485 let NumMicroOps = 11;
489 //===----------------------------------------------------------------------===//
490 // Define Generic 12 micro-op types
492 def A57Write_8cyc_8S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS,
493 A57UnitS, A57UnitS, A57UnitS, A57UnitS,
495 A57UnitV, A57UnitV]> {
497 let NumMicroOps = 12;
500 //===----------------------------------------------------------------------===//
501 // Define Generic 13 micro-op types
503 def A57Write_8cyc_1I_8S_4V : SchedWriteRes<[A57UnitI,
504 A57UnitS, A57UnitS, A57UnitS,
505 A57UnitS, A57UnitS, A57UnitS,
508 A57UnitV, A57UnitV]> {
510 let NumMicroOps = 13;