1 //=- AArch64ScheduleA53.td - ARM Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM Cortex A53 processors.
12 //===----------------------------------------------------------------------===//
14 // ===---------------------------------------------------------------------===//
15 // The following definitions describe the simpler per-operand machine model.
16 // This works with MachineScheduler. See MCSchedModel.h for details.
18 // Cortex-A53 machine model for scheduling and other instruction cost heuristics.
19 def CortexA53Model : SchedMachineModel {
20 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
21 let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
22 let LoadLatency = 2; // Optimistic load latency assuming bypass.
23 // This is overriden by OperandCycles if the
24 // Itineraries are queried instead.
25 let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
26 // Specification - Instruction Timings"
31 //===----------------------------------------------------------------------===//
32 // Define each kind of processor resource and number available.
34 // Modeling each pipeline as a ProcResource using the default BufferSize = -1.
35 // Cortex-A53 is in-order and therefore should be using BufferSize = 0. The
36 // current configuration performs better with the basic latencies provided so
37 // far. Will revisit BufferSize once the latency information is more accurate.
39 let SchedModel = CortexA53Model in {
41 def A53UnitALU : ProcResource<2>; // Int ALU
42 def A53UnitMAC : ProcResource<1>; // Int MAC
43 def A53UnitDiv : ProcResource<1>; // Int Division
44 def A53UnitLdSt : ProcResource<1>; // Load/Store
45 def A53UnitB : ProcResource<1>; // Branch
46 def A53UnitFPALU : ProcResource<1>; // FP ALU
47 def A53UnitFPMDS : ProcResource<1>; // FP Mult/Div/Sqrt
50 //===----------------------------------------------------------------------===//
51 // Subtarget-specific SchedWrite types which both map the ProcResources and
54 // Issue - Every instruction must consume an A53WriteIssue. Optionally,
55 // instructions that cannot be dual-issued will also include the
56 // A53WriteIssue2nd in their SchedRW list. That second WriteRes will
57 // ensure that a second issue slot is consumed.
58 def A53WriteIssue : SchedWriteRes<[]>;
59 def A53WriteIssue2nd : SchedWriteRes<[]> { let Latency = 0; }
61 // ALU - These are reduced to 1 despite a true latency of 4 in order to easily
62 // model forwarding logic. Once forwarding is properly modelled, then
63 // they'll be corrected.
64 def : WriteRes<WriteALU, [A53UnitALU]> { let Latency = 1; }
65 def : WriteRes<WriteALUs, [A53UnitALU]> { let Latency = 1; }
66 def : WriteRes<WriteCMP, [A53UnitALU]> { let Latency = 1; }
69 def : WriteRes<WriteMAC, [A53UnitMAC]> { let Latency = 4; }
72 def : WriteRes<WriteDiv, [A53UnitDiv]> { let Latency = 4; }
74 // Load - Note: Vector loads take 1-5 cycles to issue. For the WriteVecLd below,
75 // choosing the median of 3 which makes the latency 6. May model this more
76 // carefully in the future.
77 def : WriteRes<WriteLd, [A53UnitLdSt]> { let Latency = 4; }
78 def : WriteRes<WritePreLd, [A53UnitLdSt]> { let Latency = 4; }
79 def : WriteRes<WriteVecLd, [A53UnitLdSt]> { let Latency = 6; }
81 // Store - Note: Vector stores take 1-3 cycles to issue. For the ReadVecSt below,
82 // choosing the median of 2 which makes the latency 5. May model this more
83 // carefully in the future.
84 def : WriteRes<WriteSt, [A53UnitLdSt]> { let Latency = 4; }
85 def : WriteRes<WriteVecSt, [A53UnitLdSt]> { let Latency = 5; }
88 def : WriteRes<WriteBr, [A53UnitB]>;
89 def : WriteRes<WriteBrL, [A53UnitB]>;
92 def : WriteRes<WriteFPALU, [A53UnitFPALU]> {let Latency = 6; }
94 // FP MAC, Mul, Div, Sqrt
95 // Using Double Precision numbers for now as a worst case. Additionally, not
96 // modeling the exact hazard but instead treating the whole pipe as a hazard.
97 // As an example VMUL, VMLA, and others are actually pipelined. VDIV and VSQRT
98 // have a total latency of 33 and 32 respectively but only a hazard of 29 and
99 // 28 (double-prescion example).
100 def : WriteRes<WriteFPMAC, [A53UnitFPMDS]> { let Latency = 10; }
101 def : WriteRes<WriteFPMul, [A53UnitFPMDS]> { let Latency = 6; }
102 def : WriteRes<WriteFPDiv, [A53UnitFPMDS]> { let Latency = 33;
103 let ResourceCycles = [29]; }
104 def : WriteRes<WriteFPSqrt, [A53UnitFPMDS]> { let Latency = 32;
105 let ResourceCycles = [28]; }
108 //===----------------------------------------------------------------------===//
109 // Subtarget-specific SchedRead types.
111 // No forwarding defined for ReadALU yet.
112 def : ReadAdvance<ReadALU, 0>;
114 // No forwarding defined for ReadCMP yet.
115 def : ReadAdvance<ReadCMP, 0>;
117 // No forwarding defined for ReadBr yet.
118 def : ReadAdvance<ReadBr, 0>;
120 // No forwarding defined for ReadMAC yet.
121 def : ReadAdvance<ReadMAC, 0>;
123 // No forwarding defined for ReadDiv yet.
124 def : ReadAdvance<ReadDiv, 0>;
126 // No forwarding defined for ReadLd, ReadPreLd, ReadVecLd yet.
127 def : ReadAdvance<ReadLd, 0>;
128 def : ReadAdvance<ReadPreLd, 0>;
129 def : ReadAdvance<ReadVecLd, 0>;
131 // No forwarding defined for ReadSt and ReadVecSt yet.
132 def : ReadAdvance<ReadSt, 0>;
133 def : ReadAdvance<ReadVecSt, 0>;
135 // No forwarding defined for ReadFPALU yet.
136 def : ReadAdvance<ReadFPALU, 0>;
138 // No forwarding defined for ReadFPMAC/Mul/Div/Sqrt yet.
139 def : ReadAdvance<ReadFPMAC, 0>;
140 def : ReadAdvance<ReadFPMul, 0>;
141 def : ReadAdvance<ReadFPDiv, 0>;
142 def : ReadAdvance<ReadFPSqrt, 0>;