1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "AArch64GenSubtargetInfo.inc"
34 class AArch64Subtarget : public AArch64GenSubtargetInfo {
36 enum ARMProcFamilyEnum {
45 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
46 ARMProcFamilyEnum ARMProcFamily;
59 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
60 bool HasZeroCycleRegMove;
62 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
63 bool HasZeroCycleZeroing;
65 // StrictAlign - Disallow unaligned memory accesses.
68 // ReserveX18 - X18 is not available as a general purpose register.
73 /// CPUString - String name of used CPU.
74 std::string CPUString;
76 /// TargetTriple - What processor and OS we're targeting.
79 AArch64FrameLowering FrameLowering;
80 AArch64InstrInfo InstrInfo;
81 AArch64SelectionDAGInfo TSInfo;
82 AArch64TargetLowering TLInfo;
84 /// initializeSubtargetDependencies - Initializes using CPUString and the
85 /// passed in feature string so that we can use initializer lists for
86 /// subtarget initialization.
87 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS);
90 /// This constructor initializes the data members to match that
91 /// of the specified triple.
92 AArch64Subtarget(const Triple &TT, const std::string &CPU,
93 const std::string &FS, const TargetMachine &TM,
96 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
99 const AArch64FrameLowering *getFrameLowering() const override {
100 return &FrameLowering;
102 const AArch64TargetLowering *getTargetLowering() const override {
105 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
106 const AArch64RegisterInfo *getRegisterInfo() const override {
107 return &getInstrInfo()->getRegisterInfo();
109 const Triple &getTargetTriple() const { return TargetTriple; }
110 bool enableMachineScheduler() const override { return true; }
111 bool enablePostRAScheduler() const override {
112 return isGeneric() || isCortexA53() || isCortexA57();
115 bool hasV8_1aOps() const { return HasV8_1aOps; }
116 bool hasV8_2aOps() const { return HasV8_2aOps; }
118 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
120 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
122 bool requiresStrictAlign() const { return StrictAlign; }
124 bool isX18Reserved() const { return ReserveX18; }
125 bool hasFPARMv8() const { return HasFPARMv8; }
126 bool hasNEON() const { return HasNEON; }
127 bool hasCrypto() const { return HasCrypto; }
128 bool hasCRC() const { return HasCRC; }
129 /// CPU has TBI (top byte of addresses is ignored during HW address
130 /// translation) and OS enables it.
131 bool supportsAddressTopByteIgnored() const;
133 bool hasPerfMon() const { return HasPerfMon; }
134 bool hasFullFP16() const { return HasFullFP16; }
135 bool hasSPE() const { return HasSPE; }
137 bool isLittleEndian() const { return IsLittle; }
139 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
140 bool isTargetIOS() const { return TargetTriple.isiOS(); }
141 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
142 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
143 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
145 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
146 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
147 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
149 bool isGeneric() const { return CPUString == "generic"; }
150 bool isCyclone() const { return CPUString == "cyclone"; }
151 bool isCortexA57() const { return CPUString == "cortex-a57"; }
152 bool isCortexA53() const { return CPUString == "cortex-a53"; }
153 bool isExynosM1() const { return CPUString == "exynos-m1"; }
155 bool useAA() const override { return isCortexA53(); }
157 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
158 /// that still makes it profitable to inline the call.
159 unsigned getMaxInlineSizeThreshold() const { return 64; }
161 /// ParseSubtargetFeatures - Parses features string setting specified
162 /// subtarget options. Definition of function is auto generated by tblgen.
163 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
165 /// ClassifyGlobalReference - Find the target operand flags that describe
166 /// how a global value should be referenced for the current subtarget.
167 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
168 const TargetMachine &TM) const;
170 /// This function returns the name of a function which has an interface
171 /// like the non-standard bzero function, if such a function exists on
172 /// the current subtarget and it is considered prefereable over
173 /// memset with zero passed as the second argument. Otherwise it
175 const char *getBZeroEntry() const;
177 void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
179 unsigned NumRegionInstrs) const override;
181 bool enableEarlyIfConversion() const override;
183 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
185 } // End llvm namespace