1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "AArch64GenSubtargetInfo.inc"
34 class AArch64Subtarget : public AArch64GenSubtargetInfo {
36 enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
38 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
39 ARMProcFamilyEnum ARMProcFamily;
49 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
50 bool HasZeroCycleRegMove;
52 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
53 bool HasZeroCycleZeroing;
55 // StrictAlign - Disallow unaligned memory accesses.
58 // ReserveX18 - X18 is not available as a general purpose register.
63 /// CPUString - String name of used CPU.
64 std::string CPUString;
66 /// TargetTriple - What processor and OS we're targeting.
69 AArch64FrameLowering FrameLowering;
70 AArch64InstrInfo InstrInfo;
71 AArch64SelectionDAGInfo TSInfo;
72 AArch64TargetLowering TLInfo;
74 /// initializeSubtargetDependencies - Initializes using CPUString and the
75 /// passed in feature string so that we can use initializer lists for
76 /// subtarget initialization.
77 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS);
80 /// This constructor initializes the data members to match that
81 /// of the specified triple.
82 AArch64Subtarget(const Triple &TT, const std::string &CPU,
83 const std::string &FS, const TargetMachine &TM,
86 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
89 const AArch64FrameLowering *getFrameLowering() const override {
90 return &FrameLowering;
92 const AArch64TargetLowering *getTargetLowering() const override {
95 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
96 const AArch64RegisterInfo *getRegisterInfo() const override {
97 return &getInstrInfo()->getRegisterInfo();
99 const Triple &getTargetTriple() const { return TargetTriple; }
100 bool enableMachineScheduler() const override { return true; }
101 bool enablePostRAScheduler() const override {
102 return isCortexA53() || isCortexA57();
105 bool hasV8_1aOps() const { return HasV8_1aOps; }
107 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
109 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
111 bool requiresStrictAlign() const { return StrictAlign; }
113 bool isX18Reserved() const { return ReserveX18; }
114 bool hasFPARMv8() const { return HasFPARMv8; }
115 bool hasNEON() const { return HasNEON; }
116 bool hasCrypto() const { return HasCrypto; }
117 bool hasCRC() const { return HasCRC; }
118 bool hasPerfMon() const { return HasPerfMon; }
120 bool isLittleEndian() const { return IsLittle; }
122 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
123 bool isTargetIOS() const { return TargetTriple.isiOS(); }
124 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
125 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
127 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
128 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
129 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
131 bool isCyclone() const { return CPUString == "cyclone"; }
132 bool isCortexA57() const { return CPUString == "cortex-a57"; }
133 bool isCortexA53() const { return CPUString == "cortex-a53"; }
135 bool useAA() const override { return isCortexA53(); }
137 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
138 /// that still makes it profitable to inline the call.
139 unsigned getMaxInlineSizeThreshold() const { return 64; }
141 /// ParseSubtargetFeatures - Parses features string setting specified
142 /// subtarget options. Definition of function is auto generated by tblgen.
143 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
145 /// ClassifyGlobalReference - Find the target operand flags that describe
146 /// how a global value should be referenced for the current subtarget.
147 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
148 const TargetMachine &TM) const;
150 /// This function returns the name of a function which has an interface
151 /// like the non-standard bzero function, if such a function exists on
152 /// the current subtarget and it is considered prefereable over
153 /// memset with zero passed as the second argument. Otherwise it
155 const char *getBZeroEntry() const;
157 void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
159 unsigned NumRegionInstrs) const override;
161 bool enableEarlyIfConversion() const override;
163 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
165 } // End llvm namespace