1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/TargetRegistry.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Transforms/Scalar.h"
24 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
25 cl::init(true), cl::Hidden);
28 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
29 cl::init(true), cl::Hidden);
32 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
33 " integer instructions"), cl::init(false), cl::Hidden);
36 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
37 "constant pass"), cl::init(true), cl::Hidden);
40 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
41 " linker optimization hints (LOH)"), cl::init(true),
45 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
46 cl::desc("Enable the pass that removes dead"
47 " definitons and replaces stores to"
48 " them with stores to the zero"
53 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
54 " optimization pass"), cl::init(true), cl::Hidden);
56 extern "C" void LLVMInitializeAArch64Target() {
57 // Register the target.
58 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
59 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
61 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64leTarget);
62 RegisterTargetMachine<AArch64beTargetMachine> W(TheARM64beTarget);
65 /// TargetMachine ctor - Create an AArch64 architecture model.
67 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
68 StringRef CPU, StringRef FS,
69 const TargetOptions &Options,
70 Reloc::Model RM, CodeModel::Model CM,
73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
74 Subtarget(TT, CPU, FS, LittleEndian),
75 // This nested ternary is horrible, but DL needs to be properly
77 // before TLInfo is constructed.
78 DL(Subtarget.isTargetMachO()
79 ? "e-m:o-i64:64-i128:128-n32:64-S128"
80 : (LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128"
81 : "E-m:e-i64:64-i128:128-n32:64-S128")),
82 InstrInfo(Subtarget), TLInfo(*this), FrameLowering(*this, Subtarget),
87 void AArch64leTargetMachine::anchor() { }
89 AArch64leTargetMachine::
90 AArch64leTargetMachine(const Target &T, StringRef TT,
91 StringRef CPU, StringRef FS, const TargetOptions &Options,
92 Reloc::Model RM, CodeModel::Model CM,
94 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
96 void AArch64beTargetMachine::anchor() { }
98 AArch64beTargetMachine::
99 AArch64beTargetMachine(const Target &T, StringRef TT,
100 StringRef CPU, StringRef FS, const TargetOptions &Options,
101 Reloc::Model RM, CodeModel::Model CM,
102 CodeGenOpt::Level OL)
103 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
106 /// AArch64 Code Generator Pass Configuration Options.
107 class AArch64PassConfig : public TargetPassConfig {
109 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
110 : TargetPassConfig(TM, PM) {}
112 AArch64TargetMachine &getAArch64TargetMachine() const {
113 return getTM<AArch64TargetMachine>();
116 bool addPreISel() override;
117 bool addInstSelector() override;
118 bool addILPOpts() override;
119 bool addPreRegAlloc() override;
120 bool addPostRegAlloc() override;
121 bool addPreSched2() override;
122 bool addPreEmitPass() override;
126 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
127 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
128 // allows the AArch64 pass to delegate to the target independent layer when
130 PM.add(createBasicTargetTransformInfoPass(this));
131 PM.add(createAArch64TargetTransformInfoPass(this));
134 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
135 return new AArch64PassConfig(this, PM);
138 // Pass Pipeline Configuration
139 bool AArch64PassConfig::addPreISel() {
140 // Run promote constant before global merge, so that the promoted constants
141 // get a chance to be merged
142 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
143 addPass(createAArch64PromoteConstantPass());
144 if (TM->getOptLevel() != CodeGenOpt::None)
145 addPass(createGlobalMergePass(TM));
146 if (TM->getOptLevel() != CodeGenOpt::None)
147 addPass(createAArch64AddressTypePromotionPass());
149 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
151 addPass(createAtomicExpandLoadLinkedPass(TM));
156 bool AArch64PassConfig::addInstSelector() {
157 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
159 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
160 // references to _TLS_MODULE_BASE_ as possible.
161 if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
162 getOptLevel() != CodeGenOpt::None)
163 addPass(createAArch64CleanupLocalDynamicTLSPass());
168 bool AArch64PassConfig::addILPOpts() {
170 addPass(createAArch64ConditionalCompares());
171 addPass(&EarlyIfConverterID);
172 if (EnableStPairSuppress)
173 addPass(createAArch64StorePairSuppressPass());
177 bool AArch64PassConfig::addPreRegAlloc() {
178 // Use AdvSIMD scalar instructions whenever profitable.
179 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar)
180 addPass(createAArch64AdvSIMDScalar());
184 bool AArch64PassConfig::addPostRegAlloc() {
185 // Change dead register definitions to refer to the zero register.
186 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
187 addPass(createAArch64DeadRegisterDefinitions());
191 bool AArch64PassConfig::addPreSched2() {
192 // Expand some pseudo instructions to allow proper scheduling.
193 addPass(createAArch64ExpandPseudoPass());
194 // Use load/store pair instructions when possible.
195 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
196 addPass(createAArch64LoadStoreOptimizationPass());
200 bool AArch64PassConfig::addPreEmitPass() {
201 // Relax conditional branch instructions if they're otherwise out of
202 // range of their destination.
203 addPass(createAArch64BranchRelaxation());
204 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
205 TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
206 addPass(createAArch64CollectLOHPass());