1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/TargetRegistry.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Transforms/Scalar.h"
24 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
25 cl::init(true), cl::Hidden);
28 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
29 cl::init(true), cl::Hidden);
32 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
33 " integer instructions"), cl::init(false), cl::Hidden);
36 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
37 "constant pass"), cl::init(true), cl::Hidden);
40 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
41 " linker optimization hints (LOH)"), cl::init(true),
45 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
46 cl::desc("Enable the pass that removes dead"
47 " definitons and replaces stores to"
48 " them with stores to the zero"
53 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
54 " optimization pass"), cl::init(true), cl::Hidden);
57 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
58 cl::desc("Run SimplifyCFG after expanding atomic operations"
59 " to make use of cmpxchg flow-based information"),
62 extern "C" void LLVMInitializeAArch64Target() {
63 // Register the target.
64 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
65 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
66 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
69 /// TargetMachine ctor - Create an AArch64 architecture model.
71 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
72 StringRef CPU, StringRef FS,
73 const TargetOptions &Options,
74 Reloc::Model RM, CodeModel::Model CM,
77 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
78 Subtarget(TT, CPU, FS, *this, LittleEndian) {
82 void AArch64leTargetMachine::anchor() { }
84 AArch64leTargetMachine::
85 AArch64leTargetMachine(const Target &T, StringRef TT,
86 StringRef CPU, StringRef FS, const TargetOptions &Options,
87 Reloc::Model RM, CodeModel::Model CM,
89 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
91 void AArch64beTargetMachine::anchor() { }
93 AArch64beTargetMachine::
94 AArch64beTargetMachine(const Target &T, StringRef TT,
95 StringRef CPU, StringRef FS, const TargetOptions &Options,
96 Reloc::Model RM, CodeModel::Model CM,
98 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
101 /// AArch64 Code Generator Pass Configuration Options.
102 class AArch64PassConfig : public TargetPassConfig {
104 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
105 : TargetPassConfig(TM, PM) {}
107 AArch64TargetMachine &getAArch64TargetMachine() const {
108 return getTM<AArch64TargetMachine>();
111 void addIRPasses() override;
112 bool addPreISel() override;
113 bool addInstSelector() override;
114 bool addILPOpts() override;
115 bool addPreRegAlloc() override;
116 bool addPostRegAlloc() override;
117 bool addPreSched2() override;
118 bool addPreEmitPass() override;
122 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
123 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
124 // allows the AArch64 pass to delegate to the target independent layer when
126 PM.add(createBasicTargetTransformInfoPass(this));
127 PM.add(createAArch64TargetTransformInfoPass(this));
130 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
131 return new AArch64PassConfig(this, PM);
134 void AArch64PassConfig::addIRPasses() {
135 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
137 addPass(createAtomicExpandLoadLinkedPass(TM));
139 // Cmpxchg instructions are often used with a subsequent comparison to
140 // determine whether it succeeded. We can exploit existing control-flow in
141 // ldrex/strex loops to simplify this, but it needs tidying up.
142 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
143 addPass(createCFGSimplificationPass());
145 TargetPassConfig::addIRPasses();
148 // Pass Pipeline Configuration
149 bool AArch64PassConfig::addPreISel() {
150 // Run promote constant before global merge, so that the promoted constants
151 // get a chance to be merged
152 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
153 addPass(createAArch64PromoteConstantPass());
154 if (TM->getOptLevel() != CodeGenOpt::None)
155 addPass(createGlobalMergePass(TM));
156 if (TM->getOptLevel() != CodeGenOpt::None)
157 addPass(createAArch64AddressTypePromotionPass());
162 bool AArch64PassConfig::addInstSelector() {
163 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
165 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
166 // references to _TLS_MODULE_BASE_ as possible.
167 if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
168 getOptLevel() != CodeGenOpt::None)
169 addPass(createAArch64CleanupLocalDynamicTLSPass());
174 bool AArch64PassConfig::addILPOpts() {
176 addPass(createAArch64ConditionalCompares());
177 addPass(&EarlyIfConverterID);
178 if (EnableStPairSuppress)
179 addPass(createAArch64StorePairSuppressPass());
183 bool AArch64PassConfig::addPreRegAlloc() {
184 // Use AdvSIMD scalar instructions whenever profitable.
185 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar)
186 addPass(createAArch64AdvSIMDScalar());
190 bool AArch64PassConfig::addPostRegAlloc() {
191 // Change dead register definitions to refer to the zero register.
192 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
193 addPass(createAArch64DeadRegisterDefinitions());
197 bool AArch64PassConfig::addPreSched2() {
198 // Expand some pseudo instructions to allow proper scheduling.
199 addPass(createAArch64ExpandPseudoPass());
200 // Use load/store pair instructions when possible.
201 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
202 addPass(createAArch64LoadStoreOptimizationPass());
206 bool AArch64PassConfig::addPreEmitPass() {
207 // Relax conditional branch instructions if they're otherwise out of
208 // range of their destination.
209 addPass(createAArch64BranchRelaxation());
210 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
211 TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
212 addPass(createAArch64CollectLOHPass());