1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/TargetRegistry.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Transforms/Scalar.h"
24 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
25 cl::init(true), cl::Hidden);
28 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
29 cl::init(true), cl::Hidden);
32 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
33 " integer instructions"), cl::init(false), cl::Hidden);
36 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
37 "constant pass"), cl::init(true), cl::Hidden);
40 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
41 " linker optimization hints (LOH)"), cl::init(true),
45 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
46 cl::desc("Enable the pass that removes dead"
47 " definitons and replaces stores to"
48 " them with stores to the zero"
53 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
54 " optimization pass"), cl::init(true), cl::Hidden);
57 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
58 cl::desc("Run SimplifyCFG after expanding atomic operations"
59 " to make use of cmpxchg flow-based information"),
63 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
64 cl::desc("Run early if-conversion"),
68 extern "C" void LLVMInitializeAArch64Target() {
69 // Register the target.
70 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
71 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
72 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
75 /// TargetMachine ctor - Create an AArch64 architecture model.
77 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
78 StringRef CPU, StringRef FS,
79 const TargetOptions &Options,
80 Reloc::Model RM, CodeModel::Model CM,
83 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
84 Subtarget(TT, CPU, FS, *this, LittleEndian) {
88 void AArch64leTargetMachine::anchor() { }
90 AArch64leTargetMachine::
91 AArch64leTargetMachine(const Target &T, StringRef TT,
92 StringRef CPU, StringRef FS, const TargetOptions &Options,
93 Reloc::Model RM, CodeModel::Model CM,
95 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
97 void AArch64beTargetMachine::anchor() { }
99 AArch64beTargetMachine::
100 AArch64beTargetMachine(const Target &T, StringRef TT,
101 StringRef CPU, StringRef FS, const TargetOptions &Options,
102 Reloc::Model RM, CodeModel::Model CM,
103 CodeGenOpt::Level OL)
104 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
107 /// AArch64 Code Generator Pass Configuration Options.
108 class AArch64PassConfig : public TargetPassConfig {
110 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
111 : TargetPassConfig(TM, PM) {}
113 AArch64TargetMachine &getAArch64TargetMachine() const {
114 return getTM<AArch64TargetMachine>();
117 void addIRPasses() override;
118 bool addPreISel() override;
119 bool addInstSelector() override;
120 bool addILPOpts() override;
121 bool addPreRegAlloc() override;
122 bool addPostRegAlloc() override;
123 bool addPreSched2() override;
124 bool addPreEmitPass() override;
128 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
129 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
130 // allows the AArch64 pass to delegate to the target independent layer when
132 PM.add(createBasicTargetTransformInfoPass(this));
133 PM.add(createAArch64TargetTransformInfoPass(this));
136 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
137 return new AArch64PassConfig(this, PM);
140 void AArch64PassConfig::addIRPasses() {
141 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
143 addPass(createAtomicExpandLoadLinkedPass(TM));
145 // Cmpxchg instructions are often used with a subsequent comparison to
146 // determine whether it succeeded. We can exploit existing control-flow in
147 // ldrex/strex loops to simplify this, but it needs tidying up.
148 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
149 addPass(createCFGSimplificationPass());
151 TargetPassConfig::addIRPasses();
154 // Pass Pipeline Configuration
155 bool AArch64PassConfig::addPreISel() {
156 // Run promote constant before global merge, so that the promoted constants
157 // get a chance to be merged
158 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
159 addPass(createAArch64PromoteConstantPass());
160 if (TM->getOptLevel() != CodeGenOpt::None)
161 addPass(createGlobalMergePass(TM));
162 if (TM->getOptLevel() != CodeGenOpt::None)
163 addPass(createAArch64AddressTypePromotionPass());
168 bool AArch64PassConfig::addInstSelector() {
169 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
171 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
172 // references to _TLS_MODULE_BASE_ as possible.
173 if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
174 getOptLevel() != CodeGenOpt::None)
175 addPass(createAArch64CleanupLocalDynamicTLSPass());
180 bool AArch64PassConfig::addILPOpts() {
182 addPass(createAArch64ConditionalCompares());
183 if (EnableEarlyIfConversion)
184 addPass(&EarlyIfConverterID);
185 if (EnableStPairSuppress)
186 addPass(createAArch64StorePairSuppressPass());
190 bool AArch64PassConfig::addPreRegAlloc() {
191 // Use AdvSIMD scalar instructions whenever profitable.
192 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar)
193 addPass(createAArch64AdvSIMDScalar());
197 bool AArch64PassConfig::addPostRegAlloc() {
198 // Change dead register definitions to refer to the zero register.
199 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
200 addPass(createAArch64DeadRegisterDefinitions());
204 bool AArch64PassConfig::addPreSched2() {
205 // Expand some pseudo instructions to allow proper scheduling.
206 addPass(createAArch64ExpandPseudoPass());
207 // Use load/store pair instructions when possible.
208 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
209 addPass(createAArch64LoadStoreOptimizationPass());
213 bool AArch64PassConfig::addPreEmitPass() {
214 // Relax conditional branch instructions if they're otherwise out of
215 // range of their destination.
216 addPass(createAArch64BranchRelaxation());
217 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
218 TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
219 addPass(createAArch64CollectLOHPass());