1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "AArch64TargetObjectFile.h"
16 #include "AArch64TargetTransformInfo.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/RegAllocRegistry.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/PassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Transforms/Scalar.h"
28 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
29 cl::init(true), cl::Hidden);
31 static cl::opt<bool> EnableMCR("aarch64-mcr",
32 cl::desc("Enable the machine combiner pass"),
33 cl::init(true), cl::Hidden);
36 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
37 cl::init(true), cl::Hidden);
40 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
41 " integer instructions"), cl::init(false), cl::Hidden);
44 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
45 "constant pass"), cl::init(true), cl::Hidden);
48 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
49 " linker optimization hints (LOH)"), cl::init(true),
53 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
54 cl::desc("Enable the pass that removes dead"
55 " definitons and replaces stores to"
56 " them with stores to the zero"
61 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
62 " optimization pass"), cl::init(true), cl::Hidden);
65 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
66 cl::desc("Run SimplifyCFG after expanding atomic operations"
67 " to make use of cmpxchg flow-based information"),
71 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
72 cl::desc("Run early if-conversion"),
76 EnableCondOpt("aarch64-condopt",
77 cl::desc("Enable the condition optimizer pass"),
78 cl::init(true), cl::Hidden);
81 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
82 cl::desc("Work around Cortex-A53 erratum 835769"),
86 EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
87 cl::desc("Enable optimizations on complex GEPs"),
90 extern "C" void LLVMInitializeAArch64Target() {
91 // Register the target.
92 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
93 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
94 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
97 //===----------------------------------------------------------------------===//
98 // AArch64 Lowering public interface.
99 //===----------------------------------------------------------------------===//
100 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
101 if (TT.isOSBinFormatMachO())
102 return make_unique<AArch64_MachoTargetObjectFile>();
104 return make_unique<AArch64_ELFTargetObjectFile>();
107 /// TargetMachine ctor - Create an AArch64 architecture model.
109 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
110 StringRef CPU, StringRef FS,
111 const TargetOptions &Options,
112 Reloc::Model RM, CodeModel::Model CM,
113 CodeGenOpt::Level OL,
115 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
116 // This nested ternary is horrible, but DL needs to be properly
118 // before TLInfo is constructed.
119 DL(Triple(TT).isOSBinFormatMachO()
120 ? "e-m:o-i64:64-i128:128-n32:64-S128"
121 : (LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128"
122 : "E-m:e-i64:64-i128:128-n32:64-S128")),
123 TLOF(createTLOF(Triple(getTargetTriple()))),
124 Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) {
128 AArch64TargetMachine::~AArch64TargetMachine() {}
130 const AArch64Subtarget *
131 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
132 AttributeSet FnAttrs = F.getAttributes();
134 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
136 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
138 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
139 ? CPUAttr.getValueAsString().str()
141 std::string FS = !FSAttr.hasAttribute(Attribute::None)
142 ? FSAttr.getValueAsString().str()
145 auto &I = SubtargetMap[CPU + FS];
147 // This needs to be done before we create a new subtarget since any
148 // creation will depend on the TM and the code generation flags on the
149 // function that reside in TargetOptions.
150 resetTargetOptions(F);
151 I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);
156 void AArch64leTargetMachine::anchor() { }
158 AArch64leTargetMachine::
159 AArch64leTargetMachine(const Target &T, StringRef TT,
160 StringRef CPU, StringRef FS, const TargetOptions &Options,
161 Reloc::Model RM, CodeModel::Model CM,
162 CodeGenOpt::Level OL)
163 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
165 void AArch64beTargetMachine::anchor() { }
167 AArch64beTargetMachine::
168 AArch64beTargetMachine(const Target &T, StringRef TT,
169 StringRef CPU, StringRef FS, const TargetOptions &Options,
170 Reloc::Model RM, CodeModel::Model CM,
171 CodeGenOpt::Level OL)
172 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
175 /// AArch64 Code Generator Pass Configuration Options.
176 class AArch64PassConfig : public TargetPassConfig {
178 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
179 : TargetPassConfig(TM, PM) {
180 if (TM->getOptLevel() != CodeGenOpt::None)
181 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
184 AArch64TargetMachine &getAArch64TargetMachine() const {
185 return getTM<AArch64TargetMachine>();
188 void addIRPasses() override;
189 bool addPreISel() override;
190 bool addInstSelector() override;
191 bool addILPOpts() override;
192 void addPreRegAlloc() override;
193 void addPostRegAlloc() override;
194 void addPreSched2() override;
195 void addPreEmitPass() override;
199 TargetIRAnalysis AArch64TargetMachine::getTargetIRAnalysis() {
200 return TargetIRAnalysis([this](Function &F) {
201 return TargetTransformInfo(AArch64TTIImpl(this, F));
205 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
206 return new AArch64PassConfig(this, PM);
209 void AArch64PassConfig::addIRPasses() {
210 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
212 addPass(createAtomicExpandPass(TM));
214 // Cmpxchg instructions are often used with a subsequent comparison to
215 // determine whether it succeeded. We can exploit existing control-flow in
216 // ldrex/strex loops to simplify this, but it needs tidying up.
217 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
218 addPass(createCFGSimplificationPass());
220 TargetPassConfig::addIRPasses();
222 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
223 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
224 // and lower a GEP with multiple indices to either arithmetic operations or
225 // multiple GEPs with single index.
226 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
227 // Call EarlyCSE pass to find and remove subexpressions in the lowered
229 addPass(createEarlyCSEPass());
230 // Do loop invariant code motion in case part of the lowered result is
232 addPass(createLICMPass());
236 // Pass Pipeline Configuration
237 bool AArch64PassConfig::addPreISel() {
238 // Run promote constant before global merge, so that the promoted constants
239 // get a chance to be merged
240 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
241 addPass(createAArch64PromoteConstantPass());
242 if (TM->getOptLevel() != CodeGenOpt::None)
243 addPass(createGlobalMergePass(TM));
244 if (TM->getOptLevel() != CodeGenOpt::None)
245 addPass(createAArch64AddressTypePromotionPass());
250 bool AArch64PassConfig::addInstSelector() {
251 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
253 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
254 // references to _TLS_MODULE_BASE_ as possible.
255 if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
256 getOptLevel() != CodeGenOpt::None)
257 addPass(createAArch64CleanupLocalDynamicTLSPass());
262 bool AArch64PassConfig::addILPOpts() {
264 addPass(createAArch64ConditionOptimizerPass());
266 addPass(createAArch64ConditionalCompares());
268 addPass(&MachineCombinerID);
269 if (EnableEarlyIfConversion)
270 addPass(&EarlyIfConverterID);
271 if (EnableStPairSuppress)
272 addPass(createAArch64StorePairSuppressPass());
276 void AArch64PassConfig::addPreRegAlloc() {
277 // Use AdvSIMD scalar instructions whenever profitable.
278 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
279 addPass(createAArch64AdvSIMDScalar());
280 // The AdvSIMD pass may produce copies that can be rewritten to
281 // be register coaleascer friendly.
282 addPass(&PeepholeOptimizerID);
286 void AArch64PassConfig::addPostRegAlloc() {
287 // Change dead register definitions to refer to the zero register.
288 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
289 addPass(createAArch64DeadRegisterDefinitions());
290 if (TM->getOptLevel() != CodeGenOpt::None &&
291 (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
292 TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
293 usingDefaultRegAlloc())
294 // Improve performance for some FP/SIMD code for A57.
295 addPass(createAArch64A57FPLoadBalancing());
298 void AArch64PassConfig::addPreSched2() {
299 // Expand some pseudo instructions to allow proper scheduling.
300 addPass(createAArch64ExpandPseudoPass());
301 // Use load/store pair instructions when possible.
302 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
303 addPass(createAArch64LoadStoreOptimizationPass());
306 void AArch64PassConfig::addPreEmitPass() {
307 if (EnableA53Fix835769)
308 addPass(createAArch64A53Fix835769());
309 // Relax conditional branch instructions if they're otherwise out of
310 // range of their destination.
311 addPass(createAArch64BranchRelaxation());
312 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
313 Triple(TM->getTargetTriple()).isOSBinFormatMachO())
314 addPass(createAArch64CollectLOHPass());