1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/TargetRegistry.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Transforms/Scalar.h"
24 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
25 cl::init(true), cl::Hidden);
27 static cl::opt<bool> EnableMCR("aarch64-mcr",
28 cl::desc("Enable the machine combiner pass"),
29 cl::init(true), cl::Hidden);
32 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
33 cl::init(true), cl::Hidden);
36 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
37 " integer instructions"), cl::init(false), cl::Hidden);
40 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
41 "constant pass"), cl::init(true), cl::Hidden);
44 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
45 " linker optimization hints (LOH)"), cl::init(true),
49 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
50 cl::desc("Enable the pass that removes dead"
51 " definitons and replaces stores to"
52 " them with stores to the zero"
57 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
58 " optimization pass"), cl::init(true), cl::Hidden);
61 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
62 cl::desc("Run SimplifyCFG after expanding atomic operations"
63 " to make use of cmpxchg flow-based information"),
67 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
68 cl::desc("Run early if-conversion"),
72 extern "C" void LLVMInitializeAArch64Target() {
73 // Register the target.
74 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
75 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
76 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
79 /// TargetMachine ctor - Create an AArch64 architecture model.
81 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
82 StringRef CPU, StringRef FS,
83 const TargetOptions &Options,
84 Reloc::Model RM, CodeModel::Model CM,
87 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
88 Subtarget(TT, CPU, FS, *this, LittleEndian) {
92 void AArch64leTargetMachine::anchor() { }
94 AArch64leTargetMachine::
95 AArch64leTargetMachine(const Target &T, StringRef TT,
96 StringRef CPU, StringRef FS, const TargetOptions &Options,
97 Reloc::Model RM, CodeModel::Model CM,
99 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
101 void AArch64beTargetMachine::anchor() { }
103 AArch64beTargetMachine::
104 AArch64beTargetMachine(const Target &T, StringRef TT,
105 StringRef CPU, StringRef FS, const TargetOptions &Options,
106 Reloc::Model RM, CodeModel::Model CM,
107 CodeGenOpt::Level OL)
108 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
111 /// AArch64 Code Generator Pass Configuration Options.
112 class AArch64PassConfig : public TargetPassConfig {
114 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
115 : TargetPassConfig(TM, PM) {}
117 AArch64TargetMachine &getAArch64TargetMachine() const {
118 return getTM<AArch64TargetMachine>();
121 void addIRPasses() override;
122 bool addPreISel() override;
123 bool addInstSelector() override;
124 bool addILPOpts() override;
125 bool addPreRegAlloc() override;
126 bool addPostRegAlloc() override;
127 bool addPreSched2() override;
128 bool addPreEmitPass() override;
132 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
133 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
134 // allows the AArch64 pass to delegate to the target independent layer when
136 PM.add(createBasicTargetTransformInfoPass(this));
137 PM.add(createAArch64TargetTransformInfoPass(this));
140 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
141 return new AArch64PassConfig(this, PM);
144 void AArch64PassConfig::addIRPasses() {
145 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
147 addPass(createAtomicExpandPass(TM));
149 // Cmpxchg instructions are often used with a subsequent comparison to
150 // determine whether it succeeded. We can exploit existing control-flow in
151 // ldrex/strex loops to simplify this, but it needs tidying up.
152 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
153 addPass(createCFGSimplificationPass());
155 TargetPassConfig::addIRPasses();
158 // Pass Pipeline Configuration
159 bool AArch64PassConfig::addPreISel() {
160 // Run promote constant before global merge, so that the promoted constants
161 // get a chance to be merged
162 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
163 addPass(createAArch64PromoteConstantPass());
164 if (TM->getOptLevel() != CodeGenOpt::None)
165 addPass(createGlobalMergePass(TM));
166 if (TM->getOptLevel() != CodeGenOpt::None)
167 addPass(createAArch64AddressTypePromotionPass());
172 bool AArch64PassConfig::addInstSelector() {
173 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
175 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
176 // references to _TLS_MODULE_BASE_ as possible.
177 if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
178 getOptLevel() != CodeGenOpt::None)
179 addPass(createAArch64CleanupLocalDynamicTLSPass());
184 bool AArch64PassConfig::addILPOpts() {
186 addPass(createAArch64ConditionalCompares());
188 addPass(&MachineCombinerID);
189 if (EnableEarlyIfConversion)
190 addPass(&EarlyIfConverterID);
191 if (EnableStPairSuppress)
192 addPass(createAArch64StorePairSuppressPass());
196 bool AArch64PassConfig::addPreRegAlloc() {
197 // Use AdvSIMD scalar instructions whenever profitable.
198 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
199 addPass(createAArch64AdvSIMDScalar());
200 // The AdvSIMD pass may produce copies that can be rewritten to
201 // be register coaleascer friendly.
202 addPass(&PeepholeOptimizerID);
207 bool AArch64PassConfig::addPostRegAlloc() {
208 // Change dead register definitions to refer to the zero register.
209 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
210 addPass(createAArch64DeadRegisterDefinitions());
211 if (TM->getOptLevel() != CodeGenOpt::None &&
212 TM->getSubtarget<AArch64Subtarget>().isCortexA57())
213 // Improve performance for some FP/SIMD code for A57.
214 addPass(createAArch64A57FPLoadBalancing());
218 bool AArch64PassConfig::addPreSched2() {
219 // Expand some pseudo instructions to allow proper scheduling.
220 addPass(createAArch64ExpandPseudoPass());
221 // Use load/store pair instructions when possible.
222 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
223 addPass(createAArch64LoadStoreOptimizationPass());
227 bool AArch64PassConfig::addPreEmitPass() {
228 // Relax conditional branch instructions if they're otherwise out of
229 // range of their destination.
230 addPass(createAArch64BranchRelaxation());
231 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
232 TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
233 addPass(createAArch64CollectLOHPass());